Index: common/a8core/synchronizer.vhdl
===================================================================
--- common/a8core/synchronizer.vhdl	(nonexistent)
+++ common/a8core/synchronizer.vhdl	(revision 1)
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END synchronizer;
+
+ARCHITECTURE vhdl OF synchronizer IS
+	signal ff_next : std_logic_vector(2 downto 0);
+	signal ff_reg : std_logic_vector(2 downto 0);
+begin
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then						
+			ff_reg <= ff_next;	
+		end if;
+	end process;
+	
+	ff_next <= RAW&ff_reg(2 downto 1);
+	
+	SYNC <= ff_reg(0);
+
+end vhdl;
+
+
Index: common/components/hq_dac.v
===================================================================
--- common/components/hq_dac.v	(nonexistent)
+++ common/components/hq_dac.v	(revision 1)
@@ -0,0 +1,100 @@
+`timescale 1ns / 1ps
+
+// This module is a third order delta/sigma modulator
+// It uses no multiply only shifts by 1, 2 or 13
+// There are only 7 adders used, it takes around 110 LUTs
+module hq_dac
+(
+  input         reset,
+  input         clk,
+  input         clk_ena,
+  input  [19:0] pcm_in,
+  output reg    dac_out
+);
+
+// ======================================
+// ============== Stage #1 ==============
+// ======================================
+wire [23:0] w_data_in_p0;
+wire [23:0] w_data_err_p0;
+wire [23:0] w_data_int_p0;
+reg  [23:0] r_data_fwd_p1;
+
+// PCM input extended to 24 bits
+assign w_data_in_p0  = { {4{pcm_in[19]}}, pcm_in };
+
+// Error between the input and the quantizer output
+assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
+
+// First integrator adder
+assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+                     + r_data_fwd_p1;
+
+// First integrator forward delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_fwd_p1 <= 24'd0;
+  else if (clk_ena)
+    r_data_fwd_p1 <= w_data_int_p0;
+
+// ======================================
+// ============== Stage #2 ==============
+// ======================================
+wire [23:0] w_data_fb1_p1;
+wire [23:0] w_data_fb2_p1;
+wire [23:0] w_data_lpf_p1;
+reg  [23:0] r_data_lpf_p2;
+
+// Feedback from the quantizer output
+assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
+                     - { {3{w_data_qt_p2[23]}},  w_data_qt_p2[22:2] }; // Divide by 4
+
+// Feedback from the third stage
+assign w_data_fb2_p1 = w_data_fb1_p1
+                     - { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
+
+// Low pass filter
+assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
+
+// Low pass filter feedback delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_lpf_p2 <= 24'd0;
+  else if (clk_ena)
+    r_data_lpf_p2 <= w_data_lpf_p1;
+
+// ======================================
+// ============== Stage #3 ==============
+// ======================================
+wire [23:0] w_data_fb3_p1;
+wire [23:0] w_data_int_p1;
+reg  [23:0] r_data_fwd_p2;
+
+// Feedback from the quantizer output
+assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
+                     - { {2{w_data_qt_p2[23]}},  w_data_qt_p2[22:1] }; // Divide by 2
+
+// Second integrator adder
+assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
+
+// Second integrator forward delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_fwd_p2 <= 24'd0;
+  else if (clk_ena)
+    r_data_fwd_p2 <= w_data_int_p1;
+
+// =====================================
+// ========== 1-bit quantizer ==========
+// =====================================
+wire [23:0] w_data_qt_p2;
+
+assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
+
+always @(posedge reset or posedge clk)
+  if (reset)
+    dac_out <= 1'b0;
+  else if (clk_ena)
+    dac_out <= ~r_data_fwd_p2[23];
+
+endmodule
Index: common/a8core/pokey_keyboard_scanner.vhdl
===================================================================
--- common/a8core/pokey_keyboard_scanner.vhdl	(nonexistent)
+++ common/a8core/pokey_keyboard_scanner.vhdl	(revision 1)
@@ -0,0 +1,182 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pokey_keyboard_scanner is
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	enable : in std_logic; -- typically hsync or equiv timing
+	keyboard_response : in std_logic_vector(1 downto 0);
+	debounce_disable : in std_logic;
+	scan_enable : in std_logic;
+	
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	
+	shift_pressed : out std_logic;
+	control_pressed : out std_logic;
+	break_pressed : out std_logic;
+	key_held : out std_logic;
+	keycode : out std_logic_vector(5 downto 0);
+	other_key_irq : out std_logic
+);
+end pokey_keyboard_scanner;
+
+architecture vhdl of pokey_keyboard_scanner is
+	signal bincnt_next : std_logic_vector(5 downto 0);
+	signal bincnt_reg : std_logic_vector(5 downto 0);
+
+	signal break_pressed_next : std_logic;
+	signal break_pressed_reg : std_logic;
+
+	signal shift_pressed_next : std_logic;
+	signal shift_pressed_reg : std_logic;
+	
+	signal control_pressed_next : std_logic;
+	signal control_pressed_reg : std_logic;	
+	
+	signal compare_latch_next : std_logic_vector(5 downto 0);
+	signal compare_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal keycode_latch_next : std_logic_vector(5 downto 0);
+	signal keycode_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal irq_next : std_logic;
+	signal irq_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal my_key : std_logic;
+	
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_wait_key : std_logic_vector(1 downto 0) := "00";
+	constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
+	constant state_valid_key : std_logic_vector(1 downto 0) := "10";
+	constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
+begin
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			bincnt_reg <= (others=>'0');
+			break_pressed_reg <= '0';
+			shift_pressed_reg <= '0';
+			control_pressed_reg <= '0';
+			compare_latch_reg <= (others=>'0');
+			keycode_latch_reg <= (others=>'1');
+			key_held_reg <= '0';
+			state_reg <= state_wait_key;
+			irq_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			bincnt_reg <= bincnt_next;
+			state_reg <= state_next;
+			break_pressed_reg <= break_pressed_next;
+			shift_pressed_reg <= shift_pressed_next;
+			control_pressed_reg <= control_pressed_next;
+			compare_latch_reg <= compare_latch_next;
+			keycode_latch_reg <= keycode_latch_next;
+			key_held_reg <= key_held_next;
+			state_reg <= state_next;
+			irq_reg <= irq_next;
+		end if;
+	end process;
+
+	process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_reg, shift_pressed_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
+	begin
+		bincnt_next <= bincnt_reg;
+		state_next <= state_reg;
+		compare_latch_next <= compare_latch_reg;
+		irq_next <= '0';
+		break_pressed_next <= break_pressed_reg;
+		shift_pressed_next <= shift_pressed_reg;
+		control_pressed_next <= control_pressed_reg;
+		keycode_latch_next <= keycode_latch_reg;
+		key_held_next <= key_held_reg;
+		
+		my_key <= '0';
+		if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
+			my_key <= '1';
+		end if;
+		
+		if (enable = '1' and scan_enable='1') then			
+			bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
+		
+			key_held_next<= '0';
+		
+			case state_reg is
+			when state_wait_key =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					state_next <= state_key_bounce;
+					compare_latch_next <= bincnt_reg;
+				end if;
+				
+			when state_key_bounce =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					if (my_key = '1') then -- same key
+						keycode_latch_next <= compare_latch_reg;
+						irq_next <= '1';
+						key_held_next<= '1';
+						state_next <= state_valid_key;
+					else -- different key (multiple keys pressed)
+						state_next <= state_wait_key;
+					end if;
+				else -- key not pressed
+					if (my_key = '1') then -- same key, no longer pressed
+						state_next <= state_wait_key;
+					end if;
+				end if;
+			
+			when state_valid_key =>
+				key_held_next<= '1';
+				if (my_key = '1') then -- only response to my key
+					if (keyboard_response(0) = '1') then -- no longer pressed
+						state_next <= state_key_debounce;
+					end if;					
+				end if;
+				
+			when state_key_debounce =>
+				if (my_key = '1') then
+					state_next <= state_wait_key;
+				end if;
+
+			when others=> 
+				state_next <= state_wait_key; 
+			end case;
+
+			if (bincnt_reg(3 downto 0)  = "0000") then
+				case bincnt_reg(5 downto 4) is
+				when "11" =>
+					break_pressed_next <= not(keyboard_response(1)); --0x30
+				when "01" =>
+					shift_pressed_next <= not(keyboard_response(1)); --0x10
+				when "00" =>
+					control_pressed_next <= not(keyboard_response(1)); -- 0x00
+				when others =>
+					--
+				end case;
+			end if;
+		end if;
+	end process;
+	
+	-- outputs
+	keyboard_scan <= not(bincnt_reg);
+	
+	key_held <= key_held_reg;	
+	keycode <= keycode_latch_reg;
+	break_pressed <= break_pressed_reg;
+	shift_pressed <= shift_pressed_reg;
+	control_pressed <= control_pressed_reg;
+	other_key_irq <= irq_reg;
+end vhdl;
Index: common/a8core/pokey_noise_filter.vhdl
===================================================================
--- common/a8core/pokey_noise_filter.vhdl	(nonexistent)
+++ common/a8core/pokey_noise_filter.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY pokey_noise_filter IS
+PORT 
+( 
+	NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+		
+	PULSE_IN : IN STD_LOGIC;
+
+	NOISE_4 : IN STD_LOGIC;
+	NOISE_5 : IN STD_LOGIC;
+	NOISE_LARGE : IN STD_LOGIC;
+	
+	PULSE_OUT : OUT STD_LOGIC
+);
+END pokey_noise_filter;
+
+ARCHITECTURE vhdl OF pokey_noise_filter IS
+	signal pulse_noise_a : std_logic;
+	signal pulse_noise_b : std_logic;
+BEGIN
+	process(pulse_in, noise_4, noise_5, noise_large, pulse_noise_a, pulse_noise_b, noise_select)
+	begin
+		pulse_noise_a <= noise_large;
+		pulse_noise_b <= noise_5 and pulse_in;
+	
+		if (NOISE_SELECT(1) = '1') then
+			pulse_noise_a <= noise_4;
+		end if;
+	
+		if (NOISE_SELECT(2) = '1') then
+			pulse_noise_b <= pulse_in;
+		end if;
+		
+		PULSE_OUT <= pulse_noise_a and pulse_noise_b;
+
+		if (NOISE_SELECT(0) = '1') then
+			PULSE_OUT <= pulse_noise_b;
+		end if;		
+	end process;
+end vhdl;
\ No newline at end of file
Index: common/a8core/poly_4.vhdl
===================================================================
--- common/a8core/poly_4.vhdl	(nonexistent)
+++ common/a8core/poly_4.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_4 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;	
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_4;
+
+ARCHITECTURE vhdl OF poly_4 IS
+	signal shift_reg: std_logic_vector(3 downto 0);
+	signal shift_next: std_logic_vector(3 downto 0);
+BEGIN
+	-- register
+	process(clk, reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "1010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: common/a8core/reg_file.vhdl
===================================================================
--- common/a8core/reg_file.vhdl	(nonexistent)
+++ common/a8core/reg_file.vhdl	(revision 1)
@@ -0,0 +1,85 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END reg_file;
+
+ARCHITECTURE vhdl OF reg_file IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+
+	type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
+
+	signal digit_next : reg_file_type;
+	signal digit_reg : reg_file_type;
+	
+	signal addr_decoded : std_logic_vector(2**width-1 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => WIDTH)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(digit_reg,addr_decoded,data_in,WR_EN)
+	begin
+		digit_next <= digit_reg;
+		
+		if (WR_EN = '1') then		
+			comp_gen:
+			for i in 0 to (BYTES-1) loop
+				if (addr_decoded(i) = '1') then				
+					digit_next(i) <= data_in;
+				end if;
+			end loop;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	-- output
+	process(addr_decoded,digit_reg)
+	begin
+		data_out <= X"FF";
+		comp_gen:
+		for i in 0 to (BYTES-1) loop
+			if (addr_decoded(i) = '1') then				
+				data_out <= digit_reg(i);
+			end if;
+		end loop;	
+	end process;
+		
+END vhdl;
\ No newline at end of file
Index: common/a8core/simple_counter.vhdl
===================================================================
--- common/a8core/simple_counter.vhdl	(nonexistent)
+++ common/a8core/simple_counter.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY simple_counter IS
+generic
+(
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+);
+END simple_counter;
+
+ARCHITECTURE vhdl OF simple_counter IS
+	signal value_next : std_logic_vector(COUNT_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(COUNT_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: common/a8core/wide_delay_line.vhdl
===================================================================
--- common/a8core/wide_delay_line.vhdl	(nonexistent)
+++ common/a8core/wide_delay_line.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY wide_delay_line IS
+generic(COUNT : natural := 1; WIDTH : natural :=1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+);
+END wide_delay_line;
+
+ARCHITECTURE vhdl OF wide_delay_line IS
+	type shift_reg_type is array(COUNT-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
+	signal shift_reg : shift_reg_type;
+	signal shift_next : shift_reg_type;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>(others=>'0'));
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>(others=>'0'));
+		end if;		
+	end process;
+	
+	-- output
+	gen_output:
+	for index in 0 to WIDTH-1 generate
+		data_out(index) <= shift_reg(0)(index);
+	end generate;
+		
+END vhdl;
Index: common/components/scandouble_ram_infer.vhdl
===================================================================
--- common/components/scandouble_ram_infer.vhdl	(nonexistent)
+++ common/components/scandouble_ram_infer.vhdl	(revision 1)
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+END scandouble_ram_infer;
+
+ARCHITECTURE rtl OF scandouble_ram_infer IS
+   TYPE mem IS ARRAY(0 TO 1824) OF std_logic_vector(7 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(address) <= data;
+         END IF;
+         q <= ram_block(address);
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: common/romgen/ATARIBAS.ROM
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/romgen/ATARIBAS.ROM
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/romgen/HelloTinyROM.dis
===================================================================
--- common/romgen/HelloTinyROM.dis	(nonexistent)
+++ common/romgen/HelloTinyROM.dis	(revision 1)
@@ -0,0 +1,5937 @@
+
+HelloTinyROM.elf:     file format elf32-zpu
+
+Disassembly of section .fixed_vectors:
+
+00000000 <_start>:
+   0:	0b          	nop
+   1:	0b          	nop
+   2:	0b          	nop
+   3:	89          	im 9
+   4:	ab          	im 43
+   5:	04          	poppc
+   6:	0b          	nop
+   7:	0b          	nop
+   8:	0b          	nop
+   9:	0b          	nop
+   a:	0b          	nop
+   b:	0b          	nop
+   c:	0b          	nop
+   d:	0b          	nop
+   e:	0b          	nop
+   f:	0b          	nop
+  10:	0b          	nop
+  11:	0b          	nop
+  12:	0b          	nop
+  13:	0b          	nop
+  14:	0b          	nop
+  15:	0b          	nop
+  16:	0b          	nop
+  17:	0b          	nop
+  18:	0b          	nop
+  19:	0b          	nop
+  1a:	0b          	nop
+  1b:	0b          	nop
+  1c:	0b          	nop
+  1d:	0b          	nop
+  1e:	0b          	nop
+  1f:	0b          	nop
+  20:	0b          	nop
+  21:	0b          	nop
+  22:	0b          	nop
+  23:	0b          	nop
+	...
+
+00000040 <_loadh>:
+  40:	71          	loadsp 4
+  41:	fd          	im -3
+  42:	06          	and
+  43:	08          	load
+  44:	72          	loadsp 8
+  45:	83          	im 3
+  46:	06          	and
+  47:	09          	not
+  48:	81          	im 1
+  49:	05          	add
+  4a:	82          	im 2
+  4b:	05          	add
+  4c:	83          	im 3
+  4d:	2b          	ashiftleft
+  4e:	2a          	lshiftright
+  4f:	83          	im 3
+  50:	ff          	im -1
+  51:	ff          	im -1
+  52:	06          	and
+  53:	52          	storesp 8
+  54:	04          	poppc
+	...
+
+00000060 <_storeh>:
+  60:	71          	loadsp 4
+  61:	fd          	im -3
+  62:	06          	and
+  63:	08          	load
+  64:	83          	im 3
+  65:	ff          	im -1
+  66:	ff          	im -1
+  67:	73          	loadsp 12
+  68:	83          	im 3
+  69:	06          	and
+  6a:	09          	not
+  6b:	81          	im 1
+  6c:	05          	add
+  6d:	82          	im 2
+  6e:	05          	add
+  6f:	83          	im 3
+  70:	2b          	ashiftleft
+  71:	2b          	ashiftleft
+  72:	09          	not
+  73:	06          	and
+  74:	73          	loadsp 12
+  75:	83          	im 3
+  76:	ff          	im -1
+  77:	ff          	im -1
+  78:	0b          	nop
+  79:	0b          	nop
+  7a:	0b          	nop
+  7b:	0b          	nop
+  7c:	83          	im 3
+  7d:	a7          	im 39
+  7e:	04          	poppc
+	...
+
+00000080 <_lessthan>:
+  80:	72          	loadsp 8
+  81:	09          	not
+  82:	81          	im 1
+  83:	05          	add
+  84:	72          	loadsp 8
+  85:	05          	add
+  86:	73          	loadsp 12
+  87:	73          	loadsp 12
+  88:	09          	not
+  89:	06          	and
+  8a:	09          	not
+  8b:	06          	and
+  8c:	73          	loadsp 12
+  8d:	09          	not
+  8e:	73          	loadsp 12
+  8f:	06          	and
+  90:	07          	or
+  91:	0a          	flip
+  92:	81          	im 1
+  93:	06          	and
+  94:	53          	storesp 12
+  95:	51          	storesp 4
+  96:	04          	poppc
+	...
+
+000000a0 <_lessthanorequal>:
+  a0:	72          	loadsp 8
+  a1:	72          	loadsp 8
+  a2:	24          	lessthan
+  a3:	73          	loadsp 12
+  a4:	73          	loadsp 12
+  a5:	2e          	eq
+  a6:	07          	or
+  a7:	53          	storesp 12
+  a8:	51          	storesp 4
+  a9:	04          	poppc
+	...
+
+000000c0 <_ulessthan>:
+  c0:	71          	loadsp 4
+  c1:	73          	loadsp 12
+  c2:	71          	loadsp 4
+  c3:	09          	not
+  c4:	71          	loadsp 4
+  c5:	06          	and
+  c6:	81          	im 1
+  c7:	06          	and
+  c8:	30          	neg
+  c9:	72          	loadsp 8
+  ca:	0a          	flip
+  cb:	10          	addsp 0
+  cc:	0a          	flip
+  cd:	72          	loadsp 8
+  ce:	0a          	flip
+  cf:	10          	addsp 0
+  d0:	0a          	flip
+  d1:	31          	sub
+  d2:	05          	add
+  d3:	0a          	flip
+  d4:	81          	im 1
+  d5:	06          	and
+  d6:	51          	storesp 4
+  d7:	51          	storesp 4
+  d8:	53          	storesp 12
+  d9:	51          	storesp 4
+  da:	04          	poppc
+  db:	00          	breakpoint
+  dc:	00          	breakpoint
+  dd:	00          	breakpoint
+	...
+
+000000e0 <_ulessthanorequal>:
+  e0:	72          	loadsp 8
+  e1:	72          	loadsp 8
+  e2:	26          	ulessthan
+  e3:	73          	loadsp 12
+  e4:	73          	loadsp 12
+  e5:	2e          	eq
+  e6:	07          	or
+  e7:	53          	storesp 12
+  e8:	51          	storesp 4
+  e9:	04          	poppc
+	...
+
+00000100 <_swap>:
+	...
+
+00000120 <_slowmult>:
+ 120:	0b          	nop
+ 121:	0b          	nop
+ 122:	0b          	nop
+ 123:	88          	im 8
+ 124:	bc          	im 60
+ 125:	04          	poppc
+	...
+
+00000140 <_lshiftright>:
+ 140:	72          	loadsp 8
+ 141:	0a          	flip
+ 142:	72          	loadsp 8
+ 143:	2b          	ashiftleft
+ 144:	0a          	flip
+ 145:	53          	storesp 12
+ 146:	51          	storesp 4
+ 147:	04          	poppc
+	...
+
+00000160 <_ashiftleft>:
+ 160:	72          	loadsp 8
+ 161:	72          	loadsp 8
+ 162:	9f          	im 31
+ 163:	06          	and
+ 164:	09          	not
+ 165:	81          	im 1
+ 166:	05          	add
+ 167:	0b          	nop
+ 168:	0b          	nop
+ 169:	0b          	nop
+ 16a:	88          	im 8
+ 16b:	9f          	im 31
+ 16c:	05          	add
+ 16d:	04          	poppc
+	...
+
+00000180 <_ashiftright>:
+ 180:	72          	loadsp 8
+ 181:	72          	loadsp 8
+ 182:	2a          	lshiftright
+ 183:	ff          	im -1
+ 184:	73          	loadsp 12
+ 185:	9f          	im 31
+ 186:	06          	and
+ 187:	2a          	lshiftright
+ 188:	09          	not
+ 189:	74          	loadsp 16
+ 18a:	09          	not
+ 18b:	0a          	flip
+ 18c:	81          	im 1
+ 18d:	06          	and
+ 18e:	ff          	im -1
+ 18f:	05          	add
+ 190:	06          	and
+ 191:	07          	or
+ 192:	53          	storesp 12
+ 193:	51          	storesp 4
+ 194:	04          	poppc
+	...
+
+000001a0 <_call>:
+ 1a0:	71          	loadsp 4
+ 1a1:	71          	loadsp 4
+ 1a2:	53          	storesp 12
+ 1a3:	51          	storesp 4
+ 1a4:	02          	pushsp
+ 1a5:	0d          	popsp
+ 1a6:	04          	poppc
+
+000001a7 <_storehtail>:
+ 1a7:	06          	and
+ 1a8:	73          	loadsp 12
+ 1a9:	83          	im 3
+ 1aa:	06          	and
+ 1ab:	09          	not
+ 1ac:	81          	im 1
+ 1ad:	05          	add
+ 1ae:	82          	im 2
+ 1af:	05          	add
+ 1b0:	83          	im 3
+ 1b1:	2b          	ashiftleft
+ 1b2:	0b          	nop
+ 1b3:	2b          	ashiftleft
+ 1b4:	07          	or
+ 1b5:	72          	loadsp 8
+ 1b6:	fc          	im -4
+ 1b7:	06          	and
+ 1b8:	0c          	store
+ 1b9:	51          	storesp 4
+ 1ba:	51          	storesp 4
+ 1bb:	04          	poppc
+ 1bc:	00          	breakpoint
+ 1bd:	00          	breakpoint
+	...
+
+000001c0 <_eq>:
+ 1c0:	72          	loadsp 8
+ 1c1:	09          	not
+ 1c2:	81          	im 1
+ 1c3:	05          	add
+ 1c4:	72          	loadsp 8
+ 1c5:	05          	add
+ 1c6:	09          	not
+ 1c7:	70          	loadsp 0
+ 1c8:	81          	im 1
+ 1c9:	05          	add
+ 1ca:	09          	not
+ 1cb:	06          	and
+ 1cc:	0a          	flip
+ 1cd:	81          	im 1
+ 1ce:	06          	and
+ 1cf:	53          	storesp 12
+ 1d0:	51          	storesp 4
+ 1d1:	04          	poppc
+	...
+
+000001e0 <_neq>:
+ 1e0:	72          	loadsp 8
+ 1e1:	09          	not
+ 1e2:	81          	im 1
+ 1e3:	05          	add
+ 1e4:	72          	loadsp 8
+ 1e5:	05          	add
+ 1e6:	09          	not
+ 1e7:	70          	loadsp 0
+ 1e8:	81          	im 1
+ 1e9:	05          	add
+ 1ea:	09          	not
+ 1eb:	06          	and
+ 1ec:	0a          	flip
+ 1ed:	09          	not
+ 1ee:	81          	im 1
+ 1ef:	06          	and
+ 1f0:	53          	storesp 12
+ 1f1:	51          	storesp 4
+ 1f2:	04          	poppc
+	...
+
+00000200 <_neg>:
+ 200:	71          	loadsp 4
+ 201:	09          	not
+ 202:	81          	im 1
+ 203:	05          	add
+ 204:	52          	storesp 8
+ 205:	04          	poppc
+	...
+
+00000220 <_sub>:
+ 220:	72          	loadsp 8
+ 221:	72          	loadsp 8
+ 222:	09          	not
+ 223:	81          	im 1
+ 224:	05          	add
+ 225:	05          	add
+ 226:	53          	storesp 12
+ 227:	51          	storesp 4
+ 228:	04          	poppc
+	...
+
+00000240 <_xor>:
+ 240:	72          	loadsp 8
+ 241:	09          	not
+ 242:	72          	loadsp 8
+ 243:	06          	and
+ 244:	73          	loadsp 12
+ 245:	73          	loadsp 12
+ 246:	09          	not
+ 247:	06          	and
+ 248:	07          	or
+ 249:	53          	storesp 12
+ 24a:	51          	storesp 4
+ 24b:	04          	poppc
+	...
+
+00000260 <_loadb>:
+ 260:	71          	loadsp 4
+ 261:	fc          	im -4
+ 262:	06          	and
+ 263:	08          	load
+ 264:	72          	loadsp 8
+ 265:	83          	im 3
+ 266:	06          	and
+ 267:	09          	not
+ 268:	81          	im 1
+ 269:	05          	add
+ 26a:	83          	im 3
+ 26b:	05          	add
+ 26c:	10          	addsp 0
+ 26d:	10          	addsp 0
+ 26e:	10          	addsp 0
+ 26f:	2a          	lshiftright
+ 270:	81          	im 1
+ 271:	ff          	im -1
+ 272:	06          	and
+ 273:	52          	storesp 8
+ 274:	04          	poppc
+	...
+
+00000280 <_storeb>:
+ 280:	71          	loadsp 4
+ 281:	fc          	im -4
+ 282:	06          	and
+ 283:	08          	load
+ 284:	0b          	nop
+ 285:	0b          	nop
+ 286:	0b          	nop
+ 287:	92          	im 18
+ 288:	b8          	im 56
+ 289:	73          	loadsp 12
+ 28a:	83          	im 3
+ 28b:	06          	and
+ 28c:	10          	addsp 0
+ 28d:	10          	addsp 0
+ 28e:	05          	add
+ 28f:	08          	load
+ 290:	06          	and
+ 291:	0b          	nop
+ 292:	0b          	nop
+ 293:	0b          	nop
+ 294:	88          	im 8
+ 295:	a2          	im 34
+ 296:	04          	poppc
+	...
+
+000002a0 <_div>:
+ 2a0:	0b          	nop
+ 2a1:	0b          	nop
+ 2a2:	0b          	nop
+ 2a3:	88          	im 8
+ 2a4:	fe          	im -2
+ 2a5:	04          	poppc
+	...
+
+000002c0 <_mod>:
+ 2c0:	0b          	nop
+ 2c1:	0b          	nop
+ 2c2:	0b          	nop
+ 2c3:	88          	im 8
+ 2c4:	d8          	im -40
+ 2c5:	04          	poppc
+	...
+
+000002e0 <_eqbranch>:
+ 2e0:	72          	loadsp 8
+ 2e1:	09          	not
+ 2e2:	70          	loadsp 0
+ 2e3:	81          	im 1
+ 2e4:	05          	add
+ 2e5:	09          	not
+ 2e6:	06          	and
+ 2e7:	0a          	flip
+ 2e8:	81          	im 1
+ 2e9:	06          	and
+ 2ea:	ff          	im -1
+ 2eb:	05          	add
+ 2ec:	70          	loadsp 0
+ 2ed:	54          	storesp 16
+ 2ee:	71          	loadsp 4
+ 2ef:	06          	and
+ 2f0:	73          	loadsp 12
+ 2f1:	09          	not
+ 2f2:	72          	loadsp 8
+ 2f3:	74          	loadsp 16
+ 2f4:	05          	add
+ 2f5:	ff          	im -1
+ 2f6:	05          	add
+ 2f7:	06          	and
+ 2f8:	07          	or
+ 2f9:	51          	storesp 4
+ 2fa:	51          	storesp 4
+ 2fb:	51          	storesp 4
+ 2fc:	04          	poppc
+ 2fd:	00          	breakpoint
+	...
+
+00000300 <_neqbranch>:
+ 300:	72          	loadsp 8
+ 301:	09          	not
+ 302:	70          	loadsp 0
+ 303:	81          	im 1
+ 304:	05          	add
+ 305:	09          	not
+ 306:	06          	and
+ 307:	0a          	flip
+ 308:	09          	not
+ 309:	81          	im 1
+ 30a:	06          	and
+ 30b:	ff          	im -1
+ 30c:	05          	add
+ 30d:	70          	loadsp 0
+ 30e:	54          	storesp 16
+ 30f:	71          	loadsp 4
+ 310:	06          	and
+ 311:	73          	loadsp 12
+ 312:	09          	not
+ 313:	72          	loadsp 8
+ 314:	74          	loadsp 16
+ 315:	05          	add
+ 316:	ff          	im -1
+ 317:	05          	add
+ 318:	06          	and
+ 319:	07          	or
+ 31a:	51          	storesp 4
+ 31b:	51          	storesp 4
+ 31c:	51          	storesp 4
+ 31d:	04          	poppc
+	...
+
+00000320 <_poppcrel>:
+ 320:	05          	add
+ 321:	ff          	im -1
+ 322:	05          	add
+ 323:	04          	poppc
+	...
+
+00000340 <_config>:
+ 340:	81          	im 1
+ 341:	0b          	nop
+ 342:	92          	im 18
+ 343:	c8          	im -56
+ 344:	0c          	store
+ 345:	51          	storesp 4
+ 346:	04          	poppc
+	...
+
+0000035d <_pushpc>:
+ 35d:	71          	loadsp 4
+ 35e:	81          	im 1
+ 35f:	05          	add
+ 360:	52          	storesp 8
+ 361:	04          	poppc
+	...
+
+0000037d <_syscall_emulate>:
+	...
+
+0000039d <_pushspadd>:
+ 39d:	02          	pushsp
+ 39e:	84          	im 4
+ 39f:	05          	add
+ 3a0:	72          	loadsp 8
+ 3a1:	10          	addsp 0
+ 3a2:	10          	addsp 0
+ 3a3:	05          	add
+ 3a4:	52          	storesp 8
+ 3a5:	04          	poppc
+	...
+
+000003bd <_halfmult>:
+	...
+
+000003dd <_callpcrel>:
+ 3dd:	71          	loadsp 4
+ 3de:	71          	loadsp 4
+ 3df:	05          	add
+ 3e0:	ff          	im -1
+ 3e1:	05          	add
+ 3e2:	71          	loadsp 4
+ 3e3:	53          	storesp 12
+ 3e4:	51          	storesp 4
+ 3e5:	02          	pushsp
+ 3e6:	0d          	popsp
+ 3e7:	04          	poppc
+	...
+Disassembly of section .text:
+
+00000400 <_ashiftleftBegin>:
+ 400:	10          	addsp 0
+ 401:	10          	addsp 0
+ 402:	10          	addsp 0
+ 403:	10          	addsp 0
+ 404:	10          	addsp 0
+ 405:	10          	addsp 0
+ 406:	10          	addsp 0
+ 407:	10          	addsp 0
+ 408:	10          	addsp 0
+ 409:	10          	addsp 0
+ 40a:	10          	addsp 0
+ 40b:	10          	addsp 0
+ 40c:	10          	addsp 0
+ 40d:	10          	addsp 0
+ 40e:	10          	addsp 0
+ 40f:	10          	addsp 0
+ 410:	10          	addsp 0
+ 411:	10          	addsp 0
+ 412:	10          	addsp 0
+ 413:	10          	addsp 0
+ 414:	10          	addsp 0
+ 415:	10          	addsp 0
+ 416:	10          	addsp 0
+ 417:	10          	addsp 0
+ 418:	10          	addsp 0
+ 419:	10          	addsp 0
+ 41a:	10          	addsp 0
+ 41b:	10          	addsp 0
+ 41c:	10          	addsp 0
+ 41d:	10          	addsp 0
+ 41e:	10          	addsp 0
+
+0000041f <_ashiftleftEnd>:
+ 41f:	53          	storesp 12
+ 420:	51          	storesp 4
+ 421:	04          	poppc
+
+00000422 <_storebtail>:
+ 422:	73          	loadsp 12
+ 423:	81          	im 1
+ 424:	ff          	im -1
+ 425:	06          	and
+ 426:	73          	loadsp 12
+ 427:	83          	im 3
+ 428:	06          	and
+ 429:	09          	not
+ 42a:	81          	im 1
+ 42b:	05          	add
+ 42c:	83          	im 3
+ 42d:	05          	add
+ 42e:	10          	addsp 0
+ 42f:	10          	addsp 0
+ 430:	10          	addsp 0
+ 431:	2b          	ashiftleft
+ 432:	07          	or
+ 433:	72          	loadsp 8
+ 434:	fc          	im -4
+ 435:	06          	and
+ 436:	0c          	store
+ 437:	51          	storesp 4
+ 438:	51          	storesp 4
+ 439:	04          	poppc
+
+0000043a <_syscall>:
+ 43a:	3c          	syscall
+ 43b:	04          	poppc
+
+0000043c <_slowmultImpl>:
+ 43c:	72          	loadsp 8
+ 43d:	72          	loadsp 8
+ 43e:	80          	im 0
+ 43f:	72          	loadsp 8
+ 440:	81          	im 1
+ 441:	06          	and
+ 442:	ff          	im -1
+ 443:	05          	add
+ 444:	09          	not
+ 445:	72          	loadsp 8
+ 446:	06          	and
+ 447:	05          	add
+ 448:	71          	loadsp 4
+ 449:	10          	addsp 0
+ 44a:	52          	storesp 8
+ 44b:	72          	loadsp 8
+ 44c:	0a          	flip
+ 44d:	10          	addsp 0
+ 44e:	0a          	flip
+ 44f:	53          	storesp 12
+ 450:	72          	loadsp 8
+ 451:	ed          	im -19
+ 452:	38          	neqbranch
+ 453:	51          	storesp 4
+ 454:	51          	storesp 4
+ 455:	53          	storesp 12
+ 456:	51          	storesp 4
+ 457:	04          	poppc
+
+00000458 <___mod>:
+ 458:	83          	im 3
+ 459:	e0          	im -32
+ 45a:	80          	im 0
+ 45b:	08          	load
+ 45c:	83          	im 3
+ 45d:	e0          	im -32
+ 45e:	84          	im 4
+ 45f:	08          	load
+ 460:	83          	im 3
+ 461:	e0          	im -32
+ 462:	88          	im 8
+ 463:	08          	load
+ 464:	75          	loadsp 20
+ 465:	75          	loadsp 20
+ 466:	8f          	im 15
+ 467:	82          	im 2
+ 468:	2d          	call
+ 469:	50          	storesp 0
+ 46a:	50          	storesp 0
+ 46b:	83          	im 3
+ 46c:	e0          	im -32
+ 46d:	80          	im 0
+ 46e:	08          	load
+ 46f:	56          	storesp 24
+ 470:	83          	im 3
+ 471:	e0          	im -32
+ 472:	88          	im 8
+ 473:	0c          	store
+ 474:	83          	im 3
+ 475:	e0          	im -32
+ 476:	84          	im 4
+ 477:	0c          	store
+ 478:	83          	im 3
+ 479:	e0          	im -32
+ 47a:	80          	im 0
+ 47b:	0c          	store
+ 47c:	51          	storesp 4
+ 47d:	04          	poppc
+
+0000047e <___div>:
+ 47e:	83          	im 3
+ 47f:	e0          	im -32
+ 480:	80          	im 0
+ 481:	08          	load
+ 482:	83          	im 3
+ 483:	e0          	im -32
+ 484:	84          	im 4
+ 485:	08          	load
+ 486:	83          	im 3
+ 487:	e0          	im -32
+ 488:	88          	im 8
+ 489:	08          	load
+ 48a:	75          	loadsp 20
+ 48b:	75          	loadsp 20
+ 48c:	8d          	im 13
+ 48d:	96          	im 22
+ 48e:	2d          	call
+ 48f:	50          	storesp 0
+ 490:	50          	storesp 0
+ 491:	83          	im 3
+ 492:	e0          	im -32
+ 493:	80          	im 0
+ 494:	08          	load
+ 495:	56          	storesp 24
+ 496:	83          	im 3
+ 497:	e0          	im -32
+ 498:	88          	im 8
+ 499:	0c          	store
+ 49a:	83          	im 3
+ 49b:	e0          	im -32
+ 49c:	84          	im 4
+ 49d:	0c          	store
+ 49e:	83          	im 3
+ 49f:	e0          	im -32
+ 4a0:	80          	im 0
+ 4a1:	0c          	store
+ 4a2:	51          	storesp 4
+ 4a3:	04          	poppc
+	...
+
+000004a6 <_boot>:
+ 4a6:	80          	im 0
+ 4a7:	04          	poppc
+
+000004a8 <_break>:
+ 4a8:	89          	im 9
+ 4a9:	a8          	im 40
+ 4aa:	04          	poppc
+
+000004ab <_premain>:
+ 4ab:	89          	im 9
+ 4ac:	a8          	im 40
+ 4ad:	0b          	nop
+ 4ae:	8c          	im 12
+ 4af:	d8          	im -40
+ 4b0:	04          	poppc
+
+000004b1 <wait_us>:
+#include "led.h"
+
+void
+wait_us(int unsigned num)
+{
+ 4b1:	83          	im 3
+ 4b2:	e0          	im -32
+ 4b3:	8c          	im 12
+ 4b4:	08          	load
+ 4b5:	02          	pushsp
+ 4b6:	83          	im 3
+ 4b7:	e0          	im -32
+ 4b8:	8c          	im 12
+ 4b9:	0c          	store
+ 4ba:	fe          	im -2
+ 4bb:	3d          	pushspadd
+ 4bc:	0d          	popsp
+
+000004bd <.LM2>:
+	// 28ish
+	int unsigned cycles = num*28;
+ 4bd:	83          	im 3
+ 4be:	e0          	im -32
+ 4bf:	8c          	im 12
+ 4c0:	08          	load
+ 4c1:	88          	im 8
+ 4c2:	05          	add
+ 4c3:	08          	load
+ 4c4:	70          	loadsp 0
+ 4c5:	70          	loadsp 0
+ 4c6:	83          	im 3
+ 4c7:	2b          	ashiftleft
+ 4c8:	70          	loadsp 0
+ 4c9:	73          	loadsp 12
+ 4ca:	31          	sub
+ 4cb:	70          	loadsp 0
+ 4cc:	82          	im 2
+ 4cd:	2b          	ashiftleft
+ 4ce:	70          	loadsp 0
+ 4cf:	83          	im 3
+ 4d0:	e0          	im -32
+ 4d1:	8c          	im 12
+ 4d2:	08          	load
+ 4d3:	fc          	im -4
+ 4d4:	05          	add
+ 4d5:	0c          	store
+
+000004d6 <.LM3>:
+	*zpu_pause = cycles;
+ 4d6:	92          	im 18
+ 4d7:	d4          	im -44
+ 4d8:	08          	load
+ 4d9:	83          	im 3
+ 4da:	e0          	im -32
+ 4db:	8c          	im 12
+ 4dc:	08          	load
+ 4dd:	fc          	im -4
+ 4de:	05          	add
+ 4df:	08          	load
+ 4e0:	71          	loadsp 4
+ 4e1:	0c          	store
+ 4e2:	51          	storesp 4
+ 4e3:	51          	storesp 4
+ 4e4:	51          	storesp 4
+ 4e5:	51          	storesp 4
+ 4e6:	52          	storesp 8
+ 4e7:	52          	storesp 8
+
+000004e8 <.LM4>:
+}
+ 4e8:	84          	im 4
+ 4e9:	3d          	pushspadd
+ 4ea:	0d          	popsp
+ 4eb:	83          	im 3
+ 4ec:	e0          	im -32
+ 4ed:	8c          	im 12
+ 4ee:	0c          	store
+ 4ef:	04          	poppc
+
+000004f0 <clear_64k_ram>:
+
+void clear_64k_ram()
+{
+ 4f0:	83          	im 3
+ 4f1:	e0          	im -32
+ 4f2:	8c          	im 12
+ 4f3:	08          	load
+ 4f4:	02          	pushsp
+ 4f5:	83          	im 3
+ 4f6:	e0          	im -32
+ 4f7:	8c          	im 12
+ 4f8:	0c          	store
+ 4f9:	ff          	im -1
+ 4fa:	3d          	pushspadd
+ 4fb:	0d          	popsp
+
+000004fc <.LM6>:
+	int i=0;
+ 4fc:	80          	im 0
+ 4fd:	0b          	nop
+ 4fe:	83          	im 3
+ 4ff:	e0          	im -32
+ 500:	8c          	im 12
+ 501:	08          	load
+ 502:	fc          	im -4
+ 503:	05          	add
+ 504:	0c          	store
+
+00000505 <.LM7>:
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+ 505:	92          	im 18
+ 506:	e4          	im -28
+ 507:	08          	load
+ 508:	51          	storesp 4
+ 509:	ff          	im -1
+ 50a:	87          	im 7
+ 50b:	c3          	im -61
+ 50c:	e1          	im -31
+ 50d:	f0          	im -16
+ 50e:	71          	loadsp 4
+ 50f:	0c          	store
+
+00000510 <.LM8>:
+	*zpu_ledg = 0x0;
+ 510:	92          	im 18
+ 511:	e0          	im -32
+ 512:	08          	load
+ 513:	51          	storesp 4
+ 514:	80          	im 0
+ 515:	71          	loadsp 4
+ 516:	0c          	store
+
+00000517 <.LM9>:
+	//wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+ 517:	88          	im 8
+ 518:	80          	im 0
+ 519:	0a          	flip
+ 51a:	0b          	nop
+ 51b:	83          	im 3
+ 51c:	e0          	im -32
+ 51d:	8c          	im 12
+ 51e:	08          	load
+ 51f:	fc          	im -4
+ 520:	05          	add
+ 521:	0c          	store
+
+00000522 <.L3>:
+ 522:	83          	im 3
+ 523:	e0          	im -32
+ 524:	8c          	im 12
+ 525:	08          	load
+ 526:	fc          	im -4
+ 527:	05          	add
+ 528:	08          	load
+ 529:	81          	im 1
+ 52a:	84          	im 4
+ 52b:	80          	im 0
+ 52c:	80          	im 0
+ 52d:	2e          	eq
+ 52e:	9e          	im 30
+ 52f:	38          	neqbranch
+
+00000530 <.LM10>:
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+ 530:	83          	im 3
+ 531:	e0          	im -32
+ 532:	8c          	im 12
+ 533:	08          	load
+ 534:	fc          	im -4
+ 535:	05          	add
+ 536:	08          	load
+ 537:	51          	storesp 4
+ 538:	80          	im 0
+ 539:	71          	loadsp 4
+ 53a:	34          	storeb
+
+0000053b <.LM11>:
+ 53b:	83          	im 3
+ 53c:	e0          	im -32
+ 53d:	8c          	im 12
+ 53e:	08          	load
+ 53f:	fc          	im -4
+ 540:	05          	add
+ 541:	08          	load
+ 542:	81          	im 1
+ 543:	05          	add
+ 544:	83          	im 3
+ 545:	e0          	im -32
+ 546:	8c          	im 12
+ 547:	08          	load
+ 548:	fc          	im -4
+ 549:	05          	add
+ 54a:	0c          	store
+ 54b:	d6          	im -42
+ 54c:	39          	poppcrel
+
+0000054d <.L4>:
+	}
+
+	*zpu_ledr = 0x55555555;
+ 54d:	92          	im 18
+ 54e:	e4          	im -28
+ 54f:	08          	load
+ 550:	51          	storesp 4
+ 551:	85          	im 5
+ 552:	aa          	im 42
+ 553:	d5          	im -43
+ 554:	aa          	im 42
+ 555:	d5          	im -43
+ 556:	71          	loadsp 4
+ 557:	0c          	store
+
+00000558 <.LM13>:
+	*zpu_ledg = 0x55555555;
+ 558:	92          	im 18
+ 559:	e0          	im -32
+ 55a:	08          	load
+ 55b:	51          	storesp 4
+ 55c:	85          	im 5
+ 55d:	aa          	im 42
+ 55e:	d5          	im -43
+ 55f:	aa          	im 42
+ 560:	d5          	im -43
+ 561:	71          	loadsp 4
+ 562:	0c          	store
+
+00000563 <.LM14>:
+
+	for (i=0x800000; i!=0x810000; i+=4)
+ 563:	82          	im 2
+ 564:	80          	im 0
+ 565:	0a          	flip
+ 566:	0b          	nop
+ 567:	83          	im 3
+ 568:	e0          	im -32
+ 569:	8c          	im 12
+ 56a:	08          	load
+ 56b:	fc          	im -4
+ 56c:	05          	add
+ 56d:	0c          	store
+
+0000056e <.L6>:
+ 56e:	83          	im 3
+ 56f:	e0          	im -32
+ 570:	8c          	im 12
+ 571:	08          	load
+ 572:	fc          	im -4
+ 573:	05          	add
+ 574:	08          	load
+ 575:	84          	im 4
+ 576:	84          	im 4
+ 577:	80          	im 0
+ 578:	80          	im 0
+ 579:	2e          	eq
+ 57a:	9e          	im 30
+ 57b:	38          	neqbranch
+
+0000057c <.LM15>:
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+ 57c:	83          	im 3
+ 57d:	e0          	im -32
+ 57e:	8c          	im 12
+ 57f:	08          	load
+ 580:	fc          	im -4
+ 581:	05          	add
+ 582:	08          	load
+ 583:	51          	storesp 4
+ 584:	80          	im 0
+ 585:	71          	loadsp 4
+ 586:	0c          	store
+
+00000587 <.LM16>:
+ 587:	83          	im 3
+ 588:	e0          	im -32
+ 589:	8c          	im 12
+ 58a:	08          	load
+ 58b:	fc          	im -4
+ 58c:	05          	add
+ 58d:	08          	load
+ 58e:	84          	im 4
+ 58f:	05          	add
+ 590:	83          	im 3
+ 591:	e0          	im -32
+ 592:	8c          	im 12
+ 593:	08          	load
+ 594:	fc          	im -4
+ 595:	05          	add
+ 596:	0c          	store
+ 597:	d6          	im -42
+ 598:	39          	poppcrel
+
+00000599 <.L7>:
+	}
+
+	*zpu_ledr = 0;
+ 599:	92          	im 18
+ 59a:	e4          	im -28
+ 59b:	08          	load
+ 59c:	51          	storesp 4
+ 59d:	80          	im 0
+ 59e:	71          	loadsp 4
+ 59f:	0c          	store
+
+000005a0 <.LM18>:
+	*zpu_ledg = 0xf0f0f0f0;
+ 5a0:	92          	im 18
+ 5a1:	e0          	im -32
+ 5a2:	08          	load
+ 5a3:	51          	storesp 4
+ 5a4:	ff          	im -1
+ 5a5:	87          	im 7
+ 5a6:	c3          	im -61
+ 5a7:	e1          	im -31
+ 5a8:	f0          	im -16
+ 5a9:	71          	loadsp 4
+ 5aa:	0c          	store
+
+000005ab <.LM19>:
+	//wait_us(200000);
+	return;
+}
+ 5ab:	83          	im 3
+ 5ac:	3d          	pushspadd
+ 5ad:	0d          	popsp
+ 5ae:	83          	im 3
+ 5af:	e0          	im -32
+ 5b0:	8c          	im 12
+ 5b1:	0c          	store
+ 5b2:	04          	poppc
+
+000005b3 <reset_6502>:
+
+void reset_6502(unsigned int reset_n)
+{
+ 5b3:	83          	im 3
+ 5b4:	e0          	im -32
+ 5b5:	8c          	im 12
+ 5b6:	08          	load
+ 5b7:	02          	pushsp
+ 5b8:	83          	im 3
+ 5b9:	e0          	im -32
+ 5ba:	8c          	im 12
+ 5bb:	0c          	store
+ 5bc:	fe          	im -2
+ 5bd:	3d          	pushspadd
+ 5be:	0d          	popsp
+
+000005bf <.LM21>:
+	int prev = *zpu_config;
+ 5bf:	92          	im 18
+ 5c0:	d0          	im -48
+ 5c1:	08          	load
+ 5c2:	70          	loadsp 0
+ 5c3:	08          	load
+ 5c4:	83          	im 3
+ 5c5:	e0          	im -32
+ 5c6:	8c          	im 12
+ 5c7:	08          	load
+ 5c8:	fc          	im -4
+ 5c9:	05          	add
+ 5ca:	0c          	store
+ 5cb:	51          	storesp 4
+
+000005cc <.LM22>:
+	if (reset_n == 1)
+ 5cc:	83          	im 3
+ 5cd:	e0          	im -32
+ 5ce:	8c          	im 12
+ 5cf:	08          	load
+ 5d0:	88          	im 8
+ 5d1:	05          	add
+ 5d2:	08          	load
+ 5d3:	81          	im 1
+ 5d4:	2e          	eq
+ 5d5:	09          	not
+ 5d6:	81          	im 1
+ 5d7:	06          	and
+ 5d8:	95          	im 21
+ 5d9:	38          	neqbranch
+
+000005da <.LM23>:
+		*zpu_config = prev&~(1<<7);
+ 5da:	92          	im 18
+ 5db:	d0          	im -48
+ 5dc:	08          	load
+ 5dd:	83          	im 3
+ 5de:	e0          	im -32
+ 5df:	8c          	im 12
+ 5e0:	08          	load
+ 5e1:	fc          	im -4
+ 5e2:	05          	add
+ 5e3:	08          	load
+ 5e4:	fe          	im -2
+ 5e5:	ff          	im -1
+ 5e6:	06          	and
+ 5e7:	70          	loadsp 0
+ 5e8:	72          	loadsp 8
+ 5e9:	0c          	store
+ 5ea:	52          	storesp 8
+ 5eb:	52          	storesp 8
+ 5ec:	93          	im 19
+ 5ed:	39          	poppcrel
+
+000005ee <.L10>:
+	else
+		*zpu_config = prev|(1<<7);
+ 5ee:	92          	im 18
+ 5ef:	d0          	im -48
+ 5f0:	08          	load
+ 5f1:	83          	im 3
+ 5f2:	e0          	im -32
+ 5f3:	8c          	im 12
+ 5f4:	08          	load
+ 5f5:	fc          	im -4
+ 5f6:	05          	add
+ 5f7:	08          	load
+ 5f8:	81          	im 1
+ 5f9:	80          	im 0
+ 5fa:	07          	or
+ 5fb:	70          	loadsp 0
+ 5fc:	72          	loadsp 8
+ 5fd:	0c          	store
+ 5fe:	52          	storesp 8
+ 5ff:	52          	storesp 8
+
+00000600 <.L9>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+ 600:	84          	im 4
+ 601:	3d          	pushspadd
+ 602:	0d          	popsp
+ 603:	83          	im 3
+ 604:	e0          	im -32
+ 605:	8c          	im 12
+ 606:	0c          	store
+ 607:	04          	poppc
+
+00000608 <pause_6502>:
+
+void pause_6502(unsigned int pause)
+{
+ 608:	83          	im 3
+ 609:	e0          	im -32
+ 60a:	8c          	im 12
+ 60b:	08          	load
+ 60c:	02          	pushsp
+ 60d:	83          	im 3
+ 60e:	e0          	im -32
+ 60f:	8c          	im 12
+ 610:	0c          	store
+ 611:	fe          	im -2
+ 612:	3d          	pushspadd
+ 613:	0d          	popsp
+
+00000614 <.LM27>:
+	int prev = *zpu_config;
+ 614:	92          	im 18
+ 615:	d0          	im -48
+ 616:	08          	load
+ 617:	70          	loadsp 0
+ 618:	08          	load
+ 619:	83          	im 3
+ 61a:	e0          	im -32
+ 61b:	8c          	im 12
+ 61c:	08          	load
+ 61d:	fc          	im -4
+ 61e:	05          	add
+ 61f:	0c          	store
+ 620:	51          	storesp 4
+
+00000621 <.LM28>:
+	if (pause == 0)
+ 621:	83          	im 3
+ 622:	e0          	im -32
+ 623:	8c          	im 12
+ 624:	08          	load
+ 625:	88          	im 8
+ 626:	05          	add
+ 627:	08          	load
+ 628:	95          	im 21
+ 629:	38          	neqbranch
+
+0000062a <.LM29>:
+		*zpu_config = prev&~(1<<6);
+ 62a:	92          	im 18
+ 62b:	d0          	im -48
+ 62c:	08          	load
+ 62d:	83          	im 3
+ 62e:	e0          	im -32
+ 62f:	8c          	im 12
+ 630:	08          	load
+ 631:	fc          	im -4
+ 632:	05          	add
+ 633:	08          	load
+ 634:	ff          	im -1
+ 635:	bf          	im 63
+ 636:	06          	and
+ 637:	70          	loadsp 0
+ 638:	72          	loadsp 8
+ 639:	0c          	store
+ 63a:	52          	storesp 8
+ 63b:	52          	storesp 8
+ 63c:	93          	im 19
+ 63d:	39          	poppcrel
+
+0000063e <.L13>:
+	else
+		*zpu_config = prev|(1<<6);
+ 63e:	92          	im 18
+ 63f:	d0          	im -48
+ 640:	08          	load
+ 641:	83          	im 3
+ 642:	e0          	im -32
+ 643:	8c          	im 12
+ 644:	08          	load
+ 645:	fc          	im -4
+ 646:	05          	add
+ 647:	08          	load
+ 648:	80          	im 0
+ 649:	c0          	im -64
+ 64a:	07          	or
+ 64b:	70          	loadsp 0
+ 64c:	72          	loadsp 8
+ 64d:	0c          	store
+ 64e:	52          	storesp 8
+ 64f:	52          	storesp 8
+
+00000650 <.L12>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+ 650:	84          	im 4
+ 651:	3d          	pushspadd
+ 652:	0d          	popsp
+ 653:	83          	im 3
+ 654:	e0          	im -32
+ 655:	8c          	im 12
+ 656:	0c          	store
+ 657:	04          	poppc
+
+00000658 <main>:
+
+int main(void)
+{
+ 658:	83          	im 3
+ 659:	e0          	im -32
+ 65a:	8c          	im 12
+ 65b:	08          	load
+ 65c:	02          	pushsp
+ 65d:	83          	im 3
+ 65e:	e0          	im -32
+ 65f:	8c          	im 12
+ 660:	0c          	store
+ 661:	fd          	im -3
+ 662:	3d          	pushspadd
+ 663:	0d          	popsp
+
+00000664 <.LM33>:
+	unsigned int i=0;
+ 664:	80          	im 0
+ 665:	0b          	nop
+ 666:	83          	im 3
+ 667:	e0          	im -32
+ 668:	8c          	im 12
+ 669:	08          	load
+ 66a:	fc          	im -4
+ 66b:	05          	add
+ 66c:	0c          	store
+
+0000066d <.LM34>:
+	unsigned char temp = 0;
+ 66d:	80          	im 0
+ 66e:	0b          	nop
+ 66f:	83          	im 3
+ 670:	e0          	im -32
+ 671:	8c          	im 12
+ 672:	08          	load
+ 673:	f8          	im -8
+ 674:	05          	add
+ 675:	34          	storeb
+
+00000676 <.LM35>:
+	pause_6502(1);
+ 676:	81          	im 1
+ 677:	51          	storesp 4
+ 678:	ff          	im -1
+ 679:	8e          	im 14
+ 67a:	3f          	callpcrel
+
+0000067b <.LM36>:
+
+		//wait_us(200000);
+		reset_6502(0);
+ 67b:	80          	im 0
+ 67c:	51          	storesp 4
+ 67d:	fe          	im -2
+ 67e:	b4          	im 52
+ 67f:	3f          	callpcrel
+
+00000680 <.LM37>:
+		*atari_nmien = 0x00;
+ 680:	93          	im 19
+ 681:	b4          	im 52
+ 682:	08          	load
+ 683:	52          	storesp 8
+ 684:	80          	im 0
+ 685:	72          	loadsp 8
+ 686:	34          	storeb
+
+00000687 <.LM38>:
+		clear_64k_ram();
+ 687:	fc          	im -4
+ 688:	e7          	im -25
+ 689:	3f          	callpcrel
+
+0000068a <.LM39>:
+		reset_6502(1);
+ 68a:	81          	im 1
+ 68b:	51          	storesp 4
+ 68c:	fe          	im -2
+ 68d:	a5          	im 37
+ 68e:	3f          	callpcrel
+
+0000068f <.LM40>:
+		pause_6502(0);
+ 68f:	80          	im 0
+ 690:	51          	storesp 4
+ 691:	fe          	im -2
+ 692:	f5          	im -11
+ 693:	3f          	callpcrel
+
+00000694 <.L16>:
+	for(;;);
+ 694:	ff          	im -1
+ 695:	39          	poppcrel
+
+00000696 <__divsi3>:
+ 696:	83          	im 3
+ 697:	e0          	im -32
+ 698:	8c          	im 12
+ 699:	08          	load
+ 69a:	02          	pushsp
+ 69b:	83          	im 3
+ 69c:	e0          	im -32
+ 69d:	8c          	im 12
+ 69e:	0c          	store
+ 69f:	f9          	im -7
+ 6a0:	3d          	pushspadd
+ 6a1:	0d          	popsp
+ 6a2:	80          	im 0
+ 6a3:	0b          	nop
+ 6a4:	83          	im 3
+ 6a5:	e0          	im -32
+ 6a6:	8c          	im 12
+ 6a7:	08          	load
+ 6a8:	fc          	im -4
+ 6a9:	05          	add
+ 6aa:	0c          	store
+ 6ab:	83          	im 3
+ 6ac:	e0          	im -32
+ 6ad:	8c          	im 12
+ 6ae:	08          	load
+ 6af:	88          	im 8
+ 6b0:	05          	add
+ 6b1:	08          	load
+ 6b2:	80          	im 0
+ 6b3:	25          	lessthanorequal
+ 6b4:	b9          	im 57
+ 6b5:	38          	neqbranch
+ 6b6:	83          	im 3
+ 6b7:	e0          	im -32
+ 6b8:	8c          	im 12
+ 6b9:	08          	load
+ 6ba:	88          	im 8
+ 6bb:	05          	add
+ 6bc:	08          	load
+ 6bd:	30          	neg
+ 6be:	83          	im 3
+ 6bf:	e0          	im -32
+ 6c0:	8c          	im 12
+ 6c1:	08          	load
+ 6c2:	88          	im 8
+ 6c3:	05          	add
+ 6c4:	0c          	store
+ 6c5:	80          	im 0
+ 6c6:	0b          	nop
+ 6c7:	83          	im 3
+ 6c8:	e0          	im -32
+ 6c9:	8c          	im 12
+ 6ca:	08          	load
+ 6cb:	f4          	im -12
+ 6cc:	05          	add
+ 6cd:	0c          	store
+ 6ce:	83          	im 3
+ 6cf:	e0          	im -32
+ 6d0:	8c          	im 12
+ 6d1:	08          	load
+ 6d2:	fc          	im -4
+ 6d3:	05          	add
+ 6d4:	08          	load
+ 6d5:	8a          	im 10
+ 6d6:	38          	neqbranch
+ 6d7:	81          	im 1
+ 6d8:	0b          	nop
+ 6d9:	83          	im 3
+ 6da:	e0          	im -32
+ 6db:	8c          	im 12
+ 6dc:	08          	load
+ 6dd:	f4          	im -12
+ 6de:	05          	add
+ 6df:	0c          	store
+
+000006e0 <.L3>:
+ 6e0:	83          	im 3
+ 6e1:	e0          	im -32
+ 6e2:	8c          	im 12
+ 6e3:	08          	load
+ 6e4:	f4          	im -12
+ 6e5:	05          	add
+ 6e6:	08          	load
+ 6e7:	83          	im 3
+ 6e8:	e0          	im -32
+ 6e9:	8c          	im 12
+ 6ea:	08          	load
+ 6eb:	fc          	im -4
+ 6ec:	05          	add
+ 6ed:	0c          	store
+
+000006ee <.L2>:
+ 6ee:	83          	im 3
+ 6ef:	e0          	im -32
+ 6f0:	8c          	im 12
+ 6f1:	08          	load
+ 6f2:	8c          	im 12
+ 6f3:	05          	add
+ 6f4:	08          	load
+ 6f5:	80          	im 0
+ 6f6:	25          	lessthanorequal
+ 6f7:	b9          	im 57
+ 6f8:	38          	neqbranch
+ 6f9:	83          	im 3
+ 6fa:	e0          	im -32
+ 6fb:	8c          	im 12
+ 6fc:	08          	load
+ 6fd:	8c          	im 12
+ 6fe:	05          	add
+ 6ff:	08          	load
+ 700:	30          	neg
+ 701:	83          	im 3
+ 702:	e0          	im -32
+ 703:	8c          	im 12
+ 704:	08          	load
+ 705:	8c          	im 12
+ 706:	05          	add
+ 707:	0c          	store
+ 708:	80          	im 0
+ 709:	0b          	nop
+ 70a:	83          	im 3
+ 70b:	e0          	im -32
+ 70c:	8c          	im 12
+ 70d:	08          	load
+ 70e:	f0          	im -16
+ 70f:	05          	add
+ 710:	0c          	store
+ 711:	83          	im 3
+ 712:	e0          	im -32
+ 713:	8c          	im 12
+ 714:	08          	load
+ 715:	fc          	im -4
+ 716:	05          	add
+ 717:	08          	load
+ 718:	8a          	im 10
+ 719:	38          	neqbranch
+ 71a:	81          	im 1
+ 71b:	0b          	nop
+ 71c:	83          	im 3
+ 71d:	e0          	im -32
+ 71e:	8c          	im 12
+ 71f:	08          	load
+ 720:	f0          	im -16
+ 721:	05          	add
+ 722:	0c          	store
+
+00000723 <.L5>:
+ 723:	83          	im 3
+ 724:	e0          	im -32
+ 725:	8c          	im 12
+ 726:	08          	load
+ 727:	f0          	im -16
+ 728:	05          	add
+ 729:	08          	load
+ 72a:	83          	im 3
+ 72b:	e0          	im -32
+ 72c:	8c          	im 12
+ 72d:	08          	load
+ 72e:	fc          	im -4
+ 72f:	05          	add
+ 730:	0c          	store
+
+00000731 <.L4>:
+ 731:	80          	im 0
+ 732:	53          	storesp 12
+ 733:	83          	im 3
+ 734:	e0          	im -32
+ 735:	8c          	im 12
+ 736:	08          	load
+ 737:	8c          	im 12
+ 738:	05          	add
+ 739:	08          	load
+ 73a:	52          	storesp 8
+ 73b:	83          	im 3
+ 73c:	e0          	im -32
+ 73d:	8c          	im 12
+ 73e:	08          	load
+ 73f:	88          	im 8
+ 740:	05          	add
+ 741:	08          	load
+ 742:	51          	storesp 4
+ 743:	81          	im 1
+ 744:	df          	im -33
+ 745:	3f          	callpcrel
+ 746:	83          	im 3
+ 747:	e0          	im -32
+ 748:	80          	im 0
+ 749:	08          	load
+ 74a:	70          	loadsp 0
+ 74b:	83          	im 3
+ 74c:	e0          	im -32
+ 74d:	8c          	im 12
+ 74e:	08          	load
+ 74f:	f8          	im -8
+ 750:	05          	add
+ 751:	0c          	store
+ 752:	54          	storesp 16
+ 753:	83          	im 3
+ 754:	e0          	im -32
+ 755:	8c          	im 12
+ 756:	08          	load
+ 757:	fc          	im -4
+ 758:	05          	add
+ 759:	08          	load
+ 75a:	80          	im 0
+ 75b:	2e          	eq
+ 75c:	90          	im 16
+ 75d:	38          	neqbranch
+ 75e:	83          	im 3
+ 75f:	e0          	im -32
+ 760:	8c          	im 12
+ 761:	08          	load
+ 762:	f8          	im -8
+ 763:	05          	add
+ 764:	08          	load
+ 765:	30          	neg
+ 766:	83          	im 3
+ 767:	e0          	im -32
+ 768:	8c          	im 12
+ 769:	08          	load
+ 76a:	f8          	im -8
+ 76b:	05          	add
+ 76c:	0c          	store
+
+0000076d <.L6>:
+ 76d:	83          	im 3
+ 76e:	e0          	im -32
+ 76f:	8c          	im 12
+ 770:	08          	load
+ 771:	f8          	im -8
+ 772:	05          	add
+ 773:	08          	load
+ 774:	70          	loadsp 0
+ 775:	83          	im 3
+ 776:	e0          	im -32
+ 777:	80          	im 0
+ 778:	0c          	store
+ 779:	54          	storesp 16
+ 77a:	89          	im 9
+ 77b:	3d          	pushspadd
+ 77c:	0d          	popsp
+ 77d:	83          	im 3
+ 77e:	e0          	im -32
+ 77f:	8c          	im 12
+ 780:	0c          	store
+ 781:	04          	poppc
+
+00000782 <__modsi3>:
+ 782:	83          	im 3
+ 783:	e0          	im -32
+ 784:	8c          	im 12
+ 785:	08          	load
+ 786:	02          	pushsp
+ 787:	83          	im 3
+ 788:	e0          	im -32
+ 789:	8c          	im 12
+ 78a:	0c          	store
+ 78b:	fb          	im -5
+ 78c:	3d          	pushspadd
+ 78d:	0d          	popsp
+ 78e:	80          	im 0
+ 78f:	0b          	nop
+ 790:	83          	im 3
+ 791:	e0          	im -32
+ 792:	8c          	im 12
+ 793:	08          	load
+ 794:	fc          	im -4
+ 795:	05          	add
+ 796:	0c          	store
+ 797:	83          	im 3
+ 798:	e0          	im -32
+ 799:	8c          	im 12
+ 79a:	08          	load
+ 79b:	88          	im 8
+ 79c:	05          	add
+ 79d:	08          	load
+ 79e:	80          	im 0
+ 79f:	25          	lessthanorequal
+ 7a0:	99          	im 25
+ 7a1:	38          	neqbranch
+ 7a2:	83          	im 3
+ 7a3:	e0          	im -32
+ 7a4:	8c          	im 12
+ 7a5:	08          	load
+ 7a6:	88          	im 8
+ 7a7:	05          	add
+ 7a8:	08          	load
+ 7a9:	30          	neg
+ 7aa:	83          	im 3
+ 7ab:	e0          	im -32
+ 7ac:	8c          	im 12
+ 7ad:	08          	load
+ 7ae:	88          	im 8
+ 7af:	05          	add
+ 7b0:	0c          	store
+ 7b1:	81          	im 1
+ 7b2:	0b          	nop
+ 7b3:	83          	im 3
+ 7b4:	e0          	im -32
+ 7b5:	8c          	im 12
+ 7b6:	08          	load
+ 7b7:	fc          	im -4
+ 7b8:	05          	add
+ 7b9:	0c          	store
+
+000007ba <.L8>:
+ 7ba:	83          	im 3
+ 7bb:	e0          	im -32
+ 7bc:	8c          	im 12
+ 7bd:	08          	load
+ 7be:	8c          	im 12
+ 7bf:	05          	add
+ 7c0:	08          	load
+ 7c1:	80          	im 0
+ 7c2:	25          	lessthanorequal
+ 7c3:	90          	im 16
+ 7c4:	38          	neqbranch
+ 7c5:	83          	im 3
+ 7c6:	e0          	im -32
+ 7c7:	8c          	im 12
+ 7c8:	08          	load
+ 7c9:	8c          	im 12
+ 7ca:	05          	add
+ 7cb:	08          	load
+ 7cc:	30          	neg
+ 7cd:	83          	im 3
+ 7ce:	e0          	im -32
+ 7cf:	8c          	im 12
+ 7d0:	08          	load
+ 7d1:	8c          	im 12
+ 7d2:	05          	add
+ 7d3:	0c          	store
+
+000007d4 <.L9>:
+ 7d4:	81          	im 1
+ 7d5:	53          	storesp 12
+ 7d6:	83          	im 3
+ 7d7:	e0          	im -32
+ 7d8:	8c          	im 12
+ 7d9:	08          	load
+ 7da:	8c          	im 12
+ 7db:	05          	add
+ 7dc:	08          	load
+ 7dd:	52          	storesp 8
+ 7de:	83          	im 3
+ 7df:	e0          	im -32
+ 7e0:	8c          	im 12
+ 7e1:	08          	load
+ 7e2:	88          	im 8
+ 7e3:	05          	add
+ 7e4:	08          	load
+ 7e5:	51          	storesp 4
+ 7e6:	bd          	im 61
+ 7e7:	3f          	callpcrel
+ 7e8:	83          	im 3
+ 7e9:	e0          	im -32
+ 7ea:	80          	im 0
+ 7eb:	08          	load
+ 7ec:	70          	loadsp 0
+ 7ed:	83          	im 3
+ 7ee:	e0          	im -32
+ 7ef:	8c          	im 12
+ 7f0:	08          	load
+ 7f1:	f8          	im -8
+ 7f2:	05          	add
+ 7f3:	0c          	store
+ 7f4:	54          	storesp 16
+ 7f5:	83          	im 3
+ 7f6:	e0          	im -32
+ 7f7:	8c          	im 12
+ 7f8:	08          	load
+ 7f9:	fc          	im -4
+ 7fa:	05          	add
+ 7fb:	08          	load
+ 7fc:	80          	im 0
+ 7fd:	2e          	eq
+ 7fe:	90          	im 16
+ 7ff:	38          	neqbranch
+ 800:	83          	im 3
+ 801:	e0          	im -32
+ 802:	8c          	im 12
+ 803:	08          	load
+ 804:	f8          	im -8
+ 805:	05          	add
+ 806:	08          	load
+ 807:	30          	neg
+ 808:	83          	im 3
+ 809:	e0          	im -32
+ 80a:	8c          	im 12
+ 80b:	08          	load
+ 80c:	f8          	im -8
+ 80d:	05          	add
+ 80e:	0c          	store
+
+0000080f <.L10>:
+ 80f:	83          	im 3
+ 810:	e0          	im -32
+ 811:	8c          	im 12
+ 812:	08          	load
+ 813:	f8          	im -8
+ 814:	05          	add
+ 815:	08          	load
+ 816:	70          	loadsp 0
+ 817:	83          	im 3
+ 818:	e0          	im -32
+ 819:	80          	im 0
+ 81a:	0c          	store
+ 81b:	54          	storesp 16
+ 81c:	87          	im 7
+ 81d:	3d          	pushspadd
+ 81e:	0d          	popsp
+ 81f:	83          	im 3
+ 820:	e0          	im -32
+ 821:	8c          	im 12
+ 822:	0c          	store
+ 823:	04          	poppc
+
+00000824 <udivmodsi4>:
+ 824:	83          	im 3
+ 825:	e0          	im -32
+ 826:	8c          	im 12
+ 827:	08          	load
+ 828:	02          	pushsp
+ 829:	83          	im 3
+ 82a:	e0          	im -32
+ 82b:	8c          	im 12
+ 82c:	0c          	store
+ 82d:	fd          	im -3
+ 82e:	3d          	pushspadd
+ 82f:	0d          	popsp
+ 830:	81          	im 1
+ 831:	0b          	nop
+ 832:	83          	im 3
+ 833:	e0          	im -32
+ 834:	8c          	im 12
+ 835:	08          	load
+ 836:	fc          	im -4
+ 837:	05          	add
+ 838:	0c          	store
+ 839:	80          	im 0
+ 83a:	0b          	nop
+ 83b:	83          	im 3
+ 83c:	e0          	im -32
+ 83d:	8c          	im 12
+ 83e:	08          	load
+ 83f:	f8          	im -8
+ 840:	05          	add
+ 841:	0c          	store
+
+00000842 <.L2>:
+ 842:	83          	im 3
+ 843:	e0          	im -32
+ 844:	8c          	im 12
+ 845:	08          	load
+ 846:	8c          	im 12
+ 847:	05          	add
+ 848:	08          	load
+ 849:	83          	im 3
+ 84a:	e0          	im -32
+ 84b:	8c          	im 12
+ 84c:	08          	load
+ 84d:	88          	im 8
+ 84e:	05          	add
+ 84f:	08          	load
+ 850:	27          	ulessthanorequal
+ 851:	b9          	im 57
+ 852:	38          	neqbranch
+ 853:	83          	im 3
+ 854:	e0          	im -32
+ 855:	8c          	im 12
+ 856:	08          	load
+ 857:	fc          	im -4
+ 858:	05          	add
+ 859:	08          	load
+ 85a:	80          	im 0
+ 85b:	2e          	eq
+ 85c:	ae          	im 46
+ 85d:	38          	neqbranch
+ 85e:	80          	im 0
+ 85f:	0b          	nop
+ 860:	83          	im 3
+ 861:	e0          	im -32
+ 862:	8c          	im 12
+ 863:	08          	load
+ 864:	8c          	im 12
+ 865:	05          	add
+ 866:	08          	load
+ 867:	24          	lessthan
+ 868:	a2          	im 34
+ 869:	38          	neqbranch
+ 86a:	83          	im 3
+ 86b:	e0          	im -32
+ 86c:	8c          	im 12
+ 86d:	08          	load
+ 86e:	8c          	im 12
+ 86f:	05          	add
+ 870:	08          	load
+ 871:	10          	addsp 0
+ 872:	83          	im 3
+ 873:	e0          	im -32
+ 874:	8c          	im 12
+ 875:	08          	load
+ 876:	8c          	im 12
+ 877:	05          	add
+ 878:	0c          	store
+ 879:	83          	im 3
+ 87a:	e0          	im -32
+ 87b:	8c          	im 12
+ 87c:	08          	load
+ 87d:	fc          	im -4
+ 87e:	05          	add
+ 87f:	08          	load
+ 880:	10          	addsp 0
+ 881:	83          	im 3
+ 882:	e0          	im -32
+ 883:	8c          	im 12
+ 884:	08          	load
+ 885:	fc          	im -4
+ 886:	05          	add
+ 887:	0c          	store
+ 888:	ff          	im -1
+ 889:	b8          	im 56
+ 88a:	39          	poppcrel
+
+0000088b <.L4>:
+ 88b:	83          	im 3
+ 88c:	e0          	im -32
+ 88d:	8c          	im 12
+ 88e:	08          	load
+ 88f:	fc          	im -4
+ 890:	05          	add
+ 891:	08          	load
+ 892:	80          	im 0
+ 893:	2e          	eq
+ 894:	80          	im 0
+ 895:	e1          	im -31
+ 896:	38          	neqbranch
+ 897:	83          	im 3
+ 898:	e0          	im -32
+ 899:	8c          	im 12
+ 89a:	08          	load
+ 89b:	8c          	im 12
+ 89c:	05          	add
+ 89d:	08          	load
+ 89e:	83          	im 3
+ 89f:	e0          	im -32
+ 8a0:	8c          	im 12
+ 8a1:	08          	load
+ 8a2:	88          	im 8
+ 8a3:	05          	add
+ 8a4:	08          	load
+ 8a5:	26          	ulessthan
+ 8a6:	ad          	im 45
+ 8a7:	38          	neqbranch
+ 8a8:	83          	im 3
+ 8a9:	e0          	im -32
+ 8aa:	8c          	im 12
+ 8ab:	08          	load
+ 8ac:	88          	im 8
+ 8ad:	05          	add
+ 8ae:	08          	load
+ 8af:	83          	im 3
+ 8b0:	e0          	im -32
+ 8b1:	8c          	im 12
+ 8b2:	08          	load
+ 8b3:	8c          	im 12
+ 8b4:	05          	add
+ 8b5:	08          	load
+ 8b6:	31          	sub
+ 8b7:	83          	im 3
+ 8b8:	e0          	im -32
+ 8b9:	8c          	im 12
+ 8ba:	08          	load
+ 8bb:	88          	im 8
+ 8bc:	05          	add
+ 8bd:	0c          	store
+ 8be:	83          	im 3
+ 8bf:	e0          	im -32
+ 8c0:	8c          	im 12
+ 8c1:	08          	load
+ 8c2:	f8          	im -8
+ 8c3:	05          	add
+ 8c4:	08          	load
+ 8c5:	83          	im 3
+ 8c6:	e0          	im -32
+ 8c7:	8c          	im 12
+ 8c8:	08          	load
+ 8c9:	fc          	im -4
+ 8ca:	05          	add
+ 8cb:	08          	load
+ 8cc:	07          	or
+ 8cd:	83          	im 3
+ 8ce:	e0          	im -32
+ 8cf:	8c          	im 12
+ 8d0:	08          	load
+ 8d1:	f8          	im -8
+ 8d2:	05          	add
+ 8d3:	0c          	store
+
+000008d4 <.L6>:
+ 8d4:	83          	im 3
+ 8d5:	e0          	im -32
+ 8d6:	8c          	im 12
+ 8d7:	08          	load
+ 8d8:	fc          	im -4
+ 8d9:	05          	add
+ 8da:	08          	load
+ 8db:	81          	im 1
+ 8dc:	2a          	lshiftright
+ 8dd:	83          	im 3
+ 8de:	e0          	im -32
+ 8df:	8c          	im 12
+ 8e0:	08          	load
+ 8e1:	fc          	im -4
+ 8e2:	05          	add
+ 8e3:	0c          	store
+ 8e4:	83          	im 3
+ 8e5:	e0          	im -32
+ 8e6:	8c          	im 12
+ 8e7:	08          	load
+ 8e8:	8c          	im 12
+ 8e9:	05          	add
+ 8ea:	08          	load
+ 8eb:	81          	im 1
+ 8ec:	2a          	lshiftright
+ 8ed:	83          	im 3
+ 8ee:	e0          	im -32
+ 8ef:	8c          	im 12
+ 8f0:	08          	load
+ 8f1:	8c          	im 12
+ 8f2:	05          	add
+ 8f3:	0c          	store
+ 8f4:	ff          	im -1
+ 8f5:	95          	im 21
+ 8f6:	39          	poppcrel
+
+000008f7 <.L5>:
+ 8f7:	83          	im 3
+ 8f8:	e0          	im -32
+ 8f9:	8c          	im 12
+ 8fa:	08          	load
+ 8fb:	90          	im 16
+ 8fc:	05          	add
+ 8fd:	08          	load
+ 8fe:	80          	im 0
+ 8ff:	2e          	eq
+ 900:	93          	im 19
+ 901:	38          	neqbranch
+ 902:	83          	im 3
+ 903:	e0          	im -32
+ 904:	8c          	im 12
+ 905:	08          	load
+ 906:	88          	im 8
+ 907:	05          	add
+ 908:	08          	load
+ 909:	70          	loadsp 0
+ 90a:	83          	im 3
+ 90b:	e0          	im -32
+ 90c:	8c          	im 12
+ 90d:	08          	load
+ 90e:	f4          	im -12
+ 90f:	05          	add
+ 910:	0c          	store
+ 911:	51          	storesp 4
+ 912:	91          	im 17
+ 913:	39          	poppcrel
+
+00000914 <.L7>:
+ 914:	83          	im 3
+ 915:	e0          	im -32
+ 916:	8c          	im 12
+ 917:	08          	load
+ 918:	f8          	im -8
+ 919:	05          	add
+ 91a:	08          	load
+ 91b:	70          	loadsp 0
+ 91c:	83          	im 3
+ 91d:	e0          	im -32
+ 91e:	8c          	im 12
+ 91f:	08          	load
+ 920:	f4          	im -12
+ 921:	05          	add
+ 922:	0c          	store
+ 923:	51          	storesp 4
+
+00000924 <.L1>:
+ 924:	83          	im 3
+ 925:	e0          	im -32
+ 926:	8c          	im 12
+ 927:	08          	load
+ 928:	f4          	im -12
+ 929:	05          	add
+ 92a:	08          	load
+ 92b:	83          	im 3
+ 92c:	e0          	im -32
+ 92d:	80          	im 0
+ 92e:	0c          	store
+ 92f:	85          	im 5
+ 930:	3d          	pushspadd
+ 931:	0d          	popsp
+ 932:	83          	im 3
+ 933:	e0          	im -32
+ 934:	8c          	im 12
+ 935:	0c          	store
+ 936:	04          	poppc
+Disassembly of section .rodata:
+
+00000938 <_mask>:
+ 938:	00          	breakpoint
+ 939:	ff          	im -1
+ 93a:	ff          	im -1
+ 93b:	ff          	im -1
+ 93c:	ff          	im -1
+ 93d:	00          	breakpoint
+ 93e:	ff          	im -1
+ 93f:	ff          	im -1
+ 940:	ff          	im -1
+ 941:	ff          	im -1
+ 942:	00          	breakpoint
+ 943:	ff          	im -1
+ 944:	ff          	im -1
+ 945:	ff          	im -1
+ 946:	ff          	im -1
+	...
+Disassembly of section .data:
+
+00000948 <_data>:
+ 948:	00          	breakpoint
+ 949:	00          	breakpoint
+	...
+
+0000094c <_cpu_config>:
+ 94c:	00          	breakpoint
+ 94d:	00          	breakpoint
+	...
+
+00000950 <zpu_config>:
+ 950:	00          	breakpoint
+ 951:	04          	poppc
+	...
+
+00000954 <zpu_pause>:
+ 954:	00          	breakpoint
+ 955:	04          	poppc
+ 956:	00          	breakpoint
+ 957:	04          	poppc
+
+00000958 <zpu_switches>:
+ 958:	00          	breakpoint
+ 959:	04          	poppc
+ 95a:	00          	breakpoint
+ 95b:	08          	load
+
+0000095c <zpu_key>:
+ 95c:	00          	breakpoint
+ 95d:	04          	poppc
+ 95e:	00          	breakpoint
+ 95f:	0c          	store
+
+00000960 <zpu_ledg>:
+ 960:	00          	breakpoint
+ 961:	04          	poppc
+ 962:	00          	breakpoint
+ 963:	10          	addsp 0
+
+00000964 <zpu_ledr>:
+ 964:	00          	breakpoint
+ 965:	04          	poppc
+ 966:	00          	breakpoint
+ 967:	14          	addsp 16
+
+00000968 <zpu_spi_data>:
+ 968:	00          	breakpoint
+ 969:	04          	poppc
+ 96a:	00          	breakpoint
+ 96b:	18          	addsp 32
+
+0000096c <zpu_spi_state>:
+ 96c:	00          	breakpoint
+ 96d:	04          	poppc
+ 96e:	00          	breakpoint
+ 96f:	1c          	addsp 48
+
+00000970 <zpu_sio>:
+ 970:	00          	breakpoint
+ 971:	04          	poppc
+ 972:	00          	breakpoint
+ 973:	20          	.byte 32
+
+00000974 <zpu_board>:
+ 974:	00          	breakpoint
+ 975:	04          	poppc
+ 976:	00          	breakpoint
+ 977:	24          	lessthan
+
+00000978 <zpu_hex>:
+ 978:	00          	breakpoint
+ 979:	04          	poppc
+ 97a:	00          	breakpoint
+ 97b:	28          	swap
+
+0000097c <zpu_sector>:
+ 97c:	00          	breakpoint
+ 97d:	04          	poppc
+ 97e:	00          	breakpoint
+ 97f:	2c          	ashiftright
+
+00000980 <zpu_pokey_audf0>:
+ 980:	00          	breakpoint
+ 981:	04          	poppc
+ 982:	00          	breakpoint
+ 983:	40          	storesp 64
+
+00000984 <zpu_pokey_audc0>:
+ 984:	00          	breakpoint
+ 985:	04          	poppc
+ 986:	00          	breakpoint
+ 987:	44          	storesp 80
+
+00000988 <zpu_pokey_audf1>:
+ 988:	00          	breakpoint
+ 989:	04          	poppc
+ 98a:	00          	breakpoint
+ 98b:	48          	storesp 96
+
+0000098c <zpu_pokey_audc1>:
+ 98c:	00          	breakpoint
+ 98d:	04          	poppc
+ 98e:	00          	breakpoint
+ 98f:	4c          	storesp 112
+
+00000990 <zpu_pokey_audf2>:
+ 990:	00          	breakpoint
+ 991:	04          	poppc
+ 992:	00          	breakpoint
+ 993:	50          	storesp 0
+
+00000994 <zpu_pokey_audc2>:
+ 994:	00          	breakpoint
+ 995:	04          	poppc
+ 996:	00          	breakpoint
+ 997:	54          	storesp 16
+
+00000998 <zpu_pokey_audf3>:
+ 998:	00          	breakpoint
+ 999:	04          	poppc
+ 99a:	00          	breakpoint
+ 99b:	58          	storesp 32
+
+0000099c <zpu_pokey_audc3>:
+ 99c:	00          	breakpoint
+ 99d:	04          	poppc
+ 99e:	00          	breakpoint
+ 99f:	5c          	storesp 48
+
+000009a0 <zpu_pokey_audctl>:
+ 9a0:	00          	breakpoint
+ 9a1:	04          	poppc
+ 9a2:	00          	breakpoint
+ 9a3:	60          	loadsp 64
+
+000009a4 <zpu_pokey_skrest>:
+ 9a4:	00          	breakpoint
+ 9a5:	04          	poppc
+ 9a6:	00          	breakpoint
+ 9a7:	68          	loadsp 96
+
+000009a8 <zpu_pokey_serout>:
+ 9a8:	00          	breakpoint
+ 9a9:	04          	poppc
+ 9aa:	00          	breakpoint
+ 9ab:	74          	loadsp 16
+
+000009ac <zpu_pokey_irqen>:
+ 9ac:	00          	breakpoint
+ 9ad:	04          	poppc
+ 9ae:	00          	breakpoint
+ 9af:	78          	loadsp 32
+
+000009b0 <zpu_pokey_skctl>:
+ 9b0:	00          	breakpoint
+ 9b1:	04          	poppc
+ 9b2:	00          	breakpoint
+ 9b3:	7c          	loadsp 48
+
+000009b4 <atari_nmien>:
+ 9b4:	00          	breakpoint
+ 9b5:	01          	.byte 1
+ 9b6:	d4          	im -44
+ 9b7:	0e          	.byte 14
+
+000009b8 <atari_dlistl>:
+ 9b8:	00          	breakpoint
+ 9b9:	01          	.byte 1
+ 9ba:	d4          	im -44
+ 9bb:	02          	pushsp
+
+000009bc <atari_dlisth>:
+ 9bc:	00          	breakpoint
+ 9bd:	01          	.byte 1
+ 9be:	d4          	im -44
+ 9bf:	03          	.byte 3
+
+000009c0 <atari_colbk>:
+ 9c0:	00          	breakpoint
+ 9c1:	01          	.byte 1
+ 9c2:	d0          	im -48
+ 9c3:	1a          	addsp 40
+
+000009c4 <atari_colpf1>:
+ 9c4:	00          	breakpoint
+ 9c5:	01          	.byte 1
+ 9c6:	d0          	im -48
+ 9c7:	17          	addsp 28
+
+000009c8 <atari_colpf2>:
+ 9c8:	00          	breakpoint
+ 9c9:	01          	.byte 1
+ 9ca:	d0          	im -48
+ 9cb:	18          	addsp 32
+
+000009cc <atari_prior>:
+ 9cc:	00          	breakpoint
+ 9cd:	01          	.byte 1
+ 9ce:	d0          	im -48
+ 9cf:	1b          	addsp 44
+
+000009d0 <atari_random>:
+ 9d0:	00          	breakpoint
+ 9d1:	01          	.byte 1
+ 9d2:	d2          	im -46
+ 9d3:	0a          	flip
+
+000009d4 <atari_porta>:
+ 9d4:	00          	breakpoint
+ 9d5:	01          	.byte 1
+ 9d6:	d3          	im -45
+	...
+
+000009d8 <atari_portb>:
+ 9d8:	00          	breakpoint
+ 9d9:	01          	.byte 1
+ 9da:	d3          	im -45
+ 9db:	01          	.byte 1
+
+000009dc <atari_trig0>:
+ 9dc:	00          	breakpoint
+ 9dd:	01          	.byte 1
+ 9de:	d0          	im -48
+ 9df:	10          	addsp 0
+
+000009e0 <atari_chbase>:
+ 9e0:	00          	breakpoint
+ 9e1:	01          	.byte 1
+ 9e2:	d4          	im -44
+ 9e3:	09          	not
+
+000009e4 <atari_chactl>:
+ 9e4:	00          	breakpoint
+ 9e5:	01          	.byte 1
+ 9e6:	d4          	im -44
+ 9e7:	01          	.byte 1
+
+000009e8 <atari_dmactl>:
+ 9e8:	00          	breakpoint
+ 9e9:	01          	.byte 1
+ 9ea:	d4          	im -44
+	...
+
+000009ec <atari_skctl>:
+ 9ec:	00          	breakpoint
+ 9ed:	01          	.byte 1
+ 9ee:	d2          	im -46
+ 9ef:	0f          	.byte 15
+Disassembly of section .bss:
+
+0000f000 <__bss_start>:
+	...
+Disassembly of section .debug_abbrev:
+
+00000000 <.Ldebug_abbrev0>:
+   0:	01          	.byte 1
+   1:	11          	addsp 4
+   2:	01          	.byte 1
+   3:	10          	addsp 0
+   4:	06          	and
+   5:	12          	addsp 8
+   6:	01          	.byte 1
+   7:	11          	addsp 4
+   8:	01          	.byte 1
+   9:	25          	lessthanorequal
+   a:	08          	load
+   b:	13          	addsp 12
+   c:	0b          	nop
+   d:	03          	.byte 3
+   e:	08          	load
+   f:	1b          	addsp 44
+  10:	08          	load
+  11:	00          	breakpoint
+  12:	00          	breakpoint
+  13:	02          	pushsp
+  14:	2e          	eq
+  15:	01          	.byte 1
+  16:	01          	.byte 1
+  17:	13          	addsp 12
+  18:	3f          	callpcrel
+  19:	0c          	store
+  1a:	03          	.byte 3
+  1b:	08          	load
+  1c:	3a          	config
+  1d:	0b          	nop
+  1e:	3b          	pushpc
+  1f:	0b          	nop
+  20:	27          	ulessthanorequal
+  21:	0c          	store
+  22:	11          	addsp 4
+  23:	01          	.byte 1
+  24:	12          	addsp 8
+  25:	01          	.byte 1
+  26:	40          	storesp 64
+  27:	0a          	flip
+  28:	00          	breakpoint
+  29:	00          	breakpoint
+  2a:	03          	.byte 3
+  2b:	05          	add
+  2c:	00          	breakpoint
+  2d:	03          	.byte 3
+  2e:	08          	load
+  2f:	3a          	config
+  30:	0b          	nop
+  31:	3b          	pushpc
+  32:	0b          	nop
+  33:	49          	storesp 100
+  34:	13          	addsp 12
+  35:	02          	pushsp
+  36:	0a          	flip
+  37:	00          	breakpoint
+  38:	00          	breakpoint
+  39:	04          	poppc
+  3a:	34          	storeb
+  3b:	00          	breakpoint
+  3c:	03          	.byte 3
+  3d:	08          	load
+  3e:	3a          	config
+  3f:	0b          	nop
+  40:	3b          	pushpc
+  41:	0b          	nop
+  42:	49          	storesp 100
+  43:	13          	addsp 12
+  44:	02          	pushsp
+  45:	0a          	flip
+  46:	00          	breakpoint
+  47:	00          	breakpoint
+  48:	05          	add
+  49:	24          	lessthan
+  4a:	00          	breakpoint
+  4b:	03          	.byte 3
+  4c:	08          	load
+  4d:	0b          	nop
+  4e:	0b          	nop
+  4f:	3e          	halfmult
+  50:	0b          	nop
+  51:	00          	breakpoint
+  52:	00          	breakpoint
+  53:	06          	and
+  54:	2e          	eq
+  55:	01          	.byte 1
+  56:	01          	.byte 1
+  57:	13          	addsp 12
+  58:	3f          	callpcrel
+  59:	0c          	store
+  5a:	03          	.byte 3
+  5b:	08          	load
+  5c:	3a          	config
+  5d:	0b          	nop
+  5e:	3b          	pushpc
+  5f:	0b          	nop
+  60:	11          	addsp 4
+  61:	01          	.byte 1
+  62:	12          	addsp 8
+  63:	01          	.byte 1
+  64:	40          	storesp 64
+  65:	0a          	flip
+  66:	00          	breakpoint
+  67:	00          	breakpoint
+  68:	07          	or
+  69:	2e          	eq
+  6a:	01          	.byte 1
+  6b:	01          	.byte 1
+  6c:	13          	addsp 12
+  6d:	3f          	callpcrel
+  6e:	0c          	store
+  6f:	03          	.byte 3
+  70:	08          	load
+  71:	3a          	config
+  72:	0b          	nop
+  73:	3b          	pushpc
+  74:	0b          	nop
+  75:	27          	ulessthanorequal
+  76:	0c          	store
+  77:	49          	storesp 100
+  78:	13          	addsp 12
+  79:	11          	addsp 4
+  7a:	01          	.byte 1
+  7b:	12          	addsp 8
+  7c:	01          	.byte 1
+  7d:	40          	storesp 64
+  7e:	0a          	flip
+  7f:	00          	breakpoint
+  80:	00          	breakpoint
+  81:	08          	load
+  82:	34          	storeb
+  83:	00          	breakpoint
+  84:	03          	.byte 3
+  85:	08          	load
+  86:	3a          	config
+  87:	0b          	nop
+  88:	3b          	pushpc
+  89:	0b          	nop
+  8a:	49          	storesp 100
+  8b:	13          	addsp 12
+  8c:	3f          	callpcrel
+  8d:	0c          	store
+  8e:	3c          	syscall
+  8f:	0c          	store
+  90:	00          	breakpoint
+  91:	00          	breakpoint
+  92:	09          	not
+  93:	0f          	.byte 15
+  94:	00          	breakpoint
+  95:	0b          	nop
+  96:	0b          	nop
+  97:	49          	storesp 100
+  98:	13          	addsp 12
+  99:	00          	breakpoint
+  9a:	00          	breakpoint
+  9b:	0a          	flip
+  9c:	35          	div
+  9d:	00          	breakpoint
+  9e:	49          	storesp 100
+  9f:	13          	addsp 12
+  a0:	00          	breakpoint
+	...
+
+000000a3 <.Ldebug_abbrev0>:
+  a3:	01          	.byte 1
+  a4:	11          	addsp 4
+  a5:	01          	.byte 1
+  a6:	10          	addsp 0
+  a7:	06          	and
+  a8:	12          	addsp 8
+  a9:	01          	.byte 1
+  aa:	11          	addsp 4
+  ab:	01          	.byte 1
+  ac:	25          	lessthanorequal
+  ad:	08          	load
+  ae:	13          	addsp 12
+  af:	0b          	nop
+  b0:	03          	.byte 3
+  b1:	08          	load
+  b2:	1b          	addsp 44
+  b3:	08          	load
+  b4:	00          	breakpoint
+  b5:	00          	breakpoint
+  b6:	02          	pushsp
+  b7:	34          	storeb
+  b8:	00          	breakpoint
+  b9:	03          	.byte 3
+  ba:	08          	load
+  bb:	3a          	config
+  bc:	0b          	nop
+  bd:	3b          	pushpc
+  be:	0b          	nop
+  bf:	49          	storesp 100
+  c0:	13          	addsp 12
+  c1:	3f          	callpcrel
+  c2:	0c          	store
+  c3:	02          	pushsp
+  c4:	0a          	flip
+  c5:	00          	breakpoint
+  c6:	00          	breakpoint
+  c7:	03          	.byte 3
+  c8:	0f          	.byte 15
+  c9:	00          	breakpoint
+  ca:	0b          	nop
+  cb:	0b          	nop
+  cc:	49          	storesp 100
+  cd:	13          	addsp 12
+  ce:	00          	breakpoint
+  cf:	00          	breakpoint
+  d0:	04          	poppc
+  d1:	35          	div
+  d2:	00          	breakpoint
+  d3:	49          	storesp 100
+  d4:	13          	addsp 12
+  d5:	00          	breakpoint
+  d6:	00          	breakpoint
+  d7:	05          	add
+  d8:	24          	lessthan
+  d9:	00          	breakpoint
+  da:	03          	.byte 3
+  db:	08          	load
+  dc:	0b          	nop
+  dd:	0b          	nop
+  de:	3e          	halfmult
+  df:	0b          	nop
+  e0:	00          	breakpoint
+	...
+Disassembly of section .debug_info:
+
+00000000 <.Ldebug_info0>:
+   0:	00          	breakpoint
+   1:	00          	breakpoint
+   2:	02          	pushsp
+   3:	18          	addsp 32
+   4:	00          	breakpoint
+   5:	02          	pushsp
+   6:	00          	breakpoint
+   7:	00          	breakpoint
+   8:	00          	breakpoint
+   9:	00          	breakpoint
+   a:	04          	poppc
+   b:	01          	.byte 1
+   c:	00          	breakpoint
+   d:	00          	breakpoint
+   e:	00          	breakpoint
+   f:	00          	breakpoint
+  10:	00          	breakpoint
+  11:	00          	breakpoint
+  12:	06          	and
+  13:	96          	im 22
+  14:	00          	breakpoint
+  15:	00          	breakpoint
+  16:	04          	poppc
+  17:	b1          	im 49
+  18:	47          	storesp 92
+  19:	4e          	storesp 120
+  1a:	55          	storesp 20
+  1b:	20          	.byte 32
+  1c:	43          	storesp 76
+  1d:	20          	.byte 32
+  1e:	33          	loadb
+  1f:	2e          	eq
+  20:	34          	storeb
+  21:	2e          	eq
+  22:	32          	xor
+  23:	00          	breakpoint
+  24:	01          	.byte 1
+  25:	6d          	loadsp 116
+  26:	61          	loadsp 68
+  27:	69          	loadsp 100
+  28:	6e          	loadsp 120
+  29:	2e          	eq
+  2a:	63          	loadsp 76
+  2b:	00          	breakpoint
+  2c:	2f          	neq
+  2d:	68          	loadsp 96
+  2e:	6f          	loadsp 124
+  2f:	6d          	loadsp 116
+  30:	65          	loadsp 84
+  31:	2f          	neq
+  32:	6d          	loadsp 116
+  33:	61          	loadsp 68
+  34:	72          	loadsp 8
+  35:	6b          	loadsp 108
+  36:	77          	loadsp 28
+  37:	2f          	neq
+  38:	61          	loadsp 68
+  39:	6c          	loadsp 112
+  3a:	74          	loadsp 16
+  3b:	65          	loadsp 84
+  3c:	72          	loadsp 8
+  3d:	61          	loadsp 68
+  3e:	2f          	neq
+  3f:	61          	loadsp 68
+  40:	74          	loadsp 16
+  41:	61          	loadsp 68
+  42:	72          	loadsp 8
+  43:	69          	loadsp 100
+  44:	5f          	storesp 60
+  45:	78          	loadsp 32
+  46:	65          	loadsp 84
+  47:	5f          	storesp 60
+  48:	66          	loadsp 88
+  49:	70          	loadsp 0
+  4a:	67          	loadsp 92
+  4b:	61          	loadsp 68
+  4c:	2f          	neq
+  4d:	7a          	loadsp 40
+  4e:	70          	loadsp 0
+  4f:	75          	loadsp 20
+  50:	2f          	neq
+  51:	6c          	loadsp 112
+  52:	65          	loadsp 84
+  53:	64          	loadsp 80
+  54:	73          	loadsp 12
+  55:	5f          	storesp 60
+  56:	6e          	loadsp 120
+  57:	6f          	loadsp 124
+  58:	73          	loadsp 12
+  59:	64          	loadsp 80
+  5a:	72          	loadsp 8
+  5b:	69          	loadsp 100
+  5c:	76          	loadsp 24
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+	...
+
+0000021c <.Ldebug_info0>:
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+ 2e1:	00          	breakpoint
+ 2e2:	01          	.byte 1
+ 2e3:	08          	load
+ 2e4:	00          	breakpoint
+ 2e5:	00          	breakpoint
+ 2e6:	00          	breakpoint
+ 2e7:	78          	loadsp 32
+ 2e8:	01          	.byte 1
+ 2e9:	05          	add
+ 2ea:	03          	.byte 3
+ 2eb:	00          	breakpoint
+ 2ec:	00          	breakpoint
+ 2ed:	09          	not
+ 2ee:	5c          	storesp 48
+ 2ef:	02          	pushsp
+ 2f0:	7a          	loadsp 40
+ 2f1:	70          	loadsp 0
+ 2f2:	75          	loadsp 20
+ 2f3:	5f          	storesp 60
+ 2f4:	6c          	loadsp 112
+ 2f5:	65          	loadsp 84
+ 2f6:	64          	loadsp 80
+ 2f7:	67          	loadsp 92
+ 2f8:	00          	breakpoint
+ 2f9:	01          	.byte 1
+ 2fa:	09          	not
+ 2fb:	00          	breakpoint
+ 2fc:	00          	breakpoint
+ 2fd:	00          	breakpoint
+ 2fe:	78          	loadsp 32
+ 2ff:	01          	.byte 1
+ 300:	05          	add
+ 301:	03          	.byte 3
+ 302:	00          	breakpoint
+ 303:	00          	breakpoint
+ 304:	09          	not
+ 305:	60          	loadsp 64
+ 306:	02          	pushsp
+ 307:	7a          	loadsp 40
+ 308:	70          	loadsp 0
+ 309:	75          	loadsp 20
+ 30a:	5f          	storesp 60
+ 30b:	6c          	loadsp 112
+ 30c:	65          	loadsp 84
+ 30d:	64          	loadsp 80
+ 30e:	72          	loadsp 8
+ 30f:	00          	breakpoint
+ 310:	01          	.byte 1
+ 311:	0a          	flip
+ 312:	00          	breakpoint
+ 313:	00          	breakpoint
+ 314:	00          	breakpoint
+ 315:	78          	loadsp 32
+ 316:	01          	.byte 1
+ 317:	05          	add
+ 318:	03          	.byte 3
+ 319:	00          	breakpoint
+ 31a:	00          	breakpoint
+ 31b:	09          	not
+ 31c:	64          	loadsp 80
+ 31d:	02          	pushsp
+ 31e:	7a          	loadsp 40
+ 31f:	70          	loadsp 0
+ 320:	75          	loadsp 20
+ 321:	5f          	storesp 60
+ 322:	73          	loadsp 12
+ 323:	70          	loadsp 0
+ 324:	69          	loadsp 100
+ 325:	5f          	storesp 60
+ 326:	64          	loadsp 80
+ 327:	61          	loadsp 68
+ 328:	74          	loadsp 16
+ 329:	61          	loadsp 68
+ 32a:	00          	breakpoint
+ 32b:	01          	.byte 1
+ 32c:	0b          	nop
+ 32d:	00          	breakpoint
+ 32e:	00          	breakpoint
+ 32f:	00          	breakpoint
+ 330:	78          	loadsp 32
+ 331:	01          	.byte 1
+ 332:	05          	add
+ 333:	03          	.byte 3
+ 334:	00          	breakpoint
+ 335:	00          	breakpoint
+ 336:	09          	not
+ 337:	68          	loadsp 96
+ 338:	02          	pushsp
+ 339:	7a          	loadsp 40
+ 33a:	70          	loadsp 0
+ 33b:	75          	loadsp 20
+ 33c:	5f          	storesp 60
+ 33d:	73          	loadsp 12
+ 33e:	70          	loadsp 0
+ 33f:	69          	loadsp 100
+ 340:	5f          	storesp 60
+ 341:	73          	loadsp 12
+ 342:	74          	loadsp 16
+ 343:	61          	loadsp 68
+ 344:	74          	loadsp 16
+ 345:	65          	loadsp 84
+ 346:	00          	breakpoint
+ 347:	01          	.byte 1
+ 348:	0c          	store
+ 349:	00          	breakpoint
+ 34a:	00          	breakpoint
+ 34b:	00          	breakpoint
+ 34c:	78          	loadsp 32
+ 34d:	01          	.byte 1
+ 34e:	05          	add
+ 34f:	03          	.byte 3
+ 350:	00          	breakpoint
+ 351:	00          	breakpoint
+ 352:	09          	not
+ 353:	6c          	loadsp 112
+ 354:	02          	pushsp
+ 355:	7a          	loadsp 40
+ 356:	70          	loadsp 0
+ 357:	75          	loadsp 20
+ 358:	5f          	storesp 60
+ 359:	73          	loadsp 12
+ 35a:	69          	loadsp 100
+ 35b:	6f          	loadsp 124
+ 35c:	00          	breakpoint
+ 35d:	01          	.byte 1
+ 35e:	0d          	popsp
+ 35f:	00          	breakpoint
+ 360:	00          	breakpoint
+ 361:	00          	breakpoint
+ 362:	78          	loadsp 32
+ 363:	01          	.byte 1
+ 364:	05          	add
+ 365:	03          	.byte 3
+ 366:	00          	breakpoint
+ 367:	00          	breakpoint
+ 368:	09          	not
+ 369:	70          	loadsp 0
+ 36a:	02          	pushsp
+ 36b:	7a          	loadsp 40
+ 36c:	70          	loadsp 0
+ 36d:	75          	loadsp 20
+ 36e:	5f          	storesp 60
+ 36f:	62          	loadsp 72
+ 370:	6f          	loadsp 124
+ 371:	61          	loadsp 68
+ 372:	72          	loadsp 8
+ 373:	64          	loadsp 80
+ 374:	00          	breakpoint
+ 375:	01          	.byte 1
+ 376:	0e          	.byte 14
+ 377:	00          	breakpoint
+ 378:	00          	breakpoint
+ 379:	00          	breakpoint
+ 37a:	78          	loadsp 32
+ 37b:	01          	.byte 1
+ 37c:	05          	add
+ 37d:	03          	.byte 3
+ 37e:	00          	breakpoint
+ 37f:	00          	breakpoint
+ 380:	09          	not
+ 381:	74          	loadsp 16
+ 382:	02          	pushsp
+ 383:	7a          	loadsp 40
+ 384:	70          	loadsp 0
+ 385:	75          	loadsp 20
+ 386:	5f          	storesp 60
+ 387:	68          	loadsp 96
+ 388:	65          	loadsp 84
+ 389:	78          	loadsp 32
+ 38a:	00          	breakpoint
+ 38b:	01          	.byte 1
+ 38c:	0f          	.byte 15
+ 38d:	00          	breakpoint
+ 38e:	00          	breakpoint
+ 38f:	00          	breakpoint
+ 390:	78          	loadsp 32
+ 391:	01          	.byte 1
+ 392:	05          	add
+ 393:	03          	.byte 3
+ 394:	00          	breakpoint
+ 395:	00          	breakpoint
+ 396:	09          	not
+ 397:	78          	loadsp 32
+ 398:	02          	pushsp
+ 399:	7a          	loadsp 40
+ 39a:	70          	loadsp 0
+ 39b:	75          	loadsp 20
+ 39c:	5f          	storesp 60
+ 39d:	73          	loadsp 12
+ 39e:	65          	loadsp 84
+ 39f:	63          	loadsp 76
+ 3a0:	74          	loadsp 16
+ 3a1:	6f          	loadsp 124
+ 3a2:	72          	loadsp 8
+ 3a3:	00          	breakpoint
+ 3a4:	01          	.byte 1
+ 3a5:	10          	addsp 0
+ 3a6:	00          	breakpoint
+ 3a7:	00          	breakpoint
+ 3a8:	00          	breakpoint
+ 3a9:	78          	loadsp 32
+ 3aa:	01          	.byte 1
+ 3ab:	05          	add
+ 3ac:	03          	.byte 3
+ 3ad:	00          	breakpoint
+ 3ae:	00          	breakpoint
+ 3af:	09          	not
+ 3b0:	7c          	loadsp 48
+ 3b1:	02          	pushsp
+ 3b2:	7a          	loadsp 40
+ 3b3:	70          	loadsp 0
+ 3b4:	75          	loadsp 20
+ 3b5:	5f          	storesp 60
+ 3b6:	70          	loadsp 0
+ 3b7:	6f          	loadsp 124
+ 3b8:	6b          	loadsp 108
+ 3b9:	65          	loadsp 84
+ 3ba:	79          	loadsp 36
+ 3bb:	5f          	storesp 60
+ 3bc:	61          	loadsp 68
+ 3bd:	75          	loadsp 20
+ 3be:	64          	loadsp 80
+ 3bf:	66          	loadsp 88
+ 3c0:	30          	neg
+ 3c1:	00          	breakpoint
+ 3c2:	01          	.byte 1
+ 3c3:	12          	addsp 8
+ 3c4:	00          	breakpoint
+ 3c5:	00          	breakpoint
+ 3c6:	01          	.byte 1
+ 3c7:	b3          	im 51
+ 3c8:	01          	.byte 1
+ 3c9:	05          	add
+ 3ca:	03          	.byte 3
+ 3cb:	00          	breakpoint
+ 3cc:	00          	breakpoint
+ 3cd:	09          	not
+ 3ce:	80          	im 0
+ 3cf:	03          	.byte 3
+ 3d0:	04          	poppc
+ 3d1:	00          	breakpoint
+ 3d2:	00          	breakpoint
+ 3d3:	01          	.byte 1
+ 3d4:	b9          	im 57
+ 3d5:	04          	poppc
+ 3d6:	00          	breakpoint
+ 3d7:	00          	breakpoint
+ 3d8:	01          	.byte 1
+ 3d9:	be          	im 62
+ 3da:	05          	add
+ 3db:	75          	loadsp 20
+ 3dc:	6e          	loadsp 120
+ 3dd:	73          	loadsp 12
+ 3de:	69          	loadsp 100
+ 3df:	67          	loadsp 92
+ 3e0:	6e          	loadsp 120
+ 3e1:	65          	loadsp 84
+ 3e2:	64          	loadsp 80
+ 3e3:	20          	.byte 32
+ 3e4:	63          	loadsp 76
+ 3e5:	68          	loadsp 96
+ 3e6:	61          	loadsp 68
+ 3e7:	72          	loadsp 8
+ 3e8:	00          	breakpoint
+ 3e9:	01          	.byte 1
+ 3ea:	08          	load
+ 3eb:	02          	pushsp
+ 3ec:	7a          	loadsp 40
+ 3ed:	70          	loadsp 0
+ 3ee:	75          	loadsp 20
+ 3ef:	5f          	storesp 60
+ 3f0:	70          	loadsp 0
+ 3f1:	6f          	loadsp 124
+ 3f2:	6b          	loadsp 108
+ 3f3:	65          	loadsp 84
+ 3f4:	79          	loadsp 36
+ 3f5:	5f          	storesp 60
+ 3f6:	61          	loadsp 68
+ 3f7:	75          	loadsp 20
+ 3f8:	64          	loadsp 80
+ 3f9:	63          	loadsp 76
+ 3fa:	30          	neg
+ 3fb:	00          	breakpoint
+ 3fc:	01          	.byte 1
+ 3fd:	13          	addsp 12
+ 3fe:	00          	breakpoint
+ 3ff:	00          	breakpoint
+ 400:	01          	.byte 1
+ 401:	b3          	im 51
+ 402:	01          	.byte 1
+ 403:	05          	add
+ 404:	03          	.byte 3
+ 405:	00          	breakpoint
+ 406:	00          	breakpoint
+ 407:	09          	not
+ 408:	84          	im 4
+ 409:	02          	pushsp
+ 40a:	7a          	loadsp 40
+ 40b:	70          	loadsp 0
+ 40c:	75          	loadsp 20
+ 40d:	5f          	storesp 60
+ 40e:	70          	loadsp 0
+ 40f:	6f          	loadsp 124
+ 410:	6b          	loadsp 108
+ 411:	65          	loadsp 84
+ 412:	79          	loadsp 36
+ 413:	5f          	storesp 60
+ 414:	61          	loadsp 68
+ 415:	75          	loadsp 20
+ 416:	64          	loadsp 80
+ 417:	66          	loadsp 88
+ 418:	31          	sub
+ 419:	00          	breakpoint
+ 41a:	01          	.byte 1
+ 41b:	14          	addsp 16
+ 41c:	00          	breakpoint
+ 41d:	00          	breakpoint
+ 41e:	01          	.byte 1
+ 41f:	b3          	im 51
+ 420:	01          	.byte 1
+ 421:	05          	add
+ 422:	03          	.byte 3
+ 423:	00          	breakpoint
+ 424:	00          	breakpoint
+ 425:	09          	not
+ 426:	88          	im 8
+ 427:	02          	pushsp
+ 428:	7a          	loadsp 40
+ 429:	70          	loadsp 0
+ 42a:	75          	loadsp 20
+ 42b:	5f          	storesp 60
+ 42c:	70          	loadsp 0
+ 42d:	6f          	loadsp 124
+ 42e:	6b          	loadsp 108
+ 42f:	65          	loadsp 84
+ 430:	79          	loadsp 36
+ 431:	5f          	storesp 60
+ 432:	61          	loadsp 68
+ 433:	75          	loadsp 20
+ 434:	64          	loadsp 80
+ 435:	63          	loadsp 76
+ 436:	31          	sub
+ 437:	00          	breakpoint
+ 438:	01          	.byte 1
+ 439:	15          	addsp 20
+ 43a:	00          	breakpoint
+ 43b:	00          	breakpoint
+ 43c:	01          	.byte 1
+ 43d:	b3          	im 51
+ 43e:	01          	.byte 1
+ 43f:	05          	add
+ 440:	03          	.byte 3
+ 441:	00          	breakpoint
+ 442:	00          	breakpoint
+ 443:	09          	not
+ 444:	8c          	im 12
+ 445:	02          	pushsp
+ 446:	7a          	loadsp 40
+ 447:	70          	loadsp 0
+ 448:	75          	loadsp 20
+ 449:	5f          	storesp 60
+ 44a:	70          	loadsp 0
+ 44b:	6f          	loadsp 124
+ 44c:	6b          	loadsp 108
+ 44d:	65          	loadsp 84
+ 44e:	79          	loadsp 36
+ 44f:	5f          	storesp 60
+ 450:	61          	loadsp 68
+ 451:	75          	loadsp 20
+ 452:	64          	loadsp 80
+ 453:	66          	loadsp 88
+ 454:	32          	xor
+ 455:	00          	breakpoint
+ 456:	01          	.byte 1
+ 457:	16          	addsp 24
+ 458:	00          	breakpoint
+ 459:	00          	breakpoint
+ 45a:	01          	.byte 1
+ 45b:	b3          	im 51
+ 45c:	01          	.byte 1
+ 45d:	05          	add
+ 45e:	03          	.byte 3
+ 45f:	00          	breakpoint
+ 460:	00          	breakpoint
+ 461:	09          	not
+ 462:	90          	im 16
+ 463:	02          	pushsp
+ 464:	7a          	loadsp 40
+ 465:	70          	loadsp 0
+ 466:	75          	loadsp 20
+ 467:	5f          	storesp 60
+ 468:	70          	loadsp 0
+ 469:	6f          	loadsp 124
+ 46a:	6b          	loadsp 108
+ 46b:	65          	loadsp 84
+ 46c:	79          	loadsp 36
+ 46d:	5f          	storesp 60
+ 46e:	61          	loadsp 68
+ 46f:	75          	loadsp 20
+ 470:	64          	loadsp 80
+ 471:	63          	loadsp 76
+ 472:	32          	xor
+ 473:	00          	breakpoint
+ 474:	01          	.byte 1
+ 475:	17          	addsp 28
+ 476:	00          	breakpoint
+ 477:	00          	breakpoint
+ 478:	01          	.byte 1
+ 479:	b3          	im 51
+ 47a:	01          	.byte 1
+ 47b:	05          	add
+ 47c:	03          	.byte 3
+ 47d:	00          	breakpoint
+ 47e:	00          	breakpoint
+ 47f:	09          	not
+ 480:	94          	im 20
+ 481:	02          	pushsp
+ 482:	7a          	loadsp 40
+ 483:	70          	loadsp 0
+ 484:	75          	loadsp 20
+ 485:	5f          	storesp 60
+ 486:	70          	loadsp 0
+ 487:	6f          	loadsp 124
+ 488:	6b          	loadsp 108
+ 489:	65          	loadsp 84
+ 48a:	79          	loadsp 36
+ 48b:	5f          	storesp 60
+ 48c:	61          	loadsp 68
+ 48d:	75          	loadsp 20
+ 48e:	64          	loadsp 80
+ 48f:	66          	loadsp 88
+ 490:	33          	loadb
+ 491:	00          	breakpoint
+ 492:	01          	.byte 1
+ 493:	18          	addsp 32
+ 494:	00          	breakpoint
+ 495:	00          	breakpoint
+ 496:	01          	.byte 1
+ 497:	b3          	im 51
+ 498:	01          	.byte 1
+ 499:	05          	add
+ 49a:	03          	.byte 3
+ 49b:	00          	breakpoint
+ 49c:	00          	breakpoint
+ 49d:	09          	not
+ 49e:	98          	im 24
+ 49f:	02          	pushsp
+ 4a0:	7a          	loadsp 40
+ 4a1:	70          	loadsp 0
+ 4a2:	75          	loadsp 20
+ 4a3:	5f          	storesp 60
+ 4a4:	70          	loadsp 0
+ 4a5:	6f          	loadsp 124
+ 4a6:	6b          	loadsp 108
+ 4a7:	65          	loadsp 84
+ 4a8:	79          	loadsp 36
+ 4a9:	5f          	storesp 60
+ 4aa:	61          	loadsp 68
+ 4ab:	75          	loadsp 20
+ 4ac:	64          	loadsp 80
+ 4ad:	63          	loadsp 76
+ 4ae:	33          	loadb
+ 4af:	00          	breakpoint
+ 4b0:	01          	.byte 1
+ 4b1:	19          	addsp 36
+ 4b2:	00          	breakpoint
+ 4b3:	00          	breakpoint
+ 4b4:	01          	.byte 1
+ 4b5:	b3          	im 51
+ 4b6:	01          	.byte 1
+ 4b7:	05          	add
+ 4b8:	03          	.byte 3
+ 4b9:	00          	breakpoint
+ 4ba:	00          	breakpoint
+ 4bb:	09          	not
+ 4bc:	9c          	im 28
+ 4bd:	02          	pushsp
+ 4be:	7a          	loadsp 40
+ 4bf:	70          	loadsp 0
+ 4c0:	75          	loadsp 20
+ 4c1:	5f          	storesp 60
+ 4c2:	70          	loadsp 0
+ 4c3:	6f          	loadsp 124
+ 4c4:	6b          	loadsp 108
+ 4c5:	65          	loadsp 84
+ 4c6:	79          	loadsp 36
+ 4c7:	5f          	storesp 60
+ 4c8:	61          	loadsp 68
+ 4c9:	75          	loadsp 20
+ 4ca:	64          	loadsp 80
+ 4cb:	63          	loadsp 76
+ 4cc:	74          	loadsp 16
+ 4cd:	6c          	loadsp 112
+ 4ce:	00          	breakpoint
+ 4cf:	01          	.byte 1
+ 4d0:	1b          	addsp 44
+ 4d1:	00          	breakpoint
+ 4d2:	00          	breakpoint
+ 4d3:	01          	.byte 1
+ 4d4:	b3          	im 51
+ 4d5:	01          	.byte 1
+ 4d6:	05          	add
+ 4d7:	03          	.byte 3
+ 4d8:	00          	breakpoint
+ 4d9:	00          	breakpoint
+ 4da:	09          	not
+ 4db:	a0          	im 32
+ 4dc:	02          	pushsp
+ 4dd:	7a          	loadsp 40
+ 4de:	70          	loadsp 0
+ 4df:	75          	loadsp 20
+ 4e0:	5f          	storesp 60
+ 4e1:	70          	loadsp 0
+ 4e2:	6f          	loadsp 124
+ 4e3:	6b          	loadsp 108
+ 4e4:	65          	loadsp 84
+ 4e5:	79          	loadsp 36
+ 4e6:	5f          	storesp 60
+ 4e7:	73          	loadsp 12
+ 4e8:	6b          	loadsp 108
+ 4e9:	72          	loadsp 8
+ 4ea:	65          	loadsp 84
+ 4eb:	73          	loadsp 12
+ 4ec:	74          	loadsp 16
+ 4ed:	00          	breakpoint
+ 4ee:	01          	.byte 1
+ 4ef:	1d          	addsp 52
+ 4f0:	00          	breakpoint
+ 4f1:	00          	breakpoint
+ 4f2:	01          	.byte 1
+ 4f3:	b3          	im 51
+ 4f4:	01          	.byte 1
+ 4f5:	05          	add
+ 4f6:	03          	.byte 3
+ 4f7:	00          	breakpoint
+ 4f8:	00          	breakpoint
+ 4f9:	09          	not
+ 4fa:	a4          	im 36
+ 4fb:	02          	pushsp
+ 4fc:	7a          	loadsp 40
+ 4fd:	70          	loadsp 0
+ 4fe:	75          	loadsp 20
+ 4ff:	5f          	storesp 60
+ 500:	70          	loadsp 0
+ 501:	6f          	loadsp 124
+ 502:	6b          	loadsp 108
+ 503:	65          	loadsp 84
+ 504:	79          	loadsp 36
+ 505:	5f          	storesp 60
+ 506:	73          	loadsp 12
+ 507:	65          	loadsp 84
+ 508:	72          	loadsp 8
+ 509:	6f          	loadsp 124
+ 50a:	75          	loadsp 20
+ 50b:	74          	loadsp 16
+ 50c:	00          	breakpoint
+ 50d:	01          	.byte 1
+ 50e:	1e          	addsp 56
+ 50f:	00          	breakpoint
+ 510:	00          	breakpoint
+ 511:	01          	.byte 1
+ 512:	b3          	im 51
+ 513:	01          	.byte 1
+ 514:	05          	add
+ 515:	03          	.byte 3
+ 516:	00          	breakpoint
+ 517:	00          	breakpoint
+ 518:	09          	not
+ 519:	a8          	im 40
+ 51a:	02          	pushsp
+ 51b:	7a          	loadsp 40
+ 51c:	70          	loadsp 0
+ 51d:	75          	loadsp 20
+ 51e:	5f          	storesp 60
+ 51f:	70          	loadsp 0
+ 520:	6f          	loadsp 124
+ 521:	6b          	loadsp 108
+ 522:	65          	loadsp 84
+ 523:	79          	loadsp 36
+ 524:	5f          	storesp 60
+ 525:	69          	loadsp 100
+ 526:	72          	loadsp 8
+ 527:	71          	loadsp 4
+ 528:	65          	loadsp 84
+ 529:	6e          	loadsp 120
+ 52a:	00          	breakpoint
+ 52b:	01          	.byte 1
+ 52c:	1f          	addsp 60
+ 52d:	00          	breakpoint
+ 52e:	00          	breakpoint
+ 52f:	01          	.byte 1
+ 530:	b3          	im 51
+ 531:	01          	.byte 1
+ 532:	05          	add
+ 533:	03          	.byte 3
+ 534:	00          	breakpoint
+ 535:	00          	breakpoint
+ 536:	09          	not
+ 537:	ac          	im 44
+ 538:	02          	pushsp
+ 539:	7a          	loadsp 40
+ 53a:	70          	loadsp 0
+ 53b:	75          	loadsp 20
+ 53c:	5f          	storesp 60
+ 53d:	70          	loadsp 0
+ 53e:	6f          	loadsp 124
+ 53f:	6b          	loadsp 108
+ 540:	65          	loadsp 84
+ 541:	79          	loadsp 36
+ 542:	5f          	storesp 60
+ 543:	73          	loadsp 12
+ 544:	6b          	loadsp 108
+ 545:	63          	loadsp 76
+ 546:	74          	loadsp 16
+ 547:	6c          	loadsp 112
+ 548:	00          	breakpoint
+ 549:	01          	.byte 1
+ 54a:	20          	.byte 32
+ 54b:	00          	breakpoint
+ 54c:	00          	breakpoint
+ 54d:	01          	.byte 1
+ 54e:	b3          	im 51
+ 54f:	01          	.byte 1
+ 550:	05          	add
+ 551:	03          	.byte 3
+ 552:	00          	breakpoint
+ 553:	00          	breakpoint
+ 554:	09          	not
+ 555:	b0          	im 48
+ 556:	02          	pushsp
+ 557:	61          	loadsp 68
+ 558:	74          	loadsp 16
+ 559:	61          	loadsp 68
+ 55a:	72          	loadsp 8
+ 55b:	69          	loadsp 100
+ 55c:	5f          	storesp 60
+ 55d:	6e          	loadsp 120
+ 55e:	6d          	loadsp 116
+ 55f:	69          	loadsp 100
+ 560:	65          	loadsp 84
+ 561:	6e          	loadsp 120
+ 562:	00          	breakpoint
+ 563:	01          	.byte 1
+ 564:	22          	loadh
+ 565:	00          	breakpoint
+ 566:	00          	breakpoint
+ 567:	01          	.byte 1
+ 568:	b3          	im 51
+ 569:	01          	.byte 1
+ 56a:	05          	add
+ 56b:	03          	.byte 3
+ 56c:	00          	breakpoint
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+	...
+Disassembly of section .debug_line:
+
+00000000 <.Ldebug_line0>:
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+	...
+Disassembly of section .debug_frame:
+
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+Disassembly of section .debug_pubnames:
+
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+  f5:	00          	breakpoint
+  f6:	00          	breakpoint
+  f7:	00          	breakpoint
+  f8:	01          	.byte 1
+  f9:	66          	loadsp 88
+  fa:	7a          	loadsp 40
+  fb:	70          	loadsp 0
+  fc:	75          	loadsp 20
+  fd:	5f          	storesp 60
+  fe:	68          	loadsp 96
+  ff:	65          	loadsp 84
+ 100:	78          	loadsp 32
+ 101:	00          	breakpoint
+ 102:	00          	breakpoint
+ 103:	00          	breakpoint
+ 104:	01          	.byte 1
+ 105:	7c          	loadsp 48
+ 106:	7a          	loadsp 40
+ 107:	70          	loadsp 0
+ 108:	75          	loadsp 20
+ 109:	5f          	storesp 60
+ 10a:	73          	loadsp 12
+ 10b:	65          	loadsp 84
+ 10c:	63          	loadsp 76
+ 10d:	74          	loadsp 16
+ 10e:	6f          	loadsp 124
+ 10f:	72          	loadsp 8
+ 110:	00          	breakpoint
+ 111:	00          	breakpoint
+ 112:	00          	breakpoint
+ 113:	01          	.byte 1
+ 114:	95          	im 21
+ 115:	7a          	loadsp 40
+ 116:	70          	loadsp 0
+ 117:	75          	loadsp 20
+ 118:	5f          	storesp 60
+ 119:	70          	loadsp 0
+ 11a:	6f          	loadsp 124
+ 11b:	6b          	loadsp 108
+ 11c:	65          	loadsp 84
+ 11d:	79          	loadsp 36
+ 11e:	5f          	storesp 60
+ 11f:	61          	loadsp 68
+ 120:	75          	loadsp 20
+ 121:	64          	loadsp 80
+ 122:	66          	loadsp 88
+ 123:	30          	neg
+ 124:	00          	breakpoint
+ 125:	00          	breakpoint
+ 126:	00          	breakpoint
+ 127:	01          	.byte 1
+ 128:	cf          	im -49
+ 129:	7a          	loadsp 40
+ 12a:	70          	loadsp 0
+ 12b:	75          	loadsp 20
+ 12c:	5f          	storesp 60
+ 12d:	70          	loadsp 0
+ 12e:	6f          	loadsp 124
+ 12f:	6b          	loadsp 108
+ 130:	65          	loadsp 84
+ 131:	79          	loadsp 36
+ 132:	5f          	storesp 60
+ 133:	61          	loadsp 68
+ 134:	75          	loadsp 20
+ 135:	64          	loadsp 80
+ 136:	63          	loadsp 76
+ 137:	30          	neg
+ 138:	00          	breakpoint
+ 139:	00          	breakpoint
+ 13a:	00          	breakpoint
+ 13b:	01          	.byte 1
+ 13c:	ed          	im -19
+ 13d:	7a          	loadsp 40
+ 13e:	70          	loadsp 0
+ 13f:	75          	loadsp 20
+ 140:	5f          	storesp 60
+ 141:	70          	loadsp 0
+ 142:	6f          	loadsp 124
+ 143:	6b          	loadsp 108
+ 144:	65          	loadsp 84
+ 145:	79          	loadsp 36
+ 146:	5f          	storesp 60
+ 147:	61          	loadsp 68
+ 148:	75          	loadsp 20
+ 149:	64          	loadsp 80
+ 14a:	66          	loadsp 88
+ 14b:	31          	sub
+ 14c:	00          	breakpoint
+ 14d:	00          	breakpoint
+ 14e:	00          	breakpoint
+ 14f:	02          	pushsp
+ 150:	0b          	nop
+ 151:	7a          	loadsp 40
+ 152:	70          	loadsp 0
+ 153:	75          	loadsp 20
+ 154:	5f          	storesp 60
+ 155:	70          	loadsp 0
+ 156:	6f          	loadsp 124
+ 157:	6b          	loadsp 108
+ 158:	65          	loadsp 84
+ 159:	79          	loadsp 36
+ 15a:	5f          	storesp 60
+ 15b:	61          	loadsp 68
+ 15c:	75          	loadsp 20
+ 15d:	64          	loadsp 80
+ 15e:	63          	loadsp 76
+ 15f:	31          	sub
+ 160:	00          	breakpoint
+ 161:	00          	breakpoint
+ 162:	00          	breakpoint
+ 163:	02          	pushsp
+ 164:	29          	mult
+ 165:	7a          	loadsp 40
+ 166:	70          	loadsp 0
+ 167:	75          	loadsp 20
+ 168:	5f          	storesp 60
+ 169:	70          	loadsp 0
+ 16a:	6f          	loadsp 124
+ 16b:	6b          	loadsp 108
+ 16c:	65          	loadsp 84
+ 16d:	79          	loadsp 36
+ 16e:	5f          	storesp 60
+ 16f:	61          	loadsp 68
+ 170:	75          	loadsp 20
+ 171:	64          	loadsp 80
+ 172:	66          	loadsp 88
+ 173:	32          	xor
+ 174:	00          	breakpoint
+ 175:	00          	breakpoint
+ 176:	00          	breakpoint
+ 177:	02          	pushsp
+ 178:	47          	storesp 92
+ 179:	7a          	loadsp 40
+ 17a:	70          	loadsp 0
+ 17b:	75          	loadsp 20
+ 17c:	5f          	storesp 60
+ 17d:	70          	loadsp 0
+ 17e:	6f          	loadsp 124
+ 17f:	6b          	loadsp 108
+ 180:	65          	loadsp 84
+ 181:	79          	loadsp 36
+ 182:	5f          	storesp 60
+ 183:	61          	loadsp 68
+ 184:	75          	loadsp 20
+ 185:	64          	loadsp 80
+ 186:	63          	loadsp 76
+ 187:	32          	xor
+ 188:	00          	breakpoint
+ 189:	00          	breakpoint
+ 18a:	00          	breakpoint
+ 18b:	02          	pushsp
+ 18c:	65          	loadsp 84
+ 18d:	7a          	loadsp 40
+ 18e:	70          	loadsp 0
+ 18f:	75          	loadsp 20
+ 190:	5f          	storesp 60
+ 191:	70          	loadsp 0
+ 192:	6f          	loadsp 124
+ 193:	6b          	loadsp 108
+ 194:	65          	loadsp 84
+ 195:	79          	loadsp 36
+ 196:	5f          	storesp 60
+ 197:	61          	loadsp 68
+ 198:	75          	loadsp 20
+ 199:	64          	loadsp 80
+ 19a:	66          	loadsp 88
+ 19b:	33          	loadb
+ 19c:	00          	breakpoint
+ 19d:	00          	breakpoint
+ 19e:	00          	breakpoint
+ 19f:	02          	pushsp
+ 1a0:	83          	im 3
+ 1a1:	7a          	loadsp 40
+ 1a2:	70          	loadsp 0
+ 1a3:	75          	loadsp 20
+ 1a4:	5f          	storesp 60
+ 1a5:	70          	loadsp 0
+ 1a6:	6f          	loadsp 124
+ 1a7:	6b          	loadsp 108
+ 1a8:	65          	loadsp 84
+ 1a9:	79          	loadsp 36
+ 1aa:	5f          	storesp 60
+ 1ab:	61          	loadsp 68
+ 1ac:	75          	loadsp 20
+ 1ad:	64          	loadsp 80
+ 1ae:	63          	loadsp 76
+ 1af:	33          	loadb
+ 1b0:	00          	breakpoint
+ 1b1:	00          	breakpoint
+ 1b2:	00          	breakpoint
+ 1b3:	02          	pushsp
+ 1b4:	a1          	im 33
+ 1b5:	7a          	loadsp 40
+ 1b6:	70          	loadsp 0
+ 1b7:	75          	loadsp 20
+ 1b8:	5f          	storesp 60
+ 1b9:	70          	loadsp 0
+ 1ba:	6f          	loadsp 124
+ 1bb:	6b          	loadsp 108
+ 1bc:	65          	loadsp 84
+ 1bd:	79          	loadsp 36
+ 1be:	5f          	storesp 60
+ 1bf:	61          	loadsp 68
+ 1c0:	75          	loadsp 20
+ 1c1:	64          	loadsp 80
+ 1c2:	63          	loadsp 76
+ 1c3:	74          	loadsp 16
+ 1c4:	6c          	loadsp 112
+ 1c5:	00          	breakpoint
+ 1c6:	00          	breakpoint
+ 1c7:	00          	breakpoint
+ 1c8:	02          	pushsp
+ 1c9:	c0          	im -64
+ 1ca:	7a          	loadsp 40
+ 1cb:	70          	loadsp 0
+ 1cc:	75          	loadsp 20
+ 1cd:	5f          	storesp 60
+ 1ce:	70          	loadsp 0
+ 1cf:	6f          	loadsp 124
+ 1d0:	6b          	loadsp 108
+ 1d1:	65          	loadsp 84
+ 1d2:	79          	loadsp 36
+ 1d3:	5f          	storesp 60
+ 1d4:	73          	loadsp 12
+ 1d5:	6b          	loadsp 108
+ 1d6:	72          	loadsp 8
+ 1d7:	65          	loadsp 84
+ 1d8:	73          	loadsp 12
+ 1d9:	74          	loadsp 16
+ 1da:	00          	breakpoint
+ 1db:	00          	breakpoint
+ 1dc:	00          	breakpoint
+ 1dd:	02          	pushsp
+ 1de:	df          	im -33
+ 1df:	7a          	loadsp 40
+ 1e0:	70          	loadsp 0
+ 1e1:	75          	loadsp 20
+ 1e2:	5f          	storesp 60
+ 1e3:	70          	loadsp 0
+ 1e4:	6f          	loadsp 124
+ 1e5:	6b          	loadsp 108
+ 1e6:	65          	loadsp 84
+ 1e7:	79          	loadsp 36
+ 1e8:	5f          	storesp 60
+ 1e9:	73          	loadsp 12
+ 1ea:	65          	loadsp 84
+ 1eb:	72          	loadsp 8
+ 1ec:	6f          	loadsp 124
+ 1ed:	75          	loadsp 20
+ 1ee:	74          	loadsp 16
+ 1ef:	00          	breakpoint
+ 1f0:	00          	breakpoint
+ 1f1:	00          	breakpoint
+ 1f2:	02          	pushsp
+ 1f3:	fe          	im -2
+ 1f4:	7a          	loadsp 40
+ 1f5:	70          	loadsp 0
+ 1f6:	75          	loadsp 20
+ 1f7:	5f          	storesp 60
+ 1f8:	70          	loadsp 0
+ 1f9:	6f          	loadsp 124
+ 1fa:	6b          	loadsp 108
+ 1fb:	65          	loadsp 84
+ 1fc:	79          	loadsp 36
+ 1fd:	5f          	storesp 60
+ 1fe:	69          	loadsp 100
+ 1ff:	72          	loadsp 8
+ 200:	71          	loadsp 4
+ 201:	65          	loadsp 84
+ 202:	6e          	loadsp 120
+ 203:	00          	breakpoint
+ 204:	00          	breakpoint
+ 205:	00          	breakpoint
+ 206:	03          	.byte 3
+ 207:	1c          	addsp 48
+ 208:	7a          	loadsp 40
+ 209:	70          	loadsp 0
+ 20a:	75          	loadsp 20
+ 20b:	5f          	storesp 60
+ 20c:	70          	loadsp 0
+ 20d:	6f          	loadsp 124
+ 20e:	6b          	loadsp 108
+ 20f:	65          	loadsp 84
+ 210:	79          	loadsp 36
+ 211:	5f          	storesp 60
+ 212:	73          	loadsp 12
+ 213:	6b          	loadsp 108
+ 214:	63          	loadsp 76
+ 215:	74          	loadsp 16
+ 216:	6c          	loadsp 112
+ 217:	00          	breakpoint
+ 218:	00          	breakpoint
+ 219:	00          	breakpoint
+ 21a:	03          	.byte 3
+ 21b:	3a          	config
+ 21c:	61          	loadsp 68
+ 21d:	74          	loadsp 16
+ 21e:	61          	loadsp 68
+ 21f:	72          	loadsp 8
+ 220:	69          	loadsp 100
+ 221:	5f          	storesp 60
+ 222:	6e          	loadsp 120
+ 223:	6d          	loadsp 116
+ 224:	69          	loadsp 100
+ 225:	65          	loadsp 84
+ 226:	6e          	loadsp 120
+ 227:	00          	breakpoint
+ 228:	00          	breakpoint
+ 229:	00          	breakpoint
+ 22a:	03          	.byte 3
+ 22b:	54          	storesp 16
+ 22c:	61          	loadsp 68
+ 22d:	74          	loadsp 16
+ 22e:	61          	loadsp 68
+ 22f:	72          	loadsp 8
+ 230:	69          	loadsp 100
+ 231:	5f          	storesp 60
+ 232:	64          	loadsp 80
+ 233:	6c          	loadsp 112
+ 234:	69          	loadsp 100
+ 235:	73          	loadsp 12
+ 236:	74          	loadsp 16
+ 237:	6c          	loadsp 112
+ 238:	00          	breakpoint
+ 239:	00          	breakpoint
+ 23a:	00          	breakpoint
+ 23b:	03          	.byte 3
+ 23c:	6f          	loadsp 124
+ 23d:	61          	loadsp 68
+ 23e:	74          	loadsp 16
+ 23f:	61          	loadsp 68
+ 240:	72          	loadsp 8
+ 241:	69          	loadsp 100
+ 242:	5f          	storesp 60
+ 243:	64          	loadsp 80
+ 244:	6c          	loadsp 112
+ 245:	69          	loadsp 100
+ 246:	73          	loadsp 12
+ 247:	74          	loadsp 16
+ 248:	68          	loadsp 96
+ 249:	00          	breakpoint
+ 24a:	00          	breakpoint
+ 24b:	00          	breakpoint
+ 24c:	03          	.byte 3
+ 24d:	8a          	im 10
+ 24e:	61          	loadsp 68
+ 24f:	74          	loadsp 16
+ 250:	61          	loadsp 68
+ 251:	72          	loadsp 8
+ 252:	69          	loadsp 100
+ 253:	5f          	storesp 60
+ 254:	63          	loadsp 76
+ 255:	6f          	loadsp 124
+ 256:	6c          	loadsp 112
+ 257:	62          	loadsp 72
+ 258:	6b          	loadsp 108
+ 259:	00          	breakpoint
+ 25a:	00          	breakpoint
+ 25b:	00          	breakpoint
+ 25c:	03          	.byte 3
+ 25d:	a4          	im 36
+ 25e:	61          	loadsp 68
+ 25f:	74          	loadsp 16
+ 260:	61          	loadsp 68
+ 261:	72          	loadsp 8
+ 262:	69          	loadsp 100
+ 263:	5f          	storesp 60
+ 264:	63          	loadsp 76
+ 265:	6f          	loadsp 124
+ 266:	6c          	loadsp 112
+ 267:	70          	loadsp 0
+ 268:	66          	loadsp 88
+ 269:	31          	sub
+ 26a:	00          	breakpoint
+ 26b:	00          	breakpoint
+ 26c:	00          	breakpoint
+ 26d:	03          	.byte 3
+ 26e:	bf          	im 63
+ 26f:	61          	loadsp 68
+ 270:	74          	loadsp 16
+ 271:	61          	loadsp 68
+ 272:	72          	loadsp 8
+ 273:	69          	loadsp 100
+ 274:	5f          	storesp 60
+ 275:	63          	loadsp 76
+ 276:	6f          	loadsp 124
+ 277:	6c          	loadsp 112
+ 278:	70          	loadsp 0
+ 279:	66          	loadsp 88
+ 27a:	32          	xor
+ 27b:	00          	breakpoint
+ 27c:	00          	breakpoint
+ 27d:	00          	breakpoint
+ 27e:	03          	.byte 3
+ 27f:	da          	im -38
+ 280:	61          	loadsp 68
+ 281:	74          	loadsp 16
+ 282:	61          	loadsp 68
+ 283:	72          	loadsp 8
+ 284:	69          	loadsp 100
+ 285:	5f          	storesp 60
+ 286:	70          	loadsp 0
+ 287:	72          	loadsp 8
+ 288:	69          	loadsp 100
+ 289:	6f          	loadsp 124
+ 28a:	72          	loadsp 8
+ 28b:	00          	breakpoint
+ 28c:	00          	breakpoint
+ 28d:	00          	breakpoint
+ 28e:	03          	.byte 3
+ 28f:	f4          	im -12
+ 290:	61          	loadsp 68
+ 291:	74          	loadsp 16
+ 292:	61          	loadsp 68
+ 293:	72          	loadsp 8
+ 294:	69          	loadsp 100
+ 295:	5f          	storesp 60
+ 296:	72          	loadsp 8
+ 297:	61          	loadsp 68
+ 298:	6e          	loadsp 120
+ 299:	64          	loadsp 80
+ 29a:	6f          	loadsp 124
+ 29b:	6d          	loadsp 116
+ 29c:	00          	breakpoint
+ 29d:	00          	breakpoint
+ 29e:	00          	breakpoint
+ 29f:	04          	poppc
+ 2a0:	0f          	.byte 15
+ 2a1:	61          	loadsp 68
+ 2a2:	74          	loadsp 16
+ 2a3:	61          	loadsp 68
+ 2a4:	72          	loadsp 8
+ 2a5:	69          	loadsp 100
+ 2a6:	5f          	storesp 60
+ 2a7:	70          	loadsp 0
+ 2a8:	6f          	loadsp 124
+ 2a9:	72          	loadsp 8
+ 2aa:	74          	loadsp 16
+ 2ab:	61          	loadsp 68
+ 2ac:	00          	breakpoint
+ 2ad:	00          	breakpoint
+ 2ae:	00          	breakpoint
+ 2af:	04          	poppc
+ 2b0:	29          	mult
+ 2b1:	61          	loadsp 68
+ 2b2:	74          	loadsp 16
+ 2b3:	61          	loadsp 68
+ 2b4:	72          	loadsp 8
+ 2b5:	69          	loadsp 100
+ 2b6:	5f          	storesp 60
+ 2b7:	70          	loadsp 0
+ 2b8:	6f          	loadsp 124
+ 2b9:	72          	loadsp 8
+ 2ba:	74          	loadsp 16
+ 2bb:	62          	loadsp 72
+ 2bc:	00          	breakpoint
+ 2bd:	00          	breakpoint
+ 2be:	00          	breakpoint
+ 2bf:	04          	poppc
+ 2c0:	43          	storesp 76
+ 2c1:	61          	loadsp 68
+ 2c2:	74          	loadsp 16
+ 2c3:	61          	loadsp 68
+ 2c4:	72          	loadsp 8
+ 2c5:	69          	loadsp 100
+ 2c6:	5f          	storesp 60
+ 2c7:	74          	loadsp 16
+ 2c8:	72          	loadsp 8
+ 2c9:	69          	loadsp 100
+ 2ca:	67          	loadsp 92
+ 2cb:	30          	neg
+ 2cc:	00          	breakpoint
+ 2cd:	00          	breakpoint
+ 2ce:	00          	breakpoint
+ 2cf:	04          	poppc
+ 2d0:	5d          	storesp 52
+ 2d1:	61          	loadsp 68
+ 2d2:	74          	loadsp 16
+ 2d3:	61          	loadsp 68
+ 2d4:	72          	loadsp 8
+ 2d5:	69          	loadsp 100
+ 2d6:	5f          	storesp 60
+ 2d7:	63          	loadsp 76
+ 2d8:	68          	loadsp 96
+ 2d9:	62          	loadsp 72
+ 2da:	61          	loadsp 68
+ 2db:	73          	loadsp 12
+ 2dc:	65          	loadsp 84
+ 2dd:	00          	breakpoint
+ 2de:	00          	breakpoint
+ 2df:	00          	breakpoint
+ 2e0:	04          	poppc
+ 2e1:	78          	loadsp 32
+ 2e2:	61          	loadsp 68
+ 2e3:	74          	loadsp 16
+ 2e4:	61          	loadsp 68
+ 2e5:	72          	loadsp 8
+ 2e6:	69          	loadsp 100
+ 2e7:	5f          	storesp 60
+ 2e8:	63          	loadsp 76
+ 2e9:	68          	loadsp 96
+ 2ea:	61          	loadsp 68
+ 2eb:	63          	loadsp 76
+ 2ec:	74          	loadsp 16
+ 2ed:	6c          	loadsp 112
+ 2ee:	00          	breakpoint
+ 2ef:	00          	breakpoint
+ 2f0:	00          	breakpoint
+ 2f1:	04          	poppc
+ 2f2:	93          	im 19
+ 2f3:	61          	loadsp 68
+ 2f4:	74          	loadsp 16
+ 2f5:	61          	loadsp 68
+ 2f6:	72          	loadsp 8
+ 2f7:	69          	loadsp 100
+ 2f8:	5f          	storesp 60
+ 2f9:	64          	loadsp 80
+ 2fa:	6d          	loadsp 116
+ 2fb:	61          	loadsp 68
+ 2fc:	63          	loadsp 76
+ 2fd:	74          	loadsp 16
+ 2fe:	6c          	loadsp 112
+ 2ff:	00          	breakpoint
+ 300:	00          	breakpoint
+ 301:	00          	breakpoint
+ 302:	04          	poppc
+ 303:	ae          	im 46
+ 304:	61          	loadsp 68
+ 305:	74          	loadsp 16
+ 306:	61          	loadsp 68
+ 307:	72          	loadsp 8
+ 308:	69          	loadsp 100
+ 309:	5f          	storesp 60
+ 30a:	73          	loadsp 12
+ 30b:	6b          	loadsp 108
+ 30c:	63          	loadsp 76
+ 30d:	74          	loadsp 16
+ 30e:	6c          	loadsp 112
+ 30f:	00          	breakpoint
+ 310:	00          	breakpoint
+ 311:	00          	breakpoint
+	...
+Disassembly of section .debug_aranges:
+
+00000000 <.debug_aranges>:
+   0:	00          	breakpoint
+   1:	00          	breakpoint
+   2:	00          	breakpoint
+   3:	1c          	addsp 48
+   4:	00          	breakpoint
+   5:	02          	pushsp
+   6:	00          	breakpoint
+   7:	00          	breakpoint
+   8:	00          	breakpoint
+   9:	00          	breakpoint
+   a:	04          	poppc
+   b:	00          	breakpoint
+   c:	00          	breakpoint
+   d:	00          	breakpoint
+   e:	00          	breakpoint
+   f:	00          	breakpoint
+  10:	00          	breakpoint
+  11:	00          	breakpoint
+  12:	04          	poppc
+  13:	b1          	im 49
+  14:	00          	breakpoint
+  15:	00          	breakpoint
+  16:	02          	pushsp
+  17:	8e          	im 14
+	...
+Disassembly of section .comment:
+
+00000000 <.comment>:
+   0:	00          	breakpoint
+   1:	47          	storesp 92
+   2:	43          	storesp 76
+   3:	43          	storesp 76
+   4:	3a          	config
+   5:	20          	.byte 32
+   6:	28          	swap
+   7:	47          	storesp 92
+   8:	4e          	storesp 120
+   9:	55          	storesp 20
+   a:	29          	mult
+   b:	20          	.byte 32
+   c:	33          	loadb
+   d:	2e          	eq
+   e:	34          	storeb
+   f:	2e          	eq
+  10:	32          	xor
+  11:	00          	breakpoint
+  12:	00          	breakpoint
+  13:	47          	storesp 92
+  14:	43          	storesp 76
+  15:	43          	storesp 76
+  16:	3a          	config
+  17:	20          	.byte 32
+  18:	28          	swap
+  19:	47          	storesp 92
+  1a:	4e          	storesp 120
+  1b:	55          	storesp 20
+  1c:	29          	mult
+  1d:	20          	.byte 32
+  1e:	33          	loadb
+  1f:	2e          	eq
+  20:	34          	storeb
+  21:	2e          	eq
+  22:	32          	xor
+  23:	00          	breakpoint
+  24:	00          	breakpoint
+  25:	47          	storesp 92
+  26:	43          	storesp 76
+  27:	43          	storesp 76
+  28:	3a          	config
+  29:	20          	.byte 32
+  2a:	28          	swap
+  2b:	47          	storesp 92
+  2c:	4e          	storesp 120
+  2d:	55          	storesp 20
+  2e:	29          	mult
+  2f:	20          	.byte 32
+  30:	33          	loadb
+  31:	2e          	eq
+  32:	34          	storeb
+  33:	2e          	eq
+  34:	32          	xor
+  35:	00          	breakpoint
+  36:	00          	breakpoint
+  37:	47          	storesp 92
+  38:	43          	storesp 76
+  39:	43          	storesp 76
+  3a:	3a          	config
+  3b:	20          	.byte 32
+  3c:	28          	swap
+  3d:	47          	storesp 92
+  3e:	4e          	storesp 120
+  3f:	55          	storesp 20
+  40:	29          	mult
+  41:	20          	.byte 32
+  42:	33          	loadb
+  43:	2e          	eq
+  44:	34          	storeb
+  45:	2e          	eq
+  46:	32          	xor
+	...
Index: common/a8core/address_decoder.vhdl
===================================================================
--- common/a8core/address_decoder.vhdl	(nonexistent)
+++ common/a8core/address_decoder.vhdl	(revision 1)
@@ -0,0 +1,772 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+
+ENTITY address_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	-- bus masters - either CPU or antic
+	-- antic has priority and is slected when ANTIC_FETCH high
+	CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	CPU_FETCH : in std_logic;
+	CPU_WRITE_N : IN STD_LOGIC;
+	CPU_WRITE_DATA : in std_logic_vector(7 downto 0);	
+	
+	ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	ANTIC_FETCH : IN STD_LOGIC;
+	antic_refresh : in std_logic; -- use for sdram refresh (sdram needs more, but this is a start)
+
+	ZPU_ADDR : in std_logic_vector(23 downto 0);	
+	ZPU_FETCH : in std_logic;
+	ZPU_READ_ENABLE : in std_logic;
+	ZPU_32BIT_WRITE_ENABLE : in std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : in std_logic; -- for sram
+	ZPU_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs	
+	ZPU_WRITE_DATA : in std_logic_vector(31 downto 0);
+	
+	-- sources of data
+	ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	-- flash rom
+	GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
+	CART_ROM_DATA : in std_logic_Vector(7 downto 0);
+	
+	-- completion flags
+	RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+	ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+	CART_REQUEST_COMPLETE : IN STD_LOGIC;
+	
+	-- configuration options	
+	PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	reset_n : in std_logic;
+	
+	rom_select : in std_logic_vector(5 downto 0);
+	cart_select : in std_logic_vector(6 downto 0);
+	cart_activate : in std_logic;
+	
+	ram_select : in std_logic_vector(2 downto 0);
+	
+	CART_RD4 : in std_logic;
+	CART_RD5 : in std_logic;
+	
+	use_sdram : in std_logic;
+		
+	-- Memory read mux output
+	MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
+	
+	-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
+	-- Allow us to say we're not ready for a cycle
+	MEMORY_READY_ANTIC : OUT STD_LOGIC;
+	MEMORY_READY_ZPU : OUT STD_LOGIC;
+	MEMORY_READY_CPU : out std_logic;	
+	
+	-- Each chip does not have whole address bus, so several are addressed at once
+	-- For reads not an issue, but for writes we need to only write to a single place!
+		-- these all take 1 cycle, so fine to leave device selected in general
+	GTIA_WR_ENABLE : OUT STD_LOGIC;
+	POKEY_WR_ENABLE : OUT STD_LOGIC;
+	POKEY2_WR_ENABLE : OUT STD_LOGIC;
+	ANTIC_WR_ENABLE : OUT STD_LOGIC;
+	PIA_WR_ENABLE : OUT STD_LOGIC;
+	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+	RAM_WR_ENABLE : OUT STD_LOGIC;	
+	PBI_WR_ENABLE : OUT STD_LOGIC;
+	D6_WR_ENABLE : OUT STD_LOGIC;
+ 	
+	-- ROM and RAM have extended address busses to allow for bank switching etc.
+	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+	PBI_ADDR : out  std_logic_vector(15 downto 0);
+	
+	RAM_REQUEST : out std_logic;
+	ROM_REQUEST : out std_logic;
+	CART_REQUEST : out std_logic;
+	
+	CART_S4_n : out std_logic;
+	CART_S5_n : out std_logic;
+	CART_CCTL_n : out std_logic;
+	
+	-- width of access
+	WIDTH_8bit_ACCESS : out std_logic;
+	WIDTH_16bit_ACCESS : out std_logic;
+	WIDTH_32bit_ACCESS : out std_logic;
+	
+		-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+	SDRAM_WRITE_EN : out std_logic;
+	--SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+	SDRAM_REQUEST : out std_logic; -- Usual pattern
+	SDRAM_REFRESH : out std_logic;
+
+	--SDRAM_REPLY : in std_logic; -- This matches the request once complete
+	SDRAM_REQUEST_COMPLETE : in std_logic;
+	SDRAM_DATA : in std_logic_vector(31 downto 0);
+	
+	WRITE_DATA : out std_logic_vector(31 downto 0)
+);
+
+END address_decoder;
+
+ARCHITECTURE vhdl OF address_decoder IS
+	signal ADDR_next : std_logic_vector(23 downto 0);
+	signal ADDR_reg : std_logic_vector(23 downto 0);
+
+	signal DATA_WRITE_next : std_logic_vector(31 downto 0);
+	signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
+	
+	signal width_8bit_next : std_logic;
+	signal width_16bit_next : std_logic;
+	signal width_32bit_next : std_logic;
+	signal write_enable_next : std_logic;
+
+	signal width_8bit_reg : std_logic;
+	signal width_16bit_reg : std_logic;
+	signal width_32bit_reg : std_logic;
+	signal write_enable_reg : std_logic;
+	
+	signal request_complete : std_logic;
+	signal notify_antic : std_logic;
+	signal notify_zpu : std_logic;
+	signal notify_cpu : std_logic;
+	signal start_request : std_logic;
+	
+	signal extended_access_addr : std_logic;
+	signal extended_access_cpu_or_antic : std_logic;
+	signal extended_access_antic : std_logic;
+	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+	
+	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+
+	signal extended_self_test : std_logic;
+	signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
+	
+	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_idle : std_logic_vector(1 downto 0) := "00";
+	constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
+	constant state_waiting_zpu : std_logic_vector(1 downto 0) := "10";
+	constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
+		
+	signal ram_chip_select : std_logic;
+	signal sdram_chip_select : std_logic;
+	
+--	signal sdram_request_next : std_logic;
+--	signal sdram_request_reg : std_logic;
+--	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+	
+	signal fetch_priority : std_logic_vector(2 downto 0);
+	
+	signal fetch_wait_next : std_logic_vector(8 downto 0);
+	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
+	
+	signal rom_in_ram : std_logic;
+	
+	signal antic_fetch_real_next : std_logic;
+	signal antic_fetch_real_reg : std_logic;
+	signal cpu_fetch_real_next : std_logic;
+	signal cpu_fetch_real_reg : std_logic;
+
+	signal SDRAM_CART_ADDR   : std_logic_vector(22 downto 0);
+	signal SDRAM_BASIC_ROM_ADDR  : std_logic_vector(22 downto 0);
+	signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
+	
+	signal sdram_only_bank : std_logic;
+	
+BEGIN
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			addr_reg <= (others=>'0');
+			state_reg <= state_idle;
+			width_8bit_reg <= '0';
+			width_16bit_reg <= '0';
+			width_32bit_reg <= '0';
+			write_enable_reg <= '0';
+			data_write_reg <= (others=> '0');
+			--sdram_request_reg <= '0';
+			fetch_wait_reg <= (others=>'0');
+
+			cpu_fetch_real_reg <= '0';
+			antic_fetch_real_reg <= '0';	
+	elsif (clk'event and clk='1') then
+			addr_reg <= addr_next;
+			state_reg <= state_next;
+			width_8bit_reg <= width_8bit_next;
+			width_16bit_reg <= width_16bit_next;
+			width_32bit_reg <= width_32bit_next;
+			write_enable_reg <= write_enable_next;
+			data_write_reg <= data_WRITE_next;
+			--sdram_request_reg <= sdram_request_next;
+			fetch_wait_reg <= fetch_wait_next;
+			
+			cpu_fetch_real_reg <= cpu_fetch_real_next;
+			antic_fetch_real_reg <= antic_fetch_real_next;
+		end if;
+	end process;
+	
+	-- ANTIC FETCH
+	
+	-- concept
+	-- bus master sends request - antic or cpu
+	-- antic has priority
+	-- cpu may be idle
+	-- once request complete MEMORY_READY is set
+	-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
+	
+	-- so
+	-- memory_ready <= device_ready;
+	
+	-- problem
+	-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
+	
+	-- state machine
+	
+	-- state machine impl
+	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
+	begin
+		start_request <= '0';
+		notify_antic <= '0';
+		notify_cpu <= '0';
+		notify_zpu <= '0';
+		state_next <= state_reg;
+		fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1);
+
+		addr_next <= addr_reg;
+		data_WRITE_next <= data_WRITE_reg;
+		width_8bit_next <= width_8bit_reg;		
+		width_16bit_next <= width_16bit_reg;		
+		width_32bit_next <= width_32bit_reg;		
+		write_enable_next <= write_enable_reg;
+		
+		antic_fetch_real_next <= antic_fetch_real_reg;
+		cpu_fetch_real_next <= cpu_fetch_real_reg;
+		
+		case state_reg is
+			when state_idle =>
+				fetch_wait_next <= (others=>'0');
+				write_enable_next <= '0';
+				width_8bit_next <= '0';
+				width_16bit_next <= '0';
+				width_32bit_next <= '0';	
+				data_WRITE_next <= (others => '0');
+				addr_next <= zpu_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);				
+				
+				case fetch_priority is
+				when "100"|"101"|"110"|"111" => -- antic wins
+					start_request <= '1';
+					addr_next <= "00000000"&antic_ADDR;
+					width_8bit_next <= '1';					
+					if (request_complete = '1') then
+						notify_antic <= '1';
+					else
+						state_next <= state_waiting_antic;
+					end if;
+					antic_fetch_real_next <= '1';
+				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+					start_request <= '1';
+					addr_next <= zpu_ADDR;
+					data_WRITE_next <= zpu_wRITE_DATA;
+
+					width_8bit_next <= zpu_8BIT_WRITE_ENABLE or (zpu_READ_ENABLE and (zpu_addr(0) or zpu_addr(1)));
+					width_16bit_next <= zpu_16BIT_WRITE_ENABLE;
+					width_32bit_next <= zpu_32BIT_WRITE_ENABLE or (zpu_READ_ENABLE and not(zpu_addr(0) or zpu_addr(1))); -- narrower devices just return 8 bits on read
+					
+					write_enable_next <= not(zpu_READ_ENABLE);
+					
+					if (request_complete = '1') then
+						notify_zpu <= '1';
+					else
+						state_next <= state_waiting_zpu;
+					end if;					
+				when "001" => -- 6502 wins
+					start_request <= '1';
+					addr_next <= "00000000"&cpu_ADDR;
+					data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
+					width_8bit_next <= '1';
+					write_enable_next <= not(cpu_WRITE_N);
+					if (request_complete = '1') then
+						notify_cpu <= '1';
+					else
+						state_next <= state_waiting_cpu;
+					end if;
+					cpu_fetch_real_next <= '1';
+				when "000" =>
+					-- no requests
+				when others =>
+					-- nop
+				end case;
+			when state_waiting_antic =>
+				if (request_complete = '1') then
+					notify_antic <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_zpu =>
+				if (request_complete = '1') then
+					notify_zpu <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_cpu =>
+				if (request_complete = '1') then
+					notify_cpu <= '1';
+					state_next <= state_idle;
+				end if;				
+			when others =>
+				-- NOP
+		end case;
+	end process;
+	
+	-- output
+	MEMORY_READY_ANTIC <= notify_antic;
+	MEMORY_READY_ZPU <= notify_zpu;
+	MEMORY_READY_CPU <= notify_cpu;
+	
+	RAM_REQUEST <= ram_chip_select;
+		
+	SDRAM_REQUEST <= sdram_chip_select;
+	--SDRAM_REQUEST <= sdram_request_next;
+	SDRAM_REFRESH <= '0'; --fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+	SDRAM_READ_EN <= not(write_enable_next);
+	SDRAM_WRITE_EN <= write_enable_next;
+	
+	WIDTH_8bit_ACCESS <= width_8bit_next;
+	WIDTH_16bit_ACCESS <= width_16bit_next;
+	WIDTH_32bit_ACCESS <= width_32bit_next;	
+	
+	WRITE_DATA <= DATA_WRITE_next;
+
+	-- a little sdram glue - move to sdram wrapper? TODO
+	--SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+	
+	-- Calculate which memory area to use
+	extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
+	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+	extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
+	extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
+	extended_access_either <= extended_access_addr and not(portb(4));
+	sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
+	
+	process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
+	begin	
+		extended_bank <= "0000000"&addr_next(15 downto 14);
+		extended_self_test <= '1';
+		
+		case ram_select is
+			when "000" => -- 64k
+				-- default
+			when "001" => -- 128k			
+				if (extended_access_cpu_or_antic='1') then
+					extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
+				end if;
+			when "010" => -- 320k compy shop
+				if (extended_access_cpu_or_antic='1') then
+					extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
+					extended_self_test <= '0';
+				end if;
+			when "011" => -- 320k rambo
+				if (extended_access_either='1')then
+					extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
+				end if;
+			when "100" => -- 576k compy shop
+				if (extended_access_cpu_or_antic='1') then
+					extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
+					extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
+					extended_self_test <= '0';
+				end if;
+			when "101" => -- 576k rambo
+				if (extended_access_either='1') then
+					extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
+					extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
+				end if;
+			when "110" => -- 1088k rambo
+				if (extended_access_either='1') then
+					extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
+					extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
+					extended_self_test <= '0';
+				end if;
+			when "111" => -- 4MB!	
+				if (extended_access_addr='1') then
+					extended_bank(7 downto 0) <= portb(7 downto 0);				
+					extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
+					extended_self_test <= and_reduce(portb(6 downto 4));	 -- which means self-test is in the middle of half the banks - euuugh, oh well!						
+				end if;
+			when others =>
+				-- TODO - portc!
+		end case;
+	end process;
+
+	
+	-- SRAM memory map (512k)
+	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
+	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP)
+	-- SDRAM memory map (8MB)
+	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
+	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP) 
+	-- to 4MB RAM    - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
+	-- +64k          - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
+	-- SCRATCH       - 4MB+64k-5MB
+	-- CARTS         -              "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
+	SDRAM_CART_ADDR      <= "101"&cart_select& "0000000000000";
+	-- BASIC/OS ROM  -              "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K				
+	SDRAM_BASIC_ROM_ADDR <= "111"&"000000"   &"00000000000000";
+	SDRAM_OS_ROM_ADDR    <= "111"&rom_select &"00000000000000";
+	-- SYSTEM        -              "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
+	
+  	process(
+		-- address and writing absolutely points us at a device
+		ADDR_next,WRITE_enable_next, 
+	
+		-- except for these additional special address bits	
+		portb, 
+		antic_fetch,
+		rom_select,
+		ram_select,cart_rd4,cart_rd5,
+		use_sdram,
+		
+		-- input data from n sources
+		GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
+		CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_POKEY2_DATA,CACHE_ANTIC_DATA,
+		
+		-- input data from n sources complete?
+		-- hardware regs take 1 cycle, so always complete		
+		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+		
+		-- on new access this is set - we must select the appropriate device - for this cycle only
+		start_request,
+		
+		rom_in_ram,
+		
+		-- SDRAM base addresses
+		extended_self_test,extended_bank,sdram_only_bank,
+		SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
+		
+	)
+	begin
+		MEMORY_DATA <= (others => '1');
+		
+		ROM_ADDR <= (others=>'0');
+		RAM_ADDR <= addr_next(18 downto 0);
+		SDRAM_ADDR <= addr_next(22 downto 0);
+		
+		PBI_ADDR <= ADDR_next(15 downto 0);
+		
+		request_complete <= '0';
+		
+		GTIA_WR_ENABLE <= '0';
+		POKEY_WR_ENABLE <= '0';
+		POKEY2_WR_ENABLE <= '0';
+		ANTIC_WR_ENABLE <= '0';
+		PIA_WR_ENABLE <= '0';
+		PIA_RD_ENABLE <= '0';
+		PBI_WR_ENABLE <= '0';
+		D6_WR_ENABLE <= '0';
+
+		RAM_WR_ENABLE <= write_enable_next;
+		SDRAM_WRITE_EN <= write_enable_next;		
+		
+		CART_S4_n <= '1';
+		CART_S5_n <= '1';
+		CART_CCTL_n <= '1';
+		
+		rom_request <= '0';
+		cart_request <= '0';
+		
+		ram_chip_select <= '0';
+		sdram_chip_select <= '0';
+		
+		rom_in_ram <= '1';
+
+	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+		if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+
+		SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
+		SDRAM_ADDR(22 downto 14) <= extended_bank;
+		RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
+		RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
+					
+		if ((use_sdram or sdram_only_bank)='1') then
+			MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+			sdram_chip_select <= start_request;
+			request_complete <= sdram_request_COMPLETE;														
+		else
+			MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+			ram_chip_select <= start_request;
+			request_complete <= ram_request_COMPLETE;									
+		end if;
+		
+		case addr_next(15 downto 8) is 
+				-- GTIA
+				when X"D0" =>
+					GTIA_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';
+			
+				-- POKEY
+				when X"D2" =>				
+					if (addr_next(4) = '0') then
+						POKEY_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY_DATA;
+					else
+						POKEY2_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
+					end if;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';					
+
+				-- PIA
+				when X"D3" =>
+					PIA_WR_ENABLE <= write_enable_next;
+					PIA_RD_ENABLE <= '1';
+					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';					
+					
+				-- ANTIC
+				when X"D4" =>
+					ANTIC_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';					
+					
+				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+				when X"D5" =>
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';				
+					if ((CART_RD4 or CART_RD5) = '1') then
+						PBI_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_CCTL_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						MEMORY_DATA(7 downto 0) <= X"FF";
+						request_complete <= '1';
+					end if;
+					
+				when X"D6" =>
+					D6_WR_ENABLE <= write_enable_next;
+					-- TODO - should this still have RAM with covox here?
+										
+				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+				when 
+					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+									
+					if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';	
+						
+						if (rom_in_ram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						else
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+						end if;
+						
+						if (write_enable_next = '1') then
+							request_complete <= '1';
+						else
+							if (rom_in_ram = '1') then
+								request_complete <= sdram_request_COMPLETE;							
+								sdram_chip_select <= start_request;							
+							else
+								request_complete <= rom_request_COMPLETE;							
+								rom_request <= start_request;															
+							end if;
+						end if;
+						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
+						SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
+						ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k						
+					end if;
+				
+				-- 0x80 cart
+				when
+					X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
+					|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
+		
+					if (cart_rd4 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						rom_request <= start_request;
+						CART_S4_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';							
+					end if;	
+			
+				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+				when 
+					X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
+					|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
+					
+					if (cart_rd5 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_S5_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';													
+					else
+						if (portb(1) = '0') then
+							sdram_chip_select <= '0';
+							ram_chip_select <= '0';							
+							--request_complete <= ROM_REQUEST_COMPLETE;
+							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+							--rom_request <= start_request;					
+							if (rom_in_ram = '1') then
+								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							else
+								MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+							end if;
+							if (write_enable_next = '1') then
+								request_complete <= '1';
+							else
+								if (rom_in_ram = '1') then
+									request_complete <= sdram_request_COMPLETE;							
+									sdram_chip_select <= start_request;							
+								else
+									request_complete <= rom_request_COMPLETE;							
+									rom_request <= start_request;															
+								end if;
+							end if;
+						
+							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+						 SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
+						 SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k							
+						end if;
+					end if;
+					
+				-- OS ROM 0xc00->0xcff				
+				-- OS ROM d800->0xfff
+				when 
+					X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
+					|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
+					|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
+					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+					
+					if (portb(0) = '1') then
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';																		
+						--request_complete <= ROM_REQUEST_COMPLETE;
+						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						--rom_request <= start_request;					
+						if (rom_in_ram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						else
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+						end if;
+						if (write_enable_next = '1') then
+							request_complete <= '1';
+						else
+								if (rom_in_ram = '1') then
+									request_complete <= sdram_request_COMPLETE;							
+									sdram_chip_select <= start_request;							
+								else
+									request_complete <= rom_request_COMPLETE;							
+									rom_request <= start_request;															
+								end if;						
+						end if;																			
+
+						ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
+						SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
+					end if;
+					
+				when others =>
+			end case;				
+		else		
+			sdram_chip_select <= '0';
+			ram_chip_select <= '0';													
+			case addr_next(23 downto 21) is			
+				when "000" =>				
+					-- internal area for zpu, never happens!
+				when "001" => -- sram, 512K
+					MEMORY_DATA(15 downto 0) <= RAM_DATA;
+					ram_chip_select <= start_request;
+					request_complete <= ram_request_COMPLETE;									
+					RAM_ADDR <= addr_next(18 downto 0);
+
+				when "010"|"011" => -- flash rom, 4MB
+					request_complete <= ROM_REQUEST_COMPLETE;
+					MEMORY_DATA(7 downto 0) <= ROM_DATA;
+					rom_request <= start_request;
+					ROM_ADDR <= addr_next(21 downto 0);
+					
+				when "100"|"101"|"110"|"111" => -- sdram, 8MB
+					MEMORY_DATA <= SDRAM_DATA;
+					sdram_chip_select <= start_request;
+					request_complete <= sdram_request_COMPLETE;	
+					SDRAM_ADDR <= addr_next(22 downto 0);				
+				when others =>
+					-- NOP
+			end case;
+		end if;
+		
+--		case addr_next(15 downto 0) is
+--			when X"FFFC" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"FFFD" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0600" => --JSR 0610
+--				MEMORY_DATA(7 downto 0) <= X"20";
+--			when X"0601" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0602" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0603" => --JMP
+--				MEMORY_DATA(7 downto 0) <= X"4C";
+--			when X"0604" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"0605" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
+--				MEMORY_DATA(7 downto 0) <= X"AD";
+--			when X"0611" =>
+--				MEMORY_DATA(7 downto 0) <= X"0A";
+--			when X"0612" =>
+--				MEMORY_DATA(7 downto 0) <= X"D2";
+--			when X"0613" =>
+--				MEMORY_DATA(7 downto 0) <= X"85";
+--			when X"0614" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0615" =>
+--				MEMORY_DATA(7 downto 0) <= X"44";
+--			when X"0616" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0617" =>
+--				MEMORY_DATA(7 downto 0) <= X"60";
+--			when others =>
+--		end case;
+			
+	end process;
+END vhdl;
Index: common/a8core/antic.vhdl
===================================================================
--- common/a8core/antic.vhdl	(nonexistent)
+++ common/a8core/antic.vhdl	(revision 1)
@@ -0,0 +1,1844 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+USE ieee.math_real.log2;
+USE ieee.math_real.ceil;
+
+ENTITY antic IS
+GENERIC
+(
+	cycle_length : integer := 16; -- or 32...
+)
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	MEMORY_READY_ANTIC : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	ANTIC_ENABLE_179 : IN std_logic;
+	
+	PAL : IN STD_LOGIC;
+	
+	lightpen : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	NMI_N_OUT : OUT std_logic;
+	ANTIC_READY : OUT std_logic; -- taken low by wsync writes
+	
+	-- GTIA interface
+	AN : OUT STD_LOGIC_VECTOR(2 downto 0);
+	COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
+	COLOUR_CLOCK_OUT : out std_logic;
+	HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
+	
+	-- DMA fetch
+	dma_fetch_out : out std_logic;
+	dma_address_out : out std_logic_vector(15 downto 0);
+	
+	-- refresh
+	refresh_out : out std_logic; -- used by sdram
+	
+	-- for debugging
+	dma_clock_out : out std_logic;
+	hcount_out : out std_logic_vector(7 downto 0);
+	vcount_out : out std_logic_vector(8 downto 0)
+);
+END antic;
+
+ARCHITECTURE vhdl OF antic IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT antic_dma_clock IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		enable_dma : IN STD_LOGIC;
+		
+		playfield_start : in std_logic;
+		playfield_end : in std_logic;
+		vblank : in std_logic;
+		
+		slow_dma : in std_logic;
+		medium_dma : in std_logic;
+		fast_dma : in std_logic;
+				
+		dma_clock_out_0 : out std_logic;
+		dma_clock_out_1 : out std_logic;
+		dma_clock_out_2 : out std_logic;
+		dma_clock_out_3 : out std_logic
+	);
+	END component;
+	
+	component antic_counter IS
+	generic
+	(
+		STORE_WIDTH : natural := 1;
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+		
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;	
+
+	component reg_file IS
+	generic
+	(
+		BYTES : natural := 1;
+		WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal enable_dma : std_logic;
+	signal dma_clock_character_name : std_logic;
+	signal dma_clock_character_inc : std_logic;
+	signal dma_clock_bitmap_data : std_logic;
+	signal dma_clock_character_data : std_logic;
+	
+	signal wsync_next : std_logic;
+	signal wsync_reg : std_logic;
+	signal wsync_reset : std_logic;
+	signal wsync_write : std_logic;
+	signal wsync_delayed_write : std_logic;
+	
+	signal nmi_next : std_logic;
+	signal nmi_reg : std_logic;
+	
+	signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
+	signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
+	
+	signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
+	signal nmist_reg : std_logic_vector(7 downto 5);
+	
+	signal nmist_reset : std_logic;
+	
+	signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
+	signal nmien_raw_reg : std_logic_vector(7 downto 6);
+	signal nmien_delayed_reg : std_logic_vector(7 downto 6);
+	
+	signal dli_nmi_next : std_logic;
+	signal vbi_nmi_next : std_logic;
+	signal dli_nmi_reg : std_logic;
+	signal vbi_nmi_reg : std_logic;
+	
+	signal nmi_reset : std_logic;
+	--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
+	--signal nmi_pending_reg : std_logic;
+	
+	signal playfield_dma_start : std_logic;
+	signal playfield_dma_end : std_logic;
+	signal playfield_display_active_next : std_logic;
+	signal playfield_display_active_reg : std_logic;
+	
+	signal dmactl_raw_next : std_logic_vector(6 downto 0);
+	signal dmactl_raw_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_enabled : std_logic;
+	
+	signal chactl_next : std_logic_vector(2 downto 0);
+	signal chactl_reg : std_logic_vector(2 downto 0);
+	
+	-- dma is only allowed during certain portions of the display
+	signal allow_real_dma_next : std_logic;
+	signal allow_real_dma_reg : std_logic;
+	
+	-- dma fetch handling
+	-- dma is scheduled one cycle before it happens, so that registers can directly drive output	
+	signal dma_fetch_next : std_logic;
+	signal dma_fetch_reg : std_logic;
+	signal dma_address_next : std_logic_vector(15 downto 0);
+	signal dma_address_reg : std_logic_vector(15 downto 0);
+	
+	constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
+	constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
+	constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
+	constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
+	constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
+	constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
+	signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
+	signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
+	signal dma_fetch_request : std_logic;
+	
+	signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
+	signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
+	
+	signal character_next : std_logic_vector(7 downto 0);
+	signal character_reg : std_logic_vector(7 downto 0);
+
+	signal displayed_character_next : std_logic_vector(7 downto 0);
+	signal displayed_character_reg : std_logic_vector(7 downto 0);
+	
+	-- instruction decode
+	signal instruction_next : std_logic_vector(7 downto 0);
+	signal instruction_reg : std_logic_vector(7 downto 0);
+	
+	signal first_line_of_instruction_next : std_logic;
+	signal first_line_of_instruction_reg: std_logic;
+
+	signal last_line_of_instruction_live : std_logic;
+	signal last_line_of_instruction_next : std_logic;
+	signal last_line_of_instruction_reg: std_logic;
+	
+	signal force_final_row : std_logic;
+	
+	signal instruction_blank_reg : std_logic;
+	signal instruction_blank_next : std_logic;
+
+	--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
+	--signal dma_speed_next : dma_speed_type;
+	--signal dma_speed_reg : dma_speed_type;
+	constant no_dma : std_logic_vector(1 downto 0) := "00";
+	constant slow_dma : std_logic_vector(1 downto 0) := "01";
+	constant medium_dma : std_logic_vector(1 downto 0) := "10";
+	constant fast_dma : std_logic_vector(1 downto 0) := "11";
+	signal dma_speed_next : std_logic_vector(1 downto 0);
+	signal dma_speed_reg : std_logic_vector(1 downto 0);
+	signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
+	
+	--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
+	--signal instruction_type_next : instruction_type;
+	--signal instruction_type_reg : instruction_type;
+	constant mode_character : std_logic_vector(2 downto 0) := "000";
+	constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
+	constant mode_jvb : std_logic_vector(2 downto 0) := "010";
+	constant mode_jump : std_logic_vector(2 downto 0) := "011";
+	constant mode_blank : std_logic_vector(2 downto 0) := "100";
+	signal instruction_type_next : std_logic_vector(2 downto 0);
+	signal instruction_type_reg : std_logic_vector(2 downto 0);
+	
+	signal two_part_instruction_next : std_logic;
+	signal two_part_instruction_reg : std_logic;
+
+		-- e.g. if instruction is 8 lines long then the final row is 7
+	signal instruction_final_row_next : std_logic_vector(3 downto 0);
+	signal instruction_final_row_reg : std_logic_vector(3 downto 0);
+		
+	--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
+	--signal shift_rate_next : shift_rate_type;
+	--signal shift_rate_reg : shift_rate_type;
+	constant slow_shift : std_logic_vector(1 downto 0) := "00";
+	constant medium_shift : std_logic_vector(1 downto 0) := "01";
+	constant fast_shift : std_logic_vector(1 downto 0) := "10";
+	signal shift_rate_next : std_logic_vector(1 downto 0);
+	signal shift_rate_reg : std_logic_vector(1 downto 0);
+	
+	signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
+	signal shift_twobit_reg : std_logic;
+	
+	signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
+	signal twopixel_reg : std_logic;	
+	
+	signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
+	signal single_colour_character_reg : std_logic;
+
+	signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
+	signal multi_colour_character_reg : std_logic;
+	
+	signal twoline_character_next : std_logic; -- for antic 5/7
+	signal twoline_character_reg : std_logic;
+	
+	signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
+	signal map_background_reg : std_logic;
+	
+	signal dli_enabled_next : std_logic;
+	signal dli_enabled_reg : std_logic;
+	
+	signal descenders_next : std_logic; -- for mode 3
+	signal descenders_reg : std_logic;
+		
+	-- Shift register used to output to AN2-AN0	
+	-- Can either be loaded from memory or from the line buffer
+	signal display_shift_next : std_logic_vector(7 downto 0);
+	signal display_shift_reg : std_logic_vector(7 downto 0);
+	
+	signal delay_display_shift_next : std_logic_vector(24 downto 0);
+	signal delay_display_shift_reg : std_logic_vector(24 downto 0);
+	
+	signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
+	
+	signal load_display_shift_from_memory : std_logic;
+	signal load_display_shift_from_line_buffer : std_logic;
+	
+	signal enable_shift : std_logic;
+	signal shiftclock_next : std_logic_vector(3 downto 0);
+	signal shiftclock_reg : std_logic_vector(3 downto 0);
+	
+	signal playfield_reset : std_logic;
+	signal playfield_load : std_logic;
+	
+	-- position in frame	
+	signal hcount_next : std_logic_vector(7 downto 0);
+	signal hcount_reg : std_logic_vector(7 downto 0);
+	
+	signal vcount_next : std_logic_vector(8 downto 0);
+	signal vcount_reg : std_logic_vector(8 downto 0);
+	
+	signal vblank_next : std_logic;
+	signal vblank_reg : std_logic;
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
+	
+	signal hcount_reset : std_logic;
+	signal vcount_reset : std_logic;
+	signal vcount_increment : std_logic;
+	
+	-- scrolling	
+	signal hscrol_reg : std_logic_vector(3 downto 0);
+	signal hscrol_next : std_logic_vector(3 downto 0);
+
+	signal vscrol_raw_reg : std_logic_vector(3 downto 0);
+	signal vscrol_raw_next : std_logic_vector(3 downto 0);
+	signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
+	
+	signal vscrol_enabled_reg : std_logic;
+	signal vscrol_enabled_next : std_logic;
+	signal vscrol_last_enabled_reg : std_logic;
+	signal vscrol_last_enabled_next : std_logic;
+	
+	signal update_row_count : std_logic;
+	
+	signal hscrol_enabled_reg : std_logic;
+	signal hscrol_enabled_next : std_logic;
+
+	-- refresh
+	signal refresh_pending_next : std_logic;
+	signal refresh_pending_reg : std_logic;
+
+	signal refresh_fetch_next : std_logic;
+	signal refresh_fetch_reg : std_logic;
+	
+	-- Counter signals
+	signal increment_display_list_address : std_logic;
+	signal load_display_list_address : std_logic;
+	signal display_list_address_next : std_logic_vector(15 downto 0);
+	signal display_list_address_reg : std_logic_vector(15 downto 0);
+	signal load_display_list_address_cpu : std_logic;
+	signal load_display_list_address_dma : std_logic;
+	signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
+	signal display_list_address_next_dma : std_logic_vector(15 downto 0);	
+
+	signal increment_memory_scan_address : std_logic;
+	signal load_memory_scan_address : std_logic;
+	signal memory_scan_address_next : std_logic_vector(15 downto 0);
+	signal memory_scan_address_reg : std_logic_vector(15 downto 0);
+
+	signal increment_line_buffer_address : std_logic;
+	signal load_line_buffer_address : std_logic;
+	signal line_buffer_address_next : std_logic_vector(7 downto 0);
+	signal line_buffer_address_reg : std_logic_vector(7 downto 0);
+
+	signal increment_row_count : std_logic;
+	signal load_row_count : std_logic;
+	signal row_count_next : std_logic_vector(3 downto 0);
+	signal row_count_reg : std_logic_vector(3 downto 0);
+
+	signal increment_refresh_count : std_logic;
+	signal load_refresh_count : std_logic;
+	signal refresh_count_next : std_logic_vector(3 downto 0);
+	signal refresh_count_reg : std_logic_vector(3 downto 0);
+	
+	signal pmbase_reg : std_logic_vector(7 downto 2);
+	signal pmbase_next : std_logic_vector(7 downto 2);
+
+	signal chbase_raw_reg : std_logic_vector(7 downto 1);
+	signal chbase_raw_next : std_logic_vector(7 downto 1);
+	signal chbase_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal line_buffer_write : std_logic;
+	signal line_buffer_data_in : std_logic_vector(7 downto 0);
+	signal line_buffer_data_out : std_logic_vector(7 downto 0);
+	
+	-- output registers
+	signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
+	signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
+	signal an_prev_reg : std_logic_vector(2 downto 0);  -- previous - for hscrol
+	signal an_next : std_logic_vector(2 downto 0);
+	signal an_reg : std_logic_vector(2 downto 0);
+	
+	-- light pendin
+	signal penv_next : std_logic_vector(7 downto 0);
+	signal penv_reg : std_logic_vector(7 downto 0);
+	signal penh_next : std_logic_vector(7 downto 0);
+	signal penh_reg : std_logic_vector(7 downto 0);
+	
+	-- high res modes
+	signal colour_clock_8x : std_logic;
+	signal colour_clock_4x : std_logic;
+	signal colour_clock_2x : std_logic;
+	signal colour_clock_1x : std_logic;
+	signal colour_clock_half_x : std_logic;
+	signal colour_clock_selected : std_logic;
+	signal colour_clock_selected_highres : std_logic;
+	
+	CONSTANT cycle_length_bits: integer = integer(ceil(log2(1.0*cycle_length)));
+	signal colour_clock_count_next : std_logic_vector(cycle_length_bits-1 downto 0);
+	signal colour_clock_count_reg : std_logic_vector(cycle_length_bits-1 downto 0);
+	
+	signal memory_ready_both : std_logic;
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			nmi_reg <= '0';
+			wsync_reg <= '0';
+			vcount_reg <= (others=>'0');
+			--hcount_reg <= X"01";
+			hcount_reg <= X"00";
+			dmactl_raw_reg <= (others=>'0');
+			chactl_reg <= (others=>'0');
+			vblank_reg <= '0';			
+			vsync_reg <= '0';
+			pmbase_reg <= (others=>'0');
+			allow_real_dma_reg <= '0';
+			display_shift_reg <= (others=>'0');
+			chbase_raw_reg <= (others=>'0');
+			
+			instruction_reg <= (others=>'0');
+			first_line_of_instruction_reg <= '0';
+			last_line_of_instruction_reg <= '0';
+			dma_speed_reg <= no_dma;
+			instruction_type_reg <= mode_blank;
+			instruction_final_row_reg <= (others=>'0');
+			shift_rate_reg <= slow_shift;
+			shift_twobit_reg <= '0';
+			twopixel_reg <= '0';
+			single_colour_character_reg <= '0';
+			multi_colour_character_reg <= '0';
+			twoline_character_reg <= '0';
+			map_background_reg <= '0';
+			dli_enabled_reg <= '0';
+			two_part_instruction_reg <= '0';
+			descenders_reg <='0';
+			
+			hscrol_reg <= (others=>'0');
+			vscrol_raw_reg <= (others=>'0');			
+			vscrol_enabled_reg <= '0';
+			vscrol_last_enabled_reg <= '0';
+			hscrol_enabled_reg <= '0';
+			
+			shiftclock_reg <= (others=>'0');
+			
+			hblank_reg <= '0';
+			
+			an_reg <= (others=>'0');
+			an_prev_reg <= (others=>'0');
+			
+			dma_fetch_reg <= '0';
+			dma_address_reg <= (others=>'0');			
+			dma_fetch_destination_reg <= dma_fetch_null;
+			
+			playfield_display_active_reg <= '0';
+			
+			instruction_blank_reg <= '0';
+			
+			display_list_address_low_temp_reg <= (others=>'0');
+			
+			character_reg <= (others=>'0');
+			displayed_character_reg <= (others=>'0');
+			
+			refresh_pending_reg <= '0';
+			refresh_fetch_reg <= '0';
+			
+			--nmi_pending_reg <= '0';
+			
+			dli_nmi_reg <= '0';
+			vbi_nmi_reg <= '0';
+			nmien_raw_reg <= (others=>'0');
+			
+			delay_display_shift_reg <= (others=>'0');
+			
+			nmi_shiftreg_reg <= (others=>'1');
+			
+			penh_reg <= (others=>'0');
+			penv_reg <= (others=>'0');
+			
+			colour_clock_count_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then			
+			nmi_reg <= nmi_next;
+			wsync_reg <= wsync_next;
+			vcount_reg <= vcount_next;
+			hcount_reg <= hcount_next;
+			nmist_reg <= nmist_next;
+			dmactl_raw_reg <= dmactl_raw_next;
+			chactl_reg <= chactl_next;
+			vblank_reg <= vblank_next;
+			vsync_reg <= vsync_next;
+			pmbase_reg <= pmbase_next;
+			allow_real_dma_reg <= allow_real_dma_next;
+			display_shift_reg <= display_shift_next;
+			chbase_raw_reg <= chbase_raw_next;
+			
+			instruction_reg <= instruction_next;
+			first_line_of_instruction_reg <= first_line_of_instruction_next;
+			last_line_of_instruction_reg <= last_line_of_instruction_next;
+			dma_speed_reg <= dma_speed_next;
+			instruction_type_reg <= instruction_type_next;
+			instruction_final_row_reg <= instruction_final_row_next;
+			shift_rate_reg <= shift_rate_next;
+			shift_twobit_reg <= shift_twobit_next;
+			twopixel_reg <= twopixel_next;
+			single_colour_character_reg <= single_colour_character_next;
+			multi_colour_character_reg <= multi_colour_character_next;
+			twoline_character_reg <= twoline_character_next;
+			map_background_reg <= map_background_next;
+			dli_enabled_reg <= dli_enabled_next;
+			two_part_instruction_reg <= two_part_instruction_next;
+			descenders_reg <= descenders_next;
+			
+			hscrol_reg <= hscrol_next;
+			vscrol_raw_reg <= vscrol_raw_next;	
+			vscrol_enabled_reg <= vscrol_enabled_next;
+			vscrol_last_enabled_reg <= vscrol_last_enabled_next;
+			hscrol_enabled_reg <= hscrol_enabled_next;
+			
+			shiftclock_reg <= shiftclock_next;
+			
+			hblank_reg <= hblank_next;
+			
+			an_reg <= an_next;
+			an_prev_reg <= an_prev_next;
+			
+			dma_fetch_reg <= dma_fetch_next;
+			dma_address_reg <= dma_address_next;
+			dma_fetch_destination_reg <= dma_fetch_destination_next;
+			
+			playfield_display_active_reg <= playfield_display_active_next;
+			
+			instruction_blank_reg <= instruction_blank_next;
+			
+			display_list_address_low_temp_reg <= display_list_address_low_temp_next;
+			
+			character_reg <= character_next;
+			displayed_character_reg <= displayed_character_next;
+			
+			refresh_pending_reg <= refresh_pending_next;
+			refresh_fetch_reg <= refresh_fetch_next;
+						
+			dli_nmi_reg <= dli_nmi_next;
+			vbi_nmi_reg <= vbi_nmi_next;
+			nmien_raw_reg <= nmien_raw_next;
+			
+			delay_display_shift_reg <= delay_display_shift_next;
+			
+			nmi_shiftreg_reg <= nmi_shiftreg_next;
+			
+			penh_reg <= penh_next;
+			penv_reg <= penv_next;
+			
+			colour_clock_count_reg <= colour_clock_count_next;
+		end if;
+	end process;
+	
+	-- Colour clock (3.57MHz for PAL)
+	-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
+	-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
+	--enable_colour_clock_div : enable_divider
+		--generic map (COUNT=>7)
+		--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);	
+	process(colour_clock_count_reg, ANTIC_ENABLE_179)		
+	begin
+		colour_clock_half_x <= '0';
+		colour_clock_1x<='0';
+		colour_clock_2x<='0';
+		colour_clock_4x<='0';
+		colour_clock_8x<='0';
+	
+		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+		
+		if (ANTIC_ENABLE_179 = '1') then -- resync...
+			colour_clock_count_next <= std_logic_vector(to_unsigned(1,cycle_length_bits));
+		end if;
+
+		colour_clock_8x <= '1';
+		
+		if (or_reduce(colour_clock_count_reg( cycle_count_bits-4 downto 0) = '0') then
+			case colour_clock_count_reg(cycle_count_bits-1 downto cycle_count_bits-3) is
+			when "000" =>
+				colour_clock_half_x <= '1';
+				colour_clock_1x <= '1';
+				colour_clock_2x <= '1';
+				colour_clock_4x <= '1';
+			when "001" =>
+				colour_clock_4x <= '1';
+			when "010" =>
+				colour_clock_2x <= '1';			
+				colour_clock_4x <= '1';			
+			when "011" =>
+				colour_clock_4x <= '1';
+			when "100" =>			
+				colour_clock_1x <= '1';
+				colour_clock_2x <= '1';
+				colour_clock_4x <= '1';
+			when "101" =>
+				colour_clock_4x <= '1';
+			when "110" =>
+				colour_clock_2x <= '1';			
+				colour_clock_4x <= '1';			
+			when "111" =>
+				colour_clock_4x <= '1';			
+			when others =>
+				-- nop
+			end case;
+		end if;
+	end process;
+	
+	process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
+	begin
+		enable_dma <= colour_clock_half_x;
+		colour_clock_selected <= colour_clock_1x;
+		colour_clock_selected_highres <= colour_clock_2x;		
+		dmactl_delayed_enabled <= '0';
+		
+		case dmactl_delayed_reg(6 downto 5) is
+		when "01" =>
+			dmactl_delayed_enabled <= '1';
+		when "10" =>
+			enable_dma <= colour_clock_1x;
+			colour_clock_selected <= colour_clock_2x;		
+			colour_clock_selected_highres <= colour_clock_4x;
+			dmactl_delayed_enabled <= '1';
+		when "11" =>
+			enable_dma <= colour_clock_2x;
+			colour_clock_selected <= colour_clock_4x;
+			colour_clock_selected_highres <= colour_clock_8x;
+			dmactl_delayed_enabled <= '1';
+		when others =>
+			--nop
+		end case;		
+	end process;	
+		
+	--enable_dma_clock_div : enable_divider
+	--	generic map (COUNT=>2)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>colour_clock_selected,enable_out=>enable_dma);		
+
+	-- Counters (memory address for data, memory address for display list)
+	antic_counter_memory_scan : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
+		
+	load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
+	display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
+	antic_counter_display_list : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
+	antic_counter_line_buffer : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
+	antic_counter_row_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
+	antic_counter_refresh_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
+	
+	-- Count position on screen
+	-- horizontal
+	process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
+	begin
+		hcount_next <= hcount_reg;		
+		if (colour_clock_1x = '1') then
+			hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
+			
+			if (colour_clock_half_x = '1') then
+				hcount_next(0) <= '1';
+			end if;
+		end if;
+		
+		if (hcount_reset = '1') then
+			hcount_next <= (others=>'0');
+		end if;
+	end process;
+	
+	-- vertical
+	process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
+	begin
+		vcount_next <= vcount_reg;
+		
+		if (colour_clock_1x = '1') then		
+			if (vcount_increment = '1') then
+				vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
+			end if;
+			
+			if (vcount_reset = '1') then
+				vcount_next <= (others=>'0');
+			end if;
+		end if;
+	end process;	
+	
+	-- Actions done based on vertical position		
+	process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
+	begin
+		vblank_next <= vblank_reg;
+		vsync_next <= vsync_reg;
+		vcount_reset <= '0';
+	
+		if (colour_clock_1x='1') then
+			case vcount_reg is
+				when '0'&X"08" => 
+					vblank_next <= '0';
+				when '0'&X"F8" =>
+					vblank_next <= '1';
+				--when '1'&X"05" => (changed for testing galaxian!)
+				--	vblank_next <= '1';					
+-- PAL
+				when '1'&X"16" =>
+					vsync_next <= pal;
+				when '1'&X"19" =>
+					vsync_next <= '0';
+				when '1'&X"38" =>
+					vcount_reset <= '1'; -- Blip at 9c..., then wrap
+-- NTSC
+				when '0'&X"FA" =>
+					vsync_next <= not(pal);
+				when '0'&X"FD" =>
+					vsync_next <= '0';
+				when '1'&X"06" =>
+					vcount_reset <= not(pal); -- Blip at 9c..., then wrap
+				when others =>
+					-- nothing
+			end case;
+		end if;
+	end process;
+	
+	-- Calculate playfield start/end
+	process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
+	begin		
+		playfield_dma_start_cycle <= (others=>'1');
+		playfield_dma_end_cycle <= (others=>'1');
+		playfield_display_start_cycle <= (others=>'1');
+		playfield_display_end_cycle <= (others=>'1');
+		
+		-- DMA clock start/end
+		-- wide=3, normal=2, narrow=1
+		-- Playfield start is at (in colour clocks):
+		-- 68 + hscrol&FE - width*16
+		-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
+		-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong... 
+		-- e.g. if its 64 then we may be able to do something like base&width&
+		-- Playfield end is at (in colour clocks):
+		-- 164 + hscrol&FE + width*16
+		-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
+		
+		-- hscrol interfers with playfield dma width (for dma purposes only!)
+		if (hscrol_enabled_reg='1') then
+			case dmactl_delayed_reg(1 downto 0) is
+				when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
+					playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20  (10 in machine cycles)
+					playfield_dma_end_cycle   <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
+				when "01" => -- narrow - traated as normal due to hscrol
+					playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36  (18 in machine cycles)
+					playfield_dma_end_cycle <=   X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
+				when others =>
+					-- nothing
+			end case;
+		else
+			case dmactl_delayed_reg(1 downto 0) is
+				when "11" => -- wide
+					playfield_dma_start_cycle <= X"11";
+					playfield_dma_end_cycle   <= X"D0";
+				when "10" => -- normal
+					playfield_dma_start_cycle <= X"21";
+					playfield_dma_end_cycle   <= X"C0";
+				when "01" => -- narrow
+					playfield_dma_start_cycle <= X"31";
+					playfield_dma_end_cycle <=   X"B0";
+				when others =>
+					-- nothing
+			end case;		
+		end if;
+
+		-- background colour outside this area...
+		-- TODO - review these locations - should be clear due to garbage!
+		case dmactl_delayed_reg(1 downto 0) is
+			when "11" => -- wide
+				playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
+				if (hscrol_reg > X"C") then
+					playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol				
+				end if;
+				playfield_display_end_cycle   <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
+			when "10" => -- normal
+				playfield_display_start_cycle <= X"2F";
+				playfield_display_end_cycle   <= X"CF";
+			when "01" => -- narrow
+				playfield_display_start_cycle <= X"3F";
+				playfield_display_end_cycle <=   X"BF";
+			when others =>
+				-- nothing
+		end case;				
+	end process;
+	
+	-- Actions done based on horizontal position - notably dma!
+	process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, displayed_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg)
+	begin
+		allow_real_dma_next <= allow_real_dma_reg;
+
+		playfield_dma_start <= '0';
+		playfield_dma_end <= '0';
+		playfield_display_active_next <= playfield_display_active_reg;
+		
+		dma_fetch_request <= '0';
+		dma_address_next <= dma_address_reg;
+		dma_fetch_destination_next <= dma_fetch_destination_reg;
+		
+		first_line_of_instruction_next <= first_line_of_instruction_reg;
+		last_line_of_instruction_next <= last_line_of_instruction_reg;
+		
+		load_display_shift_from_line_buffer <= '0';
+				
+		increment_memory_scan_address <= '0';
+		
+		line_buffer_address_next <= (others=>'0');
+		load_line_buffer_address <= '0';
+		increment_line_buffer_address <= '0';
+		
+		playfield_load <= '0';
+		
+		hblank_next <= hblank_reg;
+		hcount_reset <= '0';
+		
+		vcount_increment <= '0';
+		
+		character_next <= character_reg;
+		displayed_character_next <= displayed_character_reg;
+		
+		dli_nmi_next <= dli_nmi_reg;
+		vbi_nmi_next <= vbi_nmi_reg;
+		wsync_reset <= '0';
+		
+		load_refresh_count <= '0';
+		refresh_count_next <= (others=>'0');
+		
+		update_row_count <= '0'; 
+		vscrol_last_enabled_next <= vscrol_last_enabled_reg;
+	
+		if (colour_clock_1x = '1') then	
+			-- Playfield start/end
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
+				playfield_dma_start <= '1';				
+				load_line_buffer_address <= '1';
+			end if;
+			
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
+				playfield_dma_end <= '1';
+			end if;	
+			
+			if (hcount_reg = playfield_display_start_cycle) then
+				playfield_display_active_next <= '1';				
+			end if;
+			
+			if (hcount_reg = playfield_display_end_cycle) then
+				playfield_display_active_next <= '0';
+			end if;	
+
+			if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
+				if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
+					dma_fetch_request <= '1';
+				end if;				
+
+				if (twoline_character_reg='1') then
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				else
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				end if;
+				
+				displayed_character_next <= character_reg;
+				
+				-- TODO
+				-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.				
+				dma_fetch_destination_next <= dma_fetch_shiftreg;
+				
+				load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);								
+				increment_line_buffer_address <= '1';
+			end if;						
+		
+			case hcount_reg is 		
+				when X"00" => -- missile DMA, if missile or player DMA enabled					
+					dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;									
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"02" => -- display list dma if enabled
+					first_line_of_instruction_next <= '0';
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- suppress when waiting for vblank
+						first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
+					else				
+						if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
+							dma_fetch_request <= dmactl_delayed_enabled;
+							dma_address_next <= display_list_address_reg;
+							dma_fetch_destination_next <= dma_fetch_instruction;									
+							
+							first_line_of_instruction_next <= '1';						
+							
+							vscrol_last_enabled_next <= vscrol_enabled_reg;
+						end if;
+					end if;					
+				
+				when X"03" =>				
+					update_row_count <= '1'; -- done after instruction fetch...
+					
+				when X"04"|X"06"|X"08"|X"0A" =>  -- player DMA, if enabled
+					dma_fetch_request <= dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;	
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"0C" => -- lms lower byte dma if display list dma enabled?;
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_low;
+				
+				when X"0E" => -- lms upper byte dma if display list dma enabled?
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_high;
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
+						first_line_of_instruction_next <= '0';
+					end if;
+					
+					dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
+					if (vcount_reg = '0'&X"F8") then
+						vbi_nmi_next <= '1';
+					end if;
+					
+				when X"12" =>
+					dli_nmi_next <= '0';
+					vbi_nmi_next <= '0';
+
+				when X"21" =>
+					hblank_next <= '0';					
+					
+				when X"24" => 
+					playfield_load <= '1'; -- start the shift register
+					
+				when X"31" => -- start refresh					
+					load_refresh_count <= '1';
+					refresh_count_next <= (others=>'0');
+				
+				when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
+					wsync_reset <= '1';				
+			
+				when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
+					allow_real_dma_next <= '0';				
+					load_refresh_count <= '1';
+					refresh_count_next <= "1001";
+					
+				when X"D8" => -- vscrol value checked at cycle 108
+					last_line_of_instruction_next <= last_line_of_instruction_live;
+				
+				when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
+					vcount_increment <= '1';
+										
+				when X"DD" =>
+					hblank_next <= '1';					
+					
+				when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
+					hcount_reset <= '1';
+					allow_real_dma_next <= not(vblank_reg);
+				when others =>
+					-- nothing
+			end case;	
+			
+			-- Playfield DMA
+			if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
+				dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= first_line_of_instruction_reg;
+			end if;					
+			
+			if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
+				character_next <= line_buffer_data_out;
+				increment_line_buffer_address <= '1';
+			end if;
+			
+			if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data			
+				dma_fetch_request <= dmactl_delayed_enabled;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= '1';		
+			end if;
+			
+			if (vblank_reg = '1') then
+				dma_fetch_request <= '0';
+			end if;
+			
+			if (refresh_fetch_next = '1') then
+				dma_address_next <= (others=>'0');
+			end if;
+		
+		end if;
+	end process;
+	
+	-- refresh handling
+	process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, memory_ready_antic, allow_real_dma_next)
+	begin
+		increment_refresh_count <= '0';
+		refresh_pending_next <= refresh_pending_reg;
+		refresh_fetch_next <= not(memory_ready_antic) and refresh_fetch_reg;
+		
+		if (colour_clock_1x = '1') then
+			-- do pending refresh once we have a spare cycle
+			if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
+				refresh_fetch_next <= '1';		
+				refresh_pending_next <= '0';
+			end if;
+		
+			-- do scheduled refresh - if block, enable pending one
+			if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
+				increment_refresh_count <= '1';
+				refresh_fetch_next <= not(dma_fetch_next);
+				refresh_pending_next <= dma_fetch_next;
+			end if;
+		end if;
+	end process;
+	
+	-- nmi handling
+	-- edge senstive, single cycle is enough (unless cpu disabled or  clashes)
+	-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist...	which is the goal.	
+
+	nmien_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
+		
+	nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
+	
+	process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
+	begin	
+		nmist_next(5) <= '0';
+		nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
+		nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
+	end process;
+	
+	-- dma clock	
+	process(dma_speed_reg) -- XXX TODO - remove this process!
+	begin
+		slow_dma_s <= '0';
+		medium_dma_s <= '0';
+		fast_dma_s <= '0';
+		
+		case dma_speed_reg is
+			when no_dma =>
+				-- nothing
+			when slow_dma =>
+				slow_dma_s <= '1';
+			when medium_dma =>
+				medium_dma_s <= '1';
+			when fast_dma =>
+				fast_dma_s <= '1';
+			when others =>
+				-- nothing
+		end case;
+	end process;
+	
+	antic_dma_clock1 : antic_dma_clock
+		port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
+
+	-- line buffer
+	reg_file1 : reg_file
+		generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
+		port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);		
+		--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
+		--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
+		
+	-- vertical scrolling
+	-- load row count from vscrol must be done at time of instruction load
+	-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
+	-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
+	vscrol_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>4)
+		port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));		
+	
+	process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count, force_final_row)
+	begin								
+		load_row_count <= '0';
+		row_count_next <= (others=>'0');
+		increment_row_count <= '0';
+		
+		last_line_of_instruction_live <= '0';		
+		
+		if (update_row_count = '1') then							
+			if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
+				row_count_next <= vscrol_delayed_reg;
+			end if;
+		
+			if (first_line_of_instruction_reg = '1') then
+				load_row_count <= '1';
+			else
+				increment_row_count <= '1';
+			end if;
+		end if;
+		
+		if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
+			if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
+				last_line_of_instruction_live <= '1';
+			end if;
+		else -- normal
+			if (row_count_reg = instruction_final_row_reg) then
+				last_line_of_instruction_live <= '1';
+			end if;
+		end if;
+		
+		if (vblank_reg = '1' or force_final_row = '1') then
+			last_line_of_instruction_live <= '1';
+		end if;
+						
+	end process;
+	
+	-- chbase 2 cycle delay
+	chbase_delay : wide_delay_line
+		generic map (COUNT=>cycle_length*2,WIDTH=>7)
+		port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
+		
+	-- decode instruction	
+	process(instruction_reg)
+	begin
+		dma_speed_next <= no_dma;
+		instruction_type_next <= mode_blank;
+		shift_rate_next <= slow_shift;
+		shift_twobit_next <= '0';
+		twopixel_next <= '0';
+		single_colour_character_next <= '0';		
+		multi_colour_character_next <= '0';		
+		twoline_character_next <= '0';
+		map_background_next <= '0';
+		instruction_final_row_next <= (others=>'0');
+		two_part_instruction_next <= instruction_reg(6);
+		instruction_blank_next <= '0';
+		vscrol_enabled_next <= instruction_reg(5);
+		hscrol_enabled_next <= instruction_reg(4);
+		dli_enabled_next <= instruction_reg(7);
+		descenders_next <= '0';		
+		force_final_row <= '0';
+		
+		case instruction_reg(3 downto 0) is 			
+			when X"0" =>
+				instruction_type_next <= mode_blank;
+				instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
+				two_part_instruction_next <= '0';
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				
+			when X"1" =>
+				instruction_type_next <= mode_jump;
+				instruction_final_row_next <= (others=>'0');
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				two_part_instruction_next <= '1';
+				
+				if (instruction_reg(6) = '1') then
+					instruction_type_next <= mode_jvb;
+					force_final_row <= '1';
+				end if;
+				
+			when X"2" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+			when X"3" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"9";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				descenders_next <= '1';
+				
+			when X"4" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				multi_colour_character_next <= '1';
+				
+			when X"5" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';	
+				twoline_character_next <= '1';		
+				multi_colour_character_next <= '1';
+				
+			when X"6" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				
+			when X"7" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				twoline_character_next <= '1';
+				
+			when X"8" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= slow_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"9" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"A" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"B" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"C" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"D" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"E" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"F" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+			when others =>
+				-- nothing
+				
+		end case;
+	end process;
+
+	-- dma fetching
+	process(dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,memory_ready_both,memory_data_in,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
+	begin	
+		instruction_next <= instruction_reg;
+		dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
+		
+		display_list_address_next_dma <= display_list_address_reg;
+		load_display_list_address_dma <= '0';
+		memory_scan_address_next <= memory_scan_address_reg;
+		load_memory_scan_address <= '0';
+		increment_display_list_address <= '0';
+		
+		load_display_shift_from_memory <= '0';
+		display_list_address_low_temp_next <= display_list_address_low_temp_reg;		
+		
+		line_buffer_data_in <= (others=>'0');
+		line_buffer_write <= '0';
+		
+		if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
+			instruction_next <= (others=>'0');
+		end if;
+	
+		if (dma_fetch_reg='1' and memory_ready_both='1') then
+			case dma_fetch_destination_reg is 
+				when dma_fetch_line_buffer =>
+					line_buffer_data_in <= memory_data_in;					
+					line_buffer_write <= '1';
+				when dma_fetch_shiftreg =>
+					load_display_shift_from_memory <= '1';
+				when dma_fetch_null =>
+					-- nothing (C/G/MTIA listens to bus)
+				when dma_fetch_instruction =>
+					instruction_next <= memory_data_in;
+					
+					increment_display_list_address <= '1';
+					
+				when dma_fetch_list_low =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						--display_list_address_next_dma(7 downto 0) <= memory_data_in; Changing this so soon messes up next dma cycle
+						display_list_address_low_temp_next <= memory_data_in;
+						increment_display_list_address <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(7 downto 0) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				when dma_fetch_list_high =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						 display_list_address_next_dma <= memory_data_in&display_list_address_low_temp_reg;
+						 load_display_list_address_dma <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(15 downto 8) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				
+				when others =>
+					-- nothing
+				
+			end case;
+
+			dma_fetch_next <= '0';
+		end if;
+	end process;
+	
+	-- shift reg clock
+	playfield_reset <= hblank_reg;
+	
+	process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
+	begin
+		shiftclock_next <= shiftclock_reg;
+		enable_shift <= '0';
+	
+		if (colour_clock_selected = '1') then
+		
+			shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
+			
+			if (playfield_load='1') then
+				shiftclock_next <= "1000";
+			end if;
+			
+			if (playfield_reset='1') then
+				shiftclock_next <= "0000";
+			end if;			
+			
+			--shiftclock_next(0) <= shiftclock_reg(1);
+			--shiftclock_next(1) <= shiftclock_reg(2);
+			--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
+			--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;						
+			case shift_rate_reg is
+				when slow_shift =>
+					enable_shift <= shiftclock_reg(0);
+				when medium_shift =>
+					enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
+				when fast_shift =>			
+					enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
+				when others =>
+					-- nothing
+			end case;			
+		end if;
+	end process;
+
+	-- shift reg
+	process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, memory_data_in, line_buffer_data_out)
+	begin
+		display_shift_next <= display_shift_reg;
+		
+		if (enable_shift = '1') then
+			if (shift_twobit_reg = '1') then
+				display_shift_next <= display_shift_reg(5 downto 0)&"00";
+			else
+				display_shift_next <= display_shift_reg(6 downto 0)&"0";
+			end if;			
+		end if;
+		
+		if (load_display_shift_from_memory = '1') then
+			display_shift_next(7 downto 0) <= memory_data_in;
+		end if;
+
+		if (load_display_shift_from_line_buffer = '1') then
+			display_shift_next(7 downto 0) <= line_buffer_data_out;
+		end if;
+		
+	end process;
+	
+	-- delay shift reg output for n cycles, so we can match AN with antic output
+	process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg)
+	begin
+		delay_display_shift_next <= delay_display_shift_reg;
+		
+		if (colour_clock_selected = '1') then
+			delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
+		end if;
+		
+	end process;
+	
+	-- ANO-2
+	-- XXX - clean up!	
+	-- first process - AN with no blanking	
+	process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
+	begin
+		an_current <= (others=>'0');
+		data_live <= (others=>'0');
+		if (shift_twobit_reg = '1') then				
+			an_current(0) <= delay_display_shift_reg(0);
+			an_current(1) <= delay_display_shift_reg(1);
+			an_current(2) <= '1';
+			
+			if (instruction_type_reg = mode_character) then							
+				data_live(0) <= delay_display_shift_reg(0);
+				data_live(1) <= delay_display_shift_reg(1);
+								
+				if (descenders_reg = '1') then					
+					if (delay_display_shift_reg(3 downto 2) = "11") then
+						if (unsigned(row_count_reg)<2) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					else
+						if (unsigned(row_count_reg)>=8) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					end if;
+				end if;	
+			
+				if (delay_display_shift_reg(4)='1') then -- inverse/hidden
+					if (chactl_reg(1)='1') then
+						an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
+						an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
+					else
+						an_current(0) <= data_live(0) and not(chactl_reg(0));
+						an_current(1) <= data_live(1) and not(chactl_reg(0));					
+					end if;
+				else
+					an_current(0) <= data_live(0);
+					an_current(1) <= data_live(1);				
+				end if;
+			end if;		
+
+			if (multi_colour_character_reg = '1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "11"&delay_display_shift_reg(4);										
+					when others =>
+						-- nop
+				end case;				
+			end if;
+			
+			if (map_background_reg='1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "110";										
+					when others =>
+						-- nop
+				end case;
+			end if;
+		else
+			if (single_colour_character_reg = '1') then
+				-- i.e. antic 6,7
+				if (delay_display_shift_reg(1) = '1') then
+					an_current(0) <= delay_display_shift_reg(3);
+					an_current(1) <= delay_display_shift_reg(4);
+					an_current(2) <= '1';					
+				else
+					an_current(0) <= '0';
+					an_current(1) <= '0';
+					an_current(2) <= '0';
+				end if;			
+			end if;
+			
+			if (map_background_reg='1') then
+				if (delay_display_shift_reg(1)='1') then
+					an_current <= "100";
+				else
+					an_current <= "000";										
+				end if;
+			end if;				
+		end if;		
+	end process;
+	
+	process(colour_clock_selected, an_current, an_prev_reg)
+	begin
+		an_prev_next <= an_prev_reg;
+		
+		if (colour_clock_selected = '1') then
+			an_prev_next <= an_current;
+		end if;
+	end process;
+	
+	process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
+	begin
+		an_next <= an_reg;
+	
+		if (colour_clock_selected = '1') then	
+			an_next <= an_current;
+			
+			if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
+				an_next <= an_prev_reg;
+			end if;
+			
+			if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
+				an_next <= "000";
+			end if;
+			
+			if (vblank_reg = '1' or hblank_reg = '1') then				
+				an_next(0) <= vsync_reg or twopixel_reg;
+				an_next(1) <= not(vsync_reg);
+				an_next(2) <= not(hblank_reg) and twopixel_reg;
+				
+				--an_next <= 
+						--(twopixel_reg and not(vsync_reg or hblank_reg))
+						--&((hblank_reg or vblank_reg) and not(vsync_reg))
+						--&(vsync_reg or twopixel_reg);
+			end if;			
+			
+			-- TODO this is too simplistic:
+			-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
+			-- + odd behaviour seen during high res bug
+
+		end if;
+		
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+
+	-- wsync write takes 1 cycle to assert rdy
+	-- TODO - revisit antic delays in terms of cpu cycles
+	wsync_delay : delay_line
+		generic map (COUNT=>cycle_length+cycle_length/2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
+
+	-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
+	--dmactl_delay : wide_delay_line
+	--	generic map (COUNT=>cycle_length,WIDTH=>6)
+	--	port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
+	dmactl_delayed_reg <= dmactl_raw_next;
+	--dmactl_delayed_reg <= dmactl_raw_reg;
+		
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
+	begin		
+		nmien_raw_next <= nmien_raw_reg;
+		dmactl_raw_next <= dmactl_raw_reg;
+		chactl_next <= chactl_reg;
+		hscrol_next <= hscrol_reg;
+		vscrol_raw_next <= vscrol_raw_reg;
+		chbase_raw_next <= chbase_raw_reg;
+		pmbase_next <= pmbase_reg;
+		wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
+		nmist_reset <= '0';
+		wsync_write <= '0';
+		
+		load_display_list_address_cpu <= '0';
+		display_list_address_next_cpu <= display_list_address_reg;
+	
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				dmactl_raw_next <= cpu_data_in(6 downto 0);
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				chactl_next <= cpu_data_in(2 downto 0);
+			end if;	
+			
+			if(addr_decoded(2) = '1') then
+				display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;		
+			
+			if(addr_decoded(3) = '1') then
+				display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;
+
+			if(addr_decoded(4) = '1') then
+				hscrol_next <= cpu_data_in(3 downto 0);
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				vscrol_raw_next <= cpu_data_in(3 downto 0);
+			end if;
+			
+			if(addr_decoded(7) = '1') then
+				pmbase_next <= cpu_data_in(7 downto 2);
+			end if;		
+			
+			if(addr_decoded(9) = '1') then
+				chbase_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+
+			if(addr_decoded(10) = '1') then
+				wsync_write <= '1';
+			end if;		
+	
+			if(addr_decoded(14) = '1') then
+				nmien_raw_next <= cpu_data_in(7 downto 6);
+			end if;
+		
+			if(addr_decoded(15) = '1') then
+				nmist_reset <= '1';
+			end if;		
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
+	begin
+		data_out <= X"FF";
+
+		if (addr_decoded(8) = '1') then -- HCOUNT :-)
+			data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
+		end if;
+		
+		if(addr_decoded(11) = '1') then --VCOUNT
+			data_out <= vcount_reg(8 downto 1);
+		end if;
+		
+		if (addr_decoded(12) = '1') then -- PENH
+			data_out <= penh_reg;
+		end if;
+		
+		if (addr_decoded(13) = '1') then -- PENV
+			data_out <= penv_reg;
+		end if;
+
+		if(addr_decoded(15) = '1') then --NMIST
+			data_out <= nmist_reg&"00000";
+		end if;
+		
+	end process;
+	
+	-- nmi delay
+	nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
+	
+	-- light pen
+	process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
+	begin
+		penv_next <= penv_reg;
+		penh_next <= penh_reg;
+		
+		if (lightpen = '0') then
+			penv_next <= vcount_reg(8 downto 1);
+			penh_next <= hcount_reg;
+		end if;
+	end process;
+	
+	-- Use CPU data if virtual dma
+	MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
+	
+	-- output
+	nmi_n_out <= nmi_shiftreg_reg(0);
+	
+	dma_clock_out<=dma_clock_character_name;
+	
+	AN <= an_reg;
+	
+	antic_ready <= not(wsync_reg);
+	
+	dma_fetch_out <= refresh_fetch_reg or (allow_real_dma_reg and dma_fetch_reg);
+	dma_address_out <= dma_address_reg;
+	
+	refresh_out <= refresh_fetch_reg;
+	
+	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+	COLOUR_CLOCK_OUT <= colour_clock_selected;
+	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
+
+	vcount_out <= vcount_reg;
+	hcount_out <= hcount_reg;
+	
+END vhdl;
+
Index: common/a8core/antic_counter.vhdl
===================================================================
--- common/a8core/antic_counter.vhdl	(nonexistent)
+++ common/a8core/antic_counter.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY antic_counter IS
+generic
+(
+	STORE_WIDTH : natural := 1;
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+);
+END antic_counter;
+
+ARCHITECTURE vhdl OF antic_counter IS
+	signal value_next : std_logic_vector(STORE_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(STORE_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= value_reg(STORE_WIDTH-1 downto COUNT_WIDTH)&std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: common/a8core/antic_dma_clock.vhdl
===================================================================
--- common/a8core/antic_dma_clock.vhdl	(nonexistent)
+++ common/a8core/antic_dma_clock.vhdl	(revision 1)
@@ -0,0 +1,74 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic_dma_clock IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	enable_dma : IN STD_LOGIC;
+	
+	playfield_start : in std_logic;
+	playfield_end : in std_logic;
+	vblank : in std_logic;
+	
+	slow_dma : in std_logic;
+	medium_dma : in std_logic;
+	fast_dma : in std_logic;
+	
+	dma_clock_out_0 : out std_logic;
+	dma_clock_out_1 : out std_logic;
+	dma_clock_out_2 : out std_logic;
+	dma_clock_out_3 : out std_logic
+);
+END antic_dma_clock;
+
+ARCHITECTURE vhdl OF antic_dma_clock IS
+	signal dma_shiftreg_next : std_logic_vector(7 downto 0);
+	signal dma_shiftreg_reg : std_logic_vector(7 downto 0);
+	
+	signal tick : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			dma_shiftreg_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			dma_shiftreg_reg <= dma_shiftreg_next;
+		end if;
+	end process;
+
+	-- next state
+	tick <=(dma_shiftreg_reg(0) and slow_dma) or (dma_shiftreg_reg(4) and medium_dma) or (dma_shiftreg_reg(6) and fast_dma);
+	process(enable_dma, dma_shiftreg_reg, playfield_start, playfield_end, vblank, slow_dma, medium_dma, fast_dma, tick)
+	begin
+		dma_shiftreg_next <= dma_shiftreg_reg;
+
+		if (enable_dma = '1') then			
+			dma_shiftreg_next <= 
+				not((playfield_start nor tick)
+				or playfield_end or vblank)				
+				&dma_shiftreg_reg(7 downto 1);
+		end if;
+		
+		if (playfield_start = '1') then
+			dma_shiftreg_next(7) <= not((playfield_start nor tick) or playfield_end or vblank);
+		end if;
+	end process;
+	
+	-- output
+	dma_clock_out_0 <= dma_shiftreg_reg(6) and enable_dma;
+	dma_clock_out_1 <= dma_shiftreg_reg(5) and enable_dma;
+	dma_clock_out_2 <= dma_shiftreg_reg(4) and enable_dma;
+	dma_clock_out_3 <= dma_shiftreg_reg(3) and enable_dma;
+	
+END vhdl;
Index: common/a8core/atari800core.vhd
===================================================================
--- common/a8core/atari800core.vhd	(nonexistent)
+++ common/a8core/atari800core.vhd	(revision 1)
@@ -0,0 +1,1283 @@
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use IEEE.STD_LOGIC_MISC.all;
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLK :  IN  STD_LOGIC;
+		PLL_LOCKED: IN STD_LOGIC;
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+		matrix_out : in std_logic_vector(15 downto 0);
+		matrix_in : out std_logic_vector(7 downto 0);
+		static_keys : in std_logic_vector(6 downto 0);
+		pause_key : in std_logic;
+		
+		AUDIO_L : OUT std_logic_vector(15 downto 0);
+		AUDIO_R : OUT std_logic_vector(15 downto 0);
+
+		SDRAM_REQUEST : OUT std_logic;
+		SDRAM_REQUEST_COMPLETE : IN std_logic;
+		SDRAM_READ_ENABLE : out STD_LOGIC;
+		SDRAM_WRITE_ENABLE : out std_logic;
+		SDRAM_DI : out std_logic_vector(31 downto 0);
+		SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
+		SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
+		SDRAM_WIDTH_8bit_ACCESS : out std_logic;
+		SDRAM_WIDTH_16bit_ACCESS : out std_logic;
+		SDRAM_WIDTH_32bit_ACCESS : out std_logic;
+
+		SIO_RXD : in std_logic;
+		SIO_TXD : out std_logic;
+		SIO_COMMAND_TX : out std_logic;
+
+   		ram_select : in std_logic_vector(2 downto 0);
+    		rom_select : in std_logic_vector(5 downto 0);
+
+		halt : in std_logic
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+component synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END component;
+
+COMPONENT complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);			
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END component;
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+component internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+	
+END component;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 hcount_out : out std_logic_vector(7 downto 0);
+		 vcount_out : out std_logic_vector(8 downto 0);
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : in std_logic_vector(5 downto 0);
+		 cart_select : in std_logic_vector(6 downto 0);
+		 cart_activate : in std_logic;
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 D6_WR_ENABLE : out std_logic
+	);
+END COMPONENT;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+--COMPONENT zpu_ram
+--	PORT(wren : IN STD_LOGIC;
+--		 clock : IN STD_LOGIC;
+--		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+--		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+--		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+--	);
+--END COMPONENT;
+
+component generic_ram_infer IS
+        generic
+        (
+                ADDRESS_WIDTH : natural := 9;
+                SPACE : natural := 512;
+                DATA_WIDTH : natural := 8
+        );
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+      address:  IN   std_logic_vector(address_width-1 downto 0);
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+   );
+END component;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 sector : out std_logic_vector(31 downto 0);
+		 sector_request : out std_logic;
+		 sector_ready : in std_logic
+	);
+END COMPONENT;
+
+COMPONENT gtia_palette IS
+PORT 
+( 
+	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+);
+END component;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 BLANK : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+component covox IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	covox_channel0 : out std_logic_vector(7 downto 0);
+	covox_channel1 : out std_logic_vector(7 downto 0);
+	covox_channel2 : out std_logic_vector(7 downto 0);
+	covox_channel3 : out std_logic_vector(7 downto 0)
+);
+END component;
+
+
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+signal CART_CCTL_N : std_logic;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	HALT_OR_PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT_dummy :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT_dummy :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+--SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+
+SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal UART_TXD_dummy : std_logic;
+
+SIGNAL		SD_DAT0 :  STD_LOGIC;
+SIGNAL		SD_CLK :  STD_LOGIC;
+SIGNAL		SD_CMD :  STD_LOGIC;
+SIGNAL		SD_DAT3 :  STD_LOGIC;
+
+signal mist_buttons : std_logic_vector(1 downto 0);
+signal mist_switches : std_logic_vector(1 downto 0);
+
+SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
+SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
+SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
+
+signal dummy_sector_request : std_logic;
+signal dummy_sector : std_logic_vector(31 downto 0);
+
+signal COLOUR : std_logic_vector(7 downto 0);
+
+signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
+signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
+signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
+signal POKEY1_CHANNEL3 : std_logic_vector(3 downto 0);
+
+signal POKEY2_CHANNEL0 : std_logic_vector(3 downto 0);
+signal POKEY2_CHANNEL1 : std_logic_vector(3 downto 0);
+signal POKEY2_CHANNEL2 : std_logic_vector(3 downto 0);
+signal POKEY2_CHANNEL3 : std_logic_vector(3 downto 0);
+
+signal hcount_temp : std_logic_vector(7 downto 0);
+signal vcount_temp : std_logic_vector(8 downto 0);
+signal VGA_G_dummy : std_logic_vector(7 downto 0);
+signal VGA_B_dummy : std_logic_vector(7 downto 0);
+
+signal matrix_out_match : std_logic_vector(7 downto 0);
+
+signal keyboard_scan_inv : std_logic_vector(5 downto 0);
+
+signal covox_write_enable : std_logic;
+signal covox_channel0 : std_logic_vector(7 downto 0);
+signal covox_channel1 : std_logic_vector(7 downto 0);
+signal covox_channel2 : std_logic_vector(7 downto 0);
+signal covox_channel3 : std_logic_vector(7 downto 0);
+
+signal gtia_blank : std_logic;
+
+BEGIN 
+
+cpu6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+LIGHTPEN <= '1';
+antic1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 hcount_out => hcount_temp,
+		 vcount_out => vcount_temp,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+pokey_mixer_l : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => POKEY1_CHANNEL0,
+		 CHANNEL_1 => POKEY1_CHANNEL1,
+		 CHANNEL_2 => POKEY1_CHANNEL2,
+		 CHANNEL_3 => POKEY1_CHANNEL3,
+		 CHANNEL_ENABLE => "1111",
+		 COVOX_CHANNEL_0 => covox_channel0,
+		 COVOX_CHANNEL_1 => covox_channel1,
+		 VOLUME_OUT => AUDIO_L);
+		 
+zpu_glue1 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 ZPU_SECTOR_DI => zpu_sector_data,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+pokey_mixer_r : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => POKEY2_CHANNEL0,
+		 CHANNEL_1 => POKEY2_CHANNEL1,
+		 CHANNEL_2 => POKEY2_CHANNEL2,
+		 CHANNEL_3 => POKEY2_CHANNEL3,
+		 COVOX_CHANNEL_0 => covox_channel2,
+		 COVOX_CHANNEL_1 => covox_channel3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_R);
+
+
+pokey2 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => POKEY2_CHANNEL0,
+		 CHANNEL_1_OUT => POKEY2_CHANNEL1,
+		 CHANNEL_2_OUT => POKEY2_CHANNEL2,
+		 CHANNEL_3_OUT => POKEY2_CHANNEL3,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+SIO_COMMAND_TX <= SIO_COMMAND_OUT;
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+GPIO_CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
+GPIO_CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
+GPIO_PORTA_IN <= ((JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)&JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
+
+pia1 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+HALT_OR_PAUSE_6502 <= HALT or PAUSE_6502;
+enables : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => HALT_OR_PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+-- no cart!
+CART_RD4 <= '0';
+CART_RD5 <= '0';
+CART_REQUEST_COMPLETE <= '0';
+CART_ROM_DO <= (others=>'0');
+
+mmu1 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT(2 downto 0),
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT, 
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA,
+		 d6_wr_enable => covox_write_enable,
+		 cart_select => "0000000",
+		 cart_activate => '0');
+
+zpu_rom1 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+--
+--b2v_inst23 : zpu_ram
+--PORT MAP(wren => ZPU_STACK_WRITE(2),
+--		 clock => CLK,
+--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+--		 data => ZPU_DO(23 DOWNTO 16),
+--		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+zpu_ram1 : generic_ram_infer
+generic map
+(
+	ADDRESS_WIDTH => 10,
+	SPACE => 1024,
+	DATA_WIDTH =>8
+)
+PORT MAP(clock => clk,
+		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+		 data => ZPU_DO(23 downto 16),
+		 we => ZPU_STACK_WRITE(2),
+		 q => ZPU_RAM_DATA(23 downto 16)
+		 );	
+
+SYNC_KEYS <= (others=> '0');
+SYNC_SWITCHES <= (others=> '1');
+zpu_config1 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DAT0,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_DAT3,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG_dummy,
+		 LEDR => LEDR_dummy,
+		 RAM_SELECT => RAM_SELECT_dummy,
+		 ROM_SELECT => ROM_SELECT_dummy(1 downto 0),
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX,
+		 sector_request => dummy_sector_request,
+		 sector => dummy_sector,
+		 sector_ready => '0'
+		 );
+ROM_SELECT_dummy(5 downto 2) <= "0000";
+
+--
+--b2v_inst25 : zpu_ram
+--PORT MAP(wren => ZPU_STACK_WRITE(3),
+--		 clock => CLK,
+--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+--		 data => ZPU_DO(31 DOWNTO 24),
+--		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+zpu_ram2 : generic_ram_infer
+generic map
+(
+	ADDRESS_WIDTH => 10,
+	SPACE => 1024,
+	DATA_WIDTH =>8
+)
+PORT MAP(clock => clk,
+		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+		 data => ZPU_DO(31 downto 24),
+		 we => ZPU_STACK_WRITE(3),
+		 q => ZPU_RAM_DATA(31 downto 24)
+		 );	
+
+
+--b2v_inst26 : zpu_ram
+--PORT MAP(wren => ZPU_STACK_WRITE(0),
+--		 clock => CLK,
+--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+--		 data => ZPU_DO(7 DOWNTO 0),
+--		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+zpu_ram3 : generic_ram_infer
+generic map
+(
+	ADDRESS_WIDTH => 10,
+	SPACE => 1024,
+	DATA_WIDTH =>8
+)
+PORT MAP(clock => clk,
+		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+		 data => ZPU_DO(7 downto 0),
+		 we => ZPU_STACK_WRITE(0),
+		 q => ZPU_RAM_DATA(7 downto 0)
+		 );	
+
+
+--b2v_inst27 : zpu_ram
+--PORT MAP(wren => ZPU_STACK_WRITE(1),
+--		 clock => CLK,
+--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+--		 data => ZPU_DO(15 DOWNTO 8),
+--		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+zpu_ram4 : generic_ram_infer
+generic map
+(
+	ADDRESS_WIDTH => 10,
+	SPACE => 1024,
+	DATA_WIDTH =>8
+)
+PORT MAP(clock => clk,
+		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+		 data => ZPU_DO(15 downto 8),
+		 we => ZPU_STACK_WRITE(1),
+		 q => ZPU_RAM_DATA(15 downto 8)
+		 );	
+
+pokey1 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => SIO_RXD,
+		 SIO_IN2 => '1',
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => SIO_TXD,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => POKEY1_CHANNEL0,
+		 CHANNEL_1_OUT => POKEY1_CHANNEL1,
+		 CHANNEL_2_OUT => POKEY1_CHANNEL2,
+		 CHANNEL_3_OUT => POKEY1_CHANNEL3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+	keyboard_scan_inv <= not(keyboard_scan);
+
+a4051: complete_address_decoder
+	generic map (width => 3)
+	PORT map ( addr_in => keyboard_scan_inv(5 downto 3), addr_decoded => matrix_in ); 
+
+b4051: complete_address_decoder
+	generic map (width => 3)
+	PORT map ( addr_in => keyboard_scan_inv(2 downto 0), addr_decoded => matrix_out_match ); 
+
+	process(matrix_out, matrix_out_match)
+	begin
+		keyboard_response(0) <= '1';
+
+		if (or_reduce(matrix_out(7 downto 0) and matrix_out_match(7 downto 0)) = '1') then
+			keyboard_response(0) <= '0';
+		end if;
+	end process;
+
+	process(static_keys, pause_key)
+	begin
+		keyboard_response(1) <= '1';
+
+		if (keyboard_scan(5 downto 4)="00" and pause_key = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and static_keys(0) = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and static_keys(1) = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;
+
+	CONSOL_START <= static_keys(6);
+	CONSOL_SELECT <= static_keys(5);
+	CONSOL_OPTION <= static_keys(4);
+	system_reset_request <= static_keys(3);
+
+	virtual_keys <= "000"&static_keys(2); -- todo need more static keys!! though on second thoughts using replay menu for options/loading...
+	virtual_triggers <= "00"&joy1_n(4)&joy2_n(4); -- todo joystick...
+		 	 
+gtia1 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => joy2_n(4), -- TODO - joystick trigger too
+		 TRIG1 => joy1_n(4),
+		 --TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+		 --TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+		 TRIG2 => VIRTUAL_TRIGGERS(2),
+		 TRIG3 => VIRTUAL_TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 BLANK => GTIA_BLANK,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => COLOUR,
+		 DATA_OUT => GTIA_DO);
+
+	-- colour palette
+--	Color             Value         Color             Value
+--Black           0,      0	Medium blue     8,    128
+--Rust            1,     16       Dark blue       9,    144
+--Red-orange      2,     32       Blue-grey      10,    160
+--Dark orange     3,     48       Olive green    11,    176
+--Red             4,     64       Medium green   12,    192
+--Dk lavender     5,     80       Dark green     13,    208
+--Cobalt blue     6,     96       Orange-green   14,    224
+--Ultramarine     7,    112       Orange         15,    240
+
+-- from altirra	
+	palette1 : entity work.gtia_palette(altirra)
+		port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R, G_next=>VGA_G, B_next=>VGA_B);
+	--VGA_B <= hcount_temp;
+	--VGA_G <= vcount_temp(7 downto 0);
+		
+-- from lao
+--	palette2 : entity work.gtia_palette(laoo)
+--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
+
+
+irq_glue1 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+internalromram1 : internalromram
+  PORT map(
+    clock => clk,
+    reset_n => reset_n,
+
+	ROM_ADDR =>rom_addr,
+	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
+	ROM_REQUEST => rom_REQUEST,
+	ROM_DATA => rom_DO,
+	
+	RAM_ADDR => ram_addr,
+	RAM_WR_ENABLE => ram_WRITE_ENABLE,
+	RAM_DATA_IN => wriTE_DATA(7 downto 0),
+	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
+	RAM_REQUEST => ram_REQUEST,
+	RAM_DATA => ram_do(7 downto 0)
+	);
+
+SDRAM_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
+SDRAM_WIDTH_16bit_ACCESS <= WIDTH_16bit_access;
+SDRAM_WIDTH_32bit_ACCESS <= WIDTH_32bit_access;
+SDRAM_DI <= WRITE_DATA;
+
+covox1 : covox
+	PORT map
+	( 
+		clk => clk,
+		addr => pbi_addr(1 downto 0),
+		data_in => WRITE_DATA(7 DOWNTO 0),
+		wr_en => covox_write_enable,
+		covox_channel0 => covox_channel0,
+		covox_channel1 => covox_channel1,
+		covox_channel2 => covox_channel2,
+		covox_channel3 => covox_channel3
+	);
+
+END bdf_type;
Index: common/a8core/basic.vhdl
===================================================================
--- common/a8core/basic.vhdl	(nonexistent)
+++ common/a8core/basic.vhdl	(revision 1)
@@ -0,0 +1,8226 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity basic is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(12 downto 0);
+        q:out std_logic_vector(7 downto 0)
+);
+end basic;
+
+architecture syn of basic is
+        type rom_type is array(0 to 8191) of std_logic_vector(7 downto 0);
+        signal ROM:rom_type:=
+(
+	X"a5",
+X"ca",
+X"d0",
+X"04",
+X"a5",
+X"08",
+X"d0",
+X"45",
+X"a2",
+X"ff",
+X"9a",
+X"d8",
+X"ae",
+X"e7",
+X"02",
+X"ac",
+X"e8",
+X"02",
+X"86",
+X"80",
+X"84",
+X"81",
+X"a9",
+X"00",
+X"85",
+X"92",
+X"85",
+X"ca",
+X"c8",
+X"8a",
+X"a2",
+X"82",
+X"95",
+X"00",
+X"e8",
+X"94",
+X"00",
+X"e8",
+X"e0",
+X"92",
+X"90",
+X"f6",
+X"a2",
+X"86",
+X"a0",
+X"01",
+X"20",
+X"7a",
+X"a8",
+X"a2",
+X"8c",
+X"a0",
+X"03",
+X"20",
+X"7a",
+X"a8",
+X"a9",
+X"00",
+X"a8",
+X"91",
+X"84",
+X"91",
+X"8a",
+X"c8",
+X"a9",
+X"80",
+X"91",
+X"8a",
+X"c8",
+X"a9",
+X"03",
+X"91",
+X"8a",
+X"a9",
+X"0a",
+X"85",
+X"c9",
+X"20",
+X"f1",
+X"b8",
+X"20",
+X"45",
+X"bd",
+X"20",
+X"5b",
+X"bd",
+X"a5",
+X"92",
+X"f0",
+X"03",
+X"20",
+X"9d",
+X"bd",
+X"20",
+X"62",
+X"bd",
+X"a5",
+X"ca",
+X"d0",
+X"9c",
+X"a2",
+X"ff",
+X"9a",
+X"20",
+X"51",
+X"da",
+X"a9",
+X"5d",
+X"85",
+X"c2",
+X"20",
+X"ed",
+X"bd",
+X"20",
+X"f2",
+X"a9",
+X"f0",
+X"ea",
+X"a9",
+X"00",
+X"85",
+X"f2",
+X"85",
+X"9f",
+X"85",
+X"94",
+X"85",
+X"a6",
+X"85",
+X"b3",
+X"85",
+X"b0",
+X"85",
+X"b1",
+X"a5",
+X"84",
+X"85",
+X"ad",
+X"a5",
+X"85",
+X"85",
+X"ae",
+X"20",
+X"a1",
+X"db",
+X"20",
+X"9a",
+X"a1",
+X"20",
+X"c4",
+X"a2",
+X"a5",
+X"d5",
+X"10",
+X"02",
+X"85",
+X"a6",
+X"20",
+X"a1",
+X"db",
+X"a4",
+X"f2",
+X"84",
+X"a8",
+X"b1",
+X"f3",
+X"c9",
+X"9b",
+X"d0",
+X"07",
+X"24",
+X"a6",
+X"30",
+X"b2",
+X"4c",
+X"86",
+X"a1",
+X"a5",
+X"94",
+X"85",
+X"a7",
+X"20",
+X"c4",
+X"a2",
+X"20",
+X"a1",
+X"db",
+X"a9",
+X"a4",
+X"a0",
+X"9f",
+X"a2",
+X"02",
+X"20",
+X"54",
+X"a4",
+X"86",
+X"f2",
+X"a5",
+X"af",
+X"20",
+X"c4",
+X"a2",
+X"20",
+X"a1",
+X"db",
+X"20",
+X"be",
+X"a1",
+X"90",
+X"35",
+X"a4",
+X"9f",
+X"b1",
+X"f3",
+X"c9",
+X"9b",
+X"d0",
+X"06",
+X"c8",
+X"91",
+X"f3",
+X"88",
+X"a9",
+X"20",
+X"09",
+X"80",
+X"91",
+X"f3",
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+X"08",
+X"67",
+X"40",
+X"01",
+X"57",
+X"07",
+X"96",
+X"32",
+X"40",
+X"90",
+X"00",
+X"00",
+X"00",
+X"00",
+X"3f",
+X"01",
+X"74",
+X"53",
+X"29",
+X"25",
+X"40",
+X"01",
+X"00",
+X"00",
+X"00",
+X"00",
+X"a9",
+X"00",
+X"85",
+X"f0",
+X"85",
+X"f1",
+X"a5",
+X"d4",
+X"29",
+X"7f",
+X"c9",
+X"40",
+X"30",
+X"15",
+X"a5",
+X"d4",
+X"29",
+X"80",
+X"85",
+X"f0",
+X"e6",
+X"f1",
+X"a9",
+X"7f",
+X"25",
+X"d4",
+X"85",
+X"d4",
+X"a2",
+X"ea",
+X"a0",
+X"df",
+X"20",
+X"95",
+X"de",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"a7",
+X"dd",
+X"20",
+X"b6",
+X"dd",
+X"20",
+X"db",
+X"da",
+X"b0",
+X"39",
+X"a9",
+X"0b",
+X"a2",
+X"ae",
+X"a0",
+X"df",
+X"20",
+X"40",
+X"dd",
+X"b0",
+X"2e",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"db",
+X"da",
+X"b0",
+X"22",
+X"a5",
+X"f1",
+X"f0",
+X"10",
+X"a2",
+X"f0",
+X"a0",
+X"df",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"66",
+X"da",
+X"a5",
+X"f0",
+X"05",
+X"d4",
+X"85",
+X"d4",
+X"a5",
+X"fb",
+X"f0",
+X"0a",
+X"a2",
+X"c9",
+X"a0",
+X"be",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"28",
+X"db",
+X"60",
+X"38",
+X"60",
+X"a9",
+X"00",
+X"85",
+X"f1",
+X"a5",
+X"d4",
+X"30",
+X"f6",
+X"c9",
+X"3f",
+X"f0",
+X"17",
+X"18",
+X"69",
+X"01",
+X"85",
+X"f1",
+X"85",
+X"e0",
+X"a9",
+X"01",
+X"85",
+X"e1",
+X"a2",
+X"04",
+X"a9",
+X"00",
+X"95",
+X"e2",
+X"ca",
+X"10",
+X"fb",
+X"20",
+X"28",
+X"db",
+X"a9",
+X"06",
+X"85",
+X"ef",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"a7",
+X"dd",
+X"20",
+X"b6",
+X"dd",
+X"a2",
+X"f1",
+X"a0",
+X"ba",
+X"20",
+X"89",
+X"dd",
+X"20",
+X"60",
+X"da",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"db",
+X"da",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"a7",
+X"dd",
+X"20",
+X"b6",
+X"dd",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"89",
+X"dd",
+X"20",
+X"28",
+X"db",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"60",
+X"da",
+X"a2",
+X"6c",
+X"a0",
+X"df",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"db",
+X"da",
+X"a5",
+X"d4",
+X"f0",
+X"0e",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"66",
+X"da",
+X"c6",
+X"ef",
+X"10",
+X"c6",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"89",
+X"dd",
+X"a5",
+X"f1",
+X"f0",
+X"23",
+X"38",
+X"e9",
+X"40",
+X"18",
+X"6a",
+X"18",
+X"69",
+X"40",
+X"29",
+X"7f",
+X"85",
+X"e0",
+X"a5",
+X"f1",
+X"6a",
+X"a9",
+X"01",
+X"90",
+X"02",
+X"a9",
+X"10",
+X"85",
+X"e1",
+X"a2",
+X"04",
+X"a9",
+X"00",
+X"95",
+X"e2",
+X"ca",
+X"10",
+X"fb",
+X"20",
+X"db",
+X"da",
+X"60",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"a0",
+X"00",
+X"05",
+X"f0",
+X"bf"
+
+);
+        signal rdata:std_logic_vector(7 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: common/a8core/complete_address_decoder.vhdl
===================================================================
--- common/a8core/complete_address_decoder.vhdl	(nonexistent)
+++ common/a8core/complete_address_decoder.vhdl	(revision 1)
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);	
+	
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END complete_address_decoder;
+
+--ARCHITECTURE vhdl OF complete_address_decoder IS
+--BEGIN
+--	comp_gen:
+--	for i in 0 to ((2**width)-1) generate
+--		addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
+--	end generate;
+--end vhdl;
+
+architecture tree of complete_address_decoder is
+	constant STAGE : natural:=width;
+	type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
+	signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
+	signal a: std_logic_vector(width-1 downto 0) ;
+begin
+	a<=addr_in;
+	process(a,p)
+	begin
+		p(stage,0) <= '1';
+		
+		for s in stage downto 1 loop
+			for r in 0 to (2**(stage-s)-1) loop
+				p(s-1,2*r) <= (not a(s-1)) and p(s,r);
+				p(s-1,2*r+1) <= a(s-1) and p(s,r);
+			end loop;
+		end loop;
+		
+		for i in  0 to (2**stage-1) loop
+			addr_decoded(i) <= p(0,i);
+		end loop;
+	end process;
+end tree;
\ No newline at end of file
Index: common/a8core/countdown_timer.vhdl
===================================================================
--- common/a8core/countdown_timer.vhdl	(nonexistent)
+++ common/a8core/countdown_timer.vhdl	(revision 1)
@@ -0,0 +1,102 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_countdown_timer IS
+generic(UNDERFLOW_DELAY : natural := 3);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	ENABLE_UNDERFLOW : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	WR_EN : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+	DATA_OUT : OUT STD_LOGIC
+);
+END pokey_countdown_timer;
+
+ARCHITECTURE vhdl OF pokey_countdown_timer IS
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal count_reg : std_logic_vector(7 downto 0);
+	signal count_next: std_logic_vector(7 downto 0);
+	
+	signal underflow : std_logic;
+	
+	signal count_command : std_logic_vector(1 downto 0);	
+	signal underflow_command: std_logic_vector(1 downto 0);	
+BEGIN
+	-- Instantiate delay (provides output)
+	underflow0_delay : delay_line
+		generic map (COUNT=>UNDERFLOW_DELAY)
+		port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+		end if;
+	end process;
+
+	-- count down on enable
+	process(count_reg,enable,wr_en,count_command,data_in)
+	begin	
+		count_command <= enable&wr_en;
+		case count_command is
+			when "10" =>
+				count_next <= std_logic_vector(unsigned(count_reg) -1);
+			when "01"|"11" =>
+				count_next <= data_in;
+			when others =>
+				count_next <= count_reg;
+		end case;
+	end process;
+		
+	-- underflow
+	process(count_reg,enable,underflow_command)
+	begin
+		underflow_command <= enable & To_Std_Logic(count_reg = X"00");
+		case underflow_command is
+			when "11" =>
+				underflow <= '1';
+			when others =>
+				underflow <= '0';
+		end case;
+	end process;
+		
+END vhdl;
Index: common/a8core/covox.vhd
===================================================================
--- common/a8core/covox.vhd	(nonexistent)
+++ common/a8core/covox.vhd	(revision 1)
@@ -0,0 +1,92 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY covox IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	covox_channel0 : out std_logic_vector(7 downto 0);
+	covox_channel1 : out std_logic_vector(7 downto 0);
+	covox_channel2 : out std_logic_vector(7 downto 0);
+	covox_channel3 : out std_logic_vector(7 downto 0)
+);
+END covox;
+
+ARCHITECTURE vhdl OF covox IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	signal channel0_next : std_logic_vector(7 downto 0);
+	signal channel1_next : std_logic_vector(7 downto 0);
+	signal channel2_next : std_logic_vector(7 downto 0);
+	signal channel3_next : std_logic_vector(7 downto 0);
+	signal channel0_reg : std_logic_vector(7 downto 0);
+	signal channel1_reg : std_logic_vector(7 downto 0);
+	signal channel2_reg : std_logic_vector(7 downto 0);
+	signal channel3_reg : std_logic_vector(7 downto 0);
+	
+	signal addr_decoded : std_logic_vector(3 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => 2)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(channel0_reg,channel1_reg,channel2_reg,channel3_reg,addr_decoded,data_in,WR_EN)
+	begin
+		channel0_next <= channel0_reg;
+		channel1_next <= channel1_reg;
+		channel2_next <= channel2_reg;
+		channel3_next <= channel3_reg;
+		
+		if (WR_EN = '1') then		
+			if (addr_decoded(0) = '1') then				
+				channel0_next <= data_in;
+			end if;
+			if (addr_decoded(1) = '1') then				
+				channel1_next <= data_in;
+			end if;
+			if (addr_decoded(2) = '1') then				
+				channel2_next <= data_in;
+			end if;
+			if (addr_decoded(3) = '1') then				
+				channel3_next <= data_in;
+			end if;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			channel0_reg <= channel0_next;
+			channel1_reg <= channel1_next;
+			channel2_reg <= channel2_next;
+			channel3_reg <= channel3_next;
+		end if;
+	end process;
+	
+	-- output
+	covox_channel0 <= channel0_reg;
+	covox_channel1 <= channel1_reg;
+	covox_channel2 <= channel2_reg;
+	covox_channel3 <= channel3_reg;
+END vhdl;
\ No newline at end of file
Index: common/a8core/cpu.vhd
===================================================================
--- common/a8core/cpu.vhd	(nonexistent)
+++ common/a8core/cpu.vhd	(revision 1)
@@ -0,0 +1,142 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+ENTITY cpu IS
+PORT 
+(
+	CLK,RESET,ENABLE : IN STD_logic;
+	DI : IN std_logic_vector(7 downto 0);
+	IRQ_n   : in  std_logic;
+	NMI_n   : in  std_logic;
+	MEMORY_READY : in std_logic;
+	THROTTLE : in std_logic;
+	RDY : in std_logic;
+	DO : OUT std_logic_vector(7 downto 0);
+	A : OUT std_logic_vector(15 downto 0);
+	R_W_n : OUT std_logic;
+	CPU_FETCH : out std_logic
+);
+END cpu;
+
+architecture vhdl of cpu is
+component cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end component;
+
+	signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle
+		
+	-- Support for Peter's core (NMI patch applied)
+	signal debugOpcode : unsigned(7 downto 0);
+	signal debugPc : unsigned(15 downto 0);
+	signal debugA : unsigned(7 downto 0);
+	signal debugX : unsigned(7 downto 0);
+	signal debugY : unsigned(7 downto 0);
+	signal debugS : unsigned(7 downto 0);
+	signal di_unsigned : unsigned(7 downto 0);
+   signal do_unsigned : unsigned(7 downto 0);
+	signal addr_unsigned : unsigned(15 downto 0);
+	signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line
+	signal WE : std_logic;
+	signal nmi_pending_next : std_logic; -- NMI during RDY
+	signal nmi_pending_reg : std_logic;
+	signal nmi_n_adjusted : std_logic;
+	signal nmi_n_reg : std_logic;
+	signal nmi_edge : std_logic;
+	
+	signal CPU_ENABLE_RESET : std_logic;
+	signal not_rdy : std_logic;	
+	
+BEGIN
+	CPU_ENABLE <= ENABLE and memory_ready and THROTTLE;
+	
+	-- CPU designed by Peter W - as used in Chameleon
+	di_unsigned <= unsigned(di);
+	cpu_6502_peter:cpu_65xx
+		generic map
+		(
+			pipelineOpcode => false,
+			pipelineAluMux => false,
+			pipelineAluOut => false
+		)
+		port map (
+			clk => clk,
+			enable => CPU_ENABLE_RDY,
+			halt => '0',
+			reset=>reset,
+			nmi_n=>nmi_n_adjusted,
+			irq_n=>irq_n,
+			d=>di_unsigned,
+			q=>do_unsigned,
+			addr=>addr_unsigned,
+			WE=>WE,
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugY,
+			debugS => debugS
+		);
+		CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
+		
+		CPU_ENABLE_RESET <= CPU_ENABLE or reset;
+		not_rdy <= not(rdy);
+		
+		nmi_edge <= not(nmi_n) and nmi_n_reg;
+		nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable));
+		nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n;
+		
+	-- register
+	process(clk,reset)
+	begin
+		if (RESET = '1') then
+			nmi_pending_reg <= '0';
+			nmi_n_reg <= '1';
+		elsif (clk'event and clk='1') then						
+			nmi_pending_reg <= nmi_pending_next;		
+			nmi_n_reg <= nmi_n;
+		end if;
+	end process;	
+
+	-- outputs
+	r_w_n <= not(we);
+	do <= std_logic_vector(do_unsigned);
+	a <= std_logic_vector(addr_unsigned);
+		
+	CPU_FETCH <= ENABLE and THROTTLE;
+
+END vhdl;
Index: common/a8core/cpu_6510.vhd
===================================================================
--- common/a8core/cpu_6510.vhd	(nonexistent)
+++ common/a8core/cpu_6510.vhd	(revision 1)
@@ -0,0 +1,162 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- 6510 wrapper for 65xx core
+-- Adds 8 bit I/O port mapped at addresses $0000 to $0001
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_6510 is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean;
+		emulate_bitfade : boolean
+	);
+	port (
+		clk : in std_logic;
+		ena_1khz : in std_logic := '0';
+		enable : in std_logic;
+		halt : in std_logic;
+		reset : in std_logic;
+		nmi_n : in std_logic;
+		irq_n : in std_logic;
+
+		we : out std_logic;
+		a : out unsigned(15 downto 0);
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+
+		diIO : in unsigned(7 downto 0);
+		doIO : out unsigned(7 downto 0);
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0);
+		debug_io : out unsigned(7 downto 0)
+	);
+end cpu_6510;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_6510 is
+	signal localA : unsigned(15 downto 0);
+	signal localD : unsigned(7 downto 0);
+	signal localQ : unsigned(7 downto 0);
+	signal localWe : std_logic;
+
+	signal currentIO : unsigned(7 downto 0);
+	signal ioDir : unsigned(7 downto 0);
+	signal ioData : unsigned(7 downto 0);
+	
+	signal accessIO : std_logic;
+	signal ioFade : unsigned(7 downto 0) := (others => '0');
+begin
+	cpuInstance: entity work.cpu_65xx
+		generic map (
+			pipelineOpcode => pipelineOpcode,
+			pipelineAluMux => pipelineAluMux,
+			pipelineAluOut => pipelineAluOut
+		)
+		port map (
+			clk => clk,
+			enable => enable,
+			halt => halt,
+			reset => reset,
+			nmi_n => nmi_n,
+			irq_n => irq_n,
+
+			d => localD,
+			q => localQ,
+			addr => localA,
+			we => localWe,
+
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugY,
+			debugS => debugS,
+			debug_flags => debug_flags
+		);
+	
+	process(localA)
+	begin
+		accessIO <= '0';
+		if localA(15 downto 1) = 0 then
+			accessIO <= '1';
+		end if;
+	end process;
+	
+	process(d, localA, ioDir, currentIO, accessIO)
+	begin
+		localD <= d;
+		if accessIO = '1' then
+			if localA(0) = '0' then
+				localD <= ioDir;
+			else
+				localD <= currentIO;
+			end if;
+		end if;
+	end process;
+	
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if accessIO = '1' then
+				if localWe = '1'
+				and enable = '1' then
+					if localA(0) = '0' then
+						ioDir <= localQ;
+					else
+						ioData <= localQ;
+					end if;
+				end if;
+			end if;
+			if reset = '1' then
+				ioDir <= (others => '0');
+			end if;
+		end if;
+	end process;
+	
+	process(ioDir, ioData, diIO)
+	begin
+		for i in 0 to 7 loop
+			if ioDir(i) = '0' then
+				currentIO(i) <= diIO(i);
+			else
+				currentIO(i) <= ioData(i);
+			end if;
+		end loop;
+		if emulate_bitfade then
+			currentIO(7) <= ioFade(7);
+			currentIO(6) <= ioFade(6);
+			currentIO(3) <= ioFade(3);
+		end if;
+	end process;
+	
+	-- Cunnect zee wires
+	a <= localA;
+	q <= localQ;
+	we <= localWe;
+	doIO <= currentIO;
+	debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
+end architecture;
Index: common/a8core/cpu_65xx_a.vhd
===================================================================
--- common/a8core/cpu_65xx_a.vhd	(nonexistent)
+++ common/a8core/cpu_65xx_a.vhd	(revision 1)
@@ -0,0 +1,1599 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processNmi : std_logic := '0';
+	signal processIrq : std_logic := '0';
+	signal processInt : std_logic := '0';
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal so_reg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAX  & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal Creg: std_logic; -- Carry
+	signal Zreg: std_logic; -- Zero flag
+	signal Ireg: std_logic; -- Interrupt flag
+	signal Dreg: std_logic; -- Decimal mode
+	signal Vreg: std_logic; -- Overflow
+	signal Nreg: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := Creg & aluInput;
+		when aluModeP =>
+			rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
+		when aluModeInc =>
+			rmwBits := Creg & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := Creg & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & Creg;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := Creg & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if Dreg = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if Dreg = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if Dreg = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if Dreg = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then -- and (halt = '0') then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+					
+					if theCpuCycle = cycleStack4 -- MWW
+					or reset = '1' then
+						nmiReg <= '1';
+					end if;					
+				if halt = '0' then
+					if theCpuCycle /= cycleBranchTaken then
+						-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+						-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+						processNmi <= not (nmiReg or opcInfo(opcIRQ));
+						processIrq <= not (irqReg or opcInfo(opcIRQ));
+					end if;
+				end if;
+			end if;
+			processInt <= processNmi or (processIrq and (not Ireg));
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, d, reset, processInt)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := d;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processInt = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processInt = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, halt, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if (enable = '1') and (halt = '0') then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= d;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= d;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= d;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					Creg <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Zreg <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					Ireg <= aluInput(2);
+				end if;
+			end if;
+			-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
+			if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
+				if (theOpcode = X"58") then
+					Ireg <= '0';
+				end if;
+				if (theOpcode = X"78") then
+					Ireg <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					Dreg <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					Vreg <= aluV;
+				end if;
+			end if;
+			if so_reg = '1' and so_n = '0' then
+				Vreg <= '1';
+			end if;
+			so_reg <= so_n;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					Nreg <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if (enable = '1') and (halt = '0') then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					q <= T; -- Read-modify-write write old value first.
+					doReg <= d; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	q <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+				if reset = '1' then
+					theWe <= '0';
+				end if;
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else
+							PC <= myAddr;
+						end if;
+					end if;
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset, processInt)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when opcodeFetch =>
+			if processInt = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else
+				nextAddr <= nextAddrAbsIndexed;
+			end if;
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then
+				halt_dly <= halt;
+			end if;
+			if (enable = '1') and (halt = '0') then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
+--				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= d & T;
+				when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & d;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+			if (enable = '1') and (halt_dly = '0') then
+				case nextAddr is
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
+					else myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
+
+end architecture;
+
+
Index: common/a8core/cpu_65xx_e.vhd
===================================================================
--- common/a8core/cpu_65xx_e.vhd	(nonexistent)
+++ common/a8core/cpu_65xx_e.vhd	(revision 1)
@@ -0,0 +1,52 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Interface to 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end entity;
Index: common/a8core/delay_line.vhdl
===================================================================
--- common/a8core/delay_line.vhdl	(nonexistent)
+++ common/a8core/delay_line.vhdl	(revision 1)
@@ -0,0 +1,57 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY delay_line IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC
+);
+END delay_line;
+
+ARCHITECTURE vhdl OF delay_line IS
+	signal shift_reg : std_logic_vector(COUNT-1 downto 0);
+	signal shift_next : std_logic_vector(COUNT-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>'0');
+		end if;		
+	end process;
+	
+	-- output
+	data_out <= shift_reg(0) and enable;
+		
+END vhdl;
Index: common/a8core/enable_divider.vhdl
===================================================================
--- common/a8core/enable_divider.vhdl	(nonexistent)
+++ common/a8core/enable_divider.vhdl	(revision 1)
@@ -0,0 +1,76 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY enable_divider IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END enable_divider;
+
+ARCHITECTURE vhdl OF enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: common/a8core/generic_ram_infer.vhdl
===================================================================
--- common/a8core/generic_ram_infer.vhdl	(nonexistent)
+++ common/a8core/generic_ram_infer.vhdl	(revision 1)
@@ -0,0 +1,42 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+ENTITY generic_ram_infer IS
+	generic
+	(
+		ADDRESS_WIDTH : natural := 9;
+		SPACE : natural := 512;
+		DATA_WIDTH : natural := 8
+	);
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+      address:  IN   std_logic_vector(address_width-1 downto 0);
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+   );
+END generic_ram_infer;
+
+ARCHITECTURE rtl OF generic_ram_infer IS
+   TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(to_integer(unsigned(address))) <= data;
+         END IF;
+         q <= ram_block(to_integer(unsigned(address)));
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: common/a8core/gtia.vhdl
===================================================================
--- common/a8core/gtia.vhdl	(nonexistent)
+++ common/a8core/gtia.vhdl	(revision 1)
@@ -0,0 +1,1569 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	CPU_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_FETCH : IN STD_LOGIC;
+	
+	CPU_ENABLE_ORIGINAL : in std_logic;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	PAL : IN STD_LOGIC;
+	
+	-- ANTIC interface
+	COLOUR_CLOCK_ORIGINAL : in std_logic;
+	COLOUR_CLOCK : in std_logic;
+	COLOUR_CLOCK_HIGHRES : in std_logic;
+	AN : IN STD_LOGIC_VECTOR(2 downto 0);
+	
+	-- keyboard interface
+	CONSOL_START : IN STD_LOGIC;
+	CONSOL_SELECT : IN STD_LOGIC;
+	CONSOL_OPTION : IN STD_LOGIC;
+	
+	-- keyboard interface
+	TRIG0 : IN STD_LOGIC;
+	TRIG1 : IN STD_LOGIC;
+	TRIG2 : IN STD_LOGIC;
+	TRIG3 : IN STD_LOGIC;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	-- TO scandoubler...
+	COLOUR_out : out std_logic_vector(7 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic;
+	BLANK : out std_logic;
+	
+	-- To speaker
+	sound : out std_logic
+);
+END gtia;
+
+ARCHITECTURE vhdl OF gtia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component gtia_player IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : in std_logic;
+		
+		COLOUR_ENABLE : IN STD_LOGIC;
+		LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+		PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+		SIZE : in std_logic_vector(1 downto 0);
+		bitmap : in std_logic_vector(7 downto 0);
+		
+		output : out std_logic
+	);
+	END component;
+	
+	component gtia_priority IS
+	PORT 
+	( 
+		CLK : in std_logic;
+		colour_enable : in std_logic;
+		PRIOR : in std_logic_vector(7 downto 0);
+		P0 : in std_logic;
+		P1 : in std_logic;
+		P2	: in std_logic;
+		P3 : in std_logic;
+		PF0 : in std_logic;
+		PF1 : in std_logic;
+		PF2 : in std_logic;
+		PF3 : in std_logic;
+		BK : in std_logic;
+		
+		P0_OUT : out std_logic;
+		P1_OUT : out std_logic;
+		P2_OUT : out std_logic;
+		P3_OUT : out std_logic;
+		PF0_OUT : out std_logic;
+		PF1_OUT : out std_logic;
+		PF2_OUT : out std_logic;
+		PF3_OUT : out std_logic;
+		BK_OUT : out std_logic
+	);
+	END component;	
+	
+	signal addr_decoded : std_logic_vector(31 downto 0);
+	
+	signal hposp0_raw_next : std_logic_vector(7 downto 0);
+	signal hposp0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp1_raw_next : std_logic_vector(7 downto 0);
+	signal hposp1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp2_raw_next : std_logic_vector(7 downto 0);
+	signal hposp2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp3_raw_next : std_logic_vector(7 downto 0);
+	signal hposp3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp3_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal hposm0_raw_next : std_logic_vector(7 downto 0);
+	signal hposm0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm1_raw_next : std_logic_vector(7 downto 0);
+	signal hposm1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm2_raw_next : std_logic_vector(7 downto 0);
+	signal hposm2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm3_raw_next : std_logic_vector(7 downto 0);
+	signal hposm3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm3_delayed_reg : std_logic_vector(7 downto 0);	
+	
+	signal sizep0_raw_next : std_logic_vector(1 downto 0);
+	signal sizep0_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep1_raw_next : std_logic_vector(1 downto 0);
+	signal sizep1_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep2_raw_next : std_logic_vector(1 downto 0);
+	signal sizep2_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep3_raw_next : std_logic_vector(1 downto 0);
+	signal sizep3_raw_reg : std_logic_vector(1 downto 0);
+
+	signal sizem_raw_next : std_logic_vector(7 downto 0);
+	signal sizem_raw_reg : std_logic_vector(7 downto 0);
+
+	signal sizep0_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep1_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep2_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep3_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizem_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal grafp0_next : std_logic_vector(7 downto 0);
+	signal grafp0_reg : std_logic_vector(7 downto 0);
+	signal grafp1_next : std_logic_vector(7 downto 0);
+	signal grafp1_reg : std_logic_vector(7 downto 0);
+	signal grafp2_next : std_logic_vector(7 downto 0);
+	signal grafp2_reg : std_logic_vector(7 downto 0);
+	signal grafp3_next : std_logic_vector(7 downto 0);
+	signal grafp3_reg : std_logic_vector(7 downto 0);
+	
+	signal grafm_next : std_logic_vector(7 downto 0);
+	signal grafm_reg : std_logic_vector(7 downto 0);
+
+	signal grafm_reg10_extended : std_logic_vector(7 downto 0);
+	signal grafm_reg32_extended : std_logic_vector(7 downto 0);
+	signal grafm_reg54_extended : std_logic_vector(7 downto 0);
+	signal grafm_reg76_extended : std_logic_vector(7 downto 0);
+
+	signal colpm0_raw_next : std_logic_vector(7 downto 1);
+	signal colpm0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm1_raw_next : std_logic_vector(7 downto 1);
+	signal colpm1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm2_raw_next : std_logic_vector(7 downto 1);
+	signal colpm2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm3_raw_next : std_logic_vector(7 downto 1);
+	signal colpm3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colpf0_raw_next : std_logic_vector(7 downto 1);
+	signal colpf0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf1_raw_next : std_logic_vector(7 downto 1);
+	signal colpf1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf2_raw_next : std_logic_vector(7 downto 1);
+	signal colpf2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf3_raw_next : std_logic_vector(7 downto 1);
+	signal colpf3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colbk_raw_next : std_logic_vector(7 downto 1);
+	signal colbk_raw_reg : std_logic_vector(7 downto 1);
+	signal colbk_delayed_reg : std_logic_vector(7 downto 1);	
+	
+	signal prior_raw_next : std_logic_vector(7 downto 0);
+	signal prior_raw_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed2_reg : std_logic_vector(7 downto 6);
+	
+	signal vdelay_next : std_logic_vector(7 downto 0);
+	signal vdelay_reg : std_logic_vector(7 downto 0);
+
+	signal gractl_next : std_logic_vector(2 downto 0);
+	signal gractl_reg : std_logic_vector(2 downto 0);
+	
+	signal consol_output_next : std_logic_vector(3 downto 0);
+	signal consol_output_reg : std_logic_vector(3 downto 0);
+	
+	signal trig0_next : std_logic;
+	signal trig0_reg : std_logic;
+	signal trig1_next : std_logic;
+	signal trig1_reg : std_logic;
+	signal trig2_next : std_logic;
+	signal trig2_reg : std_logic;
+	signal trig3_next : std_logic;
+	signal trig3_reg : std_logic;
+	
+	-- collisions
+	signal hitclr_write : std_logic;
+	
+	signal m0pf_next : std_logic_vector(3 downto 0);
+	signal m0pf_reg : std_logic_vector(3 downto 0);
+	signal m1pf_next : std_logic_vector(3 downto 0);
+	signal m1pf_reg : std_logic_vector(3 downto 0);
+	signal m2pf_next : std_logic_vector(3 downto 0);
+	signal m2pf_reg : std_logic_vector(3 downto 0);
+	signal m3pf_next : std_logic_vector(3 downto 0);
+	signal m3pf_reg : std_logic_vector(3 downto 0);
+
+	signal m0pl_next : std_logic_vector(3 downto 0);
+	signal m0pl_reg : std_logic_vector(3 downto 0);
+	signal m1pl_next : std_logic_vector(3 downto 0);
+	signal m1pl_reg : std_logic_vector(3 downto 0);
+	signal m2pl_next : std_logic_vector(3 downto 0);
+	signal m2pl_reg : std_logic_vector(3 downto 0);
+	signal m3pl_next : std_logic_vector(3 downto 0);
+	signal m3pl_reg : std_logic_vector(3 downto 0);
+	
+	signal p0pf_next : std_logic_vector(3 downto 0);
+	signal p0pf_reg : std_logic_vector(3 downto 0);
+	signal p1pf_next : std_logic_vector(3 downto 0);
+	signal p1pf_reg : std_logic_vector(3 downto 0);
+	signal p2pf_next : std_logic_vector(3 downto 0);
+	signal p2pf_reg : std_logic_vector(3 downto 0);
+	signal p3pf_next : std_logic_vector(3 downto 0);
+	signal p3pf_reg : std_logic_vector(3 downto 0);	
+	
+	signal p0pl_next : std_logic_vector(3 downto 0);
+	signal p0pl_reg : std_logic_vector(3 downto 0);
+	signal p1pl_next : std_logic_vector(3 downto 0);
+	signal p1pl_reg : std_logic_vector(3 downto 0);
+	signal p2pl_next : std_logic_vector(3 downto 0);
+	signal p2pl_reg : std_logic_vector(3 downto 0);
+	signal p3pl_next : std_logic_vector(3 downto 0);
+	signal p3pl_reg : std_logic_vector(3 downto 0);		
+	
+	-- priority
+	signal set_p0 : std_logic;
+	signal set_p1 : std_logic;
+	signal set_p2 : std_logic;
+	signal set_p3 : std_logic;
+	signal set_pf0 : std_logic;
+	signal set_pf1 : std_logic;
+	signal set_pf2 : std_logic;
+	signal set_pf3 : std_logic;
+	signal set_bk : std_logic;	
+	
+	-- ouput/sync
+	signal COLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal COLOUR_REG : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_REG : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+	
+	signal hsync_start : std_logic;
+	signal hsync_end : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	-- visible region (no collision detection outside this)
+	signal visible_live : std_logic;
+	
+	-- antic input decode
+	signal an_prev3_next : std_logic_vector(2 downto 0);
+	signal an_prev3_reg : std_logic_vector(2 downto 0);	
+	signal an_prev2_next : std_logic_vector(2 downto 0);
+	signal an_prev2_reg : std_logic_vector(2 downto 0);	
+	signal an_prev_next : std_logic_vector(2 downto 0);
+	signal an_prev_reg : std_logic_vector(2 downto 0);
+	
+	signal active_bk_modify_next : std_logic_vector(7 downto 0);
+	signal active_bk_modify_reg : std_logic_vector(7 downto 0);
+	signal active_bk_valid_next : std_logic_vector(7 downto 0);
+	signal active_bk_valid_reg : std_logic_vector(7 downto 0);
+	signal active_bk_live : std_logic;
+	signal active_pf0_live : std_logic;
+	signal active_pf1_live : std_logic;
+	signal active_pf2_live : std_logic;
+	signal active_pf2_collision_live : std_logic;
+	signal active_pf3_live : std_logic;
+	signal active_pf3_collision_live : std_logic;
+	signal active_pm0_live : std_logic;
+	signal active_pm1_live : std_logic;
+	signal active_pm2_live : std_logic;
+	signal active_pm3_live : std_logic;
+	
+	signal active_p0_live : std_logic;
+	signal active_p1_live : std_logic;
+	signal active_p2_live : std_logic;
+	signal active_p3_live : std_logic;
+	signal active_m0_live : std_logic;
+	signal active_m1_live : std_logic;
+	signal active_m2_live : std_logic;
+	signal active_m3_live : std_logic;
+	
+	signal active_hr_next : std_logic_vector(1 downto 0);
+	signal active_hr_reg : std_logic_vector(1 downto 0);
+	signal highres_next : std_logic;
+	signal highres_reg : std_logic;
+	
+	-- horizontal position counter
+	signal hpos_reg : std_logic_vector(7 downto 0);
+	signal reset_counter : std_logic;
+	signal counter_load_value : std_logic_vector(7 downto 0);
+	
+	-- sub colour clock highres mode	
+	signal trigger_secondhalf : std_logic;
+	
+	-- pmg dma
+	signal grafm_dma_load : std_logic;
+	signal grafm_dma_next : std_logic_vector(7 downto 0);
+	signal grafp0_dma_load : std_logic;
+	signal grafp0_dma_next : std_logic_vector(7 downto 0);
+	signal grafp1_dma_load : std_logic;
+	signal grafp1_dma_next : std_logic_vector(7 downto 0);
+	signal grafp2_dma_load : std_logic;
+	signal grafp2_dma_next : std_logic_vector(7 downto 0);
+	signal grafp3_dma_load : std_logic;
+	signal grafp3_dma_next : std_logic_vector(7 downto 0);
+	signal odd_scanline_next : std_logic;
+	signal odd_scanline_reg : std_logic;
+	
+	signal pmg_dma_state_next : std_logic_vector(2 downto 0);
+	signal pmg_dma_state_reg : std_logic_vector(2 downto 0);
+	constant pmg_dma_missile : std_logic_vector(2 downto 0) := "000";
+	constant pmg_dma_player0 : std_logic_vector(2 downto 0) := "001";
+	constant pmg_dma_player1 : std_logic_vector(2 downto 0) := "010";
+	constant pmg_dma_player2 : std_logic_vector(2 downto 0) := "011";
+	constant pmg_dma_player3 : std_logic_vector(2 downto 0) := "100";
+	constant pmg_dma_done    : std_logic_vector(2 downto 0) := "101";	
+	constant pmg_dma_instruction : std_logic_vector(2 downto 0) := "110";	
+	
+	signal memory_ready : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			hposp0_raw_reg <= (others=>'0');
+			hposp1_raw_reg <= (others=>'0');
+			hposp2_raw_reg <= (others=>'0');
+			hposp3_raw_reg <= (others=>'0');
+
+			hposm0_raw_reg <= (others=>'0');
+			hposm1_raw_reg <= (others=>'0');
+			hposm2_raw_reg <= (others=>'0');
+			hposm3_raw_reg <= (others=>'0');			
+
+			sizep0_raw_reg <= (others=>'0');
+			sizep1_raw_reg <= (others=>'0');
+			sizep2_raw_reg <= (others=>'0');
+			sizep3_raw_reg <= (others=>'0');
+
+			sizem_raw_reg <= (others=>'0');
+			
+			grafp0_reg <= (others=>'0');
+			grafp1_reg <= (others=>'0');
+			grafp2_reg <= (others=>'0');
+			grafp3_reg <= (others=>'0');
+
+			grafm_reg <= (others=>'0');
+			
+			colpm0_raw_reg <= (others=>'0');
+			colpm1_raw_reg <= (others=>'0');
+			colpm2_raw_reg <= (others=>'0');
+			colpm3_raw_reg <= (others=>'0');
+
+			colpf0_raw_reg <= (others=>'0');
+			colpf1_raw_reg <= (others=>'0');
+			colpf2_raw_reg <= (others=>'0');
+			colpf3_raw_reg <= (others=>'0');
+			
+			colbk_raw_reg <= (others=>'0');
+			
+			prior_raw_reg <= (others=>'0');
+			
+			vdelay_reg <= (others=>'0');
+			
+			gractl_reg <= (others=>'0');
+			
+			consol_output_reg <= (others=>'1');
+			
+			COLOUR_REG <= (OTHERS=>'0');
+			HRCOLOUR_REG <= (OTHERS=>'0');
+			
+			vsync_reg <= '0';
+			hsync_reg <= '0';
+			hblank_reg <= '0';
+			
+			an_prev_reg <= (others=>'0');
+			an_prev2_reg <= (others=>'0');
+			an_prev3_reg <= (others=>'0');
+			
+			highres_reg <= '0';
+			active_hr_reg <= (others=>'0');
+			
+			trig0_reg <= '0';
+			trig1_reg <= '0';
+			trig2_reg <= '0';
+			trig3_reg <= '0';
+			
+			odd_scanline_reg <= '0';
+			
+			pmg_dma_state_reg <= pmg_dma_done;
+			
+			m0pf_reg <= (others=>'0');
+			m1pf_reg <= (others=>'0');
+			m2pf_reg <= (others=>'0');
+			m3pf_reg <= (others=>'0');
+			m0pl_reg <= (others=>'0');
+			m1pl_reg <= (others=>'0');
+			m2pl_reg <= (others=>'0');
+			m3pl_reg <= (others=>'0');
+			
+			p0pf_reg <= (others=>'0');
+			p1pf_reg <= (others=>'0');
+			p2pf_reg <= (others=>'0');
+			p3pf_reg <= (others=>'0');
+			p0pl_reg <= (others=>'0');
+			p1pl_reg <= (others=>'0');
+			p2pl_reg <= (others=>'0');
+			p3pl_reg <= (others=>'0');	
+			
+			active_bk_modify_reg <= (others=>'0');
+			active_bk_valid_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then										
+			hposp0_raw_reg <= hposp0_raw_next;
+			hposp1_raw_reg <= hposp1_raw_next;
+			hposp2_raw_reg <= hposp2_raw_next;
+			hposp3_raw_reg <= hposp3_raw_next;
+
+			hposm0_raw_reg <= hposm0_raw_next;
+			hposm1_raw_reg <= hposm1_raw_next;
+			hposm2_raw_reg <= hposm2_raw_next;
+			hposm3_raw_reg <= hposm3_raw_next;			
+
+			sizep0_raw_reg <= sizep0_raw_next;
+			sizep1_raw_reg <= sizep1_raw_next;
+			sizep2_raw_reg <= sizep2_raw_next;
+			sizep3_raw_reg <= sizep3_raw_next;
+
+			sizem_raw_reg <= sizem_raw_next;
+			
+			grafp0_reg <= grafp0_next;
+			grafp1_reg <= grafp1_next;
+			grafp2_reg <= grafp2_next;
+			grafp3_reg <= grafp3_next;
+
+			grafm_reg <= grafm_next;
+			
+			colpm0_raw_reg <= colpm0_raw_next;
+			colpm1_raw_reg <= colpm1_raw_next;
+			colpm2_raw_reg <= colpm2_raw_next;
+			colpm3_raw_reg <= colpm3_raw_next;
+
+			colpf0_raw_reg <= colpf0_raw_next;
+			colpf1_raw_reg <= colpf1_raw_next;
+			colpf2_raw_reg <= colpf2_raw_next;
+			colpf3_raw_reg <= colpf3_raw_next;
+			
+			colbk_raw_reg <= colbk_raw_next;
+			
+			prior_raw_reg <= prior_raw_next;
+			
+			vdelay_reg <= vdelay_next;
+			
+			gractl_reg <= gractl_next;
+			
+			consol_output_reg <= consol_output_next;		
+
+			COLOUR_REG <= colour_next;
+			HRCOLOUR_REG <= hrcolour_next;
+			
+			vsync_reg <= vsync_next;
+			hsync_reg <= hsync_next;
+			hblank_reg <= hblank_next;
+			
+			an_prev_reg <= an_prev_next;
+			an_prev2_reg <= an_prev2_next;
+			an_prev3_reg <= an_prev3_next;
+	
+			highres_reg <= highres_next;
+			active_hr_reg <= active_hr_next;
+			
+			trig0_reg <= trig0_next;
+			trig1_reg <= trig1_next;
+			trig2_reg <= trig2_next;
+			trig3_reg <= trig3_next;
+			
+			odd_scanline_reg <= odd_scanline_next;
+			
+			pmg_dma_state_reg <= pmg_dma_state_next;
+			
+			m0pf_reg <= m0pf_next;
+			m1pf_reg <= m1pf_next;
+			m2pf_reg <= m2pf_next;
+			m3pf_reg <= m3pf_next;
+			m0pl_reg <= m0pl_next;
+			m1pl_reg <= m1pl_next;
+			m2pl_reg <= m2pl_next;
+			m3pl_reg <= m3pl_next;
+			
+			p0pf_reg <= p0pf_next;
+			p1pf_reg <= p1pf_next;
+			p2pf_reg <= p2pf_next;
+			p3pf_reg <= p3pf_next;
+			p0pl_reg <= p0pl_next;
+			p1pl_reg <= p1pl_next;
+			p2pl_reg <= p2pl_next;
+			p3pl_reg <= p3pl_next;
+			
+			active_bk_modify_reg <= active_bk_modify_next;
+			active_bk_valid_reg <= active_bk_valid_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>5)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+		
+	-- decode antic input
+	process (AN, COLOUR_CLOCK, COLOUR_CLOCK_ORIGINAL, an_prev_reg, an_prev2_reg, an_prev3_reg, hblank_reg, vsync_reg, highres_reg, odd_scanline_reg, prior_delayed_reg, prior_delayed2_reg, hpos_reg, active_p0_live, active_p1_live, active_p2_live, active_p3_live, active_m0_live, active_m1_live, active_m2_live, active_m3_live, active_pf3_collision_live, active_bk_modify_reg, active_bk_modify_next, active_bk_valid_reg, active_hr_reg, visible_live)
+	begin	
+		hblank_next <= hblank_reg;
+		reset_counter <= '0';
+		counter_load_value <= (others=>'0');
+		vsync_next <= vsync_reg;
+		
+		odd_scanline_next <= odd_scanline_reg;
+			
+		-- NB high res mode gives pf2 - which is or of the two pixels
+		highres_next <= highres_reg;
+		
+		-- for gtia modes
+		an_prev_next <= an_prev_reg;
+		an_prev2_next <= an_prev2_reg;
+		an_prev3_next <= an_prev3_reg;
+		
+		-- decoded AN
+		visible_live <= '0';
+		
+		active_hr_next <= active_hr_reg;
+		
+		active_bk_modify_next <= active_bk_modify_reg;
+		active_bk_valid_next <= active_bk_valid_reg;
+		active_bk_live <= '0';
+		active_pf0_live <= '0';
+		active_pf1_live <= '0';
+		active_pf2_live <= '0';
+		active_pf2_collision_live <= '0';
+		active_pf3_live <= '0';
+		active_pf3_collision_live <= '0';
+		active_pm0_live <= '0';
+		active_pm1_live <= '0';
+		active_pm2_live <= '0';
+		active_pm3_live <= '0';
+		
+		if (COLOUR_CLOCK = '1') then	
+			visible_live <= '1';
+			vsync_next <= '0';
+			hblank_next <= '0';
+			an_prev_next <= an;
+			an_prev2_next <= an_prev_reg;
+			an_prev3_next <= an_prev2_reg;
+			
+			active_pm0_live <= active_p0_live or (active_m0_live and not(prior_delayed_reg(4)));
+			active_pm1_live <= active_p1_live or (active_m1_live and not(prior_delayed_reg(4)));
+			active_pm2_live <= active_p2_live or (active_m2_live and not(prior_delayed_reg(4)));
+			active_pm3_live <= active_p3_live or (active_m3_live and not(prior_delayed_reg(4)));			
+			
+			active_bk_modify_next <= (others=>'0');
+			active_bk_valid_next <= (others=>'1');
+			
+			active_hr_next <= (others=>'0');
+		
+			-- 000 background colour
+			-- 001 vsync
+			-- 01X hsync (low bit is high res mode - i.e. 2 pixels per colour clock)
+			-- 1XX colour 0 to colour 3
+			
+			-- in gtia modes then we listen for 2 colour clocks to get one pixels
+			-- 1ZY (giving signal ZYXV for 4 bit colour reg/luminance - unfortunately we only have 9 colour regs!)
+			-- 1XV
+			
+			if (highres_reg = '1') then
+				if (an(2) = '1') then
+					active_hr_next <= AN(1 downto 0);				
+				end if;
+				
+				active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= an(2);
+				active_pf2_collision_live <= an(2) and (an(1) or an(0));
+				active_pf3_collision_live <= '0';				
+			else								
+				-- gtia modes										
+				case prior_delayed_reg(7 downto 6) is
+					when "00" => 
+						-- normal mode
+						active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+						active_pf0_live <= an(2) and not(an(1)) and not(an(0));
+						active_pf1_live <= an(2) and not(an(1)) and an(0);
+						active_pf2_live <= an(2) and      an(1) and not(an(0));
+						active_pf2_collision_live <= an(2) and      an(1) and not(an(0));
+						active_pf3_collision_live <= an(2) and      an(1) and an(0);
+					when "01" =>
+						-- 1 colour/16 luminance
+						-- no playfield collisions
+						-- 5th player gets my luminance
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';						
+						active_bk_live <= '1';
+						
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(3 downto 0) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(3 downto 0) <= active_bk_modify_reg(3 downto 0);
+						end if;
+					when "10" => 
+						-- 9 colour
+						-- playfield collisions
+						-- no missile/player collisions from 'playfield' data though		
+						-- offset by 1 colour clock...
+						if (hpos_reg(0) = '1') then
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev_reg(1 downto 0)&an(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an(2);
+									active_pf2_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;
+						else
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev2_reg(1 downto 0)&an_prev_reg(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an_prev_reg(2);
+									active_pf2_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;									
+						end if;
+						
+					when "11" =>
+						-- 16 colour/1 luminance
+						-- no playfield collisions
+						-- 5th player gets our luminance
+						active_bk_live <= '1';
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';	
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(7 downto 4) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(7 downto 4) <= active_bk_modify_reg(7 downto 4);
+						end if;
+						
+						if (active_bk_modify_next(7 downto 4) = "0000") then
+							active_bk_valid_next(3 downto 0) <= "0000";
+						end if;
+					when others =>
+						-- nop
+				end case;
+			end if;
+			
+			if (prior_delayed_reg(4) = '1') then
+				active_pf3_live <= active_pf3_collision_live or active_m0_live or active_m1_live or active_m2_live or active_m3_live;
+			else
+				active_pf3_live <= active_pf3_collision_live;
+			end if;
+			
+			if (not (prior_delayed2_reg(7 downto 6) = "00")) then
+				-- force off flip flop when in gtia mode
+				highres_next <= '0';
+			end if;
+			
+			-- hblank
+			if (an_prev_reg(2 downto 1) = "01") then
+				hblank_next <= '1';
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				highres_next <= an_prev_reg(0);
+			
+				if (COLOUR_CLOCK_ORIGINAL='1') then				
+					if (hblank_reg = '0' and vsync_reg = '0') then
+						reset_counter <= '1';
+						counter_load_value <= X"E0"; -- 2 lower than antic
+						odd_scanline_next <= not(odd_scanline_reg);
+					end if;
+				end if;
+			end if;
+			if (an(2 downto 1) = "01") then
+				visible_live <= '0';
+			end if;			
+	
+			-- vsync
+			if (an_prev_reg = "001") then
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				
+				vsync_next <= '1';
+
+				odd_scanline_next <= '0';
+				
+				visible_live <= '0';
+			end if;
+			
+			-- during vblank we reset our own counter - since Antic does not clear hblank_reg
+			if (hpos_reg = X"E3" and COLOUR_CLOCK_ORIGINAL='1') then
+				reset_counter <= '1';
+				counter_load_value <= X"00";
+			end if;
+
+		end if;
+	end process;
+	
+	-- hpos
+	counter_hpos : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>COLOUR_CLOCK_ORIGINAL, load=>reset_counter, load_value=>counter_load_value, current_value=>hpos_reg);
+	
+	-- visible region
+--	process(hpos_reg,vpos_reg)
+--	begin		
+--		visible_live <= '1';
+--		
+----		if (unsigned(vpos_reg) < to_unsigned(8,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(vpos_reg) > to_unsigned(247,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) <= to_unsigned(34,8)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) > to_unsigned(221,8)) then
+----			visible_live <= '0';
+----		end if;		
+--	end process;
+	
+	-- generate hsync
+	process(hpos_reg, hsync_reg, hsync_end, vsync_reg, vsync_next)
+	begin
+		hsync_start <= '0';
+		hsync_next <= hsync_reg;
+
+		if (unsigned(hpos_reg) = X"D4" and vsync_reg = '1') then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+	
+		if (unsigned(hpos_reg) = X"0" and vsync_reg = '0' ) then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+			
+		if (hsync_end = '1') then
+			hsync_next <= '0';
+		end if;
+		
+		if (vsync_next = '0' and vsync_reg = '1') then
+			hsync_next <= '0';
+		end if;
+	end process;
+
+	hsync_delay : delay_line
+		generic map (COUNT=>15)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hsync_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hsync_end);	
+
+	-- pmg dma
+	MEMORY_READY <= CPU_MEMORY_READY or ANTIC_MEMORY_READY; -- TODO, REVIEW timing vs CPU/ANTIC - simpler may be possible now
+	process(antic_fetch,CPU_ENABLE_ORIGINAL,memory_ready,memory_data_in,hsync_start,pmg_dma_state_reg,gractl_reg,odd_scanline_reg,vdelay_reg,grafm_reg, visible_live,hpos_reg, hblank_reg)
+	begin
+		pmg_dma_state_next <= pmg_dma_state_reg;
+		grafm_dma_load <= '0';
+		grafm_dma_next <= grafm_reg;		
+		grafp0_dma_load <= '0';
+		grafp0_dma_next <= (others=>'0');
+		grafp1_dma_load <= '0';
+		grafp1_dma_next <= (others=>'0');
+		grafp2_dma_load <= '0';
+		grafp2_dma_next <= (others=>'0');
+		grafp3_dma_load <= '0';
+		grafp3_dma_next <= (others=>'0');
+	
+		-- pull pmg data from bus
+		if (hpos_reg = X"E1") then
+			pmg_dma_state_next <= pmg_dma_missile;
+		end if;
+		
+		-- we start from the first antic refresh cycle
+		-- TODO - CPU enable does not identify next 'antic' cycle in turbo mode...
+		case pmg_dma_state_reg is
+			when pmg_dma_missile =>
+				if (antic_fetch = '1' and memory_ready = '1' and hblank_reg = '1' and visible_live = '0' and hpos_reg(7 downto 4) = "0000") then
+					-- here we have the missile0					
+					grafm_dma_load <= gractl_reg(0);
+				
+					if ((odd_scanline_reg or not(vdelay_reg(0))) = '1') then
+						grafm_dma_next(1 downto 0) <= memory_data_in(1 downto 0);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(1))) = '1') then
+						grafm_dma_next(3 downto 2) <= memory_data_in(3 downto 2);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(2))) = '1') then
+						grafm_dma_next(5 downto 4) <= memory_data_in(5 downto 4);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(3))) = '1') then
+						grafm_dma_next(7 downto 6) <= memory_data_in(7 downto 6);
+					end if;
+					
+					pmg_dma_state_next <= pmg_dma_instruction;
+				end if;
+			when pmg_dma_instruction =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					pmg_dma_state_next <= pmg_dma_player0;
+				end if;			
+			when pmg_dma_player0 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player0
+					grafp0_dma_next <= memory_data_in;				
+					grafp0_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(4)));
+					pmg_dma_state_next <= pmg_dma_player1;
+				end if;
+			when pmg_dma_player1 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp1_dma_next <= memory_data_in;
+					grafp1_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(5)));
+					pmg_dma_state_next <= pmg_dma_player2;
+				end if;
+			when pmg_dma_player2 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp2_dma_next <= memory_data_in;
+					grafp2_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(6)));
+					pmg_dma_state_next <= pmg_dma_player3;
+				end if;				
+			when pmg_dma_player3 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp3_dma_next <= memory_data_in;				
+					grafp3_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(7)));
+					pmg_dma_state_next <= pmg_dma_done;
+				end if;
+			when others =>
+				-- nop
+		end case;
+	end process;
+		
+	-- pmg display - same for all pmgs
+	-- TODO: priority
+	player0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp0_delayed_reg,size=>sizep0_delayed_reg(1 downto 0),bitmap=>grafp0_reg, output=>active_p0_live);	
+	player1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp1_delayed_reg,size=>sizep1_delayed_reg(1 downto 0),bitmap=>grafp1_reg, output=>active_p1_live);	
+	player2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp2_delayed_reg,size=>sizep2_delayed_reg(1 downto 0),bitmap=>grafp2_reg, output=>active_p2_live);	
+	player3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);				
+
+	grafm_reg10_extended <= grafm_reg(1 downto 0)&"000000";
+	grafm_reg32_extended <= grafm_reg(3 downto 2)&"000000";
+	grafm_reg54_extended <= grafm_reg(5 downto 4)&"000000";
+	grafm_reg76_extended <= grafm_reg(7 downto 6)&"000000";
+	missile0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg10_extended, output=>active_m0_live);
+	missile1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg32_extended, output=>active_m1_live);
+	missile2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg54_extended, output=>active_m2_live);
+	missile3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg76_extended, output=>active_m3_live);
+		
+	-- calculate atari colour
+	priority_rules : gtia_priority
+		port map(clk=>clk, colour_enable=>colour_clock, prior=>prior_delayed_reg,p0=>active_pm0_live,p1=>active_pm1_live,p2=>active_pm2_live,p3=>active_pm3_live,pf0=>active_pf0_live,pf1=>active_pf1_live,pf2=>active_pf2_live,pf3=>active_pf3_live,bk=>active_bk_live,p0_out=>set_p0,p1_out=>set_p1,p2_out=>set_p2,p3_out=>set_p3,pf0_out=>set_pf0,pf1_out=>set_pf1,pf2_out=>set_pf2,pf3_out=>set_pf3,bk_out=>set_bk);	
+
+	trigger_secondhalf <= colour_clock_HIGHRES and not colour_clock;
+	process(set_p0,set_p1,set_p2,set_p3,set_pf0,set_pf1,set_pf2,set_pf3,set_bk,highres_reg, active_hr_reg, colbk_delayed_reg, colpf0_delayed_reg, colpf1_delayed_reg, colpf2_delayed_reg, colpf3_delayed_reg, colpm0_delayed_reg, colpm1_delayed_reg, colpm2_delayed_reg, colpm3_delayed_reg, trigger_secondhalf, colour_clock, COLOUR_REG, hrcolour_reg, visible_live, active_bk_modify_next, active_bk_valid_next)
+	begin
+		colour_next <= colour_reg;
+		hrcolour_next <= hrcolour_reg;
+		
+		if (trigger_secondhalf = '1') then
+			if (highres_reg = '1') then
+				colour_next <= hrcolour_reg;
+			end if;
+		end if;		
+		
+		if (colour_clock = '1') then 
+			colour_next <= 
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+			hrcolour_next <= -- SAME FIXME
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+						
+			-- finally high-res mode overrides the luma
+			if (set_bk = '0' and highres_reg = '1') then
+			
+				if (active_hr_reg(1) = '1') then
+					colour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';						
+				end if;
+				
+				if (active_hr_reg(0) = '1') then						
+					hrcolour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
+				end if;
+			end if;				
+			
+			if (visible_live = '0') then
+				colour_next <= X"00";
+				hrcolour_next <= X"00";
+			end if;			
+		end if;
+	end process;
+
+	-- collision detection
+	process (colour_clock, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg,hitclr_write,active_pf0_live,active_pf1_live,active_pf2_collision_live,active_pf3_collision_live,active_p0_live,active_p1_live,active_p2_live,active_p3_live,active_m0_live,active_m1_live,active_m2_live,active_m3_live, visible_live)
+	begin
+		m0pf_next <= m0pf_reg;
+		m1pf_next <= m1pf_reg;
+		m2pf_next <= m2pf_reg;
+		m3pf_next <= m3pf_reg;
+		m0pl_next <= m0pl_reg;
+		m1pl_next <= m1pl_reg;
+		m2pl_next <= m2pl_reg;
+		m3pl_next <= m3pl_reg;
+		
+		p0pf_next <= p0pf_reg;
+		p1pf_next <= p1pf_reg;
+		p2pf_next <= p2pf_reg;
+		p3pf_next <= p3pf_reg;
+		p0pl_next <= p0pl_reg;
+		p1pl_next <= p1pl_reg;
+		p2pl_next <= p2pl_reg;
+		p3pl_next <= p3pl_reg;	
+		
+		if (hitclr_write = '1') then
+			m0pf_next <= (others=>'0');
+			m1pf_next <= (others=>'0');
+			m2pf_next <= (others=>'0');
+			m3pf_next <= (others=>'0');
+			m0pl_next <= (others=>'0');
+			m1pl_next <= (others=>'0');
+			m2pl_next <= (others=>'0');
+			m3pl_next <= (others=>'0');
+			
+			p0pf_next <= (others=>'0');
+			p1pf_next <= (others=>'0');
+			p2pf_next <= (others=>'0');
+			p3pf_next <= (others=>'0');
+			p0pl_next <= (others=>'0');
+			p1pl_next <= (others=>'0');
+			p2pl_next <= (others=>'0');
+			p3pl_next <= (others=>'0');
+		else
+			if (visible_live = '1' and colour_clock = '1') then
+				m0pl_next <= m0pl_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m1pl_next <= m1pl_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m2pl_next <= m2pl_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m3pl_next <= m3pl_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+
+				m0pf_next <= m0pf_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m1pf_next <= m1pf_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m2pf_next <= m2pf_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m3pf_next <= m3pf_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				
+				p0pl_next <= p0pl_reg or (active_p0_live&active_p0_live&active_p0_live&'0'        and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p1pl_next <= p1pl_reg or (active_p1_live&active_p1_live&'0'       &active_p1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p2pl_next <= p2pl_reg or (active_p2_live&'0'       &active_p2_live&active_p2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p3pl_next <= p3pl_reg or ('0'       &active_p3_live&active_p3_live&active_p3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);	
+				
+				p0pf_next <= p0pf_reg or (active_p0_live&active_p0_live&active_p0_live&active_p0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p1pf_next <= p1pf_reg or (active_p1_live&active_p1_live&active_p1_live&active_p1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p2pf_next <= p2pf_reg or (active_p2_live&active_p2_live&active_p2_live&active_p2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p3pf_next <= p3pf_reg or (active_p3_live&active_p3_live&active_p3_live&active_p3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);			
+			end if;
+		end if;
+		
+	end process;
+
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,hposp0_raw_reg,hposp1_raw_reg,hposp2_raw_reg,hposp3_raw_reg,hposm0_raw_reg,hposm1_raw_reg,hposm2_raw_reg,hposm3_raw_reg,sizep0_raw_reg,sizep1_raw_reg,sizep2_raw_reg,sizep3_raw_reg,sizem_raw_reg,grafp0_reg,grafp1_reg,grafp2_reg,grafp3_reg, grafm_reg, colpm0_raw_reg, colpm1_raw_reg, colpm2_raw_reg, colpm3_raw_reg, colpf0_raw_reg, colpf1_raw_reg,colpf2_raw_reg, colpf3_raw_reg, colbk_raw_reg, prior_raw_reg, vdelay_reg, gractl_reg, consol_output_reg, grafm_dma_load, grafm_dma_next, grafp0_dma_load, grafp0_dma_next, grafp1_dma_load, grafp1_dma_next, grafp2_dma_load, grafp2_dma_next, grafp3_dma_load, grafp3_dma_next)
+	begin
+		hposp0_raw_next <= hposp0_raw_reg;
+		hposp1_raw_next <= hposp1_raw_reg;
+		hposp2_raw_next <= hposp2_raw_reg;
+		hposp3_raw_next <= hposp3_raw_reg;
+
+		hposm0_raw_next <= hposm0_raw_reg;
+		hposm1_raw_next <= hposm1_raw_reg;
+		hposm2_raw_next <= hposm2_raw_reg;
+		hposm3_raw_next <= hposm3_raw_reg;			
+
+		sizep0_raw_next <= sizep0_raw_reg;
+		sizep1_raw_next <= sizep1_raw_reg;
+		sizep2_raw_next <= sizep2_raw_reg;
+		sizep3_raw_next <= sizep3_raw_reg;
+
+		sizem_raw_next <= sizem_raw_reg;
+		
+		grafp0_next <= grafp0_reg;
+		grafp1_next <= grafp1_reg;
+		grafp2_next <= grafp2_reg;
+		grafp3_next <= grafp3_reg;
+
+		grafm_next <= grafm_reg;
+		
+		colpm0_raw_next <= colpm0_raw_reg;
+		colpm1_raw_next <= colpm1_raw_reg;
+		colpm2_raw_next <= colpm2_raw_reg;
+		colpm3_raw_next <= colpm3_raw_reg;
+
+		colpf0_raw_next <= colpf0_raw_reg;
+		colpf1_raw_next <= colpf1_raw_reg;
+		colpf2_raw_next <= colpf2_raw_reg;
+		colpf3_raw_next <= colpf3_raw_reg;
+		
+		colbk_raw_next <= colbk_raw_reg;
+		
+		prior_raw_next <= prior_raw_reg;
+		
+		vdelay_next <= vdelay_reg;
+		
+		gractl_next <= gractl_reg;
+		
+		consol_output_next <= consol_output_reg;	
+		
+		hitclr_write <= '0';
+		
+		if (grafm_dma_load = '1') then
+			grafm_next <= grafm_dma_next;
+		end if;
+
+		if (grafp0_dma_load = '1') then
+			grafp0_next <= grafp0_dma_next;
+		end if;
+
+		if (grafp1_dma_load = '1') then
+			grafp1_next <= grafp1_dma_next;
+		end if;
+
+		if (grafp2_dma_load = '1') then
+			grafp2_next <= grafp2_dma_next;
+		end if;
+
+		if (grafp3_dma_load = '1') then
+			grafp3_next <= grafp3_dma_next;
+		end if;
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				hposp0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				hposp1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(2) = '1') then
+				hposp2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				hposp3_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(4) = '1') then
+				hposm0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				hposm1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(6) = '1') then
+				hposm2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(7) = '1') then
+				hposm3_raw_next <= cpu_data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				sizep0_raw_next <= cpu_data_in(1 downto 0);
+			end if;	
+
+			if(addr_decoded(9) = '1') then
+				sizep1_raw_next <= cpu_data_in(1 downto 0);
+			end if;		
+			
+			if(addr_decoded(10) = '1') then
+				sizep2_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+
+			if(addr_decoded(11) = '1') then
+				sizep3_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+			
+			if(addr_decoded(12) = '1') then
+				sizem_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(13) = '1') then
+				grafp0_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(14) = '1') then
+				grafp1_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(15) = '1') then
+				grafp2_next <= cpu_data_in;
+			end if;			
+			
+			if(addr_decoded(16) = '1') then
+				grafp3_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(17) = '1') then
+				grafm_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(18) = '1') then
+				colpm0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(19) = '1') then
+				colpm1_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(20) = '1') then
+				colpm2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(21) = '1') then
+				colpm3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(22) = '1') then
+				colpf0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(23) = '1') then
+				colpf1_raw_next <= cpu_data_in(7 downto 1);
+			end if;									
+
+			if(addr_decoded(24) = '1') then
+				colpf2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(25) = '1') then
+				colpf3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(26) = '1') then
+				colbk_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(27) = '1') then
+				prior_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(28) = '1') then
+				vdelay_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(29) = '1') then
+				gractl_next <= cpu_data_in(2 downto 0);
+			end if;		
+			
+			if(addr_decoded(30) = '1') then
+				-- clear the collision regs
+				hitclr_write <= '1';
+			end if;
+
+			if(addr_decoded(31) = '1') then
+				consol_output_next <= cpu_data_in(3 downto 0);
+			end if;				
+			
+		end if;
+	end process;
+	
+	-- delays...
+		-- TODO - needs more attention ... 
+		-- The prior behaviour here in real hardware is all over the place...
+		-- THESE CAN TAKE MUCH LESS SPACE - only need to store per CPU cycle, not per colour clock original
+	prior_short_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>6)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(5 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(5 downto 0));
+
+	prior_long_delay : wide_delay_line
+		generic map (COUNT=>3, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(7 downto 6));
+
+	prior_longer_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed2_reg(7 downto 6));		
+		
+	colbk_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colbk_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colbk_delayed_reg(7 downto 1));	
+
+	colpm0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm0_delayed_reg(7 downto 1));		
+	colpm1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm1_delayed_reg(7 downto 1));		
+	colpm2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm2_delayed_reg(7 downto 1));		
+	colpm3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm3_delayed_reg(7 downto 1));		
+
+	colpf0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf0_delayed_reg(7 downto 1));		
+	colpf1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf1_delayed_reg(7 downto 1));		
+	colpf2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf2_delayed_reg(7 downto 1));		
+	colpf3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf3_delayed_reg(7 downto 1));				
+
+	hposp0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp0_delayed_reg(7 downto 0));		
+	hposp1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp1_delayed_reg(7 downto 0));		
+	hposp2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp2_delayed_reg(7 downto 0));		
+	hposp3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp3_delayed_reg(7 downto 0));				
+
+	hposm0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm0_delayed_reg(7 downto 0));		
+	hposm1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm1_delayed_reg(7 downto 0));		
+	hposm2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm2_delayed_reg(7 downto 0));		
+	hposm3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm3_delayed_reg(7 downto 0));				
+		
+	sizep0_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep0_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep0_delayed_reg(1 downto 0));		
+	sizep1_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep1_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep1_delayed_reg(1 downto 0));		
+	sizep2_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep2_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep2_delayed_reg(1 downto 0));		
+	sizep3_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep3_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep3_delayed_reg(1 downto 0));		
+	sizem_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizem_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizem_delayed_reg(7 downto 0));				
+		
+	-- joystick
+	process(trig0_reg, trig1_reg, trig2_reg, trig3_reg, trig0, trig1, trig2, trig3, gractl_reg)
+	begin	
+		trig0_next <= trig0;
+		trig1_next <= trig1;
+		trig2_next <= trig2;
+		trig3_next <= trig3;
+		
+		if (gractl_reg(2) = '1') then
+			trig0_next <= trig0_reg and trig0;
+			trig1_next <= trig1_reg and trig1;
+			trig2_next <= trig2_reg and trig2;
+			trig3_next <= trig3_reg and trig3;
+		end if;
+	end process;
+	
+	-- Read from registers		
+	process(addr_decoded, CONSOL_OPTION, CONSOL_SELECT, CONSOL_START, consol_output_reg, trig0_reg, trig1_reg, trig2_reg, trig3_reg, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg, pal)
+	begin
+		data_out <= X"0F";
+
+		if (addr_decoded(0) = '1') then
+			data_out <= "0000"&m0pf_reg;
+		end if;
+
+		if (addr_decoded(1) = '1') then
+			data_out <= "0000"&m1pf_reg;
+		end if;
+		
+		if (addr_decoded(2) = '1') then
+			data_out <= "0000"&m2pf_reg;
+		end if;
+
+		if (addr_decoded(3) = '1') then
+			data_out <= "0000"&m3pf_reg;
+		end if;
+
+		if (addr_decoded(4) = '1') then
+			data_out <= "0000"&p0pf_reg;
+		end if;
+
+		if (addr_decoded(5) = '1') then
+			data_out <= "0000"&p1pf_reg;
+		end if;
+		
+		if (addr_decoded(6) = '1') then
+			data_out <= "0000"&p2pf_reg;
+		end if;
+
+		if (addr_decoded(7) = '1') then
+			data_out <= "0000"&p3pf_reg;
+		end if;
+		
+		if (addr_decoded(8) = '1') then
+			data_out <= "0000"&m0pl_reg;
+		end if;
+
+		if (addr_decoded(9) = '1') then
+			data_out <= "0000"&m1pl_reg;
+		end if;
+		
+		if (addr_decoded(10) = '1') then
+			data_out <= "0000"&m2pl_reg;
+		end if;
+
+		if (addr_decoded(11) = '1') then
+			data_out <= "0000"&m3pl_reg;
+		end if;		
+
+		if (addr_decoded(12) = '1') then
+			data_out <= "0000"&p0pl_reg;
+		end if;
+
+		if (addr_decoded(13) = '1') then
+			data_out <= "0000"&p1pl_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then
+			data_out <= "0000"&p2pl_reg;
+		end if;
+
+		if (addr_decoded(15) = '1') then
+			data_out <= "0000"&p3pl_reg;
+		end if;		
+		
+		if (addr_decoded(16) = '1') then
+			data_out <= "0000000"&trig0_reg;
+		end if;
+
+		if (addr_decoded(17) = '1') then
+			data_out <= "0000000"&trig1_reg;
+		end if;
+
+		if (addr_decoded(18) = '1') then
+			data_out <= "0000000"&trig2_reg;
+		end if;
+		
+		if (addr_decoded(19) = '1') then
+			data_out <= "0000000"&trig3_reg;
+		end if;
+		
+		if (addr_decoded(20) = '1') then
+			data_out <= "0000"&not(pal&pal&pal)&'1';
+		end if;
+
+		if (addr_decoded(31) = '1') then
+			data_out <= "0000"&('0'&not(CONSOL_OPTION)&not(CONSOL_SELECT)&not(CONSOL_START) and (not consol_output_reg));
+		end if;
+		
+	end process;
+	
+	-- output	
+	colour_out <= colour_reg;
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+	blank<=hblank_reg or vsync_reg;
+	
+	sound <= consol_output_reg(3);
+
+end vhdl;
+
+
Index: common/a8core/gtia_palette.vhdl
===================================================================
--- common/a8core/gtia_palette.vhdl	(nonexistent)
+++ common/a8core/gtia_palette.vhdl	(revision 1)
@@ -0,0 +1,2096 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_palette IS
+PORT 
+( 
+	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+);
+END gtia_palette;
+
+ARCHITECTURE altirra OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+				when X"00" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"01" =>
+					R_next <= X"11";
+					G_next <= X"11";
+					B_next <= X"11";
+				when X"02" =>
+					R_next <= X"22";
+					G_next <= X"22";
+					B_next <= X"22";
+				when X"03" =>
+					R_next <= X"33";
+					G_next <= X"33";
+					B_next <= X"33";
+				when X"04" =>
+					R_next <= X"44";
+					G_next <= X"44";
+					B_next <= X"44";
+				when X"05" =>
+					R_next <= X"55";
+					G_next <= X"55";
+					B_next <= X"55";
+				when X"06" =>
+					R_next <= X"66";
+					G_next <= X"66";
+					B_next <= X"66";
+				when X"07" =>
+					R_next <= X"77";
+					G_next <= X"77";
+					B_next <= X"77";
+				when X"08" =>
+					R_next <= X"88";
+					G_next <= X"88";
+					B_next <= X"88";
+				when X"09" =>
+					R_next <= X"99";
+					G_next <= X"99";
+					B_next <= X"99";
+				when X"0a" =>
+					R_next <= X"aa";
+					G_next <= X"aa";
+					B_next <= X"aa";
+				when X"0b" =>
+					R_next <= X"bb";
+					G_next <= X"bb";
+					B_next <= X"bb";
+				when X"0c" =>
+					R_next <= X"cc";
+					G_next <= X"cc";
+					B_next <= X"cc";
+				when X"0d" =>
+					R_next <= X"dd";
+					G_next <= X"dd";
+					B_next <= X"dd";
+				when X"0e" =>
+					R_next <= X"ee";
+					G_next <= X"ee";
+					B_next <= X"ee";
+				when X"0f" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"10" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"11" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"12" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"13" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"14" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"15" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"16" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"17" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"18" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"19" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"1a" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"1b" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"1c" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"1d" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"1e" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"1f" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+				when X"20" =>
+					R_next <= X"50";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"21" =>
+					R_next <= X"61";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"22" =>
+					R_next <= X"72";
+					G_next <= X"03";
+					B_next <= X"00";
+				when X"23" =>
+					R_next <= X"83";
+					G_next <= X"14";
+					B_next <= X"03";
+				when X"24" =>
+					R_next <= X"94";
+					G_next <= X"25";
+					B_next <= X"14";
+				when X"25" =>
+					R_next <= X"a5";
+					G_next <= X"36";
+					B_next <= X"25";
+				when X"26" =>
+					R_next <= X"b6";
+					G_next <= X"47";
+					B_next <= X"36";
+				when X"27" =>
+					R_next <= X"c7";
+					G_next <= X"58";
+					B_next <= X"47";
+				when X"28" =>
+					R_next <= X"d8";
+					G_next <= X"69";
+					B_next <= X"58";
+				when X"29" =>
+					R_next <= X"e9";
+					G_next <= X"7a";
+					B_next <= X"69";
+				when X"2a" =>
+					R_next <= X"fa";
+					G_next <= X"8b";
+					B_next <= X"7a";
+				when X"2b" =>
+					R_next <= X"ff";
+					G_next <= X"9c";
+					B_next <= X"8b";
+				when X"2c" =>
+					R_next <= X"ff";
+					G_next <= X"ad";
+					B_next <= X"9c";
+				when X"2d" =>
+					R_next <= X"ff";
+					G_next <= X"be";
+					B_next <= X"ad";
+				when X"2e" =>
+					R_next <= X"ff";
+					G_next <= X"cf";
+					B_next <= X"be";
+				when X"2f" =>
+					R_next <= X"ff";
+					G_next <= X"e0";
+					B_next <= X"cf";
+				when X"30" =>
+					R_next <= X"54";
+					G_next <= X"00";
+					B_next <= X"03";
+				when X"31" =>
+					R_next <= X"65";
+					G_next <= X"00";
+					B_next <= X"14";
+				when X"32" =>
+					R_next <= X"76";
+					G_next <= X"00";
+					B_next <= X"25";
+				when X"33" =>
+					R_next <= X"87";
+					G_next <= X"08";
+					B_next <= X"36";
+				when X"34" =>
+					R_next <= X"98";
+					G_next <= X"19";
+					B_next <= X"47";
+				when X"35" =>
+					R_next <= X"a9";
+					G_next <= X"2a";
+					B_next <= X"58";
+				when X"36" =>
+					R_next <= X"ba";
+					G_next <= X"3b";
+					B_next <= X"69";
+				when X"37" =>
+					R_next <= X"cb";
+					G_next <= X"4c";
+					B_next <= X"7a";
+				when X"38" =>
+					R_next <= X"dc";
+					G_next <= X"5d";
+					B_next <= X"8b";
+				when X"39" =>
+					R_next <= X"ed";
+					G_next <= X"6e";
+					B_next <= X"9c";
+				when X"3a" =>
+					R_next <= X"fe";
+					G_next <= X"7f";
+					B_next <= X"ad";
+				when X"3b" =>
+					R_next <= X"ff";
+					G_next <= X"90";
+					B_next <= X"be";
+				when X"3c" =>
+					R_next <= X"ff";
+					G_next <= X"a1";
+					B_next <= X"cf";
+				when X"3d" =>
+					R_next <= X"ff";
+					G_next <= X"b2";
+					B_next <= X"e0";
+				when X"3e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"f1";
+				when X"3f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"40" =>
+					R_next <= X"4f";
+					G_next <= X"00";
+					B_next <= X"35";
+				when X"41" =>
+					R_next <= X"60";
+					G_next <= X"00";
+					B_next <= X"46";
+				when X"42" =>
+					R_next <= X"71";
+					G_next <= X"00";
+					B_next <= X"57";
+				when X"43" =>
+					R_next <= X"82";
+					G_next <= X"01";
+					B_next <= X"68";
+				when X"44" =>
+					R_next <= X"93";
+					G_next <= X"12";
+					B_next <= X"79";
+				when X"45" =>
+					R_next <= X"a4";
+					G_next <= X"23";
+					B_next <= X"8a";
+				when X"46" =>
+					R_next <= X"b5";
+					G_next <= X"34";
+					B_next <= X"9b";
+				when X"47" =>
+					R_next <= X"c6";
+					G_next <= X"45";
+					B_next <= X"ac";
+				when X"48" =>
+					R_next <= X"d7";
+					G_next <= X"56";
+					B_next <= X"bd";
+				when X"49" =>
+					R_next <= X"e8";
+					G_next <= X"67";
+					B_next <= X"ce";
+				when X"4a" =>
+					R_next <= X"f9";
+					G_next <= X"78";
+					B_next <= X"df";
+				when X"4b" =>
+					R_next <= X"ff";
+					G_next <= X"89";
+					B_next <= X"f0";
+				when X"4c" =>
+					R_next <= X"ff";
+					G_next <= X"9a";
+					B_next <= X"ff";
+				when X"4d" =>
+					R_next <= X"ff";
+					G_next <= X"ab";
+					B_next <= X"ff";
+				when X"4e" =>
+					R_next <= X"ff";
+					G_next <= X"bc";
+					B_next <= X"ff";
+				when X"4f" =>
+					R_next <= X"ff";
+					G_next <= X"cd";
+					B_next <= X"ff";
+				when X"50" =>
+					R_next <= X"3d";
+					G_next <= X"00";
+					B_next <= X"68";
+				when X"51" =>
+					R_next <= X"4e";
+					G_next <= X"00";
+					B_next <= X"79";
+				when X"52" =>
+					R_next <= X"5f";
+					G_next <= X"00";
+					B_next <= X"8a";
+				when X"53" =>
+					R_next <= X"70";
+					G_next <= X"00";
+					B_next <= X"9b";
+				when X"54" =>
+					R_next <= X"81";
+					G_next <= X"11";
+					B_next <= X"ac";
+				when X"55" =>
+					R_next <= X"92";
+					G_next <= X"22";
+					B_next <= X"bd";
+				when X"56" =>
+					R_next <= X"a3";
+					G_next <= X"33";
+					B_next <= X"ce";
+				when X"57" =>
+					R_next <= X"b4";
+					G_next <= X"44";
+					B_next <= X"df";
+				when X"58" =>
+					R_next <= X"c5";
+					G_next <= X"55";
+					B_next <= X"f0";
+				when X"59" =>
+					R_next <= X"d6";
+					G_next <= X"66";
+					B_next <= X"ff";
+				when X"5a" =>
+					R_next <= X"e7";
+					G_next <= X"77";
+					B_next <= X"ff";
+				when X"5b" =>
+					R_next <= X"f8";
+					G_next <= X"88";
+					B_next <= X"ff";
+				when X"5c" =>
+					R_next <= X"ff";
+					G_next <= X"99";
+					B_next <= X"ff";
+				when X"5d" =>
+					R_next <= X"ff";
+					G_next <= X"aa";
+					B_next <= X"ff";
+				when X"5e" =>
+					R_next <= X"ff";
+					G_next <= X"bb";
+					B_next <= X"ff";
+				when X"5f" =>
+					R_next <= X"ff";
+					G_next <= X"cc";
+					B_next <= X"ff";
+				when X"60" =>
+					R_next <= X"20";
+					G_next <= X"00";
+					B_next <= X"8b";
+				when X"61" =>
+					R_next <= X"31";
+					G_next <= X"00";
+					B_next <= X"9c";
+				when X"62" =>
+					R_next <= X"42";
+					G_next <= X"00";
+					B_next <= X"ad";
+				when X"63" =>
+					R_next <= X"53";
+					G_next <= X"08";
+					B_next <= X"be";
+				when X"64" =>
+					R_next <= X"64";
+					G_next <= X"19";
+					B_next <= X"cf";
+				when X"65" =>
+					R_next <= X"75";
+					G_next <= X"2a";
+					B_next <= X"e0";
+				when X"66" =>
+					R_next <= X"86";
+					G_next <= X"3b";
+					B_next <= X"f1";
+				when X"67" =>
+					R_next <= X"97";
+					G_next <= X"4c";
+					B_next <= X"ff";
+				when X"68" =>
+					R_next <= X"a8";
+					G_next <= X"5d";
+					B_next <= X"ff";
+				when X"69" =>
+					R_next <= X"b9";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"6a" =>
+					R_next <= X"ca";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"6b" =>
+					R_next <= X"db";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"6c" =>
+					R_next <= X"ec";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"6d" =>
+					R_next <= X"fd";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"6e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"6f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"70" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"89";
+				when X"71" =>
+					R_next <= X"00";
+					G_next <= X"08";
+					B_next <= X"9a";
+				when X"72" =>
+					R_next <= X"00";
+					G_next <= X"19";
+					B_next <= X"ab";
+				when X"73" =>
+					R_next <= X"10";
+					G_next <= X"2a";
+					B_next <= X"bc";
+				when X"74" =>
+					R_next <= X"21";
+					G_next <= X"3b";
+					B_next <= X"cd";
+				when X"75" =>
+					R_next <= X"32";
+					G_next <= X"4c";
+					B_next <= X"de";
+				when X"76" =>
+					R_next <= X"43";
+					G_next <= X"5d";
+					B_next <= X"ef";
+				when X"77" =>
+					R_next <= X"54";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"78" =>
+					R_next <= X"65";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"79" =>
+					R_next <= X"76";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"7a" =>
+					R_next <= X"87";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"7b" =>
+					R_next <= X"98";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"7c" =>
+					R_next <= X"a9";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"7d" =>
+					R_next <= X"ba";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"7e" =>
+					R_next <= X"cb";
+					G_next <= X"e5";
+					B_next <= X"ff";
+				when X"7f" =>
+					R_next <= X"dc";
+					G_next <= X"f6";
+					B_next <= X"ff";
+				when X"80" =>
+					R_next <= X"00";
+					G_next <= X"0c";
+					B_next <= X"65";
+				when X"81" =>
+					R_next <= X"00";
+					G_next <= X"1d";
+					B_next <= X"76";
+				when X"82" =>
+					R_next <= X"00";
+					G_next <= X"2e";
+					B_next <= X"87";
+				when X"83" =>
+					R_next <= X"00";
+					G_next <= X"3f";
+					B_next <= X"98";
+				when X"84" =>
+					R_next <= X"05";
+					G_next <= X"50";
+					B_next <= X"a9";
+				when X"85" =>
+					R_next <= X"16";
+					G_next <= X"61";
+					B_next <= X"ba";
+				when X"86" =>
+					R_next <= X"27";
+					G_next <= X"72";
+					B_next <= X"cb";
+				when X"87" =>
+					R_next <= X"38";
+					G_next <= X"83";
+					B_next <= X"dc";
+				when X"88" =>
+					R_next <= X"49";
+					G_next <= X"94";
+					B_next <= X"ed";
+				when X"89" =>
+					R_next <= X"5a";
+					G_next <= X"a5";
+					B_next <= X"fe";
+				when X"8a" =>
+					R_next <= X"6b";
+					G_next <= X"b6";
+					B_next <= X"ff";
+				when X"8b" =>
+					R_next <= X"7c";
+					G_next <= X"c7";
+					B_next <= X"ff";
+				when X"8c" =>
+					R_next <= X"8d";
+					G_next <= X"d8";
+					B_next <= X"ff";
+				when X"8d" =>
+					R_next <= X"9e";
+					G_next <= X"e9";
+					B_next <= X"ff";
+				when X"8e" =>
+					R_next <= X"af";
+					G_next <= X"fa";
+					B_next <= X"ff";
+				when X"8f" =>
+					R_next <= X"c0";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"90" =>
+					R_next <= X"00";
+					G_next <= X"1f";
+					B_next <= X"30";
+				when X"91" =>
+					R_next <= X"00";
+					G_next <= X"30";
+					B_next <= X"41";
+				when X"92" =>
+					R_next <= X"00";
+					G_next <= X"41";
+					B_next <= X"52";
+				when X"93" =>
+					R_next <= X"00";
+					G_next <= X"52";
+					B_next <= X"63";
+				when X"94" =>
+					R_next <= X"00";
+					G_next <= X"63";
+					B_next <= X"74";
+				when X"95" =>
+					R_next <= X"05";
+					G_next <= X"74";
+					B_next <= X"85";
+				when X"96" =>
+					R_next <= X"16";
+					G_next <= X"85";
+					B_next <= X"96";
+				when X"97" =>
+					R_next <= X"27";
+					G_next <= X"96";
+					B_next <= X"a7";
+				when X"98" =>
+					R_next <= X"38";
+					G_next <= X"a7";
+					B_next <= X"b8";
+				when X"99" =>
+					R_next <= X"49";
+					G_next <= X"b8";
+					B_next <= X"c9";
+				when X"9a" =>
+					R_next <= X"5a";
+					G_next <= X"c9";
+					B_next <= X"da";
+				when X"9b" =>
+					R_next <= X"6b";
+					G_next <= X"da";
+					B_next <= X"eb";
+				when X"9c" =>
+					R_next <= X"7c";
+					G_next <= X"eb";
+					B_next <= X"fc";
+				when X"9d" =>
+					R_next <= X"8d";
+					G_next <= X"fc";
+					B_next <= X"ff";
+				when X"9e" =>
+					R_next <= X"9e";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"9f" =>
+					R_next <= X"af";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"a0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"a1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"0e";
+				when X"a2" =>
+					R_next <= X"00";
+					G_next <= X"4d";
+					B_next <= X"1f";
+				when X"a3" =>
+					R_next <= X"00";
+					G_next <= X"5e";
+					B_next <= X"30";
+				when X"a4" =>
+					R_next <= X"00";
+					G_next <= X"6f";
+					B_next <= X"41";
+				when X"a5" =>
+					R_next <= X"01";
+					G_next <= X"80";
+					B_next <= X"52";
+				when X"a6" =>
+					R_next <= X"12";
+					G_next <= X"91";
+					B_next <= X"63";
+				when X"a7" =>
+					R_next <= X"23";
+					G_next <= X"a2";
+					B_next <= X"74";
+				when X"a8" =>
+					R_next <= X"34";
+					G_next <= X"b3";
+					B_next <= X"85";
+				when X"a9" =>
+					R_next <= X"45";
+					G_next <= X"c4";
+					B_next <= X"96";
+				when X"aa" =>
+					R_next <= X"56";
+					G_next <= X"d5";
+					B_next <= X"a7";
+				when X"ab" =>
+					R_next <= X"67";
+					G_next <= X"e6";
+					B_next <= X"b8";
+				when X"ac" =>
+					R_next <= X"78";
+					G_next <= X"f7";
+					B_next <= X"c9";
+				when X"ad" =>
+					R_next <= X"89";
+					G_next <= X"ff";
+					B_next <= X"da";
+				when X"ae" =>
+					R_next <= X"9a";
+					G_next <= X"ff";
+					B_next <= X"eb";
+				when X"af" =>
+					R_next <= X"ab";
+					G_next <= X"ff";
+					B_next <= X"fc";
+				when X"b0" =>
+					R_next <= X"00";
+					G_next <= X"33";
+					B_next <= X"00";
+				when X"b1" =>
+					R_next <= X"00";
+					G_next <= X"44";
+					B_next <= X"00";
+				when X"b2" =>
+					R_next <= X"00";
+					G_next <= X"55";
+					B_next <= X"00";
+				when X"b3" =>
+					R_next <= X"00";
+					G_next <= X"66";
+					B_next <= X"00";
+				when X"b4" =>
+					R_next <= X"07";
+					G_next <= X"77";
+					B_next <= X"00";
+				when X"b5" =>
+					R_next <= X"18";
+					G_next <= X"88";
+					B_next <= X"00";
+				when X"b6" =>
+					R_next <= X"29";
+					G_next <= X"99";
+					B_next <= X"00";
+				when X"b7" =>
+					R_next <= X"3a";
+					G_next <= X"aa";
+					B_next <= X"0f";
+				when X"b8" =>
+					R_next <= X"4b";
+					G_next <= X"bb";
+					B_next <= X"20";
+				when X"b9" =>
+					R_next <= X"5c";
+					G_next <= X"cc";
+					B_next <= X"31";
+				when X"ba" =>
+					R_next <= X"6d";
+					G_next <= X"dd";
+					B_next <= X"42";
+				when X"bb" =>
+					R_next <= X"7e";
+					G_next <= X"ee";
+					B_next <= X"53";
+				when X"bc" =>
+					R_next <= X"8f";
+					G_next <= X"ff";
+					B_next <= X"64";
+				when X"bd" =>
+					R_next <= X"a0";
+					G_next <= X"ff";
+					B_next <= X"75";
+				when X"be" =>
+					R_next <= X"b1";
+					G_next <= X"ff";
+					B_next <= X"86";
+				when X"bf" =>
+					R_next <= X"c2";
+					G_next <= X"ff";
+					B_next <= X"97";
+				when X"c0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"c1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"c2" =>
+					R_next <= X"02";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"c3" =>
+					R_next <= X"13";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"c4" =>
+					R_next <= X"24";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"c5" =>
+					R_next <= X"35";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"c6" =>
+					R_next <= X"46";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"c7" =>
+					R_next <= X"57";
+					G_next <= X"a2";
+					B_next <= X"00";
+				when X"c8" =>
+					R_next <= X"68";
+					G_next <= X"b3";
+					B_next <= X"00";
+				when X"c9" =>
+					R_next <= X"79";
+					G_next <= X"c4";
+					B_next <= X"0e";
+				when X"ca" =>
+					R_next <= X"8a";
+					G_next <= X"d5";
+					B_next <= X"1f";
+				when X"cb" =>
+					R_next <= X"9b";
+					G_next <= X"e6";
+					B_next <= X"30";
+				when X"cc" =>
+					R_next <= X"ac";
+					G_next <= X"f7";
+					B_next <= X"41";
+				when X"cd" =>
+					R_next <= X"bd";
+					G_next <= X"ff";
+					B_next <= X"52";
+				when X"ce" =>
+					R_next <= X"ce";
+					G_next <= X"ff";
+					B_next <= X"63";
+				when X"cf" =>
+					R_next <= X"df";
+					G_next <= X"ff";
+					B_next <= X"74";
+				when X"d0" =>
+					R_next <= X"01";
+					G_next <= X"1c";
+					B_next <= X"00";
+				when X"d1" =>
+					R_next <= X"12";
+					G_next <= X"2d";
+					B_next <= X"00";
+				when X"d2" =>
+					R_next <= X"23";
+					G_next <= X"3e";
+					B_next <= X"00";
+				when X"d3" =>
+					R_next <= X"34";
+					G_next <= X"4f";
+					B_next <= X"00";
+				when X"d4" =>
+					R_next <= X"45";
+					G_next <= X"60";
+					B_next <= X"00";
+				when X"d5" =>
+					R_next <= X"56";
+					G_next <= X"71";
+					B_next <= X"00";
+				when X"d6" =>
+					R_next <= X"67";
+					G_next <= X"82";
+					B_next <= X"00";
+				when X"d7" =>
+					R_next <= X"78";
+					G_next <= X"93";
+					B_next <= X"00";
+				when X"d8" =>
+					R_next <= X"89";
+					G_next <= X"a4";
+					B_next <= X"00";
+				when X"d9" =>
+					R_next <= X"9a";
+					G_next <= X"b5";
+					B_next <= X"03";
+				when X"da" =>
+					R_next <= X"ab";
+					G_next <= X"c6";
+					B_next <= X"14";
+				when X"db" =>
+					R_next <= X"bc";
+					G_next <= X"d7";
+					B_next <= X"25";
+				when X"dc" =>
+					R_next <= X"cd";
+					G_next <= X"e8";
+					B_next <= X"36";
+				when X"dd" =>
+					R_next <= X"de";
+					G_next <= X"f9";
+					B_next <= X"47";
+				when X"de" =>
+					R_next <= X"ef";
+					G_next <= X"ff";
+					B_next <= X"58";
+				when X"df" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"69";
+				when X"e0" =>
+					R_next <= X"23";
+					G_next <= X"09";
+					B_next <= X"00";
+				when X"e1" =>
+					R_next <= X"34";
+					G_next <= X"1a";
+					B_next <= X"00";
+				when X"e2" =>
+					R_next <= X"45";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"e3" =>
+					R_next <= X"56";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"e4" =>
+					R_next <= X"67";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"e5" =>
+					R_next <= X"78";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"e6" =>
+					R_next <= X"89";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"e7" =>
+					R_next <= X"9a";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"e8" =>
+					R_next <= X"ab";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"e9" =>
+					R_next <= X"bc";
+					G_next <= X"a2";
+					B_next <= X"10";
+				when X"ea" =>
+					R_next <= X"cd";
+					G_next <= X"b3";
+					B_next <= X"21";
+				when X"eb" =>
+					R_next <= X"de";
+					G_next <= X"c4";
+					B_next <= X"32";
+				when X"ec" =>
+					R_next <= X"ef";
+					G_next <= X"d5";
+					B_next <= X"43";
+				when X"ed" =>
+					R_next <= X"ff";
+					G_next <= X"e6";
+					B_next <= X"54";
+				when X"ee" =>
+					R_next <= X"ff";
+					G_next <= X"f7";
+					B_next <= X"65";
+				when X"ef" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"76";
+				when X"f0" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"f1" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"f2" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"f3" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"f4" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"f5" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"f6" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"f7" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"f8" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"f9" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"fa" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"fb" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"fc" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"fd" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"fe" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"ff" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+				when others =>
+					-- nop
+			end case;
+			
+		end process;
+		
+end altirra;
+
+
+ARCHITECTURE laoo OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+					when X"00" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"01" =>
+						R_next <= X"0e";
+						G_next <= X"0d";
+						B_next <= X"0e";
+					when X"02" =>
+						R_next <= X"1d";
+						G_next <= X"1d";
+						B_next <= X"1d";
+					when X"03" =>
+						R_next <= X"2e";
+						G_next <= X"2d";
+						B_next <= X"2e";
+					when X"04" =>
+						R_next <= X"3e";
+						G_next <= X"3d";
+						B_next <= X"3e";
+					when X"05" =>
+						R_next <= X"4f";
+						G_next <= X"4e";
+						B_next <= X"4f";
+					when X"06" =>
+						R_next <= X"5f";
+						G_next <= X"5e";
+						B_next <= X"5f";
+					when X"07" =>
+						R_next <= X"70";
+						G_next <= X"6f";
+						B_next <= X"6f";
+					when X"08" =>
+						R_next <= X"7a";
+						G_next <= X"7a";
+						B_next <= X"79";
+					when X"09" =>
+						R_next <= X"8b";
+						G_next <= X"8a";
+						B_next <= X"8b";
+					when X"0a" =>
+						R_next <= X"9c";
+						G_next <= X"9b";
+						B_next <= X"9b";
+					when X"0b" =>
+						R_next <= X"ad";
+						G_next <= X"ac";
+						B_next <= X"ac";
+					when X"0c" =>
+						R_next <= X"bc";
+						G_next <= X"bb";
+						B_next <= X"bb";
+					when X"0d" =>
+						R_next <= X"cd";
+						G_next <= X"cc";
+						B_next <= X"cd";
+					when X"0e" =>
+						R_next <= X"dc";
+						G_next <= X"db";
+						B_next <= X"dc";
+					when X"0f" =>
+						R_next <= X"ec";
+						G_next <= X"ec";
+						B_next <= X"ec";
+					when X"10" =>
+						R_next <= X"35";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"11" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"12" =>
+						R_next <= X"4f";
+						G_next <= X"14";
+						B_next <= X"00";
+					when X"13" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"14" =>
+						R_next <= X"6e";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"15" =>
+						R_next <= X"7f";
+						G_next <= X"45";
+						B_next <= X"03";
+					when X"16" =>
+						R_next <= X"8e";
+						G_next <= X"55";
+						B_next <= X"13";
+					when X"17" =>
+						R_next <= X"9f";
+						G_next <= X"66";
+						B_next <= X"23";
+					when X"18" =>
+						R_next <= X"a9";
+						G_next <= X"71";
+						B_next <= X"2d";
+					when X"19" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"1a" =>
+						R_next <= X"ca";
+						G_next <= X"92";
+						B_next <= X"50";
+					when X"1b" =>
+						R_next <= X"db";
+						G_next <= X"a3";
+						B_next <= X"61";
+					when X"1c" =>
+						R_next <= X"ea";
+						G_next <= X"b2";
+						B_next <= X"70";
+					when X"1d" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"1e" =>
+						R_next <= X"fe";
+						G_next <= X"d2";
+						B_next <= X"91";
+					when X"1f" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+					when X"20" =>
+						R_next <= X"3f";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"21" =>
+						R_next <= X"4b";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"22" =>
+						R_next <= X"59";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"23" =>
+						R_next <= X"69";
+						G_next <= X"19";
+						B_next <= X"03";
+					when X"24" =>
+						R_next <= X"78";
+						G_next <= X"29";
+						B_next <= X"12";
+					when X"25" =>
+						R_next <= X"88";
+						G_next <= X"3a";
+						B_next <= X"23";
+					when X"26" =>
+						R_next <= X"98";
+						G_next <= X"4a";
+						B_next <= X"34";
+					when X"27" =>
+						R_next <= X"a9";
+						G_next <= X"5b";
+						B_next <= X"45";
+					when X"28" =>
+						R_next <= X"b3";
+						G_next <= X"65";
+						B_next <= X"4f";
+					when X"29" =>
+						R_next <= X"c4";
+						G_next <= X"76";
+						B_next <= X"61";
+					when X"2a" =>
+						R_next <= X"d4";
+						G_next <= X"87";
+						B_next <= X"72";
+					when X"2b" =>
+						R_next <= X"e5";
+						G_next <= X"98";
+						B_next <= X"83";
+					when X"2c" =>
+						R_next <= X"f4";
+						G_next <= X"a7";
+						B_next <= X"92";
+					when X"2d" =>
+						R_next <= X"fd";
+						G_next <= X"b8";
+						B_next <= X"a3";
+					when X"2e" =>
+						R_next <= X"ff";
+						G_next <= X"c7";
+						B_next <= X"b3";
+					when X"2f" =>
+						R_next <= X"ff";
+						G_next <= X"d7";
+						B_next <= X"c2";
+					when X"30" =>
+						R_next <= X"3d";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"31" =>
+						R_next <= X"49";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"32" =>
+						R_next <= X"57";
+						G_next <= X"05";
+						B_next <= X"0b";
+					when X"33" =>
+						R_next <= X"68";
+						G_next <= X"15";
+						B_next <= X"1b";
+					when X"34" =>
+						R_next <= X"77";
+						G_next <= X"25";
+						B_next <= X"2a";
+					when X"35" =>
+						R_next <= X"88";
+						G_next <= X"36";
+						B_next <= X"3c";
+					when X"36" =>
+						R_next <= X"98";
+						G_next <= X"46";
+						B_next <= X"4c";
+					when X"37" =>
+						R_next <= X"a8";
+						G_next <= X"57";
+						B_next <= X"5d";
+					when X"38" =>
+						R_next <= X"b2";
+						G_next <= X"61";
+						B_next <= X"67";
+					when X"39" =>
+						R_next <= X"c3";
+						G_next <= X"72";
+						B_next <= X"79";
+					when X"3a" =>
+						R_next <= X"d3";
+						G_next <= X"83";
+						B_next <= X"89";
+					when X"3b" =>
+						R_next <= X"e4";
+						G_next <= X"94";
+						B_next <= X"9a";
+					when X"3c" =>
+						R_next <= X"f3";
+						G_next <= X"a3";
+						B_next <= X"a9";
+					when X"3d" =>
+						R_next <= X"fd";
+						G_next <= X"b4";
+						B_next <= X"ba";
+					when X"3e" =>
+						R_next <= X"ff";
+						G_next <= X"c4";
+						B_next <= X"ca";
+					when X"3f" =>
+						R_next <= X"ff";
+						G_next <= X"d4";
+						B_next <= X"d9";
+					when X"40" =>
+						R_next <= X"38";
+						G_next <= X"00";
+						B_next <= X"27";
+					when X"41" =>
+						R_next <= X"42";
+						G_next <= X"00";
+						B_next <= X"32";
+					when X"42" =>
+						R_next <= X"51";
+						G_next <= X"01";
+						B_next <= X"40";
+					when X"43" =>
+						R_next <= X"61";
+						G_next <= X"0e";
+						B_next <= X"50";
+					when X"44" =>
+						R_next <= X"70";
+						G_next <= X"1e";
+						B_next <= X"5f";
+					when X"45" =>
+						R_next <= X"81";
+						G_next <= X"2f";
+						B_next <= X"70";
+					when X"46" =>
+						R_next <= X"90";
+						G_next <= X"3f";
+						B_next <= X"81";
+					when X"47" =>
+						R_next <= X"a0";
+						G_next <= X"51";
+						B_next <= X"90";
+					when X"48" =>
+						R_next <= X"ab";
+						G_next <= X"5b";
+						B_next <= X"9a";
+					when X"49" =>
+						R_next <= X"bc";
+						G_next <= X"6c";
+						B_next <= X"ac";
+					when X"4a" =>
+						R_next <= X"cc";
+						G_next <= X"7c";
+						B_next <= X"bc";
+					when X"4b" =>
+						R_next <= X"dc";
+						G_next <= X"8d";
+						B_next <= X"cd";
+					when X"4c" =>
+						R_next <= X"ec";
+						G_next <= X"9d";
+						B_next <= X"dc";
+					when X"4d" =>
+						R_next <= X"fa";
+						G_next <= X"ae";
+						B_next <= X"ed";
+					when X"4e" =>
+						R_next <= X"fe";
+						G_next <= X"bd";
+						B_next <= X"fa";
+					when X"4f" =>
+						R_next <= X"ff";
+						G_next <= X"cd";
+						B_next <= X"fe";
+					when X"50" =>
+						R_next <= X"2c";
+						G_next <= X"00";
+						B_next <= X"46";
+					when X"51" =>
+						R_next <= X"37";
+						G_next <= X"00";
+						B_next <= X"50";
+					when X"52" =>
+						R_next <= X"46";
+						G_next <= X"01";
+						B_next <= X"5f";
+					when X"53" =>
+						R_next <= X"55";
+						G_next <= X"0e";
+						B_next <= X"6e";
+					when X"54" =>
+						R_next <= X"65";
+						G_next <= X"1e";
+						B_next <= X"7d";
+					when X"55" =>
+						R_next <= X"75";
+						G_next <= X"2f";
+						B_next <= X"8e";
+					when X"56" =>
+						R_next <= X"85";
+						G_next <= X"3f";
+						B_next <= X"9f";
+					when X"57" =>
+						R_next <= X"95";
+						G_next <= X"50";
+						B_next <= X"ae";
+					when X"58" =>
+						R_next <= X"a0";
+						G_next <= X"5b";
+						B_next <= X"b8";
+					when X"59" =>
+						R_next <= X"b1";
+						G_next <= X"6c";
+						B_next <= X"ca";
+					when X"5a" =>
+						R_next <= X"c1";
+						G_next <= X"7c";
+						B_next <= X"da";
+					when X"5b" =>
+						R_next <= X"d2";
+						G_next <= X"8d";
+						B_next <= X"eb";
+					when X"5c" =>
+						R_next <= X"e1";
+						G_next <= X"9d";
+						B_next <= X"f8";
+					when X"5d" =>
+						R_next <= X"f2";
+						G_next <= X"ae";
+						B_next <= X"fe";
+					when X"5e" =>
+						R_next <= X"fc";
+						G_next <= X"bd";
+						B_next <= X"ff";
+					when X"5f" =>
+						R_next <= X"fe";
+						G_next <= X"cd";
+						B_next <= X"ff";
+					when X"60" =>
+						R_next <= X"19";
+						G_next <= X"00";
+						B_next <= X"5e";
+					when X"61" =>
+						R_next <= X"24";
+						G_next <= X"00";
+						B_next <= X"67";
+					when X"62" =>
+						R_next <= X"34";
+						G_next <= X"03";
+						B_next <= X"76";
+					when X"63" =>
+						R_next <= X"44";
+						G_next <= X"13";
+						B_next <= X"85";
+					when X"64" =>
+						R_next <= X"53";
+						G_next <= X"22";
+						B_next <= X"94";
+					when X"65" =>
+						R_next <= X"64";
+						G_next <= X"33";
+						B_next <= X"a5";
+					when X"66" =>
+						R_next <= X"74";
+						G_next <= X"43";
+						B_next <= X"b5";
+					when X"67" =>
+						R_next <= X"85";
+						G_next <= X"55";
+						B_next <= X"c4";
+					when X"68" =>
+						R_next <= X"8f";
+						G_next <= X"5f";
+						B_next <= X"ce";
+					when X"69" =>
+						R_next <= X"a0";
+						G_next <= X"70";
+						B_next <= X"e0";
+					when X"6a" =>
+						R_next <= X"b0";
+						G_next <= X"81";
+						B_next <= X"f0";
+					when X"6b" =>
+						R_next <= X"c1";
+						G_next <= X"92";
+						B_next <= X"fc";
+					when X"6c" =>
+						R_next <= X"d0";
+						G_next <= X"a1";
+						B_next <= X"fe";
+					when X"6d" =>
+						R_next <= X"e1";
+						G_next <= X"b2";
+						B_next <= X"ff";
+					when X"6e" =>
+						R_next <= X"f0";
+						G_next <= X"c2";
+						B_next <= X"ff";
+					when X"6f" =>
+						R_next <= X"fc";
+						G_next <= X"d2";
+						B_next <= X"ff";
+					when X"70" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"5c";
+					when X"71" =>
+						R_next <= X"00";
+						G_next <= X"09";
+						B_next <= X"66";
+					when X"72" =>
+						R_next <= X"09";
+						G_next <= X"18";
+						B_next <= X"75";
+					when X"73" =>
+						R_next <= X"1a";
+						G_next <= X"29";
+						B_next <= X"84";
+					when X"74" =>
+						R_next <= X"29";
+						G_next <= X"38";
+						B_next <= X"93";
+					when X"75" =>
+						R_next <= X"3a";
+						G_next <= X"49";
+						B_next <= X"a4";
+					when X"76" =>
+						R_next <= X"4a";
+						G_next <= X"59";
+						B_next <= X"b4";
+					when X"77" =>
+						R_next <= X"5c";
+						G_next <= X"6a";
+						B_next <= X"c3";
+					when X"78" =>
+						R_next <= X"66";
+						G_next <= X"74";
+						B_next <= X"cd";
+					when X"79" =>
+						R_next <= X"77";
+						G_next <= X"85";
+						B_next <= X"df";
+					when X"7a" =>
+						R_next <= X"87";
+						G_next <= X"96";
+						B_next <= X"ef";
+					when X"7b" =>
+						R_next <= X"98";
+						G_next <= X"a7";
+						B_next <= X"fc";
+					when X"7c" =>
+						R_next <= X"a8";
+						G_next <= X"b6";
+						B_next <= X"fe";
+					when X"7d" =>
+						R_next <= X"b9";
+						G_next <= X"c7";
+						B_next <= X"ff";
+					when X"7e" =>
+						R_next <= X"c8";
+						G_next <= X"d6";
+						B_next <= X"ff";
+					when X"7f" =>
+						R_next <= X"d8";
+						G_next <= X"e7";
+						B_next <= X"ff";
+					when X"80" =>
+						R_next <= X"00";
+						G_next <= X"0b";
+						B_next <= X"45";
+					when X"81" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"4f";
+					when X"82" =>
+						R_next <= X"00";
+						G_next <= X"25";
+						B_next <= X"5d";
+					when X"83" =>
+						R_next <= X"09";
+						G_next <= X"36";
+						B_next <= X"6d";
+					when X"84" =>
+						R_next <= X"18";
+						G_next <= X"45";
+						B_next <= X"7c";
+					when X"85" =>
+						R_next <= X"29";
+						G_next <= X"56";
+						B_next <= X"8d";
+					when X"86" =>
+						R_next <= X"39";
+						G_next <= X"66";
+						B_next <= X"9d";
+					when X"87" =>
+						R_next <= X"4b";
+						G_next <= X"77";
+						B_next <= X"ac";
+					when X"88" =>
+						R_next <= X"56";
+						G_next <= X"81";
+						B_next <= X"b6";
+					when X"89" =>
+						R_next <= X"67";
+						G_next <= X"92";
+						B_next <= X"c8";
+					when X"8a" =>
+						R_next <= X"77";
+						G_next <= X"a2";
+						B_next <= X"d9";
+					when X"8b" =>
+						R_next <= X"88";
+						G_next <= X"b3";
+						B_next <= X"e9";
+					when X"8c" =>
+						R_next <= X"98";
+						G_next <= X"c3";
+						B_next <= X"f7";
+					when X"8d" =>
+						R_next <= X"a9";
+						G_next <= X"d3";
+						B_next <= X"fe";
+					when X"8e" =>
+						R_next <= X"b8";
+						G_next <= X"e3";
+						B_next <= X"ff";
+					when X"8f" =>
+						R_next <= X"c8";
+						G_next <= X"f3";
+						B_next <= X"ff";
+					when X"90" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"25";
+					when X"91" =>
+						R_next <= X"00";
+						G_next <= X"22";
+						B_next <= X"30";
+					when X"92" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"3f";
+					when X"93" =>
+						R_next <= X"01";
+						G_next <= X"42";
+						B_next <= X"4f";
+					when X"94" =>
+						R_next <= X"0c";
+						G_next <= X"51";
+						B_next <= X"5e";
+					when X"95" =>
+						R_next <= X"1e";
+						G_next <= X"62";
+						B_next <= X"6f";
+					when X"96" =>
+						R_next <= X"2e";
+						G_next <= X"72";
+						B_next <= X"80";
+					when X"97" =>
+						R_next <= X"40";
+						G_next <= X"82";
+						B_next <= X"8f";
+					when X"98" =>
+						R_next <= X"4a";
+						G_next <= X"8d";
+						B_next <= X"99";
+					when X"99" =>
+						R_next <= X"5c";
+						G_next <= X"9d";
+						B_next <= X"ab";
+					when X"9a" =>
+						R_next <= X"6c";
+						G_next <= X"ae";
+						B_next <= X"bc";
+					when X"9b" =>
+						R_next <= X"7e";
+						G_next <= X"be";
+						B_next <= X"cc";
+					when X"9c" =>
+						R_next <= X"8d";
+						G_next <= X"ce";
+						B_next <= X"db";
+					when X"9d" =>
+						R_next <= X"9e";
+						G_next <= X"de";
+						B_next <= X"ed";
+					when X"9e" =>
+						R_next <= X"ad";
+						G_next <= X"ee";
+						B_next <= X"fa";
+					when X"9f" =>
+						R_next <= X"bd";
+						G_next <= X"fc";
+						B_next <= X"fe";
+					when X"a0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"a1" =>
+						R_next <= X"00";
+						G_next <= X"2f";
+						B_next <= X"00";
+					when X"a2" =>
+						R_next <= X"00";
+						G_next <= X"3e";
+						B_next <= X"0a";
+					when X"a3" =>
+						R_next <= X"00";
+						G_next <= X"4f";
+						B_next <= X"1a";
+					when X"a4" =>
+						R_next <= X"08";
+						G_next <= X"5e";
+						B_next <= X"29";
+					when X"a5" =>
+						R_next <= X"18";
+						G_next <= X"6f";
+						B_next <= X"3b";
+					when X"a6" =>
+						R_next <= X"28";
+						G_next <= X"7f";
+						B_next <= X"4b";
+					when X"a7" =>
+						R_next <= X"3a";
+						G_next <= X"8f";
+						B_next <= X"5c";
+					when X"a8" =>
+						R_next <= X"44";
+						G_next <= X"9a";
+						B_next <= X"65";
+					when X"a9" =>
+						R_next <= X"55";
+						G_next <= X"ab";
+						B_next <= X"78";
+					when X"aa" =>
+						R_next <= X"65";
+						G_next <= X"bb";
+						B_next <= X"88";
+					when X"ab" =>
+						R_next <= X"77";
+						G_next <= X"cc";
+						B_next <= X"99";
+					when X"ac" =>
+						R_next <= X"86";
+						G_next <= X"db";
+						B_next <= X"a8";
+					when X"ad" =>
+						R_next <= X"97";
+						G_next <= X"ec";
+						B_next <= X"ba";
+					when X"ae" =>
+						R_next <= X"a6";
+						G_next <= X"fa";
+						B_next <= X"c9";
+					when X"af" =>
+						R_next <= X"b7";
+						G_next <= X"fe";
+						B_next <= X"d9";
+					when X"b0" =>
+						R_next <= X"00";
+						G_next <= X"2a";
+						B_next <= X"00";
+					when X"b1" =>
+						R_next <= X"00";
+						G_next <= X"37";
+						B_next <= X"00";
+					when X"b2" =>
+						R_next <= X"00";
+						G_next <= X"46";
+						B_next <= X"00";
+					when X"b3" =>
+						R_next <= X"01";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"b4" =>
+						R_next <= X"0f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"b5" =>
+						R_next <= X"20";
+						G_next <= X"76";
+						B_next <= X"03";
+					when X"b6" =>
+						R_next <= X"31";
+						G_next <= X"85";
+						B_next <= X"13";
+					when X"b7" =>
+						R_next <= X"42";
+						G_next <= X"96";
+						B_next <= X"24";
+					when X"b8" =>
+						R_next <= X"4c";
+						G_next <= X"a1";
+						B_next <= X"2d";
+					when X"b9" =>
+						R_next <= X"5d";
+						G_next <= X"b1";
+						B_next <= X"40";
+					when X"ba" =>
+						R_next <= X"6d";
+						G_next <= X"c1";
+						B_next <= X"51";
+					when X"bb" =>
+						R_next <= X"7f";
+						G_next <= X"d2";
+						B_next <= X"62";
+					when X"bc" =>
+						R_next <= X"8e";
+						G_next <= X"e2";
+						B_next <= X"71";
+					when X"bd" =>
+						R_next <= X"9f";
+						G_next <= X"f2";
+						B_next <= X"82";
+					when X"be" =>
+						R_next <= X"af";
+						G_next <= X"fd";
+						B_next <= X"92";
+					when X"bf" =>
+						R_next <= X"bf";
+						G_next <= X"ff";
+						B_next <= X"a1";
+					when X"c0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"c1" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"00";
+					when X"c2" =>
+						R_next <= X"05";
+						G_next <= X"40";
+						B_next <= X"00";
+					when X"c3" =>
+						R_next <= X"16";
+						G_next <= X"50";
+						B_next <= X"00";
+					when X"c4" =>
+						R_next <= X"26";
+						G_next <= X"5f";
+						B_next <= X"00";
+					when X"c5" =>
+						R_next <= X"36";
+						G_next <= X"70";
+						B_next <= X"00";
+					when X"c6" =>
+						R_next <= X"47";
+						G_next <= X"80";
+						B_next <= X"00";
+					when X"c7" =>
+						R_next <= X"58";
+						G_next <= X"90";
+						B_next <= X"08";
+					when X"c8" =>
+						R_next <= X"62";
+						G_next <= X"9b";
+						B_next <= X"12";
+					when X"c9" =>
+						R_next <= X"73";
+						G_next <= X"ac";
+						B_next <= X"24";
+					when X"ca" =>
+						R_next <= X"84";
+						G_next <= X"bc";
+						B_next <= X"35";
+					when X"cb" =>
+						R_next <= X"95";
+						G_next <= X"cd";
+						B_next <= X"46";
+					when X"cc" =>
+						R_next <= X"a4";
+						G_next <= X"dc";
+						B_next <= X"55";
+					when X"cd" =>
+						R_next <= X"b5";
+						G_next <= X"ed";
+						B_next <= X"67";
+					when X"ce" =>
+						R_next <= X"c5";
+						G_next <= X"fb";
+						B_next <= X"77";
+					when X"cf" =>
+						R_next <= X"d5";
+						G_next <= X"ff";
+						B_next <= X"86";
+					when X"d0" =>
+						R_next <= X"02";
+						G_next <= X"18";
+						B_next <= X"00";
+					when X"d1" =>
+						R_next <= X"0f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"d2" =>
+						R_next <= X"1f";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"d3" =>
+						R_next <= X"2f";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"d4" =>
+						R_next <= X"3f";
+						G_next <= X"54";
+						B_next <= X"00";
+					when X"d5" =>
+						R_next <= X"4f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"d6" =>
+						R_next <= X"60";
+						G_next <= X"75";
+						B_next <= X"00";
+					when X"d7" =>
+						R_next <= X"70";
+						G_next <= X"86";
+						B_next <= X"01";
+					when X"d8" =>
+						R_next <= X"7b";
+						G_next <= X"90";
+						B_next <= X"0a";
+					when X"d9" =>
+						R_next <= X"8c";
+						G_next <= X"a1";
+						B_next <= X"1c";
+					when X"da" =>
+						R_next <= X"9c";
+						G_next <= X"b1";
+						B_next <= X"2c";
+					when X"db" =>
+						R_next <= X"ad";
+						G_next <= X"c2";
+						B_next <= X"3e";
+					when X"dc" =>
+						R_next <= X"bd";
+						G_next <= X"d1";
+						B_next <= X"4d";
+					when X"dd" =>
+						R_next <= X"cd";
+						G_next <= X"e2";
+						B_next <= X"5e";
+					when X"de" =>
+						R_next <= X"dd";
+						G_next <= X"f1";
+						B_next <= X"6e";
+					when X"df" =>
+						R_next <= X"ed";
+						G_next <= X"fd";
+						B_next <= X"7e";
+					when X"e0" =>
+						R_next <= X"1e";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"e1" =>
+						R_next <= X"2a";
+						G_next <= X"16";
+						B_next <= X"00";
+					when X"e2" =>
+						R_next <= X"39";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"e3" =>
+						R_next <= X"49";
+						G_next <= X"36";
+						B_next <= X"00";
+					when X"e4" =>
+						R_next <= X"58";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"e5" =>
+						R_next <= X"69";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"e6" =>
+						R_next <= X"79";
+						G_next <= X"66";
+						B_next <= X"00";
+					when X"e7" =>
+						R_next <= X"8a";
+						G_next <= X"77";
+						B_next <= X"08";
+					when X"e8" =>
+						R_next <= X"94";
+						G_next <= X"81";
+						B_next <= X"12";
+					when X"e9" =>
+						R_next <= X"a5";
+						G_next <= X"92";
+						B_next <= X"24";
+					when X"ea" =>
+						R_next <= X"b5";
+						G_next <= X"a3";
+						B_next <= X"35";
+					when X"eb" =>
+						R_next <= X"c6";
+						G_next <= X"b3";
+						B_next <= X"46";
+					when X"ec" =>
+						R_next <= X"d6";
+						G_next <= X"c3";
+						B_next <= X"55";
+					when X"ed" =>
+						R_next <= X"e6";
+						G_next <= X"d4";
+						B_next <= X"66";
+					when X"ee" =>
+						R_next <= X"f6";
+						G_next <= X"e3";
+						B_next <= X"76";
+					when X"ef" =>
+						R_next <= X"fe";
+						G_next <= X"f3";
+						B_next <= X"86";
+					when X"f0" =>
+						R_next <= X"34";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"f1" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"f2" =>
+						R_next <= X"4f";
+						G_next <= X"15";
+						B_next <= X"00";
+					when X"f3" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"f4" =>
+						R_next <= X"6e";
+						G_next <= X"35";
+						B_next <= X"00";
+					when X"f5" =>
+						R_next <= X"7f";
+						G_next <= X"46";
+						B_next <= X"03";
+					when X"f6" =>
+						R_next <= X"8f";
+						G_next <= X"56";
+						B_next <= X"13";
+					when X"f7" =>
+						R_next <= X"9f";
+						G_next <= X"67";
+						B_next <= X"23";
+					when X"f8" =>
+						R_next <= X"aa";
+						G_next <= X"71";
+						B_next <= X"2e";
+					when X"f9" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"fa" =>
+						R_next <= X"cb";
+						G_next <= X"92";
+						B_next <= X"51";
+					when X"fb" =>
+						R_next <= X"dc";
+						G_next <= X"a3";
+						B_next <= X"62";
+					when X"fc" =>
+						R_next <= X"eb";
+						G_next <= X"b3";
+						B_next <= X"71";
+					when X"fd" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"fe" =>
+						R_next <= X"fe";
+						G_next <= X"d3";
+						B_next <= X"92";
+					when X"ff" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+					when others =>
+						-- nop
+			end case;
+			
+		end process;
+		
+end laoo;
Index: common/a8core/gtia_player.vhdl
===================================================================
--- common/a8core/gtia_player.vhdl	(nonexistent)
+++ common/a8core/gtia_player.vhdl	(revision 1)
@@ -0,0 +1,116 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_player IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : in std_logic;
+	
+	COLOUR_ENABLE : IN STD_LOGIC;
+	LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+	PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+	SIZE : in std_logic_vector(1 downto 0);
+	bitmap : in std_logic_vector(7 downto 0);
+	
+	output : out std_logic
+);
+END gtia_player;
+
+ARCHITECTURE vhdl OF gtia_player IS
+
+	-- pmgs
+	signal shift_next : std_logic_vector(7 downto 0);
+	signal shift_reg : std_logic_vector(7 downto 0);
+	signal count_next : std_logic_vector(1 downto 0);
+	signal count_reg : std_logic_vector(1 downto 0);
+begin
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= (others=>'0');
+			count_reg <= (others=>'0');		
+		elsif (clk'event and clk='1') then										
+			shift_reg <= shift_next;
+			count_reg <= count_next;
+		end if;
+	end process;
+	
+	
+	process(shift_next,COLOUR_ENABLE, live_position, player_position, size, bitmap, shift_reg, count_reg)
+	begin
+		-- size is 2 bits (00 normal, 01 twice, 10 normal(bugged), 11 four times)
+		-- grafp0 is 8 bits of data (2 bits for missiles)
+		-- hposp0_reg is position - 0x30 is left side of normal playfield, 0xd0 is right size of normal playfield
+		
+		-- 'or' into shift register, so if not empty we get extra pixels
+		
+		-- counter before we shift	
+		
+		shift_next <= shift_reg;
+		count_next <= count_reg;
+		
+		output <= shift_next(7);
+		
+		if (COLOUR_ENABLE = '1') then								
+			case size is 
+				when "00" => -- normal size
+					count_next <= "00";
+					shift_next <= shift_reg(6 downto 0) &'0';
+				when "10" => -- normal size (with bug)
+					case count_reg is
+						when "00"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "01"|"10" =>
+							count_next <= "10";						
+						when others=>
+							--hang!
+					end case;					
+				when "01" =>					
+					case count_reg is
+						when "01"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "00"|"10" =>
+							count_next <= "01";							
+						when others=>
+							--hang!
+					end case;					
+
+				when "11" =>
+					case count_reg is
+						when "00" =>
+							count_next <= "01";
+						when "01" =>
+							count_next <= "10";						
+						when "10" =>
+							count_next <= "11";
+						when "11" =>
+							shift_next <= shift_reg(6 downto 0) &'0';
+							count_next <= "00";
+						when others=>
+							--hang!
+					end case;
+				when others=>
+					--hang!
+			end case;	
+
+			if (live_position = player_position) then
+				shift_next <= shift_reg(6 downto 0) &'0' or bitmap;
+				count_next <= (others=>'0');
+			end if;			
+		end if;
+		
+	end process;
+	
+end vhdl;
Index: common/a8core/gtia_priority.vhdl
===================================================================
--- common/a8core/gtia_priority.vhdl	(nonexistent)
+++ common/a8core/gtia_priority.vhdl	(revision 1)
@@ -0,0 +1,175 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_priority IS
+PORT 
+( 
+	CLK : in std_logic;
+	colour_enable : in std_logic;
+
+	PRIOR : in std_logic_vector(7 downto 0);
+	P0 : in std_logic;
+	P1 : in std_logic;
+	P2	: in std_logic;
+	P3 : in std_logic;
+	PF0 : in std_logic;
+	PF1 : in std_logic;
+	PF2 : in std_logic;
+	PF3 : in std_logic;
+	BK : in std_logic;
+	
+	P0_OUT : out std_logic;
+	P1_OUT : out std_logic;
+	P2_OUT : out std_logic;
+	P3_OUT : out std_logic;
+	PF0_OUT : out std_logic;
+	PF1_OUT : out std_logic;
+	PF2_OUT : out std_logic;
+	PF3_OUT : out std_logic;
+	BK_OUT : out std_logic
+);
+END gtia_priority;
+
+ARCHITECTURE vhdl OF gtia_priority IS
+	signal P01 : std_logic;
+	signal P23 : std_logic;
+	
+	signal PF01 : std_logic;
+	signal PF23 : std_logic;
+	
+	signal PRI01 : std_logic;
+	signal PRI12 : std_logic;
+	signal PRI23 : std_logic;
+	signal PRI03 : std_logic;
+	
+	signal PRI0 : std_logic;
+	signal PRI1 : std_logic;
+	signal PRI2 : std_logic;
+	signal PRI3 : std_logic;
+	signal MULTI : std_logic;
+	
+	signal SP0 : std_logic;
+	signal SP1 : std_logic;
+	signal SP2 : std_logic;
+	signal SP3 : std_logic;	
+	signal SF0 : std_logic;
+	signal SF1 : std_logic;
+	signal SF2 : std_logic;
+	signal SF3 : std_logic;	
+	signal SB : std_logic;
+	
+	signal SP0_next : std_logic;
+	signal SP1_next : std_logic;
+	signal SP2_next : std_logic;
+	signal SP3_next : std_logic;	
+	signal SF0_next : std_logic;
+	signal SF1_next : std_logic;
+	signal SF2_next : std_logic;
+	signal SF3_next : std_logic;	
+	signal SB_next : std_logic;
+
+	signal SP0_reg : std_logic;
+	signal SP1_reg : std_logic;
+	signal SP2_reg : std_logic;
+	signal SP3_reg : std_logic;	
+	signal SF0_reg : std_logic;
+	signal SF1_reg : std_logic;
+	signal SF2_reg : std_logic;
+	signal SF3_reg : std_logic;	
+	signal SB_reg : std_logic;
+begin
+	-- Use actual GTIA logic...
+	P01 <= P0 or P1;
+	P23 <= P2 or P3;
+
+	PF01 <= PF0 or PF1;
+	PF23 <= PF2 or PF3;
+	
+	PRI0 <= prior(0);
+	PRI1 <= prior(1);
+	PRI2 <= prior(2);
+	PRI3 <= prior(3);
+	MULTI <= prior(5);
+	
+	PRI01 <= PRI0  or  PRI1;
+	PRI12 <= PRI1  or  PRI2;
+	PRI23 <= PRI2  or  PRI3;
+	PRI03 <= PRI0  or  PRI3;
+	
+	SP0 <= P0  and   not (PF01 and PRI23)  and   not (PRI2 and PF23);
+	SP1 <= P1  and   not (PF01 and PRI23)  and   not (PRI2 and PF23)  and  ( not P0  or  MULTI);
+	SP2 <= P2  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0);
+	SP3 <= P3  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0)  and  ( not P2  or  MULTI);
+	SF0 <= PF0  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF1 <= PF1  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF2 <= PF2  and   not (P23 and PRI03)  and   not (P01 and  not PRI2)  and   not SF3;
+	SF3 <= PF3  and   not (P23 and PRI03)  and   not (P01 and  not PRI2);
+	SB <=  not P01  and   not P23  and   not PF01  and   not PF23;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+		SP0_reg <= SP0_next;
+		SP1_reg <= SP1_next;
+		SP2_reg <= SP2_next;
+		SP3_reg <= SP3_next;
+		
+		SF0_reg <= SF0_next;
+		SF1_reg <= SF1_next;
+		SF2_reg <= SF2_next;
+		SF3_reg <= SF3_next;
+		
+		SB_reg <= SB_next;
+		end if;
+	end process;
+	
+	-- need to register this to get same position as GTIA modes - i.e. two colour clocks after AN data received
+	process(colour_enable,SP0_reg,SP1_reg,SP2_reg,SP3_reg,SF0_reg,SF1_reg,SF2_reg,SF3_reg,SB_reg,SP0,SP1,SP2,SP3,SF0,SF1,SF2,SF3,SB)
+	begin
+		SP0_next <= SP0_reg;
+		SP1_next <= SP1_reg;
+		SP2_next <= SP2_reg;
+		SP3_next <= SP3_reg;
+		
+		SF0_next <= SF0_reg;
+		SF1_next <= SF1_reg;
+		SF2_next <= SF2_reg;
+		SF3_next <= SF3_reg;
+		
+		SB_next <= SB_reg;
+		
+		if (colour_enable = '1') then	
+			SP0_next <= SP0;
+			SP1_next <= SP1;
+			SP2_next <= SP2;
+			SP3_next <= SP3;
+			
+			SF0_next <= SF0;
+			SF1_next <= SF1;
+			SF2_next <= SF2;
+			SF3_next <= SF3;
+			
+			SB_next <= SB;	
+		end if;
+	end process;
+		
+	-- output
+	P0_OUT <= SP0_reg;
+	P1_OUT <= SP1_reg;
+	P2_OUT <= SP2_reg;
+	P3_OUT <= SP3_reg;
+	PF0_OUT <= SF0_reg;
+	PF1_OUT <= SF1_reg;
+	PF2_OUT <= SF2_reg;
+	PF3_OUT <= SF3_reg;
+	BK_OUT <= SB_reg;
+end vhdl;
\ No newline at end of file
Index: common/a8core/internalromram.vhd
===================================================================
--- common/a8core/internalromram.vhd	(nonexistent)
+++ common/a8core/internalromram.vhd	(revision 1)
@@ -0,0 +1,138 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+END internalromram;
+
+architecture vhdl of internalromram is
+--component ramint IS
+--	PORT
+--	(
+--		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+--		clock		: IN STD_LOGIC  := '1';
+--		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+--		wren		: IN STD_LOGIC ;
+--		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+--	);
+--END component;
+
+component generic_ram_infer IS
+        generic
+        (
+                ADDRESS_WIDTH : natural := 9;
+                SPACE : natural := 512;
+                DATA_WIDTH : natural := 8
+        );
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+      address:  IN   std_logic_vector(address_width-1 downto 0);
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+   );
+END component;
+
+component os16 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+component basic IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+	signal rom_request_reg : std_logic;
+	signal ram_request_reg : std_logic;
+	
+	signal ROM16_DATA : std_logic_vector(7 downto 0);
+	signal BASIC_DATA : std_logic_vector(7 downto 0);	
+	
+	signal RAM_WR_ENABLE_REAL : std_logic;
+	signal IRAM_DATA : std_logic_vector(7 downto 0);
+
+begin
+	process(clock,reset_n)
+	begin
+		if (reset_n ='0') then
+			rom_request_reg <= '0';
+			ram_request_reg <= '0';
+		elsif (clock'event and clock='1') then
+			rom_request_reg <= rom_request;
+			ram_request_reg <= ram_request;
+		end if;
+	end process;
+
+	rom_request_complete <= rom_request_reg;
+	--C000 = basic. 
+	--0000-07FF = low
+	--0800-27ff high
+	
+	process(rom16_data,basic_data, rom_addr(15 downto 0))
+	begin
+		ROM_DATA <= ROM16_DATA;
+		if (rom_addr(15)='1') then
+			ROM_DATA <= BASIC_DATA;
+		end if;
+	end process;
+	
+	
+	--ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
+	--ROM_DATA <= ROMHI_DATA;
+	basic1 : basic
+	PORT MAP(clock => clock,
+			 address => rom_addr(12 downto 0),
+			 q => BASIC_data
+			 );			 
+			 
+	rom16a : os16
+	PORT MAP(clock => clock,
+			 address => rom_addr(13 downto 0),
+			 q => ROM16_data
+			 );
+	
+	ramint1 : generic_ram_infer
+        generic map
+        (
+                ADDRESS_WIDTH => 14,
+                SPACE => 16384,
+                DATA_WIDTH =>8
+        )
+	PORT MAP(clock => clock,
+			 address => ram_addr(13 downto 0),
+			 data => ram_data_in(7 downto 0),
+			 we => RAM_WR_ENABLE_REAL,
+			 q => iram_data
+			 );	
+	ram_request_complete <= ram_request_reg;
+	
+	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 14)= "00" else X"FF";
+	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 14)="00" else '0'; -- ban writes over 16k when using int ram - HACK
+end vhdl;
Index: common/a8core/irq_glue.vhdl
===================================================================
--- common/a8core/irq_glue.vhdl	(nonexistent)
+++ common/a8core/irq_glue.vhdl	(revision 1)
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY irq_glue IS
+PORT 
+( 
+	pokey_irq : in std_logic;
+	pia_irqa : in std_logic;
+	pia_irqb : in std_logic;
+	
+	combined_irq : out std_logic
+);
+end irq_glue;
+
+architecture vhdl of irq_glue is
+begin
+	combined_irq <= pokey_irq and pia_irqa and pia_irqb;
+end vhdl;
\ No newline at end of file
Index: common/a8core/os16.vhdl
===================================================================
--- common/a8core/os16.vhdl	(nonexistent)
+++ common/a8core/os16.vhdl	(revision 1)
@@ -0,0 +1,16418 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity os16 is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(13 downto 0);
+        q:out std_logic_vector(7 downto 0)
+);
+end os16;
+
+architecture syn of os16 is
+        type rom_type is array(0 to 16383) of std_logic_vector(7 downto 0);
+        signal ROM:rom_type:=
+(
+	X"11",
+X"92",
+X"10",
+X"05",
+X"83",
+X"00",
+X"42",
+X"42",
+X"00",
+X"00",
+X"01",
+X"02",
+X"a9",
+X"40",
+X"8d",
+X"0e",
+X"d4",
+X"ad",
+X"13",
+X"d0",
+X"8d",
+X"fa",
+X"03",
+X"60",
+X"2c",
+X"0f",
+X"d4",
+X"10",
+X"03",
+X"6c",
+X"00",
+X"02",
+X"d8",
+X"48",
+X"8a",
+X"48",
+X"98",
+X"48",
+X"8d",
+X"0f",
+X"d4",
+X"6c",
+X"22",
+X"02",
+X"d8",
+X"6c",
+X"16",
+X"02",
+X"48",
+X"ad",
+X"0e",
+X"d2",
+X"29",
+X"20",
+X"d0",
+X"0d",
+X"a9",
+X"df",
+X"8d",
+X"0e",
+X"d2",
+X"a5",
+X"10",
+X"8d",
+X"0e",
+X"d2",
+X"6c",
+X"0a",
+X"02",
+X"8a",
+X"48",
+X"ad",
+X"ff",
+X"d1",
+X"2d",
+X"49",
+X"02",
+X"f0",
+X"03",
+X"6c",
+X"38",
+X"02",
+X"a2",
+X"06",
+X"bd",
+X"cf",
+X"c0",
+X"e0",
+X"05",
+X"d0",
+X"04",
+X"25",
+X"10",
+X"f0",
+X"05",
+X"2c",
+X"0e",
+X"d2",
+X"f0",
+X"06",
+X"ca",
+X"10",
+X"ed",
+X"4c",
+X"a0",
+X"c0",
+X"49",
+X"ff",
+X"8d",
+X"0e",
+X"d2",
+X"a5",
+X"10",
+X"8d",
+X"0e",
+X"d2",
+X"e0",
+X"00",
+X"d0",
+X"05",
+X"ad",
+X"6d",
+X"02",
+X"d0",
+X"23",
+X"bd",
+X"d7",
+X"c0",
+X"aa",
+X"bd",
+X"00",
+X"02",
+X"8d",
+X"8c",
+X"02",
+X"bd",
+X"01",
+X"02",
+X"8d",
+X"8d",
+X"02",
+X"68",
+X"aa",
+X"6c",
+X"8c",
+X"02",
+X"a9",
+X"00",
+X"85",
+X"11",
+X"8d",
+X"ff",
+X"02",
+X"8d",
+X"f0",
+X"02",
+X"85",
+X"4d",
+X"68",
+X"40",
+X"68",
+X"aa",
+X"2c",
+X"02",
+X"d3",
+X"10",
+X"06",
+X"ad",
+X"00",
+X"d3",
+X"6c",
+X"02",
+X"02",
+X"2c",
+X"03",
+X"d3",
+X"10",
+X"06",
+X"ad",
+X"01",
+X"d3",
+X"6c",
+X"04",
+X"02",
+X"68",
+X"8d",
+X"8c",
+X"02",
+X"68",
+X"48",
+X"29",
+X"10",
+X"f0",
+X"07",
+X"ad",
+X"8c",
+X"02",
+X"48",
+X"6c",
+X"06",
+X"02",
+X"ad",
+X"8c",
+X"02",
+X"48",
+X"68",
+X"40",
+X"80",
+X"40",
+X"04",
+X"02",
+X"01",
+X"08",
+X"10",
+X"20",
+X"36",
+X"08",
+X"14",
+X"12",
+X"10",
+X"0e",
+X"0c",
+X"0a",
+X"4c",
+X"df",
+X"c0",
+X"e6",
+X"14",
+X"d0",
+X"08",
+X"e6",
+X"4d",
+X"e6",
+X"13",
+X"d0",
+X"02",
+X"e6",
+X"12",
+X"a9",
+X"fe",
+X"a2",
+X"00",
+X"a4",
+X"4d",
+X"10",
+X"06",
+X"85",
+X"4d",
+X"a6",
+X"13",
+X"a9",
+X"f6",
+X"85",
+X"4e",
+X"86",
+X"4f",
+X"ad",
+X"c5",
+X"02",
+X"45",
+X"4f",
+X"25",
+X"4e",
+X"8d",
+X"17",
+X"d0",
+X"a2",
+X"00",
+X"20",
+X"55",
+X"c2",
+X"d0",
+X"03",
+X"20",
+X"4f",
+X"c2",
+X"a5",
+X"42",
+X"d0",
+X"08",
+X"ba",
+X"bd",
+X"04",
+X"01",
+X"29",
+X"04",
+X"f0",
+X"03",
+X"4c",
+X"8a",
+X"c2",
+X"ad",
+X"13",
+X"d0",
+X"cd",
+X"fa",
+X"03",
+X"d0",
+X"b4",
+X"ad",
+X"0d",
+X"d4",
+X"8d",
+X"35",
+X"02",
+X"ad",
+X"0c",
+X"d4",
+X"8d",
+X"34",
+X"02",
+X"ad",
+X"31",
+X"02",
+X"8d",
+X"03",
+X"d4",
+X"ad",
+X"30",
+X"02",
+X"8d",
+X"02",
+X"d4",
+X"ad",
+X"2f",
+X"02",
+X"8d",
+X"00",
+X"d4",
+X"ad",
+X"6f",
+X"02",
+X"8d",
+X"1b",
+X"d0",
+X"ad",
+X"6c",
+X"02",
+X"f0",
+X"0e",
+X"ce",
+X"6c",
+X"02",
+X"a9",
+X"08",
+X"38",
+X"ed",
+X"6c",
+X"02",
+X"29",
+X"07",
+X"8d",
+X"05",
+X"d4",
+X"a2",
+X"08",
+X"8e",
+X"1f",
+X"d0",
+X"58",
+X"bd",
+X"c0",
+X"02",
+X"45",
+X"4f",
+X"25",
+X"4e",
+X"9d",
+X"12",
+X"d0",
+X"ca",
+X"10",
+X"f2",
+X"ad",
+X"f4",
+X"02",
+X"8d",
+X"09",
+X"d4",
+X"ad",
+X"f3",
+X"02",
+X"8d",
+X"01",
+X"d4",
+X"a2",
+X"02",
+X"20",
+X"55",
+X"c2",
+X"d0",
+X"03",
+X"20",
+X"52",
+X"c2",
+X"a2",
+X"02",
+X"e8",
+X"e8",
+X"bd",
+X"18",
+X"02",
+X"1d",
+X"19",
+X"02",
+X"f0",
+X"06",
+X"20",
+X"55",
+X"c2",
+X"9d",
+X"26",
+X"02",
+X"e0",
+X"08",
+X"d0",
+X"ec",
+X"ad",
+X"0f",
+X"d2",
+X"29",
+X"04",
+X"f0",
+X"08",
+X"ad",
+X"f1",
+X"02",
+X"f0",
+X"03",
+X"ce",
+X"f1",
+X"02",
+X"ad",
+X"2b",
+X"02",
+X"f0",
+X"3e",
+X"ad",
+X"0f",
+X"d2",
+X"29",
+X"04",
+X"d0",
+X"32",
+X"ce",
+X"2b",
+X"02",
+X"d0",
+X"32",
+X"ad",
+X"6d",
+X"02",
+X"d0",
+X"2d",
+X"ad",
+X"da",
+X"02",
+X"8d",
+X"2b",
+X"02",
+X"ad",
+X"09",
+X"d2",
+X"c9",
+X"9f",
+X"f0",
+X"20",
+X"c9",
+X"83",
+X"f0",
+X"1c",
+X"c9",
+X"84",
+X"f0",
+X"18",
+X"c9",
+X"94",
+X"f0",
+X"14",
+X"29",
+X"3f",
+X"c9",
+X"11",
+X"f0",
+X"0e",
+X"ad",
+X"09",
+X"d2",
+X"8d",
+X"fc",
+X"02",
+X"4c",
+X"f3",
+X"c1",
+X"a9",
+X"00",
+X"8d",
+X"2b",
+X"02",
+X"ad",
+X"00",
+X"d3",
+X"4a",
+X"4a",
+X"4a",
+X"4a",
+X"8d",
+X"79",
+X"02",
+X"8d",
+X"7b",
+X"02",
+X"ad",
+X"00",
+X"d3",
+X"29",
+X"0f",
+X"8d",
+X"78",
+X"02",
+X"8d",
+X"7a",
+X"02",
+X"ad",
+X"10",
+X"d0",
+X"8d",
+X"84",
+X"02",
+X"8d",
+X"86",
+X"02",
+X"ad",
+X"11",
+X"d0",
+X"8d",
+X"85",
+X"02",
+X"8d",
+X"87",
+X"02",
+X"a2",
+X"03",
+X"bd",
+X"00",
+X"d2",
+X"9d",
+X"70",
+X"02",
+X"9d",
+X"74",
+X"02",
+X"ca",
+X"10",
+X"f4",
+X"8d",
+X"0b",
+X"d2",
+X"a2",
+X"02",
+X"a0",
+X"01",
+X"b9",
+X"78",
+X"02",
+X"4a",
+X"4a",
+X"4a",
+X"9d",
+X"7d",
+X"02",
+X"9d",
+X"81",
+X"02",
+X"a9",
+X"00",
+X"2a",
+X"9d",
+X"7c",
+X"02",
+X"9d",
+X"80",
+X"02",
+X"ca",
+X"ca",
+X"88",
+X"10",
+X"e6",
+X"6c",
+X"24",
+X"02",
+X"6c",
+X"26",
+X"02",
+X"6c",
+X"28",
+X"02",
+X"bc",
+X"18",
+X"02",
+X"d0",
+X"08",
+X"bc",
+X"19",
+X"02",
+X"f0",
+X"10",
+X"de",
+X"19",
+X"02",
+X"de",
+X"18",
+X"02",
+X"d0",
+X"08",
+X"bc",
+X"19",
+X"02",
+X"d0",
+X"03",
+X"a9",
+X"00",
+X"60",
+X"a9",
+X"ff",
+X"60",
+X"0a",
+X"8d",
+X"2d",
+X"02",
+X"8a",
+X"a2",
+X"05",
+X"8d",
+X"0a",
+X"d4",
+X"ca",
+X"d0",
+X"fd",
+X"ae",
+X"2d",
+X"02",
+X"9d",
+X"17",
+X"02",
+X"98",
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+X"a9",
+X"00",
+X"8d",
+X"de",
+X"02",
+X"ae",
+X"a1",
+X"fe",
+X"ac",
+X"a2",
+X"fe",
+X"20",
+X"14",
+X"ff",
+X"4c",
+X"59",
+X"e4",
+X"20",
+X"4b",
+X"ff",
+X"a9",
+X"9b",
+X"ae",
+X"de",
+X"02",
+X"d0",
+X"dc",
+X"a0",
+X"01",
+X"60",
+X"8e",
+X"04",
+X"03",
+X"8c",
+X"05",
+X"03",
+X"a9",
+X"40",
+X"8d",
+X"00",
+X"03",
+X"a5",
+X"21",
+X"8d",
+X"01",
+X"03",
+X"a9",
+X"80",
+X"ae",
+X"02",
+X"03",
+X"e0",
+X"53",
+X"d0",
+X"02",
+X"a9",
+X"40",
+X"8d",
+X"03",
+X"03",
+X"ad",
+X"df",
+X"02",
+X"8d",
+X"08",
+X"03",
+X"a9",
+X"00",
+X"8d",
+X"09",
+X"03",
+X"ad",
+X"14",
+X"03",
+X"8d",
+X"06",
+X"03",
+X"60",
+X"ad",
+X"ec",
+X"02",
+X"8d",
+X"14",
+X"03",
+X"60",
+X"a0",
+X"57",
+X"a5",
+X"2b",
+X"c9",
+X"4e",
+X"d0",
+X"04",
+X"a2",
+X"28",
+X"d0",
+X"0e",
+X"c9",
+X"44",
+X"d0",
+X"04",
+X"a2",
+X"14",
+X"d0",
+X"06",
+X"c9",
+X"53",
+X"d0",
+X"0c",
+X"a2",
+X"1d",
+X"8e",
+X"df",
+X"02",
+X"8c",
+X"02",
+X"03",
+X"8d",
+X"0a",
+X"03",
+X"60",
+X"a9",
+X"4e",
+X"d0",
+X"dc",
+X"a2",
+X"00",
+X"86",
+X"8b",
+X"86",
+X"8c",
+X"20",
+X"a9",
+X"ff",
+X"e0",
+X"0c",
+X"d0",
+X"f9",
+X"ad",
+X"00",
+X"c0",
+X"ae",
+X"01",
+X"c0",
+X"c5",
+X"8b",
+X"d0",
+X"06",
+X"e4",
+X"8c",
+X"d0",
+X"02",
+X"18",
+X"60",
+X"38",
+X"60",
+X"a2",
+X"00",
+X"86",
+X"8b",
+X"86",
+X"8c",
+X"a2",
+X"0c",
+X"20",
+X"a9",
+X"ff",
+X"20",
+X"a9",
+X"ff",
+X"ad",
+X"f8",
+X"ff",
+X"ae",
+X"f9",
+X"ff",
+X"4c",
+X"86",
+X"ff",
+X"a0",
+X"00",
+X"bd",
+X"d7",
+X"ff",
+X"99",
+X"9e",
+X"00",
+X"e8",
+X"c8",
+X"c0",
+X"04",
+X"d0",
+X"f4",
+X"a0",
+X"00",
+X"18",
+X"b1",
+X"9e",
+X"65",
+X"8b",
+X"85",
+X"8b",
+X"90",
+X"02",
+X"e6",
+X"8c",
+X"e6",
+X"9e",
+X"d0",
+X"02",
+X"e6",
+X"9f",
+X"a5",
+X"9e",
+X"c5",
+X"a0",
+X"d0",
+X"e9",
+X"a5",
+X"9f",
+X"c5",
+X"a1",
+X"d0",
+X"e3",
+X"60",
+X"02",
+X"c0",
+X"00",
+X"d0",
+X"00",
+X"50",
+X"00",
+X"58",
+X"00",
+X"d8",
+X"00",
+X"e0",
+X"00",
+X"e0",
+X"f8",
+X"ff",
+X"fa",
+X"ff",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"10",
+X"05",
+X"83",
+X"02",
+X"42",
+X"42",
+X"00",
+X"00",
+X"01",
+X"02",
+X"8c",
+X"6c",
+X"18",
+X"c0",
+X"aa",
+X"c2",
+X"2c",
+X"c0"
+
+);
+        signal rdata:std_logic_vector(7 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: common/a8core/pia.vhdl
===================================================================
--- common/a8core/pia.vhdl	(nonexistent)
+++ common/a8core/pia.vhdl	(revision 1)
@@ -0,0 +1,406 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;	
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- pull up - i.e. 0 driven only
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC
+);
+END pia;
+
+ARCHITECTURE vhdl OF pia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	signal addr_decoded : std_logic_vector(3 downto 0);
+	
+	signal porta_output_next : std_logic_vector(7 downto 0);
+	signal porta_output_reg : std_logic_vector(7 downto 0);
+	signal porta_input_reg : std_logic_vector(7 downto 0);
+	signal porta_input_next : std_logic_vector(7 downto 0);
+
+	signal porta_direction_next : std_logic_vector(7 downto 0);
+	signal porta_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal porta_control_next : std_logic_vector(5 downto 0);
+	signal porta_control_reg : std_logic_vector(5 downto 0);
+	
+	signal portb_output_next : std_logic_vector(7 downto 0);
+	signal portb_output_reg : std_logic_vector(7 downto 0);
+	signal portb_input_reg : std_logic_vector(7 downto 0);
+	signal portb_input_next : std_logic_vector(7 downto 0);	
+
+	signal portb_direction_next : std_logic_vector(7 downto 0);
+	signal portb_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal portb_control_next : std_logic_vector(5 downto 0);
+	signal portb_control_reg : std_logic_vector(5 downto 0);
+	
+	signal irqa_next : std_logic_vector(1 downto 0);
+	signal irqa_reg : std_logic_vector(1 downto 0);
+	signal irqb_next : std_logic_vector(1 downto 0);
+	signal irqb_reg : std_logic_vector(1 downto 0);
+	
+	signal CA1_reg : std_logic;
+	signal CA2_reg : std_logic;
+	signal CB1_reg : std_logic;
+	signal CB2_reg : std_logic;
+
+	signal CA2_output_next : std_logic;
+	signal CA2_output_reg : std_logic;
+	signal CB2_output_next : std_logic;
+	signal CB2_output_reg : std_logic;
+	
+	signal read_ora : std_logic;
+	signal read_orb : std_logic;
+	
+	signal write_ora : std_logic;
+	signal write_orb : std_logic;
+
+	signal ca1_edge_next : std_logic;
+	signal ca1_edge_reg : std_logic;	
+	signal ca2_edge_next : std_logic;
+	signal ca2_edge_reg : std_logic;
+	
+	signal cb1_edge_next : std_logic;
+	signal cb1_edge_reg : std_logic;	
+	signal cb2_edge_next : std_logic;
+	signal cb2_edge_reg : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			porta_output_reg <= (others=>'0');
+			porta_input_reg <= (others=>'0');
+			porta_direction_reg <= (others=>'0'); -- default to input
+			porta_control_reg <= (others=>'0');
+			
+			portb_output_reg <= X"FF"; -- all high to ensure we have OS Rom enabled
+			portb_input_reg <= (others=>'0');
+			portb_direction_reg <= (others=>'1'); -- default to ouput
+			portb_control_reg <= (others=>'0');
+			
+			irqa_reg <= (others=>'0');
+			irqb_reg <= (others=>'0');
+			
+			CA1_reg	<= '0';
+			CA2_reg	<= '0';
+			CB1_reg	<= '0';
+			CB2_reg	<= '0';
+			
+			CA2_output_reg <= '0';
+			CB2_output_reg <= '0';
+			
+			ca1_edge_reg <= '0';
+			ca2_edge_reg <= '0';
+			
+			cb1_edge_reg <= '0';
+			cb2_edge_reg <= '0';
+			
+		elsif (clk'event and clk='1') then						
+			porta_output_reg <= porta_output_next;
+			porta_input_reg <= porta_input_next;
+			porta_direction_reg <= porta_direction_next;
+			porta_control_reg <= porta_control_next;
+			
+			portb_output_reg <= portb_output_next;
+			portb_input_reg <= PORTB_input_next;
+			portb_direction_reg <= portb_direction_next;
+			portb_control_reg <= portb_control_next;	
+	
+			irqa_reg <= irqa_next;
+			irqb_reg <= irqb_next;
+	
+			CA1_reg	<= CA1;
+			CA2_reg	<= CA2_in;
+			CB1_reg	<= CB1;
+			CB2_reg	<= CB2_in;
+			
+			CA2_output_reg <= CA2_output_next;
+			CB2_output_reg <= CB2_output_next;
+
+			ca1_edge_reg <= ca1_edge_next;			
+			ca2_edge_reg <= ca2_edge_next;
+			
+			cb1_edge_reg <= cb1_edge_next;			
+			cb2_edge_reg <= cb2_edge_next;			
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>2)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded, porta_output_reg, portb_output_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg)
+	begin
+		porta_output_next <= porta_output_reg;
+		portb_output_next <= portb_output_reg;
+		porta_direction_next <= porta_direction_reg;
+		portb_direction_next <= portb_direction_reg;
+		porta_control_next(5 downto 0) <= porta_control_reg(5 downto 0);
+		portb_control_next(5 downto 0) <= portb_control_reg(5 downto 0);
+		
+		write_ora <= '0';
+		write_orb <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					porta_output_next <= cpu_data_in;
+					write_ora <= '1';
+				else
+					porta_direction_next <= cpu_data_in;
+				end if;
+			end if;	
+
+			if(addr_decoded(1) = '1') then				
+				if (portb_control_reg(2) = '1') then
+					portb_output_next <= cpu_data_in;
+					write_orb <= '1';
+				else
+					portb_direction_next <= cpu_data_in;
+				end if;			
+			end if;						
+
+			if(addr_decoded(2) = '1') then	
+				porta_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;						
+			
+			if(addr_decoded(3) = '1') then		
+				portb_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;															
+
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded, en, porta_input_reg, portb_input_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg, irqa_reg, irqb_reg)
+	begin
+		data_out <= X"FF";
+		read_ora <= '0';
+		read_orb <= '0';
+
+		if (EN = '1') then -- since reads have an effect here...
+			if (addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					data_out <= porta_input_reg;
+					read_ora <= '1';
+				else
+					data_out <= porta_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(1) = '1') then
+				if (portb_control_reg(2) = '1') then
+					data_out <= portb_input_reg;
+					read_orb <= '1';
+				else
+					data_out <= portb_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(2) = '1') then			
+				data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
+			end if;
+
+			if (addr_decoded(3) = '1') then			
+				data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
+			end if;
+		end if;
+		
+	end process;
+	
+	-- irq handing
+	-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
+	process (irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1, CA1_reg, ca2_in, ca2_reg, ca1_edge_reg, ca2_edge_reg)
+	begin
+		irqa_next(1) <= irqa_reg(1) and not(read_ora);
+		irqa_next(0) <= irqa_reg(0) and not(read_ora);
+				
+		ca2_output_next <= ca2_output_reg;
+
+		if (CA1 = '1' and CA1_reg = '0') then
+			irqa_next(1) <= ca1_edge_reg;
+		end if;
+		if (CA1 = '0' and CA1_reg = '1') then
+			irqa_next(1) <= not(ca1_edge_reg);
+		end if;
+		
+		if (CA2_in = '1' and CA2_reg = '0') then
+			irqa_next(0) <= ca2_edge_reg;
+		end if;
+		
+		if (CA2_in = '0' and CA2_reg = '1') then
+			irqa_next(0) <= not(ca2_edge_reg);
+		end if;	
+		
+		ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (porta_control_next(5) = '0') then -- CA2 is an input					
+		else -- CA2 is an output
+			--irqa_next(0) <= '0';
+			
+			case porta_control_next(4 downto 3) is
+				when "10" =>
+					ca2_output_next <= '0'; -- direct control
+				when "11" =>
+					ca2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					else						
+						-- clock restore
+						ca2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					elsif (irqa_reg(1) = '1') then
+						-- ca1 restore
+						ca2_output_next <= '1';	
+					end if;				
+				when others =>
+					-- nop
+			end case;					
+		end if;
+
+	end process;
+
+	process (irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1, CB1_reg, cb2_in, cb2_reg, cb1_edge_reg, cb2_edge_reg)
+	begin
+		irqb_next(1) <= irqb_reg(1) and not(read_orb);
+		irqb_next(0) <= irqb_reg(0) and not(read_orb);
+				
+		cb2_output_next <= cb2_output_reg;
+
+		if (CB1 = '1' and CB1_reg = '0') then
+			irqb_next(1) <= cb1_edge_reg;
+		end if;
+		if (CB1 = '0' and CB1_reg = '1') then
+			irqb_next(1) <= not(cb1_edge_reg);
+		end if;
+		
+		if (CB2_in = '1' and CB2_reg = '0') then
+			irqb_next(0) <= cb2_edge_reg;
+		end if;
+		
+		if (CB2_in = '0' and CB2_reg = '1') then
+			irqb_next(0) <= not(cb2_edge_reg);
+		end if;	
+		
+		cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (portb_control_next(5) = '0') then -- CB2 is an input					
+		else -- CB2 is an output
+			--irqb_next(0) <= '0';
+			
+			case portb_control_next(4 downto 3) is
+				when "10" =>
+					cb2_output_next <= '0'; -- direct control
+				when "11" =>
+					cb2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					else						
+						-- clock restore
+						cb2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					elsif (irqb_reg(1) = '1') then
+						-- cb1 restore
+						cb2_output_next <= '1';	
+					end if;				
+				when others =>
+					--nop
+			end case;					
+		end if;
+
+	end process;
+	
+	-- output
+		-- TODO - review if ca2 and cb2 are push pull or pull up...
+	--ca2 <= CA2_output_reg when porta_control_reg(5) = '1' else 'Z';
+	--cb2 <= CB2_output_reg when portb_control_reg(5) = '1' else 'Z';
+	ca2_out <= CA2_output_reg;
+	ca2_dir_out <= porta_control_reg(5);
+	cb2_out <= CB2_output_reg;
+	cb2_dir_out <= portb_control_reg(5);
+	
+	porta_out <= porta_output_reg;
+	porta_dir_out <= porta_direction_reg;
+	porta_input_next <= porta_in;
+
+	--portb_out <= portb_output_reg;
+	-- forced to 1 when in input mode - star raiders relies on this
+	portb_out(0) <= portb_output_reg(0) when portb_direction_reg(0)='1' else '1';
+	portb_out(1) <= portb_output_reg(1) when portb_direction_reg(1)='1' else '1';
+	portb_out(2) <= portb_output_reg(2) when portb_direction_reg(2)='1' else '1';
+	portb_out(3) <= portb_output_reg(3) when portb_direction_reg(3)='1' else '1';	
+	portb_out(4) <= portb_output_reg(4) when portb_direction_reg(4)='1' else '1';
+	portb_out(5) <= portb_output_reg(5) when portb_direction_reg(5)='1' else '1';
+	portb_out(6) <= portb_output_reg(6) when portb_direction_reg(6)='1' else '1';
+	portb_out(7) <= portb_output_reg(7) when portb_direction_reg(7)='1' else '1';		
+	portb_dir_out <= portb_direction_reg;
+	portb_input_next <= portb_in;
+	
+	irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
+	irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
+	
+end vhdl;
+
+
Index: common/a8core/pokey.vhdl
===================================================================
--- common/a8core/pokey.vhdl	(nonexistent)
+++ common/a8core/pokey.vhdl	(revision 1)
@@ -0,0 +1,1233 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Problem - UART on the DE1 does not have all pins connected. Need to use...
+
+ENTITY pokey IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	--ENABLE_179 :in std_logic;
+	CPU_MEMORY_READY :in std_logic;
+	ANTIC_MEMORY_READY :in std_logic;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	-- keyboard interface
+--	KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
+--	KEY_HELD : IN STD_LOGIC;
+--	SHIFT_PRESSED : IN STD_LOGIC;
+--	BREAK_PRESSED : IN STD_LOGIC;
+--	KEY_INTERRUPT : IN STD_LOGIC;
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	keyboard_response : in std_logic_vector(1 downto 0);
+	
+	-- pots - go high as capacitor charges
+	POT_IN : in std_logic_vector(7 downto 0);
+	
+	-- sio interface
+	SIO_IN1 : IN std_logic;
+	SIO_IN2 : IN std_logic;
+	SIO_IN3 : IN std_logic;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	
+	IRQ_N_OUT : OUT std_logic;
+	
+	SIO_OUT1 : OUT std_logic;
+	SIO_OUT2 : OUT std_logic;
+	SIO_OUT3 : OUT std_logic;
+	
+	SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+	
+	POT_RESET : out std_logic
+);
+END pokey;
+
+ARCHITECTURE vhdl OF pokey IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+
+	component syncreset_enable_divider IS
+	generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		syncreset : in std_logic;
+		reset_n : in std_logic;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_17_9 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC;
+		
+		RAND_OUT : OUT std_logic_vector(7 downto 0)
+	);
+	END component;
+	
+	component poly_5 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_4 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_countdown_timer IS
+	generic(UNDERFLOW_DELAY : natural := 3);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		ENABLE_UNDERFLOW : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		WR_EN : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_noise_filter IS
+	PORT 
+	( 
+		NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+			
+		PULSE_IN : IN STD_LOGIC;
+
+		NOISE_4 : IN STD_LOGIC;
+		NOISE_5 : IN STD_LOGIC;
+		NOISE_LARGE : IN STD_LOGIC;
+		
+		PULSE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_keyboard_scanner is
+	port
+	(
+		clk : in std_logic;
+		reset_n : in std_logic;
+		
+		enable : in std_logic; -- typically hsync or equiv timing
+		keyboard_response : in std_logic_vector(1 downto 0);
+		debounce_disable : in std_logic;
+		scan_enable : in std_logic;
+		
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		
+		shift_pressed : out std_logic;
+		control_pressed : out std_logic;
+		break_pressed : out std_logic;
+		key_held : out std_logic;
+		keycode : out std_logic_vector(5 downto 0);
+		other_key_irq : out std_logic
+	);
+	end component;
+	
+	--signal enable_179 : std_logic;
+	signal enable_64 : std_logic;
+	signal enable_15 : std_logic;
+
+	signal audf0_reg : std_logic_vector(7 downto 0);
+	signal audc0_reg : std_logic_vector(7 downto 0);
+	signal audf1_reg : std_logic_vector(7 downto 0);
+	signal audc1_reg : std_logic_vector(7 downto 0);
+	signal audf2_reg : std_logic_vector(7 downto 0);
+	signal audc2_reg : std_logic_vector(7 downto 0);
+	signal audf3_reg : std_logic_vector(7 downto 0);
+	signal audc3_reg : std_logic_vector(7 downto 0);
+	signal audctl_reg : std_logic_vector(7 downto 0);	
+	signal audf0_next : std_logic_vector(7 downto 0);
+	signal audc0_next : std_logic_vector(7 downto 0);
+	signal audf1_next : std_logic_vector(7 downto 0);
+	signal audc1_next : std_logic_vector(7 downto 0);
+	signal audf2_next : std_logic_vector(7 downto 0);
+	signal audc2_next : std_logic_vector(7 downto 0);
+	signal audf3_next : std_logic_vector(7 downto 0);
+	signal audc3_next : std_logic_vector(7 downto 0);
+	signal audctl_next : std_logic_vector(7 downto 0);
+
+	signal audf0_pulse : std_logic;
+	signal audf1_pulse : std_logic;
+	signal audf2_pulse : std_logic;
+	signal audf3_pulse : std_logic;
+	
+	signal audf0_reload : std_logic;
+	signal audf1_reload : std_logic;
+	signal audf2_reload : std_logic;
+	signal audf3_reload : std_logic;
+	
+	signal stimer_write : std_logic;
+	signal stimer_write_delayed : std_logic;
+	
+	signal audf0_pulse_noise : std_logic;
+	signal audf1_pulse_noise : std_logic;
+	signal audf2_pulse_noise : std_logic;
+	signal audf3_pulse_noise : std_logic;
+	
+	signal audf0_enable : std_logic;
+	signal audf1_enable : std_logic;
+	signal audf2_enable : std_logic;
+	signal audf3_enable : std_logic;
+	
+	signal chan0_output_next : std_logic;
+	signal chan1_output_next : std_logic;
+	signal chan2_output_next : std_logic;
+	signal chan3_output_next : std_logic;
+	signal chan0_output_reg : std_logic;
+	signal chan1_output_reg : std_logic;
+	signal chan2_output_reg : std_logic;
+	signal chan3_output_reg : std_logic;
+	
+	signal highpass0_next : std_logic;
+	signal highpass1_next : std_logic;	
+	signal highpass0_reg : std_logic;
+	signal highpass1_reg : std_logic;
+	
+	signal volume_channel_0_next : std_logic_vector(3 downto 0);
+	signal volume_channel_1_next : std_logic_vector(3 downto 0);
+	signal volume_channel_2_next : std_logic_vector(3 downto 0);
+	signal volume_channel_3_next : std_logic_vector(3 downto 0);
+	signal volume_channel_0_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_1_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_2_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_3_reg : std_logic_vector(3 downto 0);
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal noise_4 : std_logic;
+	signal noise_5 : std_logic;
+	signal noise_large : std_logic;
+	signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
+	
+	signal initmode : std_logic;
+	
+	signal irqen_next : std_logic_vector(7 downto 0);
+	signal irqen_reg : std_logic_vector(7 downto 0);
+
+	signal irqst_next : std_logic_vector(7 downto 0);
+	signal irqst_reg : std_logic_vector(7 downto 0);
+	
+	signal irq_n_next : std_logic;
+	signal irq_n_reg : std_logic; -- for output
+	
+	-- serial ports!
+	signal serial_ip_ready_interrupt : std_logic;
+	signal serial_ip_framing_next : std_logic;
+	signal serial_ip_framing_reg : std_logic;
+	signal serial_ip_overrun_next : std_logic;
+	signal serial_ip_overrun_reg : std_logic;
+	signal serial_op_needed_interrupt : std_logic;
+	
+	signal skctl_next : std_logic_vector(7 downto 0);
+	signal skctl_reg : std_logic_vector(7 downto 0);
+	
+	signal serin_shift_next : std_logic_vector(9 downto 0);
+	signal serin_shift_reg : std_logic_vector(9 downto 0);
+	signal serin_next : std_logic_vector(7 downto 0);
+	signal serin_reg : std_logic_vector(7 downto 0);
+	signal serin_bitcount_next : std_logic_vector(3 downto 0);
+	signal serin_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal sio_in1_reg : std_logic;
+	signal sio_in2_reg : std_logic;
+	signal sio_in3_reg : std_logic;
+	signal sio_in_next : std_logic;
+	signal sio_in_reg : std_logic;
+	
+	signal sio_out_next : std_logic;
+	signal sio_out_reg : std_logic;
+	signal serial_out_next : std_logic;
+	signal serial_out_reg : std_logic;
+	
+	signal serout_shift_next : std_logic_vector(9 downto 0);
+	signal serout_shift_reg : std_logic_vector(9 downto 0);
+	
+	signal serout_holding_full_next : std_logic;
+	signal serout_holding_full_reg : std_logic;
+	signal serout_holding_next : std_logic_vector(7 downto 0);
+	signal serout_holding_reg : std_logic_vector(7 downto 0);
+	signal serout_holding_load : std_logic;
+
+	signal serout_bitcount_next : std_logic_vector(3 downto 0);
+	signal serout_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal serout_active_next : std_logic;
+	signal serout_active_reg : std_logic;
+	
+	signal serial_reset : std_logic;
+	signal serout_sync_reset : std_logic;
+	signal skrest_write : std_logic;
+	
+	signal serout_enable : std_logic;
+	signal serout_enable_delayed : std_logic;
+	signal serin_enable : std_logic;
+	
+	signal async_serial_reset : std_logic;
+	signal waiting_for_start_bit : std_logic;
+	
+	signal serin_clock_next : std_logic;
+	signal serin_clock_reg : std_logic;
+	signal serin_clock_last_next : std_logic;
+	signal serin_clock_last_reg : std_logic;
+
+	signal serout_clock_next : std_logic;
+	signal serout_clock_reg : std_logic;
+	signal serout_clock_last_next : std_logic;
+	signal serout_clock_last_reg : std_logic;
+	
+	signal twotone_reset : std_logic;
+	signal twotone_next : std_logic;
+	signal twotone_reg : std_logic;
+	
+	signal clock_next : std_logic;
+	signal clock_reg : std_logic;
+	signal clock_sync_next : std_logic;
+	signal clock_sync_reg : std_logic;
+	signal clock_input : std_logic;
+	
+	-- keyboard
+	signal keyboard_overrun_next : std_logic;
+	signal keyboard_overrun_reg : std_logic;
+	
+	signal shift_pressed : std_logic;
+	signal control_pressed : std_logic;
+	signal break_pressed : std_logic;
+	signal key_held : std_logic;
+	signal other_key_irq : std_logic;
+	
+	signal kbcode : std_logic_vector(5 downto 0);
+	
+	-- pots
+	signal pot0_next : std_logic_vector(7 downto 0);
+	signal pot0_reg : std_logic_vector(7 downto 0);
+	signal pot1_next : std_logic_vector(7 downto 0);
+	signal pot1_reg : std_logic_vector(7 downto 0);
+	signal pot2_next : std_logic_vector(7 downto 0);
+	signal pot2_reg : std_logic_vector(7 downto 0);
+	signal pot3_next : std_logic_vector(7 downto 0);
+	signal pot3_reg : std_logic_vector(7 downto 0);
+	signal pot4_next : std_logic_vector(7 downto 0);
+	signal pot4_reg : std_logic_vector(7 downto 0);
+	signal pot5_next : std_logic_vector(7 downto 0);
+	signal pot5_reg : std_logic_vector(7 downto 0);	
+	signal pot6_next : std_logic_vector(7 downto 0);
+	signal pot6_reg : std_logic_vector(7 downto 0);
+	signal pot7_next : std_logic_vector(7 downto 0);
+	signal pot7_reg : std_logic_vector(7 downto 0);	
+	
+	signal pot_counter_next : std_logic_vector(7 downto 0);
+	signal pot_counter_reg : std_logic_vector(7 downto 0);
+	
+	signal potgo_write : std_logic;
+	
+	signal pot_reset_next : std_logic;
+	signal pot_reset_reg : std_logic;
+	
+	signal enable_179 : std_logic;
+BEGIN
+	--HACK FIXME TODO
+	enable_179 <= cpu_MEMORY_READY or antIC_MEMORY_READY;
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
+			audf0_reg <= X"00";
+			audc0_reg <= X"00";
+			audf1_reg <= X"00";
+			audc1_reg <= X"00";
+			audf2_reg <= X"00";
+			audc2_reg <= X"00";
+			audf3_reg <= X"00";
+			audc3_reg <= X"00";
+			audctl_reg <= X"00";
+			
+			irqen_reg <= X"00";
+			irqst_reg <= X"FF";
+			irq_n_reg <= '1';
+			
+			skctl_reg <= X"00";
+			
+			highpass0_reg <= '0';
+			highpass1_reg <= '0';
+			
+			chan0_output_reg <= '0';
+			chan1_output_reg <= '0';
+			chan2_output_reg <= '0';
+			chan3_output_reg <= '0';
+			
+			volume_channel_0_reg <= (others=>'0');
+			volume_channel_1_reg <= (others=>'0');
+			volume_channel_2_reg <= (others=>'0');
+			volume_channel_3_reg <= (others=>'0');
+			
+			serin_reg <= (others=>'0');
+			serin_shift_reg <= (others=>'0');
+			serin_bitcount_reg <= (others=>'0');
+			serout_shift_reg <= (others=>'0');
+			serout_holding_reg <= (others=>'0');
+			serout_holding_full_reg <= '0';
+			serout_active_reg <= '0';		
+			sio_out_reg <= '1';
+			serial_out_reg <= '1';
+			
+			serial_ip_framing_reg <= '0';
+			serial_ip_overrun_reg <= '0';
+			
+			clock_reg <= '0';
+			clock_sync_reg <= '0';
+	
+			keyboard_overrun_reg <= '0';
+			
+			serin_clock_reg <= '0';
+			serin_clock_last_reg <= '0';
+			serout_clock_reg <= '0';
+			serout_clock_last_reg <= '0';
+			
+			twotone_reg <= '0';
+			
+			sio_in_reg <= '0';
+			
+			pot0_reg <= (others=>'0');
+			pot1_reg <= (others=>'0');
+			pot2_reg <= (others=>'0');
+			pot3_reg <= (others=>'0');
+			pot4_reg <= (others=>'0');
+			pot5_reg <= (others=>'0');
+			pot6_reg <= (others=>'0');
+			pot7_reg <= (others=>'0');
+			
+			pot_counter_reg <= (others=>'0');
+			
+			pot_reset_reg <= '1';
+			
+		elsif (clk'event and clk='1') then			
+			audf0_reg <= audf0_next;
+			audc0_reg <= audc0_next;
+			audf1_reg <= audf1_next;
+			audc1_reg <= audc1_next;
+			audf2_reg <= audf2_next;
+			audc2_reg <= audc2_next;
+			audf3_reg <= audf3_next;
+			audc3_reg <= audc3_next;
+			audctl_reg <= audctl_next;
+			
+			irqen_reg <= irqen_next;
+			irqst_reg <= irqst_next;
+			irq_n_reg <= irq_n_next;
+			
+			skctl_reg <= skctl_next;
+			
+			highpass0_reg <= highpass0_next;
+			highpass1_reg <= highpass1_next;
+			
+			chan0_output_reg <= chan0_output_next;
+			chan1_output_reg <= chan1_output_next;
+			chan2_output_reg <= chan2_output_next;
+			chan3_output_reg <= chan3_output_next;
+			
+			volume_channel_0_reg<= volume_channel_0_next;
+			volume_channel_1_reg<= volume_channel_1_next;
+			volume_channel_2_reg<= volume_channel_2_next;
+			volume_channel_3_reg<= volume_channel_3_next;
+			
+			serin_reg <= serin_next;
+			serin_shift_reg <= serin_shift_next;
+			serin_bitcount_reg <= serin_bitcount_next;
+			serout_shift_reg <= serout_shift_next;
+			serout_bitcount_reg <= serout_bitcount_next;
+			
+			serout_holding_reg<=serout_holding_next;
+			serout_holding_full_reg<=serout_holding_full_next;
+			serout_active_reg <= serout_active_next;
+			
+			sio_out_reg <= sio_out_next;
+			serial_out_reg <= serial_out_next;
+			
+			serial_ip_framing_reg <= serial_ip_framing_next;
+			serial_ip_overrun_reg <= serial_ip_overrun_next;
+			
+			clock_reg <= clock_next;
+			clock_sync_reg <= clock_sync_next;
+			
+			keyboard_overrun_reg <= keyboard_overrun_next;
+			
+			serin_clock_reg <= serin_clock_next;
+			serin_clock_last_reg <= serin_clock_last_next;
+			serout_clock_reg <= serout_clock_next;
+			serout_clock_last_reg <= serout_clock_last_next;
+			
+			twotone_reg <= twotone_next;
+			
+			sio_in_reg <= sio_in_next;
+			
+			pot0_reg <= pot0_next;
+			pot1_reg <= pot1_next;
+			pot2_reg <= pot2_next;
+			pot3_reg <= pot3_next;
+			pot4_reg <= pot4_next;
+			pot5_reg <= pot5_next;
+			pot6_reg <= pot6_next;
+			pot7_reg <= pot7_next;
+			
+			pot_counter_reg <= pot_counter_next;
+			
+			pot_reset_reg <= pot_reset_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+	
+	-- clock selection
+	process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
+	begin
+		audf0_enable <= enable_64;
+		audf1_enable <= enable_64;
+		audf2_enable <= enable_64;
+		audf3_enable <= enable_64;		
+		
+		if (audctl_reg(0) = '1') then
+			audf0_enable <= enable_15;
+			audf1_enable <= enable_15;
+			audf2_enable <= enable_15;
+			audf3_enable <= enable_15;
+		end if;
+
+		if (audctl_reg(6) = '1') then
+			audf0_enable <= enable_179;
+		end if;
+		
+		if (audctl_reg(5) = '1') then
+			audf2_enable <= enable_179;
+		end if;
+		
+		if(audctl_reg(4) = '1') then
+			audf1_enable <= audf0_pulse;
+		end if;
+		
+		if(audctl_reg(3) = '1') then
+			audf3_enable <= audf2_pulse;
+		end if;
+	end process;
+	
+	-- Instantiate timers
+	timer0 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
+	timer1 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
+	timer2 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
+	timer3 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);		
+		
+	-- Timer reloading
+	process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
+	begin
+		audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
+		audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
+		audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
+		audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
+	end process;
+	
+	-- Writes to registers
+	process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
+	begin
+		audf0_next <= audf0_reg;
+		audc0_next <= audc0_reg;
+		audf1_next <= audf1_reg;
+		audc1_next <= audc1_reg;
+		audf2_next <= audf2_reg;
+		audc2_next <= audc2_reg;
+		audf3_next <= audf3_reg;
+		audc3_next <= audc3_reg;
+		audctl_next <= audctl_reg;		
+		
+		irqen_next <= irqen_reg;
+		skctl_next <= skctl_reg;
+		
+		stimer_write <= '0';
+		
+		serout_holding_load <= '0';
+		serout_holding_next <= serout_holding_reg;
+		
+		serial_reset <= '0';
+		skrest_write <= '0';
+		potgo_write <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				audf0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(1) = '1') then
+				audc0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(2) = '1') then
+				audf1_next <= data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				audc1_next <= data_in;
+			end if;
+			
+			if(addr_decoded(4) = '1') then
+				audf2_next <= data_in;
+			end if;
+
+			if(addr_decoded(5) = '1') then
+				audc2_next <= data_in;
+			end if;
+			
+			if(addr_decoded(6) = '1') then
+				audf3_next <= data_in;
+			end if;		
+
+			if(addr_decoded(7) = '1') then
+				audc3_next <= data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				audctl_next <= data_in;
+			end if;
+			
+			if (addr_decoded(9) = '1') then --STIMER
+				stimer_write <= '1';
+			end if;
+			
+			if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
+				skrest_write <= '1';
+			end if;
+
+			if (addr_decoded(11) = '1') then -- POTGO - start POT scan
+				potgo_write <= '1';
+			end if;
+			
+			if (addr_decoded(13) = '1') then --SEROUT								
+				serout_holding_next <= data_in;
+				serout_holding_load <= '1';
+			end if;
+			
+			if (addr_decoded(14) = '1') then --IRQEN
+				irqen_next <= data_in;
+			end if;
+
+			if (addr_decoded(15) = '1') then --SKCTL
+				skctl_next <= data_in;
+				
+				if (data_in(6 downto 4)="000") then
+					serial_reset <= '1';
+				end if;
+			end if;	
+	
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin
+		data_out <= X"FF";
+
+		if(addr_decoded(0) = '1') then --POT0
+			data_out <= pot0_reg;
+		end if;
+
+		if(addr_decoded(1) = '1') then --POT1
+			data_out <= pot1_reg;
+		end if;
+
+		if(addr_decoded(2) = '1') then --POT2
+			data_out <= pot2_reg;
+		end if;
+
+		if(addr_decoded(3) = '1') then --POT3
+			data_out <= pot3_reg;
+		end if;
+		
+		if(addr_decoded(4) = '1') then --POT4
+			data_out <= pot4_reg;
+		end if;
+
+		if(addr_decoded(5) = '1') then --POT5
+			data_out <= pot5_reg;
+		end if;
+
+		if(addr_decoded(6) = '1') then --POT6
+			data_out <= pot6_reg;
+		end if;
+
+		if(addr_decoded(7) = '1') then --POT7
+			data_out <= pot7_reg;
+		end if;
+
+		if(addr_decoded(8) = '1') then --ALLPOT
+			data_out <= not(pot_in);
+		end if;
+		
+		if(addr_decoded(9) = '1') then --KBCODE
+			data_out <= control_pressed&shift_pressed&kbcode;
+		end if;
+		
+		if(addr_decoded(10) = '1') then -- RANDOM
+			data_out <= RAND_OUT;
+		end if;
+
+		if (addr_decoded(13) = '1') then --SERIN			
+			data_out <= serin_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
+			data_out <= IRQST_REG;
+			--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
+		end if;		
+
+		if (addr_decoded(15) = '1') then --SKSTAT
+			data_out <= not(serial_ip_framing_reg)&not(keyboard_overrun_reg)&not(serial_ip_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
+		end if;		
+		
+	end process;
+	
+	-- Fire interrupts
+	process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
+	begin
+		-- clear interrupts
+		irqst_next <= irqst_reg or not(irqen_reg);
+				
+		irq_n_next <= '0';
+
+		if ((irqst_reg or "0000"&not(irqen_reg(3))&"000") = X"FF") then
+			irq_n_next <= '1';
+		end if;
+	
+		-- set interrupts
+		if (audf0_pulse = '1') then
+			irqst_next(0) <= not(irqen_reg(0));
+		end if;
+
+		if (audf1_pulse = '1') then
+			irqst_next(1) <= not(irqen_reg(1));
+		end if;
+
+		if (audf3_pulse = '1') then
+			irqst_next(2) <= not(irqen_reg(2));
+		end if;
+		
+		if (other_key_irq = '1') then
+			irqst_next(6) <= not(irqen_reg(6));			
+		end if;
+		
+		if (break_pressed = '1') then
+			irqst_next(7) <= not(irqen_reg(7));			
+		end if;		
+	
+		if (serial_ip_ready_interrupt = '1') then
+			irqst_next(5) <= not(irqen_reg(5));
+		end if;
+		
+		irqst_next(3) <= serout_active_reg;
+		
+		if (serial_op_needed_interrupt = '1') then
+			irqst_next(4) <= not(irqen_reg(4));
+		end if;
+		
+	end process;
+	
+	-- Instantiate delay for stimer reload_request
+	stimer_delay : delay_line
+		generic map (count=>3)
+		port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
+		
+	--stimer_write_delayed <= stimer_write;
+	
+	-- Instantiate audio noise filters
+	pokey_noise_filter0 : pokey_noise_filter
+		port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter1 : pokey_noise_filter
+		port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter2 : pokey_noise_filter
+		port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter3 : pokey_noise_filter
+		port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	
+	-- Audio output stage
+	process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
+	begin
+		chan0_output_next <= chan0_output_reg;
+		chan1_output_next <= chan1_output_reg;
+		chan2_output_next <= chan2_output_reg;
+		chan3_output_next <= chan3_output_reg;
+		
+		if (audf0_pulse_noise = '1') then
+			chan0_output_next <= not(chan0_output_reg);
+		end if;
+		
+		if (audf1_pulse_noise = '1') then
+			chan1_output_next <= not(chan1_output_reg);
+		end if;
+		
+		if (audf2_pulse_noise = '1') then
+			chan2_output_next <= not(chan2_output_reg);
+		end if;
+		
+		if (audf3_pulse_noise = '1') then
+			chan3_output_next <= not(chan3_output_reg);
+		end if;
+	end process;
+	
+	-- High pass filters
+	process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
+	begin
+		highpass0_next <= highpass0_reg;
+		highpass1_next <= highpass1_reg;
+		
+		if (audctl_reg(2) = '1') then
+			if (audf2_pulse = '1') then
+				highpass0_next <= chan0_output_reg;
+			end if;
+		else
+			highpass0_next <= '1';
+		end if;
+		
+		if (audctl_reg(1) = '1') then
+			if (audf3_pulse = '1') then
+				highpass1_next <= chan1_output_reg;
+			end if;
+		else
+			highpass1_next <= '1';
+		end if;
+		
+	end process;
+	
+	-- Instantiate key pokey clocks
+	-- ~1.79MHz - from 25MHz/14
+	-- ~64KHz - from 1.79MHz/28
+	-- ~15KHz - from 1.79MHz/114
+	--enable_179_div : enable_divider
+	--	generic map (COUNT=>14)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);		
+		
+	-- resetcount 6/33
+	enable_64_div : syncreset_enable_divider
+		generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
+		
+	enable_15_div : syncreset_enable_divider
+		generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
+		
+	-- Instantiate pokey noise circuits (lfsr)
+	initmode <= skctl_next(1) nor skctl_next(0);
+	poly_17_19_lfsr : poly_17_9
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
+		
+	poly_5_lfsr : poly_5
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
+		
+	poly_4_lfsr : poly_4
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
+	
+	--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
+	process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
+	begin
+		volume_channel_0_next <= "0000";
+		volume_channel_1_next <= "0000";
+		volume_channel_2_next <= "0000";
+		volume_channel_3_next <= "0000";
+			
+		if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
+			volume_channel_0_next <= audc0_reg(3 downto 0);
+		end if;
+		
+		if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
+			volume_channel_1_next <= audc1_reg(3 downto 0);
+		end if;
+		
+		if ((chan2_output_reg or audc2_reg(4)) = '1') then
+			volume_channel_2_next <= audc2_reg(3 downto 0);
+		end if;
+		
+		if ((chan3_output_reg or audc3_reg(4)) = '1') then
+			volume_channel_3_next <= audc3_reg(3 downto 0);
+		end if;
+		
+	end process;
+	
+	-- serial port output	
+	-- urghhh
+        serout_sync_reset <= serial_reset or stimer_write_delayed;
+	serout_clock_delay : delay_line
+		generic map (count=>2)
+		port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+		
+	
+	process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
+	begin
+		serout_clock_next <= serout_clock_reg;
+		serout_clock_last_next <= serout_clock_reg;
+	
+		serout_shift_next <= serout_shift_reg;
+		serout_bitcount_next <= serout_bitcount_reg;
+		serout_holding_full_next <= serout_holding_full_reg;
+		serout_active_next <= serout_active_reg;
+		
+		serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
+		sio_out_next <= serial_out_reg;		
+	
+		-- two tone output
+		twotone_next <= twotone_reg;
+		twotone_reset <= '0';
+		
+		if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
+			twotone_next <= not(twotone_reg);
+			twotone_reset <= skctl_reg(3);
+		end if;
+		
+		if (skctl_reg(3) = '1') then
+			sio_out_next <= twotone_reg;
+		end if;
+	
+		-- force break
+		if (skctl_reg(7) = '1') then
+			sio_out_next <= '0';
+		end if;
+		
+		serial_op_needed_interrupt <= '0';		
+		
+		-- generate clock from enable signals
+		if (serout_enable_delayed = '1') then
+			serout_clock_next <= not(serout_clock_reg);
+		end if;
+		
+		-- output bits over sio
+		if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then			
+			serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
+			serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
+				
+			-- reload			
+			if (serout_bitcount_reg = X"0") then
+				if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
+					serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
+					serout_shift_next <= '1'&serout_holding_reg&'0';
+					serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
+					serout_holding_full_next <= '0';					
+					serial_op_needed_interrupt <= '1'; -- more data please!
+					serout_active_next <= '1';
+				else
+					serout_active_next <= '0';
+					serial_out_next <= '1'; -- remove blip! 
+				end if;
+			else
+				serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
+			end if;
+		end if;
+		
+		-- register to load has been written too, update our state to reflect that it is full
+		if (serout_holding_load = '1') then
+			serout_holding_full_next <= '1';
+		end if;
+		
+		if (serial_reset = '1') then
+			twotone_next <= '0';
+			serout_bitcount_next <= (others=>'0');
+			serout_shift_next <= (others=>'0');
+			serout_holding_full_next <= '0';
+			serout_clock_next <= '0';
+			serout_clock_last_next <= '0';
+			serout_active_next <= '0';
+		end if;
+	end process;
+	
+	-- serial port input
+	sio_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);	
+	sio_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);	
+	sio_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);	
+	sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
+		
+	waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
+	process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
+	begin
+		serin_clock_next <= serin_clock_reg;
+		serin_clock_last_next <= serin_clock_reg;
+	
+		serin_shift_next <= serin_shift_reg;
+		serin_bitcount_next <= serin_bitcount_reg;
+		serin_next <= serin_reg;
+		
+		serial_ip_overrun_next <= serial_ip_overrun_reg;
+		serial_ip_framing_next <= serial_ip_framing_reg;
+		serial_ip_ready_interrupt <= '0';
+		
+		async_serial_reset <= '0';
+		
+		-- generate clock from enable signals
+		if (serin_enable = '1') then
+			serin_clock_next <= not(serin_clock_reg);
+		end if;
+		
+		-- resync clock on receipt of start bit
+		if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
+			async_serial_reset <= '1';
+			serin_clock_next <= '1';
+		end if;
+		
+		-- receive bits into shift reg		
+		if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge					
+			if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then				
+				serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
+			
+				if (serin_bitcount_reg = X"0") then -- full byte
+					serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
+					
+					serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
+					
+					-- irq to alert new data avilable
+					serial_ip_ready_interrupt <= '1';
+					
+					-- flag up overrun
+					if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
+						serial_ip_overrun_next <= '1';
+					end if;				
+					
+					-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
+					if (sio_in_reg='0') then
+						serial_ip_framing_next <= '1';
+					end if;
+				else			
+					serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
+				end if;
+			end if;
+		end if;
+		
+		if (skrest_write = '1') then
+			serial_ip_overrun_next <= '0';
+			serial_ip_framing_next <= '0';
+		end if;
+		
+		if (serial_reset = '1') then
+			serin_clock_next <= '0';
+			serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
+			serin_shift_next <= (others=>'0');			
+		end if;		
+	end process;
+	
+	-- serial clocks
+	process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
+	begin
+		clock_next <= sio_clock;
+		clock_sync_next <= clock_reg;
+	
+		serout_enable <= '0';
+		serin_enable <= '0';
+		clock_input <= '1'; -- when output, outputs channel 4
+		
+		case skctl_reg(6 downto 4) is
+			when "000" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "001" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "010" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+				clock_input <= '0';
+			when "011" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "100" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= audf3_pulse;
+			when "101" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "110" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+				clock_input <= '0';
+			when "111" =>			
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+			when others =>
+				-- nop
+		end case;
+	end process;
+	
+	-- keyboard overrun (i.e. second key pressed before interrupt cleared)
+	process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
+	begin
+		keyboard_overrun_next <= keyboard_overrun_reg;
+		
+		if (other_key_irq='1' and irqst_reg(6)='0') then
+			keyboard_overrun_next <= '1';
+		end if;
+		
+		if (skrest_write = '1') then
+			keyboard_overrun_next <= '0';
+		end if;
+	end process;
+	
+	-- keyboard scan
+	pokey_keyboard_scanner1 : pokey_keyboard_scanner
+		port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);	
+	
+	-- POT scan
+	process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin	
+		pot0_next <= pot0_reg;
+		pot1_next <= pot1_reg;
+		pot2_next <= pot2_reg;
+		pot3_next <= pot3_reg;
+		pot4_next <= pot4_reg;
+		pot5_next <= pot5_reg;
+		pot6_next <= pot6_reg;
+		pot7_next <= pot7_reg;
+		
+		pot_reset_next <= pot_reset_reg;
+		
+		pot_counter_next <= pot_counter_reg;
+		
+		if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
+			pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
+			if (pot_counter_reg = X"E4") then
+				pot_reset_next <= '1'; -- turn on pot dump transistors
+			end if;
+			
+			if (pot_reset_reg = '0') then
+				if (pot_in(0) = '0') then -- pot now high, latch
+					pot0_next <= pot_counter_reg;
+				end if;
+				if (pot_in(1) = '0') then -- pot now high, latch
+					pot1_next <= pot_counter_reg;
+				end if;				
+				if (pot_in(2) = '0') then -- pot now high, latch
+					pot2_next <= pot_counter_reg;
+				end if;
+				if (pot_in(3) = '0') then -- pot now high, latch
+					pot3_next <= pot_counter_reg;
+				end if;
+				if (pot_in(4) = '0') then -- pot now high, latch
+					pot4_next <= pot_counter_reg;
+				end if;
+				if (pot_in(5) = '0') then -- pot now high, latch
+					pot5_next <= pot_counter_reg;
+				end if;
+				if (pot_in(6) = '0') then -- pot now high, latch
+					pot6_next <= pot_counter_reg;
+				end if;
+				if (pot_in(7) = '0') then -- pot now high, latch
+					pot7_next <= pot_counter_reg;
+				end if;
+			end if;			
+		end if;
+			
+		if (potgo_write = '1') then
+			pot_counter_next <= (others=>'0');
+			pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
+		end if;		
+	end process;
+	
+	-- Outputs
+	irq_n_out <= irq_n_reg;	
+	
+	CHANNEL_0_OUT <= volume_channel_0_reg;
+	CHANNEL_1_OUT <= volume_channel_1_reg;
+	CHANNEL_2_OUT <= volume_channel_2_reg;
+	CHANNEL_3_OUT <= volume_channel_3_reg;
+	
+	sio_out1 <= sio_out_reg;	
+	sio_out2 <= sio_out_reg;	
+	sio_out3 <= sio_out_reg;	
+	
+	sio_clock <= audf3_pulse when clock_input='0' else 'Z';
+	
+	pot_reset <= pot_reset_reg;
+		
+END vhdl;
+
+
Index: common/a8core/pokey_mixer.vhdl
===================================================================
--- common/a8core/pokey_mixer.vhdl	(nonexistent)
+++ common/a8core/pokey_mixer.vhdl	(revision 1)
@@ -0,0 +1,249 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_mixer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
+		
+	CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	GTIA_SOUND : IN STD_LOGIC;
+
+	COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+	COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+);
+END pokey_mixer;
+
+ARCHITECTURE vhdl OF pokey_mixer IS
+	signal volume_reg : std_logic_vector(15 downto 0);
+	signal volume_next : std_logic_vector(15 downto 0);
+	signal volume_next_real : std_logic_vector(15 downto 0);	
+	
+	signal volume_sum : std_logic_vector(5 downto 0);
+	
+	signal channel_0_en : std_logic_vector(3 downto 0);
+	signal channel_1_en : std_logic_vector(3 downto 0);
+	signal channel_2_en : std_logic_vector(3 downto 0);
+	signal channel_3_en : std_logic_vector(3 downto 0);
+	
+	signal gtia_en : std_logic_vector(15 downto 0);
+BEGIN
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			volume_reg <= volume_next_real;
+		end if;
+	end process;
+	
+	-- next state
+	process(channel_enable,channel_0,channel_1,channel_2,channel_3)
+	begin
+		channel_0_en <= channel_0;
+		channel_1_en <= channel_1;
+		channel_2_en <= channel_2;
+		channel_3_en <= channel_3;
+	
+--		if (channel_enable(3)='0') then
+--			channel_0_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(2)='0') then
+--			channel_1_en <= X"0";
+--		end if;
+--
+--		if (channel_enable(1)='0') then
+--			channel_2_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(0)='0') then
+--			channel_3_en <= X"0";
+--		end if;
+	end process;
+	
+	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_en)
+	begin
+		volume_sum <= 
+			std_logic_vector
+			(
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_0_en)
+						+ unsigned('0'&CHANNEL_1_en)
+					)) 
+					+ 
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_2_en) + 
+						unsigned('0'&CHANNEL_3_en)
+					))
+			);
+	end process;
+	
+	gtia_en(15 downto 13) <= (others=>'0');
+	gtia_en(12) <= gtia_sound;
+	gtia_en(11 downto 0) <= (others=>'0');
+ 	process (volume_sum, volume_next, gtia_en, covOX_CHANNEL_0,covOX_CHANNEL_1)
+	begin
+		case volume_sum is 
+			when "000000" =>
+				volume_next <= X"0000";
+			when "000001" =>
+				volume_next <= X"05e4";
+			when "000010" =>
+				volume_next <= X"0b90";
+			when "000011" =>
+				volume_next <= X"1107";
+			when "000100" =>
+				volume_next <= X"1649";
+			when "000101" =>
+				volume_next <= X"1b57";
+			when "000110" =>
+				volume_next <= X"2032";
+			when "000111" =>
+				volume_next <= X"24db";
+			when "001000" =>
+				volume_next <= X"2954";
+			when "001001" =>
+				volume_next <= X"2d9d";
+			when "001010" =>
+				volume_next <= X"31b8";
+			when "001011" =>
+				volume_next <= X"35a6";
+			when "001100" =>
+				volume_next <= X"3968";
+			when "001101" =>
+				volume_next <= X"3cff";
+			when "001110" =>
+				volume_next <= X"406b";
+			when "001111" =>
+				volume_next <= X"43af";
+			when "010000" =>
+				volume_next <= X"46cc";
+			when "010001" =>
+				volume_next <= X"49c2";
+			when "010010" =>
+				volume_next <= X"4c92";
+			when "010011" =>
+				volume_next <= X"4f3e";
+			when "010100" =>
+				volume_next <= X"51c7";
+			when "010101" =>
+				volume_next <= X"542d";
+			when "010110" =>
+				volume_next <= X"5673";
+			when "010111" =>
+				volume_next <= X"5898";
+			when "011000" =>
+				volume_next <= X"5a9f";
+			when "011001" =>
+				volume_next <= X"5c88";
+			when "011010" =>
+				volume_next <= X"5e55";
+			when "011011" =>
+				volume_next <= X"6006";
+			when "011100" =>
+				volume_next <= X"619d";
+			when "011101" =>
+				volume_next <= X"631a";
+			when "011110" =>
+				volume_next <= X"647f";
+			when "011111" =>
+				volume_next <= X"65ce";
+			when "100000" =>
+				volume_next <= X"6706";
+			when "100001" =>
+				volume_next <= X"682a";
+			when "100010" =>
+				volume_next <= X"6939";
+			when "100011" =>
+				volume_next <= X"6a37";
+			when "100100" =>
+				volume_next <= X"6b22";
+			when "100101" =>
+				volume_next <= X"6bfe";
+			when "100110" =>
+				volume_next <= X"6cca";
+			when "100111" =>
+				volume_next <= X"6d88";
+			when "101000" =>
+				volume_next <= X"6e38";
+			when "101001" =>
+				volume_next <= X"6edd";
+			when "101010" =>
+				volume_next <= X"6f77";
+			when "101011" =>
+				volume_next <= X"7008";
+			when "101100" =>
+				volume_next <= X"708f";
+			when "101101" =>
+				volume_next <= X"710f";
+			when "101110" =>
+				volume_next <= X"7189";
+			when "101111" =>
+				volume_next <= X"71fe";
+			when "110000" =>
+				volume_next <= X"726e";
+			when "110001" =>
+				volume_next <= X"72db";
+			when "110010" =>
+				volume_next <= X"7347";
+			when "110011" =>
+				volume_next <= X"73b1";
+			when "110100" =>
+				volume_next <= X"741c";
+			when "110101" =>
+				volume_next <= X"7488";
+			when "110110" =>
+				volume_next <= X"74f6";
+			when "110111" =>
+				volume_next <= X"7568";
+			when "111000" =>
+				volume_next <= X"75df";
+			when "111001" =>
+				volume_next <= X"765c";
+			when "111010" =>
+				volume_next <= X"76df";
+			when "111011" =>
+				volume_next <= X"776b";
+			when "111100" =>
+				volume_next <= X"7800";				
+			when others =>
+				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+		end case;
+		
+--		volume_next_real <= std_LOGIC_vector(
+--			(unsigned('0'&volume_next(15 downto 1)) 
+--			+ unsigned(gtia_en)) 
+--			+ (unsigned("00"&covox_CHANNEL_0) 
+--			+ unsigned("00"&covox_CHANNEL_1)));
+		
+		--volume_next_real <= '0'&volume_next(15 downto 1);
+		
+		volume_next_real <= std_LOGIC_vector(
+			(unsigned("00"&volume_next(15 downto 2)) 
+			+ unsigned(gtia_en)) 		
+			+ (unsigned("000"&covox_CHANNEL_0&"00000") 
+			+ unsigned("000"&covox_CHANNEL_1&"00000")));
+		
+	end process;
+			
+	-- output
+	-- TODO
+	volume_out <= volume_reg;
+		
+END vhdl;
\ No newline at end of file
Index: common/a8core/poly_17_9.vhdl
===================================================================
--- common/a8core/poly_17_9.vhdl	(nonexistent)
+++ common/a8core/poly_17_9.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_17_9 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC;
+	
+	RAND_OUT : OUT std_logic_vector(7 downto 0)
+);
+END poly_17_9;
+
+ARCHITECTURE vhdl OF poly_17_9 IS
+	signal shift_reg: std_logic_vector(16 downto 0);
+	signal shift_next: std_logic_vector(16 downto 0);
+	
+	signal feedback : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010101010101010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state (as pokey decap)
+	feedback <= shift_reg(13) xnor shift_reg(8);
+	process(enable,shift_reg,feedback,select_9_17,init)
+	begin
+		shift_next <= shift_reg;
+		
+		if (enable = '1') then	
+			shift_next(15 downto 8) <= shift_reg(16 downto 9);	
+			shift_next(7) <= feedback;
+			shift_next(6 downto 0) <= shift_reg(7 downto 1);
+
+			shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
+		end if;
+	end process;
+	
+		-- output
+	bit_out <= shift_reg(9);
+	RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
+		
+END vhdl;
Index: common/a8core/poly_5.vhdl
===================================================================
--- common/a8core/poly_5.vhdl	(nonexistent)
+++ common/a8core/poly_5.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_5 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_5;
+
+ARCHITECTURE vhdl OF poly_5 IS
+	signal shift_reg: std_logic_vector(4 downto 0);
+	signal shift_next: std_logic_vector(4 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: common/a8core/shared_enable.vhdl
===================================================================
--- common/a8core/shared_enable.vhdl	(nonexistent)
+++ common/a8core/shared_enable.vhdl	(revision 1)
@@ -0,0 +1,166 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY shared_enable IS
+GENERIC
+(
+	cycle_length : integer := 16; -- or 32...
+)
+PORT 
+( 
+	CLK : IN STD_LOGIC;	
+	RESET_N : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	MEMORY_READY_ANTIC : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	PAUSE_6502 : in std_logic;
+	THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
+
+	POKEY_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same
+	ANTIC_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same - 1 cycle early
+	oldcpu_enable : OUT STD_LOGIC;     -- always about 1.79MHz to keep sound the same - expanded to next ready
+	CPU_ENABLE_OUT : OUT STD_LOGIC;    -- for compatibility run at 1.79MHz, for speed run as fast as we can
+	
+	SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC; -- double antic's rate - due to high-res mode
+	SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC -- four times antic's rate - due to high-res mode
+	
+	-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by 31 cycles vs CPU_ENABLE (when in 1.79MHz mode)
+	-- XXX watch out on clock speed change from 56MHz!
+);
+END shared_enable;
+
+ARCHITECTURE vhdl OF shared_enable IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;		
+	
+	signal enable_179 : std_logic;
+	signal enable_179_early : std_logic;
+	signal enable_179_late : std_logic;
+	signal cpu_enable : std_logic;
+	
+	signal cpu_extra_enable_next : std_logic;
+	signal cpu_extra_enable_reg : std_logic;
+	
+	signal turbo_next : std_logic;
+	signal turbo_reg : std_logic;	
+
+	signal throttle_count_next : std_logic_vector(5 downto 0);
+	signal throttle_count_reg : std_logic_vector(5 downto 0);	
+	
+	-- TODO - clean up
+	signal oldcpu_extra_enable_next : std_logic;
+	signal oldcpu_extra_enable_reg : std_logic;
+	signal enable_179_expanded : std_logic;
+	
+	signal memory_ready : std_logic;
+begin
+	-- instantiate some clock calcs
+	-- TODO - scandouble clocks assume 58MHz...
+	SCANDOUBLER_ENABLE_HIGH <= '1';
+		
+	sl_enable_colour_clock_div : enable_divider
+		generic map (COUNT=>2)
+		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
+
+	enable_179_clock_div : enable_divider
+		generic map (COUNT=>cycle_length)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
+		
+	process(THROTTLE_COUNT_6502, throttle_count_reg, enable_179)
+	begin
+		turbo_next <= '0';
+		throttle_count_next <= std_logic_vector(unsigned(throttle_count_reg) + 1);
+
+		--011111/31/1f = run every 32 cycles
+		
+		if (throttle_count_reg = THROTTLE_COUNT_6502) then
+			throttle_count_next <= (others=>'0');
+			turbo_next <= '1';
+		end if;
+		
+		if (enable_179 = '1') then -- synchronize
+			throttle_count_next <= "000001";
+		end if;
+		--0000000000111111111122222222223333
+		--0123456789012345678901234567890123
+		--X-------------------------------X
+		--
+		--000000000011111111112222222222333
+		--R12345678901234567890123456789012
+		---------------------------------NT
+		
+		--000000000011111100000000001111111
+		--R12345678901234501234567890123456
+		-----------------NT--------------NT
+	end process;
+
+	delay_line_phase : delay_line
+		generic map (COUNT=>cycle_length-1)
+		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+
+	delay_line_phase2 : delay_line
+		generic map (COUNT=>cycle_length/2)
+		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+	
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			cpu_extra_enable_reg <= '0';
+			oldcpu_extra_enable_reg <= '0';
+			turbo_reg <= '0';
+			throttle_count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then										
+			cpu_extra_enable_reg <= cpu_extra_enable_next;
+			oldcpu_extra_enable_reg <= oldcpu_extra_enable_next;
+			turbo_reg <= turbo_next;
+			throttle_count_reg <= throttle_count_next;
+		end if;
+	end process;
+	
+	-- next state
+	memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
+	cpu_enable <= (turbo_reg or cpu_extra_enable_reg or enable_179) and not(pause_6502);
+	cpu_extra_enable_next <= cpu_enable and not(memory_ready);
+	
+	oldcpu_extra_enable_next <= enable_179_expanded and not(memory_ready);
+	enable_179_expanded <= oldcpu_extra_enable_reg or enable_179;
+	
+	-- output
+	POKEY_ENABLE_179 <= enable_179_late; -- aka enable_179_late!  TODO!!!
+	oldcpu_enable <= enable_179_expanded;
+	ANTIC_ENABLE_179 <= enable_179_early;
+	
+	CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
+
+end vhdl;
Index: common/a8core/syncreset_enable_divider.vhd
===================================================================
--- common/a8core/syncreset_enable_divider.vhd	(nonexistent)
+++ common/a8core/syncreset_enable_divider.vhd	(revision 1)
@@ -0,0 +1,81 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY syncreset_enable_divider IS
+generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNCRESET : in std_logic;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END syncreset_enable_divider;
+
+ARCHITECTURE vhdl OF syncreset_enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg,syncreset)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+		
+		if (syncreset='1') then
+			count_next <= std_logic_vector(to_unsigned(resetcount,width));
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: common/components/ps2_keyboard.vhdl
===================================================================
--- common/components/ps2_keyboard.vhdl	(nonexistent)
+++ common/components/ps2_keyboard.vhdl	(revision 1)
@@ -0,0 +1,266 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+--	KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code
+	
+--	KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed
+--	SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held
+--	CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held
+--	BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers)
+
+ENTITY ps2_keyboard IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	PS2_CLK : IN STD_LOGIC;
+	PS2_DAT : IN STD_LOGIC;
+	
+	KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released
+	KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code
+	KEY_EXTENDED : OUT STD_LOGIC;           -- valid on event, if scan code extended
+	KEY_UP : OUT STD_LOGIC                 -- value on event, if key released
+);
+END ps2_keyboard;
+
+ARCHITECTURE vhdl OF ps2_keyboard IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	-- PS2 keyboard sends on its own clock high->low transition
+	-- start, 8 data bits, parity, stop
+	
+	-- Codes are either 1 bytes or 2 bytes (extended) on press
+	-- XX
+	-- EX YY
+	-- Codes are eighter 2 bytes or 3 bytes (extended) on release
+	-- F0 XX
+	-- EX F0 YY
+	
+	-- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77
+	
+	-- LSB first
+	-- Start bit 0
+	-- Stop bit 1
+	-- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7))
+	-- e.g. 
+	-- '0 1100 0010 0 1'
+	-- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0
+	
+
+	-- Receive raw data from ps2 serial interface
+	signal ps2_shiftreg_next : std_logic_vector(10 downto 0);
+	signal ps2_shiftreg_reg : std_logic_vector(10 downto 0);
+	
+	signal idle_next : std_logic_vector(3 downto 0);
+	signal idle_reg : std_logic_vector(3 downto 0);	
+
+	signal bitcount_next : std_logic_vector(3 downto 0);
+	signal bitcount_reg : std_logic_vector(3 downto 0);	
+	
+	signal enable_ps2 : std_logic;
+	
+	signal last_ps2_clk_next : std_logic;
+	signal last_ps2_clk_reg : std_logic;
+	
+	signal ps2_clk_reg : std_logic;
+	signal ps2_dat_reg : std_logic;
+	
+	signal parity : std_logic;
+	
+	-- Once we have whole parity checked bytes
+	signal byte_next : std_logic_vector(7 downto 0);
+	signal byte_reg : std_logic_vector(7 downto 0);
+	
+	signal byte_received_next : std_logic;
+	signal byte_received_reg : std_logic;	
+	
+	-- Decode if they are press(or repeat)/release or extended
+	signal pending_extended_next : std_logic;
+	signal pending_extended_reg : std_logic;
+	
+	signal pending_keyup_next : std_logic;
+	signal pending_keyup_reg : std_logic;
+	
+	-- To eventually get the code itself
+	signal key_event_next : std_logic;
+	signal key_event_reg : std_logic;
+	
+	signal key_value_next : std_logic_vector(9 downto 0);
+	signal key_value_reg : std_logic_vector(9 downto 0);
+	
+	-- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard
+	signal key_value_last_next : std_logic_vector(9 downto 0);
+	signal key_value_last_reg : std_logic_vector(9 downto 0);
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			ps2_clk_reg <= '0';
+			ps2_dat_reg <= '0';
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= '0';
+			
+			ps2_shiftreg_reg<= (others=>'0');		
+			idle_reg <= (others=>'0');
+			bitcount_reg <= (others=>'0');
+			
+			byte_received_reg <= '0';
+			byte_reg <= (others=>'0');
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= '0';
+			pending_keyup_reg <= '0';			
+
+			-- Output registers
+			key_event_reg <= '0';
+			key_value_reg <= (others=>'0');
+			
+			key_value_last_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			-- Raw interface
+			-- async - do we need some form of synchronizer?
+			ps2_clk_reg <= ps2_clk;
+			ps2_dat_reg <= ps2_dat;
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= last_ps2_clk_next;
+			
+			ps2_shiftreg_reg<= ps2_shiftreg_next;		
+			idle_reg <= idle_next;
+			bitcount_reg <= bitcount_next;
+			
+			byte_received_reg <= byte_received_next;
+			byte_reg <= byte_next;
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= pending_extended_next;
+			pending_keyup_reg <= pending_keyup_next;			
+
+			-- Output registers
+			key_event_reg <= key_event_next;
+			key_value_reg <= key_value_next;
+			
+			key_value_last_reg <= key_value_last_next;
+			
+		end if;
+	end process;
+
+	-- Divide clock by 256 to get approx 4*ps2 clock
+	enable_div : enable_divider
+		generic map (COUNT=>256)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2);
+	
+	-- capture bytes from ps2
+	parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor  ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1));
+	process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity)
+	begin	
+		ps2_shiftreg_next <= ps2_shiftreg_reg;
+		last_ps2_clk_next <= last_ps2_clk_reg;
+		
+		bitcount_next <= bitcount_reg;
+		
+		idle_next <= idle_reg;
+		
+		byte_received_next <= '0';
+		byte_next <= (others=>'0');
+		
+		if (enable_ps2 = '1') then		
+			last_ps2_clk_next <= ps2_clk_reg;
+			
+			-- sample on falling edge
+			if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then
+				ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1);
+				bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1);
+			end if;
+			
+			-- output to next stage when done
+			if (bitcount_reg = X"B") then
+				byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10);
+				byte_next <= ps2_shiftreg_reg(8 downto 1);
+				bitcount_next <= (others=>'0');
+			end if;
+			
+			-- reset if both high for a time period
+			idle_next <= std_logic_vector(unsigned(idle_reg) +1);
+			if (idle_reg = X"F") then
+				ps2_shiftreg_next <= (others=>'0');
+				bitcount_next <= (others=>'0');
+			end if;
+			if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then
+				idle_next <= X"0";
+			end if;		
+		end if;
+	end process;
+	
+	-- process bytes
+	process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg)
+	begin
+		pending_extended_next <=  pending_extended_reg;
+		pending_keyup_next <=  pending_keyup_reg;
+		
+		key_event_next <= '0';
+		key_value_next <= (others =>'0');
+		
+		key_value_last_next <= key_value_last_reg;
+		
+		if (byte_received_reg = '1') then		
+			case byte_reg is 
+				when X"E0" =>
+					pending_extended_next <= '1';					
+				when X"E1" =>
+					pending_extended_next <= '1';
+				when X"F0" =>
+					pending_keyup_next <= '1';
+				when others => 
+					pending_extended_next <= '0';
+					pending_keyup_next <= '0';	
+					
+					if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then
+						key_event_next <= '1';
+						key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+						
+						key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+					end if;
+			end case;
+		end if;
+	end process;
+			
+	-- Output
+	key_event <= key_event_reg;
+	key_value <= key_value_reg(7 downto 0);
+	key_extended <= key_value_reg(8);
+	key_up <= key_value_reg(9);
+		
+END vhdl;
Index: common/components/spi_master.vhd
===================================================================
--- common/components/spi_master.vhd	(nonexistent)
+++ common/components/spi_master.vhd	(revision 1)
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+--
+--   FileName:         spi_master.vhd
+--   Dependencies:     none
+--   Design Software:  Quartus II Version 9.0 Build 132 SJ Full Version
+--
+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+--   Version History
+--   Version 1.0 7/23/2010 Scott Larson
+--     Initial Public Release
+--   Version 1.1 4/11/2013 Scott Larson
+--     Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
+--    
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_master IS
+  GENERIC(
+    slaves  : INTEGER := 4;  --number of spi slaves
+    d_width : INTEGER := 2); --data bus width
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+    enable  : IN     STD_LOGIC;                             --initiate transaction
+    cpol    : IN     STD_LOGIC;                             --spi clock polarity
+    cpha    : IN     STD_LOGIC;                             --spi clock phase
+    cont    : IN     STD_LOGIC;                             --continuous mode command
+    clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+    addr    : IN     INTEGER;                               --address of slave
+    tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+    miso    : IN     STD_LOGIC;                             --master in, slave out
+    sclk    : BUFFER STD_LOGIC;                             --spi clock
+    ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+    mosi    : OUT    STD_LOGIC;                             --master out, slave in
+    busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+    rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+END spi_master;
+
+ARCHITECTURE logic OF spi_master IS
+  TYPE machine IS(ready, execute);                           --state machine data type
+  SIGNAL state       : machine;                              --current state
+  SIGNAL slave       : INTEGER;                              --slave selected for current transaction
+  SIGNAL clk_ratio   : INTEGER;                              --current clk_div
+  SIGNAL count       : INTEGER;                              --counter to trigger sclk from system clock
+  SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1;     --count spi clock toggles
+  SIGNAL assert_data : STD_LOGIC;                            --'1' is tx sclk toggle, '0' is rx sclk toggle
+  SIGNAL continue    : STD_LOGIC;                            --flag to continue transaction
+  SIGNAL rx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
+  SIGNAL tx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
+  SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2;         --last rx data bit location
+BEGIN
+  PROCESS(clock, reset_n)
+  BEGIN
+
+    IF(reset_n = '0') THEN        --reset system
+      busy <= '1';                --set busy signal
+      ss_n <= (OTHERS => '1');    --deassert all slave select lines
+      mosi <= 'Z';                --set master out to high impedance
+      rx_data <= (OTHERS => '0'); --clear receive data port
+      state <= ready;             --go to ready state when reset is exited
+
+    ELSIF(clock'EVENT AND clock = '1') THEN
+      CASE state IS               --state machine
+
+        WHEN ready =>
+          busy <= '0';             --clock out not busy signal
+          ss_n <= (OTHERS => '1'); --set all slave select outputs high
+          mosi <= 'Z';             --set mosi output high impedance
+          continue <= '0';         --clear continue flag
+
+          --user input to initiate transaction
+          IF(enable = '1') THEN       
+            busy <= '1';             --set busy signal
+            IF(addr < slaves) THEN   --check for valid slave address
+              slave <= addr;         --clock in current slave selection if valid
+            ELSE
+              slave <= 0;            --set to first slave if not valid
+            END IF;
+            IF(clk_div = 0) THEN     --check for valid spi speed
+              clk_ratio <= 1;        --set to maximum speed if zero
+              count <= 1;            --initiate system-to-spi clock counter
+            ELSE
+              clk_ratio <= clk_div;  --set to input selection if valid
+              count <= clk_div;      --initiate system-to-spi clock counter
+            END IF;
+            sclk <= cpol;            --set spi clock polarity
+            assert_data <= NOT cpha; --set spi clock phase
+            tx_buffer <= tx_data;    --clock in data for transmit into buffer
+            clk_toggles <= 0;        --initiate clock toggle counter
+            last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
+            state <= execute;        --proceed to execute state
+          ELSE
+            state <= ready;          --remain in ready state
+          END IF;
+
+        WHEN execute =>
+          busy <= '1';        --set busy signal
+          ss_n(slave) <= '0'; --set proper slave select output
+          
+          --system clock to sclk ratio is met
+          IF(count = clk_ratio) THEN        
+            count <= 1;                     --reset system-to-spi clock counter
+            assert_data <= NOT assert_data; --switch transmit/receive indicator
+            IF(clk_toggles = d_width*2 + 1) THEN
+              clk_toggles <= 0;               --reset spi clock toggles counter
+            ELSE
+              clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
+            END IF;
+            
+            --spi clock toggle needed
+            IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN 
+              sclk <= NOT sclk; --toggle spi clock
+            END IF;
+            
+            --receive spi clock toggle
+            IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN 
+              rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
+            END IF;
+            
+            --transmit spi clock toggle
+            IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN 
+              mosi <= tx_buffer(d_width-1);                     --clock out data bit
+              tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
+            END IF;
+            
+            --last data receive, but continue
+            IF(clk_toggles = last_bit_rx AND cont = '1') THEN 
+              tx_buffer <= tx_data;                       --reload transmit buffer
+              clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
+              continue <= '1';                            --set continue flag
+            END IF;
+            
+            --normal end of transaction, but continue
+            IF(continue = '1') THEN  
+              continue <= '0';      --clear continue flag
+              busy <= '0';          --clock out signal that first receive data is ready
+              rx_data <= rx_buffer; --clock out received data to output port    
+            END IF;
+            
+            --end of transaction
+            IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN   
+              busy <= '0';             --clock out not busy signal
+              ss_n <= (OTHERS => '1'); --set all slave selects high
+              mosi <= 'Z';             --set mosi output high impedance
+              rx_data <= rx_buffer;    --clock out received data to output port
+              state <= ready;          --return to ready state
+            ELSE                       --not end of transaction
+              state <= execute;        --remain in execute state
+            END IF;
+          
+          ELSE        --system clock to sclk ratio not met
+            count <= count + 1; --increment counter
+            state <= execute;   --remain in execute state
+          END IF;
+
+      END CASE;
+    END IF;
+  END PROCESS; 
+END logic;
Index: common/romgen/HelloTinyROM.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/romgen/HelloTinyROM.bin
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/components/scandoubler.vhdl
===================================================================
--- common/components/scandoubler.vhdl	(nonexistent)
+++ common/components/scandoubler.vhdl	(revision 1)
@@ -0,0 +1,301 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY scandoubler IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	VGA : IN STD_LOGIC;
+	COMPOSITE_ON_HSYNC : in std_logic;
+
+	colour_enable : in std_logic;
+	doubled_enable : in std_logic;
+	
+	-- GTIA interface
+	colour_in : in std_logic_vector(7 downto 0);
+	vsync_in : in std_logic;
+	hsync_in : in std_logic;
+	
+	-- TO TV...
+	R : OUT STD_LOGIC_vector(3 downto 0);
+	G : OUT STD_LOGIC_vector(3 downto 0);
+	B : OUT STD_LOGIC_vector(3 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic
+);
+END scandoubler;
+
+ARCHITECTURE vhdl OF scandoubler IS
+
+	COMPONENT gtia_palette IS
+	PORT 
+	( 
+		ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+		
+		R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+	);
+	END component;
+	
+--	component reg_file IS
+--	generic
+--	(
+--		BYTES : natural := 1;
+--		WIDTH : natural := 1
+--	);
+--	PORT 
+--	( 
+--		CLK : IN STD_LOGIC;
+--		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+--		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+--		WR_EN : IN STD_LOGIC;
+--		
+--		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+--	);
+--	END component;
+	
+	component scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	signal colour_next : std_logic_vector(7 downto 0);
+	signal colour_reg : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+
+	signal r_next : std_logic_vector(7 downto 0);
+	signal g_next : std_logic_vector(7 downto 0);
+	signal b_next : std_logic_vector(7 downto 0);	
+	signal r_reg : std_logic_vector(7 downto 0);
+	signal g_reg : std_logic_vector(7 downto 0);
+	signal b_reg : std_logic_vector(7 downto 0);
+	
+	signal linea_address : std_logic_vector(10 downto 0);
+	signal linea_write_enable : std_logic;
+	signal linea_out : std_logic_vector(7 downto 0);
+
+	signal lineb_address : std_logic_vector(10 downto 0);
+	signal lineb_write_enable : std_logic;
+	signal lineb_out : std_logic_vector(7 downto 0);
+	
+	signal input_address_next : std_logic_vector(10 downto 0);
+	signal input_address_reg : std_logic_vector(10 downto 0);
+
+	signal output_address_next : std_logic_vector(10 downto 0);
+	signal output_address_reg : std_logic_vector(10 downto 0);
+	
+	signal buffer_select_next : std_logic;
+	signal buffer_select_reg : std_logic;
+	
+	signal hsync_in_reg : std_logic;
+	
+	signal vga_hsync_next : std_logic;
+	signal vga_hsync_reg : std_logic;
+	signal vga_hsync_start : std_logic;
+	signal vga_hsync_end : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			r_reg <= (others=>'0');
+			g_reg <= (others=>'0');
+			b_reg <= (others=>'0');			
+			colour_reg <= (others=>'0');
+			hsync_reg <= '0';
+			vsync_reg <= '0';
+			
+			input_address_reg <= (others=>'0');
+			output_address_reg <= (others=>'0');
+			
+			buffer_select_reg <= '0';
+			
+			vga_hsync_reg <= '0';
+		elsif (clk'event and clk='1') then										
+			r_reg <= r_next;
+			g_reg <= g_next;
+			b_reg <= b_next;
+			colour_reg <= colour_next;
+			hsync_reg <= hsync_next;
+			vsync_reg <= vsync_next;
+		
+			input_address_reg <= input_address_next;
+			output_address_reg <= output_address_next;
+			
+			buffer_select_reg <= buffer_select_next;
+			
+			hsync_in_reg <= hsync_in;
+			
+			vga_hsync_reg <= vga_hsync_next;
+		end if;
+	end process;
+	
+	-- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!!
+	--	linea : reg_file
+		--generic map (BYTES=>456,WIDTH=>9)
+		--port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out);
+
+	--lineb : reg_file
+	--	generic map (BYTES=>456,WIDTH=>9)
+	--	port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);	
+	
+	linea : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
+
+	lineb : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);	
+	
+	-- capture
+	process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
+	begin
+		input_address_next <= input_address_reg;
+		buffer_select_next <= buffer_select_reg;
+		
+		linea_write_enable <= '0';
+		lineb_write_enable <= '0';
+		
+		if (colour_enable = '1') then
+			input_address_next <= std_logic_vector(unsigned(input_address_reg)+1);
+			linea_write_enable <= buffer_select_reg;
+			lineb_write_enable <= not(buffer_select_reg);
+		end if;		
+		
+		if (hsync_in = '1' and hsync_in_reg = '0') then
+				input_address_next <= (others=>'0');
+				buffer_select_next <= not(buffer_select_reg);
+		end if;		
+	end process;
+	
+	-- output
+	process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable)
+	begin
+		output_address_next <= output_address_reg;
+		vga_hsync_start<='0';
+		vga_hsync_next <= vga_hsync_reg;
+		
+		if (doubled_enable = '1') then
+			output_address_next <= std_logic_vector(unsigned(output_address_reg)+1);
+			
+			if (output_address_reg = "111"&X"1F") then
+				output_address_next <= (others=>'0');
+				vga_hsync_start <= '1';
+				vga_hsync_next <= '1';
+			end if;
+		end if;
+		
+		if (vga_hsync_end = '1') then
+			vga_hsync_next <= '0';
+		end if;
+	end process;
+	
+	linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg;
+	lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg;
+	
+	hsync_delay : delay_line
+		generic map (COUNT=>128)
+		port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end);			
+	
+	-- display
+	process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out)
+	begin	
+		colour_next <= colour_reg;
+		vsync_next <= vsync_reg;
+		hsync_next <= hsync_reg;
+		
+		if (vga = '0') then
+			-- non-vga mode - pass through
+			colour_next <= colour_in;
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(hsync_in or vsync_in);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(hsync_in xor vsync_in);
+			else
+				hsync_next <= not(hsync_in);			
+			end if;
+		else
+			-- vga mode, store all inputs - then play back!			
+			if (buffer_select_reg = '0') then
+				colour_next <= linea_out; -- todo, smoothly increase/decrease...
+			else
+				colour_next <= lineb_out;
+			end if;
+			
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(vga_hsync_reg);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(vga_hsync_reg xor vsync_in);
+			else
+				hsync_next <= not(vga_hsync_reg);			
+			end if;
+		end if;
+	end process;
+
+	-- colour palette
+--	Color             Value         Color             Value
+--Black           0,      0	Medium blue     8,    128
+--Rust            1,     16       Dark blue       9,    144
+--Red-orange      2,     32       Blue-grey      10,    160
+--Dark orange     3,     48       Olive green    11,    176
+--Red             4,     64       Medium green   12,    192
+--Dk lavender     5,     80       Dark green     13,    208
+--Cobalt blue     6,     96       Orange-green   14,    224
+--Ultramarine     7,    112       Orange         15,    240
+
+-- from altirra	
+	palette1 : entity work.gtia_palette(altirra)
+		port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next);
+		
+-- from lao
+--	palette2 : entity work.gtia_palette(laoo)
+--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
+	
+	-- output	
+		-- TODO - for DE2, output full 8 bits
+	R <= R_reg(7 downto 4);
+	G <= G_reg(7 downto 4);
+	B <= B_reg(7 downto 4);
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+
+end vhdl;
+
+
Index: common/romgen/ATARIXL.ROM
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: common/romgen/ATARIXL.ROM
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: common/romgen/basic.vhdl
===================================================================
--- common/romgen/basic.vhdl	(nonexistent)
+++ common/romgen/basic.vhdl	(revision 1)
@@ -0,0 +1,8226 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity basic is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(12 downto 0);
+        q:out std_logic_vector(7 downto 0)
+);
+end basic;
+
+architecture syn of basic is
+        type rom_type is array(0 to 8191) of std_logic_vector(7 downto 0);
+        signal ROM:rom_type:=
+(
+	X"a5",
+X"ca",
+X"d0",
+X"04",
+X"a5",
+X"08",
+X"d0",
+X"45",
+X"a2",
+X"ff",
+X"9a",
+X"d8",
+X"ae",
+X"e7",
+X"02",
+X"ac",
+X"e8",
+X"02",
+X"86",
+X"80",
+X"84",
+X"81",
+X"a9",
+X"00",
+X"85",
+X"92",
+X"85",
+X"ca",
+X"c8",
+X"8a",
+X"a2",
+X"82",
+X"95",
+X"00",
+X"e8",
+X"94",
+X"00",
+X"e8",
+X"e0",
+X"92",
+X"90",
+X"f6",
+X"a2",
+X"86",
+X"a0",
+X"01",
+X"20",
+X"7a",
+X"a8",
+X"a2",
+X"8c",
+X"a0",
+X"03",
+X"20",
+X"7a",
+X"a8",
+X"a9",
+X"00",
+X"a8",
+X"91",
+X"84",
+X"91",
+X"8a",
+X"c8",
+X"a9",
+X"80",
+X"91",
+X"8a",
+X"c8",
+X"a9",
+X"03",
+X"91",
+X"8a",
+X"a9",
+X"0a",
+X"85",
+X"c9",
+X"20",
+X"f1",
+X"b8",
+X"20",
+X"45",
+X"bd",
+X"20",
+X"5b",
+X"bd",
+X"a5",
+X"92",
+X"f0",
+X"03",
+X"20",
+X"9d",
+X"bd",
+X"20",
+X"62",
+X"bd",
+X"a5",
+X"ca",
+X"d0",
+X"9c",
+X"a2",
+X"ff",
+X"9a",
+X"20",
+X"51",
+X"da",
+X"a9",
+X"5d",
+X"85",
+X"c2",
+X"20",
+X"ed",
+X"bd",
+X"20",
+X"f2",
+X"a9",
+X"f0",
+X"ea",
+X"a9",
+X"00",
+X"85",
+X"f2",
+X"85",
+X"9f",
+X"85",
+X"94",
+X"85",
+X"a6",
+X"85",
+X"b3",
+X"85",
+X"b0",
+X"85",
+X"b1",
+X"a5",
+X"84",
+X"85",
+X"ad",
+X"a5",
+X"85",
+X"85",
+X"ae",
+X"20",
+X"a1",
+X"db",
+X"20",
+X"9a",
+X"a1",
+X"20",
+X"c4",
+X"a2",
+X"a5",
+X"d5",
+X"10",
+X"02",
+X"85",
+X"a6",
+X"20",
+X"a1",
+X"db",
+X"a4",
+X"f2",
+X"84",
+X"a8",
+X"b1",
+X"f3",
+X"c9",
+X"9b",
+X"d0",
+X"07",
+X"24",
+X"a6",
+X"30",
+X"b2",
+X"4c",
+X"86",
+X"a1",
+X"a5",
+X"94",
+X"85",
+X"a7",
+X"20",
+X"c4",
+X"a2",
+X"20",
+X"a1",
+X"db",
+X"a9",
+X"a4",
+X"a0",
+X"9f",
+X"a2",
+X"02",
+X"20",
+X"54",
+X"a4",
+X"86",
+X"f2",
+X"a5",
+X"af",
+X"20",
+X"c4",
+X"a2",
+X"20",
+X"a1",
+X"db",
+X"20",
+X"be",
+X"a1",
+X"90",
+X"35",
+X"a4",
+X"9f",
+X"b1",
+X"f3",
+X"c9",
+X"9b",
+X"d0",
+X"06",
+X"c8",
+X"91",
+X"f3",
+X"88",
+X"a9",
+X"20",
+X"09",
+X"80",
+X"91",
+X"f3",
+X"a9",
+X"40",
+X"05",
+X"a6",
+X"85",
+X"a6",
+X"a4",
+X"a8",
+X"84",
+X"f2",
+X"a2",
+X"03",
+X"86",
+X"a7",
+X"e8",
+X"86",
+X"94",
+X"a9",
+X"37",
+X"20",
+X"c4",
+X"a2",
+X"a4",
+X"f2",
+X"b1",
+X"f3",
+X"e6",
+X"f2",
+X"c9",
+X"9b",
+X"d0",
+X"f3",
+X"20",
+X"c4",
+X"a2",
+X"a5",
+X"94",
+X"a4",
+X"a7",
+X"91",
+X"80",
+X"a4",
+X"f2",
+X"88",
+X"b1",
+X"f3",
+X"c9",
+X"9b",
+X"d0",
+X"9a",
+X"a0",
+X"02",
+X"a5",
+X"94",
+X"91",
+X"80",
+X"20",
+X"a2",
+X"a9",
+X"a9",
+X"00",
+X"b0",
+X"03",
+X"20",
+X"dc",
+X"a9",
+X"38",
+X"e5",
+X"94",
+X"f0",
+X"1e",
+X"b0",
+X"13",
+X"49",
+X"ff",
+X"a8",
+X"c8",
+X"a2",
+X"8a",
+X"20",
+X"7a",
+X"a8",
+X"a5",
+X"97",
+X"85",
+X"8a",
+X"a5",
+X"98",
+X"85",
+X"8b",
+X"d0",
+X"09",
+X"a8",
+X"20",
+X"d0",
+X"a9",
+X"a2",
+X"8a",
+X"20",
+X"f8",
+X"a8",
+X"a4",
+X"94",
+X"88",
+X"b1",
+X"80",
+X"91",
+X"8a",
+X"98",
+X"d0",
+X"f8",
+X"24",
+X"a6",
+X"50",
+X"29",
+X"a5",
+X"b1",
+X"0a",
+X"0a",
+X"0a",
+X"a2",
+X"88",
+X"20",
+X"f7",
+X"a8",
+X"38",
+X"a5",
+X"84",
+X"e5",
+X"ad",
+X"a8",
+X"a5",
+X"85",
+X"e5",
+X"ae",
+X"a2",
+X"84",
+X"20",
+X"fa",
+X"a8",
+X"24",
+X"a6",
+X"10",
+X"06",
+X"20",
+X"aa",
+X"b5",
+X"4c",
+X"60",
+X"a0",
+X"20",
+X"8e",
+X"b5",
+X"4c",
+X"60",
+X"a0",
+X"10",
+X"fb",
+X"4c",
+X"5e",
+X"a9",
+X"20",
+X"a2",
+X"a9",
+X"b0",
+X"f3",
+X"20",
+X"dc",
+X"a9",
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+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"a7",
+X"dd",
+X"20",
+X"b6",
+X"dd",
+X"a2",
+X"f1",
+X"a0",
+X"ba",
+X"20",
+X"89",
+X"dd",
+X"20",
+X"60",
+X"da",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"db",
+X"da",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"a7",
+X"dd",
+X"20",
+X"b6",
+X"dd",
+X"a2",
+X"e6",
+X"a0",
+X"05",
+X"20",
+X"89",
+X"dd",
+X"20",
+X"28",
+X"db",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"60",
+X"da",
+X"a2",
+X"6c",
+X"a0",
+X"df",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"db",
+X"da",
+X"a5",
+X"d4",
+X"f0",
+X"0e",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"98",
+X"dd",
+X"20",
+X"66",
+X"da",
+X"c6",
+X"ef",
+X"10",
+X"c6",
+X"a2",
+X"ec",
+X"a0",
+X"05",
+X"20",
+X"89",
+X"dd",
+X"a5",
+X"f1",
+X"f0",
+X"23",
+X"38",
+X"e9",
+X"40",
+X"18",
+X"6a",
+X"18",
+X"69",
+X"40",
+X"29",
+X"7f",
+X"85",
+X"e0",
+X"a5",
+X"f1",
+X"6a",
+X"a9",
+X"01",
+X"90",
+X"02",
+X"a9",
+X"10",
+X"85",
+X"e1",
+X"a2",
+X"04",
+X"a9",
+X"00",
+X"95",
+X"e2",
+X"ca",
+X"10",
+X"fb",
+X"20",
+X"db",
+X"da",
+X"60",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"00",
+X"a0",
+X"00",
+X"05",
+X"f0",
+X"bf"
+
+);
+        signal rdata:std_logic_vector(7 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: common/romgen/createall
===================================================================
--- common/romgen/createall	(nonexistent)
+++ common/romgen/createall	(revision 1)
@@ -0,0 +1,7 @@
+cp /home/markw/altera/atari_xe_fpga/zpu/leds_nosdrive/HelloTinyROM.bin .
+cp /home/markw/altera/atari_xe_fpga/zpu/leds_nosdrive/HelloTinyROM.dis .
+./create_rom.pl 1 ATARIXL.ROM os16 > os16.vhdl
+./create_rom.pl 1 ATARIBAS.ROM basic > basic.vhdl
+./create_rom.pl 4 HelloTinyROM.bin zpu_rom 12 > zpu_rom.vhdl
+cp *.vhdl ../source/
+cp *.vhdl ../sim/

Property changes on: common/romgen/createall
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/romgen/create_rom.pl
===================================================================
--- common/romgen/create_rom.pl	(nonexistent)
+++ common/romgen/create_rom.pl	(revision 1)
@@ -0,0 +1,86 @@
+#!/usr/bin/perl -w
+use strict;
+use POSIX;
+
+my $length = shift @ARGV;
+my $data_max = ($length*8) - 1;
+my $filename= shift @ARGV;
+my $name = shift @ARGV;
+my $fixedsize = shift @ARGV;
+
+#Based on file size
+my $filesize = -s $filename;
+my $addr_max = ceil((log($filesize/$length)/log(2)))-1;
+if (defined $fixedsize)
+{
+	$addr_max = $fixedsize-1;
+}
+
+my $size_max = 2**($addr_max+1)-1;
+
+my $data = "";
+   open(my $FILE, "$filename") or die $!;
+   binmode($FILE);
+
+   my $needed = 2**($addr_max+1);
+   my $bytes = "";
+   while (read($FILE, my $byte, 1)) {
+        $bytes .= $byte;
+	if ($length == length $bytes)
+	{
+		$data.= "X\"".unpack('H*', $bytes)."\",\n";
+		$bytes = "";
+		$needed = $needed-1;
+	}
+   }
+
+   my $content = "00"x$length;
+   for (1..$needed)
+   {
+       $data.="X\"$content\",\n";
+   }
+   $data=~s/(.*).$/$1/;
+
+   
+
+   close $FILE;
+
+#X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A", X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002", X"08201",X"00500",X"04001",X"02500",X"00340",X"00241", X"04002",X"08300",X"08201",X"00500",X"08101",X"00602", X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021", X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B", X"00900",X"00302",X"00102",X"04002",X"00900",X"08201", X"02023",X"00303",X"02433",X"00301",X"04004",X"00301", X"00102",X"02137",X"02036",X"00301",X"00102",X"02237", X"04004",X"00304",X"04040",X"02500",X"02500",X"02500", X"0030D",X"02341",X"08201",X"0400D"
+
+print <<END
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity $name is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector($addr_max downto 0);
+        q:out std_logic_vector($data_max downto 0)
+);
+end $name;
+
+architecture syn of $name is
+        type rom_type is array(0 to $size_max) of std_logic_vector($data_max downto 0);
+        signal ROM:rom_type:=
+(
+	$data
+);
+        signal rdata:std_logic_vector($data_max downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
+END
+

Property changes on: common/romgen/create_rom.pl
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: common/romgen/zpu_rom.vhdl
===================================================================
--- common/romgen/zpu_rom.vhdl	(nonexistent)
+++ common/romgen/zpu_rom.vhdl	(revision 1)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ab040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
+X"0a535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
+X"0772fc06",
+X"0c515104",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a810653",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72098105",
+X"72050970",
+X"81050906",
+X"0a098106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71098105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72720981",
+X"05055351",
+X"04000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097206",
+X"73730906",
+X"07535104",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"72830609",
+X"81058305",
+X"1010102a",
+X"81ff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fc0608",
+X"0b0b0b92",
+X"b8738306",
+X"10100508",
+X"060b0b0b",
+X"88a20400",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"fe040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"d8040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"72097081",
+X"0509060a",
+X"8106ff05",
+X"70547106",
+X"73097274",
+X"05ff0506",
+X"07515151",
+X"04000000",
+X"72097081",
+X"0509060a",
+X"098106ff",
+X"05705471",
+X"06730972",
+X"7405ff05",
+X"06075151",
+X"51040000",
+X"05ff0504",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"810b92c8",
+X"0c510400",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00718105",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00028405",
+X"72101005",
+X"52040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00717105",
+X"ff057153",
+X"51020d04",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101010",
+X"10101053",
+X"51047381",
+X"ff067383",
+X"06098105",
+X"83051010",
+X"102b0772",
+X"fc060c51",
+X"51043c04",
+X"72728072",
+X"8106ff05",
+X"09720605",
+X"71105272",
+X"0a100a53",
+X"72ed3851",
+X"51535104",
+X"83e08008",
+X"83e08408",
+X"83e08808",
+X"75758f82",
+X"2d505083",
+X"e0800856",
+X"83e0880c",
+X"83e0840c",
+X"83e0800c",
+X"510483e0",
+X"800883e0",
+X"840883e0",
+X"88087575",
+X"8d962d50",
+X"5083e080",
+X"085683e0",
+X"880c83e0",
+X"840c83e0",
+X"800c5104",
+X"00008004",
+X"89a80489",
+X"a80b8cd8",
+X"0483e08c",
+X"080283e0",
+X"8c0cfe3d",
+X"0d83e08c",
+X"08880508",
+X"7070832b",
+X"70733170",
+X"822b7083",
+X"e08c08fc",
+X"050c92d4",
+X"0883e08c",
+X"08fc0508",
+X"710c5151",
+X"51515252",
+X"843d0d83",
+X"e08c0c04",
+X"83e08c08",
+X"0283e08c",
+X"0cff3d0d",
+X"800b83e0",
+X"8c08fc05",
+X"0c92e408",
+X"51ff87c3",
+X"e1f0710c",
+X"92e00851",
+X"80710c88",
+X"800a0b83",
+X"e08c08fc",
+X"050c83e0",
+X"8c08fc05",
+X"08818480",
+X"802e9e38",
+X"83e08c08",
+X"fc050851",
+X"80713483",
+X"e08c08fc",
+X"05088105",
+X"83e08c08",
+X"fc050cd6",
+X"3992e408",
+X"5185aad5",
+X"aad5710c",
+X"92e00851",
+X"85aad5aa",
+X"d5710c82",
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+X"3992e408",
+X"5180710c",
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+X"ff87c3e1",
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+X"83e08c0c",
+X"fe3d0d92",
+X"d0087008",
+X"83e08c08",
+X"fc050c51",
+X"83e08c08",
+X"88050881",
+X"2e098106",
+X"953892d0",
+X"0883e08c",
+X"08fc0508",
+X"feff0670",
+X"720c5252",
+X"933992d0",
+X"0883e08c",
+X"08fc0508",
+X"81800770",
+X"720c5252",
+X"843d0d83",
+X"e08c0c04",
+X"83e08c08",
+X"0283e08c",
+X"0cfe3d0d",
+X"92d00870",
+X"0883e08c",
+X"08fc050c",
+X"5183e08c",
+X"08880508",
+X"953892d0",
+X"0883e08c",
+X"08fc0508",
+X"ffbf0670",
+X"720c5252",
+X"933992d0",
+X"0883e08c",
+X"08fc0508",
+X"80c00770",
+X"720c5252",
+X"843d0d83",
+X"e08c0c04",
+X"83e08c08",
+X"0283e08c",
+X"0cfd3d0d",
+X"800b83e0",
+X"8c08fc05",
+X"0c800b83",
+X"e08c08f8",
+X"05348151",
+X"ff8e3f80",
+X"51feb43f",
+X"93b40852",
+X"807234fc",
+X"e73f8151",
+X"fea53f80",
+X"51fef53f",
+X"ff3983e0",
+X"8c080283",
+X"e08c0cf9",
+X"3d0d800b",
+X"83e08c08",
+X"fc050c83",
+X"e08c0888",
+X"05088025",
+X"b93883e0",
+X"8c088805",
+X"083083e0",
+X"8c088805",
+X"0c800b83",
+X"e08c08f4",
+X"050c83e0",
+X"8c08fc05",
+X"088a3881",
+X"0b83e08c",
+X"08f4050c",
+X"83e08c08",
+X"f4050883",
+X"e08c08fc",
+X"050c83e0",
+X"8c088c05",
+X"088025b9",
+X"3883e08c",
+X"088c0508",
+X"3083e08c",
+X"088c050c",
+X"800b83e0",
+X"8c08f005",
+X"0c83e08c",
+X"08fc0508",
+X"8a38810b",
+X"83e08c08",
+X"f0050c83",
+X"e08c08f0",
+X"050883e0",
+X"8c08fc05",
+X"0c805383",
+X"e08c088c",
+X"05085283",
+X"e08c0888",
+X"05085181",
+X"df3f83e0",
+X"80087083",
+X"e08c08f8",
+X"050c5483",
+X"e08c08fc",
+X"0508802e",
+X"903883e0",
+X"8c08f805",
+X"083083e0",
+X"8c08f805",
+X"0c83e08c",
+X"08f80508",
+X"7083e080",
+X"0c54893d",
+X"0d83e08c",
+X"0c0483e0",
+X"8c080283",
+X"e08c0cfb",
+X"3d0d800b",
+X"83e08c08",
+X"fc050c83",
+X"e08c0888",
+X"05088025",
+X"993883e0",
+X"8c088805",
+X"083083e0",
+X"8c088805",
+X"0c810b83",
+X"e08c08fc",
+X"050c83e0",
+X"8c088c05",
+X"08802590",
+X"3883e08c",
+X"088c0508",
+X"3083e08c",
+X"088c050c",
+X"815383e0",
+X"8c088c05",
+X"085283e0",
+X"8c088805",
+X"0851bd3f",
+X"83e08008",
+X"7083e08c",
+X"08f8050c",
+X"5483e08c",
+X"08fc0508",
+X"802e9038",
+X"83e08c08",
+X"f8050830",
+X"83e08c08",
+X"f8050c83",
+X"e08c08f8",
+X"05087083",
+X"e0800c54",
+X"873d0d83",
+X"e08c0c04",
+X"83e08c08",
+X"0283e08c",
+X"0cfd3d0d",
+X"810b83e0",
+X"8c08fc05",
+X"0c800b83",
+X"e08c08f8",
+X"050c83e0",
+X"8c088c05",
+X"0883e08c",
+X"08880508",
+X"27b93883",
+X"e08c08fc",
+X"0508802e",
+X"ae38800b",
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+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000"
+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: common/zpu/zpu_rom.vhdl
===================================================================
--- common/zpu/zpu_rom.vhdl	(nonexistent)
+++ common/zpu/zpu_rom.vhdl	(revision 1)
@@ -0,0 +1,4130 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity zpu_rom is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(11 downto 0);
+        q:out std_logic_vector(31 downto 0)
+);
+end zpu_rom;
+
+architecture syn of zpu_rom is
+        type rom_type is array(0 to 4095) of std_logic_vector(31 downto 0);
+        signal ROM:rom_type:=
+(
+	X"0b0b0b89",
+X"ab040b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"0b0b0b0b",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"72830609",
+X"81058205",
+X"832b2a83",
+X"ffff0652",
+X"04000000",
+X"00000000",
+X"00000000",
+X"71fd0608",
+X"83ffff73",
+X"83060981",
+X"05820583",
+X"2b2b0906",
+X"7383ffff",
+X"0b0b0b0b",
+X"83a70400",
+X"72098105",
+X"72057373",
+X"09060906",
+X"73097306",
+X"070a8106",
+X"53510400",
+X"00000000",
+X"00000000",
+X"72722473",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"71737109",
+X"71068106",
+X"30720a10",
+X"0a720a10",
+X"0a31050a",
+X"81065151",
+X"53510400",
+X"00000000",
+X"72722673",
+X"732e0753",
+X"51040000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
+X"00000000",
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+X"00000000",
+X"00000000",
+X"0b0b0b88",
+X"bc040000",
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+X"00000000",
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+X"00000000",
+X"00000000",
+X"00000000",
+X"720a722b",
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+X"72729f06",
+X"0981050b",
+X"0b0b889f",
+X"05040000",
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+X"00000000",
+X"00000000",
+X"72722aff",
+X"739f062a",
+X"0974090a",
+X"8106ff05",
+X"06075351",
+X"04000000",
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+X"00000000",
+X"71715351",
+X"020d0406",
+X"73830609",
+X"81058205",
+X"832b0b2b",
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+X"72050970",
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+X"72720981",
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+
+);
+        signal rdata:std_logic_vector(31 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: de1/atari800core.jdi
===================================================================
--- de1/atari800core.jdi	(nonexistent)
+++ de1/atari800core.jdi	(revision 1)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: de1/atari800core.sdc
===================================================================
--- de1/atari800core.sdc	(nonexistent)
+++ de1/atari800core.sdc	(revision 1)
@@ -0,0 +1,6 @@
+create_clock -period 50MHz [get_ports CLOCK_50]
+derive_pll_clocks
+
+set_input_delay -max -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+set_input_delay -min -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+
Index: de1/gpio.vhd
===================================================================
--- de1/gpio.vhd	(nonexistent)
+++ de1/gpio.vhd	(revision 1)
@@ -0,0 +1,413 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio is
+port
+(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal read_write_n : std_logic;	
+	signal cart_data_read_async : std_logic_vector(7 downto 0);
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+	
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0');
+	GPIO_0_OUT(7 downto 5) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= '1';
+	GPIO_0_OUT(4) <= MONITOR; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= read_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable;
+	GPIO_0_OUT(33) <= pbi_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable;
+	GPIO_0_OUT(32) <= pbi_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and pbi_write_enable; -- d7
+	GPIO_0_OUT(31) <= cart_data_write(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and pbi_write_enable; -- d3
+	GPIO_0_OUT(30) <= cart_data_write(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable;
+	GPIO_0_OUT(29) <= pbi_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable;
+	GPIO_0_OUT(28) <= pbi_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable;
+	GPIO_0_OUT(27) <= pbi_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable;
+	GPIO_0_OUT(26) <= pbi_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable;
+	GPIO_0_OUT(25) <= pbi_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable;
+	GPIO_0_OUT(24) <= pbi_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable;
+	GPIO_0_OUT(23) <= pbi_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable;
+	GPIO_0_OUT(21) <= S4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable;
+	GPIO_0_OUT(20) <= pbi_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable;
+	GPIO_0_OUT(19) <= pbi_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable;
+	GPIO_0_OUT(18) <= pbi_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable;
+	GPIO_0_OUT(17) <= pbi_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and pbi_write_enable; -- d4
+	GPIO_0_OUT(16) <= cart_data_write(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and pbi_write_enable; -- d5
+	GPIO_0_OUT(15) <= cart_data_write(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and pbi_write_enable; -- d2
+	GPIO_0_OUT(14) <= cart_data_write(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and pbi_write_enable; -- d1
+	GPIO_0_OUT(13) <= cart_data_write(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and pbi_write_enable; -- d0
+	GPIO_0_OUT(12) <= cart_data_write(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and pbi_write_enable; -- d6
+	GPIO_0_OUT(11) <= cart_data_write(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable;
+	GPIO_0_OUT(10) <= S5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
+	GPIO_0_OUT(8) <= CCTL_n; -- cart control
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0'); -- unused
+	GPIO_0_OUT(7 downto 5) <= (others=>'0'); -- unused	
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4) when virtual_stick_in(7 downto 4) = "1111" else virtual_stick_in(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0) when virtual_stick_in(3 downto 0) = "1111" else virtual_stick_in(3 downto 0);
+		
+	--trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&gpio_enable&gpio_enable) or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= GPIO_1_IN(7)& GPIO_1_IN(6);
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	process(gpio_enable, keyboard_scan, keyboard_response_gpio, virtual_keycode, virtual_keyheld, virtual_shift_pressed, virtual_control_pressed, virtual_break_pressed, virtual_stick_in, virtual_trig_in)
+	begin	
+		keyboard_response <= keyboard_response_gpio;
+		
+		if (gpio_enable = '0') then
+			keyboard_response <= (others=>'1');
+		end if;
+		
+		if (virtual_keyheld='1' and virtual_keycode = not(keyboard_scan)) then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and virtual_break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and virtual_shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and virtual_control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;	
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+	
+	read_write_n <= not(pbi_write_enable);
+	
+	cart_complete <= cart_request; -- TODO!
+	
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	cart_data_read_async <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+	cart_data0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+	cart_data1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+	cart_data2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+	cart_data3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+	cart_data4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+	cart_data5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+	cart_data6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+	cart_data7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: de1/ledsw.vhd
===================================================================
--- de1/ledsw.vhd	(nonexistent)
+++ de1/ledsw.vhd	(revision 1)
@@ -0,0 +1,70 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+-- Simple module that connects the SW switches to the LEDR lights
+ENTITY ledsw IS
+PORT ( 
+	CLK : IN STD_LOGIC;
+
+	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	SYNC_KEYS : out std_logic_vector(3 downto 0);
+	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
+); 
+END ledsw;
+
+ARCHITECTURE Behavior OF ledsw IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+		
+	signal sw_reg : std_logic_vector(9 downto 0);
+	signal key_reg : std_logic_vector(3 downto 0);
+	
+BEGIN
+	sw9_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
+	sw8_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
+	sw7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
+	sw6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
+	sw5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
+	sw4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
+	sw3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
+	sw2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
+	sw1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
+	sw0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
+
+	key3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
+	key2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
+	key1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
+	key0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
+	
+	-- outputs
+	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
+	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
+END Behavior;
Index: de1/pll.vhd
===================================================================
--- de1/pll.vhd	(nonexistent)
+++ de1/pll.vhd	(revision 1)
@@ -0,0 +1,427 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		gate_lock_counter		: NATURAL;
+		gate_lock_signal		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		invalid_lock_multiplier		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		valid_lock_multiplier		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 10,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 20,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 10,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		gate_lock_counter => 1048575,
+		gate_lock_signal => "YES",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone II",
+		invalid_lock_multiplier => 5,
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		valid_lock_multiplier => 1
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: mcc216/atari800core.jdi
===================================================================
--- mcc216/atari800core.jdi	(nonexistent)
+++ mcc216/atari800core.jdi	(revision 1)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: mcc216/atari800core.sdc
===================================================================
--- mcc216/atari800core.sdc	(nonexistent)
+++ mcc216/atari800core.sdc	(revision 1)
@@ -0,0 +1,3 @@
+create_clock -period 5MHz [get_ports FPGA_CLK]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: mcc216/pll.ppf
===================================================================
--- mcc216/pll.ppf	(nonexistent)
+++ mcc216/pll.ppf	(revision 1)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mcc216/sdram_ctrl_4_ports.v
===================================================================
--- mcc216/sdram_ctrl_4_ports.v	(nonexistent)
+++ mcc216/sdram_ctrl_4_ports.v	(revision 1)
@@ -0,0 +1,561 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    	 
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b1000;
+            r_ram_ph  <= 4'b1000;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+					 //r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+                r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            //r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+            //          | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b0_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: common/romgen/os16.vhdl
===================================================================
--- common/romgen/os16.vhdl	(nonexistent)
+++ common/romgen/os16.vhdl	(revision 1)
@@ -0,0 +1,16418 @@
+
+--
+--ROMsUsingBlockRAMResources.
+--VHDLcodeforaROMwithregisteredoutput(template2)
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity os16 is
+port(
+        clock:in std_logic;
+        address:in std_logic_vector(13 downto 0);
+        q:out std_logic_vector(7 downto 0)
+);
+end os16;
+
+architecture syn of os16 is
+        type rom_type is array(0 to 16383) of std_logic_vector(7 downto 0);
+        signal ROM:rom_type:=
+(
+	X"11",
+X"92",
+X"10",
+X"05",
+X"83",
+X"00",
+X"42",
+X"42",
+X"00",
+X"00",
+X"01",
+X"02",
+X"a9",
+X"40",
+X"8d",
+X"0e",
+X"d4",
+X"ad",
+X"13",
+X"d0",
+X"8d",
+X"fa",
+X"03",
+X"60",
+X"2c",
+X"0f",
+X"d4",
+X"10",
+X"03",
+X"6c",
+X"00",
+X"02",
+X"d8",
+X"48",
+X"8a",
+X"48",
+X"98",
+X"48",
+X"8d",
+X"0f",
+X"d4",
+X"6c",
+X"22",
+X"02",
+X"d8",
+X"6c",
+X"16",
+X"02",
+X"48",
+X"ad",
+X"0e",
+X"d2",
+X"29",
+X"20",
+X"d0",
+X"0d",
+X"a9",
+X"df",
+X"8d",
+X"0e",
+X"d2",
+X"a5",
+X"10",
+X"8d",
+X"0e",
+X"d2",
+X"6c",
+X"0a",
+X"02",
+X"8a",
+X"48",
+X"ad",
+X"ff",
+X"d1",
+X"2d",
+X"49",
+X"02",
+X"f0",
+X"03",
+X"6c",
+X"38",
+X"02",
+X"a2",
+X"06",
+X"bd",
+X"cf",
+X"c0",
+X"e0",
+X"05",
+X"d0",
+X"04",
+X"25",
+X"10",
+X"f0",
+X"05",
+X"2c",
+X"0e",
+X"d2",
+X"f0",
+X"06",
+X"ca",
+X"10",
+X"ed",
+X"4c",
+X"a0",
+X"c0",
+X"49",
+X"ff",
+X"8d",
+X"0e",
+X"d2",
+X"a5",
+X"10",
+X"8d",
+X"0e",
+X"d2",
+X"e0",
+X"00",
+X"d0",
+X"05",
+X"ad",
+X"6d",
+X"02",
+X"d0",
+X"23",
+X"bd",
+X"d7",
+X"c0",
+X"aa",
+X"bd",
+X"00",
+X"02",
+X"8d",
+X"8c",
+X"02",
+X"bd",
+X"01",
+X"02",
+X"8d",
+X"8d",
+X"02",
+X"68",
+X"aa",
+X"6c",
+X"8c",
+X"02",
+X"a9",
+X"00",
+X"85",
+X"11",
+X"8d",
+X"ff",
+X"02",
+X"8d",
+X"f0",
+X"02",
+X"85",
+X"4d",
+X"68",
+X"40",
+X"68",
+X"aa",
+X"2c",
+X"02",
+X"d3",
+X"10",
+X"06",
+X"ad",
+X"00",
+X"d3",
+X"6c",
+X"02",
+X"02",
+X"2c",
+X"03",
+X"d3",
+X"10",
+X"06",
+X"ad",
+X"01",
+X"d3",
+X"6c",
+X"04",
+X"02",
+X"68",
+X"8d",
+X"8c",
+X"02",
+X"68",
+X"48",
+X"29",
+X"10",
+X"f0",
+X"07",
+X"ad",
+X"8c",
+X"02",
+X"48",
+X"6c",
+X"06",
+X"02",
+X"ad",
+X"8c",
+X"02",
+X"48",
+X"68",
+X"40",
+X"80",
+X"40",
+X"04",
+X"02",
+X"01",
+X"08",
+X"10",
+X"20",
+X"36",
+X"08",
+X"14",
+X"12",
+X"10",
+X"0e",
+X"0c",
+X"0a",
+X"4c",
+X"df",
+X"c0",
+X"e6",
+X"14",
+X"d0",
+X"08",
+X"e6",
+X"4d",
+X"e6",
+X"13",
+X"d0",
+X"02",
+X"e6",
+X"12",
+X"a9",
+X"fe",
+X"a2",
+X"00",
+X"a4",
+X"4d",
+X"10",
+X"06",
+X"85",
+X"4d",
+X"a6",
+X"13",
+X"a9",
+X"f6",
+X"85",
+X"4e",
+X"86",
+X"4f",
+X"ad",
+X"c5",
+X"02",
+X"45",
+X"4f",
+X"25",
+X"4e",
+X"8d",
+X"17",
+X"d0",
+X"a2",
+X"00",
+X"20",
+X"55",
+X"c2",
+X"d0",
+X"03",
+X"20",
+X"4f",
+X"c2",
+X"a5",
+X"42",
+X"d0",
+X"08",
+X"ba",
+X"bd",
+X"04",
+X"01",
+X"29",
+X"04",
+X"f0",
+X"03",
+X"4c",
+X"8a",
+X"c2",
+X"ad",
+X"13",
+X"d0",
+X"cd",
+X"fa",
+X"03",
+X"d0",
+X"b4",
+X"ad",
+X"0d",
+X"d4",
+X"8d",
+X"35",
+X"02",
+X"ad",
+X"0c",
+X"d4",
+X"8d",
+X"34",
+X"02",
+X"ad",
+X"31",
+X"02",
+X"8d",
+X"03",
+X"d4",
+X"ad",
+X"30",
+X"02",
+X"8d",
+X"02",
+X"d4",
+X"ad",
+X"2f",
+X"02",
+X"8d",
+X"00",
+X"d4",
+X"ad",
+X"6f",
+X"02",
+X"8d",
+X"1b",
+X"d0",
+X"ad",
+X"6c",
+X"02",
+X"f0",
+X"0e",
+X"ce",
+X"6c",
+X"02",
+X"a9",
+X"08",
+X"38",
+X"ed",
+X"6c",
+X"02",
+X"29",
+X"07",
+X"8d",
+X"05",
+X"d4",
+X"a2",
+X"08",
+X"8e",
+X"1f",
+X"d0",
+X"58",
+X"bd",
+X"c0",
+X"02",
+X"45",
+X"4f",
+X"25",
+X"4e",
+X"9d",
+X"12",
+X"d0",
+X"ca",
+X"10",
+X"f2",
+X"ad",
+X"f4",
+X"02",
+X"8d",
+X"09",
+X"d4",
+X"ad",
+X"f3",
+X"02",
+X"8d",
+X"01",
+X"d4",
+X"a2",
+X"02",
+X"20",
+X"55",
+X"c2",
+X"d0",
+X"03",
+X"20",
+X"52",
+X"c2",
+X"a2",
+X"02",
+X"e8",
+X"e8",
+X"bd",
+X"18",
+X"02",
+X"1d",
+X"19",
+X"02",
+X"f0",
+X"06",
+X"20",
+X"55",
+X"c2",
+X"9d",
+X"26",
+X"02",
+X"e0",
+X"08",
+X"d0",
+X"ec",
+X"ad",
+X"0f",
+X"d2",
+X"29",
+X"04",
+X"f0",
+X"08",
+X"ad",
+X"f1",
+X"02",
+X"f0",
+X"03",
+X"ce",
+X"f1",
+X"02",
+X"ad",
+X"2b",
+X"02",
+X"f0",
+X"3e",
+X"ad",
+X"0f",
+X"d2",
+X"29",
+X"04",
+X"d0",
+X"32",
+X"ce",
+X"2b",
+X"02",
+X"d0",
+X"32",
+X"ad",
+X"6d",
+X"02",
+X"d0",
+X"2d",
+X"ad",
+X"da",
+X"02",
+X"8d",
+X"2b",
+X"02",
+X"ad",
+X"09",
+X"d2",
+X"c9",
+X"9f",
+X"f0",
+X"20",
+X"c9",
+X"83",
+X"f0",
+X"1c",
+X"c9",
+X"84",
+X"f0",
+X"18",
+X"c9",
+X"94",
+X"f0",
+X"14",
+X"29",
+X"3f",
+X"c9",
+X"11",
+X"f0",
+X"0e",
+X"ad",
+X"09",
+X"d2",
+X"8d",
+X"fc",
+X"02",
+X"4c",
+X"f3",
+X"c1",
+X"a9",
+X"00",
+X"8d",
+X"2b",
+X"02",
+X"ad",
+X"00",
+X"d3",
+X"4a",
+X"4a",
+X"4a",
+X"4a",
+X"8d",
+X"79",
+X"02",
+X"8d",
+X"7b",
+X"02",
+X"ad",
+X"00",
+X"d3",
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+X"8d",
+X"78",
+X"02",
+X"8d",
+X"7a",
+X"02",
+X"ad",
+X"10",
+X"d0",
+X"8d",
+X"84",
+X"02",
+X"8d",
+X"86",
+X"02",
+X"ad",
+X"11",
+X"d0",
+X"8d",
+X"85",
+X"02",
+X"8d",
+X"87",
+X"02",
+X"a2",
+X"03",
+X"bd",
+X"00",
+X"d2",
+X"9d",
+X"70",
+X"02",
+X"9d",
+X"74",
+X"02",
+X"ca",
+X"10",
+X"f4",
+X"8d",
+X"0b",
+X"d2",
+X"a2",
+X"02",
+X"a0",
+X"01",
+X"b9",
+X"78",
+X"02",
+X"4a",
+X"4a",
+X"4a",
+X"9d",
+X"7d",
+X"02",
+X"9d",
+X"81",
+X"02",
+X"a9",
+X"00",
+X"2a",
+X"9d",
+X"7c",
+X"02",
+X"9d",
+X"80",
+X"02",
+X"ca",
+X"ca",
+X"88",
+X"10",
+X"e6",
+X"6c",
+X"24",
+X"02",
+X"6c",
+X"26",
+X"02",
+X"6c",
+X"28",
+X"02",
+X"bc",
+X"18",
+X"02",
+X"d0",
+X"08",
+X"bc",
+X"19",
+X"02",
+X"f0",
+X"10",
+X"de",
+X"19",
+X"02",
+X"de",
+X"18",
+X"02",
+X"d0",
+X"08",
+X"bc",
+X"19",
+X"02",
+X"d0",
+X"03",
+X"a9",
+X"00",
+X"60",
+X"a9",
+X"ff",
+X"60",
+X"0a",
+X"8d",
+X"2d",
+X"02",
+X"8a",
+X"a2",
+X"05",
+X"8d",
+X"0a",
+X"d4",
+X"ca",
+X"d0",
+X"fd",
+X"ae",
+X"2d",
+X"02",
+X"9d",
+X"17",
+X"02",
+X"98",
+X"9d",
+X"16",
+X"02",
+X"60",
+X"68",
+X"a8",
+X"68",
+X"aa",
+X"68",
+X"40",
+X"78",
+X"ad",
+X"13",
+X"d0",
+X"cd",
+X"fa",
+X"03",
+X"d0",
+X"2f",
+X"6a",
+X"90",
+X"05",
+X"20",
+X"c9",
+X"c4",
+X"d0",
+X"27",
+X"ad",
+X"44",
+X"02",
+X"d0",
+X"22",
+X"a9",
+X"ff",
+X"d0",
+X"20",
+X"78",
+X"a2",
+X"8c",
+X"88",
+X"d0",
+X"fd",
+X"ca",
+X"d0",
+X"fa",
+X"ad",
+X"3d",
+X"03",
+X"c9",
+X"5c",
+X"d0",
+X"0e",
+X"ad",
+X"3e",
+X"03",
+X"c9",
+X"93",
+X"d0",
+X"07",
+X"ad",
+X"3f",
+X"03",
+X"c9",
+X"25",
+X"f0",
+X"c8",
+X"a9",
+X"00",
+X"85",
+X"08",
+X"78",
+X"d8",
+X"a2",
+X"ff",
+X"9a",
+X"20",
+X"71",
+X"c4",
+X"a9",
+X"01",
+X"85",
+X"01",
+X"a5",
+X"08",
+X"d0",
+X"52",
+X"a9",
+X"00",
+X"a0",
+X"08",
+X"85",
+X"04",
+X"85",
+X"05",
+X"a9",
+X"ff",
+X"91",
+X"04",
+X"d1",
+X"04",
+X"f0",
+X"02",
+X"46",
+X"01",
+X"a9",
+X"00",
+X"91",
+X"04",
+X"d1",
+X"04",
+X"f0",
+X"02",
+X"46",
+X"01",
+X"c8",
+X"d0",
+X"e9",
+X"e6",
+X"05",
+X"a6",
+X"05",
+X"e4",
+X"06",
+X"d0",
+X"e1",
+X"a9",
+X"23",
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+X"e4",
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+X"18",
+X"60",
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+X"60",
+X"a2",
+X"00",
+X"86",
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+X"ff",
+X"a0",
+X"00",
+X"bd",
+X"d7",
+X"ff",
+X"99",
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+X"c0",
+X"04",
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+X"60",
+X"02",
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+X"ff",
+X"fa",
+X"ff",
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+X"02",
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+X"6c",
+X"18",
+X"c0",
+X"aa",
+X"c2",
+X"2c",
+X"c0"
+
+);
+        signal rdata:std_logic_vector(7 downto 0);
+begin
+        rdata<=ROM(conv_integer(address));
+
+        process(clock)
+        begin
+                if(clock'event and clock='1')then
+                	q<=rdata;
+                end if;
+        end process;
+end syn;
Index: common/zpu/zpu_core.vhd
===================================================================
--- common/zpu/zpu_core.vhd	(nonexistent)
+++ common/zpu/zpu_core.vhd	(revision 1)
@@ -0,0 +1,961 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium                                                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the medium size version.  ----
+----  Supports external memories.                                         ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPUMediumCore(Behave) (Entity and architecture)    ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+--
+-- write_en_o   - set to '1' for a single cycle to send off a write request.
+--                data_o is valid only while write_en_o='1'.
+-- read_en_o    - set to '1' for a single cycle to send off a read request.
+-- mem_busy_i   - It is illegal to send off a read/write request when
+--                mem_busy_i='1'.
+--                Set to '0' when data_i  is valid after a read request.
+--                If it goes to '1'(busy), it is on the cycle after read/
+--                write_en_o is '1'.
+-- addr_o       - address for read/write request
+-- data_i       - read data. Valid only on the cycle after mem_busy_i='0'
+--                after read_en_o='1' for a single cycle.
+-- data_o       - data to write
+-- break_o      - set to '1' when CPU hits break instruction
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.zpupkg.all;
+
+entity ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+end entity ZPUMediumCore;
+
+architecture Behave of ZPUMediumCore is
+   constant BYTE_BITS    : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+   constant WORD_BYTES   : integer:=WORD_SIZE/OPCODE_W;
+   constant MAX_ADDR_BIT : integer:=ADDR_W-2;
+   -- Stack Pointer initial value: BRAM size-8
+   constant SP_START_1   : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
+   constant SP_START     : unsigned(ADDR_W-1 downto BYTE_BITS):=
+                           SP_START_1(ADDR_W-1 downto BYTE_BITS);
+
+   -- Update [SP+1]. We hold it in b_r, this writes the value to memory.
+   procedure FlushB(signal we     : out std_logic;
+                    signal addr   : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal inc_sp : in  unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal data   : out unsigned(WORD_SIZE-1 downto 0);
+                    signal b      : in  unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      we   <= '1';
+      addr <= inc_sp;
+      data <= b;
+   end procedure FlushB;
+
+   -- Do a simple stack push, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Push(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                  signal a      : in    unsigned(WORD_SIZE-1 downto 0);
+                  signal b      : out   unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      b  <= a;      -- Update cache [SP+1]=[SP]
+      sp <= sp-1;
+   end procedure Push;
+
+   -- Do a simple stack pop, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Pop(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                 signal a      : out   unsigned(WORD_SIZE-1 downto 0);
+                 signal b      : in    unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      a  <= b;      -- Update cache [SP]=[SP+1]
+      sp <= sp+1;
+   end procedure Pop;
+
+   -- Expand a PC value to WORD_SIZE
+   function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
+      variable nv : unsigned(WORD_SIZE-1 downto 0);
+   begin
+      nv:=(others => '0');
+      nv(ADDR_W-1 downto 0):=v;
+      return nv;
+   end function ExpandPC;
+
+   -- Program counter
+   signal pc_r          : unsigned(ADDR_W-1 downto 0):=(others => '0');
+   -- Stack pointer
+   signal sp_r          : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
+   -- SP+1, SP+2 and SP-1 are very used, these are shortcuts
+   signal inc_sp        : unsigned(ADDR_W-1 downto BYTE_BITS);
+   signal inc_inc_sp    : unsigned(ADDR_W-1 downto BYTE_BITS);
+   -- a_r is a cache for the top of the stack [SP]
+   -- Note: as this is a stack CPU this is a very important register.
+   signal a_r           : unsigned(WORD_SIZE-1 downto 0);
+   -- b_r is a cache for the next value in the stack [SP+1]
+   signal b_r           : unsigned(WORD_SIZE-1 downto 0);
+   signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_res1_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res2_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res3_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_a_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_b_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal idim_r        : std_logic;
+   signal write_en_r    : std_logic;
+	signal byte_read_r  : std_logic;
+	signal byte_write_r  : std_logic;
+	signal short_write_r : std_logic;
+   signal read_en_r     : std_logic;
+   signal addr_r        : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
+	signal addrl_r        : unsigned(BYTE_BITS-1 downto 0):=(others => '0');
+   signal fetched_w_r   : unsigned(WORD_SIZE-1 downto 0);
+
+   type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
+                   st_fetch, st_execute, st_decode, st_decode2, st_resync,
+                   st_store_sp2, st_resync2, st_resync3, st_loadb2,
+                   st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
+                   st_binary_op_res, st_idle); 
+   signal state : state_t:=st_resync;
+
+   -- Go to st_fetch state or just do its work
+   procedure DoFetch(constant FAST   : boolean;
+                     signal state    : out state_t;
+                     signal addr     : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal pc       : in  unsigned(ADDR_W-1 downto 0);
+                     signal re       : out std_logic;
+                     signal busy     : in  std_logic) is
+   begin
+      if FAST then
+         -- Equivalent to st_fetch
+         if busy='0' then
+            addr  <= pc(ADDR_W-1 downto BYTE_BITS);
+            re    <= '1';
+            state <= st_decode;
+         end if;
+      else
+         state <= st_fetch;
+      end if;
+   end procedure DoFetch;
+
+   -- Perform a "binary operation" (2 operands)
+   procedure DoBinOp(result         : in    unsigned(WORD_SIZE-1 downto 0);
+                     signal state   : out   state_t;
+                     signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal re      : out   std_logic;
+                     signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                     signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                     constant DEPTH :       natural) is
+   begin
+      if DEPTH=2 then
+         -- 2 clocks: st_binary_op_res+st_binary_op_res2
+         state  <= st_binary_op_res;
+         dest_p <= result;
+      elsif DEPTH=1 then
+         -- 1 clock: st_binary_op_res2
+         state  <= st_binary_op_res2;
+         dest_p <= result;
+      else -- 0 clocks
+         re    <= '1';
+         addr  <= sp+2;
+         sp    <= sp+1;
+         dest  <= result;
+         state <= st_popped;
+      end if;
+   end procedure DoBinOp;
+
+   -- Perform a boolean "binary operation" (2 operands)
+   procedure DoBinOpBool(result         : in    boolean;
+                         signal state   : out   state_t;
+                         signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal re      : out   std_logic;
+                         signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                         signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                         constant DEPTH :       natural) is
+      variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   begin
+      if result then
+         res(0):='1';
+      end if;
+      DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
+   end procedure DoBinOpBool;
+
+   type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
+                   dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
+                   dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
+                   dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
+                   dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
+                   dec_less_than, dec_less_than_or_equal, dec_lshr,
+                   dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
+                   dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
+                   dec_insn_fetch, dec_pop_down);
+   signal insn : insn_t;
+   type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
+   signal insns : insn_array_t;
+   type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
+   signal opcode_r : opcode_array_t;
+begin
+   -- the memory subsystem will tell us one cycle later whether or
+   -- not it is busy
+   write_en_o <= write_en_r;
+   read_en_o  <= read_en_r;
+	byte_read_o  <= byte_read_r;
+	byte_write_o  <= byte_write_r;
+	short_write_o  <= short_write_r;
+   addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
+   addr_o(BYTE_BITS-1 downto 0)      <= addrl_r;
+
+   -- SP+1 and +2
+   inc_sp     <= sp_r+1;
+   inc_inc_sp <= sp_r+2;
+
+   opcode_control:
+   process (clk_i)
+      variable topcode     : unsigned(OPCODE_W-1 downto 0);
+      variable ex_opcode   : unsigned(OPCODE_W-1 downto 0);
+      variable sp_offset   : unsigned(4 downto 0);
+      variable tsp_offset  : unsigned(4 downto 0);
+      variable next_pc     : unsigned(ADDR_W-1 downto 0);
+      variable tdecoded    : insn_t;
+      variable tinsns   : insn_array_t;
+      variable mult_res    : unsigned(WORD_SIZE*2-1 downto 0);
+      variable ipc_low     : integer range 0 to 3; -- Address inside a word (pc_r)
+      variable inpc_low    : integer range 0 to 3; -- Address inside a word (next_pc)
+      variable not_lshr    : std_logic:='1';
+   begin
+      if rising_edge(clk_i) then
+         break_o <= '0';
+         if reset_i='1' then
+            if ENA_IDLE then
+               state <= st_idle;
+            else
+               state <= st_resync;
+            end if;
+            sp_r         <= SP_START;
+            pc_r         <= (others => '0');
+            idim_r       <= '0';
+            write_en_r   <= '0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            read_en_r    <= '0';
+            mult_a_r     <= (others => '0');
+            mult_b_r     <= (others => '0');
+            dbg_o.b_inst <= '0';
+            -- Reseting add_r here makes XST fail to use BRAMs ?!
+         else -- reset_i='1'
+            if MULT_PIPE then
+               -- We must multiply unconditionally to get pipelined multiplication
+               mult_res:=mult_a_r*mult_b_r;
+               mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+               mult_res2_r <= mult_res1_r;
+               mult_res3_r <= mult_res2_r;
+               mult_a_r    <= (others => D_CARE_VAL);
+               mult_b_r    <= (others => D_CARE_VAL);
+            end if;
+
+            if BINOP_PIPE=2 then
+               bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
+            end if;
+   
+            read_en_r  <='0';
+            write_en_r <='0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            -- Allow synthesis tools to load bogus values when we don't
+            -- care about the address and output data.
+            addr_r     <= (others => D_CARE_VAL);
+            data_o     <= (others => D_CARE_VAL);
+				addrl_r    <= "00";
+   
+            if (write_en_r='1') and (read_en_r='1') then
+               report "read/write collision" severity failure;
+            end if;
+
+            ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
+            sp_offset(4):=not opcode_r(ipc_low)(4);
+            sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
+            next_pc:=pc_r+1;
+   
+            -- Prepare trace snapshot
+            dbg_o.opcode <= opcode_r(ipc_low);
+            dbg_o.pc     <= resize(pc_r,32);
+            dbg_o.stk_a  <= resize(a_r,32);
+            dbg_o.stk_b  <= resize(b_r,32);
+            dbg_o.b_inst <= '0';
+            dbg_o.sp     <= (others => '0');
+            dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+   
+            case state is
+                 when st_idle =>
+                      if enable_i='1' then
+                         state <= st_resync;
+                      end if;
+                 -- Initial state of ZPU, fetch top of stack (A/B) + first instruction
+                 when st_resync =>
+                      if mem_busy_i='0' then
+                         addr_r    <= sp_r;
+                         read_en_r <= '1';
+                         state     <= st_resync2;
+                      end if;
+                 when st_resync2 =>
+                      if mem_busy_i='0' then
+                         a_r       <= data_i;
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_resync3;
+                      end if;
+                 when st_resync3 =>
+                      if mem_busy_i='0' then
+                         b_r       <= data_i;
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 when st_decode =>
+                      if mem_busy_i='0' then
+                         -- Here we latch the fetched word to give one full clock
+                         -- cycle to the instruction decoder. This could be removed
+                         -- if using BRAMs and the decoder delay isn't important.
+                         fetched_w_r <= data_i;
+                         state       <= st_decode2;
+                      end if;
+                 when st_decode2 =>
+                      -- decode 4 instructions in parallel
+                      for i in 0 to WORD_BYTES-1 loop
+                          topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
+
+                          tsp_offset(4):=not topcode(4);
+                          tsp_offset(3 downto 0):=topcode(3 downto 0);
+
+                          opcode_r(i) <= topcode;
+                          if topcode(7 downto 7)=OPCODE_IM then
+                             tdecoded:=dec_im;
+                          elsif topcode(7 downto 5)=OPCODE_STORESP then
+                             if tsp_offset=0 then
+                                -- Special case, we can avoid a write
+                                tdecoded:=dec_pop;
+                             elsif tsp_offset=1 then
+                                -- Special case, collision
+                                tdecoded:=dec_pop_down;
+                             else
+                                tdecoded:=dec_store_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_LOADSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_dup;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_dup_stk_b;
+                             else
+                                tdecoded:=dec_load_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_EMULATE then
+                             tdecoded:=dec_emulate;
+                             if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
+                                tdecoded:=dec_neq_branch;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
+                                tdecoded:=dec_eq;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
+                                tdecoded:=dec_loadb;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
+                                tdecoded:=dec_push_sp_add;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
+                                tdecoded:=dec_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
+                                tdecoded:=dec_u_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
+                                tdecoded:=dec_mult;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
+                                tdecoded:=dec_storeb;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
+                                tdecoded:=dec_call_pc_rel;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
+                                tdecoded:=dec_sub;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+                                tdecoded:=dec_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+                                tdecoded:=dec_u_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
+                                tdecoded:=dec_call;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
+                                tdecoded:=dec_pop_pc_rel;
+                             elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+                                tdecoded:=dec_lshr;
+                             end if;
+                          elsif topcode(7 downto 4)=OPCODE_ADDSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_shift;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_add_top;
+                             else
+                                tdecoded:=dec_add_sp;
+                             end if;
+                          else -- OPCODE_SHORT
+                             case topcode(3 downto 0) is
+                                  when OPCODE_BREAK =>
+                                       tdecoded:=dec_break;
+                                  when OPCODE_PUSHSP =>
+                                       tdecoded:=dec_push_sp;
+                                  when OPCODE_POPPC =>
+                                       tdecoded:=dec_pop_pc;
+                                  when OPCODE_ADD =>
+                                       tdecoded:=dec_add;
+                                  when OPCODE_OR =>
+                                       tdecoded:=dec_or;
+                                  when OPCODE_AND =>
+                                       tdecoded:=dec_and;
+                                  when OPCODE_LOAD =>
+                                       tdecoded:=dec_load;
+                                  when OPCODE_NOT =>
+                                       tdecoded:=dec_not;
+                                  when OPCODE_FLIP =>
+                                       tdecoded:=dec_flip;
+                                  when OPCODE_STORE =>
+                                       tdecoded:=dec_store;
+                                  when OPCODE_POPSP =>
+                                       tdecoded:=dec_pop_sp;
+                                  when others => -- OPCODE_NOP and others
+                                       tdecoded:=dec_nop;
+                             end case;
+                          end if;
+                          tinsns(i):=tdecoded;
+                      end loop;
+                      
+                      insn <= tinsns(ipc_low);
+                      -- once we wrap, we need to fetch
+                      tinsns(0):=dec_insn_fetch;
+                      insns <= tinsns;
+                      state <= st_execute;
+
+                      -- Each instruction must:
+                      --
+                      -- 1. increase pc_r if applicable
+                      -- 2. set next state if applicable
+                      -- 3. do it's operation
+                 when st_execute =>
+                      -- Some shortcut to make the code readable:
+                      inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
+                      ex_opcode:=opcode_r(ipc_low);
+							 
+							 if (mem_busy_i = '0') then -- MWW, do not move on until mem is not busy!
+							 insn <= insns(inpc_low);
+							 
+                      -- Defaults used by most instructions
+                      if insn/=dec_insn_fetch and insn/=dec_im then
+                         dbg_o.b_inst <= '1';
+                         idim_r       <= '0';
+                      end if;
+							
+							case insn is
+                           when dec_insn_fetch =>
+                                -- Not a real instruction, fetch new instructions
+                                DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
+                           when dec_im =>
+                                -- Push(immediate value), IDIM=1
+                                -- if IDIM=0 Push(signed(opcode & 0x7F)) else
+                                --           Push((Pop()<<7)|(opcode&0x7F))
+                                if mem_busy_i='0' then
+                                   dbg_o.b_inst <= '1';
+                                   idim_r       <= '1';
+                                   pc_r             <= pc_r+1;
+                                   if idim_r='1' then
+                                      -- We already started an IM sequence
+                                      -- Shift left 7 bits
+                                      a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
+                                      -- Put the new value
+                                      a_r(6 downto 0) <= ex_opcode(6 downto 0);
+                                   else
+                                      -- First IM, push the value sign extended
+                                      FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                      a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
+                                      Push(sp_r,a_r,b_r);
+                                   end if;
+                                end if;
+                           when dec_store_sp =>
+                                -- [SP+Offset]=Pop()
+                                if mem_busy_i='0' then
+                                   write_en_r <= '1';
+                                   addr_r     <= sp_r+sp_offset;
+                                   data_o     <= a_r;
+                                   Pop(sp_r,a_r,b_r);
+                                   -- We need to fetch B
+                                   state      <= st_store_sp2;
+                                end if;
+                           when dec_load_sp =>
+                                -- Push([SP+Offset])
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   Push(sp_r,a_r,b_r);
+                                   -- We are flushing B cache, so we need more time to
+                                   -- read the value.
+                                   state <= st_load_sp2;
+                                end if;
+                           when dec_emulate =>
+                                -- Push(PC+1), PC=Opcode[4:0]*32
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   Push(sp_r,a_r,b_r);
+                                   -- The emulate address is:
+                                   --        98 7654 3210
+                                   -- 0000 00aa aaa0 0000
+                                   pc_r             <= (others => '0');
+                                   pc_r(9 downto 5) <= ex_opcode(4 downto 0);
+                                end if;
+                           when dec_call_pc_rel =>
+                                -- t=Pop(), Push(PC+1), PC=PC+t
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= pc_r+a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_call =>
+                                -- t=Pop(), Push(PC+1), PC=t
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_add_sp =>
+                                -- Push(Pop()+[SP+Offset])
+                                if mem_busy_i='0' then
+                                   -- Read SP+Offset
+                                   state     <= st_add_sp2;
+                                   read_en_r <= '1';
+                                   addr_r    <= sp_r+sp_offset;
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_push_sp =>
+                                -- Push(SP)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+                                   Push(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_pc =>
+                                -- PC=Pop() (return)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_pop_pc_rel =>
+                                -- PC=PC+Pop()
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_add =>
+                                -- Push(Pop()+Pop())  [A=A+B, SP++, update B]
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r+b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_sub =>
+                                -- a=Pop(), b=Pop(), Push(b-a)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
+                                           a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_pop =>
+                                -- Pop()
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   Pop(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_down =>
+                                -- t=Pop(), Pop(), Push(t)
+                                if mem_busy_i='0' then
+                                   -- PopDown leaves top of stack unchanged
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_or =>
+                                -- Push(Pop() or Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r or b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_and =>
+                                -- Push(Pop() and Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r and b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_eq =>
+                                -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than =>
+                                -- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than_or_equal =>
+                                -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_less_than =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_less_than_or_equal =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_load =>
+                                -- Push([Pop()])
+                                if mem_busy_i='0' then
+                                   state     <= st_load2;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   read_en_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_dup =>
+                                -- t=Pop(), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   -- A is dupped, no change
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_dup_stk_b =>
+                                -- Pop(), t=Pop(), Push(t), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= b_r;
+                                   -- B goes to A
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_store =>
+                                -- a=Pop(), b=Pop(), [a]=b
+                                if mem_busy_i='0' then
+                                   state      <= st_resync;
+                                   pc_r       <= pc_r+1;
+                                   addr_r     <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   data_o     <= b_r;
+                                   write_en_r <= '1';
+                                   sp_r       <= inc_inc_sp;
+                                end if;
+                           when dec_pop_sp =>
+                                -- SP=Pop()
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= pc_r+1;
+                                   sp_r  <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                end if;
+                           when dec_nop =>
+                                pc_r <= pc_r+1;
+                           when dec_not =>
+                                -- Push(not(Pop()))
+                                pc_r <= pc_r+1;
+                                a_r  <= not a_r;
+                           when dec_flip =>
+                                -- Push(flip(Pop()))
+                                pc_r <= pc_r+1;
+                                for i in 0 to WORD_SIZE-1 loop
+                                    a_r(i) <= a_r(WORD_SIZE-1-i);
+                                end loop;
+                           when dec_add_top =>
+                                -- a=Pop(), b=Pop(), Push(b), Push(a+b)
+                                pc_r <= pc_r+1;
+                                a_r  <= a_r+b_r;
+                           when dec_shift =>
+                                -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
+                                pc_r <= pc_r+1;
+                                a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
+                                a_r(0) <= '0';
+                           when dec_push_sp_add =>
+                                -- Push(Pop()+SP)
+                                if ENA_LEVEL0 then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <=
+                                      a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
+                                end if;
+                           when dec_neq_branch =>
+                                -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
+                                -- Branches are almost always taken as they form loops
+                                if ENA_LEVEL0 then
+                                   sp_r  <= inc_inc_sp;
+                                   -- Need to fetch stack again.
+                                   state <= st_resync;
+                                   if b_r/=0 then
+                                      pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   else
+                                      pc_r <= pc_r+1;
+                                   end if;
+                                end if;
+                           when dec_mult =>
+                                -- Push(Pop()*Pop())
+                                if ENA_LEVEL1 then
+                                   if MULT_PIPE then
+                                      mult_a_r <= a_r;
+                                      mult_b_r <= b_r;
+                                      state    <= st_mult2;
+                                   else
+                                      mult_res:=a_r*b_r;
+                                      mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+                                      state       <= st_mult5;
+                                   end if;
+                                end if;
+                           when dec_break =>
+                                -- Assert the break_o signal
+                                --report "Break instruction encountered" severity failure;
+                                break_o <= '1';
+                                pc_r    <= pc_r+1;
+                           when dec_loadb =>
+                                -- Push([Pop()] & 0xFF) (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   state     <= st_loadb2;                                   
+											  addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --read_en_r <= '1';
+											  byte_read_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_storeb =>
+                                -- [Pop()]=Pop() & 0xFF (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state     <= st_resync;
+											  sp_r       <= inc_inc_sp;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --write_en_r <= '1';
+											  byte_write_r <= '1';
+                                   pc_r      <= pc_r+1;
+											  --data_o(WORD_SIZE-1 downto 8) <= (others=>'0');
+											  --data_o(7 downto 0) <= b_r(7 downto 0);										  
+											  data_o(WORD_SIZE-1 downto 0) <= b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0);										  
+                                end if;
+                           when dec_lshr =>
+                                -- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
+                                if ENA_LSHR then
+                                   -- This instruction takes more than one cycle.
+                                   -- We must avoid duplications in the trace log.
+                                   dbg_o.b_inst <= not_lshr;
+                                   not_lshr:='0';
+                                   if a_r(5 downto 0)=0 then -- Only 6 bits used
+                                      -- No more shifts
+                                      if mem_busy_i='0' then
+                                         state     <= st_popped;
+                                         a_r       <= b_r;
+                                         read_en_r <= '1';
+                                         addr_r    <= inc_inc_sp;
+                                         sp_r      <= inc_sp;
+                                         not_lshr:='1';
+                                      end if;
+                                   else -- More shifts needed
+                                      b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
+                                      a_r(5 downto 0) <= a_r(5 downto 0)-1;
+                                      insn <= insn;
+                                   end if;
+                                end if;
+                           when others =>
+                                -- Undefined behavior, we shouldn't get here.
+                                -- It only helps synthesis tools.
+                                sp_r <= (others => D_CARE_VAL);
+                                report "Illegal decode instruction?!" severity failure;
+                                --break_o <= '1';
+                      end case;
+							 end if;
+                 -- The followup of operations that takes more than one execution clock
+                 when st_store_sp2 =>
+                      if mem_busy_i='0' then
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_popped;
+                      end if;
+                 when st_load_sp2 =>
+                      if mem_busy_i='0' then
+                         state     <= st_load_sp3;
+                         -- Now we can read SP+Offset (SP already decremented)
+                         read_en_r <= '1';
+                         addr_r    <= sp_r+sp_offset+1;
+                      end if;
+                 when st_load_sp3 =>
+                      if mem_busy_i='0' then
+                         -- Note: We can't increment PC in the decode stage
+                         -- because it will modify sp_offset.
+                         pc_r  <= pc_r+1;
+                         -- Finally we have the result in A
+                         state <= st_execute;
+                         a_r   <= data_i;
+                      end if;
+                 when st_add_sp2 =>
+                      if mem_busy_i='0' then
+                         state <= st_execute;
+                         a_r   <= a_r+data_i;
+                      end if;
+                 when st_load2 =>
+                      if mem_busy_i='0' then
+                         a_r   <= data_i;
+                         state <= st_execute;
+                      end if;
+                 when st_loadb2 =>
+                      if mem_busy_i='0' then
+                         a_r(WORD_SIZE-1 downto 8) <= (others => '0');								 
+								 a_r(7 downto 0) <= data_i(7 downto 0);
+                         state <= st_execute;
+                      end if;
+                 when st_fetch =>
+                      if mem_busy_i='0' then
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 -- The following states can be used to leave cycles free for
+                 -- tools that can automagically decompose the multiplication
+                 -- in various stages. Xilinx tools can do it to increase the
+                 -- multipliers performance.
+                 when st_mult2 =>
+                      state <= st_mult3;
+                 when st_mult3 =>
+                      state <= st_mult4;
+                 when st_mult4 =>
+                      state <= st_mult5;
+                 when st_mult5 =>
+                      if mem_busy_i='0' then
+                         if MULT_PIPE then
+                            a_r <= mult_res3_r;
+                         else
+                            a_r <= mult_res1_r;
+                         end if;
+                         read_en_r <= '1';
+                         addr_r    <= inc_inc_sp;
+                         sp_r      <= inc_sp;
+                         state     <= st_popped;
+                      end if;
+               when st_binary_op_res =>
+                    -- BINOP_PIPE=2
+                    state <= st_binary_op_res2;
+               when st_binary_op_res2 =>
+                    -- BINOP_PIPE>=1
+                    read_en_r <= '1';
+                    addr_r    <= inc_inc_sp;
+                    sp_r      <= inc_sp;
+                    state     <= st_popped;
+                    if BINOP_PIPE=2 then
+                       a_r <= bin_op_res2_r;
+                    else -- 1
+                       a_r <= bin_op_res1_r;
+                    end if;
+               when st_popped =>
+                    if mem_busy_i='0' then
+                       -- Note: Moving this PC++ to the decoder seems to
+                       -- consume more LUTs.
+                       pc_r  <= pc_r+1;
+                       b_r   <= data_i;
+                       state <= st_execute;
+                    end if;
+               when others =>
+                    -- Undefined behavior, we shouldn't get here.
+                    -- It only helps synthesis tools.
+                    sp_r <= (others => D_CARE_VAL);
+                    report "Illegal state?!" severity failure;
+                    --break_o <= '1';
+            end case; -- state
+         end if; -- else reset_i='1'
+      end if; -- rising_edge(clk_i)
+   end process opcode_control;
+end architecture Behave; -- Entity: ZPUMediumCore
+
Index: de1/CHANGELOG
===================================================================
--- de1/CHANGELOG	(nonexistent)
+++ de1/CHANGELOG	(revision 1)
@@ -0,0 +1,3 @@
+Version 1
+---------
+Initial source release
Index: de1/atari800core.qsf
===================================================================
--- de1/atari800core.qsf	(nonexistent)
+++ de1/atari800core.qsf	(revision 1)
@@ -0,0 +1,626 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_CE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_LB_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_OE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_UB_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_WE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[0]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[1]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[2]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[3]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[4]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[5]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[6]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[7]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[8]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[9]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[10]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[11]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[12]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[13]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[14]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[15]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[16]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[17]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[0]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[1]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[2]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[3]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[4]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[5]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[6]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[7]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[8]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[9]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[10]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[11]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[12]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[13]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[14]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[15]
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_V20 -to SD_CLK
+set_location_assignment PIN_Y20 -to SD_CMD
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_W20 -to SD_DATA
+set_location_assignment PIN_U20 -to SD_THREE
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name VHDL_FILE ledsw.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE dumprom.vhdl
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE nmigen.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE tvsync.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE flashrom.vhdl
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: de1/defunct/flashrom.vhdl
===================================================================
--- de1/defunct/flashrom.vhdl	(nonexistent)
+++ de1/defunct/flashrom.vhdl	(revision 1)
@@ -0,0 +1,63 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY flashrom IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+
+	ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+	
+	REQUEST : IN STD_LOGIC;
+
+	-- takes 90+ns, wait states handled here
+	
+	-- Flash interface
+	FLASH_D : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	FLASH_CE_N : OUT STD_LOGIC;
+	FLASH_OE_N : OUT STD_LOGIC;
+	FLASH_WE_N : OUT STD_LOGIC;
+	FLASH_RESET_N : OUT STD_LOGIC;
+	FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	COMPLETE : OUT STD_LOGIC
+);
+
+END flashrom;
+
+ARCHITECTURE vhdl OF flashrom IS
+	signal complete_next : std_logic_vector(4 downto 0); --56MHZ, 17ns per cycle.
+	signal complete_reg : std_logic_vector(4 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			complete_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			complete_reg <= complete_next;
+		end if;
+	end process;
+	
+	complete_next <= request&complete_reg(complete_reg'left downto 1);
+
+	FLASH_CE_N <= '0';
+	FLASH_OE_N <= '0';
+	FLASH_WE_N <= '1';
+	FLASH_RESET_N <= RESET_N;
+	FLASH_ADDRESS <= ADDRESS;
+	
+	DOUT <= FLASH_D;
+	COMPLETE <= complete_reg(0);
+END vhdl;
\ No newline at end of file
Index: de1/i2s_intf.vhd
===================================================================
--- de1/i2s_intf.vhd	(nonexistent)
+++ de1/i2s_intf.vhd	(revision 1)
@@ -0,0 +1,183 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+-- Modified by Mark Watson for the Atari800
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity i2s_intf is
+generic(
+   inclk_rate : positive := 25000000;
+	sample_rate : positive := 8000;
+	preamble : positive := 1; -- I2S
+	word_length : positive := 16
+	);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	-- Parallel IO
+	PCM_INL		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_INR		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTL	:	in	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTR	:	in	std_logic_vector(word_length - 1 downto 0);
+	
+	-- Codec interface (right justified mode)
+	-- LRCLK is equal to the sample rate and is synchronous to
+	-- MCLK.  It must be related to MCLK by the oversampling ratio
+	-- given in the codec datasheet.
+	I2S_LRCLK	:	out	std_logic;
+	
+	-- Data is shifted out on the falling edge of BCLK, sampled
+	-- on the rising edge.  The bit rate is determined such that
+	-- it is fast enough to fit preamble + word_length bits into
+	-- each LRCLK half cycle.  The last cycle of each word may be 
+	-- stretched to fit to LRCLK.  This is OK at least for the 
+	-- WM8731 codec.
+	-- The first falling edge of each timeslot is always synchronised
+	-- with the LRCLK edge.
+	I2S_BCLK	:	out	std_logic;
+	-- Output bitstream
+	I2S_DOUT	:	out	std_logic;
+	-- Input bitstream
+	I2S_DIN		:	in	std_logic
+	);
+end i2s_intf;
+
+architecture i2s_intf_arch of i2s_intf is
+constant ratio_mclk_fs : positive := (inclk_rate / sample_rate);
+constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
+constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
+constant nbits : positive := preamble + word_length;
+
+subtype lrdivider_t is integer range 0 to lrdivider_top;
+subtype bdivider_t is integer range 0 to bdivider_top;
+subtype bitcount_t is integer range 0 to nbits;
+
+signal lrdivider : lrdivider_t; 
+signal bdivider : bdivider_t;
+signal bitcount : bitcount_t;
+
+signal lrclk_r : std_logic;
+signal bclk_r : std_logic;
+
+-- Shift register is long enough for the number of data bits
+-- plus the preamble, plus an extra bit on the right to register
+-- the incoming data
+signal shiftreg : std_logic_vector(nbits downto 0);
+begin
+	I2S_LRCLK <= lrclk_r;
+	I2S_BCLK <= bclk_r;
+	I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
+
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			PCM_INL <= (others => '0');
+			PCM_INR <= (others => '0');
+						
+			-- Preload down-counters for clock generation
+			lrdivider <= lrdivider_top;
+			bdivider <= bdivider_top;
+			bitcount <= nbits;
+			
+			lrclk_r <= '0';
+			bclk_r <= '0';
+			shiftreg <= (others => '0');
+		elsif rising_edge(CLK) then		
+			-- Generate LRCLK at rate specified by codec configuration
+			if lrdivider = 0 then
+				-- LRCLK divider has reached 0 - start again from the top
+				lrdivider <= lrdivider_top;
+				
+				-- Generate LRCLK edge and sync the BCLK counter
+				lrclk_r <= not lrclk_r;
+				bclk_r <= '0';
+				bitcount <= nbits; -- 1 extra required for setup
+				bdivider <= bdivider_top;
+				
+				-- Load shift register with output data padding preamble
+				-- with 0s.  Load output buses with input word from the 
+				-- previous timeslot.
+				shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
+				if lrclk_r = '0' then
+					-- Previous channel input is LEFT.  This is available in the
+					-- shift register at the end of a cycle, right justified
+					PCM_INL <= shiftreg(word_length - 1 downto 0);
+					-- Next channel to output is RIGHT.  Load this into the
+					-- shift register at the start of a cycle, left justified
+					shiftreg(word_length downto 1) <= PCM_OUTR;
+				else
+					-- Previous channel input is RIGHT
+					PCM_INR <= shiftreg(word_length - 1 downto 0);
+					-- Next channel is LEFT
+					shiftreg(word_length downto 1) <= PCM_OUTL;
+				end if;
+			else
+				-- Decrement the LRCLK counter
+				lrdivider <= lrdivider - 1;
+				
+				-- Generate BCLK at a suitable rate to fit the required number
+				-- of bits into each timeslot.  Data is changed on the falling edge,
+				-- sampled on the rising edge
+				if bdivider = 0 then
+					-- If all bits have been output for this phase then
+					-- stop and wait to sync back up with LRCLK
+					if bitcount > 0 then
+						-- Reset
+						bdivider <= bdivider_top;
+						
+						-- Toggle BCLK
+						bclk_r <= not bclk_r;
+						if bclk_r = '0' then
+							-- Rising edge - shift in current bit and decrement bit counter
+							bitcount <= bitcount - 1;
+							shiftreg(0) <= I2S_DIN;
+						else
+							-- Falling edge - shift out next bit
+							shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
+						end if;
+					end if;
+				else
+					-- Decrement the BCLK counter
+					bdivider <= bdivider - 1;
+				end if;
+			end if;
+			
+		end if;
+	end process;
+end i2s_intf_arch;
+
Index: de1/pll.ppf
===================================================================
--- de1/pll.ppf	(nonexistent)
+++ de1/pll.ppf	(revision 1)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: de1/zpu_config_regs.vhdl
===================================================================
--- de1/zpu_config_regs.vhdl	(nonexistent)
+++ de1/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,501 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(1 downto 0);
+	signal ram_select_reg : std_logic_vector(1 downto 0);
+	signal rom_select_next : std_logic_vector(1 downto 0);
+	signal rom_select_reg : std_logic_vector(1 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				rom_select_reg <= "01";
+				ram_select_reg <= "10";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(9 downto 8);
+				rom_select_next <= cpu_DATA_IN(13 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(9 downto 8) <= ram_select_reg;
+				data_out(13 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= SWITCH;
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= KEY;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				--data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= switch(6);
+	USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= switch(9);
+	COMPOSITE_ON_HSYNC <= switch(8);
+	GPIO_ENABLE <= gpio_enable_reg; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+end vhdl;
+
+
Index: mcc216/atari800core.qsf
===================================================================
--- mcc216/atari800core.qsf	(nonexistent)
+++ mcc216/atari800core.qsf	(revision 1)
@@ -0,0 +1,348 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_134 -to VGA_R[1]
+set_location_assignment PIN_133 -to VGA_R[2]
+set_location_assignment PIN_132 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_G[0]
+set_location_assignment PIN_142 -to VGA_G[1]
+set_location_assignment PIN_143 -to VGA_G[2]
+set_location_assignment PIN_144 -to VGA_G[3]
+set_location_assignment PIN_4 -to VGA_B[0]
+set_location_assignment PIN_7 -to VGA_B[1]
+set_location_assignment PIN_10 -to VGA_B[2]
+set_location_assignment PIN_11 -to VGA_B[3]
+set_location_assignment PIN_136 -to VGA_HS
+set_location_assignment PIN_137 -to VGA_VS
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_44 -to SD_CLK
+set_location_assignment PIN_46 -to SD_CMD
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_location_assignment PIN_28 -to AUDIO_L
+set_location_assignment PIN_30 -to AUDIO_R
+set_location_assignment PIN_53 -to CPU_RESET_n
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_127 -to JOY1_n[0]
+set_location_assignment PIN_91 -to JOY1_n[1]
+set_location_assignment PIN_90 -to JOY1_n[2]
+set_location_assignment PIN_88 -to JOY1_n[3]
+set_location_assignment PIN_89 -to JOY1_n[4]
+set_location_assignment PIN_126 -to JOY1_n[5]
+set_location_assignment PIN_128 -to JOY2_n[0]
+set_location_assignment PIN_25 -to JOY2_n[1]
+set_location_assignment PIN_24 -to JOY2_n[2]
+set_location_assignment PIN_22 -to JOY2_n[3]
+set_location_assignment PIN_23 -to JOY2_n[4]
+set_location_assignment PIN_129 -to JOY2_n[5]
+set_location_assignment PIN_33 -to PS2K_DAT
+set_location_assignment PIN_39 -to PS2K_CLK
+set_location_assignment PIN_32 -to PS2M_DAT
+set_location_assignment PIN_31 -to PS2M_CLK
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_49 -to SD_DAT3
+set_location_assignment PIN_42 -to USB_P
+set_location_assignment PIN_43 -to USB_N
+set_location_assignment PIN_50 -to USB2_P
+set_location_assignment PIN_51 -to USB2_N
+set_location_assignment PIN_112 -to SDRAM_CLK
+set_location_assignment PIN_61 -to SDRAM_A[0]
+set_location_assignment PIN_60 -to SDRAM_A[1]
+set_location_assignment PIN_59 -to SDRAM_A[2]
+set_location_assignment PIN_58 -to SDRAM_A[3]
+set_location_assignment PIN_125 -to SDRAM_A[4]
+set_location_assignment PIN_121 -to SDRAM_A[5]
+set_location_assignment PIN_120 -to SDRAM_A[6]
+set_location_assignment PIN_119 -to SDRAM_A[7]
+set_location_assignment PIN_115 -to SDRAM_A[8]
+set_location_assignment PIN_114 -to SDRAM_A[9]
+set_location_assignment PIN_64 -to SDRAM_A[10]
+set_location_assignment PIN_113 -to SDRAM_A[11]
+set_location_assignment PIN_111 -to SDRAM_A[12]
+set_location_assignment PIN_66 -to SDRAM_BA[0]
+set_location_assignment PIN_65 -to SDRAM_BA[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_79 -to SDRAM_DQ[5]
+set_location_assignment PIN_77 -to SDRAM_DQ[6]
+set_location_assignment PIN_76 -to SDRAM_DQ[7]
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_67 -to SDRAM_CS_n
+set_location_assignment PIN_68 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_CAS_n
+set_location_assignment PIN_71 -to SDRAM_WE_n
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_13 -to CFG_DIN
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
+set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
+
+
+set_global_assignment -name VERILOG_FILE hq_dac.v
+set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+set_global_assignment -name VHDL_FILE romlo.vhd
+set_global_assignment -name VHDL_FILE romhi.vhd
+set_global_assignment -name VHDL_FILE ramint.vhd
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name VHDL_FILE internalromram.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: mcc216/pll.bsf
===================================================================
--- mcc216/pll.bsf	(nonexistent)
+++ mcc216/pll.bsf	(revision 1)
@@ -0,0 +1,100 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 248 184)
+	(text "pll" (rect 118 0 133 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 248 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 232 50 242 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 248 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 232 66 240 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 248 96)
+		(output)
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 232 82 242 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 248 112)
+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 213 98 242 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 186 168 417 347)(font "Arial" ))
+		(text "inclk0 frequency: 5.000 MHz" (rect 50 59 218 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "23/2" (rect 74 107 164 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "23/2" (rect 74 121 164 253)(font "Arial" ))
+		(text "0.00" (rect 104 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(text "c2" (rect 54 135 116 281)(font "Arial" ))
+		(text "23/2" (rect 74 135 164 281)(font "Arial" ))
+		(text "0.00" (rect 104 135 224 281)(font "Arial" ))
+		(text "50.00" (rect 136 135 293 281)(font "Arial" ))
+		(line (pt 0 0)(pt 249 0))
+		(line (pt 249 0)(pt 249 185))
+		(line (pt 0 185)(pt 249 185))
+		(line (pt 0 0)(pt 0 185))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 146)(pt 164 146))
+		(line (pt 48 91)(pt 48 146))
+		(line (pt 69 91)(pt 69 146)(line_width 3))
+		(line (pt 95 91)(pt 95 146)(line_width 3))
+		(line (pt 129 91)(pt 129 146)(line_width 3))
+		(line (pt 163 91)(pt 163 146))
+		(line (pt 40 48)(pt 199 48))
+		(line (pt 199 48)(pt 199 167))
+		(line (pt 40 167)(pt 199 167))
+		(line (pt 40 48)(pt 40 167))
+		(line (pt 247 64)(pt 199 64))
+		(line (pt 247 80)(pt 199 80))
+		(line (pt 247 96)(pt 199 96))
+		(line (pt 247 112)(pt 199 112))
+	)
+)
Index: mcc216/pll.vhd
===================================================================
--- mcc216/pll.vhd	(nonexistent)
+++ mcc216/pll.vhd	(revision 1)
@@ -0,0 +1,424 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 2,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 2,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 2,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: common/zpu/zpu_config_regs.vhdl
===================================================================
--- common/zpu/zpu_config_regs.vhdl	(nonexistent)
+++ common/zpu/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,515 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(2 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+	
+	-- sector buffer
+	sector : out std_logic_vector(31 downto 0);
+	sector_request : out std_logic;
+	sector_ready : in std_logic;
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(2 downto 0);
+	signal ram_select_reg : std_logic_vector(2 downto 0);
+	signal rom_select_next : std_logic_vector(1 downto 0);
+	signal rom_select_reg : std_logic_vector(1 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+	
+	signal sector_next : std_logic_vector(31 downto 0);
+	signal sector_reg : std_logic_vector(31 downto 0);
+	signal sector_request_next : std_logic;
+	signal sector_request_reg : std_logic; -- cleared when ready asserted
+
+	signal spi_addr_reg_integer : integer;
+	signal spi_speed_reg_integer : integer;
+	signal wr_en_pokey : std_logic;
+	
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"001111"; -- reset_6502, halt_6502, run_every 16 cycles
+				rom_select_reg <= "01";
+				ram_select_reg <= "010";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+				
+				sector_reg <= (others=>'0');
+				sector_request_reg <= '0';
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+				
+				sector_reg <= sector_next;
+				sector_request_reg <= sector_request_next;				
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	wr_en_pokey <= addr(4) and wr_en;
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>wr_en_pokey, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	-- SECTOR
+	--   W(32 bits) - write here initiates a request_reset_zpu
+	--   R: 0=request_active
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		sector_next <= sector_reg;
+		sector_request_next <= sector_request_reg and not(sector_ready);
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(10 downto 8);
+				rom_select_next <= cpu_DATA_IN(13 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+			if(addr_decoded(11) = '1') then
+				sector_next <= cpu_data_in;
+				sector_request_next <= '1';
+			end if;
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(10 downto 8) <= ram_select_reg;
+				data_out(13 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= key;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				--data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+			
+			if (addr_decoded(11) = '1') then
+				data_out(0) <= sector_request_reg;
+			end if;			
+			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1'; -- TODO
+	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	--USE_SDRAM <= '0'; -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= '1';
+	COMPOSITE_ON_HSYNC <= '0';
+	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= "01";--rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+	
+	sector <= sector_reg;
+	sector_request <= sector_request_reg;
+end vhdl;
+
+
Index: common/zpu/zpupkg.vhd
===================================================================
--- common/zpu/zpupkg.vhd	(nonexistent)
+++ common/zpu/zpupkg.vhd	(revision 1)
@@ -0,0 +1,292 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Package                                                         ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the package.              ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      zpupkg, UART (Package)                             ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpupkg is
+   constant OPCODE_W : integer:=8;
+
+   -- Debug structure, currently only for the trace module
+   type zpu_dbgo_t is record
+      b_inst : std_logic;
+      opcode : unsigned(OPCODE_W-1 downto 0);
+      pc     : unsigned(31 downto 0);
+      sp     : unsigned(31 downto 0);
+      stk_a  : unsigned(31 downto 0);
+      stk_b  : unsigned(31 downto 0);
+   end record;
+
+   component Trace is
+      generic(
+         LOG_FILE   : string:="trace.txt"; -- Name of the trace file
+         ADDR_W     : integer:=16;  -- Address width
+         WORD_SIZE  : integer:=32); -- 16/32
+      port(
+         clk_i      : in std_logic;
+         dbg_i      : in zpu_dbgo_t;
+         stop_i     : in std_logic;
+         busy_i     : in std_logic
+         );
+   end component Trace;
+
+   component ZPUSmallCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'); -- Value used to fill the unsused bits
+      port(
+         clk_i        : in  std_logic; -- System Clock
+         reset_i      : in  std_logic; -- Synchronous Reset
+         interrupt_i  : in  std_logic; -- Interrupt
+         break_o      : out std_logic; -- Breakpoint opcode executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- BRAM (text, data, bss and stack)
+         a_we_o       : out std_logic; -- BRAM A port Write Enable
+         a_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+         a_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+         a_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+         b_we_o       : out std_logic; -- BRAM B port Write Enable
+         b_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+         b_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+         b_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+         -- Memory mapped I/O
+         mem_busy_i   : in  std_logic;
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0);
+         data_o       : out unsigned(WORD_SIZE-1 downto 0);
+         addr_o       : out unsigned(ADDR_W-1 downto 0);
+         write_en_o   : out std_logic;
+         read_en_o    : out std_logic);
+   end component ZPUSmallCore;
+
+   component ZPUMediumCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+         MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+         BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+         ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+         ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+         ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+         ENA_LSHR     : boolean:=true;  -- lshiftright
+         ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+         FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+      port(
+         clk_i        : in  std_logic; -- CPU Clock
+         reset_i      : in  std_logic; -- Sync Reset
+         enable_i     : in  std_logic; -- Hold the CPU (after reset)
+         break_o      : out std_logic; -- Break instruction executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- Memory interface
+         mem_busy_i   : in  std_logic; -- Memory is busy
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+         data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+         addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+         write_en_o   : out std_logic;  -- Memory write enable
+         read_en_o    : out std_logic); -- Memory read enable
+   end component ZPUMediumCore;
+
+   component Timer is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned(0 downto 0);
+         data_o   : out unsigned(31 downto 0));
+   end component Timer;
+
+   component gpio is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         --
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned( 0 downto 0);
+         data_o   : out unsigned(31 downto 0);
+         --
+         port_in  : in  std_logic_vector(31 downto 0);
+         port_out : out std_logic_vector(31 downto 0);
+         port_dir : out std_logic_vector(31 downto 0)
+         );
+   end component gpio;
+
+
+   component ZPUPhiIO is
+      generic(
+         BRDIVISOR : positive:=1;   -- Baud rate divisor i.e. br_clk/9600/4
+         ENA_LOG   : boolean:=true; -- Enable log
+         LOG_FILE  : string:="log.txt"); -- Name for the log file
+      port(
+         clk_i      : in  std_logic; -- System Clock
+         reset_i    : in  std_logic; -- Synchronous Reset
+         busy_o     : out std_logic; -- I/O is busy
+         we_i       : in  std_logic; -- Write Enable
+         re_i       : in  std_logic; -- Read Enable
+         data_i     : in  unsigned(31 downto 0);
+         data_o     : out unsigned(31 downto 0);
+         addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+         --
+         rs232_rx_i : in  std_logic;  -- UART Rx input
+         rs232_tx_o : out std_logic;  -- UART Tx output
+         br_clk_i   : in  std_logic;  -- UART base clock (enable)
+         --
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)
+         );
+   end component ZPUPhiIO;
+
+   -- Opcode decode constants
+   -- Note: these are the basic opcodes, always implemented using hardware.
+   constant OPCODE_IM        : unsigned(7 downto 7):="1";
+   constant OPCODE_STORESP   : unsigned(7 downto 5):="010";
+   constant OPCODE_LOADSP    : unsigned(7 downto 5):="011";
+   constant OPCODE_EMULATE   : unsigned(7 downto 5):="001";
+   constant OPCODE_ADDSP     : unsigned(7 downto 4):="0001";
+   constant OPCODE_SHORT     : unsigned(7 downto 4):="0000";
+   
+   constant OPCODE_BREAK     : unsigned(3 downto 0):="0000";
+   constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
+   constant OPCODE_PUSHSP    : unsigned(3 downto 0):="0010";
+   constant OPCODE_PUSHINT   : unsigned(3 downto 0):="0011";
+   
+   constant OPCODE_POPPC     : unsigned(3 downto 0):="0100";
+   constant OPCODE_ADD       : unsigned(3 downto 0):="0101";
+   constant OPCODE_AND       : unsigned(3 downto 0):="0110";
+   constant OPCODE_OR        : unsigned(3 downto 0):="0111";
+   
+   constant OPCODE_LOAD      : unsigned(3 downto 0):="1000";
+   constant OPCODE_NOT       : unsigned(3 downto 0):="1001";
+   constant OPCODE_FLIP      : unsigned(3 downto 0):="1010";
+   constant OPCODE_NOP       : unsigned(3 downto 0):="1011";
+   
+   constant OPCODE_STORE     : unsigned(3 downto 0):="1100";
+   constant OPCODE_POPSP     : unsigned(3 downto 0):="1101";
+   constant OPCODE_COMPARE   : unsigned(3 downto 0):="1110";
+   constant OPCODE_POPINT    : unsigned(3 downto 0):="1111";
+
+   -- The following instructions are emulated in the small version and
+   -- implemented as hardware in the full version.
+   -- The constants correpond to the "emulated" instruction number.
+
+   -- Enabled by the ENA_LEVEL0 generic:
+   constant OPCODE_EQ               : unsigned(5 downto 0):=to_unsigned(46,6);
+   constant OPCODE_LOADB            : unsigned(5 downto 0):=to_unsigned(51,6);
+   constant OPCODE_NEQBRANCH        : unsigned(5 downto 0):=to_unsigned(56,6);
+   constant OPCODE_PUSHSPADD        : unsigned(5 downto 0):=to_unsigned(61,6);
+   -- Enabled by the ENA_LEVEL1 generic:
+   constant OPCODE_LESSTHAN         : unsigned(5 downto 0):=to_unsigned(36,6);
+   constant OPCODE_ULESSTHAN        : unsigned(5 downto 0):=to_unsigned(38,6);
+   constant OPCODE_MULT             : unsigned(5 downto 0):=to_unsigned(41,6);
+   constant OPCODE_STOREB           : unsigned(5 downto 0):=to_unsigned(52,6);
+   constant OPCODE_CALLPCREL        : unsigned(5 downto 0):=to_unsigned(63,6);
+   constant OPCODE_SUB              : unsigned(5 downto 0):=to_unsigned(49,6);
+   -- Enabled by the ENA_LEVEL2 generic:
+   constant OPCODE_LESSTHANOREQUAL  : unsigned(5 downto 0):=to_unsigned(37,6);
+   constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
+   constant OPCODE_CALL             : unsigned(5 downto 0):=to_unsigned(45,6);
+   constant OPCODE_POPPCREL         : unsigned(5 downto 0):=to_unsigned(57,6);
+   -- Enabled by the ENA_LSHR generic:
+   constant OPCODE_LSHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(42,6);
+   -- The following opcodes are always emulated.
+   constant OPCODE_LOADH            : unsigned(5 downto 0):=to_unsigned(34,6);
+   constant OPCODE_STOREH           : unsigned(5 downto 0):=to_unsigned(35,6);
+   constant OPCODE_ASHIFTLEFT       : unsigned(5 downto 0):=to_unsigned(43,6);
+   constant OPCODE_ASHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(44,6);
+   constant OPCODE_NEQ              : unsigned(5 downto 0):=to_unsigned(47,6);
+   constant OPCODE_NEG              : unsigned(5 downto 0):=to_unsigned(48,6);
+   constant OPCODE_XOR              : unsigned(5 downto 0):=to_unsigned(50,6);
+   constant OPCODE_DIV              : unsigned(5 downto 0):=to_unsigned(53,6);
+   constant OPCODE_MOD              : unsigned(5 downto 0):=to_unsigned(54,6);
+   constant OPCODE_EQBRANCH         : unsigned(5 downto 0):=to_unsigned(55,6);
+   constant OPCODE_CONFIG           : unsigned(5 downto 0):=to_unsigned(58,6);
+   constant OPCODE_PUSHPC           : unsigned(5 downto 0):=to_unsigned(59,6);
+end package zpupkg;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package UART is
+   ----------------------
+   -- Very simple UART --
+   ----------------------
+   component RxUnit is
+      port(
+         clk_i    : in  std_logic;  -- System clock signal
+         reset_i  : in  std_logic;  -- Reset input (sync)
+         enable_i : in  std_logic;  -- Enable input (rate*4)
+         read_i   : in  std_logic;  -- Received Byte Read
+         rxd_i    : in  std_logic;  -- RS-232 data input
+         rxav_o   : out std_logic;  -- Byte available
+         datao_o  : out std_logic_vector(7 downto 0)); -- Byte received
+   end component RxUnit;
+
+   component TxUnit is
+     port (
+        clk_i    : in  std_logic;  -- Clock signal
+        reset_i  : in  std_logic;  -- Reset input
+        enable_i : in  std_logic;  -- Enable input
+        load_i   : in  std_logic;  -- Load input
+        txd_o    : out std_logic;  -- RS-232 data output
+        busy_o   : out std_logic;  -- Tx Busy
+        datai_i  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
+   end component TxUnit;
+
+   component BRGen is
+     generic(
+        COUNT : integer range 0 to 65535);-- Count revolution
+     port (
+        clk_i   : in  std_logic;  -- Clock
+        reset_i : in  std_logic;  -- Reset input
+        ce_i    : in  std_logic;  -- Chip Enable
+        o_o     : out std_logic); -- Output
+   end component BRGen;
+end package UART;
+
Index: de1/atari800core.qpf
===================================================================
--- de1/atari800core.qpf	(nonexistent)
+++ de1/atari800core.qpf	(revision 1)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: de1/atari800core.vhd
===================================================================
--- de1/atari800core.vhd	(nonexistent)
+++ de1/atari800core.vhd	(revision 1)
@@ -0,0 +1,1461 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLOCK_50 :  IN  STD_LOGIC;
+		AUD_BCLK :  IN  STD_LOGIC;
+		AUD_DACLRCK :  IN  STD_LOGIC;
+		PS2_CLK :  IN  STD_LOGIC;
+		PS2_DAT :  IN  STD_LOGIC;
+		UART_RXD :  IN  STD_LOGIC;
+		SD_DATA :  IN  STD_LOGIC;
+		I2C_SCLK :  INOUT  STD_LOGIC;
+		I2C_SDAT :  INOUT  STD_LOGIC;
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		AUD_XCK :  OUT  STD_LOGIC;
+		AUD_DACDAT :  OUT  STD_LOGIC;
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		FL_OE_N :  OUT  STD_LOGIC;
+		FL_WE_N :  OUT  STD_LOGIC;
+		FL_RST_N :  OUT  STD_LOGIC;
+		SRAM_CE_N :  OUT  STD_LOGIC;
+		SRAM_OE_N :  OUT  STD_LOGIC;
+		SRAM_WE_N :  OUT  STD_LOGIC;
+		SRAM_LB_N :  OUT  STD_LOGIC;
+		SRAM_UB_N :  OUT  STD_LOGIC;
+		UART_TXD :  OUT  STD_LOGIC;
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_THREE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT hexdecoder
+	PORT(CLK : IN STD_LOGIC;
+		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sram
+	PORT(WREN : IN STD_LOGIC;
+		 clk : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 request : IN STD_LOGIC;
+		 width_16bit : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_CE_N : OUT STD_LOGIC;
+		 SRAM_OE_N : OUT STD_LOGIC;
+		 SRAM_WE_N : OUT STD_LOGIC;
+		 SRAM_LB_N : OUT STD_LOGIC;
+		 SRAM_UB_N : OUT STD_LOGIC;
+		 complete : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT gpio
+	PORT(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+	);
+END COMPONENT;
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REPLY : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 REPLY : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT i2c_loader
+GENERIC (device_address : INTEGER;
+			log2_divider : INTEGER;
+			num_retries : INTEGER
+			);
+	PORT(CLK : IN STD_LOGIC;
+		 nRESET : IN STD_LOGIC;
+		 I2C_SCL : INOUT STD_LOGIC;
+		 I2C_SDA : INOUT STD_LOGIC;
+		 IS_DONE : OUT STD_LOGIC;
+		 IS_ERROR : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT flashrom
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_CE_N : OUT STD_LOGIC;
+		 FLASH_OE_N : OUT STD_LOGIC;
+		 FLASH_WE_N : OUT STD_LOGIC;
+		 FLASH_RESET_N : OUT STD_LOGIC;
+		 COMPLETE : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT i2sslave
+	PORT(CLK : IN STD_LOGIC;
+		 BCLK : IN STD_LOGIC;
+		 DACLRC : IN STD_LOGIC;
+		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 MCLK_2 : OUT STD_LOGIC;
+		 DACDAT : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+SIGNAL	CART_CCTL_N :  STD_LOGIC;
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+
+BEGIN 
+
+
+
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+
+b2v_hex0_inst : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(3 DOWNTO 0),
+		 DIGIT => HEX0);
+
+
+b2v_hex0_inst2 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(7 DOWNTO 4),
+		 DIGIT => HEX1);
+
+
+b2v_hex0_inst3 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(11 DOWNTO 8),
+		 DIGIT => HEX2);
+
+
+b2v_hex0_inst4 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(15 DOWNTO 12),
+		 DIGIT => HEX3);
+
+
+b2v_inst : sram
+PORT MAP(WREN => RAM_WRITE_ENABLE,
+		 clk => CLK,
+		 reset_n => RESET_N,
+		 request => RAM_REQUEST,
+		 width_16bit => WIDTH_16BIT_ACCESS,
+		 ADDRESS => RAM_ADDR,
+		 DIN => WRITE_DATA(15 DOWNTO 0),
+		 SRAM_DQ => SRAM_DQ,
+		 SRAM_CE_N => SRAM_CE_N,
+		 SRAM_OE_N => SRAM_OE_N,
+		 SRAM_WE_N => SRAM_WE_N,
+		 SRAM_LB_N => SRAM_LB_N,
+		 SRAM_UB_N => SRAM_UB_N,
+		 complete => RAM_REQUEST_COMPLETE,
+		 DOUT => RAM_DO,
+		 SRAM_ADDR => SRAM_ADDR);
+
+
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+
+b2v_inst10 : ledsw
+PORT MAP(CLK => CLK,
+		 KEY => KEY,
+		 SW => SW,
+		 SYNC_KEYS => SYNC_KEYS,
+		 SYNC_SWITCHES => SYNC_SWITCHES);
+
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2_CLK,
+		 PS2_DAT => PS2_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+b2v_inst18 : pokey_ps2_decoder
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_CODE => SYNTHESIZED_WIRE_11,
+		 KEY_HELD => KEY_HELD,
+		 SHIFT_PRESSED => SHIFT_PRESSED,
+		 BREAK_PRESSED => BREAK_PRESSED,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+		 KBCODE => KBCODE,
+		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
+
+gpio0_gen:
+   for I in 0 to 35 generate
+		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+   end generate gpio0_gen;
+
+gpio1_gen:
+   for I in 0 to 35 generate
+		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+   end generate gpio1_gen;
+	
+b2v_inst19 : gpio
+PORT MAP(clk => CLK,
+		 gpio_enable => GPIO_ENABLE,
+		 pot_reset => POT_RESET,
+		 virtual_keyheld => KEY_HELD,
+		 virtual_shift_pressed => SHIFT_PRESSED,
+		 virtual_control_pressed => KBCODE(7),
+		 virtual_break_pressed => BREAK_PRESSED,
+		 pbi_write_enable => PBI_WRITE_ENABLE,
+		 cart_request => CART_REQUEST,
+		 s4_n => CART_S4_n,
+		 s5_n => CART_S5_N,
+		 cctl_n => CART_CCTL_N,
+		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+		 GPIO_0_IN => GPIO_0,
+		 GPIO_0_OUT => GPIO_0_OUT,
+		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+		 GPIO_1_IN => GPIO_1,
+		 GPIO_1_OUT => GPIO_1_OUT,
+		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN,
+		 pbi_addr_out => PBI_ADDR,
+		 porta_out => PORTA_OUT,
+		 porta_output => PORTA_DIR_OUT,
+		 virtual_keycode => KBCODE(5 DOWNTO 0),
+		 virtual_stick_in => VIRTUAL_STICKS,
+		 virtual_trig_in => VIRTUAL_TRIGGERS,
+		 lightpen => LIGHTPEN,
+		 cart_complete => CART_REQUEST_COMPLETE,
+		 rd4 => CART_RD4,
+		 rd5 => CART_RD5,
+		 cart_data_read => CART_ROM_DO,
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 porta_in => GPIO_PORTA_IN,
+		 pot_in => POT_IN,
+		 trig_in => TRIGGERS,
+		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_OUT => CA2_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_OUT => CB2_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 SIO_IN => GPIO_SIO_IN,
+		 SIO_OUT => GPIO_SIO_OUT
+		 );
+
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REPLY => SDRAM_REPLY,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT,
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT,
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA);
+
+
+b2v_inst20 : sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => DRAM_DQ,
+		 REPLY => SDRAM_REPLY,
+		 SDRAM_BA0 => DRAM_BA_0,
+		 SDRAM_BA1 => DRAM_BA_1,
+		 SDRAM_CKE => DRAM_CKE,
+		 SDRAM_CS_N => DRAM_CS_N,
+		 SDRAM_RAS_N => DRAM_RAS_N,
+		 SDRAM_CAS_N => DRAM_CAS_N,
+		 SDRAM_WE_N => DRAM_WE_N,
+		 SDRAM_ldqm => DRAM_LDQM,
+		 SDRAM_udqm => DRAM_UDQM,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => DRAM_ADDR);
+
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DATA,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_THREE,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG,
+		 LEDR => LEDR,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX);
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst3 : i2c_loader
+GENERIC MAP(device_address => 26,
+			log2_divider => 6,
+			num_retries => 0
+			)
+PORT MAP(CLK => CLK,
+		 nRESET => RESET_N,
+		 I2C_SCL => I2C_SCLK,
+		 I2C_SDA => I2C_SDAT);
+
+
+b2v_inst4 : flashrom
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 REQUEST => ROM_REQUEST,
+		 ADDRESS => ROM_ADDR,
+		 FLASH_D => FL_DQ,
+		 FLASH_OE_N => FL_OE_N,
+		 FLASH_WE_N => FL_WE_N,
+		 FLASH_RESET_N => FL_RST_N,
+		 COMPLETE => ROM_REQUEST_COMPLETE,
+		 DOUT => ROM_DO,
+		 FLASH_ADDRESS => FL_ADDR);
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => CLOCK_50,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+
+
+b2v_inst6 : i2sslave
+PORT MAP(CLK => CLK,
+		 BCLK => AUD_BCLK,
+		 DACLRC => AUD_DACLRCK,
+		 LEFT_IN => AUDIO_LEFT,
+		 RIGHT_IN => AUDIO_RIGHT,
+		 MCLK_2 => AUD_XCK,
+		 DACDAT => AUD_DACDAT);
+
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => UART_RXD,
+		 SIO_IN2 => GPIO_SIO_IN,
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => TRIGGERS(0),
+		 TRIG1 => TRIGGERS(1),
+		 TRIG2 => TRIGGERS(2),
+		 TRIG3 => TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+END bdf_type;
\ No newline at end of file
Index: de1/i2c_loader.vhd
===================================================================
--- de1/i2c_loader.vhd	(nonexistent)
+++ de1/i2c_loader.vhd	(revision 1)
@@ -0,0 +1,302 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
+use IEEE.NUMERIC_STD.ALL;
+
+entity i2c_loader is
+generic (
+	-- Address of slave to be loaded
+	device_address : integer := 16#1a#;
+	-- Number of retries to allow before stopping
+	num_retries : integer := 0;
+	-- Length of clock divider in bits.  Resulting bus frequency is
+	-- CLK/2^(log2_divider + 2)
+	log2_divider : integer := 7
+);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	I2C_SCL		:	inout	std_logic;
+	I2C_SDA		:	inout	std_logic;
+	
+	IS_DONE		:	out std_logic;
+	IS_ERROR	:	out	std_logic
+	);
+end i2c_loader;
+
+architecture i2c_loader_arch of i2c_loader is
+type regs is array(0 to 19) of std_logic_vector(7 downto 0);
+constant init_regs : regs := (
+	-- Left line in, 0dB, mute
+	X"00", X"97",
+	-- Right line in, 0dB, mute
+	X"02", X"97",
+	-- Left headphone out, -29dB, zero cross disabled
+	--X"04", X"58",
+	X"04", X"78",
+	-- Right headphone out, -29dB, zero cross disabled
+	--X"06", X"58",
+	X"06", X"78",
+	-- Audio path, DAC enabled, Line in, Bypass off, mic muted
+	X"08", X"12",
+	-- Digital path, Unmute, HP filter enabled
+	X"0A", X"00",
+	-- Power down mic, clkout and xtal osc, line in and adc
+	X"0C", X"67",
+	-- Format 16-bit I2S, no bit inversion or phase changes, MASTER
+	X"0E", X"42",
+	-- Sampling control, Normal mode, mclk/2 used, We should provide 12.288MHz but will provide 12.25MHz - making 96KHz notional, 97.656KHz actual 
+	X"10", X"DC",
+	-- Activate
+	X"12", X"01"
+	);
+-- Number of bursts (i.e. total number of registers)
+constant burst_length : positive := 2;
+-- Number of bytes to transfer per burst
+constant num_bursts : positive := (init_regs'length / burst_length);
+	
+type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
+signal state : state_t;
+signal phase : std_logic_vector(1 downto 0);
+subtype nbit_t is integer range 0 to 7;
+signal nbit : nbit_t;
+subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
+signal nbyte : nbyte_t;
+subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
+signal thisbyte : thisbyte_t;
+subtype retries_t is integer range 0 to num_retries;
+signal retries : retries_t;
+
+signal clken : std_logic;
+signal divider : std_logic_vector(log2_divider-1 downto 0);
+signal shiftreg : std_logic_vector(7 downto 0);
+signal scl_out : std_logic;
+signal sda_out : std_logic;
+signal nak : std_logic;
+begin
+	-- Create open-drain outputs for I2C bus
+	I2C_SCL <= '0' when scl_out = '0' else 'Z';
+	I2C_SDA <= '0' when sda_out = '0' else 'Z';
+	-- Status outputs are driven both ways
+	IS_DONE <= '1' when state = Done else '0';
+	IS_ERROR <= nak;
+	
+	-- Generate clock enable for desired bus speed
+	clken <= AND_REDUCE(divider);
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			divider <= (others => '0');
+		elsif falling_edge(CLK) then
+			divider <= divider + '1';
+		end if;
+	end process;
+
+	-- The I2C loader process
+	process(nRESET,CLK,clken)
+	begin
+		if nRESET = '0' then
+			scl_out <= '1';
+			sda_out <= '1';
+			state <= Idle;
+			phase <= "00";
+			nbit <= 0;
+			nbyte <= 0;
+			thisbyte <= 0;
+			shiftreg <= (others => '0');
+			nak <= '0'; -- No error
+			retries <= num_retries;
+		elsif rising_edge(CLK) and clken = '1' then
+  			-- Next phase by default
+			phase <= phase + 1;
+
+			-- STATE: IDLE
+			if state = Idle then
+				-- Start loading the device registers straight away
+				-- A 'GO' bit could be polled here if required
+				state <= Start;
+				phase <= "00";
+				scl_out <= '1';
+				sda_out <= '1';
+				
+			-- STATE: START
+			elsif state = Start then
+				-- Generate START condition
+				case phase is
+				when "00" =>
+					-- Drop SDA first
+					sda_out <= '0';
+				when "10" =>
+					-- Then drop SCL
+					scl_out <= '0';
+				when "11" =>
+					-- Advance to next state
+					-- Shift register loaded with device slave address
+					state <= Data;
+					nbit <= 7;
+					shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
+					nbyte <= burst_length;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: DATA
+			elsif state = Data then
+				-- Generate data
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Output data and shift (MSb first)
+					sda_out <= shiftreg(7);
+					shiftreg <= shiftreg(6 downto 0) & '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Next bit or advance to next state when done
+					if nbit = 0 then
+						state <= Ack;
+					else
+						nbit <= nbit - 1;
+					end if;
+				when others =>
+				  null;
+				end case;
+				
+			-- STATE: ACK
+			elsif state = Ack then
+				-- Generate ACK clock and check for error condition
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Float data
+					sda_out <= '1';
+				when "10" =>
+					-- Sample ack bit
+					nak <= I2C_SDA;
+					if I2C_SDA = '1' then
+						-- Error
+						nbyte <= 0; -- Close this burst and skip remaining registers
+						thisbyte <= init_regs'length;
+					else
+						-- Hold ACK to avoid spurious stops - this seems to fix a
+						-- problem with the Wolfson codec which releases the ACK
+						-- right on the falling edge of the clock pulse.  It looks like
+						-- the device interprets this is a STOP condition and then fails
+						-- to acknowledge the next byte.  We can avoid this by holding the
+						-- ACK condition for a little longer.
+						sda_out <= '0';
+					end if;
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Advance to next state
+					if nbyte = 0 then
+						-- No more bytes in this burst - generate a STOP
+						state <= Stop;
+					else
+						-- Generate next byte
+						state <= Data;
+						nbit <= 7;
+						shiftreg <= init_regs(thisbyte);
+						nbyte <= nbyte - 1;
+						thisbyte <= thisbyte + 1;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: STOP
+			elsif state = Stop then
+				-- Generate STOP condition
+				case phase is
+				when "00" =>
+					-- Drop SCL first
+					scl_out <= '0';
+				when "01" =>
+					-- Drop SDA
+					sda_out <= '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					if thisbyte = init_regs'length then
+						-- All registers done, advance to finished state.  This will
+						-- bring SDA high while SCL is still high, completing the STOP
+						-- condition
+						state <= Done;
+					else
+						-- Load the next register after a short delay
+						state <= Pause;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: PAUSE
+			elsif state = Pause then
+				-- Delay for one cycle of 'phase' then start the next burst
+				scl_out <= '1';
+				sda_out <= '1';
+				if phase = "11" then
+					state <= Start;
+				end if;
+				
+			-- STATE: DONE
+			else
+				-- Finished
+				scl_out <= '1';
+				sda_out <= '1';
+				
+				if nak = '1' and retries > 0 then
+					-- We can retry in the event of a NAK in case the
+					-- slave got out of sync for some reason
+					retries <= retries - 1;
+					state <= Idle;
+				end if;
+			end if;
+		end if;
+	end process;
+end i2c_loader_arch;
+
Index: de1/pll.cmp
===================================================================
--- de1/pll.cmp	(nonexistent)
+++ de1/pll.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: de1/sram.vhdl
===================================================================
--- de1/sram.vhdl	(nonexistent)
+++ de1/sram.vhdl	(revision 1)
@@ -0,0 +1,143 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY sram IS
+PORT 
+( 
+	ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+	DIN : IN STD_LOGIC_vector(15 downto 0);
+	WREN : IN STD_LOGIC;
+	
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	request : in std_logic;
+	
+	width_16bit : in std_logic;
+	
+	-- SRAM interface
+	SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
+	SRAM_CE_N: OUT STD_LOGIC;
+	SRAM_OE_N: OUT STD_LOGIC;
+	SRAM_WE_N: OUT STD_LOGIC;
+
+	SRAM_LB_N: OUT STD_LOGIC;
+	SRAM_UB_N: OUT STD_LOGIC;
+	
+	SRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
+	complete : out std_logic
+);
+
+END sram;
+
+-- TODO, implement 32-bit accesses in two cycles
+
+-- first cycle, capture inputs
+-- second cycle, sram access
+ARCHITECTURE slow OF sram IS
+	signal oe_n_next : std_logic;
+	signal oe_n_reg : std_logic;
+	
+	signal we_n_next : std_logic;
+	signal we_n_reg : std_logic;	
+	
+	signal data_next : std_logic_vector(15 downto 0);
+	signal data_reg : std_logic_vector(15 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+	signal low_byte : std_logic_vector(7 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			oe_n_reg <= '1';
+			we_n_reg <= '1';
+			data_reg <= (others=>'0');
+			request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			oe_n_reg <= oe_n_next;
+			we_n_reg <= we_n_next;
+			data_reg <= data_next;
+			request_reg <= request_next;
+		end if;
+	end process;
+
+	-- next state
+	process(din,wren,request,request_reg,width_16bit)
+	begin		
+		data_next <= din;
+		request_next <= '0';
+		
+		oe_n_next <= '0';
+		we_n_next <= '1';
+		
+		if (width_16bit = '0') then
+			data_next <= din(7 downto 0)&din(7 downto 0);
+		end if;
+		
+		if (request = '1') then
+			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
+			oe_n_next <= wren;
+			we_n_next <= not(wren);		
+			request_next <= '1';
+		end if;
+	end process;
+	
+	LOW_BYTE <= SRAM_DQ(7 downto 0) when address(0)='0' else SRAM_DQ(15 downto 8);
+	
+	-- output
+	SRAM_ADDR <= address(18 downto 1);
+	SRAM_CE_N <= '0';
+	SRAM_OE_N <= oe_n_reg;
+	SRAM_WE_N <= we_n_reg;
+	SRAM_LB_N <= not(width_16bit) and address(0);
+	SRAM_UB_N <= not(width_16bit) and NOT(address(0));
+	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+
+	DOUT <= SRAM_DQ(15 downto 8)&LOW_BYTE;
+			
+	complete <= request_reg;		
+		
+	--GPIO <= (others=>'0');
+END slow;
+
+--ARCHITECTURE fast OF sram IS
+--	signal we_n : std_logic;
+--	signal dq : std_logic_vector(7 downto 0);
+--	
+--BEGIN
+--	we_n <= not(clk) nand WREN;
+--	dq <= SRAM_DQ(7 downto 0) when address(0)='0' else
+--		SRAM_DQ(15 downto 8);
+--		
+--	-- output
+--	SRAM_ADDR <= ADDRESS(18 downto 1);
+--	--SRAM_ADDR <= ADDRESS(17 downto 0);
+--	SRAM_CE_N <= '0';
+--	SRAM_OE_N <= WREN;
+--	SRAM_WE_N <= we_n;
+--	
+--	SRAM_LB_N <= ADDRESS(0);
+--	SRAM_UB_N <= NOT(ADDRESS(0));
+--	--SRAM_LB_N <= '0';
+--	--SRAM_UB_N <= '0';
+--		
+--	DOUT <= dq;		
+--	SRAM_DQ <= DIN&DIN when wren='1' else (others=>'Z');
+--	
+--	-- immediate completion
+--	complete <= request;
+--END fast;
\ No newline at end of file
Index: mcc216/atari800core.qpf
===================================================================
--- mcc216/atari800core.qpf	(nonexistent)
+++ mcc216/atari800core.qpf	(revision 1)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: mcc216/atari800core.vhd
===================================================================
--- mcc216/atari800core.vhd	(nonexistent)
+++ mcc216/atari800core.vhd	(revision 1)
@@ -0,0 +1,1349 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		FPGA_CLK :  IN  STD_LOGIC;
+		PS2K_CLK :  IN  STD_LOGIC;
+		PS2K_DAT :  IN  STD_LOGIC;
+		PS2M_CLK :  IN  STD_LOGIC;
+		PS2M_DAT :  IN  STD_LOGIC;		
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		
+		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_CS_N :  OUT  STD_LOGIC;
+		SDRAM_RAS_N :  OUT  STD_LOGIC;
+		SDRAM_CAS_N :  OUT  STD_LOGIC;
+		SDRAM_WE_N :  OUT  STD_LOGIC;
+		SDRAM_DQM_n :  OUT  STD_LOGIC_vector(1 downto 0);
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		--SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+	
+END component;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+	);
+END COMPONENT;
+
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 REPLY : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+component sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END component;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+signal CART_CCTL_N : std_logic;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+--SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal UART_TXD_dummy : std_logic;
+
+BEGIN 
+
+
+
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+LIGHTPEN <= '1';
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+		 
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_left&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_right&"0000",
+  dac_out => audio_r
+);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2K_CLK,
+		 PS2_DAT => PS2K_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+GPIO_CA2_IN <= CA2_OUT;
+GPIO_CB2_IN <= CB2_OUT;
+GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+b2v_inst18 : pokey_ps2_decoder
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_CODE => SYNTHESIZED_WIRE_11,
+		 KEY_HELD => KEY_HELD,
+		 SHIFT_PRESSED => SHIFT_PRESSED,
+		 BREAK_PRESSED => BREAK_PRESSED,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+		 KBCODE => KBCODE,
+		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+
+-- no cart!
+CART_RD4 <= '0';
+CART_RD5 <= '0';
+CART_REQUEST_COMPLETE <= '0';
+CART_ROM_DO <= (others=>'0');
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT,
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT,
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA);
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+SYNC_KEYS <= (others=> '0');
+SYNC_SWITCHES <= (others=> '1');
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DAT0,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_DAT3,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG_dummy,
+		 LEDR => LEDR_dummy,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX);
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => FPGA_CLK,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 locked => PLL_LOCKED);
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD_dummy,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+	begin	
+		keyboard_response <= (others=>'1');
+		
+		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;		 
+		 	 
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+		 TRIG2 => VIRTUAL_TRIGGERS(2),
+		 TRIG3 => VIRTUAL_TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+irr : internalromram
+  PORT map(
+    clock => clk,
+    reset_n => reset_n,
+
+	ROM_ADDR =>rom_addr,
+	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
+	ROM_REQUEST => rom_REQUEST,
+	ROM_DATA => rom_DO,
+	
+	RAM_ADDR => ram_addr,
+	RAM_WR_ENABLE => ram_WRITE_ENABLE,
+	RAM_DATA_IN => wriTE_DATA(7 downto 0),
+	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
+	RAM_REQUEST => ram_REQUEST,
+	RAM_DATA => ram_do(7 downto 0)
+	);
+
+--b2v_inst20 : sdram_statemachine
+--GENERIC MAP(ADDRESS_WIDTH => 22,
+--			AP_BIT => 10,
+--			COLUMN_WIDTH => 8,
+--			ROW_WIDTH => 12
+--			)
+--PORT MAP(CLK_SYSTEM => CLK,
+--		 CLK_SDRAM => CLK_SDRAM,
+--		 RESET_N => RESET_N,
+--		 READ_EN => SDRAM_READ_ENABLE,
+--		 WRITE_EN => SDRAM_WRITE_ENABLE,
+--		 REQUEST => SDRAM_REQUEST,
+--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+--		 REFRESH => SDRAM_REFRESH,
+--		 ADDRESS_IN => SDRAM_ADDR,
+--		 DATA_IN => WRITE_DATA,
+--		 SDRAM_DQ => SDRAM_DQ,
+--		 REPLY => SDRAM_REPLY,
+--		 SDRAM_BA0 => SDRAM_BA(0),
+--		 SDRAM_BA1 => SDRAM_BA(1),
+--		 SDRAM_CKE => SDRAM_A(12),
+--		 SDRAM_CS_N => SDRAM_CS_N,
+--		 SDRAM_RAS_N => SDRAM_RAS_N,
+--		 SDRAM_CAS_N => SDRAM_CAS_N,
+--		 SDRAM_WE_N => SDRAM_WE_N,
+--		 SDRAM_ldqm => SDRAM_DQM_n(0),
+--		 SDRAM_udqm => SDRAM_DQM_n(1),
+--		 DATA_OUT => SDRAM_DO,
+--		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+
+b2v_inst20 : sdram_statemachine_mcc
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => SDRAM_DQ,
+		 REPLY => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => SDRAM_BA(0),
+		 SDRAM_BA1 => SDRAM_BA(1),
+		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+		 SDRAM_CS_N => SDRAM_CS_N,
+		 SDRAM_RAS_N => SDRAM_RAS_N,
+		 SDRAM_CAS_N => SDRAM_CAS_N,
+		 SDRAM_WE_N => SDRAM_WE_N,
+		 SDRAM_ldqm => SDRAM_DQM_n(0),
+		 SDRAM_udqm => SDRAM_DQM_n(1),
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
+
+		
+END bdf_type;
\ No newline at end of file
Index: mcc216/pll.qip
===================================================================
--- mcc216/pll.qip	(nonexistent)
+++ mcc216/pll.qip	(revision 1)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: mcc216/sdram_statemachine_mcc.vhdl
===================================================================
--- mcc216/sdram_statemachine_mcc.vhdl	(nonexistent)
+++ mcc216/sdram_statemachine_mcc.vhdl	(revision 1)
@@ -0,0 +1,480 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine_mcc;
+
+ARCHITECTURE vhdl OF sdram_statemachine_mcc IS
+component sdram_ctrl
+port
+(
+--    //-----------------------------
+--    // Clock and reset
+--    //-----------------------------
+--    input         rst,             // Global reset
+--    input         clk,             // Master clock (72 MHz)
+--    
+--    output        ram_rdy_n,       // SDRAM ready
+--    output        ram_ref,         // SDRAM refresh
+--    output  [3:0] ram_cyc,         // SDRAM cycles
+--    output  [3:0] ram_ph,          // SDRAM phases
+--    output  [8:0] ram_ph_ctr,      // Phase counter
+    rst : in std_logic;
+	 clk : in std_logic;
+	 
+	 ram_rdy_n : out std_logic;
+	 ram_ref : out std_logic;
+	 ram_cyc : out std_logic_vector(3 downto 0);
+	 ram_ph : out std_logic_vector(3 downto 0);
+	 ram_ph_ctr : out std_logic_vector(8 downto 0);
+	
+	rden_b0 : in std_logic;
+	wren_b0 : in std_logic;
+	addr_b0 : in std_logic_vector(22 downto 2);
+	valid_b0 : out std_logic;
+	fetch_b0 : out std_logic;
+	rdata_b0 : out std_logic_vector(15 downto 0);
+	wdata_b0 : in std_logic_vector(15 downto 0);
+	bena_b0 : in std_logic_vector(1 downto 0);
+
+	rden_b1 : in std_logic;
+	wren_b1 : in std_logic;
+	addr_b1 : in std_logic_vector(22 downto 2);
+	valid_b1 : out std_logic;
+	fetch_b1 : out std_logic;
+	rdata_b1 : out std_logic_vector(15 downto 0);
+	wdata_b1 : in std_logic_vector(15 downto 0);
+	bena_b1 : in std_logic_vector(1 downto 0);
+
+	rden_b2 : in std_logic;
+	wren_b2 : in std_logic;
+	addr_b2 : in std_logic_vector(22 downto 2);
+	valid_b2 : out std_logic;
+	fetch_b2 : out std_logic;
+	rdata_b2 : out std_logic_vector(15 downto 0);
+	wdata_b2 : in std_logic_vector(15 downto 0);
+	bena_b2 : in std_logic_vector(1 downto 0);
+
+	rden_b3 : in std_logic;
+	wren_b3 : in std_logic;
+	addr_b3 : in std_logic_vector(22 downto 2);
+	valid_b3 : out std_logic;
+	fetch_b3 : out std_logic;
+	rdata_b3 : out std_logic_vector(15 downto 0);
+	wdata_b3 : in std_logic_vector(15 downto 0);
+	bena_b3 : in std_logic_vector(1 downto 0);
+	
+--    //-----------------------------
+--    // Access bank #0
+--    //-----------------------------
+--    input         rden_b0,         // Read enable
+--    input         wren_b0,         // Write enable
+--    input  [22:2] addr_b0,         // Address (up to 8 MB)
+--    output        valid_b0,        // Read data valid
+--    output        fetch_b0,        // Write data fetch
+--    output [15:0] rdata_b0,        // Read data
+--    input  [15:0] wdata_b0,        // Write data
+--    input   [1:0] bena_b0,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #1
+--    //-----------------------------
+--    input         rden_b1,         // Read enable
+--    input         wren_b1,         // Write enable
+--    input  [22:2] addr_b1,         // Address (up to 8 MB)
+--    output        valid_b1,        // Read data valid
+--    output        fetch_b1,        // Write data fetch
+--    output [15:0] rdata_b1,        // Read data
+--    input  [15:0] wdata_b1,        // Write data
+--    input   [1:0] bena_b1,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #2
+--    //-----------------------------
+--    input         rden_b2,         // Read enable
+--    input         wren_b2,         // Write enable
+--    input  [22:2] addr_b2,         // Address (up to 8 MB)
+--    output        valid_b2,        // Read data valid
+--    output        fetch_b2,        // Write data fetch
+--    output [15:0] rdata_b2,        // Read data
+--    input  [15:0] wdata_b2,        // Write data
+--    input   [1:0] bena_b2,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #3
+--    //-----------------------------
+--    input         rden_b3,         // Read enable
+--    input         wren_b3,         // Write enable
+--    input  [22:2] addr_b3,         // Address (up to 8 MB)
+--    output        valid_b3,        // Read data valid
+--    output        fetch_b3,        // Write data fetch
+--    output [15:0] rdata_b3,        // Read data
+--    input  [15:0] wdata_b3,        // Write data
+--    input   [1:0] bena_b3,         // Byte enable
+    
+--    //-----------------------------
+--    // SDRAM memory signals
+--    //-----------------------------
+--    output            sdram_cs_n,  // SDRAM chip select
+--    output reg        sdram_ras_n, // SDRAM row address strobe
+--    output reg        sdram_cas_n, // SDRAM column address strobe
+--    output reg        sdram_we_n,  // SDRAM write enable
+--    //
+--    output reg  [1:0] sdram_ba,    // SDRAM bank address
+--    output reg [12:0] sdram_addr,  // SDRAM address
+--    //
+--    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+--    output reg        sdram_dq_oe, // SDRAM data output enable
+--    output reg [31:0] sdram_dq_o,  // SDRAM data output
+--    input      [31:0] sdram_dq_i   // SDRAM data input
+
+	sdram_cs_n : out std_logic;
+	sdram_ras_n : out std_logic;
+	sdram_cas_n : out std_logic;
+	sdram_we_n : out std_logic;
+	sdram_ba : out std_logic_vector(1 downto 0);
+	sdram_addr : out std_logic_vector(12 downto 0);
+	sdram_dqm_n : out std_logic_vector(3 downto 0);
+	sdram_dq_oe : out std_logic;
+	sdram_dq_o : out std_logic_vector(31 downto 0);
+	sdram_dq_i : in std_logic_vector(31 downto 0)
+);
+end component;
+
+signal SDRAM_CKE_dummy : std_logic;
+
+signal sdram_valid_b0_dummy : std_logic;
+signal sdram_valid_b1_dummy : std_logic;
+signal sdram_valid_b2_dummy : std_logic;
+signal sdram_valid_b3_dummy : std_logic;
+
+signal sdram_fetch_b0_dummy : std_logic;
+signal sdram_fetch_b1_dummy : std_logic;
+signal sdram_fetch_b2_dummy : std_logic;
+signal sdram_fetch_b3_dummy : std_logic;
+
+signal sdram_read_b0_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b1_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b2_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b3_dummy : std_logic_vector(15 downto 0);
+
+signal reset : std_logic;
+
+signal sdram_ctl_rdy_dummy : std_logic;
+signal sdram_ctl_ref_dummy : std_logic;
+signal sdram_ctl_cyc_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_ctr_dummy : std_logic_vector(8 downto 0);
+
+signal SDRAM_VALID : std_logic;
+signal SDRAM_FETCH : std_logic;
+
+signal SDRAM_dq_oe : std_logic;
+signal sdram_dq_o : std_logic_vector(31 downto 0);
+signal sdram_dq_i : std_logic_vector(31 downto 0);
+signal sdram_dqm_N_temp : std_logic_vector(3 downto 0);
+
+signal sdram_ba : std_logic_vector(1 downto 0);
+
+signal sdram_enable_byte : std_logic_vector(1 downto 0);
+
+signal sdram_reply_reg : std_logic;
+signal state_reg : std_logic_vector(2 downto 0);
+signal store_data_in_reg : std_logic_vector(47 downto 0);
+signal data_out_reg : std_logic_vector(31 downto 0);
+signal sdram_reply_next : std_logic;
+signal state_next : std_logic_vector(2 downto 0);
+signal store_data_in_next : std_logic_vector(47 downto 0);
+signal data_out_next : std_logic_vector(31 downto 0);
+
+constant state_idle : std_logic_vector(2 downto 0) := "000";
+constant state_write_wait_1 : std_logic_vector(2 downto 0) := "001";
+constant state_write_wait_2 : std_logic_vector(2 downto 0) := "010";
+constant state_write_wait_3 : std_logic_vector(2 downto 0) := "111";
+constant state_read_wait_1 : std_logic_vector(2 downto 0) := "011";
+constant state_read_wait_2 : std_logic_vector(2 downto 0) := "100";
+constant state_read_wait_3 : std_logic_vector(2 downto 0) := "101";
+constant state_read_wait_4 : std_logic_vector(2 downto 0) := "110";
+
+
+signal internal_data_in : std_logic_vector(15 downto 0);
+signal internal_data_out : std_logic_vector(15 downto 0);
+
+signal write_en_next : std_logic;
+signal write_en_reg : std_logic;
+
+signal read_en_next : std_logic;
+signal read_en_reg : std_logic;
+
+signal SDRAM_ADDR_temp : std_logic_vector(12 downto 0);
+
+begin
+
+
+reset <= not(reset_n);
+
+process(clk_system, reset_n)
+begin
+	if (reset_n = '0') then
+		sdram_reply_reg <= '0';
+		state_reg <= state_idle;
+		store_data_in_reg <= (others=>'0');
+		data_out_reg <= (others=>'0');
+		write_en_reg <= '0';
+		read_en_reg <= '0';
+	elsif (clk_system'event and clk_system = '1') then
+		sdram_reply_reg <= sdram_reply_next;
+		state_reg <= state_next;
+		store_data_in_reg <= store_data_in_next;
+		data_out_reg <= data_out_next;
+		write_en_reg <= write_en_next;
+		read_en_reg <= read_en_next;		
+	end if;
+end process;	
+
+data_out <= data_out_reg;
+reply <= sdram_reply_reg;
+
+process(read_en_reg, write_en_reg, state_reg, request, write_en, store_data_in_reg, internal_data_in, data_in, sdram_reply_reg, byte_access, longword_access, address_in, sdram_valid, sdram_fetch)
+begin
+	sdram_reply_next <= sdram_reply_reg;
+	state_next <= state_reg;
+	store_data_in_next <= store_data_in_reg;
+	data_out_next <= (others=>'0');
+	
+	read_en_next <= read_en_reg;
+	write_en_next <= write_en_reg;
+	
+	internal_data_out <= (others=>'0');
+	sdram_enable_byte <= "11";
+
+	case state_reg is
+	when state_idle => 
+		sdram_reply_next <= '0';
+		if (request = '1') then
+			if (write_en = '1') then
+				-- 4 byte write
+				state_next <= state_write_wait_1;
+				write_en_next <= '1';
+			else
+				-- 8 byte read
+				state_next <= state_read_wait_1;
+				read_en_next <= '1';
+				-- TODO - read from cached?
+			end if;
+		end if;
+	when state_write_wait_1 =>
+		if (sdram_fetch = '1') then
+			state_next <= state_write_wait_2;
+		end if;
+		internal_data_out <= data_in(31 downto 16);
+	when state_write_wait_2 =>
+		state_next <= state_write_wait_3;
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "01";
+			when "01" =>	
+				sdram_enable_byte <= "10";				
+			when "10" =>
+				sdram_enable_byte <= "00";								
+			when "11" =>	
+				sdram_enable_byte <= "00";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(15 downto 0);
+		end if;
+		sdram_reply_next <= '1';	
+	when state_write_wait_3 =>
+		state_next <= state_idle;
+		write_en_next <= '0';		
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "00";
+			when "01" =>	
+				sdram_enable_byte <= "00";				
+			when "10" =>
+				sdram_enable_byte <= "01";								
+			when "11" =>	
+				sdram_enable_byte <= "10";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(31 downto 16);
+		end if;
+		sdram_reply_next <= '0';
+	when state_read_wait_1 =>
+		if (sdram_valid = '1') then
+			state_next <= state_read_wait_2;
+			store_data_in_next(15 downto 0) <= internal_data_in;
+		end if;
+	when state_read_wait_2 =>
+		state_next <= state_read_wait_3;
+		store_data_in_next(31 downto 16) <= internal_data_in;
+	when state_read_wait_3 =>
+		state_next <= state_read_wait_4;
+		store_data_in_next(47 downto 32) <= internal_data_in;
+	when state_read_wait_4 =>
+		read_en_next <= '0';
+		state_next <= state_idle;
+		--store_data_in_next(63 downto 48) <= internal_data_in;
+		sdram_reply_next <= '1';
+		if (byte_access = '1') then
+			case address_in(2 downto 0) is
+			when "000" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(7 downto 0);
+			when "001" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(15 downto 8);
+			when "010" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(23 downto 16);
+			when "011" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(31 downto 24);
+			when "100" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(39 downto 32);
+			when "101" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(47 downto 40);
+			when "110" =>
+				data_out_next(7 downto 0) <= internal_data_in(7 downto 0);
+			when "111" =>
+				data_out_next(7 downto 0) <= internal_data_in(15 downto 8);
+			end case;
+		elsif (longword_access = '1') then
+			case address_in(2 downto 0) is -- aligned only!
+			when "000" =>
+				data_out_next <= store_data_in_reg(31 downto 0);
+			when "100" =>
+				data_out_next <= internal_data_in&store_data_in_reg(47 downto 32);
+			when others =>
+				-- NOP
+			end case;		
+		end if;
+	end case;	
+end process;
+
+
+sdram_mcc : sdram_ctrl 
+	PORT map
+	(
+		rst => reset,
+		clk => clk_SYSTEM,
+		
+		ram_rdy_n => sdram_ctl_rdy_dummy,
+		ram_ref => sdram_ctl_ref_dummy,
+		ram_cyc => sdram_ctl_cyc_dummy,
+		ram_ph => sdram_ctl_ph_dummy,
+		ram_ph_ctr => sdram_ctl_ph_ctr_dummy,
+
+		 --BYTE_ACCESS : IN STD_LOGIC;
+		 --WORD_ACCESS : IN STD_LOGIC;
+		 --LONGWORD_ACCESS : IN STD_LOGIC;		
+		 
+		rden_b0 => READ_EN_reg,
+		wren_b0 => WRITE_EN_reg,
+		addr_b0 => ADDRESS_IN(22 downto 2),
+		valid_b0 => SDRAM_VALID,
+		fetch_b0 => SDRAM_FETCH,
+		rdata_b0 => INTERNAL_DATA_IN(15 downto 0),
+		wdata_b0 => INTERNAL_DATA_OUT(15 downto 0),
+		bena_b0 => sdram_enable_byte,
+
+		rden_b1 => '0',
+		wren_b1 => '0',
+		addr_b1 => (others=>'0'),
+		valid_b1 => sdram_valid_b1_dummy,
+		fetch_b1 => sdram_fetch_b1_dummy,
+		rdata_b1 => sdram_read_b1_dummy,
+		wdata_b1 => (others=>'0'),
+		bena_b1 => "00",
+
+		rden_b2 => '0',
+		wren_b2 => '0',
+		addr_b2 => (others=>'0'),
+		valid_b2 => sdram_valid_b2_dummy,
+		fetch_b2 => sdram_fetch_b2_dummy,
+		rdata_b2 => sdram_read_b2_dummy,
+		wdata_b2 => (others=>'0'),
+		bena_b2 => "00",
+
+		rden_b3 => '0',
+		wren_b3 => '0',
+		addr_b3 => (others=>'0'),
+		valid_b3 => sdram_valid_b3_dummy,
+		fetch_b3 => sdram_fetch_b3_dummy,		
+		rdata_b3 => sdram_read_b3_dummy,
+		wdata_b3 => (others=>'0'),
+		bena_b3 => "00",	
+		
+		sdram_cs_n => SDRAM_CS_N,
+		sdram_ras_n => SDRAM_RAS_N,
+		sdram_cas_n => SDRAM_CAS_N,
+		sdram_we_n => SDRAM_WE_N,
+		sdram_ba => SDRAM_BA,
+		sdram_addr => SDRAM_ADDR_temp,
+		sdram_dqm_n => sdram_dqm_N_temp,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+);
+sdram_dq <= sdram_dq_o(15 downto 0) when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i(15 downto 0) <= sdram_dq;
+sdram_dq_i(31 downto 16) <= (others=>'0');
+SDRAM_LDQM<= sdram_dqm_N_temp(0);
+SDRAM_UDQM<= sdram_dqm_N_temp(1);
+SDRAM_BA0 <= sdram_ba(0);
+SDRAM_BA1 <= sdram_ba(1);
+
+SDRAM_ADDR(12) <= '1';
+SDRAM_ADDR(11 downto 0) <= SDRAM_ADDR_temp(11 downto 0);
+
+end vhdl;
\ No newline at end of file
Index: common/romgen/rom_example
===================================================================
--- common/romgen/rom_example	(nonexistent)
+++ common/romgen/rom_example	(revision 1)
@@ -0,0 +1,36 @@
+--
+--ROMsUsingBlockRAMResources. 
+--VHDLcodeforaROMwithregisteredoutput(template2) 
+--
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity rams_21b is 
+port(
+	clk:instd_logic;
+	en:instd_logic;
+	addr:instd_logic_vector(5 downto 0); 
+	data:outstd_logic_vector(19 downto 0)
+);
+end rams_21b;
+
+architecture syn of rams_21b is 
+	type rom_type is array(63 downto 0) of std_logic_vector(19 downto 0);
+	signal ROM:rom_type:=
+(
+	X"0200A",X"00300",X"08101",X"04000",X"08601",X"0233A", X"00300",X"08602",X"02310",X"0203B",X"08300",X"04002", X"08201",X"00500",X"04001",X"02500",X"00340",X"00241", X"04002",X"08300",X"08201",X"00500",X"08101",X"00602", X"04003",X"0241E",X"00301",X"00102",X"02122",X"02021", X"00301",X"00102",X"02222",X"04001",X"00342",X"0232B", X"00900",X"00302",X"00102",X"04002",X"00900",X"08201", X"02023",X"00303",X"02433",X"00301",X"04004",X"00301", X"00102",X"02137",X"02036",X"00301",X"00102",X"02237", X"04004",X"00304",X"04040",X"02500",X"02500",X"02500", X"0030D",X"02341",X"08201",X"0400D"
+);
+	signal rdata:std_logic_vector(19 downto 0);
+begin
+	rdata<=ROM(conv_integer(addr));
+
+	process(clk)
+	begin
+		if(clk’eventandclk=’1’)then
+			if(en=’1’)then
+				data<=rdata;
+			endif;
+		endif;
+	endprocess;
+end syn;
Index: common/zpu/zpu_glue.vhdl
===================================================================
--- common/zpu/zpu_glue.vhdl	(nonexistent)
+++ common/zpu/zpu_glue.vhdl	(revision 1)
@@ -0,0 +1,395 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+library work;
+use work.zpupkg.all;
+
+ENTITY zpu_glue IS
+PORT 
+(
+	CLK : in std_logic;
+	RESET : in std_logic;
+	PAUSE : in std_logic;
+
+	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
+	ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+	
+	ZPU_DO : out std_logic_vector(31 downto 0);
+	
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
+	
+	-- request
+	MEMORY_FETCH : out std_logic;
+	ZPU_READ_ENABLE : out std_logic;
+	ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
+	ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
+	
+	-- config
+	ZPU_CONFIG_WRITE : out std_logic;
+	
+	-- stack request
+	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+
+	-- response
+	MEMORY_READY : in std_logic
+);
+END zpu_glue;
+
+architecture sticky of zpu_glue is
+component ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=24;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=16;  -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+	end component;	
+			
+	signal zpu_addr_unsigned : unsigned(23 downto 0);
+	signal zpu_do_unsigned : unsigned(31 downto 0);
+	signal ZPU_DI_unsigned : unsigned(31 downto 0);
+	signal zpu_break : std_logic;
+	signal zpu_debug : zpu_dbgo_t;
+	
+	signal zpu_mem_busy : std_logic;
+	
+	signal zpu_memory_fetch_pending_next : std_logic;
+	signal zpu_memory_fetch_pending_reg : std_logic;
+	
+	signal ZPU_32bit_READ_ENABLE_temp : std_logic;
+	signal ZPU_8bit_READ_ENABLE_temp : std_logic;	
+	signal ZPU_READ_temp : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;	
+	signal ZPU_WRITE_temp : std_logic;
+	
+	signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;	
+	signal ZPU_READ_next : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;	
+	signal ZPU_READ_reg : std_logic;
+	
+	signal block_mem : std_logic;
+	signal config_mem : std_logic;
+	signal special_mem : std_logic;
+	
+	signal result_next : std_logic_vector(4 downto 0);
+	signal result_reg : std_logic_vector(4 downto 0);
+	constant result_external   : std_logic_vector(4 downto 0) := "00000";
+	constant result_ram        : std_logic_vector(4 downto 0) := "00001";
+	constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
+	constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
+	constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
+	constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
+	constant result_rom        : std_logic_vector(4 downto 0) := "00110";
+	constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
+	constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
+	constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
+	constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";	
+	constant result_config     : std_logic_vector(4 downto 0) := "01011";	
+	constant result_external_special : std_logic_vector(4 downto 0) := "01100";
+	constant result_sec        : std_logic_vector(4 downto 0) := "01101";
+	constant result_sec_8bit_0 : std_logic_vector(4 downto 0) := "01110";
+	constant result_sec_8bit_1 : std_logic_vector(4 downto 0) := "01111";
+	constant result_sec_8bit_2 : std_logic_vector(4 downto 0) := "10000";
+	constant result_sec_8bit_3 : std_logic_vector(4 downto 0) := "10001";
+	
+	signal request_type : std_logic_vector(4 downto 0);
+	
+	signal zpu_di_use : std_logic_vector(31 downto 0);
+	
+	signal memORY_ACCESS : std_logic;
+
+	-- 1 cycle delay on memory read - needed to allow running at higher clock
+	signal zpu_di_next : std_logic_vector(31 downto 0);
+	signal zpu_di_reg : std_logic_vector(31 downto 0);
+	
+	signal memory_ready_next : std_logic;
+	signal memory_ready_reg : std_logic;
+	
+	signal zpu_enable : std_logic;
+	
+	signal zpu_addr_next : std_logic_vector(23 downto 0);
+	signal zpu_addr_reg : std_logic_vector(23 downto 0);
+
+	signal ZPU_DO_next : std_logic_vector(31 downto 0);
+	signal ZPU_DO_reg : std_logic_vector(31 downto 0);
+	
+begin
+		-- register
+	process(clk,reset)
+	begin
+		if (reset='1') then
+			zpu_memory_fetch_pending_reg <= '0';
+			result_reg <= result_rom;
+			zpu_di_reg <= (others=>'0');
+			zpu_do_reg <= (others=>'0');
+			memory_ready_reg <= '0';
+			zpu_addr_reg <= (others=>'0');
+			ZPU_32BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_16BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_8BIT_WRITE_ENABLE_reg <= '0';	
+			ZPU_READ_reg <= '0';
+		elsif (clk'event and clk='1') then
+			zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
+			result_reg <= result_next;
+			zpu_di_reg <= zpu_di_next;
+			zpu_do_reg <= zpu_do_next;
+			memory_ready_reg <= memORY_READY_next;
+			zpu_addr_reg <=zpu_addr_next;
+			ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
+			ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
+			ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
+			ZPU_READ_reg <= ZPU_READ_next;
+		end if;
+	end process;
+
+-- a little glue
+	process(zpu_ADDR_unsigned)
+	begin
+		block_mem <= '0';
+		config_mem <= '0';
+		special_mem <= '0';
+		-- $00000-$0FFFF = Own ROM/RAM
+		-- $10000-$1FFFF = Atari
+		-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
+		-- $40000-$4FFFF = Config area
+		if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
+			block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
+			config_mem <= zpu_addr_unsigned(18);
+			special_mem <= zpu_addr_unsigned(17);
+		end if;	
+	end process;
+
+	ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
+	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
+	zpu_do_unsigned, zpu_do_reg
+			  )
+	begin
+		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+		result_next <= result_reg;
+		memory_ready_next <= memory_ready;
+		zpu_stACK_WRITE <= (others=>'0');
+		ZPU_config_write <= '0';
+		zpu_addr_next <= zpu_addr_reg;
+		zpu_do_next <= zpu_do_reg;
+	
+		ZPU_MEM_BUSY <= pause;
+		
+		MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
+
+		if (memory_access = '1') then
+			zpu_do_next <= std_logic_vector(zpu_do_unsigned);
+		end if;
+		
+		memory_fetch <= zpu_memory_fetch_pending_reg;
+		
+		zpu_read_next <= zpu_read_reg;
+		zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
+		zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
+		zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;	
+		
+		request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
+		case request_type is
+			when "00010"|"00110" =>
+				zpu_memory_fetch_pending_next <= '1';
+				if (special_mem='0') then
+					result_next <= result_external;
+				else
+					result_next <= result_external_special;
+				end if;
+				
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+				zpu_read_next <= zpu_read_temp;
+				zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
+				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+			when "01010" =>
+				-- TODO - addr(14) should just feed 1 bit in result reg!
+				if (zpu_addr_unsigned(14) = '1') then
+					if (zpu_8bit_read_enable_temp='1') then
+						case (zpu_addr_unsigned(1 downto 0)) is
+						when "00" =>
+							result_next <= result_sec_8bit_0;										
+						when "01" =>
+							result_next <= result_sec_8bit_1;
+						when "10" =>
+							result_next <= result_sec_8bit_2;										
+						when "11" =>
+							result_next <= result_sec_8bit_3;
+						when others =>
+							--nop
+						end case;
+					else
+						result_next <= result_sec;
+					end if;					
+				else
+					if (zpu_8bit_read_enable_temp='1') then
+						case (zpu_addr_unsigned(1 downto 0)) is
+						when "00" =>
+							result_next <= result_rom_8bit_3;										
+						when "01" =>
+							result_next <= result_rom_8bit_2;
+						when "10" =>
+							result_next <= result_rom_8bit_1;										
+						when "11" =>
+							result_next <= result_rom_8bit_0;
+						when others =>
+							--nop
+						end case;
+					else
+						result_next <= result_rom;
+					end if;
+				end if;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "01110" =>
+				if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_ram_8bit_3;										
+						ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
+					when "01" =>
+						result_next <= result_ram_8bit_2;
+						ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
+					when "10" =>
+						result_next <= result_ram_8bit_1;					
+						ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;					
+					when "11" =>
+						result_next <= result_ram_8bit_0;
+						ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
+					when others =>
+						--nop
+					end case;
+				else
+					result_next <= result_ram;
+					ZPU_STACK_WRITE <= (others=>zpu_write_temp);					
+				end if;
+				ZPU_MEM_BUSY <= '1';				
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "10110"|"10010" =>
+				result_next <= result_config;
+				ZPU_MEM_BUSY <= '1';
+				ZPU_config_write <= ZPU_WRITE_temp; 
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);				
+			when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
+				  "10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111"|"00X01" =>
+				ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
+				zpu_memory_fetch_pending_next <= not(memORY_READY);
+			when others =>
+				-- nop
+		end case;
+	end process;
+
+	zpu_di_next <= zpu_di;
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di, zpu_sector_di)
+	begin
+		zpu_di_use <= (others=>'0');
+		case result_reg is 
+			when result_external =>
+				zpu_di_use <= zpu_di_reg;
+			when result_external_special =>
+				zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);				
+			when result_rom =>
+				zpu_di_use <= zpu_rom_DI;
+			when result_rom_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
+			when result_rom_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
+			when result_rom_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
+			when result_rom_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);				
+			when result_ram =>
+				zpu_di_use <= zpu_ram_DI;
+			when result_ram_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
+			when result_ram_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
+			when result_ram_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+			when result_ram_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
+			when result_sec =>
+				zpu_di_use <= zpu_sector_DI;
+			when result_sec_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(7 downto 0);
+			when result_sec_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(15 downto 8);
+			when result_sec_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(23 downto 16);
+			when result_sec_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(31 downto 24);								
+			when result_config =>
+				zpu_di_use <= zpu_config_di;
+			when others =>
+				-- nothing
+		end case;
+	end process;
+
+-- zpu itself
+	--zpu_enable <= enable and not(pause);
+	zpu_enable <= '1'; -- does nothing useful...
+	
+myzpu: ZPUMediumCore
+	port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
+	data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
+	byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
+	
+	zpu_di_unsigned <= unsigned(zpu_di_use);
+	zpu_do <= zpu_do_next;
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_FETCH <= zpu_addr_reg;
+		
+	zpu_read_enable <= zpu_read_reg;
+	zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
+	zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
+	zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
+
+end sticky;
Index: de1/COPYRIGHT_NOTICE
===================================================================
--- de1/COPYRIGHT_NOTICE	(nonexistent)
+++ de1/COPYRIGHT_NOTICE	(revision 1)
@@ -0,0 +1,129 @@
+(c) 2013 Mark Watson
+I am happy for anyone to use these for non-commercial use.
+If my vhdl files are used commercially or sold please contact me for explicit permission at scrameta@gmail.com.
+This applies for source and binary form and derived works.
+
+pokey.vhdl
+pokey_noise_filter.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_ps2_decoder.vhdl
+pokey_mixer.vhdl
+poly_4.vhdl
+poly_5.vhdl
+poly_17_9.vhdl
+
+gtia.vhdl
+gtia_priority.vhdl
+gtia_palette.vhdl // Palette data itself from laoo and Altirra
+gtia_player.vhdl
+
+antic.vhdl
+antic_dma_clock.vhdl
+antic_counter.vhdl
+
+pia.vhdl
+
+cpu.vhd
+shared_enable.vhdl
+irq_glue.vhdl
+
+ps2_keyboard.vhdl
+
+scandoubler.vhdl
+scandouble_ram_infer.vhdl
+
+zpu_glue.vhdl
+zpu_config_regs.vhdl
+
+// utils
+synchronizer.vhdl
+delay_line.vhdl
+wide_delay_line.vhdl
+reg_file.vhdl
+enable_divider.vhdl
+syncreset_enable_divider.vhd
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+simple_counter.vhdl
+
+// semi de1 specific
+sram.vhdl
+flashrom.vhdl
+sdram_statemachine.vhdl
+address_decoder.vhdl
+
+// de1 specific
+atari800core.vhd // top level for DE1
+i2sslave.vhdl
+hexdecoder.vhd
+gpio.vhd
+ledsw.vhd
+
+// altera megafunctions
+pll.vhd 
+zpu_ram.vhd
+zpu_rom.vhd
+
+-----------------------------------------------------------------------------------
+(c) Mike Stirling (from Spectrum core)
+See header for Mike's copyright note
+Parameters modified for my use case
+
+i2c_loader.vhd
+i2s_intf.vhd
+
+-----------------------------------------------------------------------------------
+(c) Peter Wendrich
+Please contact Peter if you wish to use them. I have permission for use as part of the Atari800 core.
+
+cpu_6510.vhd
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+
+-----------------------------------------------------------------------------------
+---- Copyright (c) 2008 Ãvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+ZPU implementation. See headers for more details
+I made a few fixes to make it work for my use case.
+
+zpu_core.vhd
+zpupkg.vhd
+
+-----------------------------------------------------------------------------------
+(c) Scott Larson
+See file header
+
+spi_master.vhd
+
+-----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+zpu/*.[ch]
+SD card/OSD
+-----------------------------------------------------------------------------------
+(c) Mark Watson
+Also some portions taken from SDrive, so (c) Bob and Raster
+
+I am happy for these to be used freely for commercial and non-commercial use.
+
+debug.h  led.h   pause.h  regs.h  types.h  uart.h
+bootdump.c  debug.c  led.c  main.c  regs.c  test.c  uart.c
+
+zpuromgen.c
+
+----------------------------------------------------------------------------------
+(c) Pascal Stang + Bob and Raster
+spi.c
+spi.h
+mmc.c  
+mmc.h
+mmcconf.h 
+
+-----------------------------------------------------------------------------------
+(c) ChaN
+Petit File System
+
+integer.h  
+diskio.h  
+pff.h
+pff.c  
Index: de1/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: de1/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: de1/defunct/hexdecoder.vhd
===================================================================
--- de1/defunct/hexdecoder.vhd	(nonexistent)
+++ de1/defunct/hexdecoder.vhd	(revision 1)
@@ -0,0 +1,75 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY hexdecoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+);
+END hexdecoder;
+
+ARCHITECTURE vhdl OF hexdecoder IS
+	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
+	signal digit_next : std_logic_vector(6 downto 0);
+	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
+BEGIN
+	--numinv <= not(NUMBER);
+	numinv <= NUMBER;
+	process(numinv)
+	begin
+		case numinv is
+			when "0000" =>
+				digit_next <= "1111111";
+			when "0001" =>
+				digit_next <= "1111001";
+			when "0010" =>
+				digit_next <= "0100100";
+			when "0011" =>
+				digit_next <= "0110000";
+			when "0100" =>
+				digit_next <= "0011001";
+			when "0101" =>
+				digit_next <= "0010010";
+			when "0110" =>
+				digit_next <= "0000010";
+			when "0111" =>
+				digit_next <= "1111000";
+			when "1000" =>
+				digit_next <= "0000000";
+			when "1001" =>
+				digit_next <= "0011000";
+			when "1010" =>
+				digit_next <= "0001000";
+			when "1011" =>
+				digit_next <= "0000011";
+			when "1100" =>
+				digit_next <= "1000110";
+			when "1101" =>
+				digit_next <= "0100001";
+			when "1110" =>
+				digit_next <= "0000110";
+			when "1111" =>
+				digit_next <= "0001110";
+			when others =>
+				digit_next <= "1111111";
+		end case;
+	end process;
+	
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	digit<=digit_reg;
+END vhdl;
\ No newline at end of file
Index: de1/i2sslave.vhdl
===================================================================
--- de1/i2sslave.vhdl	(nonexistent)
+++ de1/i2sslave.vhdl	(revision 1)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY i2sslave IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	BCLK : IN STD_LOGIC;
+	DACLRC : IN STD_LOGIC;
+	
+	LEFT_IN : in std_logic_vector(15 downto 0);
+	RIGHT_IN : in std_logic_vector(15 downto 0);
+	
+	MCLK_2 : OUT STD_LOGIC;
+	DACDAT : OUT STD_LOGIC
+);
+END i2sslave;
+
+ARCHITECTURE vhdl OF i2sslave IS
+	signal bclk_reg : std_logic;
+	signal bclk_last_reg : std_logic;
+	signal daclrc_reg : std_logic;
+	signal daclrc_last_reg : std_logic;
+	
+	signal shiftreg_reg : std_logic_vector(15 downto 0);
+	signal shiftreg_next : std_logic_vector(15 downto 0);
+	
+	signal CLK_FAKE : std_logic;
+BEGIN
+	MCLK_2 <= CLK_FAKE; -- bad practice, but pll out of...
+	
+	-- Data read on bclk low->high transition
+	-- daclrc is set on bclk high->low transition
+	
+	-- register inputs
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			CLK_FAKE <= not(CLK_FAKE);
+		end if;
+	end process;
+	
+	process(CLK_FAKE)
+	begin	
+		if (CLK_FAKE'event and CLK_FAKE='1') then
+			bclk_reg <= bclk;
+			bclk_last_reg <= bclk_reg;
+			daclrc_reg <= daclrc;
+			daclrc_last_reg <= daclrc_reg;
+			shiftreg_reg <= shiftreg_next;
+		end if;
+	end process;
+	
+	-- sample on change to daclrc, shift out bit if required
+	process(daclrc_reg,daclrc_last_reg,bclk_reg,shiftreg_reg,left_in,right_in,bclk_last_reg)
+		variable reload : std_logic;
+	begin
+		reload := '0';
+		shiftreg_next <= shiftreg_reg;
+		
+		if (daclrc_reg = '1' and daclrc_last_reg = '0') then
+			shiftreg_next <= right_in;
+			reload := '1';
+		end if;
+		
+		if (daclrc_reg = '0' and daclrc_last_reg = '1') then
+			shiftreg_next <= left_in;
+			reload := '1';
+		end if;
+		
+		if (bclk_reg = '0' and bclk_last_reg = '1' and reload='0') then
+				shiftreg_next <= shiftreg_reg(14 downto 0)&'0';
+		end if;
+			
+	end process;
+	
+	DACDAT <= shiftreg_reg(15);
+END vhdl;
\ No newline at end of file
Index: de1/pll.qip
===================================================================
--- de1/pll.qip	(nonexistent)
+++ de1/pll.qip	(revision 1)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: mcc216/PLLJ_PLLSPE_INFO.txt
===================================================================
--- mcc216/PLLJ_PLLSPE_INFO.txt	(nonexistent)
+++ mcc216/PLLJ_PLLSPE_INFO.txt	(revision 1)
@@ -0,0 +1,5 @@
+PLL_Name	pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
+PLLJITTER	NA
+PLLSPEmax	84
+PLLSPEmin	-53
+
Index: mcc216/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mcc216/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mcc216/pll.cmp
===================================================================
--- mcc216/pll.cmp	(nonexistent)
+++ mcc216/pll.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mcc216/pokey_ps2_decoder.vhdl
===================================================================
--- mcc216/pokey_ps2_decoder.vhdl	(nonexistent)
+++ mcc216/pokey_ps2_decoder.vhdl	(revision 1)
@@ -0,0 +1,468 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_ps2_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : std_logic;
+	-- ENABLE : IN STD_LOGIC; TODO Pokey debounce and scanning can be disabled
+	
+	-- ps2 keyboard input
+	KEY_EVENT : IN STD_LOGIC;
+	KEY_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
+	KEY_EXTENDED : IN STD_LOGIC;
+	KEY_UP : IN STD_LOGIC;
+	
+	-- pokey output
+	KBCODE : OUT STD_LOGIC_VECTOR(7 downto 0);
+	KEY_HELD : OUT STD_LOGIC;
+	SHIFT_PRESSED : OUT STD_LOGIC;
+	BREAK_PRESSED : OUT STD_LOGIC;
+	KEY_INTERRUPT : OUT STD_LOGIC;
+	
+	-- other output
+	CONSOL_START : OUT STD_LOGIC;
+	CONSOL_SELECT : OUT STD_LOGIC;
+	CONSOL_OPTION : OUT STD_LOGIC;
+	
+	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+	
+	SYSTEM_RESET : out std_logic;
+	
+	VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+);
+END pokey_ps2_decoder;
+
+ARCHITECTURE vhdl OF pokey_ps2_decoder IS
+	signal left_shift_pressed_reg : std_logic;
+	signal left_shift_pressed_next : std_logic;
+	signal right_shift_pressed_reg : std_logic;
+	signal right_shift_pressed_next : std_logic;	
+	
+	signal left_control_pressed_reg : std_logic;
+	signal left_control_pressed_next : std_logic;	
+	signal right_control_pressed_reg : std_logic;
+	signal right_control_pressed_next : std_logic;	
+	
+	signal kbcode_next : std_logic_vector(7 downto 0);
+	signal kbcode_reg : std_logic_vector(7 downto 0); -- XXX remove unused upper bits
+	
+	signal interrupt_next : std_logic;
+	signal interrupt_reg : std_logic;
+	
+	signal break_next : std_logic;
+	signal break_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal start_next : std_logic;
+	signal start_reg : std_logic;
+	signal select_next : std_logic;
+	signal select_reg : std_logic;	
+	signal option_next : std_logic;
+	signal option_reg : std_logic;
+	
+	signal virtual_up_next : std_logic;
+	signal virtual_up_reg : std_logic;
+	signal virtual_down_next : std_logic;
+	signal virtual_down_reg : std_logic;
+	signal virtual_left_next : std_logic;
+	signal virtual_left_reg : std_logic;
+	signal virtual_right_next : std_logic;
+	signal virtual_right_reg : std_logic;
+	signal virtual_stick_pressed_next : std_logic;
+	signal virtual_stick_pressed_reg : std_logic;
+	
+	signal system_reset_next : std_logic;
+	signal system_reset_reg : std_logic;	
+
+	signal virtual_keys_next : std_logic_vector(3 downto 0);
+	signal virtual_keys_reg : std_logic_vector(3 downto 0);	
+	
+	signal no_kbcode_update : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			left_shift_pressed_reg <= '0';
+			right_shift_pressed_reg <= '0';
+			
+			left_control_pressed_reg <= '0';
+			right_control_pressed_reg <= '0';
+			
+			kbcode_reg <= X"3F";
+			
+			interrupt_reg <= '0';
+			
+			break_reg <= '0';
+			
+			key_held_reg <= '0';
+			
+			start_reg <= '0';
+			select_reg <= '0';
+			option_reg <= '0';
+			
+			virtual_up_reg <= '0';
+			virtual_down_reg <= '0';
+			virtual_left_reg <= '0';
+			virtual_right_reg <= '0';
+			virtual_stick_pressed_reg <= '0';
+			
+			system_reset_reg <= '0';
+			
+			virtual_keys_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			left_shift_pressed_reg <= left_shift_pressed_next;
+			right_shift_pressed_reg <= right_shift_pressed_next;
+			
+			left_control_pressed_reg <= left_control_pressed_next;
+			right_control_pressed_reg <= right_control_pressed_next;			
+			
+			kbcode_reg <= kbcode_next;
+			
+			interrupt_reg <= interrupt_next;
+			
+			break_reg <= break_next;
+			
+			key_held_reg <= key_held_next;
+			
+			start_reg <= start_next;
+			select_reg <= select_next;
+			option_reg <= option_next;
+			
+			virtual_up_reg <= virtual_up_next;
+			virtual_down_reg <= virtual_down_next;
+			virtual_left_reg <= virtual_left_next;
+			virtual_right_reg <= virtual_right_next;
+			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+			
+			system_reset_reg <= system_reset_next;
+			virtual_keys_reg <= virtual_keys_next;
+		end if;
+	end process;
+	
+	-- update key pressed
+	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg, virtual_keys_reg)
+	begin
+		left_shift_pressed_next <= left_shift_pressed_reg;
+		right_shift_pressed_next <= right_shift_pressed_reg;
+		
+		left_control_pressed_next <= left_control_pressed_reg;
+		right_control_pressed_next <= right_control_pressed_reg;		
+	
+		kbcode_next <= kbcode_reg;
+		interrupt_next <= '0';
+		
+		break_next <= break_reg;
+	
+		start_next <= start_reg;
+		select_next <= select_reg;
+		option_next <= option_reg;
+		
+		virtual_up_next <= virtual_up_reg;
+		virtual_down_next <= virtual_down_reg;
+		virtual_left_next <= virtual_left_reg;
+		virtual_right_next <= virtual_right_reg;				
+		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+		
+		system_reset_next <= system_reset_reg;
+		virtual_keys_next <= virtual_keys_reg;
+		
+		key_held_next <= key_held_reg;
+		
+		no_kbcode_update <= '0';
+	
+		-- Core functionality exactly as the Atari layout
+		if (key_event = '1') then
+			interrupt_next <= not(key_up);			
+			key_held_next <= not(key_up);
+			
+			case key_extended&key_code is 
+			
+				-- Basic mapping - should allow all keys on Atari, just fiddly
+				when 
+					'0'&X"AA"|'1'&X"AA"|  -- BAT SUCCESSFUL
+					'0'&X"FC"|'1'&X"FC"   -- BAT FAIL
+					=>
+					no_kbcode_update <= '1';
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"4B" => --L
+					kbcode_next <= X"00";
+				when '0'&X"3B" => --J
+					kbcode_next <= X"01";					
+				when '0'&X"4C" => --;
+					kbcode_next <= X"02";										
+				when '0'&X"42" => --K
+					kbcode_next <= X"05";				
+				when '0'&X"79" => --+
+					kbcode_next <= X"06";
+				when '0'&X"7C" => --*
+					kbcode_next <= X"07";
+				when '0'&X"44" => --O
+					kbcode_next <= X"08";
+				when '0'&X"4D" => --P
+					kbcode_next <= X"0A";
+				when '0'&X"3C" => --U
+					kbcode_next <= X"0B";
+				when '0'&X"5A" => --Enter
+					kbcode_next <= X"0C";
+				when '0'&X"43" => --I
+					kbcode_next <= X"0D";
+				when '0'&X"4E" => -- -
+					kbcode_next <= X"0E";
+				when '0'&X"55" => -- =
+					kbcode_next <= X"0F";
+
+				when '0'&X"2A" => --V
+					kbcode_next <= X"10";
+				when '0'&X"05" => --Help (Using F1)
+					kbcode_next <= X"11";					
+				when '0'&X"21" => --C
+					kbcode_next <= X"12";										
+				when '0'&X"32" => --B
+					kbcode_next <= X"15";				
+				when '0'&X"22" => --X
+					kbcode_next <= X"16";
+				when '0'&X"1A" => --Z
+					kbcode_next <= X"17";
+				when '0'&X"25" => --4
+					kbcode_next <= X"18";
+				when '0'&X"26" => --3
+					kbcode_next <= X"1A";
+				when '0'&X"36" => --6
+					kbcode_next <= X"1B";
+				when '0'&X"76" => --Esc
+					kbcode_next <= X"1C";
+				when '0'&X"2E" => --5
+					kbcode_next <= X"1D";
+				when '0'&X"1E" => --2
+					kbcode_next <= X"1E";
+				when '0'&X"16" => --1
+					kbcode_next <= X"1F";
+
+				when '0'&X"41" => --,
+					kbcode_next <= X"20";
+				when '0'&X"29" => --Spc
+					kbcode_next <= X"21";					
+				when '0'&X"49" => --.
+					kbcode_next <= X"22";										
+				when '0'&X"31" => --N
+					kbcode_next <= X"23";
+				when '0'&X"3A" => --M
+					kbcode_next <= X"25";				
+				when '0'&X"4A" => --/
+					kbcode_next <= X"26";
+				when '1'&X"11" => --Inv
+					kbcode_next <= X"27";
+				when '0'&X"2D" => --R
+					kbcode_next <= X"28";
+				when '0'&X"24" => --E
+					kbcode_next <= X"2A";
+				when '0'&X"35" => --Y
+					kbcode_next <= X"2B";
+				when '0'&X"0D" => --Tab
+					kbcode_next <= X"2C";
+				when '0'&X"2C" => --T
+					kbcode_next <= X"2D";
+				when '0'&X"1D" => --W
+					kbcode_next <= X"2E";
+				when '0'&X"15" => --Q
+					kbcode_next <= X"2F";					
+					
+				when '0'&X"46" => --9
+					kbcode_next <= X"30";				
+				when '0'&X"45" => --0
+					kbcode_next <= X"32";										
+				when '0'&X"3D" => --7
+					kbcode_next <= X"33";
+				when '0'&X"66" => --Backspace
+					kbcode_next <= X"34";						
+				when '0'&X"3E" => --8
+					kbcode_next <= X"35";				
+				when '0'&X"54" => --< (using [)
+					kbcode_next <= X"36";
+				when '0'&X"5B" => --> (using ])
+					kbcode_next <= X"37";
+				when '0'&X"2B" => --F
+					kbcode_next <= X"38";
+				when '0'&X"33" => --H
+					kbcode_next <= X"39";					
+				when '0'&X"23" => --D
+					kbcode_next <= X"3A";
+				when '0'&X"58" => --Caps
+					kbcode_next <= X"3C";
+				when '0'&X"34" => --G
+					kbcode_next <= X"3D";
+				when '0'&X"1B" => --S
+					kbcode_next <= X"3E";
+				when '0'&X"1C" => --A
+					kbcode_next <= X"3F";
+
+				when '0'&X"77" => --Break - XXX BUG, also presses 14, since E1 ext code...
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+				when '1'&X"77" => --Break
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+					
+				-- XXX BUGS
+				-- i) press shift when already holding key - does not update kbcode
+				-- ii) press key, then press another, then release second key. Should go back to first...
+				when '0'&X"12" => --Left shift
+					no_kbcode_update <= '1';
+					left_shift_pressed_next <= not(key_UP);					
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"59" => --Right shift
+					no_kbcode_update <= '1';
+					right_shift_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+					
+				when '0'&X"14" => --Left control
+					no_kbcode_update <= '1';
+					left_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '1'&X"14" => --Right control
+					no_kbcode_update <= '1';
+					right_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';			
+					key_held_next <= '0';
+					
+				when '0'&X"06" => --Start (F2)
+					no_kbcode_update <= '1';
+					start_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"04" => --Select (F3)
+					no_kbcode_update <= '1';
+					select_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"0C" => --Option (F4)
+					no_kbcode_update <= '1';
+					option_next <= not(key_UP);
+					interrupt_next <= '0';					
+					key_held_next <= '0';
+
+				-- TODO will also be useful to cursor control...
+				when '1'&X"75" => -- up
+					no_kbcode_update <= '1';
+					virtual_up_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"72" => -- down
+					no_kbcode_update <= '1';
+					virtual_down_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"6b" => -- left
+					no_kbcode_update <= '1';
+					virtual_left_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"74" => -- right
+					no_kbcode_update <= '1';
+					virtual_right_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';
+				when '1'&X"27" => -- right windows key -> fire button
+					no_kbcode_update <= '1';
+					virtual_stick_pressed_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"0a" => -- f8 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(0) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"01" => -- f9 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(1) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';						
+					
+				when '0'&X"09" => -- f10 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(2) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';						
+					
+				when '0'&X"78" => -- f11 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(3) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"07" => -- f12 => system reset
+					no_kbcode_update <= '1';
+					system_reset_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';										
+					
+				when others =>
+					no_kbcode_update <= '1';
+					-- nop
+				-- Idea: Use Windows key and Alt for atari shift/control. Then use keyboard ones for 'nice' mapping as displayed on keyboard?
+			end case;
+			
+			if (key_up = '1' or no_kbcode_update = '1') then
+				kbcode_next <= kbcode_reg;				
+			else
+				kbcode_next(7 downto 6) <= (left_control_pressed_reg or right_control_pressed_reg)&(left_shift_pressed_reg or right_shift_pressed_reg);
+			end if;
+		end if;
+		
+		-- Then override a few for convenience
+		-- e.g. if we press '#' on the keyboard we want to see '#' on the atari, even though on the atari its shift a different key.
+
+--http://atariwiki.de/wiki/Wiki.jsp?page=KBCODE
+-- 			$00	$01	$02	$03	$04	$05	$06	$07	$08	$09	$0A	$0B	$0C	$0D	$0E	$0F
+--		$00	L		J		;		F1		F2		K		+		*		O	 			P		U		CR		I		-		=
+--		$10	V		Help	C		F3		F4		B		X		Z		4	 			3		6		Esc	5		2		1
+--		$20	,		Spc	.		N	 			M		/		Inv	R	 			E		Y		Tab	T		W		Q
+--		$30	9	 			0		7		BS		8		<		>		F		H		D	 			Caps	G		S		A
+--together with Shift Key: add +$40
+--together with Control key: add +$80
+
+-- Would be great to have option of using real Atari keyboard, but probably not worthwhile yet.
+
+	end process;
+			
+	-- output
+	kbcode <= kbcode_reg;
+	KEY_HELD <= key_held_reg;
+	shift_pressed <= left_shift_pressed_reg or right_shift_pressed_reg;
+	break_pressed <= break_reg;
+	
+	key_interrupt <= interrupt_reg;
+	
+	consol_start <= start_reg;
+	consol_select <= select_reg;
+	consol_option <= option_reg;
+	
+	VIRTUAL_STICKS <= not(virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg&virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg);
+	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+	
+	system_reset <= system_reset_reg;
+	virtual_keys <= virtual_keys_reg;
+		
+END vhdl;
\ No newline at end of file
Index: mcc216/zpu_config_regs.vhdl
===================================================================
--- mcc216/zpu_config_regs.vhdl	(nonexistent)
+++ mcc216/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,501 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(1 downto 0);
+	signal ram_select_reg : std_logic_vector(1 downto 0);
+	signal rom_select_next : std_logic_vector(1 downto 0);
+	signal rom_select_reg : std_logic_vector(1 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				rom_select_reg <= "01";
+				ram_select_reg <= "10";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(9 downto 8);
+				rom_select_next <= cpu_DATA_IN(13 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(9 downto 8) <= ram_select_reg;
+				data_out(13 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= key;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				--data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1'; -- TODO
+	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= '1';
+	COMPOSITE_ON_HSYNC <= '0';
+	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+end vhdl;
+
+
Index: mist/atari800core.qsf
===================================================================
--- mist/atari800core.qsf	(nonexistent)
+++ mist/atari800core.qsf	(revision 1)
@@ -0,0 +1,634 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		minimig_de1_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_22 -to CLOCK_50[0]
+set_location_assignment PIN_23 -to CLOCK_50[1]
+set_location_assignment PIN_128 -to CLOCK_32[0]
+set_location_assignment PIN_129 -to CLOCK_32[1]
+set_location_assignment PIN_54 -to CLOCK_27[0]
+set_location_assignment PIN_55 -to CLOCK_27[1]
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name TPD_REQUIREMENT "2 ns"
+set_global_assignment -name TSU_REQUIREMENT "2 ns"
+set_global_assignment -name TCO_REQUIREMENT "2 ns"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name MISC_FILE atari800core.dpf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
+
+#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
+
+
+set_global_assignment -name VHDL_FILE data_io.vhdl
+set_global_assignment -name QIP_FILE basic.qip
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name VERILOG_FILE hq_dac.v
+set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+set_global_assignment -name VHDL_FILE ramint.vhd
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name VHDL_FILE internalromram.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name QIP_FILE rom16.qip
+set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SPI_DI -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SPI_DO -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SPI_SS2 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "data_io:mist_spi_interface|SPI_CLK" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
+set_global_assignment -name QIP_FILE mist_sector_buffer.qip
+set_global_assignment -name VHDL_FILE covox.vhd
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SPI_DI -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SPI_DO -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SPI_SS2 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=119" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=119" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=382" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=25945" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=37736" -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: mist/atari800core_assignment_defaults.qdf
===================================================================
--- mist/atari800core_assignment_defaults.qdf	(nonexistent)
+++ mist/atari800core_assignment_defaults.qdf	(revision 1)
@@ -0,0 +1,796 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition
+# Date created = 09:08:15  February 16, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Night Fury"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Night Fury"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Night Fury"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Night Fury"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Night Fury"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Night Fury"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Night Fury"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
Index: mist/atari800core.qpf
===================================================================
--- mist/atari800core.qpf	(nonexistent)
+++ mist/atari800core.qpf	(revision 1)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: mist/atari800core.vhd
===================================================================
--- mist/atari800core.vhd	(nonexistent)
+++ mist/atari800core.vhd	(revision 1)
@@ -0,0 +1,1846 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
+--		PS2K_CLK :  IN  STD_LOGIC;
+--		PS2K_DAT :  IN  STD_LOGIC;
+--		PS2M_CLK :  IN  STD_LOGIC;
+--		PS2M_DAT :  IN  STD_LOGIC;		
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+--		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+--		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_nCS :  OUT  STD_LOGIC;
+		SDRAM_nRAS :  OUT  STD_LOGIC;
+		SDRAM_nCAS :  OUT  STD_LOGIC;
+		SDRAM_nWE :  OUT  STD_LOGIC;
+		SDRAM_DQMH :  OUT  STD_LOGIC;
+		SDRAM_DQML :  OUT  STD_LOGIC;
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+--		SD_DAT0 :  IN  STD_LOGIC;
+--		SD_CLK :  OUT  STD_LOGIC;
+--		SD_CMD :  OUT  STD_LOGIC;
+--		SD_DAT3 :  OUT  STD_LOGIC
+
+		LED : OUT std_logic;
+		
+		UART_TX :  OUT  STD_LOGIC;
+		UART_RX :  IN  STD_LOGIC;
+		
+		SPI_DO :  INOUT  STD_LOGIC;
+		SPI_DI :  IN  STD_LOGIC;
+		SPI_SCK :  IN  STD_LOGIC;
+		SPI_SS2 :  IN  STD_LOGIC;		
+		SPI_SS3 :  IN  STD_LOGIC;		
+		SPI_SS4 :  IN  STD_LOGIC;
+		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+--
+--component generic_ram_infer IS
+--	generic
+--	(
+--		ADDRESS_WIDTH : natural := 9;
+--		SPACE : natural := 512;
+--		DATA_WIDTH : natural := 8
+--	);
+--   PORT
+--   (
+--      clock: IN   std_logic;
+--      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+--      address:  IN   std_logic_vector(address_width-1 downto 0);
+--      we:    IN   std_logic;
+--      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+--   );
+--END component;
+
+component mist_sector_buffer IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END component;
+
+component synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END component;
+
+component data_io IS 
+	PORT
+	(
+		CLK : in std_logic;
+		RESET_n : in std_logic;
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO: out std_logic;
+	   SPI_MOSI : in std_logic;
+		
+		-- Sector access request
+		request : in std_logic;
+		sector : in std_logic_vector(23 downto 0);
+		ready : out std_logic;
+		
+		-- DMA to RAM
+		ADDR: out std_logic_vector(8 downto 0);
+		DATA_OUT : out std_logic_vector(7 downto 0);
+		DATA_IN : in std_logic_vector(7 downto 0);
+		WR_EN : out std_logic
+	 );
+end component;
+
+component user_io
+	PORT(
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO : out std_logic;
+	   SPI_MOSI : in std_logic;
+	   CORE_TYPE : in std_logic_vector(7 downto 0);
+		JOY0 : out std_logic_vector(5 downto 0);
+		JOY1 : out std_logic_vector(5 downto 0);
+		KEYBOARD : out std_logic_vector(127 downto 0);
+		BUTTONS : out std_logic_vector(1 downto 0);
+		SWITCHES : out std_logic_vector(1 downto 0)
+	  );
+end component;
+
+COMPONENT complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);			
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END component;
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+	
+END component;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+	);
+END COMPONENT;
+
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : in std_logic_vector(5 downto 0);
+		 cart_select : in std_logic_vector(6 downto 0);
+		 cart_activate : in std_logic;
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 D6_WR_ENABLE : out std_logic
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 COMPLETE : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+component sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END component;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 sector : out std_logic_vector(31 downto 0);
+		 sector_request : out std_logic;
+		 sector_ready : in std_logic
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+component covox IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	covox_channel0 : out std_logic_vector(7 downto 0);
+	covox_channel1 : out std_logic_vector(7 downto 0);
+	covox_channel2 : out std_logic_vector(7 downto 0);
+	covox_channel3 : out std_logic_vector(7 downto 0)
+);
+END component;
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+signal CART_CCTL_N : std_logic;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE_DUMMY :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+--SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal UART_TXD_dummy : std_logic;
+
+-- STUB OUT FOR NOW
+SIGNAL		PS2K_CLK :  STD_LOGIC;
+SIGNAL		PS2K_DAT :  STD_LOGIC;
+signal		JOY1_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal		JOY2_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+
+SIGNAL		SD_DAT0 :  STD_LOGIC;
+SIGNAL		SD_CLK :  STD_LOGIC;
+SIGNAL		SD_CMD :  STD_LOGIC;
+SIGNAL		SD_DAT3 :  STD_LOGIC;
+
+signal mist_buttons : std_logic_vector(1 downto 0);
+signal mist_switches : std_logic_vector(1 downto 0);
+
+signal keyboard : std_logic_vector(127 downto 0);
+signal atari_keyboard : std_logic_vector(63 downto 0);
+
+SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
+SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
+SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
+
+SIGNAL	CONSOL_OPTION_DUMMY :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT_DUMMY :  STD_LOGIC;
+SIGNAL	CONSOL_START_DUMMY :  STD_LOGIC;
+
+signal capslock_pressed : std_logic;
+signal capsheld_next : std_logic;
+signal capsheld_reg : std_logic;
+
+signal mist_sector_ready : std_logic;
+signal mist_sector_ready_sync : std_logic;
+signal mist_sector_request : std_logic;
+signal mist_sector_request_sync : std_logic;
+signal mist_sector : std_logic_vector(31 downto 0);
+signal mist_sector_sync : std_logic_vector(31 downto 0);
+
+		
+signal mist_addr : std_logic_vector(8 downto 0);
+signal mist_do : std_logic_vector(7 downto 0);
+signal mist_di : std_logic_vector(7 downto 0);
+signal mist_wren : std_logic;
+
+signal spi_miso_data : std_logic;
+signal spi_miso_io : std_logic;
+
+signal covox_write_enable : std_logic;
+signal covox_channel0 : std_logic_vector(7 downto 0);
+signal covox_channel1 : std_logic_vector(7 downto 0);
+signal covox_channel2 : std_logic_vector(7 downto 0);
+signal covox_channel3 : std_logic_vector(7 downto 0);
+
+BEGIN 
+
+	
+-- mist spi io
+mist_spi_interface : data_io 
+	PORT map
+	(
+		CLK =>spi_sck,
+		RESET_n =>reset_n,
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+		SPI_CLK =>spi_sck,
+		SPI_SS_IO => spi_ss2,
+		SPI_MISO => spi_miso_data,
+		SPI_MOSI => spi_di,
+		
+		-- Sector access request
+		request => mist_sector_request_sync,
+		sector => mist_sector_sync(23 downto 0),
+		ready => mist_sector_ready,
+		
+		-- DMA to RAM
+		ADDR => mist_addr,
+		DATA_OUT => mist_do,
+		DATA_IN => mist_di,
+		WR_EN => mist_wren
+	 );
+ 
+	select_sync : synchronizer
+	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
+
+	select_sync2 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
+
+	sector_sync0 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
+
+	sector_sync1 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
+
+	sector_sync2 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
+
+	sector_sync3 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
+
+	sector_sync4 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
+
+	sector_sync5 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
+
+	sector_sync6 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
+
+	sector_sync7 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
+
+	sector_sync8 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
+
+	sector_sync9 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
+
+	sector_sync10 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
+
+	sector_sync11 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
+
+	sector_sync12 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
+
+	sector_sync13 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
+
+	sector_sync14 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
+
+	sector_sync15 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
+
+	sector_sync16 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
+
+	sector_sync17 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
+
+	sector_sync18 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
+
+	sector_sync19 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
+
+	sector_sync20 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
+
+	sector_sync21 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
+
+	sector_sync22 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
+
+	sector_sync23 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
+	
+	
+	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
+
+	-- TODO, dual port, dual clock! 
+--	mist_sector_buffer : generic_ram_infer
+--	generic map
+--	(
+--		ADDRESS_WIDTH => 9,
+--		SPACE => 512,
+--		DATA_WIDTH => 8
+--	)
+--   PORT map
+--   (
+--      clock => spi_sck,
+--      data => mist_do,
+--      address => mist_addr,
+--      we => mist_wren,
+--      q => mist_di
+--   );
+
+mist_sector_buffer1 : mist_sector_buffer
+	PORT map
+	(
+		address_a		=> mist_addr,
+		address_b		=> ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
+		clock_a		=> spi_sck,
+		clock_b		=> clk,
+		data_a		=> mist_do,
+		data_b		=> zpu_do,
+		wren_a		=> mist_wren,
+		wren_b		=> '0',
+		q_a		=> mist_di,
+		q_b		=> zpu_sector_data
+	);
+	
+my_user_io : user_io
+	PORT map(
+	   SPI_CLK => SPI_SCK,
+	   SPI_SS_IO => CONF_DATA0,
+	   SPI_MISO => SPI_miso_io,
+	   SPI_MOSI => SPI_DI,
+	   CORE_TYPE => x"A4",
+		JOY0 => joy1,
+		JOY1 => joy2,
+		KEYBOARD => keyboard,
+		BUTTONS => mist_buttons,
+		SWITCHES => mist_switches
+	  );
+	  
+	 joy1_n <= not(joy1);
+	 joy2_n <= not(joy2);
+	 
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			capsheld_reg <= '0';
+		elsif (clk'event and clk='1') then
+			capsheld_reg <= capsheld_next;
+		end if;
+	end process;
+
+	process(keyboard,capsheld_reg)
+	begin
+		capsheld_next <= capsheld_reg;
+		capslock_pressed <= '0';
+		
+		if ((keyboard(58) xor capsheld_reg)='1') then
+			capsheld_next <= keyboard(58);
+			
+			-- assert something for 10 frames
+			capslock_pressed <= '1';
+		end if;
+	end process;
+	
+atari_keyboard(63) <= keyboard(30);
+atari_keyboard(62) <= keyboard(31);
+atari_keyboard(61) <= keyboard(34);
+atari_keyboard(60) <= '0';
+atari_keyboard(58) <= keyboard(32);
+atari_keyboard(57) <= keyboard(35);
+atari_keyboard(56) <= keyboard(33);
+atari_keyboard(55) <= keyboard(13);
+atari_keyboard(54) <= keyboard(12);
+atari_keyboard(53) <= keyboard(9);
+atari_keyboard(52) <= keyboard(14);
+atari_keyboard(51) <= keyboard(8);
+atari_keyboard(50) <= keyboard(11);
+atari_keyboard(48) <= keyboard(10);
+atari_keyboard(47) <= keyboard(16);
+atari_keyboard(46) <= keyboard(17);
+atari_keyboard(45) <= keyboard(20);
+atari_keyboard(44) <= keyboard(15);
+atari_keyboard(43) <= keyboard(21);
+atari_keyboard(42) <= keyboard(18);
+atari_keyboard(40) <= keyboard(19);
+atari_keyboard(39) <= keyboard(56);
+atari_keyboard(38) <= keyboard(53);
+atari_keyboard(37) <= keyboard(50);
+atari_keyboard(35) <= keyboard(49);
+atari_keyboard(34) <= keyboard(52);
+atari_keyboard(33) <= keyboard(57);
+atari_keyboard(32) <= keyboard(51);
+atari_keyboard(31) <= keyboard(2);
+atari_keyboard(30) <= keyboard(3);
+atari_keyboard(29) <= keyboard(6);
+atari_keyboard(28) <= keyboard(1);
+atari_keyboard(27) <= keyboard(7);
+atari_keyboard(26) <= keyboard(4);
+atari_keyboard(24) <= keyboard(5);
+atari_keyboard(23) <= keyboard(44);
+atari_keyboard(22) <= keyboard(45);
+atari_keyboard(21) <= keyboard(48);
+atari_keyboard(18) <= keyboard(46);
+atari_keyboard(17) <= keyboard(59);
+atari_keyboard(16) <= keyboard(47);
+atari_keyboard(15) <= keyboard(27);
+atari_keyboard(14) <= keyboard(26);
+atari_keyboard(13) <= keyboard(23);
+atari_keyboard(12) <= keyboard(28);
+atari_keyboard(11) <= keyboard(22);
+atari_keyboard(10) <= keyboard(25);
+atari_keyboard(8) <= keyboard(24);
+atari_keyboard(7) <= keyboard(41);
+atari_keyboard(6) <= keyboard(40);
+atari_keyboard(5) <= keyboard(37);
+atari_keyboard(2) <= keyboard(39);
+atari_keyboard(1) <= keyboard(36);
+atari_keyboard(0) <= keyboard(38);
+
+	  
+shift_pressed <= keyboard(54) or keyboard(42);
+control_pressed <= keyboard(29);
+break_pressed <= keyboard(96); -- TODO - not on st keyboard
+
+consol_start <= keyboard(60); --F2
+consol_select <= keyboard(61); --F3
+consol_option <= keyboard(62); -- F4
+		
+--f5 <= keyboard(63);
+--f6 <= keyboard(64);
+--f7 <= keyboard(65);
+--f8 <= keyboard(66);
+--f9 <= keyboard(67);
+--f10 <= keyboard(68);
+
+virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
+SYSTEM_RESET_REQUEST <= keyboard(63);
+
+process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
+	begin	
+		keyboard_response <= (others=>'1');		
+		
+		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
+			keyboard_response(0) <= '0';
+		end if;
+		
+--		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+--			keyboard_response(0) <= '0';
+--		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+end process;		 
+		  
+	-- decode address
+--decode_addr1 : complete_address_decoder
+--	generic map(width=>6)
+--	port map (addr_in=>keyboard_scan, addr_decoded=>keyboard_scan_decoded);
+	  
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+LIGHTPEN <= '1';
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 COVOX_CHANNEL_0 => covox_channel0,
+		 COVOX_CHANNEL_1 => covox_channel1,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+		 
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_left&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_right&"0000",
+  dac_out => audio_r
+);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2K_CLK,
+		 PS2_DAT => PS2K_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 ZPU_SECTOR_DI => zpu_sector_data,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 COVOX_CHANNEL_0 => covox_channel2,
+		 COVOX_CHANNEL_1 => covox_channel3, 
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+GPIO_CA2_IN <= CA2_OUT;
+GPIO_CB2_IN <= CB2_OUT;
+GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+virtual_sticks <= (others=>'1');
+virtual_triggers <= "0011";
+--b2v_inst18 : pokey_ps2_decoder
+--PORT MAP(CLK => CLK,
+--		 RESET_N => RESET_N,
+--		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+--		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+--		 KEY_UP => SYNTHESIZED_WIRE_10,
+--		 KEY_CODE => SYNTHESIZED_WIRE_11,
+--		 KEY_HELD => KEY_HELD,
+--		 SHIFT_PRESSED => SHIFT_PRESSED_DUMMY,
+--		 BREAK_PRESSED => BREAK_PRESSED_DUMMY,
+--		 CONSOL_START => CONSOL_START_DUMMY,
+--		 CONSOL_SELECT => CONSOL_SELECT_DUMMY,
+--		 CONSOL_OPTION => CONSOL_OPTION_DUMMY,
+--		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+--		 KBCODE => KBCODE_dummy,
+--		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+--		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+--		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+
+-- no cart!
+CART_RD4 <= '0';
+CART_RD5 <= '0';
+CART_REQUEST_COMPLETE <= '0';
+CART_ROM_DO <= (others=>'0');
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT(2 downto 0),
+		 ROM_DATA => ROM_DO,
+		 rom_select => "00"&ROM_SELECT, -- TODO
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA,
+		 d6_wr_enable => covox_write_enable,
+		 cart_select => "0000000",
+		 cart_activate => '0');
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B(5 downto 2),
+		 G => VGA_G(5 downto 2),
+		 R => VGA_R(5 downto 2));
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+SYNC_KEYS <= (others=> '0');
+SYNC_SWITCHES <= (others=> '1');
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DAT0,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_DAT3,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG_dummy,
+		 LEDR => LEDR_dummy,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX,
+		 sector_request => mist_sector_request,
+		 sector => mist_sector,
+		 sector_ready => mist_sector_ready_sync
+		 );
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => CLOCK_27(0),
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 locked => PLL_LOCKED);
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD_dummy,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+--	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+--	begin	
+--		keyboard_response <= (others=>'1');
+--		
+--		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+--			keyboard_response(0) <= '0';
+--		end if;
+--		
+--		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+--			keyboard_response(1) <= '0';
+--		end if;
+--		
+--		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+--			keyboard_response(1) <= '0';
+--		end if;
+--
+--		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
+--			keyboard_response(1) <= '0';
+--		end if;
+--	end process;		 
+--		 	 
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+		 TRIG2 => VIRTUAL_TRIGGERS(2),
+		 TRIG3 => VIRTUAL_TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+irr : internalromram
+  PORT map(
+    clock => clk,
+    reset_n => reset_n,
+
+	ROM_ADDR =>rom_addr,
+	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
+	ROM_REQUEST => rom_REQUEST,
+	ROM_DATA => rom_DO,
+	
+	RAM_ADDR => ram_addr,
+	RAM_WR_ENABLE => ram_WRITE_ENABLE,
+	RAM_DATA_IN => wriTE_DATA(7 downto 0),
+	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
+	RAM_REQUEST => ram_REQUEST,
+	RAM_DATA => ram_do(7 downto 0)
+	);
+
+b2v_inst20 : sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => SDRAM_DQ,
+		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => SDRAM_BA(0),
+		 SDRAM_BA1 => SDRAM_BA(1),
+		 SDRAM_CKE => SDRAM_CKE,
+		 SDRAM_CS_N => SDRAM_nCS,
+		 SDRAM_RAS_N => SDRAM_nRAS,
+		 SDRAM_CAS_N => SDRAM_nCAS,
+		 SDRAM_WE_N => SDRAM_nWE,
+		 SDRAM_ldqm => SDRAM_DQML,
+		 SDRAM_udqm => SDRAM_DQMH,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+		 
+SDRAM_A(12) <= '0';
+
+--b2v_inst20 : sdram_statemachine_mcc
+--GENERIC MAP(ADDRESS_WIDTH => 22,
+--			AP_BIT => 10,
+--			COLUMN_WIDTH => 8,
+--			ROW_WIDTH => 12
+--			)
+--PORT MAP(CLK_SYSTEM => CLK,
+--		 CLK_SDRAM => CLK_SDRAM,
+--		 RESET_N => RESET_N,
+--		 READ_EN => SDRAM_READ_ENABLE,
+--		 WRITE_EN => SDRAM_WRITE_ENABLE,
+--		 REQUEST => SDRAM_REQUEST,
+--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+--		 REFRESH => SDRAM_REFRESH,
+--		 ADDRESS_IN => SDRAM_ADDR,
+--		 DATA_IN => WRITE_DATA,
+--		 SDRAM_DQ => SDRAM_DQ,
+--		 REPLY => SDRAM_REQUEST_COMPLETE,
+--		 SDRAM_BA0 => SDRAM_BA(0),
+--		 SDRAM_BA1 => SDRAM_BA(1),
+--		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+--		 SDRAM_CS_N => SDRAM_nCS,
+--		 SDRAM_RAS_N => SDRAM_nRAS,
+--		 SDRAM_CAS_N => SDRAM_nCAS,
+--		 SDRAM_WE_N => SDRAM_nWE,
+--		 SDRAM_ldqm => SDRAM_DQML,
+--		 SDRAM_udqm => SDRAM_DQMH,
+--		 DATA_OUT => SDRAM_DO,
+--		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
+
+--SDRAM_CKE <= '1';		 
+LED <= '0';
+VGA_R(1 downto 0) <= "00";
+VGA_G(1 downto 0) <= "00";
+VGA_B(1 downto 0) <= "00";
+
+covox1 : covox
+	PORT map
+	( 
+		clk => clk,
+		addr => pbi_addr(1 downto 0),
+		data_in => WRITE_DATA(7 DOWNTO 0),
+		wr_en => covox_write_enable,
+		covox_channel0 => covox_channel0,
+		covox_channel1 => covox_channel1,
+		covox_channel2 => covox_channel2,
+		covox_channel3 => covox_channel3
+	);
+		
+END bdf_type;
\ No newline at end of file
Index: mist/mist_sector_buffer.qip
===================================================================
--- mist/mist_sector_buffer.qip	(nonexistent)
+++ mist/mist_sector_buffer.qip	(revision 1)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_sector_buffer.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_sector_buffer.cmp"]
Index: mist/atari800core.jdi
===================================================================
--- mist/atari800core.jdi	(nonexistent)
+++ mist/atari800core.jdi	(revision 1)
@@ -0,0 +1,62 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="7d0f11bf891bc55d775e"/>
+  </project>
+  <file_info/>
+  <hub_info ir_width="8" node_count="1"/>
+  <node_info>
+    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
+      <parameters>
+        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
+        <parameter name="sld_node_info" type="unknown" value="805334528"/>
+        <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
+        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
+        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
+        <parameter name="sld_data_bits" type="unknown" value="119"/>
+        <parameter name="sld_trigger_bits" type="unknown" value="119"/>
+        <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
+        <parameter name="sld_node_crc_hiword" type="unknown" value="37736"/>
+        <parameter name="sld_node_crc_loword" type="unknown" value="25945"/>
+        <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
+        <parameter name="sld_sample_depth" type="unknown" value="2048"/>
+        <parameter name="sld_segment_size" type="unknown" value="2048"/>
+        <parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
+        <parameter name="sld_state_bits" type="unknown" value="11"/>
+        <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
+        <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
+        <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
+        <parameter name="sld_trigger_level" type="unknown" value="1"/>
+        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
+        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
+        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
+        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
+        <parameter name="sld_inversion_mask_length" type="unknown" value="382"/>
+        <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
+        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
+        <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
+        <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
+        <parameter name="sld_current_resource_width" type="unknown" value="1"/>
+        <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
+        <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
+      </parameters>
+      <inputs/>
+      <outputs/>
+    </node>
+  </node_info>
+</sld_project_info>
Index: mist/atari800core.sdc
===================================================================
--- mist/atari800core.sdc	(nonexistent)
+++ mist/atari800core.sdc	(revision 1)
@@ -0,0 +1,3 @@
+create_clock -period 27MHz [get_ports CLOCK_27[0]]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: mist/mist_sector_buffer.cmp
===================================================================
--- mist/mist_sector_buffer.cmp	(nonexistent)
+++ mist/mist_sector_buffer.cmp	(revision 1)
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component mist_sector_buffer
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
Index: mist/mist_sector_buffer.vhd
===================================================================
--- mist/mist_sector_buffer.vhd	(nonexistent)
+++ mist/mist_sector_buffer.vhd	(revision 1)
@@ -0,0 +1,270 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: mist_sector_buffer.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY mist_sector_buffer IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mist_sector_buffer;
+
+
+ARCHITECTURE SYN OF mist_sector_buffer IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+			clock1	: IN STD_LOGIC ;
+			data_b	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_b	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		numwords_b => 128,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => 9,
+		widthad_b => 7,
+		width_a => 8,
+		width_b => 32,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		clock0 => clock_a,
+		wren_a => wren_a,
+		address_b => address_b,
+		clock1 => clock_b,
+		data_b => data_b,
+		wren_b => wren_b,
+		address_a => address_a,
+		data_a => data_a,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 7 0 INPUT NODEFVAL "address_b[6..0]"
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+-- Retrieval info: CONNECT: @address_b 0 0 7 0 address_b 0 0 7 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: mist/pll.qip
===================================================================
--- mist/pll.qip	(nonexistent)
+++ mist/pll.qip	(revision 1)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: mist/zpu_config_regs.vhdl
===================================================================
--- mist/zpu_config_regs.vhdl	(nonexistent)
+++ mist/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,538 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(3 downto 0);
+	
+	-- sector buffer
+	sector : out std_logic_vector(31 downto 0);
+	sector_request : out std_logic;
+	sector_ready : in std_logic;
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(3 downto 0);
+	signal ram_select_reg : std_logic_vector(3 downto 0);
+	signal rom_select_next : std_logic_vector(3 downto 0);
+	signal rom_select_reg : std_logic_vector(3 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+	
+	signal sector_next : std_logic_vector(31 downto 0);
+	signal sector_reg : std_logic_vector(31 downto 0);
+	signal sector_request_next : std_logic;
+	signal sector_request_reg : std_logic; -- cleared when ready asserted
+	
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				rom_select_reg <= "0010";
+				ram_select_reg <= "0010";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+				
+				sector_reg <= (others=>'0');
+				sector_request_reg <= '0';
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+				
+				sector_reg <= sector_next;
+				sector_request_reg <= sector_request_next;				
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	-- SECTOR
+	--   W(32 bits) - write here initiates a request_reset_zpu
+	--   R: 0=request_active
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		sector_next <= sector_reg;
+		sector_request_next <= sector_request_reg and not(sector_ready);
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(11 downto 8);
+				rom_select_next <= cpu_DATA_IN(15 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+			if(addr_decoded(11) = '1') then
+				sector_next <= cpu_data_in;
+				sector_request_next <= '1';
+			end if;
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(11 downto 8) <= ram_select_reg;
+				data_out(15 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= key;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				--data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+			
+			if (addr_decoded(11) = '1') then
+				data_out(0) <= sector_request_reg;
+			end if;			
+			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1'; -- TODO
+	--USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= '1';
+	COMPOSITE_ON_HSYNC <= '0';
+	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+	
+	sector <= sector_reg;
+	sector_request <= sector_request_reg;
+end vhdl;
+
+
Index: mist/PLLJ_PLLSPE_INFO.txt
===================================================================
--- mist/PLLJ_PLLSPE_INFO.txt	(nonexistent)
+++ mist/PLLJ_PLLSPE_INFO.txt	(revision 1)
@@ -0,0 +1,5 @@
+PLL_Name	pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
+PLLJITTER	26
+PLLSPEmax	84
+PLLSPEmin	-53
+
Index: mist/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: mist/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mist/data_io.vhdl
===================================================================
--- mist/data_io.vhdl	(nonexistent)
+++ mist/data_io.vhdl	(revision 1)
@@ -0,0 +1,204 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY data_io IS 
+	PORT
+	(
+		CLK : in std_logic;
+		RESET_n : in std_logic;
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO: out std_logic;
+	   SPI_MOSI : in std_logic;
+		
+		-- Sector access request
+		request : in std_logic;
+		sector : in std_logic_vector(23 downto 0);
+		ready : out std_logic;
+		
+		-- DMA to RAM
+		ADDR: out std_logic_vector(8 downto 0);
+		DATA_OUT : out std_logic_vector(7 downto 0);
+		DATA_IN : in std_logic_vector(7 downto 0);
+		WR_EN : out std_logic
+	 );
+end data_io;
+
+architecture vhdl of data_io is
+
+
+   signal sbuf_next : std_logic_vector(6 downto 0);
+	signal sbuf_reg : std_logic_vector(6 downto 0);
+	
+   signal cmd_next : std_logic_vector(7 downto 0);
+	signal cmd_reg : std_logic_vector(7 downto 0);
+	
+	signal cnt_next : std_logic_vector(15 downto 0);
+	signal cnt_reg : std_logic_vector(15 downto 0);
+
+	signal data_out_next : std_logic_vector(7 downto 0);
+	signal data_out_reg : std_logic_vector(7 downto 0);
+
+	signal addr_next : std_logic_vector(8 downto 0);
+	signal addr_reg : std_logic_vector(8 downto 0);
+
+	signal wren_next : std_logic;
+	signal wren_reg : std_logic;
+
+	signal ready_next : std_logic;
+	signal ready_reg : std_logic;
+	
+	signal transmit_next : std_logic_vector(7 downto 0);
+	signal transmit_reg : std_logic_vector(7 downto 0);
+	
+	signal sector_next : std_logic_vector(23 downto 0);
+	signal sector_reg : std_logic_vector(23 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+begin	 
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			cnt_reg <= (others=>'0');
+			cmd_reg <= (others=>'0');
+			sbuf_reg <= (others=>'0');
+			
+			addr_reg <= (others => '0');
+			data_out_reg <= (others => '0');
+			wren_reg <= '0';			
+			
+			ready_reg <= '0';
+			
+			transmit_reg <= (others=>'0');
+			
+			request_reg <= '0';
+			sector_reg <=(others=>'0');
+		elsif (clk'event and clk='1') then
+			cnt_reg <= cnt_next;
+			cmd_reg <= cmd_next;
+			sbuf_reg <= sbuf_next;			
+			
+			addr_reg <= addr_next;
+			data_out_reg <= data_out_next;
+			wren_reg <= wren_next;
+			
+			ready_reg <= ready_next;
+		
+			transmit_reg <= transmit_next;
+
+			request_reg <= request_next;
+			sector_reg <= sector_next;			
+		end if;
+	end process;	
+	
+--	clk_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_clk, sync=>spi_clk_next);
+--spi_clk_next <= spi_clk;
+
+--	input_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_mosi, sync=>spi_mosi_next);
+
+--	select_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
+
+	process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, request_reg, ready_reg,request,sector)
+	begin
+		cnt_next <= cnt_reg;
+		sbuf_next <= sbuf_reg;
+		cmd_next <= cmd_reg;
+		ready_next <= ready_reg and request; -- stay ready until request cleared (received by other end)
+		
+		transmit_next <= transmit_reg;
+		
+		wren_next <= '0';
+		data_out_next <= (others=>'0');		
+		addr_next <= addr_reg;
+		
+		sector_next <= sector_reg;
+		request_next <= request_reg;		
+		
+--- It polls get_status 10 times a second
+--- it uses SPI_SS2 for this
+--- it sends command code 0x50
+--- reads 4 bytes afterwards
+
+--- it reports whenever the returned value is different then the one from previous get_status
+
+--- if the lowest byte of the status (the last transmitted of the four) is 0xa5:
+--- a sector is read from sd card with the sector no being the upper/first three bytes transmitted
+--- if the sector could be read
+--- SPI_SS2 is activated
+--- command byte 0x51 is sent
+--- all 512 sector bytes are sent
+		
+		--if (spi_clk_reg = '1' and spi_clk_next = '0') then
+		transmit_next(7 downto 1) <= transmit_reg(6 downto 0);
+		transmit_next(0) <= '0';
+
+		cnt_next <= std_logic_vector(unsigned(cnt_reg) + 1);		
+		
+		sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
+		sbuf_next(0) <= SPI_MOSI;
+			
+		if (cnt_reg = X"0007") then
+			cmd_next(7 downto 1) <= sbuf_reg;
+			cmd_next(0) <= SPI_MOSI;
+			addr_next <= (others=>'1');
+			
+			sector_next <= sector;
+			request_next <= request;		
+		end if;
+			
+		--end if;
+		
+		if (spi_ss_io = '1') then
+			cnt_next <= (others=>'0');
+			cmd_next <= (others=>'0');
+		end if;	
+		
+		case cmd_reg is
+		when X"50" => --get status
+			case cnt_reg is 
+			when X"0008" =>
+				transmit_next <= sector_reg(23 downto 16);
+			when X"0010" =>
+				transmit_next <= sector_reg(15 downto 8);
+			when X"0018" =>
+				transmit_next <= sector_reg(7 downto 0);				
+			when X"0020" =>
+				transmit_next <= "1010010"&request_reg; --read request
+			when others =>
+				-- nothing
+			end case;
+		when X"51" => --sector read from sd, write it...
+			if (cnt_reg(2 downto 0) = "111") then
+				addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
+				data_out_next(7 downto 1) <= sbuf_reg;
+				data_out_next(0) <= SPI_MOSI;
+				wren_next <= request;
+				
+				if (cnt_reg(12) = '1')then
+					ready_next <= '1';
+				end if;
+			end if;
+		when others =>
+			-- nop
+		end case;
+	end process;
+
+	-- outputs
+	addr <= addr_reg;
+	data_out <= data_out_reg;
+	wr_en <= wren_reg;
+	
+	ready <= ready_reg;
+
+	spi_miso <= transmit_next(7);
+end vhdl;
Index: mist/pll.bsf
===================================================================
--- mist/pll.bsf	(nonexistent)
+++ mist/pll.bsf	(revision 1)
@@ -0,0 +1,100 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 256 184)
+	(text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 256 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 112)
+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 194 168 433 347)(font "Arial" ))
+		(text "inclk0 frequency: 27.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
+		(text "DC (%)" (rect 133 93 296 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "69/16" (rect 72 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 105 107 226 225)(font "Arial" ))
+		(text "50.00" (rect 137 107 295 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "69/32" (rect 72 121 165 253)(font "Arial" ))
+		(text "0.00" (rect 105 121 226 253)(font "Arial" ))
+		(text "50.00" (rect 137 121 295 253)(font "Arial" ))
+		(text "c2" (rect 54 135 116 281)(font "Arial" ))
+		(text "69/16" (rect 72 135 165 281)(font "Arial" ))
+		(text "-67.06" (rect 101 135 226 281)(font "Arial" ))
+		(text "50.00" (rect 137 135 295 281)(font "Arial" ))
+		(line (pt 0 0)(pt 257 0))
+		(line (pt 257 0)(pt 257 185))
+		(line (pt 0 185)(pt 257 185))
+		(line (pt 0 0)(pt 0 185))
+		(line (pt 48 91)(pt 165 91))
+		(line (pt 48 104)(pt 165 104))
+		(line (pt 48 118)(pt 165 118))
+		(line (pt 48 132)(pt 165 132))
+		(line (pt 48 146)(pt 165 146))
+		(line (pt 48 91)(pt 48 146))
+		(line (pt 69 91)(pt 69 146)(line_width 3))
+		(line (pt 96 91)(pt 96 146)(line_width 3))
+		(line (pt 130 91)(pt 130 146)(line_width 3))
+		(line (pt 164 91)(pt 164 146))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 167))
+		(line (pt 40 167)(pt 207 167))
+		(line (pt 40 48)(pt 40 167))
+		(line (pt 255 64)(pt 207 64))
+		(line (pt 255 80)(pt 207 80))
+		(line (pt 255 96)(pt 207 96))
+		(line (pt 255 112)(pt 207 112))
+	)
+)
Index: mist/pll.ppf
===================================================================
--- mist/pll.ppf	(nonexistent)
+++ mist/pll.ppf	(revision 1)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: mist/user_io.v
===================================================================
--- mist/user_io.v	(nonexistent)
+++ mist/user_io.v	(revision 1)
@@ -0,0 +1,91 @@
+module user_io(
+	   input      SPI_CLK,
+	   input      SPI_SS_IO,
+	   output     reg SPI_MISO,
+	   input      SPI_MOSI,
+	   input [7:0] CORE_TYPE,
+		output [5:0] JOY0,
+		output [5:0] JOY1,
+		output [127:0] KEYBOARD,		
+		output [1:0] BUTTONS,
+		output [1:0] SWITCHES
+	   );
+
+   reg [6:0]         sbuf;
+   reg [7:0]         cmd;
+   reg [7:0] 	      cnt;
+   reg [5:0]         joystick0;
+   reg [5:0]         joystick1;
+	reg [119:0]       keyboard;
+	reg [127:0]       keyboard_out;	
+   reg [3:0] 	      but_sw;
+
+	assign JOY0 = joystick0;
+	assign JOY1 = joystick1;
+	assign KEYBOARD = keyboard_out;
+	assign BUTTONS = but_sw[1:0];
+	assign SWITCHES = but_sw[3:2];
+   
+   always@(negedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+		   SPI_MISO <= 1'bZ;
+		end else begin
+	      if(cnt < 8) begin
+			  SPI_MISO <= CORE_TYPE[7-cnt];
+			end else begin
+		     SPI_MISO <= 1'bZ;
+			end
+	   end
+	end
+		
+   always@(posedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+        cnt <= 0;
+		end else begin
+			sbuf[6:1] <= sbuf[5:0];
+			sbuf[0] <= SPI_MOSI;
+
+			cnt <= cnt + 1;
+
+	      if(cnt == 7) begin
+			   cmd[7:1] <= sbuf; 
+				cmd[0] <= SPI_MOSI;
+		   end	
+
+	      if(cnt == 15) begin
+			   if(cmd == 1) begin
+					 but_sw[3:1] <= sbuf[2:0]; 
+					 but_sw[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 2) begin
+					 joystick0[5:1] <= sbuf[4:0]; 
+					 joystick0[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 3) begin
+					 joystick1[5:1] <= sbuf[4:0]; 
+					 joystick1[0] <= SPI_MOSI; 
+				end			
+			end	
+			
+			// 15,23,31,39,47,55,63,71
+			if (cnt[2:0]==7) begin
+			   if(cmd == 5) begin
+					if (!cnt[7]) begin
+					 keyboard[111:0] <= keyboard[119:8];
+					 keyboard[119:113] <= sbuf[6:0]; 
+					 keyboard[112] <= SPI_MOSI; 
+					end
+					if (cnt[7]) begin
+					 keyboard_out[119:0] <= keyboard[119:0];
+					 keyboard_out[127:121] <= sbuf[6:0]; 
+					 keyboard_out[120] <= SPI_MOSI; 					
+					end
+				end
+			end
+		end
+   end		
+//   always@(posedge clk2) begin
+//      LED <= ~LED;
+//   end
+   
+endmodule
Index: replay/Replay.cmd
===================================================================
--- replay/Replay.cmd	(nonexistent)
+++ replay/Replay.cmd	(revision 1)
@@ -0,0 +1,6 @@
+#onerror {resume}
+# GAME
+#=====================
+#run 18871970 ns
+#isim force add {/replay_tb/uut/tpp2/cpu/dd_s} 11111111 -radix bin -cancel 250 ns 
+#run 200 ms
Index: replay/Replay.ut
===================================================================
--- replay/Replay.ut	(nonexistent)
+++ replay/Replay.ut	(revision 1)
@@ -0,0 +1,8 @@
+-g DonePin:PULLUP
+-g TdoPin:PULLNONE
+-g M0Pin:PULLUP
+-g M1Pin:PULLUP
+-g M2Pin:PULLUP
+-g StartUpClk:CCLK
+-g DriveDone:Yes
+-g Binary:Yes
Index: mist/pll.cmp
===================================================================
--- mist/pll.cmp	(nonexistent)
+++ mist/pll.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: mist/sdram_statemachine.vhdl
===================================================================
--- mist/sdram_statemachine.vhdl	(nonexistent)
+++ mist/sdram_statemachine.vhdl	(revision 1)
@@ -0,0 +1,526 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- set true to request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	COMPLETE : out std_logic;
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CKE : out std_logic;
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine;
+
+ARCHITECTURE vhdl OF sdram_statemachine IS
+	function repeat(N: natural; B: std_logic) 
+	return std_logic_vector
+	is
+	variable result: std_logic_vector(1 to N);
+	begin
+	for i in 1 to N loop
+	result(i) := B;
+	end loop;
+	return result;
+	end;
+
+	-- bits are: CS_n, RAS_n, CAS_n,WE_n
+	constant sdram_command_inhibit                  : std_logic_vector(3 downto 0) := "1000";
+	constant sdram_command_no_operation             : std_logic_vector(3 downto 0) := "0111";
+	constant sdram_command_device_burst_stop        : std_logic_vector(3 downto 0) := "0110";
+	constant sdram_command_read                     : std_logic_vector(3 downto 0) := "0101";
+	constant sdram_command_write                    : std_logic_vector(3 downto 0) := "0100";
+	constant sdram_command_bank_activate            : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
+	constant sdram_command_precharge                : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
+	constant sdram_command_mode_register            : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
+	constant sdram_command_refresh                  : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
+	
+	signal command_next : std_logic_vector(3 downto 0);
+	
+--	constant bank_state_idle                 : std_logic_vector(3 downto 0) := "0000";
+--	constant bank_state_row_active           : std_logic_vector(3 downto 0) := "0001";
+--	constant bank_state_read                 : std_logic_vector(3 downto 0) := "0010";
+--	constant bank_state_write                : std_logic_vector(3 downto 0) := "0011";
+--	constant bank_state_read_pre             : std_logic_vector(3 downto 0) := "0100";
+--	constant bank_state_write_pre            : std_logic_vector(3 downto 0) := "0101";
+--	constant bank_state_precharging          : std_logic_vector(3 downto 0) := "0111";
+--	constant bank_state_row_activating       : std_logic_vector(3 downto 0) := "1000";
+--	constant bank_state_write_recovering     : std_logic_vector(3 downto 0) := "1001";
+--	constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
+--	constant bank_state_refresh              : std_logic_vector(3 downto 0) := "1011";
+--	constant bank_state_mode_access          : std_logic_vector(3 downto 0) := "1100"; 
+--	constant bank_state_init                 : std_logic_vector(3 downto 0) := "1101"; 
+-- Banks each have their own state, but since read/write lines are shared they are not truly independent
+-- Also for auto-refresh all banks must be in idle state
+
+	constant sdram_state_powerup        : std_logic_vector(2 downto 0) := "000"; -- requires standard init
+	constant sdram_state_init           : std_logic_vector(2 downto 0) := "001"; -- requires standard init
+	constant sdram_state_idle           : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
+	constant sdram_state_refresh        : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
+	constant sdram_state_read           : std_logic_vector(2 downto 0) := "100"; -- processing a read request
+	constant sdram_state_write          : std_logic_vector(2 downto 0) := "101"; -- processing a write request
+	constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
+	
+	signal sdram_state_next : std_logic_vector(2 downto 0);
+	signal sdram_state_reg : std_logic_vector(2 downto 0);
+	
+	signal delay_next : std_logic_vector(13 downto 0);
+	signal delay_reg : std_logic_vector(13 downto 0);
+	
+	signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
+	signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
+	
+	signal refresh_pending_next : std_logic_vector(11 downto 0);
+	signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
+	
+	signal suggest_refresh : std_logic; -- i.e. do we have any pending?
+	signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
+	signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time	
+	signal refreshing_now : std_logic;
+	
+	signal idle_priority : std_logic_vector(3 downto 0);
+
+	signal data_out_next : std_logic_vector(31 downto 0);
+	signal data_out_reg : std_logic_vector(31 downto 0);
+	
+	signal reply_next : std_logic;
+	signal reply_reg : std_logic;
+	
+	-- track the active bank
+	-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
+	-- CAS,NOP,NOP,DATA
+	-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
+	--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	
+	-- capture inputs
+	signal DATA_IN_snext      : std_logic_vector(31 downto 0);
+	signal DATA_IN_sreg       : std_logic_vector(31 downto 0);
+	signal ADDRESS_IN_snext   : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal ADDRESS_IN_sreg    : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal READ_EN_snext      : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal READ_EN_sreg       : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal WRITE_EN_snext     : std_logic;
+	signal WRITE_EN_sreg      : std_logic;	
+	signal dqm_mask_snext     : std_logic_vector(3 downto 0);
+	signal dqm_mask_sreg      : std_logic_vector(3 downto 0);
+	signal request_snext      : std_logic;
+	signal request_sreg       : std_logic;
+	signal refresh_snext      : std_logic;
+	signal refresh_sreg       : std_logic;
+	
+	-- slow clock output regs
+	signal DATA_OUT_snext     : std_logic_vector(31 downto 0);
+	signal DATA_OUT_sreg      : std_logic_vector(31 downto 0);
+	
+	signal reply_snext : std_logic;
+	signal reply_sreg  : std_logic;
+	
+	-- sdram output registers 
+	signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_next : std_logic_vector(15 downto 0);
+	signal dq_output_next : std_logic;
+	signal dq_in_next  : std_logic_vector(15 downto 0);	
+	signal ba_next : std_logic_vector(1 downto 0);
+	signal cs_n_next : std_logic;
+	signal ras_n_next : std_logic;
+	signal cas_n_next : std_logic;
+	signal we_n_next : std_logic;
+	signal ldqm_next : std_logic;
+	signal udqm_next : std_logic;
+	signal cke_next : std_logic;
+	
+	signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_reg : std_logic_vector(15 downto 0);
+	signal dq_output_reg : std_logic;
+	signal ba_reg : std_logic_vector(1 downto 0);
+	signal cs_n_reg : std_logic;
+	signal ras_n_reg : std_logic;
+	signal cas_n_reg : std_logic;
+	signal we_n_reg : std_logic;
+	signal ldqm_reg : std_logic;
+	signal udqm_reg : std_logic;
+	signal cke_reg : std_logic;
+	
+	signal sdram_request_reg : std_logic;
+	signal sdram_request_next : std_logic;
+	
+BEGIN
+	-- register
+	process(CLK_SDRAM,reset_n)
+	begin
+		if (reset_N = '0') then
+			sdram_state_reg <= sdram_state_init;
+			delay_reg <= (others=>'0');
+			refresh_pending_reg <= (others=>'0');
+			cycles_since_refresh_reg <= (others=>'0');
+			data_out_reg <= (others=>'0');
+			reply_reg <= '0';
+			
+			addr_reg <= (others => '0');
+			dq_out_reg <= (others=> '0');
+			dq_output_reg <= '0';
+			ba_reg <= (others=>'0');
+			cs_n_reg <= '0';
+			ras_n_reg <= '0';
+			cas_n_reg <= '0';
+			we_n_reg <= '0';
+			ldqm_reg <= '0';
+			udqm_reg <= '0';
+			cke_reg <= '0';
+			
+			--bank_row_reg <= (others=>(others=>'0'));
+		elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
+			sdram_state_reg <= sdram_state_next;
+			delay_reg <= delay_next;
+			refresh_pending_reg <= refresh_pending_next;
+			cycles_since_refresh_reg <= cycles_since_refresh_next;
+			data_out_reg <= data_out_next;
+			reply_reg <= reply_next;
+			
+			addr_reg <= addr_next;
+			dq_out_reg <= dq_out_next;
+			dq_output_reg <= dq_output_next;
+			ba_reg <= ba_next;
+			cs_n_reg <= cs_n_next;
+			ras_n_reg <= ras_n_next;
+			cas_n_reg <= cas_n_next;
+			we_n_reg <= we_n_next;
+			ldqm_reg <=ldqm_next;
+			udqm_reg <= udqm_next;
+			cke_reg <= cke_next;
+			
+			--bank_row_reg <= bank_row_next;
+		end if;
+	end process;
+
+	-- register request	
+	process(CLK_SYSTEM,reset_n)
+	begin
+		if (reset_N = '0') then
+			data_in_sreg <= (others=>'0');
+			address_in_sreg <= (others=>'0');
+			read_en_sreg <= '0';
+			write_en_sreg <= '0';
+			request_sreg <= '0';
+			dqm_mask_sreg <= (others=>'1');
+			refresh_sreg <= '0';
+			
+			data_out_sreg <= (others=>'0');
+			reply_sreg <= '0';
+			
+			sdram_request_reg <= '0';
+		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+			data_in_sreg <= data_in_snext;
+			address_in_sreg <= address_in_snext;
+			read_en_sreg <= read_en_snext;
+			write_en_sreg <= write_en_snext;
+			request_sreg <= request_snext;
+			dqm_mask_sreg <= dqm_mask_snext;
+			refresh_sreg <= refresh_snext;
+			
+			data_out_sreg <= data_out_snext;
+			reply_sreg <= reply_snext;
+			
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+
+	-- Inputs - NB, clocked at a smaller multiple
+	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, sdram_request_next, byte_access, word_access, longword_access, refresh)
+	begin
+		data_in_snext <= data_in_sreg;
+		address_in_snext <= address_in_sreg;
+		read_en_snext <= read_en_sreg;
+		write_en_snext <= write_en_sreg;
+		request_snext <= request_sreg;
+		dqm_mask_snext <= dqm_mask_sreg;
+		
+		refresh_snext <= refresh; -- independent of memory requests
+	
+		-- only snap inputs on new request
+		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+		if ((sdram_request_next xor request_sreg) = '1') then
+			data_in_snext <= data_in;
+			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+			read_en_snext <= read_en;
+			write_en_snext <= write_en;
+			request_snext <= sdram_request_next;
+			
+			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+			dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
+			dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
+		end if;
+	end process;
+	
+	-- refresh counters
+	process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
+	begin
+		cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
+		refresh_pending_next <= refresh_pending_reg;
+		suggest_refresh <= '0';
+		force_refresh <= '0';
+		
+		if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
+			suggest_refresh <= '1';
+		end if;
+		
+		if (refresh_pending_reg = X"FFF") then
+			force_refresh <= '1';
+		end if;
+		
+		require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
+		
+		if (refreshing_now = '1') then
+			-- refreshing right now
+			cycles_since_refresh_next <= (others=>'0');
+			
+			-- This is one of our pending refreshes (if we have any)			
+			if (suggest_refresh = '1') then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
+			end if;
+		else
+			if (cycles_since_refresh_reg = "11111111111") then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
+				cycles_since_refresh_next <= (others=>'0');
+			end if;
+		end if;
+
+	end process;
+	
+	--
+	process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
+	begin
+		idle_priority <= (others=>'0');
+		refreshing_now <= '0';
+	
+		sdram_state_next <= sdram_state_reg;
+		
+		command_next <= sdram_command_no_operation;
+		
+		delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
+		
+		data_out_next <= data_out_reg;
+		reply_next <= reply_reg;
+		
+		-- Set some default for when we're sending NOP
+		dq_out_next <= (others=>'0');
+		dq_output_next <= '0';
+		cke_next <= '1';
+		ldqm_next <= '1';
+		udqm_next <= '1';
+		ba_next <= (others=>'0');
+		addr_next <= (others=>'1');
+
+		-- TODO - use bank states!!
+		-- TODO - MUCH MORE SMART STUFF!
+		-- Lets do them once we have Hello World running...
+		case sdram_state_reg is
+		when sdram_state_powerup =>			
+			-- wait 100us (min)
+			if (delay_reg(13) = '1') then
+				sdram_state_next <= sdram_state_init_precharge;
+				delay_next <= (others=>'0');
+			end if;			
+		when sdram_state_init =>			
+			case delay_reg(5 downto 3)&delay_reg(0) is
+			when "0001" =>
+				command_next <= sdram_command_precharge;
+				addr_next(AP_BIT) <= '1'; --all banks
+			when "0010" =>
+				command_next <= sdram_command_refresh;				
+				-- cke still high, so auto refresh
+			when "0100" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+			when "1000" =>
+				command_next <= sdram_command_mode_register;
+				--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
+				addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
+				addr_next(3) <= '0'; -- sequential
+				addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
+				addr_next(8 downto 7) <= "00"; -- standard operation
+				addr_next(9) <= '0'; -- programmed burst access - of single cycle!
+				addr_next(11 downto 10) <= "00"; -- reserved
+			when "1010" =>
+				sdram_state_next <= sdram_state_idle;
+				delay_next <= (others=>'0');
+			when others =>
+				-- nop
+			end case;
+		when sdram_state_idle =>
+			delay_next <= (others=>'0');						
+			
+			idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
+			case idle_priority is -- priority encoder...
+			when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
+				sdram_state_next <= sdram_state_refresh;
+			when "1010"|"1011" =>				
+				sdram_state_next <= sdram_state_write;
+			when "1001" =>
+				sdram_state_next <= sdram_state_read;
+			when others =>
+				-- stay here
+			end case;
+		when sdram_state_read =>
+			-- TODO - if same bank we can save some time... ?
+			-- Only do precharge on switching bank?
+				
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_read;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+			when X"4" =>  -- command actually sent now
+				ldqm_next <= dqm_mask_sreg(0);  -- for first read
+				udqm_next <= dqm_mask_sreg(1);
+			
+			when X"5" =>  -- dqm for 1st read is sent
+				ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
+				udqm_next <= dqm_mask_sreg(3);				
+			when X"7" => 
+				data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				data_out_next(15 downto 8) <= dq_in_next(15 downto 8);				
+			when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
+				data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
+				data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
+				
+				reply_next <= request_sreg;
+				sdram_state_next <= sdram_state_idle;
+				-- after 3 cycles we can do the next ACT (21 ns psc)
+				-- TODO - directly switch to next action so as not to waste a cycle
+			when others =>
+			end case;				
+		when sdram_state_write =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_write; 
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
+				dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
+				ldqm_next <= dqm_mask_sreg(0);
+				udqm_next <= dqm_mask_sreg(1);
+			when X"4" =>
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
+				ldqm_next <= dqm_mask_sreg(2);
+				udqm_next <= dqm_mask_sreg(3);
+
+				reply_next <= request_sreg;				
+			when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
+				sdram_state_next <= sdram_state_idle;		
+				-- TODO - directly switch to next action to match read
+			when others =>
+			end case;				
+		when sdram_state_refresh =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+				refreshing_now <= '1';
+			when X"8" =>
+				sdram_state_next <= sdram_state_idle;
+			when others =>
+			end case;
+		when others =>
+			sdram_state_next <= sdram_state_init;			
+		end case;
+	end process;
+	
+	-- command_next directly translates to lines to send
+	-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
+	process(command_next)
+	begin
+		cs_n_next <= command_next(3);
+		ras_n_next <= command_next(2);
+		cas_n_next <= command_next(1);
+		we_n_next <= command_next(0);
+	end process;
+	
+	-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
+	SDRAM_ADDR <= addr_reg;
+	SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
+	SDRAM_BA0 <= ba_reg(0);
+	SDRAM_BA1 <= ba_reg(1);
+	SDRAM_CS_N <= cs_n_reg;
+	SDRAM_RAS_N <= ras_n_reg;
+	SDRAM_CAS_N <= cas_n_reg;
+	SDRAM_WE_N <= we_n_reg;
+	SDRAM_ldqm <= ldqm_reg;
+	SDRAM_udqm <= udqm_reg;
+	SDRAM_CKE <= cke_reg;
+	
+	-- inputs from SDRAM
+	dq_in_next <= SDRAM_DQ;
+	
+	-- back to slower clock
+	reply_snext <= reply_reg;
+	data_out_snext <= data_out_reg;
+	
+	-- outputs to rest of system
+	--REPLY <= reply_sreg;
+	DATA_OUT <= DATA_OUT_sreg;
+
+	-- a little sdram glue - move to sdram wrapper?
+	COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
+	sdram_request_next <= sdram_request_reg xor request;
+	
+END vhdl;
Index: replay/COPYRIGHT_NOTICE
===================================================================
--- replay/COPYRIGHT_NOTICE	(nonexistent)
+++ replay/COPYRIGHT_NOTICE	(revision 1)
@@ -0,0 +1,131 @@
+(c) 2013 Mark Watson
+I am happy for anyone to use these for non-commercial use.
+If my vhdl files are used commercially or sold please contact me for explicit permission at scrameta@gmail.com.
+This applies for source and binary form and derived works.
+
+pokey.vhdl
+pokey_noise_filter.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_ps2_decoder.vhdl
+pokey_mixer.vhdl
+poly_4.vhdl
+poly_5.vhdl
+poly_17_9.vhdl
+
+covox.vhdl
+
+gtia.vhdl
+gtia_priority.vhdl
+gtia_palette.vhdl // Palette data itself from laoo and Altirra
+gtia_player.vhdl
+
+antic.vhdl
+antic_dma_clock.vhdl
+antic_counter.vhdl
+
+pia.vhdl
+
+cpu.vhd
+shared_enable.vhdl
+irq_glue.vhdl
+
+ps2_keyboard.vhdl
+
+scandoubler.vhdl
+scandouble_ram_infer.vhdl
+
+zpu_glue.vhdl
+zpu_config_regs.vhdl
+
+// utils
+synchronizer.vhdl
+delay_line.vhdl
+wide_delay_line.vhdl
+reg_file.vhdl
+enable_divider.vhdl
+syncreset_enable_divider.vhd
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+simple_counter.vhdl
+
+// semi de1 specific
+sram.vhdl
+flashrom.vhdl
+sdram_statemachine.vhdl
+address_decoder.vhdl
+
+// de1 specific
+atari800core.vhd // top level for DE1
+i2sslave.vhdl
+hexdecoder.vhd
+gpio.vhd
+ledsw.vhd
+
+// altera megafunctions
+pll.vhd 
+zpu_ram.vhd
+zpu_rom.vhd
+
+-----------------------------------------------------------------------------------
+(c) Mike Stirling (from Spectrum core)
+See header for Mike's copyright note
+Parameters modified for my use case
+
+i2c_loader.vhd
+i2s_intf.vhd
+
+-----------------------------------------------------------------------------------
+(c) Peter Wendrich
+Please contact Peter if you wish to use them. I have permission for use as part of the Atari800 core.
+
+cpu_6510.vhd
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+
+-----------------------------------------------------------------------------------
+---- Copyright (c) 2008 Ãvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+ZPU implementation. See headers for more details
+I made a few fixes to make it work for my use case.
+
+zpu_core.vhd
+zpupkg.vhd
+
+-----------------------------------------------------------------------------------
+(c) Scott Larson
+See file header
+
+spi_master.vhd
+
+-----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+zpu/*.[ch]
+SD card/OSD
+-----------------------------------------------------------------------------------
+(c) Mark Watson
+Also some portions taken from SDrive, so (c) Bob and Raster
+
+I am happy for these to be used freely for commercial and non-commercial use.
+
+debug.h  led.h   pause.h  regs.h  types.h  uart.h
+bootdump.c  debug.c  led.c  main.c  regs.c  test.c  uart.c
+
+zpuromgen.c
+
+----------------------------------------------------------------------------------
+(c) Pascal Stang + Bob and Raster
+spi.c
+spi.h
+mmc.c  
+mmc.h
+mmcconf.h 
+
+-----------------------------------------------------------------------------------
+(c) ChaN
+Petit File System
+
+integer.h  
+diskio.h  
+pff.h
+pff.c  
Index: replay/Replay.ucf
===================================================================
--- replay/Replay.ucf	(nonexistent)
+++ replay/Replay.ucf	(revision 1)
@@ -0,0 +1,365 @@
+# WWW.FPGAArcade.COM
+# REPLAY 1.0
+# Retro Gaming Platform
+# No Emulation No Compromise
+#
+# $Id: Replay.ucf 36 2013-09-08 17:32:44Z wolfgang.scherr $
+#
+# All rights reserved
+# Mike Johnson 2010
+CONFIG PART = XC3S1600E-FG320-4 ;
+
+NET ClK_A       TNM_NET = clk_a_grp;
+NET ClK_B       TNM_NET = clk_b_grp;
+NET ClK_C       TNM_NET = clk_c_grp;
+
+TIMESPEC TS03 = PERIOD : clk_a_grp :  9.39 ; # 106,47 MHz
+TIMESPEC TS02 = PERIOD : clk_b_grp : 20.13 ; # 49,66 MHz
+TIMESPEC TS01 = PERIOD : clk_c_grp : 36.98 ; # 27,04 MHz
+
+TIMESPEC TS11 = FROM:PADS:TO:FFS : 30 ns;
+TIMESPEC TS12 = FROM:FFS:TO:PADS : 30 ns;
+
+INST "u_ClockGen/u_a_dcm" LOC = "DCM_X2Y0";
+INST "u_ClockGen/phase_ctrl.u_a2_dcm" LOC = "DCM_X1Y0";
+INST "u_ClockGen/u_b_dcm" LOC = "DCM_X2Y3";
+INST "u_ClockGen/u_c_dcm" LOC = "DCM_X1Y3";
+
+#clock phase delay not important, between the two A dcms it does matter - force local routing
+# better result than one direct and one not
+NET "ClK_A" CLOCK_DEDICATED_ROUTE = FALSE;
+##PIN "u_ClockGen/u_a_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+PIN "u_ClockGen/phase_ctrl.u_a2_dcm" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "u_ClockGen/clk_a_ibuf" MAXSKEW = 0.3 ns;
+
+INST "u_ClockGen/u_dcm_a_clk_div_bufg" LOC = "BUFGMUX_X1Y1";
+INST "u_ClockGen/u_dcm_a_clk_0_bufg"   LOC = "BUFGMUX_X2Y1";
+INST "u_ClockGen/u_dcm_a_clk_90_bufg"  LOC = "BUFGMUX_X1Y0";
+INST "u_ClockGen/phase_ctrl.u_dcm_a2_clk_bufg"  LOC = "BUFGMUX_X2Y0";
+
+# C is routed to reset generator, phase not important
+NET "ClK_C" CLOCK_DEDICATED_ROUTE = FALSE;
+##PIN "u_ClockGen/u_c_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE;
+
+INST "u_ClockGen/u_dcm_c_clk_0_bufg"   LOC = "BUFGMUX_X2Y10";
+INST "u_ClockGen/u_dcm_c_clk_90_bufg"  LOC = "BUFGMUX_X2Y11";
+INST "u_spi_bufg"                      LOC = "BUFGMUX_X1Y11";
+
+# 30MHz SPI clock MAX
+NET "i_FPGA_SPI_Clk" TNM_NET = i_FPGA_SPI_Clk;
+TIMESPEC TS_i_FPGA_SPI_Clk = PERIOD "i_FPGA_SPI_Clk" 30 ns HIGH 50%;
+
+# domain crossing
+NET Clk_Ram     TNM_NET = clk_ram_grp;
+NET Clk_Capture TNM_NET = clk_capture_grp;
+NET Clk_Ctl     TNM_NET = clk_ctl_grp;
+
+TIMESPEC TS_20 = FROM "clk_ctl_grp" TO "clk_capture_grp" TIG;
+TIMESPEC TS_21 = FROM "clk_ram_grp" TO "clk_capture_grp" TIG;
+TIMESPEC TS_22 = FROM "clk_capture_grp" TO "clk_ram_grp" TIG;
+
+# area constraints
+INST "u_Syscon/u_spi" AREA_GROUP = "AG_u_Syscon/u_spi" ;
+AREA_GROUP "AG_u_Syscon/u_spi" RANGE = SLICE_X32Y149:SLICE_X41Y140 ;
+
+INST "u_FileIO/u_spi" AREA_GROUP = "AG_u_FileIO/u_spi" ;
+AREA_GROUP "AG_u_FileIO/u_spi" RANGE = SLICE_X42Y149:SLICE_X49Y140 ;
+
+INST "u_DDRCtrl/u_ddr_ctrl/u_datapath" AREA_GROUP = "AG_u_DDRCtrl/u_ddr_ctrl/u_datapath" ;
+AREA_GROUP "AG_u_DDRCtrl/u_ddr_ctrl/u_datapath" RANGE = SLICE_X112Y0:SLICE_X115Y151 ;
+
+INST "u_ClockGen/u_reset" AREA_GROUP = "AG_u_ClockGen/u_reset" ;
+AREA_GROUP "AG_u_ClockGen/u_reset" RANGE = SLICE_X50Y143:SLICE_X55Y138 ;
+
+
+#
+# 3V3
+#
+NET "i_RS232_RXD"               LOC = "A3"  | IOSTANDARD = LVTTL;
+NET "b_Aux_IO(37)"              LOC = "C3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_RS232_RTS"               LOC = "A4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(0)"               LOC = "B4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(2)"               LOC = "C4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_RS232_CTS"               LOC = "A5"  | IOSTANDARD = LVTTL;
+NET "i_Joy_A(5)"                LOC = "B5"  | IOSTANDARD = LVTTL | PULLUP;
+NET "o_RS232_TXD"               LOC = "C5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_Aux_IO(4)"               LOC = "C2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(5)"               LOC = "D5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(6)"               LOC = "D6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(7)"               LOC = "E6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(8)"               LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(9)"               LOC = "C7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(10)"              LOC = "D7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(11)"              LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(12)"              LOC = "E7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(13)"              LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(14)"              LOC = "D9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(15)"              LOC = "G9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_Aux_IO(26)"              LOC = "A6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(38)"              LOC = "B6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(29)"              LOC = "A7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_Aux_IO(3)"               LOC = "F7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(27)"              LOC = "A8"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Joy_B(0)"                LOC = "B8"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Joy_A(4)"                LOC = "C8"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Joy_A(1)"                LOC = "D8"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_FPGA_SPI_MOSI"           LOC = "E8"  | IOSTANDARD = LVTTL;
+NET "b_Aux_IO(20)"              LOC = "F8"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "i_Joy_A(2)"                LOC = "B9"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_FPGA_SPI_Clk"            LOC = "C9"  | IOSTANDARD = LVTTL;
+NET "b_Aux_IO(25)"              LOC = "E9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_FPGA_SPI_MISO"           LOC = "F9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_Aux_IO(32)"              LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "ClK_B"                     LOC = "B10" | IOSTANDARD = LVTTL;
+NET "ClK_C"                     LOC = "D10" | IOSTANDARD = LVTTL;
+NET "b_Aux_IO(17)"              LOC = "E10" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Joy_B(3)"                LOC = "F10" | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Joy_B(5)"                LOC = "G10" | IOSTANDARD = LVTTL | PULLUP;
+NET "b_Aux_IO(21)"              LOC = "B11" | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_Aux_IO(23)"              LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(22)"              LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(34)"              LOC = "E11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(36)"              LOC = "F11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(24)"              LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Joy_A(0)"                LOC = "C12" | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Joy_B(2)"                LOC = "D12" | IOSTANDARD = LVTTL | PULLUP;
+NET "b_Aux_IO(35)"              LOC = "E12" | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_Aux_IO(30)"              LOC = "F12" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(28)"              LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(31)"              LOC = "D13" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_PS2A_Data"               LOC = "E13" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(16)"              LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(33)"              LOC = "C14" | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_PS2A_Clk"                LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Joy_A(3)"                LOC = "A15" | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Joy_B(1)"                LOC = "B15" | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Joy_B(4)"                LOC = "C15" | IOSTANDARD = LVTTL | PULLUP;
+NET "b_Aux_IO(18)"              LOC = "A16" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(19)"              LOC = "B16" | IOSTANDARD = LVTTL | DRIVE = 8;
+
+#
+#   2V5
+#
+#NET ""                         LOC = "B18"; # NC INP
+NET "o_Mem_Addr(2)"             LOC = "C18" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(3)"             LOC = "C17" | IOSTANDARD = SSTL2_I;
+#NET ""                         LOC = "D18"; # VREF
+NET "o_Disk_Led"                LOC = "D17" | IOSTANDARD = LVCMOS25;
+NET "o_Pwr_Led"                 LOC = "D16" | IOSTANDARD = LVCMOS25;
+#NET ""                         LOC = "E18"; # NC INP
+#NET ""                         LOC = "E17"; # NC INP
+
+NET "b_2V5_IO_1"                LOC = "E16" | IOSTANDARD = LVCMOS25;
+NET "b_2V5_IO_0"                LOC = "E15" | IOSTANDARD = LVCMOS25;
+NET "o_Mem_Addr(1)"             LOC = "F18" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(4)"             LOC = "F17" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(0)"             LOC = "F15" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(5)"             LOC = "F14" | IOSTANDARD = SSTL2_I;
+#NET ""                         LOC = "G18"; # NC INP
+NET "o_Mem_Addr(10)"            LOC = "G16" | IOSTANDARD = SSTL2_I;
+
+NET "o_Mem_Addr(6)"             LOC = "G15" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(14)"            LOC = "G14" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(7)"             LOC = "G13" | IOSTANDARD = SSTL2_I;
+#NET ""                         LOC = "H18"; # VREF
+NET "o_Mem_Addr(13)"            LOC = "H17" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(8)"             LOC = "H16" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Addr(9)"             LOC = "H15" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_CS"                  LOC = "H14" | IOSTANDARD = SSTL2_I; # ctrl4
+
+#NET ""                         LOC = "H13"; # NC INP
+NET "o_Mem_Addr(11)"            LOC = "J17" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_RAS"                 LOC = "J16" | IOSTANDARD = SSTL2_I; # ctrl3
+NET "o_Mem_Addr(12)"            LOC = "J15" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_CAS"                 LOC = "J14" | IOSTANDARD = SSTL2_I; # ctrl2
+NET "o_Mem_CKE"                 LOC = "J13" | IOSTANDARD = SSTL2_I; # ctrl0
+NET "o_Mem_WE"                  LOC = "J12" | IOSTANDARD = SSTL2_I; # ctrl1
+
+#NET ""                         LOC = "K18"; # NC INP
+#NET ""                         LOC = "K17"; # NC INP
+NET "o_Mem_Clk_P"               LOC = "K15" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_Clk_N"               LOC = "K14" | IOSTANDARD = SSTL2_I;
+NET "o_Mem_UDM"                 LOC = "K13" | IOSTANDARD = SSTL2_I; # ctrl6
+NET "o_Mem_LDM"                 LOC = "K12" | IOSTANDARD = SSTL2_I; # ctrl5
+NET "b_Mem_UDQS"                LOC = "L18" | IOSTANDARD = SSTL2_I; # ctrl8
+#NET ""                         LOC = "L17"; # VREF
+
+NET "b_Mem_DQ(8)"               LOC = "L16" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(10)"              LOC = "L15" | IOSTANDARD = SSTL2_I;
+#NET ""                         LOC = "L14"; # NC INP
+#NET ""                         LOC = "L13"; # NC INP
+NET "b_Mem_DQ(7)"               LOC = "M18" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(9)"               LOC = "M16" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(6)"               LOC = "M15" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_LDQS"                LOC = "M14" | IOSTANDARD = SSTL2_I; # ctrl7
+
+#NET ""                         LOC = "M13" # VREF
+NET "b_Mem_DQ(5)"               LOC = "N18" | IOSTANDARD = SSTL2_I;
+#NET ""                         LOC = "N17"; # NC INP
+NET "b_Mem_DQ(4)"               LOC = "N15" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(11)"              LOC = "N14" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(3)"               LOC = "P18" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(12)"              LOC = "P17" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(13)"              LOC = "P16" | IOSTANDARD = SSTL2_I;
+
+NET "i_Ext_Rst_L"               LOC = "P15" | IOSTANDARD = LVCMOS25 | PULLUP;
+NET "b_Mem_DQ(2)"               LOC = "R18" | IOSTANDARD = SSTL2_I;
+#NET ""                         LOC = "R17"; # NC INP
+#NET ""                         LOC = "R16"; # VREF
+NET "b_Mem_DQ(14)"              LOC = "R15" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(1)"               LOC = "T18" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(0)"               LOC = "T17" | IOSTANDARD = SSTL2_I;
+NET "b_Mem_DQ(15)"              LOC = "U18" | IOSTANDARD = SSTL2_I;
+#
+# 3V3
+#
+NET "i_Video_Int"               LOC = "V16" | IOSTANDARD = LVTTL; #video15
+NET "o_Audio_LRCIN"             LOC = "T16" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Audio_MCLK"              LOC = "V15" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Audio_BCKIN"             LOC = "U15" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Audio_DIN"               LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_FPGA_Ctrl1"              LOC = "V14" | IOSTANDARD = LVTTL;
+NET "i_FPGA_Ctrl0"              LOC = "U14" | IOSTANDARD = LVTTL;
+NET "b_PS2B_Data"               LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_PS2B_Clk"                LOC = "R14" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(7)"           LOC = "V13" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(0)"           LOC = "U13" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Rst_L"             LOC = "R13" | IOSTANDARD = LVTTL | DRIVE = 8; # video16
+NET "o_Video_DE"                LOC = "P13" | IOSTANDARD = LVTTL | DRIVE = 8; # video14
+NET "o_Video_Data(2)"           LOC = "V12" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(1)"           LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_V"                 LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 8; #video13
+
+NET "o_Video_H"                 LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8; #video12
+NET "o_Video_Data(4)"           LOC = "N12" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(0)"               LOC = "U11" | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Aux_IP(6)"               LOC = "T11" | IOSTANDARD = LVTTL | PULLUP;
+NET "o_Video_Data(5)"           LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(3)"           LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(8)"           LOC = "N11" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "ClK_A"                     LOC = "U10" | IOSTANDARD = LVTTL;
+
+NET "b_SCL"                     LOC = "R10" | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_SDA"                     LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "o_Video_Clk_N"             LOC = "V9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Clk_P"             LOC = "U9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(9)"           LOC = "R9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(6)"           LOC = "P9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Clk_Aux"                 LOC = "N9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Clk_68K"                 LOC = "M9"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(2)"               LOC = "V8"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Aux_IP(1)"               LOC = "U8"  | IOSTANDARD = LVTTL | PULLUP;
+
+NET "o_Video_Data(10)"          LOC = "T8"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_Data(11)"          LOC = "R8"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_HSync"             LOC = "P8"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "o_Video_VSync"             LOC = "N8"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Video_DDC_Clk"           LOC = "V7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(4)"               LOC = "T7"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Aux_IP(3)"               LOC = "R7"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_Video_DDC_Data"          LOC = "P7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(15)"                  LOC = "N7"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Video_SPC"               LOC = "V6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(0)"                   LOC = "U6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(1)"                   LOC = "R6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(2)"                   LOC = "P6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(3)"                   LOC = "V5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(4)"                   LOC = "U5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(5)"                   LOC = "T5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(6)"                   LOC = "R5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(5)"               LOC = "V4"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(7)"                   LOC = "T4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(7)"               LOC = "V3"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(8)"                   LOC = "U3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(8)"               LOC = "V2"  | IOSTANDARD = LVTTL | PULLUP;
+#
+# 3V3
+#
+NET "i_Aux_IP(9)"               LOC = "U1"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(9)"                   LOC = "T1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(10)"                  LOC = "T2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(10)"              LOC = "R1"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(11)"                  LOC = "R2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(12)"                  LOC = "R3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(11)"              LOC = "R4"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(13)"                  LOC = "P1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(14)"                  LOC = "P2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Video_SPD"               LOC = "P3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(43)"                  LOC = "P4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(12)"              LOC = "N1"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Aux_IP(13)"              LOC = "N2"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(42)"                  LOC = "N4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(41)"                  LOC = "N5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(14)"              LOC = "M1"  | IOSTANDARD = LVTTL | PULLUP;
+
+NET "b_IO(40)"                  LOC = "M3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(27)"                  LOC = "M4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(26)"                  LOC = "M5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(25)"                  LOC = "M6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(24)"                  LOC = "L1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(23)"                  LOC = "L2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(22)"                  LOC = "L3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(21)"                  LOC = "L4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(20)"                  LOC = "L5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(19)"                  LOC = "L6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(15)"              LOC = "K2"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(18)"                  LOC = "K3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(17)"                  LOC = "K4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(16)"                  LOC = "K5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(44)"                  LOC = "K6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(16)"              LOC = "K7"  | IOSTANDARD = LVTTL | PULLUP;
+
+NET "b_IO(45)"                  LOC = "J1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(46)"                  LOC = "J2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(47)"                  LOC = "J4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(48)"                  LOC = "J5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(17)"              LOC = "J6"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Aux_IP(18)"              LOC = "J7"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(49)"                  LOC = "H1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(50)"                  LOC = "H2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(51)"                  LOC = "H3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(52)"                  LOC = "H4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(53)"                  LOC = "H5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(54)"                  LOC = "H6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(19)"              LOC = "G1"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(39)"                  LOC = "G3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(38)"                  LOC = "G4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(37)"                  LOC = "G5"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(36)"                  LOC = "G6"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(35)"                  LOC = "F1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(34)"                  LOC = "F2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(20)"              LOC = "F4"  | IOSTANDARD = LVTTL | PULLUP;
+NET "i_Aux_IP(21)"              LOC = "F5"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_IO(33)"                  LOC = "E1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(32)"                  LOC = "E2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(31)"                  LOC = "E3"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+NET "b_IO(30)"                  LOC = "E4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(29)"                  LOC = "D1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_IO(28)"                  LOC = "D2"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "i_Aux_IP(22)"              LOC = "D3"  | IOSTANDARD = LVTTL | PULLUP;
+NET "b_Aux_IO(1)"               LOC = "D4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+NET "b_Aux_IO(39)"              LOC = "C1"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+#NET "i_SSC_TF"                  LOC = "T3"  | IOSTANDARD = LVTTL;
+#NET "i_SSC_TD"                  LOC = "N10" | IOSTANDARD = LVTTL;
+#NET "i_SSC_RK"                  LOC = "U16" | IOSTANDARD = LVTTL;
+NET "o_SSC_RD"                  LOC = "U4"  | IOSTANDARD = LVTTL | DRIVE = 8;
+
+
Index: replay/build.sh
===================================================================
--- replay/build.sh	(nonexistent)
+++ replay/build.sh	(revision 1)
@@ -0,0 +1,75 @@
+#!/bin/bash
+
+name=Replay
+args=$@
+shift
+
+embed_roms=0
+
+
+. /home/markw/altera/xilinx/ise/14.7/ISE_DS/settings32.sh
+
+if [ $embed_roms = 1 ]; then
+    pushd sdcard
+    cat lb1.cpu lb2.cpu lb3.cpu lb4.cpu lb5.cpu lb6.cpu lb10.vid lb9.vid lb7.cpu lb8.cpu > ../rom_stripe.bin
+    cat 10-1.vid >> ../rom_stripe.bin
+    dd if=/dev/zero bs=2016 count=1 >> ../rom_stripe.bin
+    cat 10-3.vid >> ../rom_stripe.bin
+    dd if=/dev/zero bs=2016 count=1 >> ../rom_stripe.bin
+    cat 10-2.vid >> ../rom_stripe.bin
+    dd if=/dev/zero bs=2016 count=1 >> ../rom_stripe.bin
+    popd
+fi
+
+mkdir -p build
+pushd build
+
+cp -p ../../replay_lib/rtl/*.vhd .
+cp -p ../source/*.v* .
+
+cp -p ../$name.ucf .
+cp -p ../$name.ut .
+cp -p ../$name.scr .
+cp -p ../$name.prj .
+if [ $embed_roms = 1 ]; then
+    cp -p ../roms.bmm .
+fi
+
+
+if [ "${args[0]}" != "-xil" ]; then
+
+    echo "Starting Synthesis..."
+    xst -ifn $name.scr -ofn $name.srp || exit 1
+
+fi
+
+echo "Starting Translate..."
+if [ $embed_roms = 1 ]; then
+    ngdbuild -nt on -uc $name.ucf -bm roms.bmm $name.ngc $name.ngd || exit 1
+else
+    ngdbuild -nt on -uc $name.ucf $name.ngc $name.ngd || exit 1
+fi
+
+echo "Starting Map..."
+map -pr b $name.ngd -o $name.ncd $name.pcf || exit 1
+
+echo "Starting Place & Route..."
+par -w -ol std $name.ncd $name.ncd $name.pcf || exit 1
+
+echo "Starting Timing Analysis..."
+trce -v 10 -o $name.twr $name.ncd $name.pcf || exit 1
+
+echo "Starting Bitgen..."
+bitgen $name.ncd $name.bit -w -f $name.ut || exit 1
+
+if [ $embed_roms = 1 ]; then
+    echo "Annotating ROM contents to bit file..."
+    data2mem -bm roms_bd.bmm -bt $name.bit -bd ../rom_stripe.bin -o b loader.bit || exit 1
+    promgen -u 0 loader.bit -p bin -w -b -o atari800.bin || exit 1
+
+    popd
+    cp build/atari800.bin sdcard/atari800.bin
+else
+    popd
+    cp build/$name.bin sdcard/atari800.bin
+fi

Property changes on: replay/build.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: replay/sdcard/osaorig.rom
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/osaorig.rom
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: mist/pll.vhd
===================================================================
--- mist/pll.vhd	(nonexistent)
+++ mist/pll.vhd	(revision 1)
@@ -0,0 +1,424 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 16,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 69,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 32,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 69,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 16,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 69,
+		clk2_phase_shift => "-1600",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.60000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1600"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: replay/CHANGELOG
===================================================================
--- replay/CHANGELOG	(nonexistent)
+++ replay/CHANGELOG	(revision 1)
@@ -0,0 +1,20 @@
+Version 1
+---------
+Initial source release
+
+Version 2
+---------
+Initial release that runs on Replay
+Disks can be loaded via SIO2PC (P1 jumper to FPGA, serial cable to PC, run aspeqt)
+No internal floppy emulation in this release (i.e. no loading from SD card)
+Running pretty well, but a few small things to fix - such as it seems to be impossible to press option in time to boot!
+A lot of the DE1 code has been stripped from this version, but there is still considerable cruft...
+For now memory config is fixed and ROM is built in.
+
+Version 3
+---------
+Memory and rom selectable from replay menu
+Improvements to video out
+PAL/NTSC bits fixed
+
+
Index: replay/Replay.scr
===================================================================
--- replay/Replay.scr	(nonexistent)
+++ replay/Replay.scr	(revision 1)
@@ -0,0 +1,10 @@
+run
+-ifn Replay.prj
+-ifmt VHDL
+-ofn Replay.ngc
+-ofmt NGC
+-p XC3S1600E-FG320-4
+-opt_mode Area
+-opt_level 1
+-keep_hierarchy yes
+-top Replay_Top
Index: replay/Replay_tb.prj
===================================================================
--- replay/Replay_tb.prj	(nonexistent)
+++ replay/Replay_tb.prj	(revision 1)
@@ -0,0 +1,6 @@
+
+verilog work ddr.v
+vhdl work Replay_I2C_CH7301.vhd
+vhdl work Replay_tb.vhd
+
+nosort
Index: replay/sdcard/ataribas.rom
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/ataribas.rom
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: replay/sdcard/replay.ini
===================================================================
--- replay/sdcard/replay.ini	(nonexistent)
+++ replay/sdcard/replay.ini	(revision 1)
@@ -0,0 +1,393 @@
+# Replay INI file
+
+# PRE PROCESSING PART
+#####################
+[SETUP]
+
+#      "123456789012345678901234567890"
+info = "Replay (c) 2013 MikeJ"
+info = "http://www.fpgaarcade.com/"
+info = "A8 core (c) 2014 Mark Watson"
+info = "-Joystick1 in upper port----"
+info = "-Joystick2 in lower port----"
+info = "-Keyboard in lower PS/2 in -"
+info = "-Start/Select/Option(F2-F4)-"
+
+bin = atari800.bin
+
+# sets initial clocking (PLL)
+#CLOCK = NTSC
+#
+# y0 - FPGA DRAM/sys clk
+# y1 - Coder
+# y2 - FPGA aux/audio clk
+# y3 - Expansion Main
+# y4 - FPGA video
+# y5 - Expansion Small
+# OUTPUT_y = (27 * Nx / Mx) / PDy     (if YSy=1, PSy selects PLL "x")
+#
+#         PLL1      PLL2      PLL3      1/2/4..PLL1/2/4 0..byp.    outp. divider          outp.enable
+#         M1   N1   M2   N2   M3   N3   ps0 ps1 ps2 ps3 ps4 ps5 pd0 pd1 pd2 pd3 pd4 pd5 ys0 ys1 ys2 ys3 ys4 ys5
+#SYSCLK=4436250Hz, Nsys=1183, Msys=300, Psys=1 ... VIDCLK=27035651Hz, Nvid=2275, Mvid=284, Pvid=8
+#CLOCK =   284,2275, 300,1183,  46, 423,  2,  4,  4,  0,  1,  0,  1, 14,  5,  1,  8,  1,  1,  1,  1,  0,  1,  0
+#SYSCLK=7116310Hz, Nsys=1729, Msys=205, Psys=2 ... VIDCLK=27010289HZ, Nvid=2625, Mvid=328, Pvid=8
+CLOCK =    328,2625, 205,1729,  46, 423,  2,  4,  4,  0,  1,  0,  2, 14,  5,  1,  8,  1,  1,  1,  1,  0,  1,  0
+
+
+# sets composite/svhs coder, if fitted
+coder =  PAL
+
+# sets video filter for all 3 channels
+# dc=250mv, 9MHZ
+VFILTER = 0, 0, 3
+
+# configures what will be available on FPGA after bin is loaded,
+# if a line is ommited, the interface will be not used at all (= all zero)
+#
+# twi for further video configuration
+#
+#         vid
+en_twi =   1
+
+# spi for:
+#     cfg to send config word
+#     osd for OSD support (required for menu handling)
+#
+#         cfg osd
+en_spi =   1,  1
+
+# set spi to 6 MHz
+#spi_clk = 8
+
+# replay button configuration
+#
+#        off / menu / reset
+button = menu
+
+# POST PROCESSING PART
+######################
+
+# VGA/DVI settings, "EN_TWI" must be set to one !
+#           0x1c 0x1d 0x1e 0x1f 0x20 0x21 0x23 0x31 0x33 0x34 0x35 0x36 0x37 0x48 0x49 0x56
+video =     0x00,0x48,0xC0,0x80,0x00,0x01,0x00,0x80,0x08,0x16,0x30,0x60,0x00,0x18,0xC0,0x00
+
+# 2x32bit static+dynamic configuration bits, "CFG" in EN_SPI must be set to one!
+# It is only required if no menu setup is given (which manipulates the settings as well)
+#         31                             0,  31                             0
+config = *11111111111111111111111111111111, *11111111111111111111111111111111
+
+[UPLOAD]
+VERIFY = 1
+#This doesn't seem to work - need to work out how to sim/debug...
+#Checked addresses in sim
+#TODO - check the output on rs232
+ROM = xlorig.rom,0x4000, 0x704000
+ROM = xlhias.rom,0x4000, 0x708000
+ROM = ultimon.rom,0x4000, 0x70c000
+ROM = osbhias.rom,0x4000, 0x710000
+ROM = osborig.rom,0x2800, 0x715800
+ROM = osaorig.rom,0x2800, 0x719800
+
+ROM = ataribas.rom,0x2000,0x700000
+
+# we can use this to modify the Replay keyboard mapper
+# the LUT is located from 0x00020000 to 0x000201FF, each key uses two bytes, 
+# each byte describe one x/y position in the matrix (thus, one key can be
+# mapped to two keys on the matrix):   0yyyxxxx ... matrix key map output
+#                                      1sssssss ... static key map output
+
+#How does this not conflict with RAM? I use this area...
+
+DATA = 0xff,0xff,0x00020000,2
+DATA = 0xff,0xff,0x00020002,2
+DATA = 0xff,0xff,0x00020004,2
+DATA = 0x88,0xff,0x00020006,2
+DATA = 0xa0,0xff,0x00020008,2
+DATA = 0,0xff,0x0002000A,2
+DATA = 0xc0,0xff,0x0002000C,2
+DATA = 0xff,0xff,0x0002000E,2
+DATA = 0xff,0xff,0x00020010,2
+DATA = 0xff,0xff,0x00020012,2
+DATA = 0xff,0xff,0x00020014,2
+DATA = 0xff,0xff,0x00020016,2
+DATA = 0x90,0xff,0x00020018,2
+DATA = 0x54,0xff,0x0002001A,2
+DATA = 0xff,0xff,0x0002001C,2
+DATA = 0xff,0xff,0x0002001E,2
+DATA = 0xff,0xff,0x00020020,2
+DATA = 0xff,0xff,0x00020022,2
+DATA = 0x81,0xff,0x00020024,2
+DATA = 0xff,0xff,0x00020026,2
+DATA = 0x82,0xff,0x00020028,2
+DATA = 0x57,0xff,0x0002002A,2
+DATA = 0x37,0xff,0x0002002C,2
+DATA = 0xff,0xff,0x0002002E,2
+DATA = 0xff,0xff,0x00020030,2
+DATA = 0xff,0xff,0x00020032,2
+DATA = 0x27,0xff,0x00020034,2
+DATA = 0x76,0xff,0x00020036,2
+DATA = 0x77,0xff,0x00020038,2
+DATA = 0x56,0xff,0x0002003A,2
+DATA = 0x36,0xff,0x0002003C,2
+DATA = 0xff,0xff,0x0002003E,2
+DATA = 0xff,0xff,0x00020040,2
+DATA = 0x22,0xff,0x00020042,2
+DATA = 0x26,0xff,0x00020044,2
+DATA = 0x72,0xff,0x00020046,2
+DATA = 0x52,0xff,0x00020048,2
+DATA = 0x30,0xff,0x0002004A,2
+DATA = 0x32,0xff,0x0002004C,2
+DATA = 0xff,0xff,0x0002004E,2
+DATA = 0xff,0xff,0x00020050,2
+DATA = 0x41,0xff,0x00020052,2
+DATA = 0x20,0xff,0x00020054,2
+DATA = 0x70,0xff,0x00020056,2
+DATA = 0x55,0xff,0x00020058,2
+DATA = 0x50,0xff,0x0002005A,2
+DATA = 0x35,0xff,0x0002005C,2
+DATA = 0xff,0xff,0x0002005E,2
+DATA = 0xff,0xff,0x00020060,2
+DATA = 0x43,0xff,0x00020062,2
+DATA = 0x25,0xff,0x00020064,2
+DATA = 0x71,0xff,0x00020066,2
+DATA = 0x75,0xff,0x00020068,2
+DATA = 0x53,0xff,0x0002006A,2
+DATA = 0x33,0xff,0x0002006C,2
+DATA = 0xff,0xff,0x0002006E,2
+DATA = 0xff,0xff,0x00020070,2
+DATA = 0xff,0xff,0x00020072,2
+DATA = 0x45,0xff,0x00020074,2
+DATA = 0x1,0xff,0x00020076,2
+DATA = 0x13,0xff,0x00020078,2
+DATA = 0x63,0xff,0x0002007A,2
+DATA = 0x65,0xff,0x0002007C,2
+DATA = 0xff,0xff,0x0002007E,2
+DATA = 0xff,0xff,0x00020080,2
+DATA = 0x40,0xff,0x00020082,2
+DATA = 0x5,0xff,0x00020084,2
+DATA = 0x15,0xff,0x00020086,2
+DATA = 0x10,0xff,0x00020088,2
+DATA = 0x62,0xff,0x0002008A,2
+DATA = 0x60,0xff,0x0002008C,2
+DATA = 0xff,0xff,0x0002008E,2
+DATA = 0xff,0xff,0x00020090,2
+DATA = 0x42,0xff,0x00020092,2
+DATA = 0x46,0xff,0x00020094,2
+DATA = 0x0,0xff,0x00020096,2
+DATA = 0x2,0xff,0x00020098,2
+DATA = 0x12,0xff,0x0002009A,2
+DATA = 0x66,0xff,0x0002009C,2
+DATA = 0xff,0xff,0x0002009E,2
+DATA = 0xff,0xff,0x000200A0,2
+DATA = 0xff,0xff,0x000200A2,2
+DATA = 0x6,0xff,0x000200A4,2
+DATA = 0xff,0xff,0x000200A6,2
+DATA = 0x16,0xff,0x000200A8,2
+DATA = 0x67,0xff,0x000200AA,2
+DATA = 0xff,0xff,0x000200AC,2
+DATA = 0xff,0xff,0x000200AE,2
+DATA = 0x74,0xff,0x000200B0,2
+DATA = 0x81,0xff,0x000200B2,2
+DATA = 0x14,0xff,0x000200B4,2
+DATA = 0x17,0xff,0x000200B6,2
+DATA = 0xff,0xff,0x000200B8,2
+DATA = 0x7,0xff,0x000200BA,2
+DATA = 0xff,0xff,0x000200BC,2
+DATA = 0xff,0xff,0x000200BE,2
+DATA = 0xff,0xff,0x000200C0,2
+DATA = 0xff,0xff,0x000200C2,2
+DATA = 0xff,0xff,0x000200C4,2
+DATA = 0xff,0xff,0x000200C6,2
+DATA = 0xff,0xff,0x000200C8,2
+DATA = 0xff,0xff,0x000200CA,2
+DATA = 0x64,0xff,0x000200CC,2
+DATA = 0xff,0xff,0x000200CE,2
+DATA = 0xff,0xff,0x000200D0,2
+DATA = 0xff,0xff,0x000200D2,2
+DATA = 0xff,0xff,0x000200D4,2
+DATA = 0xff,0xff,0x000200D6,2
+DATA = 0xff,0xff,0x000200D8,2
+DATA = 0xff,0xff,0x000200DA,2
+DATA = 0xff,0xff,0x000200DC,2
+DATA = 0xff,0xff,0x000200DE,2
+DATA = 0xff,0xff,0x000200E0,2
+DATA = 0xff,0xff,0x000200E2,2
+DATA = 0xff,0xff,0x000200E4,2
+DATA = 0xff,0xff,0x000200E6,2
+DATA = 0xff,0xff,0x000200E8,2
+DATA = 0xff,0xff,0x000200EA,2
+DATA = 0x34,0xff,0x000200EC,2
+DATA = 0xff,0xff,0x000200EE,2
+DATA = 0xff,0xff,0x000200F0,2
+DATA = 0xff,0xff,0x000200F2,2
+DATA = 0xff,0xff,0x000200F4,2
+DATA = 0xff,0xff,0x000200F6,2
+DATA = 0xff,0xff,0x000200F8,2
+DATA = 0xff,0xff,0x000200FA,2
+DATA = 0xff,0xff,0x000200FC,2
+DATA = 0xff,0xff,0x000200FE,2
+DATA = 0xff,0xff,0x00020100,2
+DATA = 0xff,0xff,0x00020102,2
+DATA = 0xff,0xff,0x00020104,2
+DATA = 0xff,0xff,0x00020106,2
+DATA = 0xff,0xff,0x00020108,2
+DATA = 0xff,0xff,0x0002010A,2
+DATA = 0xff,0xff,0x0002010C,2
+DATA = 0xff,0xff,0x0002010E,2
+DATA = 0xff,0xff,0x00020110,2
+DATA = 0xff,0xff,0x00020112,2
+DATA = 0xff,0xff,0x00020114,2
+DATA = 0xff,0xff,0x00020116,2
+DATA = 0xff,0xff,0x00020118,2
+DATA = 0xff,0xff,0x0002011A,2
+DATA = 0xff,0xff,0x0002011C,2
+DATA = 0xff,0xff,0x0002011E,2
+DATA = 0xff,0xff,0x00020120,2
+DATA = 0x47,0xff,0x00020122,2
+DATA = 0xff,0xff,0x00020124,2
+DATA = 0xff,0xff,0x00020126,2
+DATA = 0x82,0xff,0x00020128,2
+DATA = 0xff,0xff,0x0002012A,2
+DATA = 0xff,0xff,0x0002012C,2
+DATA = 0xff,0xff,0x0002012E,2
+DATA = 0xff,0xff,0x00020130,2
+DATA = 0xff,0xff,0x00020132,2
+DATA = 0xff,0xff,0x00020134,2
+DATA = 0xff,0xff,0x00020136,2
+DATA = 0xff,0xff,0x00020138,2
+DATA = 0xff,0xff,0x0002013A,2
+DATA = 0xff,0xff,0x0002013C,2
+DATA = 0xff,0xff,0x0002013E,2
+DATA = 0xff,0xff,0x00020140,2
+DATA = 0xff,0xff,0x00020142,2
+DATA = 0xff,0xff,0x00020144,2
+DATA = 0xff,0xff,0x00020146,2
+DATA = 0xff,0xff,0x00020148,2
+DATA = 0xff,0xff,0x0002014A,2
+DATA = 0xff,0xff,0x0002014C,2
+DATA = 0xff,0xff,0x0002014E,2
+DATA = 0xff,0xff,0x00020150,2
+DATA = 0xff,0xff,0x00020152,2
+DATA = 0xff,0xff,0x00020154,2
+DATA = 0xff,0xff,0x00020156,2
+DATA = 0xff,0xff,0x00020158,2
+DATA = 0xff,0xff,0x0002015A,2
+DATA = 0xff,0xff,0x0002015C,2
+DATA = 0xff,0xff,0x0002015E,2
+DATA = 0xff,0xff,0x00020160,2
+DATA = 0xff,0xff,0x00020162,2
+DATA = 0xff,0xff,0x00020164,2
+DATA = 0xff,0xff,0x00020166,2
+DATA = 0xff,0xff,0x00020168,2
+DATA = 0xff,0xff,0x0002016A,2
+DATA = 0xff,0xff,0x0002016C,2
+DATA = 0xff,0xff,0x0002016E,2
+DATA = 0xff,0xff,0x00020170,2
+DATA = 0xff,0xff,0x00020172,2
+DATA = 0xff,0xff,0x00020174,2
+DATA = 0xff,0xff,0x00020176,2
+DATA = 0xff,0xff,0x00020178,2
+DATA = 0xff,0xff,0x0002017A,2
+DATA = 0xff,0xff,0x0002017C,2
+DATA = 0xff,0xff,0x0002017E,2
+DATA = 0xff,0xff,0x00020180,2
+DATA = 0xff,0xff,0x00020182,2
+DATA = 0xff,0xff,0x00020184,2
+DATA = 0xff,0xff,0x00020186,2
+DATA = 0xff,0xff,0x00020188,2
+DATA = 0xff,0xff,0x0002018A,2
+DATA = 0xff,0xff,0x0002018C,2
+DATA = 0xff,0xff,0x0002018E,2
+DATA = 0xff,0xff,0x00020190,2
+DATA = 0xff,0xff,0x00020192,2
+DATA = 0xff,0xff,0x00020194,2
+DATA = 0xff,0xff,0x00020196,2
+DATA = 0xff,0xff,0x00020198,2
+DATA = 0xff,0xff,0x0002019A,2
+DATA = 0xff,0xff,0x0002019C,2
+DATA = 0xff,0xff,0x0002019E,2
+DATA = 0xff,0xff,0x000201A0,2
+DATA = 0xff,0xff,0x000201A2,2
+DATA = 0xff,0xff,0x000201A4,2
+DATA = 0xff,0xff,0x000201A6,2
+DATA = 0xff,0xff,0x000201A8,2
+DATA = 0xff,0xff,0x000201AA,2
+DATA = 0xff,0xff,0x000201AC,2
+DATA = 0xff,0xff,0x000201AE,2
+DATA = 0xff,0xff,0x000201B0,2
+DATA = 0xff,0xff,0x000201B2,2
+DATA = 0xff,0xff,0x000201B4,2
+DATA = 0xff,0xff,0x000201B6,2
+DATA = 0xff,0xff,0x000201B8,2
+DATA = 0xff,0xff,0x000201BA,2
+DATA = 0xff,0xff,0x000201BC,2
+DATA = 0xff,0xff,0x000201BE,2
+DATA = 0xff,0xff,0x000201C0,2
+DATA = 0xff,0xff,0x000201C2,2
+DATA = 0xff,0xff,0x000201C4,2
+DATA = 0xff,0xff,0x000201C6,2
+DATA = 0xff,0xff,0x000201C8,2
+DATA = 0xff,0xff,0x000201CA,2
+DATA = 0xff,0xff,0x000201CC,2
+DATA = 0xff,0xff,0x000201CE,2
+DATA = 0xff,0xff,0x000201D0,2
+DATA = 0xff,0xff,0x000201D2,2
+DATA = 0xff,0xff,0x000201D4,2
+DATA = 0xff,0xff,0x000201D6,2
+DATA = 0x21,0xff,0x000201D8,2
+DATA = 0xff,0xff,0x000201DA,2
+DATA = 0xff,0xff,0x000201DC,2
+DATA = 0xff,0xff,0x000201DE,2
+DATA = 0xff,0xff,0x000201E0,2
+DATA = 0xff,0xff,0x000201E2,2
+DATA = 0xff,0xff,0x000201E4,2
+DATA = 0xff,0xff,0x000201E6,2
+DATA = 0xff,0xff,0x000201E8,2
+DATA = 0xff,0xff,0x000201EA,2
+DATA = 0xff,0xff,0x000201EC,2
+DATA = 0xff,0xff,0x000201EE,2
+DATA = 0xff,0xff,0x000201F0,2
+DATA = 0xff,0xff,0x000201F2,2
+DATA = 0xff,0xff,0x000201F4,2
+DATA = 0xff,0xff,0x000201F6,2
+DATA = 0xff,0xff,0x000201F8,2
+DATA = 0xff,0xff,0x000201FA,2
+DATA = 0xff,0xff,0x000201FC,2
+DATA = 0xff,0xff,0x000201FE,2
+
+[MENU]
+
+## menu entry - ATARIXL A/V
+title = "800XL Audio/Video"
+
+item = "Double scan",     0x00010000,dynamic
+option = "Yes (HD mode)", 0x00010000,default
+option = "No  (SD mode)", 0x00000000
+
+item = "Audio level", 0x00060000,dynamic
+option = "Max (3)",   0x00060000,default
+option = "Med (2)",   0x00040000
+option = "Med (1)",   0x00020000
+option = "Min (0)",   0x00000000
+
+## menu entry - ATARIXL SETUP
+title = "800XL Setup"
+
+item = "RAM Expansion",0x00000007,dynamic
+option = "64KB",       0x00000000,default
+option = "128KB",      0x00000001
+option = "320KB(Compy)",      0x00000002
+option = "320KB(Rambo)",      0x00000003
+option = "576KB(Compy)",      0x00000004
+option = "576KB(Rambo)",      0x00000005
+option = "1088KB",      0x00000006
+option = "4MB!",      0x00000007
+
+item = "OS",0x000001f8,dynamic
+option = "XL original",0x00000008,default
+option = "XL fast sio",0x00000010
+option = "Ultimon",0x00000018
+option = "OSB fast",0x00000020
+option = "OSB original",0x00000028
+option = "OSA original",0x00000030
+
Index: replay/simulate.sh
===================================================================
--- replay/simulate.sh	(nonexistent)
+++ replay/simulate.sh	(revision 1)
@@ -0,0 +1,67 @@
+#!/bin/bash
+
+echo "---------------------------------------------------------"
+echo "Use 'simulate -run' to skip compilation stage."
+echo "Use 'simulate -view' to show previous simulation results."
+echo "---------------------------------------------------------"
+
+name=Replay
+
+
+
+. /home/markw/altera/xilinx/ise/14.7/ISE_DS/settings32.sh
+
+mkdir -p sim
+pushd sim
+
+# if we have a WDB file, we can view it if requested (otherwise we remove it)
+if [ ! -e $name.wdb -o "$1" != "-view" ]; then
+
+    rm -f $name.wdb
+
+    # if we have a EXE, we can run it if requested (otherwise we remove it)
+    if [ ! -e $name.exe -o "$1" != "-run" ]; then
+
+        rm -f $name.exe
+
+        # copy testbench files
+        cp -p ../tb/Replay_tb.vhd .
+        cp -p ../../replay_lib/tb/ddr.v .
+        cp -p ../../replay_lib/tb/ddr_parameters.vh .
+        cp -p ../../replay_lib/tb/Replay_I2C_CH7301.vhd .
+
+        # copy source files
+        cp -p ../../replay_lib/rtl/*.vhd .
+        cp -p ../source/*.vhd .
+        cp -p ../source/*.vhdl .
+
+
+        # set up project definition file
+        xilperl -p -e 's/^(.+)/vhdl work $1/;' ../$name.prj > $name.prj
+        cat ../${name}_tb.prj >> $name.prj
+
+
+        # verbose & no multthreading - fallback in case of problems
+        # fuse -v 1 -mt off -incremental -prj %name%.prj -o %name%.exe -t %name%
+
+        fuse -timeprecision_vhdl 1fs -incremental -prj $name.prj -o $name.exe -t ${name}_tb || exit 1
+        # fuse --mt off -prj %name%.prj -o %name%.exe -t %name%_tb
+
+        # Check for the EXE again, independent of the errorlevel of fuse...
+        [ -e $name.exe ] || echo "No simulation executable created"
+
+
+    fi
+
+    # Open the iSIM GUI and run the simulation
+    ./$name.exe -gui -f ../$name.cmd -wdb $name.wdb -log $name.log -view ../$name.wcfg || exit 1
+
+
+else
+
+    # Only start the viewer on an existing wave configuration (from an old simulation)
+    isimgui -view ../$name.wcfg || exit 1
+
+fi
+
+popd

Property changes on: replay/simulate.sh
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: unmerged/NOTES
===================================================================
--- unmerged/NOTES	(nonexistent)
+++ unmerged/NOTES	(revision 1)
@@ -0,0 +1,11 @@
+DE1 first
+DE1 ported to MCC
+  -- changes:
+	
+MCC ported to MIST
+MIST ported to Replay
+
+So replay has latest core version!
+TAKE THAT...
+
+Then copy core specific bits to their own dir...
Index: replay/Replay.prj
===================================================================
--- replay/Replay.prj	(nonexistent)
+++ replay/Replay.prj	(revision 1)
@@ -0,0 +1,76 @@
+Replay_Pack.vhd
+Replay_VideoTiming_Pack.vhd
+Replay_DDRCtrl_Pack.vhd
+Replay_TranslatePS2_Pack.vhd
+Replay_TranslatePS2.vhd
+FIFO_Async_D16.vhd
+FIFO_Async_D32.vhd
+FIFO_SyncSRL_D16.vhd
+FIFO_SyncBlock_D1024_W18.vhd
+FIFO_SyncBlock_D2048_W8.vhd
+DPRAM_BE_D64.vhd
+Replay_DDRCtrl_Datapath.vhd
+Replay_DDRCtrl.vhd
+Replay_DDRCtrl_Top.vhd
+font0_rom.vhd
+font1_rom.vhd
+font2_rom.vhd
+kcpsm3.vhd
+ps2_rom.vhd
+Replay_I2C.vhd
+Replay_SPI8.vhd
+Replay_VideoTiming.vhd
+Replay_VideoConverter.vhd
+Replay_OSD.vhd
+Replay_Syscon.vhd
+Replay_FileIO_Sync.vhd
+Replay_Video.vhd
+Replay_ClockGen_Sync.vhd
+Replay_DDRCtrl.vhd
+Replay_JoyPS2.vhd
+Replay_Audio.vhd
+Replay_MousePointer.vhd
+address_decoder.vhdl
+antic_counter.vhdl
+antic_dma_clock.vhdl
+antic.vhdl
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+cpu_6510.vhd
+cpu.vhd
+delay_line.vhdl
+enable_divider.vhdl
+generic_ram_infer.vhdl
+gtia_palette.vhdl
+gtia_player.vhdl
+gtia_priority.vhdl
+gtia.vhdl
+internalromram.vhd
+irq_glue.vhdl
+pia.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_mixer.vhdl
+pokey_noise_filter.vhdl
+pokey.vhdl
+poly_17_9.vhdl
+poly_4.vhdl
+poly_5.vhdl
+reg_file.vhdl
+shared_enable.vhdl
+simple_counter.vhdl
+synchronizer.vhdl
+syncreset_enable_divider.vhd
+wide_delay_line.vhdl
+zpupkg.vhd
+zpu_config_regs.vhdl
+zpu_core.vhd
+zpu_glue.vhdl
+zpu_rom.vhdl
+basic.vhdl
+os16.vhdl
+covox.vhd
+atari800core.vhd
+Core_Top.vhd
+Replay_Top.vhd
Index: replay/sdcard/ultimon.rom
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/ultimon.rom
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: replay/source/Core_Top.vhd
===================================================================
--- replay/source/Core_Top.vhd	(nonexistent)
+++ replay/source/Core_Top.vhd	(revision 1)
@@ -0,0 +1,510 @@
+-- WWW.FPGAArcade.COM
+-- REPLAY 1.0
+-- Retro Gaming Platform
+-- No Emulation No Compromise
+--
+-- All rights reserved
+-- Mike Johnson 2008/2009
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.FPGAArcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- ===================================================================
+--
+-- This file was modified to embed Mikes VIC-20 core by W. Scherr
+-- Email ws_arcade <at> pin4.at
+--
+-- $Id: Core_Top.vhd 357 2014-02-22 20:32:21Z wolfgang.scherr $
+--
+-- Latest version can be found at: www.pin4.at
+--
+-- ===================================================================
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+  use work.Replay_Pack.all;
+  use work.Replay_VideoTiming_Pack.all;
+  use work.Replay_TranslatePS2_Pack.all;
+
+library UNISIM;
+  use UNISIM.Vcomponents.all;
+
+entity Core_Top is
+  port (
+    i_Clk_Vid             : in    bit1; -- ~27 MHz
+    i_Ena_Vid             : in    bit1;
+    i_Rst_Vid             : in    bit1;
+    --
+    i_ClK_Sys             : in    bit1; -- 106.4 / 4 --> 26.62 MHz
+    i_Ena_Sys             : in    bit1; -- 26.62 / 3 --> 8.875 MHz
+    i_Ena_Sub4            : in    bit1; -- 26.62 / 6  --> 4.43 MHz
+    i_Ena_Sub1            : in    bit1; -- 26.62 / 24 --> 1.11 MHz
+    i_Rst_Sys             : in    bit1;
+    --
+    i_Joy_A               : in    word( 5 downto 0); -- lower port
+    i_Joy_B               : in    word( 5 downto 0); -- upper port
+    --
+    i_Ms_We               : in    bit1;
+    i_Ms_PosX             : in    word(11 downto 0);
+    i_Ms_PosY             : in    word(11 downto 0);
+    i_Ms_Butn             : in    word( 2 downto 0);
+    --
+    i_Kb_osd_inhibit      : in    bit1;
+    i_Kb_ps2_we           : in    bit1;
+    i_Kb_ps2              : in    word( 7 downto 0);
+    o_kb_led              : out   word( 2 downto 0);
+    --
+    core_ps2_data         : in bit1;
+    core_ps2_clk          : in bit1;
+    --
+    i_Rst_Core            : in    bit1;
+    i_Halt_Core           : in    bit1;
+    i_HD_Mode             : in    bit1; -- selects between the HD and SD video mode generic
+    o_act_led_n           : out   bit1;
+    --
+    i_Audio_lvl           : in    word(1 downto 0);
+    --
+    o_Audio_l             : out   word(23 downto 0);
+    o_Audio_R             : out   word(23 downto 0);
+    i_Audio_Taken         : in    bit1;
+    -- config stuff
+    I_CART_RO             : in    bit1; -- high means read-only for VIC-20 (write only via low-prio IF fram ARM)
+    I_CART_EN             : in    bit1; -- at $A000(8k)
+    I_RAM_EXT             : in    word(3 downto 0); -- at $6000(8k),$4000(8k),$2000(8k),$0400(3k)
+    drive_address         : in    word(1 downto 0); -- 0/1/2/3 means drive address 8/9/10/11
+    --
+    o_Vid_RGB             : out   word(23 downto 0);
+    o_Vid_Sync            : out   r_Vidsync;
+    -- media access (directly mapped d64 file format)
+    diskid_i              : in  std_logic_vector(15 downto 0);
+    media_adr_o           : out   unsigned(17 downto 0);
+    media_read_o          : out   bit1;
+    media_dat_i           : in    word(7 downto 0);
+    floppy_inserted       : in    bit1;
+    write_prot_n          : in    bit1;
+    -- sideband info
+    o_Vid_Timing          : out   r_Vidtiming;
+    o_Vid_Std             : out   r_Vidstd;
+    -- to DRAM controller
+    hp_ddr_valid          : out std_logic;
+    hp_ddr_taken          : in std_logic;
+    hp_ddr_addr           : out std_logic_vector(25 downto 2);
+    hp_wl                 : out std_logic;
+    hp_wbe                : out   std_logic_vector(3 downto 0);
+    hp_wdata              : out std_logic_vector(31 downto 0);
+    hp_rdata              : in std_logic_vector(31 downto 0);
+    hp_ddr_wr             : in std_logic;
+
+    -- RS232 debug port
+    i_RS232_RXD           : in    bit1;
+    o_RS232_TXD           : out   bit1;
+    i_RS232_CTS           : in    bit1;
+    o_RS232_RTS           : out   bit1;
+
+    -- debug port for ext. DLA (4 channels with 9 bit) 
+    debug                 : out   word(9*4-1 downto 0);
+    debugi                : in    word(2 downto 0);
+    -- setup bus (write only)
+    CONF_WR               : in    bit1;
+    CONF_WR_1541          : in    bit1;
+    CONF_WR_KEY           : in    bit1;
+    CONF_AI               : in    word(15 downto 0);
+    CONF_DI               : in    word(7 downto 0);
+
+    ram_select            : in word(2 downto 0);
+    rom_select            : in word(5 downto 0)
+    );
+end;
+
+architecture RTL of Core_Top is
+
+  -- selects core related debugging signals for internal debug
+  constant int_dla_core_debug : boolean := false;
+
+  signal PLL_LOCKED : std_logic;
+
+  signal res_s                     : bit1;
+  signal core_en_s                 : bit1;
+
+  signal atn_i                     : bit1;
+  signal clk_i                     : bit1;
+  signal data_i                    : bit1;
+
+  signal fatn_o                    : bit1;
+  signal fclk_o                    : bit1;
+  signal fdata_o                   : bit1;
+  signal catn_o                    : bit1;
+  signal cclk_o                    : bit1;
+  signal cdata_o                   : bit1;
+
+  signal lsound_s                   : std_logic_vector(15 downto 0);
+  signal rsound_s                   : std_logic_vector(15 downto 0);
+  signal lsample_s                  : word(23 downto 0);
+  signal rsample_s                  : word(23 downto 0);
+
+  signal core_blankn_s             : bit1;
+  signal core_blankn_ds            : bit1;
+  signal core_hsyncn_s             : bit1;
+  signal core_vsyncn_s             : bit1;
+  signal core_hsync                : bit1;
+  signal core_vsync                : bit1;
+  signal core_blank                : bit1;
+  signal core_r_s                  : std_logic_vector(7 downto 0);
+  signal core_g_s                  : std_logic_vector(7 downto 0);
+  signal core_b_s                  : std_logic_vector(7 downto 0);
+
+  signal matrix_in                 : word(7 downto 0);
+  signal matrix_out                : word(15 downto 0);
+  signal matrix_out_mix            : word(7 downto 0);
+  signal static_keys               : word(6 downto 0);
+  signal pause_key                 : bit1;
+  signal sh_lock_key               : bit1;
+  signal stat6_del                 : bit1;
+
+  signal joy_mix                   : word(4 downto 0);
+
+  signal SDRAM_REQUEST : std_logic;
+  signal SDRAM_REQUEST_COMPLETE : std_logic;
+  signal SDRAM_READ_ENABLE :  STD_LOGIC;
+  signal SDRAM_WRITE_ENABLE : std_logic;
+  signal SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+  signal SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  signal SDRAM_DI : STD_LOGIC_VECTOR(31 DOWNTO 0);
+  signal SDRAM_WIDTH_8bit_ACCESS : std_logic;
+  signal SDRAM_WIDTH_16bit_ACCESS : std_logic;
+  signal SDRAM_WIDTH_32bit_ACCESS : std_logic;
+
+  signal ddr_response_pending_next : std_logic;
+  signal ddr_response_pending_reg : std_logic;
+
+  signal ddr_request_pending_next : std_logic;
+  signal ddr_request_pending_reg : std_logic;
+
+  signal core_blank_count_next : std_logic_vector(23 downto 0);
+  signal core_blank_count_reg : std_logic_vector(23 downto 0);
+
+begin
+  -- core control
+  res_s <= i_Rst_Core;
+  core_en_s <= i_Ena_Sys and not i_Halt_Core and not pause_key;
+
+PLL_LOCKED <= not(i_rst_sys or i_Rst_Core);
+atari800core : entity work.atari800core
+	PORT map
+	(
+		CLK => i_clk_sys,
+		PLL_LOCKED => PLL_LOCKED,
+
+		VGA_VS => core_vsync,
+		VGA_HS => core_hsync,
+		VGA_B => core_b_s,
+		VGA_G => core_g_s,
+		VGA_R => core_r_s,
+
+		matrix_out => matrix_out,
+		matrix_in => matrix_in,
+		static_keys => static_keys,
+		pause_key => pause_key,
+
+		JOY1_n => i_Joy_A,
+		JOY2_n => i_Joy_B,
+		
+		AUDIO_L => lsound_s,
+		AUDIO_R => rsound_s,
+
+		SDRAM_REQUEST => SDRAM_REQUEST,
+		SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		SDRAM_READ_ENABLE => SDRAM_READ_ENABLE,
+		SDRAM_WRITE_ENABLE => SDRAM_WRITE_ENABLE,
+		SDRAM_ADDR => SDRAM_ADDR,
+		SDRAM_DO => SDRAM_DO,
+		SDRAM_DI => SDRAM_DI,
+		SDRAM_WIDTH_8bit_ACCESS => SDRAM_WIDTH_8bit_ACCESS,
+		SDRAM_WIDTH_16bit_ACCESS => SDRAM_WIDTH_16bit_ACCESS,
+		SDRAM_WIDTH_32bit_ACCESS => SDRAM_WIDTH_32bit_ACCESS,
+
+		SIO_RXD => i_RS232_RXD,
+		SIO_TXD => o_RS232_TXD,
+		SIO_COMMAND_TX => o_RS232_RTS,
+
+		ram_select => ram_select,
+		rom_select => rom_select,
+
+		halt => i_Halt_Core
+	);
+
+  ----------------------------------------------------------
+  -- KEYBOARD MAPPER
+  ----------------------------------------------------------
+
+  u_Kbd : entity work.Replay_TranslatePS2
+  generic map (
+    g_kb_map              => c_vic20_kb_map -- TODO make atari version rather than putting it all in the ini file!
+  )
+  port map (
+    i_ClK_Sys               => i_ClK_Sys,
+    i_ena_sys             => core_en_s,
+    i_rst_sys             => res_s,
+    i_kb_osd_inhibit      => i_kb_osd_inhibit,
+    i_kb_ps2_we           => i_kb_ps2_we,
+    i_kb_ps2              => i_kb_ps2,
+    i_matrix_in           => matrix_in,
+    o_matrix_out          => matrix_out,
+    o_static_keys         => static_keys,
+    o_pause_key           => pause_key,
+    i_conf_wr             => CONF_WR_KEY,
+    i_conf_adr            => CONF_AI(8 downto 0),
+    i_conf_dat            => CONF_DI
+  );
+
+  -- mix joystick / keyboard (num-pad)
+  joy_mix <= i_Joy_A(4 downto 0) and not( static_keys(4 downto 0) );
+
+  -- handling shift-lock key (on/off switch on CBM keyboard)
+  shiftlock : process (i_ClK_Sys, i_Rst_Sys) is
+  begin
+    if i_Rst_Sys='1' then
+      sh_lock_key <= '0';
+    elsif rising_edge(i_ClK_Sys) then
+      stat6_del <= static_keys(6);
+      if static_keys(6)='1' and stat6_del='0' then
+        -- shift-lock pressed, toggle it
+        sh_lock_key <= not sh_lock_key;
+      end if;
+    end if;
+  end process shiftlock;
+  o_kb_led(0) <= pause_key;     -- SCROLL LOCK LED
+  o_kb_led(1) <= '0';           -- NUM LOCK LED (take care, enables overlayed NUM keys on compact keyboards as well!)
+  o_kb_led(2) <= sh_lock_key;   -- CAPS LOCK LED
+
+  -- mix keyboard matrix with shift-lock key
+  matrix_out_mix <= matrix_out(7 downto 0) OR X"02" when sh_lock_key='1' and matrix_in=X"08" else
+                    matrix_out(7 downto 0);
+
+  ----------------------------------------------------------
+  -- AUDIO
+  ----------------------------------------------------------
+
+  -- we have some simple gain setup (a little logarithmic) as well before passing to replay
+  lsample_s <= lsound_s(15) & lsound_s & "0000000" when i_Audio_lvl="11" else
+              lsound_s(15) & lsound_s(15) & lsound_s & "000000" when i_Audio_lvl="10" else
+              lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s & "0000" when i_Audio_lvl="01" else
+              lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s(15) & lsound_s & "0";
+
+  rsample_s <= rsound_s(15) & rsound_s & "0000000" when i_Audio_lvl="11" else
+              rsound_s(15) & rsound_s(15) & rsound_s & "000000" when i_Audio_lvl="10" else
+              rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s & "0000" when i_Audio_lvl="01" else
+              rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s(15) & rsound_s & "0";
+  o_Audio_l <= lsample_s;
+  o_Audio_R <= rsample_s;
+
+  ----------------------------------------------------------
+  -- VIDEO CONVERTER
+  ----------------------------------------------------------
+
+  process(i_ena_sys, core_hsync, core_blank_count_reg)
+  begin
+    core_blank_count_next <= core_blank_count_reg;
+    core_blankn_s <= '1';
+
+    if (i_ena_sys = '1') then
+      core_blank_count_next <= std_logic_vector(unsigned(core_blank_count_reg)+1);
+    end if;
+
+    if (core_hsync = '1') then
+      core_blank_count_next <= (others=>'0');
+    end if;
+
+    if (core_blank_count_reg < X"33") then
+      core_blankn_s <= '0';
+    end if;
+
+  end process;
+
+  process(i_Clk_sys,i_rst_sys)
+  begin
+  	if (i_rst_sys = '1') then
+  		core_blank_count_reg <= (others=>'0');
+  	elsif (i_clk_sys'event and i_clk_sys='1') then
+  		core_blank_count_reg <= core_blank_count_next;
+  	end if;
+  end process;
+
+  core_hsyncn_s <= not(core_hsync);
+  core_vsyncn_s <= not(core_vsync);
+
+  vconv : entity work.Replay_VideoConverter
+    generic map (
+      -- output format
+      g_Vid_Param_HD  => c_Vidparam_720x576p_50,
+      g_Vid_Param_SD  => c_Vidparam_720x576i_50,
+      -- input parameters
+      g_R_Bitwidth    => 8,  -- color bitwidths
+      g_G_Bitwidth    => 8,  -- color bitwidths
+      g_B_Bitwidth    => 8,  -- color bitwidths
+      -- conversion parameters
+      g_Vsize         => 248,-- visible vertical frame size
+      g_Hsize         => 900,-- visible horizontal frame size
+      g_Match_Line    => 0,  -- input line used for frame sync  (up to 311)
+      g_Vadr_Width    => 2,  -- buffer vertical address width
+      g_Hadr_Width    => 9,  -- buffer horizontal address width
+      g_Hscale        => "010000000", -- scales horizontally (256*360/720) NON INTEGRAL FRACTIONS LOOK TERRIBLE
+      g_Vres_half     => 1,  -- half output lines vertically (=double-scan)
+      g_Loffset       => 0,  -- buffer line offset on output
+      g_Voffset       => 21,  -- vertical buffer offset on output
+      g_Hoffset       => 0 -- horizontal buffer offset on output
+      )
+    port map (
+      i_Clk_Vid       => i_Clk_Vid,
+      i_Ena_Vid       => i_Ena_Vid,
+      i_Rst_Vid       => i_Rst_Vid,
+      --
+      i_ClK_Sys         => i_ClK_Sys,
+      i_Ena_Sys       => i_Ena_Sys,
+      i_Rst_Sys       => i_Rst_Sys,
+      --
+      i_HD_Mode       => i_HD_Mode,
+      --
+      i_Vid_r         => std_logic_vector(core_r_s),
+      i_Vid_g         => std_logic_vector(core_g_s),
+      i_Vid_b         => std_logic_vector(core_b_s),
+      i_Vid_hsyncn    => core_hsyncn_s,
+      i_Vid_vsyncn    => core_vsyncn_s,
+      i_Vid_blankn    => core_blankn_s,
+      --
+      o_Vid_RGB       => o_Vid_RGB,
+      o_Vid_Sync      => o_Vid_Sync,
+      o_Vid_Timing    => o_Vid_Timing,
+      o_Vid_Std       => o_Vid_Std
+    );
+
+-----------------------------------
+-- DRAM ADAPTOR for atari
+-----------------------------------
+-- Atari signals
+--  SDRAM_REQUEST : std_logic;
+--  SDRAM_REQUEST_COMPLETE : std_logic;
+--  SDRAM_READ_ENABLE :  STD_LOGIC;
+--  SDRAM_WRITE_ENABLE : std_logic;
+--  SDRAM_ADDR : STD_LOGIC_VECTOR(22 DOWNTO 0);
+--  SDRAM_DO : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SDRAM_DI : STD_LOGIC_VECTOR(31 DOWNTO 0);
+--  SDRAM_WIDTH_8bit_ACCESS : std_logic;
+--  SDRAM_WIDTH_16bit_ACCESS : std_logic;
+--  SDRAM_WIDTH_32bit_ACCESS : std_logic.
+--
+-- Replay signals
+--    hp_ddr_valid          : out std_logic;
+--    hp_ddr_taken          : in std_logic;
+--    hp_ddr_addr           : out std_logic_vector(25 downto 2);
+--    hp_wl                 : out std_logic;
+--    hp_wbe                : out   std_logic_vector(1 downto 0);
+--    hp_wdata              : out std_logic_vector(31 downto 0);
+--    hp_rdata              : in std_logic_vector(31 downto 0);
+--    hp_ddr_wr             : in std_logic;
+--
+-- Every ena_sys cycle I can do a single 32 bit read/write access
+-- For the Atari I'm going to do an access every other ena_sys...
+process(i_ena_sys, SDRAM_REQUEST, SDRAM_READ_ENABLE, SDRAM_WRITE_ENABLE, SDRAM_ADDR, SDRAM_DI, SDRAM_WIDTH_8bit_access, SDRAM_WIDTH_16bit_ACCESS, SDRAM_WIDTH_32bit_ACCESS, ddr_request_pending_reg, ddr_response_pending_reg, hp_ddr_wr, hp_ddr_taken)
+begin
+	ddr_request_pending_next <= ddr_request_pending_reg or sdram_request;
+	dDR_REsponse_pending_next <= ddr_response_pending_reg;
+
+	sdram_request_complete <= '0';
+	hp_ddr_valid <= '0';
+
+	if (i_ena_sys='1') then
+		if (((ddr_request_pending_reg or sdram_request) and not (ddr_response_pending_reg)) = '1') then
+			hp_ddr_valid <= '1';
+			ddr_request_pending_next <= '0';
+			ddr_response_pending_next <= '1';
+		end if;
+
+		-- Is there an issue with hp_ddr_wr - it gets cleared before the enable??
+		if (ddr_response_pending_reg = '1') then
+			-- previous request completed
+			sdram_request_complete <= '1';
+			ddr_response_pending_next <= '0';
+		end if;
+	end if;
+
+	hp_ddr_addr <= "000"&sdram_addr(22 downto 2);
+	hp_wl <= not(sdram_write_enable);
+	hp_wbe <= (others=>SDRAM_WIDTH_32bit_ACCESS);
+	-- TODO 16-bit (not used anyway by a800 yet)
+
+	SDRAM_DO <= hp_rdata;
+	hp_wdata <= SDRAM_DI;
+
+	if (SDRAM_WIDTH_8bit_access = '1') then
+		hp_wdata <= (others=>'0');
+		SDRAM_DO <= (others=>'0');
+
+		case (sdram_addr(1 downto 0)) is
+		when "11" =>
+			hp_wbe(0) <= '1';
+			SDRAM_DO(7 downto 0) <= hp_rdata(7 downto 0);
+			hp_wdata(7 downto 0) <= SDRAM_DI(7 downto 0);
+		when "10" =>
+			hp_wbe(1) <= '1';
+			SDRAM_DO(7 downto 0) <= hp_rdata(15 downto 8);
+			hp_wdata(15 downto 8) <= SDRAM_DI(7 downto 0);
+		when "01" =>
+			hp_wbe(2) <= '1';
+			SDRAM_DO(7 downto 0) <= hp_rdata(23 downto 16);
+			hp_wdata(23 downto 16) <= SDRAM_DI(7 downto 0);
+		when "00" =>
+			hp_wbe(3) <= '1';
+			SDRAM_DO(7 downto 0) <= hp_rdata(31 downto 24);
+			hp_wdata(31 downto 24) <= SDRAM_DI(7 downto 0);
+		when others =>
+			-- nop
+		end case;
+	end if;
+
+end process;
+
+process(i_Clk_sys,i_rst_sys)
+begin
+	if (i_rst_sys = '1') then
+		ddr_request_pending_reg <= '0';
+		ddr_response_pending_reg <= '0';
+	elsif (i_clk_sys'event and i_clk_sys='1') then
+		ddr_request_pending_reg <= ddr_request_pending_next;
+		ddr_response_pending_reg <= ddr_response_pending_next;
+	end if;
+end process;
+
+end RTL;
Index: replay/Replay.wcfg
===================================================================
--- replay/Replay.wcfg	(nonexistent)
+++ replay/Replay.wcfg	(revision 1)
@@ -0,0 +1,1973 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="Replay.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="numeric_std" />
+            <top_module name="replay_ddrctrl_pack" />
+            <top_module name="replay_pack" />
+            <top_module name="replay_tb" />
+            <top_module name="replay_translateps2_pack" />
+            <top_module name="replay_videotiming_pack" />
+            <top_module name="std_logic_1164" />
+            <top_module name="std_logic_arith" />
+            <top_module name="std_logic_textio" />
+            <top_module name="std_logic_unsigned" />
+            <top_module name="t65_pack" />
+            <top_module name="textio" />
+            <top_module name="vcomponents" />
+            <top_module name="vital_primitives" />
+            <top_module name="vital_timing" />
+            <top_module name="vl_types" />
+            <top_module name="vpkg" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="439" />
+   <wave_markers>
+      <marker time="176223965008000" label="" />
+      <marker time="176305111888000" label="" />
+      <marker time="5280905469000" label="" />
+      <marker time="176560308000" label="" />
+   </wave_markers>
+   <wvobject fp_name="divider65" type="divider">
+      <obj_property name="label">TOP</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_2v5_io_0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_2v5_io_0</obj_property>
+      <obj_property name="ObjectShortName">b_2v5_io_0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_2v5_io_1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_2v5_io_1</obj_property>
+      <obj_property name="ObjectShortName">b_2v5_io_1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_aux_io" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">b_aux_io[39:0]</obj_property>
+      <obj_property name="ObjectShortName">b_aux_io[39:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_clk_aux" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_clk_aux</obj_property>
+      <obj_property name="ObjectShortName">b_clk_aux</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_fpga_spi_miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_fpga_spi_miso</obj_property>
+      <obj_property name="ObjectShortName">b_fpga_spi_miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_fpga_spi_mosi" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_fpga_spi_mosi</obj_property>
+      <obj_property name="ObjectShortName">b_fpga_spi_mosi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_io" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">b_io[54:0]</obj_property>
+      <obj_property name="ObjectShortName">b_io[54:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_mem_dq" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">b_mem_dq[15:0]</obj_property>
+      <obj_property name="ObjectShortName">b_mem_dq[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_mem_ldqs" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_mem_ldqs</obj_property>
+      <obj_property name="ObjectShortName">b_mem_ldqs</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_mem_udqs" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_mem_udqs</obj_property>
+      <obj_property name="ObjectShortName">b_mem_udqs</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_ps2a_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_ps2a_clk</obj_property>
+      <obj_property name="ObjectShortName">b_ps2a_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_ps2a_data" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_ps2a_data</obj_property>
+      <obj_property name="ObjectShortName">b_ps2a_data</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_ps2b_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_ps2b_clk</obj_property>
+      <obj_property name="ObjectShortName">b_ps2b_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_ps2b_data" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_ps2b_data</obj_property>
+      <obj_property name="ObjectShortName">b_ps2b_data</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_scl" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_scl</obj_property>
+      <obj_property name="ObjectShortName">b_scl</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_sda" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_sda</obj_property>
+      <obj_property name="ObjectShortName">b_sda</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_video_ddc_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_video_ddc_clk</obj_property>
+      <obj_property name="ObjectShortName">b_video_ddc_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_video_ddc_data" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_video_ddc_data</obj_property>
+      <obj_property name="ObjectShortName">b_video_ddc_data</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_video_spc" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_video_spc</obj_property>
+      <obj_property name="ObjectShortName">b_video_spc</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/b_video_spd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">b_video_spd</obj_property>
+      <obj_property name="ObjectShortName">b_video_spd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_cal_sel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_cal_sel[1:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_cal_sel[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_ctrl" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_ctrl[15:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_ctrl[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_dynamic" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_dynamic[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_dynamic[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_fileio" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_fileio[7:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_fileio[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_fileio_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_fileio_i[7:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_fileio_i[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_phase" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_phase[7:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_phase[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/cfg_static" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">cfg_static[31:0]</obj_property>
+      <obj_property name="ObjectShortName">cfg_static[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_a</obj_property>
+      <obj_property name="ObjectShortName">clk_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_aud" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_aud</obj_property>
+      <obj_property name="ObjectShortName">clk_aud</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_b" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_b</obj_property>
+      <obj_property name="ObjectShortName">clk_b</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_c" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_c</obj_property>
+      <obj_property name="ObjectShortName">clk_c</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_capture" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_capture</obj_property>
+      <obj_property name="ObjectShortName">clk_capture</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_ctl" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_ctl</obj_property>
+      <obj_property name="ObjectShortName">clk_ctl</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_ram" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_ram</obj_property>
+      <obj_property name="ObjectShortName">clk_ram</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_ram_90" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_ram_90</obj_property>
+      <obj_property name="ObjectShortName">clk_ram_90</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_spi" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_spi</obj_property>
+      <obj_property name="ObjectShortName">clk_spi</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_sys" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_sys</obj_property>
+      <obj_property name="ObjectShortName">clk_sys</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_vid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_vid</obj_property>
+      <obj_property name="ObjectShortName">clk_vid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/clk_vid_90" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_vid_90</obj_property>
+      <obj_property name="ObjectShortName">clk_vid_90</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_audio_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">core_audio_l[23:0]</obj_property>
+      <obj_property name="ObjectShortName">core_audio_l[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_audio_r" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">core_audio_r[23:0]</obj_property>
+      <obj_property name="ObjectShortName">core_audio_r[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_ps2_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">core_ps2_clk</obj_property>
+      <obj_property name="ObjectShortName">core_ps2_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_ps2_data" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">core_ps2_data</obj_property>
+      <obj_property name="ObjectShortName">core_ps2_data</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_vid_rgb" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">core_vid_rgb[23:0]</obj_property>
+      <obj_property name="ObjectShortName">core_vid_rgb[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_vid_std" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">core_vid_std</obj_property>
+      <obj_property name="ObjectShortName">core_vid_std</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_vid_sync" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">core_vid_sync</obj_property>
+      <obj_property name="ObjectShortName">core_vid_sync</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/core_vid_timing" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">core_vid_timing</obj_property>
+      <obj_property name="ObjectShortName">core_vid_timing</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/diskid_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">diskid_s[15:0]</obj_property>
+      <obj_property name="ObjectShortName">diskid_s[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/dla_mem_enable" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">dla_mem_enable</obj_property>
+      <obj_property name="ObjectShortName">dla_mem_enable</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/drive_scl_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">drive_scl_low</obj_property>
+      <obj_property name="ObjectShortName">drive_scl_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/drive_sda_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">drive_sda_low</obj_property>
+      <obj_property name="ObjectShortName">drive_sda_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/drive_spc_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">drive_spc_low</obj_property>
+      <obj_property name="ObjectShortName">drive_spc_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/drive_spd_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">drive_spd_low</obj_property>
+      <obj_property name="ObjectShortName">drive_spd_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ena_sub1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sub1</obj_property>
+      <obj_property name="ObjectShortName">ena_sub1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ena_sub4" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sub4</obj_property>
+      <obj_property name="ObjectShortName">ena_sub4</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ena_sys" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sys</obj_property>
+      <obj_property name="ObjectShortName">ena_sys</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ena_sys_c1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sys_c1</obj_property>
+      <obj_property name="ObjectShortName">ena_sys_c1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ena_sys_ddr" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sys_ddr</obj_property>
+      <obj_property name="ObjectShortName">ena_sys_ddr</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ena_vid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_vid</obj_property>
+      <obj_property name="ObjectShortName">ena_vid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/extmem_addr_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_addr_s[15:0]</obj_property>
+      <obj_property name="ObjectShortName">extmem_addr_s[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/extmem_datai_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_datai_s[7:0]</obj_property>
+      <obj_property name="ObjectShortName">extmem_datai_s[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/extmem_datao_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_datao_s[7:0]</obj_property>
+      <obj_property name="ObjectShortName">extmem_datao_s[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/extmem_r_wn_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_r_wn_s</obj_property>
+      <obj_property name="ObjectShortName">extmem_r_wn_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/extmem_sel_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_sel_s</obj_property>
+      <obj_property name="ObjectShortName">extmem_sel_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/halt_soft" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">halt_soft</obj_property>
+      <obj_property name="ObjectShortName">halt_soft</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_ddr_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_ddr_addr[25:0]</obj_property>
+      <obj_property name="ObjectShortName">hp_ddr_addr[25:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_ddr_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_ddr_taken</obj_property>
+      <obj_property name="ObjectShortName">hp_ddr_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_ddr_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_ddr_valid</obj_property>
+      <obj_property name="ObjectShortName">hp_ddr_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_ddr_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_ddr_we</obj_property>
+      <obj_property name="ObjectShortName">hp_ddr_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_rdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_rdata[31:0]</obj_property>
+      <obj_property name="ObjectShortName">hp_rdata[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_wbe" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_wbe[3:0]</obj_property>
+      <obj_property name="ObjectShortName">hp_wbe[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_wdata" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_wdata[31:0]</obj_property>
+      <obj_property name="ObjectShortName">hp_wdata[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/hp_wl" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_wl</obj_property>
+      <obj_property name="ObjectShortName">hp_wl</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_aux_ip" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_aux_ip[22:0]</obj_property>
+      <obj_property name="ObjectShortName">i_aux_ip[22:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_ext_rst_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_ext_rst_l</obj_property>
+      <obj_property name="ObjectShortName">i_ext_rst_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_fpga_ctrl0" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_fpga_ctrl0</obj_property>
+      <obj_property name="ObjectShortName">i_fpga_ctrl0</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_fpga_ctrl1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_fpga_ctrl1</obj_property>
+      <obj_property name="ObjectShortName">i_fpga_ctrl1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_fpga_spi_clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_fpga_spi_clk</obj_property>
+      <obj_property name="ObjectShortName">i_fpga_spi_clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_joy_a" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_joy_a[5:0]</obj_property>
+      <obj_property name="ObjectShortName">i_joy_a[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_joy_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_joy_b[5:0]</obj_property>
+      <obj_property name="ObjectShortName">i_joy_b[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_rs232_cts" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_rs232_cts</obj_property>
+      <obj_property name="ObjectShortName">i_rs232_cts</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_rs232_rxd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_rs232_rxd</obj_property>
+      <obj_property name="ObjectShortName">i_rs232_rxd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/i_video_int" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_video_int</obj_property>
+      <obj_property name="ObjectShortName">i_video_int</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/init_diskinsert_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">init_diskinsert_s</obj_property>
+      <obj_property name="ObjectShortName">init_diskinsert_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/inscnt_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">inscnt_s[18:0]</obj_property>
+      <obj_property name="ObjectShortName">inscnt_s[18:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/kb_inhibit" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">kb_inhibit</obj_property>
+      <obj_property name="ObjectShortName">kb_inhibit</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/kb_led" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">kb_led[2:0]</obj_property>
+      <obj_property name="ObjectShortName">kb_led[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/kb_ps2" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">kb_ps2[7:0]</obj_property>
+      <obj_property name="ObjectShortName">kb_ps2[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/kb_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">kb_we</obj_property>
+      <obj_property name="ObjectShortName">kb_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/led" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">led</obj_property>
+      <obj_property name="ObjectShortName">led</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_addr[31:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_addr[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_addr_int" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_addr_int[31:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_addr_int[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_addr_last_lsb" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_addr_last_lsb</obj_property>
+      <obj_property name="ObjectShortName">mch_addr_last_lsb</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_ddr_rd_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_ddr_rd_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_ddr_rd_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_ddr_rd_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_ddr_rd_we</obj_property>
+      <obj_property name="ObjectShortName">mch_ddr_rd_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_ddr_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_ddr_taken</obj_property>
+      <obj_property name="ObjectShortName">mch_ddr_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_ram_rd_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_ram_rd_data[0:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_ram_rd_data[0:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_ram_rd_we" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_ram_rd_we[0:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_ram_rd_we[0:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_ram_taken" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_ram_taken[0:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_ram_taken[0:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_rd_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_rd_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">mch_rd_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_rd_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_rd_we</obj_property>
+      <obj_property name="ObjectShortName">mch_rd_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_read</obj_property>
+      <obj_property name="ObjectShortName">mch_read</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_read_int" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_read_int</obj_property>
+      <obj_property name="ObjectShortName">mch_read_int</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_taken</obj_property>
+      <obj_property name="ObjectShortName">mch_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mch_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mch_valid</obj_property>
+      <obj_property name="ObjectShortName">mch_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_ai_core" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_ai_core[15:0]</obj_property>
+      <obj_property name="ObjectShortName">conf_ai_core[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_ai_int" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_ai_int[15:0]</obj_property>
+      <obj_property name="ObjectShortName">conf_ai_int[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_di_core" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_di_core[7:0]</obj_property>
+      <obj_property name="ObjectShortName">conf_di_core[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_taken</obj_property>
+      <obj_property name="ObjectShortName">conf_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_valid</obj_property>
+      <obj_property name="ObjectShortName">conf_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_wr_1541" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_wr_1541</obj_property>
+      <obj_property name="ObjectShortName">conf_wr_1541</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_wr_core" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_wr_core</obj_property>
+      <obj_property name="ObjectShortName">conf_wr_core</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_write</obj_property>
+      <obj_property name="ObjectShortName">conf_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/conf_write_p" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_write_p</obj_property>
+      <obj_property name="ObjectShortName">conf_write_p</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/media_adr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">media_adr[17:0]</obj_property>
+      <obj_property name="ObjectShortName">media_adr[17:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/media_dat" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">media_dat[7:0]</obj_property>
+      <obj_property name="ObjectShortName">media_dat[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/media_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">media_read</obj_property>
+      <obj_property name="ObjectShortName">media_read</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mode_1541" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mode_1541</obj_property>
+      <obj_property name="ObjectShortName">mode_1541</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/mode_prg" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mode_prg</obj_property>
+      <obj_property name="ObjectShortName">mode_prg</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ms_butn" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ms_butn[2:0]</obj_property>
+      <obj_property name="ObjectShortName">ms_butn[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ms_posx" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ms_posx[11:0]</obj_property>
+      <obj_property name="ObjectShortName">ms_posx[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ms_posy" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ms_posy[11:0]</obj_property>
+      <obj_property name="ObjectShortName">ms_posy[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ms_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ms_we</obj_property>
+      <obj_property name="ObjectShortName">ms_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_audio_bckin" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_audio_bckin</obj_property>
+      <obj_property name="ObjectShortName">o_audio_bckin</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_audio_din" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_audio_din</obj_property>
+      <obj_property name="ObjectShortName">o_audio_din</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_audio_lrcin" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_audio_lrcin</obj_property>
+      <obj_property name="ObjectShortName">o_audio_lrcin</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_audio_mclk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_audio_mclk</obj_property>
+      <obj_property name="ObjectShortName">o_audio_mclk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_clk_68k" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_clk_68k</obj_property>
+      <obj_property name="ObjectShortName">o_clk_68k</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_disk_led" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_disk_led</obj_property>
+      <obj_property name="ObjectShortName">o_disk_led</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_addr[14:0]</obj_property>
+      <obj_property name="ObjectShortName">o_mem_addr[14:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_cas" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_cas</obj_property>
+      <obj_property name="ObjectShortName">o_mem_cas</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_cke" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_cke</obj_property>
+      <obj_property name="ObjectShortName">o_mem_cke</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_clk_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_clk_n</obj_property>
+      <obj_property name="ObjectShortName">o_mem_clk_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_clk_p" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_clk_p</obj_property>
+      <obj_property name="ObjectShortName">o_mem_clk_p</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_cs" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_cs</obj_property>
+      <obj_property name="ObjectShortName">o_mem_cs</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_ldm" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_ldm</obj_property>
+      <obj_property name="ObjectShortName">o_mem_ldm</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_ras" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_ras</obj_property>
+      <obj_property name="ObjectShortName">o_mem_ras</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_udm" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_udm</obj_property>
+      <obj_property name="ObjectShortName">o_mem_udm</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_mem_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_mem_we</obj_property>
+      <obj_property name="ObjectShortName">o_mem_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_pwr_led" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_pwr_led</obj_property>
+      <obj_property name="ObjectShortName">o_pwr_led</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_rs232_rts" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_rs232_rts</obj_property>
+      <obj_property name="ObjectShortName">o_rs232_rts</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_rs232_txd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_rs232_txd</obj_property>
+      <obj_property name="ObjectShortName">o_rs232_txd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_ssc_rd" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ssc_rd</obj_property>
+      <obj_property name="ObjectShortName">o_ssc_rd</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_clk_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_clk_n</obj_property>
+      <obj_property name="ObjectShortName">o_video_clk_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_clk_p" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_clk_p</obj_property>
+      <obj_property name="ObjectShortName">o_video_clk_p</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_data[11:0]</obj_property>
+      <obj_property name="ObjectShortName">o_video_data[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_de" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_de</obj_property>
+      <obj_property name="ObjectShortName">o_video_de</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_h" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_h</obj_property>
+      <obj_property name="ObjectShortName">o_video_h</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_hsync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_hsync</obj_property>
+      <obj_property name="ObjectShortName">o_video_hsync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_rst_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_rst_l</obj_property>
+      <obj_property name="ObjectShortName">o_video_rst_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_v" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_v</obj_property>
+      <obj_property name="ObjectShortName">o_video_v</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/o_video_vsync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_vsync</obj_property>
+      <obj_property name="ObjectShortName">o_video_vsync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/phy_audio_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">phy_audio_taken</obj_property>
+      <obj_property name="ObjectShortName">phy_audio_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ps2a_drive_clk_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ps2a_drive_clk_low</obj_property>
+      <obj_property name="ObjectShortName">ps2a_drive_clk_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ps2a_drive_data_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ps2a_drive_data_low</obj_property>
+      <obj_property name="ObjectShortName">ps2a_drive_data_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ps2b_drive_clk_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ps2b_drive_clk_low</obj_property>
+      <obj_property name="ObjectShortName">ps2b_drive_clk_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ps2b_drive_data_low" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ps2b_drive_data_low</obj_property>
+      <obj_property name="ObjectShortName">ps2b_drive_data_low</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_addr[24:2]</obj_property>
+      <obj_property name="ObjectShortName">ram_addr[24:2]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ram_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_data[63:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_data[63:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ram_r_w_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_r_w_l</obj_property>
+      <obj_property name="ObjectShortName">ram_r_w_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/ram_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_valid</obj_property>
+      <obj_property name="ObjectShortName">ram_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_aud" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_aud</obj_property>
+      <obj_property name="ObjectShortName">rst_aud</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_capture" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_capture</obj_property>
+      <obj_property name="ObjectShortName">rst_capture</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_ctl" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_ctl</obj_property>
+      <obj_property name="ObjectShortName">rst_ctl</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_ctl_hard" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_ctl_hard</obj_property>
+      <obj_property name="ObjectShortName">rst_ctl_hard</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_ram" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_ram</obj_property>
+      <obj_property name="ObjectShortName">rst_ram</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_soft" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_soft</obj_property>
+      <obj_property name="ObjectShortName">rst_soft</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_sys" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_sys</obj_property>
+      <obj_property name="ObjectShortName">rst_sys</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_vid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_vid</obj_property>
+      <obj_property name="ObjectShortName">rst_vid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/rst_vid_hard" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_vid_hard</obj_property>
+      <obj_property name="ObjectShortName">rst_vid_hard</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/spi_fileio_cs_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_fileio_cs_l</obj_property>
+      <obj_property name="ObjectShortName">spi_fileio_cs_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/spi_fileio_miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_fileio_miso</obj_property>
+      <obj_property name="ObjectShortName">spi_fileio_miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/spi_syscon_cs_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_syscon_cs_l</obj_property>
+      <obj_property name="ObjectShortName">spi_syscon_cs_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/spi_syscon_miso" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">spi_syscon_miso</obj_property>
+      <obj_property name="ObjectShortName">spi_syscon_miso</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/syscon_vid_rgb" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">syscon_vid_rgb[23:0]</obj_property>
+      <obj_property name="ObjectShortName">syscon_vid_rgb[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/syscon_vid_sync" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">syscon_vid_sync</obj_property>
+      <obj_property name="ObjectShortName">syscon_vid_sync</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/tick" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">tick</obj_property>
+      <obj_property name="ObjectShortName">tick</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/tick_ctl_100us" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">tick_ctl_100us</obj_property>
+      <obj_property name="ObjectShortName">tick_ctl_100us</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/tick_ctl_1us" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">tick_ctl_1us</obj_property>
+      <obj_property name="ObjectShortName">tick_ctl_1us</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/tick_pre1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">tick_pre1</obj_property>
+      <obj_property name="ObjectShortName">tick_pre1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/writeprotn_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">writeprotn_s</obj_property>
+      <obj_property name="ObjectShortName">writeprotn_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider65" type="divider">
+      <obj_property name="label">DDR</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_clk_ram" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_clk_ram</obj_property>
+      <obj_property name="ObjectShortName">i_clk_ram</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_clk_ram_90" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_clk_ram_90</obj_property>
+      <obj_property name="ObjectShortName">i_clk_ram_90</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_rst_ram" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_rst_ram</obj_property>
+      <obj_property name="ObjectShortName">i_rst_ram</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_clk_capture" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_clk_capture</obj_property>
+      <obj_property name="ObjectShortName">i_clk_capture</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_rst_capture" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_rst_capture</obj_property>
+      <obj_property name="ObjectShortName">i_rst_capture</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_clk_sys" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_clk_sys</obj_property>
+      <obj_property name="ObjectShortName">i_clk_sys</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_ena_sys" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_ena_sys</obj_property>
+      <obj_property name="ObjectShortName">i_ena_sys</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_ena_sys_c1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_ena_sys_c1</obj_property>
+      <obj_property name="ObjectShortName">i_ena_sys_c1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_rst_sys" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_rst_sys</obj_property>
+      <obj_property name="ObjectShortName">i_rst_sys</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_ba" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_ba[1:0]</obj_property>
+      <obj_property name="ObjectShortName">o_ram_ba[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_addr[12:0]</obj_property>
+      <obj_property name="ObjectShortName">o_ram_addr[12:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_cs_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_cs_l</obj_property>
+      <obj_property name="ObjectShortName">o_ram_cs_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_we_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_we_l</obj_property>
+      <obj_property name="ObjectShortName">o_ram_we_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_ras_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_ras_l</obj_property>
+      <obj_property name="ObjectShortName">o_ram_ras_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_cas_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_cas_l</obj_property>
+      <obj_property name="ObjectShortName">o_ram_cas_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_dm_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_dm_l[1:0]</obj_property>
+      <obj_property name="ObjectShortName">o_ram_dm_l[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/b_ram_dqs" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">b_ram_dqs[1:0]</obj_property>
+      <obj_property name="ObjectShortName">b_ram_dqs[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/b_ram_dq" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">b_ram_dq[15:0]</obj_property>
+      <obj_property name="ObjectShortName">b_ram_dq[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_cke" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_cke</obj_property>
+      <obj_property name="ObjectShortName">o_ram_cke</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_ck_p" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_ck_p</obj_property>
+      <obj_property name="ObjectShortName">o_ram_ck_p</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_ram_ck_n" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_ram_ck_n</obj_property>
+      <obj_property name="ObjectShortName">o_ram_ck_n</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_cfg_cal_sel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_cfg_cal_sel[1:0]</obj_property>
+      <obj_property name="ObjectShortName">i_cfg_cal_sel[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_cfg_ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_cfg_ready</obj_property>
+      <obj_property name="ObjectShortName">o_cfg_ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_cfg_present" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_cfg_present</obj_property>
+      <obj_property name="ObjectShortName">o_cfg_present</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_hp_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_hp_valid</obj_property>
+      <obj_property name="ObjectShortName">i_hp_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_hp_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_hp_taken</obj_property>
+      <obj_property name="ObjectShortName">o_hp_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_hp_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_hp_addr[25:2]</obj_property>
+      <obj_property name="ObjectShortName">i_hp_addr[25:2]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_hp_rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_hp_rw_l</obj_property>
+      <obj_property name="ObjectShortName">i_hp_rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_hp_w_be" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_hp_w_be[3:0]</obj_property>
+      <obj_property name="ObjectShortName">i_hp_w_be[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_hp_w_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_hp_w_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">i_hp_w_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_hp_r_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_hp_r_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">o_hp_r_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_hp_r_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_hp_r_we</obj_property>
+      <obj_property name="ObjectShortName">o_hp_r_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_lp_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_lp_valid</obj_property>
+      <obj_property name="ObjectShortName">i_lp_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_lp_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_lp_taken</obj_property>
+      <obj_property name="ObjectShortName">o_lp_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_lp_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_lp_addr[25:0]</obj_property>
+      <obj_property name="ObjectShortName">i_lp_addr[25:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_lp_rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_lp_rw_l</obj_property>
+      <obj_property name="ObjectShortName">i_lp_rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/i_lp_w_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_lp_w_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">i_lp_w_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_lp_r_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_lp_r_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">o_lp_r_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/o_lp_r_we" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_lp_r_we</obj_property>
+      <obj_property name="ObjectShortName">o_lp_r_we</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/ena_sys_t1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sys_t1</obj_property>
+      <obj_property name="ObjectShortName">ena_sys_t1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/ena_sys_t2" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sys_t2</obj_property>
+      <obj_property name="ObjectShortName">ena_sys_t2</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/ena_sys_t3" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_sys_t3</obj_property>
+      <obj_property name="ObjectShortName">ena_sys_t3</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/hp_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_valid</obj_property>
+      <obj_property name="ObjectShortName">hp_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/hp_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_addr[25:2]</obj_property>
+      <obj_property name="ObjectShortName">hp_addr[25:2]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/hp_rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_rw_l</obj_property>
+      <obj_property name="ObjectShortName">hp_rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/hp_w_be" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_w_be[3:0]</obj_property>
+      <obj_property name="ObjectShortName">hp_w_be[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/hp_w_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">hp_w_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">hp_w_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/lp_valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_valid</obj_property>
+      <obj_property name="ObjectShortName">lp_valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/lp_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_addr[25:2]</obj_property>
+      <obj_property name="ObjectShortName">lp_addr[25:2]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/lp_r_sel" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_r_sel[1:0]</obj_property>
+      <obj_property name="ObjectShortName">lp_r_sel[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/lp_rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_rw_l</obj_property>
+      <obj_property name="ObjectShortName">lp_rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/lp_w_be" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_w_be[3:0]</obj_property>
+      <obj_property name="ObjectShortName">lp_w_be[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/lp_w_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_w_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">lp_w_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/phase" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">phase[3:0]</obj_property>
+      <obj_property name="ObjectShortName">phase[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/start_a" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">start_a</obj_property>
+      <obj_property name="ObjectShortName">start_a</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/start_b" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">start_b</obj_property>
+      <obj_property name="ObjectShortName">start_b</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/cur_hp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cur_hp</obj_property>
+      <obj_property name="ObjectShortName">cur_hp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/cur_lp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cur_lp</obj_property>
+      <obj_property name="ObjectShortName">cur_lp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/cur_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cur_read</obj_property>
+      <obj_property name="ObjectShortName">cur_read</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/ref_req_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ref_req_in</obj_property>
+      <obj_property name="ObjectShortName">ref_req_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/ref_req" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ref_req</obj_property>
+      <obj_property name="ObjectShortName">ref_req</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/sys_taken_meta1" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sys_taken_meta1</obj_property>
+      <obj_property name="ObjectShortName">sys_taken_meta1</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/sys_taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sys_taken</obj_property>
+      <obj_property name="ObjectShortName">sys_taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/sys_cur_hp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sys_cur_hp</obj_property>
+      <obj_property name="ObjectShortName">sys_cur_hp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/sys_cur_lp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sys_cur_lp</obj_property>
+      <obj_property name="ObjectShortName">sys_cur_lp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/sys_cur_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sys_cur_read</obj_property>
+      <obj_property name="ObjectShortName">sys_cur_read</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/ready" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ready</obj_property>
+      <obj_property name="ObjectShortName">ready</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">addr[23:0]</obj_property>
+      <obj_property name="ObjectShortName">addr[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rw_l</obj_property>
+      <obj_property name="ObjectShortName">rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/w_be" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">w_be[3:0]</obj_property>
+      <obj_property name="ObjectShortName">w_be[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/w_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">w_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">w_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/valid" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">valid</obj_property>
+      <obj_property name="ObjectShortName">valid</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/valid_hp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">valid_hp</obj_property>
+      <obj_property name="ObjectShortName">valid_hp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/taken" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">taken</obj_property>
+      <obj_property name="ObjectShortName">taken</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/r_buf_ena" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_buf_ena</obj_property>
+      <obj_property name="ObjectShortName">r_buf_ena</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/r_buf_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_buf_addr[3:0]</obj_property>
+      <obj_property name="ObjectShortName">r_buf_addr[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/r_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">r_data[31:0]</obj_property>
+      <obj_property name="ObjectShortName">r_data[31:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/r_load_hp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_load_hp</obj_property>
+      <obj_property name="ObjectShortName">r_load_hp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/r_we_hp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_we_hp</obj_property>
+      <obj_property name="ObjectShortName">r_we_hp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/r_we_lp" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">r_we_lp</obj_property>
+      <obj_property name="ObjectShortName">r_we_lp</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_DDRCtrl/g_lp_big_endian" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">g_lp_big_endian</obj_property>
+      <obj_property name="ObjectShortName">g_lp_big_endian</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider300" type="divider">
+      <obj_property name="label">VIC-20</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_sysclk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_sysclk</obj_property>
+      <obj_property name="ObjectShortName">i_sysclk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_sysclk_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_sysclk_en</obj_property>
+      <obj_property name="ObjectShortName">i_sysclk_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_reset" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_reset</obj_property>
+      <obj_property name="ObjectShortName">i_reset</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/atn_o" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">atn_o</obj_property>
+      <obj_property name="ObjectShortName">atn_o</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/atn_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">atn_i</obj_property>
+      <obj_property name="ObjectShortName">atn_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/clk_o" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_o</obj_property>
+      <obj_property name="ObjectShortName">clk_o</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/clk_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_i</obj_property>
+      <obj_property name="ObjectShortName">clk_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/data_o" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">data_o</obj_property>
+      <obj_property name="ObjectShortName">data_o</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/data_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">data_i</obj_property>
+      <obj_property name="ObjectShortName">data_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_joy" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_joy[3:0]</obj_property>
+      <obj_property name="ObjectShortName">i_joy[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_fire" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_fire</obj_property>
+      <obj_property name="ObjectShortName">i_fire</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_cart_en" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_cart_en</obj_property>
+      <obj_property name="ObjectShortName">i_cart_en</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_cart_ro" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_cart_ro</obj_property>
+      <obj_property name="ObjectShortName">i_cart_ro</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_ram_ext" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_ram_ext[3:0]</obj_property>
+      <obj_property name="ObjectShortName">i_ram_ext[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_video_r" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_r[3:0]</obj_property>
+      <obj_property name="ObjectShortName">o_video_r[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_video_g" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_g[3:0]</obj_property>
+      <obj_property name="ObjectShortName">o_video_g[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_video_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_video_b[3:0]</obj_property>
+      <obj_property name="ObjectShortName">o_video_b[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_hsync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_hsync</obj_property>
+      <obj_property name="ObjectShortName">o_hsync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_vsync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_vsync</obj_property>
+      <obj_property name="ObjectShortName">o_vsync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_de" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_de</obj_property>
+      <obj_property name="ObjectShortName">o_de</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_matrix_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_matrix_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">o_matrix_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_matrix_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_matrix_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">i_matrix_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_restore_out" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">i_restore_out</obj_property>
+      <obj_property name="ObjectShortName">i_restore_out</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_audio" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_audio[15:0]</obj_property>
+      <obj_property name="ObjectShortName">o_audio[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_extmem_sel" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_extmem_sel</obj_property>
+      <obj_property name="ObjectShortName">o_extmem_sel</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_extmem_r_wn" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">o_extmem_r_wn</obj_property>
+      <obj_property name="ObjectShortName">o_extmem_r_wn</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_extmem_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_extmem_addr[15:0]</obj_property>
+      <obj_property name="ObjectShortName">o_extmem_addr[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/i_extmem_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">i_extmem_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">i_extmem_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/o_extmem_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">o_extmem_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">o_extmem_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/debug" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">debug[32:0]</obj_property>
+      <obj_property name="ObjectShortName">debug[32:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/debugi" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">debugi[2:0]</obj_property>
+      <obj_property name="ObjectShortName">debugi[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/conf_wr" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_wr</obj_property>
+      <obj_property name="ObjectShortName">conf_wr</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/conf_ai" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_ai[15:0]</obj_property>
+      <obj_property name="ObjectShortName">conf_ai[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/conf_di" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">conf_di[7:0]</obj_property>
+      <obj_property name="ObjectShortName">conf_di[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/reset_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_l</obj_property>
+      <obj_property name="ObjectShortName">reset_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ena_4" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_4</obj_property>
+      <obj_property name="ObjectShortName">ena_4</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/reset_l_sampled" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">reset_l_sampled</obj_property>
+      <obj_property name="ObjectShortName">reset_l_sampled</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_ena" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">c_ena</obj_property>
+      <obj_property name="ObjectShortName">c_ena</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">c_addr[23:0]</obj_property>
+      <obj_property name="ObjectShortName">c_addr[23:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_din" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">c_din[7:0]</obj_property>
+      <obj_property name="ObjectShortName">c_din[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">c_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">c_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">c_rw_l</obj_property>
+      <obj_property name="ObjectShortName">c_rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_irq_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">c_irq_l</obj_property>
+      <obj_property name="ObjectShortName">c_irq_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/c_nmi_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">c_nmi_l</obj_property>
+      <obj_property name="ObjectShortName">c_nmi_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/io_sel_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">io_sel_l[3:0]</obj_property>
+      <obj_property name="ObjectShortName">io_sel_l[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/blk_sel_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">blk_sel_l[7:0]</obj_property>
+      <obj_property name="ObjectShortName">blk_sel_l[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ram_sel_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram_sel_l[7:0]</obj_property>
+      <obj_property name="ObjectShortName">ram_sel_l[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/vic_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">vic_addr[13:0]</obj_property>
+      <obj_property name="ObjectShortName">vic_addr[13:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/vic_oe_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">vic_oe_l</obj_property>
+      <obj_property name="ObjectShortName">vic_oe_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/vic_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">vic_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">vic_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/vic_din" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">vic_din[11:0]</obj_property>
+      <obj_property name="ObjectShortName">vic_din[11:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/p2_h" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">p2_h</obj_property>
+      <obj_property name="ObjectShortName">p2_h</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ena_1mhz" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ena_1mhz</obj_property>
+      <obj_property name="ObjectShortName">ena_1mhz</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/via1_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">via1_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">via1_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/via2_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">via2_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">via2_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/vic_audio" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">vic_audio[5:0]</obj_property>
+      <obj_property name="ObjectShortName">vic_audio[5:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/lp_output" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_output[15:0]</obj_property>
+      <obj_property name="ObjectShortName">lp_output[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/lp_filtered" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lp_filtered[15:0]</obj_property>
+      <obj_property name="ObjectShortName">lp_filtered[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/v_addr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">v_addr[13:0]</obj_property>
+      <obj_property name="ObjectShortName">v_addr[13:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/v_data" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">v_data[7:0]</obj_property>
+      <obj_property name="ObjectShortName">v_data[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/v_data_oe_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">v_data_oe_l</obj_property>
+      <obj_property name="ObjectShortName">v_data_oe_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/v_data_read_mux" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">v_data_read_mux[7:0]</obj_property>
+      <obj_property name="ObjectShortName">v_data_read_mux[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/v_data_read_muxr" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">v_data_read_muxr[7:0]</obj_property>
+      <obj_property name="ObjectShortName">v_data_read_muxr[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/v_rw_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">v_rw_l</obj_property>
+      <obj_property name="ObjectShortName">v_rw_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/col_ram_sel_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">col_ram_sel_l</obj_property>
+      <obj_property name="ObjectShortName">col_ram_sel_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ram0_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram0_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">ram0_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ram45_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram45_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">ram45_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ram67_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram67_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">ram67_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/col_ram_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">col_ram_dout[3:0]</obj_property>
+      <obj_property name="ObjectShortName">col_ram_dout[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ram1_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram1_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">ram1_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ram23_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">ram23_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">ram23_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/extmem_8" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_8[7:0]</obj_property>
+      <obj_property name="ObjectShortName">extmem_8[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/extmem_16" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_16[7:0]</obj_property>
+      <obj_property name="ObjectShortName">extmem_16[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/extmem_24" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem_24[7:0]</obj_property>
+      <obj_property name="ObjectShortName">extmem_24[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/char_rom_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">char_rom_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">char_rom_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/basic_rom_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">basic_rom_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">basic_rom_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/kernal_rom_dout" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">kernal_rom_dout[7:0]</obj_property>
+      <obj_property name="ObjectShortName">kernal_rom_dout[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/expansion_din" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">expansion_din[7:0]</obj_property>
+      <obj_property name="ObjectShortName">expansion_din[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/expansion_nmi_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">expansion_nmi_l</obj_property>
+      <obj_property name="ObjectShortName">expansion_nmi_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/expansion_irq_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">expansion_irq_l</obj_property>
+      <obj_property name="ObjectShortName">expansion_irq_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/via1_nmi_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">via1_nmi_l</obj_property>
+      <obj_property name="ObjectShortName">via1_nmi_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/via1_pa_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">via1_pa_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">via1_pa_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/via1_pa_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">via1_pa_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">via1_pa_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/via2_irq_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">via2_irq_l</obj_property>
+      <obj_property name="ObjectShortName">via2_irq_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/cass_write" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cass_write</obj_property>
+      <obj_property name="ObjectShortName">cass_write</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/cass_read" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cass_read</obj_property>
+      <obj_property name="ObjectShortName">cass_read</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/cass_motor" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cass_motor</obj_property>
+      <obj_property name="ObjectShortName">cass_motor</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/cass_sw" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">cass_sw</obj_property>
+      <obj_property name="ObjectShortName">cass_sw</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/keybd_col_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">keybd_col_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">keybd_col_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/keybd_col_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">keybd_col_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">keybd_col_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/keybd_col_oe_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">keybd_col_oe_l[7:0]</obj_property>
+      <obj_property name="ObjectShortName">keybd_col_oe_l[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/keybd_row_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">keybd_row_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">keybd_row_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/keybd_restore" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">keybd_restore</obj_property>
+      <obj_property name="ObjectShortName">keybd_restore</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/joy" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">joy[3:0]</obj_property>
+      <obj_property name="ObjectShortName">joy[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/light_pen" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">light_pen</obj_property>
+      <obj_property name="ObjectShortName">light_pen</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_srq_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_srq_in</obj_property>
+      <obj_property name="ObjectShortName">serial_srq_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_atn_out_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_atn_out_l</obj_property>
+      <obj_property name="ObjectShortName">serial_atn_out_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_atn_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_atn_in</obj_property>
+      <obj_property name="ObjectShortName">serial_atn_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_clk_out_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_clk_out_l</obj_property>
+      <obj_property name="ObjectShortName">serial_clk_out_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_clk_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_clk_in</obj_property>
+      <obj_property name="ObjectShortName">serial_clk_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_data_out_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_data_out_l</obj_property>
+      <obj_property name="ObjectShortName">serial_data_out_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/serial_data_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">serial_data_in</obj_property>
+      <obj_property name="ObjectShortName">serial_data_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_cb1_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_cb1_in</obj_property>
+      <obj_property name="ObjectShortName">user_port_cb1_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_cb1_out" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_cb1_out</obj_property>
+      <obj_property name="ObjectShortName">user_port_cb1_out</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_cb1_oe_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_cb1_oe_l</obj_property>
+      <obj_property name="ObjectShortName">user_port_cb1_oe_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_cb2_in" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_cb2_in</obj_property>
+      <obj_property name="ObjectShortName">user_port_cb2_in</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_cb2_out" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_cb2_out</obj_property>
+      <obj_property name="ObjectShortName">user_port_cb2_out</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_cb2_oe_l" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_cb2_oe_l</obj_property>
+      <obj_property name="ObjectShortName">user_port_cb2_oe_l</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_in" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_in[7:0]</obj_property>
+      <obj_property name="ObjectShortName">user_port_in[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_out" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_out[7:0]</obj_property>
+      <obj_property name="ObjectShortName">user_port_out[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/user_port_oe_l" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">user_port_oe_l[7:0]</obj_property>
+      <obj_property name="ObjectShortName">user_port_oe_l[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/sw_reg" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sw_reg[3:0]</obj_property>
+      <obj_property name="ObjectShortName">sw_reg[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/extmem" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">extmem</obj_property>
+      <obj_property name="ObjectShortName">extmem</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/video_r" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">video_r[3:0]</obj_property>
+      <obj_property name="ObjectShortName">video_r[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/video_g" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">video_g[3:0]</obj_property>
+      <obj_property name="ObjectShortName">video_g[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/video_b" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">video_b[3:0]</obj_property>
+      <obj_property name="ObjectShortName">video_b[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/hsync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">hsync</obj_property>
+      <obj_property name="ObjectShortName">hsync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/vsync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">vsync</obj_property>
+      <obj_property name="ObjectShortName">vsync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/csync" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">csync</obj_property>
+      <obj_property name="ObjectShortName">csync</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/de" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">de</obj_property>
+      <obj_property name="ObjectShortName">de</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/ext_dla_cpu_debug" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">ext_dla_cpu_debug</obj_property>
+      <obj_property name="ObjectShortName">ext_dla_cpu_debug</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/k_offset" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">k_offset[4:0]</obj_property>
+      <obj_property name="ObjectShortName">k_offset[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/disable_24k" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">disable_24k</obj_property>
+      <obj_property name="ObjectShortName">disable_24k</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/disable_16k" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">disable_16k</obj_property>
+      <obj_property name="ObjectShortName">disable_16k</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/vic20/cartridge_4k" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">cartridge_4k</obj_property>
+      <obj_property name="ObjectShortName">cartridge_4k</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="divider65" type="divider">
+      <obj_property name="label">FLOPPY</obj_property>
+      <obj_property name="DisplayName">label</obj_property>
+      <obj_property name="BkColor">128 128 255</obj_property>
+      <obj_property name="TextColor">230 230 230</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/clk_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_i</obj_property>
+      <obj_property name="ObjectShortName">clk_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/clk_en4_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk_en4_i</obj_property>
+      <obj_property name="ObjectShortName">clk_en4_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/rst_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst_i</obj_property>
+      <obj_property name="ObjectShortName">rst_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/floppy_avail_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">floppy_avail_i</obj_property>
+      <obj_property name="ObjectShortName">floppy_avail_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/motor_on_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">motor_on_i</obj_property>
+      <obj_property name="ObjectShortName">motor_on_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/mode_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">mode_i</obj_property>
+      <obj_property name="ObjectShortName">mode_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/write_prot_ni" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">write_prot_ni</obj_property>
+      <obj_property name="ObjectShortName">write_prot_ni</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/step_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">step_i[1:0]</obj_property>
+      <obj_property name="ObjectShortName">step_i[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/soe_i" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">soe_i</obj_property>
+      <obj_property name="ObjectShortName">soe_i</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/rate_ctrl_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">rate_ctrl_i[1:0]</obj_property>
+      <obj_property name="ObjectShortName">rate_ctrl_i[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/byte_ready_o" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">byte_ready_o</obj_property>
+      <obj_property name="ObjectShortName">byte_ready_o</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/sync_o" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sync_o</obj_property>
+      <obj_property name="ObjectShortName">sync_o</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_data_o" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_data_o[7:0]</obj_property>
+      <obj_property name="ObjectShortName">gcr_data_o[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/debug_o" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">debug_o[34:0]</obj_property>
+      <obj_property name="ObjectShortName">debug_o[34:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/track_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">track_s[8:0]</obj_property>
+      <obj_property name="ObjectShortName">track_s[8:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/new_track_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">new_track_s</obj_property>
+      <obj_property name="ObjectShortName">new_track_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/region_lut_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">region_lut_s[41:0]</obj_property>
+      <obj_property name="ObjectShortName">region_lut_s[41:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/region_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">region_s[1:0]</obj_property>
+      <obj_property name="ObjectShortName">region_s[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/sector_lut_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sector_lut_s[3:0]</obj_property>
+      <obj_property name="ObjectShortName">sector_lut_s[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/sectors_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sectors_s[4:0]</obj_property>
+      <obj_property name="ObjectShortName">sectors_s[4:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/sector_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">sector_s[7:0]</obj_property>
+      <obj_property name="ObjectShortName">sector_s[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/data_crc_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">data_crc_s[7:0]</obj_property>
+      <obj_property name="ObjectShortName">data_crc_s[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/bit_time_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">bit_time_s[1:0]</obj_property>
+      <obj_property name="ObjectShortName">bit_time_s[1:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/bit_timer_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">bit_timer_s[3:0]</obj_property>
+      <obj_property name="ObjectShortName">bit_timer_s[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/bit_square_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">bit_square_s</obj_property>
+      <obj_property name="ObjectShortName">bit_square_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/bit_tick_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">bit_tick_s</obj_property>
+      <obj_property name="ObjectShortName">bit_tick_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_shifter_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_shifter_s[17:0]</obj_property>
+      <obj_property name="ObjectShortName">gcr_shifter_s[17:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_bitcnt_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_bitcnt_s[2:0]</obj_property>
+      <obj_property name="ObjectShortName">gcr_bitcnt_s[2:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_nextbyte_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_nextbyte_s</obj_property>
+      <obj_property name="ObjectShortName">gcr_nextbyte_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_cnt10_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_cnt10_s[3:0]</obj_property>
+      <obj_property name="ObjectShortName">gcr_cnt10_s[3:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_nextgbyte_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_nextgbyte_s</obj_property>
+      <obj_property name="ObjectShortName">gcr_nextgbyte_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/sync_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sync_s</obj_property>
+      <obj_property name="ObjectShortName">sync_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/byte_ready_s" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">byte_ready_s</obj_property>
+      <obj_property name="ObjectShortName">byte_ready_s</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/sync_as" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">sync_as</obj_property>
+      <obj_property name="ObjectShortName">sync_as</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/byte_ready_as" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">byte_ready_as</obj_property>
+      <obj_property name="ObjectShortName">byte_ready_as</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_shiftin_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_shiftin_s[9:0]</obj_property>
+      <obj_property name="ObjectShortName">gcr_shiftin_s[9:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/gcr_data_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">gcr_data_s[9:0]</obj_property>
+      <obj_property name="ObjectShortName">gcr_data_s[9:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/track_cnt_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">track_cnt_s[7:0]</obj_property>
+      <obj_property name="ObjectShortName">track_cnt_s[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/trackstate_s" type="other" db_ref_id="1">
+      <obj_property name="ElementShortName">trackstate_s</obj_property>
+      <obj_property name="ObjectShortName">trackstate_s</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/nib2gcr_lut_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">nib2gcr_lut_s[15:0]</obj_property>
+      <obj_property name="ObjectShortName">nib2gcr_lut_s[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/start_adr_lut_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">start_adr_lut_s[0:41]</obj_property>
+      <obj_property name="ObjectShortName">start_adr_lut_s[0:41]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/bin_data_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">bin_data_s[7:0]</obj_property>
+      <obj_property name="ObjectShortName">bin_data_s[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/media_adr_s" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">media_adr_s[17:0]</obj_property>
+      <obj_property name="ObjectShortName">media_adr_s[17:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/diskid_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">diskid_i[15:0]</obj_property>
+      <obj_property name="ObjectShortName">diskid_i[15:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/media_read_o" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">media_read_o</obj_property>
+      <obj_property name="ObjectShortName">media_read_o</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/media_adr_o" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">media_adr_o[17:0]</obj_property>
+      <obj_property name="ObjectShortName">media_adr_o[17:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/replay_tb/u_Replay/u_Core/c1541/disk_stream/media_dat_i" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">media_dat_i[7:0]</obj_property>
+      <obj_property name="ObjectShortName">media_dat_i[7:0]</obj_property>
+      <obj_property name="Radix">HEXRADIX</obj_property>
+   </wvobject>
+</wave_config>
Index: unmerged/changes_mcc_to_mist_summary
===================================================================
--- unmerged/changes_mcc_to_mist_summary	(nonexistent)
+++ unmerged/changes_mcc_to_mist_summary	(revision 1)
@@ -0,0 +1,40 @@
+diff -ur atari800core_v1_20140121_mcc216/address_decoder.vhdl atari800core_v1_20140312_mist/address_decoder.vhdl
+Only in atari800core_v1_20140312_mist/: atari800core_assignment_defaults.qdf
+diff -ur atari800core_v1_20140121_mcc216/atari800core.jdi atari800core_v1_20140312_mist/atari800core.jdi
+diff -ur atari800core_v1_20140121_mcc216/atari800core.qsf atari800core_v1_20140312_mist/atari800core.qsf
+Binary files atari800core_v1_20140121_mcc216/atari800core.qws and atari800core_v1_20140312_mist/atari800core.qws differ
+diff -ur atari800core_v1_20140121_mcc216/atari800core.sdc atari800core_v1_20140312_mist/atari800core.sdc
+diff -ur atari800core_v1_20140121_mcc216/atari800core.vhd atari800core_v1_20140312_mist/atari800core.vhd
+Only in atari800core_v1_20140312_mist/: ataribas.mif
+Only in atari800core_v1_20140312_mist/: basic.cmp
+Only in atari800core_v1_20140312_mist/: basic.qip
+Only in atari800core_v1_20140312_mist/: basic.vhd
+Only in atari800core_v1_20140312_mist/: covox.vhd
+Only in atari800core_v1_20140312_mist/: covox.vhd.bak
+Only in atari800core_v1_20140312_mist/: custom_io.vhd
+Only in atari800core_v1_20140312_mist/: data_io.v~
+Only in atari800core_v1_20140312_mist/: data_io.vhdl
+Only in atari800core_v1_20140312_mist/: data_io.vhdl.bak
+Only in atari800core_v1_20140312_mist/: generic_ram_infer.vhdl
+Only in atari800core_v1_20140312_mist/: generic_ram_infer.vhdl.bak
+diff -ur atari800core_v1_20140121_mcc216/internalromram.vhd atari800core_v1_20140312_mist/internalromram.vhd
+Only in atari800core_v1_20140312_mist/: mist_sector_buffer.cmp
+Only in atari800core_v1_20140312_mist/: mist_sector_buffer.qip
+Only in atari800core_v1_20140312_mist/: mist_sector_buffer.vhd
+Only in atari800core_v1_20140312_mist/: os16.mif
+Only in atari800core_v1_20140312_mist/: output_file.rbf
+diff -ur atari800core_v1_20140121_mcc216/pll.bsf atari800core_v1_20140312_mist/pll.bsf
+diff -ur atari800core_v1_20140121_mcc216/PLLJ_PLLSPE_INFO.txt atari800core_v1_20140312_mist/PLLJ_PLLSPE_INFO.txt
+diff -ur atari800core_v1_20140121_mcc216/pll.vhd atari800core_v1_20140312_mist/pll.vhd
+diff -ur atari800core_v1_20140121_mcc216/pokey_mixer.vhdl atari800core_v1_20140312_mist/pokey_mixer.vhdl
+Only in atari800core_v1_20140312_mist/: pokey_mixer.vhdl.bak
+Only in atari800core_v1_20140312_mist/: rom16.cmp
+Only in atari800core_v1_20140312_mist/: rom16.qip
+Only in atari800core_v1_20140312_mist/: rom16.vhd
+diff -ur atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl atari800core_v1_20140312_mist/sdram_statemachine.vhdl
+Only in atari800core_v1_20140312_mist/: stp1.stp
+Only in atari800core_v1_20140312_mist/: user_io.v
+Only in atari800core_v1_20140312_mist/: user_io.v.bak
+diff -ur atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif atari800core_v1_20140312_mist/zpu/HelloTinyROM_ROM.mif
+diff -ur atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl atari800core_v1_20140312_mist/zpu_config_regs.vhdl
+diff -ur atari800core_v1_20140121_mcc216/zpu_glue.vhdl atari800core_v1_20140312_mist/zpu_glue.vhdl
Index: unmerged/core/de1/antic.vhdl
===================================================================
--- unmerged/core/de1/antic.vhdl	(nonexistent)
+++ unmerged/core/de1/antic.vhdl	(revision 1)
@@ -0,0 +1,1824 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	MEMORY_READY_ANTIC : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	ANTIC_ENABLE_179 : IN std_logic;
+	
+	PAL : IN STD_LOGIC;
+	
+	lightpen : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	NMI_N_OUT : OUT std_logic;
+	ANTIC_READY : OUT std_logic; -- taken low by wsync writes
+	
+	-- GTIA interface
+	AN : OUT STD_LOGIC_VECTOR(2 downto 0);
+	COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
+	COLOUR_CLOCK_OUT : out std_logic;
+	HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
+	
+	-- DMA fetch
+	dma_fetch_out : out std_logic;
+	dma_address_out : out std_logic_vector(15 downto 0);
+	
+	-- refresh
+	refresh_out : out std_logic; -- used by sdram
+	
+	-- for debugging
+	dma_clock_out : out std_logic
+);
+END antic;
+
+ARCHITECTURE vhdl OF antic IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT antic_dma_clock IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		enable_dma : IN STD_LOGIC;
+		
+		playfield_start : in std_logic;
+		playfield_end : in std_logic;
+		vblank : in std_logic;
+		
+		slow_dma : in std_logic;
+		medium_dma : in std_logic;
+		fast_dma : in std_logic;
+				
+		dma_clock_out_0 : out std_logic;
+		dma_clock_out_1 : out std_logic;
+		dma_clock_out_2 : out std_logic;
+		dma_clock_out_3 : out std_logic
+	);
+	END component;
+	
+	component antic_counter IS
+	generic
+	(
+		STORE_WIDTH : natural := 1;
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+		
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;	
+
+	component reg_file IS
+	generic
+	(
+		BYTES : natural := 1;
+		WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal enable_dma : std_logic;
+	signal dma_clock_character_name : std_logic;
+	signal dma_clock_character_inc : std_logic;
+	signal dma_clock_bitmap_data : std_logic;
+	signal dma_clock_character_data : std_logic;
+	
+	signal wsync_next : std_logic;
+	signal wsync_reg : std_logic;
+	signal wsync_reset : std_logic;
+	signal wsync_write : std_logic;
+	signal wsync_delayed_write : std_logic;
+	
+	signal nmi_next : std_logic;
+	signal nmi_reg : std_logic;
+	
+	signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
+	signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
+	
+	signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
+	signal nmist_reg : std_logic_vector(7 downto 5);
+	
+	signal nmist_reset : std_logic;
+	
+	signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
+	signal nmien_raw_reg : std_logic_vector(7 downto 6);
+	signal nmien_delayed_reg : std_logic_vector(7 downto 6);
+	
+	signal dli_nmi_next : std_logic;
+	signal vbi_nmi_next : std_logic;
+	signal dli_nmi_reg : std_logic;
+	signal vbi_nmi_reg : std_logic;
+	
+	signal nmi_reset : std_logic;
+	--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
+	--signal nmi_pending_reg : std_logic;
+	
+	signal playfield_dma_start : std_logic;
+	signal playfield_dma_end : std_logic;
+	signal playfield_display_active_next : std_logic;
+	signal playfield_display_active_reg : std_logic;
+	
+	signal dmactl_raw_next : std_logic_vector(6 downto 0);
+	signal dmactl_raw_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_enabled : std_logic;
+	
+	signal chactl_next : std_logic_vector(2 downto 0);
+	signal chactl_reg : std_logic_vector(2 downto 0);
+	
+	-- dma is only allowed during certain portions of the display
+	signal allow_real_dma_next : std_logic;
+	signal allow_real_dma_reg : std_logic;
+	
+	-- dma fetch handling
+	-- dma is scheduled one cycle before it happens, so that registers can directly drive output	
+	signal dma_fetch_next : std_logic;
+	signal dma_fetch_reg : std_logic;
+	signal dma_address_next : std_logic_vector(15 downto 0);
+	signal dma_address_reg : std_logic_vector(15 downto 0);
+	
+	constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
+	constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
+	constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
+	constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
+	constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
+	constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
+	signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
+	signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
+	signal dma_fetch_request : std_logic;
+	
+	signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
+	signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
+	
+	signal character_next : std_logic_vector(7 downto 0);
+	signal character_reg : std_logic_vector(7 downto 0);
+
+	signal displayed_character_next : std_logic_vector(7 downto 0);
+	signal displayed_character_reg : std_logic_vector(7 downto 0);
+	
+	-- instruction decode
+	signal instruction_next : std_logic_vector(7 downto 0);
+	signal instruction_reg : std_logic_vector(7 downto 0);
+	
+	signal first_line_of_instruction_next : std_logic;
+	signal first_line_of_instruction_reg: std_logic;
+
+	signal last_line_of_instruction_live : std_logic;
+	signal last_line_of_instruction_next : std_logic;
+	signal last_line_of_instruction_reg: std_logic;
+	
+	signal force_final_row : std_logic;
+	
+	signal instruction_blank_reg : std_logic;
+	signal instruction_blank_next : std_logic;
+
+	--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
+	--signal dma_speed_next : dma_speed_type;
+	--signal dma_speed_reg : dma_speed_type;
+	constant no_dma : std_logic_vector(1 downto 0) := "00";
+	constant slow_dma : std_logic_vector(1 downto 0) := "01";
+	constant medium_dma : std_logic_vector(1 downto 0) := "10";
+	constant fast_dma : std_logic_vector(1 downto 0) := "11";
+	signal dma_speed_next : std_logic_vector(1 downto 0);
+	signal dma_speed_reg : std_logic_vector(1 downto 0);
+	signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
+	
+	--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
+	--signal instruction_type_next : instruction_type;
+	--signal instruction_type_reg : instruction_type;
+	constant mode_character : std_logic_vector(2 downto 0) := "000";
+	constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
+	constant mode_jvb : std_logic_vector(2 downto 0) := "010";
+	constant mode_jump : std_logic_vector(2 downto 0) := "011";
+	constant mode_blank : std_logic_vector(2 downto 0) := "100";
+	signal instruction_type_next : std_logic_vector(2 downto 0);
+	signal instruction_type_reg : std_logic_vector(2 downto 0);
+	
+	signal two_part_instruction_next : std_logic;
+	signal two_part_instruction_reg : std_logic;
+
+		-- e.g. if instruction is 8 lines long then the final row is 7
+	signal instruction_final_row_next : std_logic_vector(3 downto 0);
+	signal instruction_final_row_reg : std_logic_vector(3 downto 0);
+		
+	--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
+	--signal shift_rate_next : shift_rate_type;
+	--signal shift_rate_reg : shift_rate_type;
+	constant slow_shift : std_logic_vector(1 downto 0) := "00";
+	constant medium_shift : std_logic_vector(1 downto 0) := "01";
+	constant fast_shift : std_logic_vector(1 downto 0) := "10";
+	signal shift_rate_next : std_logic_vector(1 downto 0);
+	signal shift_rate_reg : std_logic_vector(1 downto 0);
+	
+	signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
+	signal shift_twobit_reg : std_logic;
+	
+	signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
+	signal twopixel_reg : std_logic;	
+	
+	signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
+	signal single_colour_character_reg : std_logic;
+
+	signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
+	signal multi_colour_character_reg : std_logic;
+	
+	signal twoline_character_next : std_logic; -- for antic 5/7
+	signal twoline_character_reg : std_logic;
+	
+	signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
+	signal map_background_reg : std_logic;
+	
+	signal dli_enabled_next : std_logic;
+	signal dli_enabled_reg : std_logic;
+	
+	signal descenders_next : std_logic; -- for mode 3
+	signal descenders_reg : std_logic;
+		
+	-- Shift register used to output to AN2-AN0	
+	-- Can either be loaded from memory or from the line buffer
+	signal display_shift_next : std_logic_vector(7 downto 0);
+	signal display_shift_reg : std_logic_vector(7 downto 0);
+	
+	signal delay_display_shift_next : std_logic_vector(24 downto 0);
+	signal delay_display_shift_reg : std_logic_vector(24 downto 0);
+	
+	signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
+	
+	signal load_display_shift_from_memory : std_logic;
+	signal load_display_shift_from_line_buffer : std_logic;
+	
+	signal enable_shift : std_logic;
+	signal shiftclock_next : std_logic_vector(3 downto 0);
+	signal shiftclock_reg : std_logic_vector(3 downto 0);
+	
+	signal playfield_reset : std_logic;
+	signal playfield_load : std_logic;
+	
+	-- position in frame	
+	signal hcount_next : std_logic_vector(7 downto 0);
+	signal hcount_reg : std_logic_vector(7 downto 0);
+	
+	signal vcount_next : std_logic_vector(8 downto 0);
+	signal vcount_reg : std_logic_vector(8 downto 0);
+	
+	signal vblank_next : std_logic;
+	signal vblank_reg : std_logic;
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
+	
+	signal hcount_reset : std_logic;
+	signal vcount_reset : std_logic;
+	signal vcount_increment : std_logic;
+	
+	-- scrolling	
+	signal hscrol_reg : std_logic_vector(3 downto 0);
+	signal hscrol_next : std_logic_vector(3 downto 0);
+
+	signal vscrol_raw_reg : std_logic_vector(3 downto 0);
+	signal vscrol_raw_next : std_logic_vector(3 downto 0);
+	signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
+	
+	signal vscrol_enabled_reg : std_logic;
+	signal vscrol_enabled_next : std_logic;
+	signal vscrol_last_enabled_reg : std_logic;
+	signal vscrol_last_enabled_next : std_logic;
+	
+	signal update_row_count : std_logic;
+	
+	signal hscrol_enabled_reg : std_logic;
+	signal hscrol_enabled_next : std_logic;
+
+	-- refresh
+	signal refresh_pending_next : std_logic;
+	signal refresh_pending_reg : std_logic;
+
+	signal refresh_fetch_next : std_logic;
+	signal refresh_fetch_reg : std_logic;
+	
+	-- Counter signals
+	signal increment_display_list_address : std_logic;
+	signal load_display_list_address : std_logic;
+	signal display_list_address_next : std_logic_vector(15 downto 0);
+	signal display_list_address_reg : std_logic_vector(15 downto 0);
+	signal load_display_list_address_cpu : std_logic;
+	signal load_display_list_address_dma : std_logic;
+	signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
+	signal display_list_address_next_dma : std_logic_vector(15 downto 0);	
+
+	signal increment_memory_scan_address : std_logic;
+	signal load_memory_scan_address : std_logic;
+	signal memory_scan_address_next : std_logic_vector(15 downto 0);
+	signal memory_scan_address_reg : std_logic_vector(15 downto 0);
+
+	signal increment_line_buffer_address : std_logic;
+	signal load_line_buffer_address : std_logic;
+	signal line_buffer_address_next : std_logic_vector(7 downto 0);
+	signal line_buffer_address_reg : std_logic_vector(7 downto 0);
+
+	signal increment_row_count : std_logic;
+	signal load_row_count : std_logic;
+	signal row_count_next : std_logic_vector(3 downto 0);
+	signal row_count_reg : std_logic_vector(3 downto 0);
+
+	signal increment_refresh_count : std_logic;
+	signal load_refresh_count : std_logic;
+	signal refresh_count_next : std_logic_vector(3 downto 0);
+	signal refresh_count_reg : std_logic_vector(3 downto 0);
+	
+	signal pmbase_reg : std_logic_vector(7 downto 2);
+	signal pmbase_next : std_logic_vector(7 downto 2);
+
+	signal chbase_raw_reg : std_logic_vector(7 downto 1);
+	signal chbase_raw_next : std_logic_vector(7 downto 1);
+	signal chbase_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal line_buffer_write : std_logic;
+	signal line_buffer_data_in : std_logic_vector(7 downto 0);
+	signal line_buffer_data_out : std_logic_vector(7 downto 0);
+	
+	-- output registers
+	signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
+	signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
+	signal an_prev_reg : std_logic_vector(2 downto 0);  -- previous - for hscrol
+	signal an_next : std_logic_vector(2 downto 0);
+	signal an_reg : std_logic_vector(2 downto 0);
+	
+	-- light pendin
+	signal penv_next : std_logic_vector(7 downto 0);
+	signal penv_reg : std_logic_vector(7 downto 0);
+	signal penh_next : std_logic_vector(7 downto 0);
+	signal penh_reg : std_logic_vector(7 downto 0);
+	
+	-- high res modes
+	signal colour_clock_8x : std_logic;
+	signal colour_clock_4x : std_logic;
+	signal colour_clock_2x : std_logic;
+	signal colour_clock_1x : std_logic;
+	signal colour_clock_half_x : std_logic;
+	signal colour_clock_selected : std_logic;
+	signal colour_clock_selected_highres : std_logic;
+	
+	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
+	
+	constant cycle_length : integer := 32;	
+	
+	signal memory_ready_both : std_logic;
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			nmi_reg <= '0';
+			wsync_reg <= '0';
+			vcount_reg <= (others=>'0');
+			--hcount_reg <= X"01";
+			hcount_reg <= X"00";
+			dmactl_raw_reg <= (others=>'0');
+			chactl_reg <= (others=>'0');
+			vblank_reg <= '0';			
+			vsync_reg <= '0';
+			pmbase_reg <= (others=>'0');
+			allow_real_dma_reg <= '0';
+			display_shift_reg <= (others=>'0');
+			chbase_raw_reg <= (others=>'0');
+			
+			instruction_reg <= (others=>'0');
+			first_line_of_instruction_reg <= '0';
+			last_line_of_instruction_reg <= '0';
+			dma_speed_reg <= no_dma;
+			instruction_type_reg <= mode_blank;
+			instruction_final_row_reg <= (others=>'0');
+			shift_rate_reg <= slow_shift;
+			shift_twobit_reg <= '0';
+			twopixel_reg <= '0';
+			single_colour_character_reg <= '0';
+			multi_colour_character_reg <= '0';
+			twoline_character_reg <= '0';
+			map_background_reg <= '0';
+			dli_enabled_reg <= '0';
+			two_part_instruction_reg <= '0';
+			descenders_reg <='0';
+			
+			hscrol_reg <= (others=>'0');
+			vscrol_raw_reg <= (others=>'0');			
+			vscrol_enabled_reg <= '0';
+			vscrol_last_enabled_reg <= '0';
+			hscrol_enabled_reg <= '0';
+			
+			shiftclock_reg <= (others=>'0');
+			
+			hblank_reg <= '0';
+			
+			an_reg <= (others=>'0');
+			an_prev_reg <= (others=>'0');
+			
+			dma_fetch_reg <= '0';
+			dma_address_reg <= (others=>'0');			
+			dma_fetch_destination_reg <= dma_fetch_null;
+			
+			playfield_display_active_reg <= '0';
+			
+			instruction_blank_reg <= '0';
+			
+			display_list_address_low_temp_reg <= (others=>'0');
+			
+			character_reg <= (others=>'0');
+			displayed_character_reg <= (others=>'0');
+			
+			refresh_pending_reg <= '0';
+			refresh_fetch_reg <= '0';
+			
+			--nmi_pending_reg <= '0';
+			
+			dli_nmi_reg <= '0';
+			vbi_nmi_reg <= '0';
+			nmien_raw_reg <= (others=>'0');
+			
+			delay_display_shift_reg <= (others=>'0');
+			
+			nmi_shiftreg_reg <= (others=>'1');
+			
+			penh_reg <= (others=>'0');
+			penv_reg <= (others=>'0');
+			
+			colour_clock_count_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then			
+			nmi_reg <= nmi_next;
+			wsync_reg <= wsync_next;
+			vcount_reg <= vcount_next;
+			hcount_reg <= hcount_next;
+			nmist_reg <= nmist_next;
+			dmactl_raw_reg <= dmactl_raw_next;
+			chactl_reg <= chactl_next;
+			vblank_reg <= vblank_next;
+			vsync_reg <= vsync_next;
+			pmbase_reg <= pmbase_next;
+			allow_real_dma_reg <= allow_real_dma_next;
+			display_shift_reg <= display_shift_next;
+			chbase_raw_reg <= chbase_raw_next;
+			
+			instruction_reg <= instruction_next;
+			first_line_of_instruction_reg <= first_line_of_instruction_next;
+			last_line_of_instruction_reg <= last_line_of_instruction_next;
+			dma_speed_reg <= dma_speed_next;
+			instruction_type_reg <= instruction_type_next;
+			instruction_final_row_reg <= instruction_final_row_next;
+			shift_rate_reg <= shift_rate_next;
+			shift_twobit_reg <= shift_twobit_next;
+			twopixel_reg <= twopixel_next;
+			single_colour_character_reg <= single_colour_character_next;
+			multi_colour_character_reg <= multi_colour_character_next;
+			twoline_character_reg <= twoline_character_next;
+			map_background_reg <= map_background_next;
+			dli_enabled_reg <= dli_enabled_next;
+			two_part_instruction_reg <= two_part_instruction_next;
+			descenders_reg <= descenders_next;
+			
+			hscrol_reg <= hscrol_next;
+			vscrol_raw_reg <= vscrol_raw_next;	
+			vscrol_enabled_reg <= vscrol_enabled_next;
+			vscrol_last_enabled_reg <= vscrol_last_enabled_next;
+			hscrol_enabled_reg <= hscrol_enabled_next;
+			
+			shiftclock_reg <= shiftclock_next;
+			
+			hblank_reg <= hblank_next;
+			
+			an_reg <= an_next;
+			an_prev_reg <= an_prev_next;
+			
+			dma_fetch_reg <= dma_fetch_next;
+			dma_address_reg <= dma_address_next;
+			dma_fetch_destination_reg <= dma_fetch_destination_next;
+			
+			playfield_display_active_reg <= playfield_display_active_next;
+			
+			instruction_blank_reg <= instruction_blank_next;
+			
+			display_list_address_low_temp_reg <= display_list_address_low_temp_next;
+			
+			character_reg <= character_next;
+			displayed_character_reg <= displayed_character_next;
+			
+			refresh_pending_reg <= refresh_pending_next;
+			refresh_fetch_reg <= refresh_fetch_next;
+						
+			dli_nmi_reg <= dli_nmi_next;
+			vbi_nmi_reg <= vbi_nmi_next;
+			nmien_raw_reg <= nmien_raw_next;
+			
+			delay_display_shift_reg <= delay_display_shift_next;
+			
+			nmi_shiftreg_reg <= nmi_shiftreg_next;
+			
+			penh_reg <= penh_next;
+			penv_reg <= penv_next;
+			
+			colour_clock_count_reg <= colour_clock_count_next;
+		end if;
+	end process;
+	
+	-- Colour clock (3.57MHz for PAL)
+	-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
+	-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
+	--enable_colour_clock_div : enable_divider
+		--generic map (COUNT=>7)
+		--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);	
+	process(colour_clock_count_reg, ANTIC_ENABLE_179)		
+	begin
+		colour_clock_half_x <= '0';
+		colour_clock_1x<='0';
+		colour_clock_2x<='0';
+		colour_clock_4x<='0';
+		colour_clock_8x<='0';
+	
+		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+		
+		if (ANTIC_ENABLE_179 = '1') then -- resync...
+			colour_clock_count_next <= "00001";
+		end if;
+
+		colour_clock_8x <= '1';
+		
+		case colour_clock_count_reg(4 downto 0) is
+		when "00000" =>
+			colour_clock_half_x <= '1';
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "00100" =>
+			colour_clock_4x <= '1';
+		when "01000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "01100" =>
+			colour_clock_4x <= '1';
+		when "10000" =>			
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "10100" =>
+			colour_clock_4x <= '1';
+		when "11000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "11100" =>
+			colour_clock_4x <= '1';			
+		when others =>
+			-- nop
+		end case;
+	end process;
+	
+	process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
+	begin
+		enable_dma <= colour_clock_half_x;
+		colour_clock_selected <= colour_clock_1x;
+		colour_clock_selected_highres <= colour_clock_2x;		
+		dmactl_delayed_enabled <= '0';
+		
+		case dmactl_delayed_reg(6 downto 5) is
+		when "01" =>
+			dmactl_delayed_enabled <= '1';
+		when "10" =>
+			enable_dma <= colour_clock_1x;
+			colour_clock_selected <= colour_clock_2x;		
+			colour_clock_selected_highres <= colour_clock_4x;
+			dmactl_delayed_enabled <= '1';
+		when "11" =>
+			enable_dma <= colour_clock_2x;
+			colour_clock_selected <= colour_clock_4x;
+			colour_clock_selected_highres <= colour_clock_8x;
+			dmactl_delayed_enabled <= '1';
+		when others =>
+			--nop
+		end case;		
+	end process;	
+		
+	--enable_dma_clock_div : enable_divider
+	--	generic map (COUNT=>2)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>colour_clock_selected,enable_out=>enable_dma);		
+
+	-- Counters (memory address for data, memory address for display list)
+	antic_counter_memory_scan : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
+		
+	load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
+	display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
+	antic_counter_display_list : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
+	antic_counter_line_buffer : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
+	antic_counter_row_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
+	antic_counter_refresh_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
+	
+	-- Count position on screen
+	-- horizontal
+	process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
+	begin
+		hcount_next <= hcount_reg;		
+		if (colour_clock_1x = '1') then
+			hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
+			
+			if (colour_clock_half_x = '1') then
+				hcount_next(0) <= '1';
+			end if;
+		end if;
+		
+		if (hcount_reset = '1') then
+			hcount_next <= (others=>'0');
+		end if;
+	end process;
+	
+	-- vertical
+	process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
+	begin
+		vcount_next <= vcount_reg;
+		
+		if (colour_clock_1x = '1') then		
+			if (vcount_increment = '1') then
+				vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
+			end if;
+			
+			if (vcount_reset = '1') then
+				vcount_next <= (others=>'0');
+			end if;
+		end if;
+	end process;	
+	
+	-- Actions done based on vertical position		
+	process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
+	begin
+		vblank_next <= vblank_reg;
+		vsync_next <= vsync_reg;
+		vcount_reset <= '0';
+	
+		if (colour_clock_1x='1') then
+			case vcount_reg is
+				when '0'&X"08" => 
+					vblank_next <= '0';
+				when '0'&X"F8" =>
+					vblank_next <= '1';
+				--when '1'&X"05" => (changed for testing galaxian!)
+				--	vblank_next <= '1';					
+-- PAL
+				when '1'&X"16" =>
+					vsync_next <= pal;
+				when '1'&X"19" =>
+					vsync_next <= '0';
+				when '1'&X"38" =>
+					vcount_reset <= '1'; -- Blip at 9c..., then wrap
+-- NTSC
+				when '0'&X"FA" =>
+					vsync_next <= not(pal);
+				when '0'&X"FD" =>
+					vsync_next <= '0';
+				when '1'&X"06" =>
+					vcount_reset <= not(pal); -- Blip at 9c..., then wrap
+				when others =>
+					-- nothing
+			end case;
+		end if;
+	end process;
+	
+	-- Calculate playfield start/end
+	process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
+	begin		
+		playfield_dma_start_cycle <= (others=>'1');
+		playfield_dma_end_cycle <= (others=>'1');
+		playfield_display_start_cycle <= (others=>'1');
+		playfield_display_end_cycle <= (others=>'1');
+		
+		-- DMA clock start/end
+		-- wide=3, normal=2, narrow=1
+		-- Playfield start is at (in colour clocks):
+		-- 68 + hscrol&FE - width*16
+		-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
+		-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong... 
+		-- e.g. if its 64 then we may be able to do something like base&width&
+		-- Playfield end is at (in colour clocks):
+		-- 164 + hscrol&FE + width*16
+		-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
+		
+		-- hscrol interfers with playfield dma width (for dma purposes only!)
+		if (hscrol_enabled_reg='1') then
+			case dmactl_delayed_reg(1 downto 0) is
+				when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
+					playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20  (10 in machine cycles)
+					playfield_dma_end_cycle   <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
+				when "01" => -- narrow - traated as normal due to hscrol
+					playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36  (18 in machine cycles)
+					playfield_dma_end_cycle <=   X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
+				when others =>
+					-- nothing
+			end case;
+		else
+			case dmactl_delayed_reg(1 downto 0) is
+				when "11" => -- wide
+					playfield_dma_start_cycle <= X"11";
+					playfield_dma_end_cycle   <= X"D0";
+				when "10" => -- normal
+					playfield_dma_start_cycle <= X"21";
+					playfield_dma_end_cycle   <= X"C0";
+				when "01" => -- narrow
+					playfield_dma_start_cycle <= X"31";
+					playfield_dma_end_cycle <=   X"B0";
+				when others =>
+					-- nothing
+			end case;		
+		end if;
+
+		-- background colour outside this area...
+		-- TODO - review these locations - should be clear due to garbage!
+		case dmactl_delayed_reg(1 downto 0) is
+			when "11" => -- wide
+				playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
+				if (hscrol_reg > X"C") then
+					playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol				
+				end if;
+				playfield_display_end_cycle   <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
+			when "10" => -- normal
+				playfield_display_start_cycle <= X"2F";
+				playfield_display_end_cycle   <= X"CF";
+			when "01" => -- narrow
+				playfield_display_start_cycle <= X"3F";
+				playfield_display_end_cycle <=   X"BF";
+			when others =>
+				-- nothing
+		end case;				
+	end process;
+	
+	-- Actions done based on horizontal position - notably dma!
+	process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, displayed_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg)
+	begin
+		allow_real_dma_next <= allow_real_dma_reg;
+
+		playfield_dma_start <= '0';
+		playfield_dma_end <= '0';
+		playfield_display_active_next <= playfield_display_active_reg;
+		
+		dma_fetch_request <= '0';
+		dma_address_next <= dma_address_reg;
+		dma_fetch_destination_next <= dma_fetch_destination_reg;
+		
+		first_line_of_instruction_next <= first_line_of_instruction_reg;
+		last_line_of_instruction_next <= last_line_of_instruction_reg;
+		
+		load_display_shift_from_line_buffer <= '0';
+				
+		increment_memory_scan_address <= '0';
+		
+		line_buffer_address_next <= (others=>'0');
+		load_line_buffer_address <= '0';
+		increment_line_buffer_address <= '0';
+		
+		playfield_load <= '0';
+		
+		hblank_next <= hblank_reg;
+		hcount_reset <= '0';
+		
+		vcount_increment <= '0';
+		
+		character_next <= character_reg;
+		displayed_character_next <= displayed_character_reg;
+		
+		dli_nmi_next <= dli_nmi_reg;
+		vbi_nmi_next <= vbi_nmi_reg;
+		wsync_reset <= '0';
+		
+		load_refresh_count <= '0';
+		refresh_count_next <= (others=>'0');
+		
+		update_row_count <= '0'; 
+		vscrol_last_enabled_next <= vscrol_last_enabled_reg;
+	
+		if (colour_clock_1x = '1') then	
+			-- Playfield start/end
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
+				playfield_dma_start <= '1';				
+				load_line_buffer_address <= '1';
+			end if;
+			
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
+				playfield_dma_end <= '1';
+			end if;	
+			
+			if (hcount_reg = playfield_display_start_cycle) then
+				playfield_display_active_next <= '1';				
+			end if;
+			
+			if (hcount_reg = playfield_display_end_cycle) then
+				playfield_display_active_next <= '0';
+			end if;	
+
+			if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
+				if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
+					dma_fetch_request <= '1';
+				end if;				
+
+				if (twoline_character_reg='1') then
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				else
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				end if;
+				
+				displayed_character_next <= character_reg;
+				
+				-- TODO
+				-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.				
+				dma_fetch_destination_next <= dma_fetch_shiftreg;
+				
+				load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);								
+				increment_line_buffer_address <= '1';
+			end if;						
+		
+			case hcount_reg is 		
+				when X"00" => -- missile DMA, if missile or player DMA enabled					
+					dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;									
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"02" => -- display list dma if enabled
+					first_line_of_instruction_next <= '0';
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- suppress when waiting for vblank
+						first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
+					else				
+						if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
+							dma_fetch_request <= dmactl_delayed_enabled;
+							dma_address_next <= display_list_address_reg;
+							dma_fetch_destination_next <= dma_fetch_instruction;									
+							
+							first_line_of_instruction_next <= '1';						
+							
+							vscrol_last_enabled_next <= vscrol_enabled_reg;
+						end if;
+					end if;					
+				
+				when X"03" =>				
+					update_row_count <= '1'; -- done after instruction fetch...
+					
+				when X"04"|X"06"|X"08"|X"0A" =>  -- player DMA, if enabled
+					dma_fetch_request <= dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;	
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"0C" => -- lms lower byte dma if display list dma enabled?;
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_low;
+				
+				when X"0E" => -- lms upper byte dma if display list dma enabled?
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_high;
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
+						first_line_of_instruction_next <= '0';
+					end if;
+					
+					dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
+					if (vcount_reg = '0'&X"F8") then
+						vbi_nmi_next <= '1';
+					end if;
+					
+				when X"12" =>
+					dli_nmi_next <= '0';
+					vbi_nmi_next <= '0';
+
+				when X"21" =>
+					hblank_next <= '0';					
+					
+				when X"24" => 
+					playfield_load <= '1'; -- start the shift register
+					
+				when X"31" => -- start refresh					
+					load_refresh_count <= '1';
+					refresh_count_next <= (others=>'0');
+				
+				when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
+					wsync_reset <= '1';				
+			
+				when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
+					allow_real_dma_next <= '0';				
+					load_refresh_count <= '1';
+					refresh_count_next <= "1001";
+					
+				when X"D8" => -- vscrol value checked at cycle 108
+					last_line_of_instruction_next <= last_line_of_instruction_live;
+				
+				when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
+					vcount_increment <= '1';
+										
+				when X"DD" =>
+					hblank_next <= '1';					
+					
+				when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
+					hcount_reset <= '1';
+					allow_real_dma_next <= not(vblank_reg);
+				when others =>
+					-- nothing
+			end case;	
+			
+			-- Playfield DMA
+			if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
+				dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= first_line_of_instruction_reg;
+			end if;					
+			
+			if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
+				character_next <= line_buffer_data_out;
+				increment_line_buffer_address <= '1';
+			end if;
+			
+			if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data			
+				dma_fetch_request <= dmactl_delayed_enabled;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= '1';		
+			end if;
+			
+			if (vblank_reg = '1') then
+				dma_fetch_request <= '0';
+			end if;
+			
+			if (refresh_fetch_next = '1') then
+				dma_address_next <= (others=>'0');
+			end if;
+		
+		end if;
+	end process;
+	
+	-- refresh handling
+	process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, memory_ready_antic, allow_real_dma_next)
+	begin
+		increment_refresh_count <= '0';
+		refresh_pending_next <= refresh_pending_reg;
+		refresh_fetch_next <= not(memory_ready_antic) and refresh_fetch_reg;
+		
+		if (colour_clock_1x = '1') then
+			-- do pending refresh once we have a spare cycle
+			if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
+				refresh_fetch_next <= '1';		
+				refresh_pending_next <= '0';
+			end if;
+		
+			-- do scheduled refresh - if block, enable pending one
+			if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
+				increment_refresh_count <= '1';
+				refresh_fetch_next <= not(dma_fetch_next);
+				refresh_pending_next <= dma_fetch_next;
+			end if;
+		end if;
+	end process;
+	
+	-- nmi handling
+	-- edge senstive, single cycle is enough (unless cpu disabled or  clashes)
+	-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist...	which is the goal.	
+
+	nmien_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
+		
+	nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
+	
+	process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
+	begin	
+		nmist_next(5) <= '0';
+		nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
+		nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
+	end process;
+	
+	-- dma clock	
+	process(dma_speed_reg) -- XXX TODO - remove this process!
+	begin
+		slow_dma_s <= '0';
+		medium_dma_s <= '0';
+		fast_dma_s <= '0';
+		
+		case dma_speed_reg is
+			when no_dma =>
+				-- nothing
+			when slow_dma =>
+				slow_dma_s <= '1';
+			when medium_dma =>
+				medium_dma_s <= '1';
+			when fast_dma =>
+				fast_dma_s <= '1';
+		end case;
+	end process;
+	
+	antic_dma_clock1 : antic_dma_clock
+		port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
+
+	-- line buffer
+	reg_file1 : reg_file
+		generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
+		port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);		
+		--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
+		--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
+		
+	-- vertical scrolling
+	-- load row count from vscrol must be done at time of instruction load
+	-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
+	-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
+	vscrol_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>4)
+		port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));		
+	
+	process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count, force_final_row)
+	begin								
+		load_row_count <= '0';
+		row_count_next <= (others=>'0');
+		increment_row_count <= '0';
+		
+		last_line_of_instruction_live <= '0';		
+		
+		if (update_row_count = '1') then							
+			if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
+				row_count_next <= vscrol_delayed_reg;
+			end if;
+		
+			if (first_line_of_instruction_reg = '1') then
+				load_row_count <= '1';
+			else
+				increment_row_count <= '1';
+			end if;
+		end if;
+		
+		if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
+			if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
+				last_line_of_instruction_live <= '1';
+			end if;
+		else -- normal
+			if (row_count_reg = instruction_final_row_reg) then
+				last_line_of_instruction_live <= '1';
+			end if;
+		end if;
+		
+		if (vblank_reg = '1' or force_final_row = '1') then
+			last_line_of_instruction_live <= '1';
+		end if;
+						
+	end process;
+	
+	-- chbase 2 cycle delay
+	chbase_delay : wide_delay_line
+		generic map (COUNT=>cycle_length*2,WIDTH=>7)
+		port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
+		
+	-- decode instruction	
+	process(instruction_reg)
+	begin
+		dma_speed_next <= no_dma;
+		instruction_type_next <= mode_blank;
+		shift_rate_next <= slow_shift;
+		shift_twobit_next <= '0';
+		twopixel_next <= '0';
+		single_colour_character_next <= '0';		
+		multi_colour_character_next <= '0';		
+		twoline_character_next <= '0';
+		map_background_next <= '0';
+		instruction_final_row_next <= (others=>'0');
+		two_part_instruction_next <= instruction_reg(6);
+		instruction_blank_next <= '0';
+		vscrol_enabled_next <= instruction_reg(5);
+		hscrol_enabled_next <= instruction_reg(4);
+		dli_enabled_next <= instruction_reg(7);
+		descenders_next <= '0';		
+		force_final_row <= '0';
+		
+		case instruction_reg(3 downto 0) is 			
+			when X"0" =>
+				instruction_type_next <= mode_blank;
+				instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
+				two_part_instruction_next <= '0';
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				
+			when X"1" =>
+				instruction_type_next <= mode_jump;
+				instruction_final_row_next <= (others=>'0');
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				two_part_instruction_next <= '1';
+				
+				if (instruction_reg(6) = '1') then
+					instruction_type_next <= mode_jvb;
+					force_final_row <= '1';
+				end if;
+				
+			when X"2" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+			when X"3" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"9";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				descenders_next <= '1';
+				
+			when X"4" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				multi_colour_character_next <= '1';
+				
+			when X"5" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';	
+				twoline_character_next <= '1';		
+				multi_colour_character_next <= '1';
+				
+			when X"6" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				
+			when X"7" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				twoline_character_next <= '1';
+				
+			when X"8" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= slow_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"9" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"A" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"B" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"C" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"D" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"E" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"F" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+		end case;
+	end process;
+
+	-- dma fetching
+	process(dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,memory_ready_both,memory_data_in,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
+	begin	
+		instruction_next <= instruction_reg;
+		dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
+		
+		display_list_address_next_dma <= display_list_address_reg;
+		load_display_list_address_dma <= '0';
+		memory_scan_address_next <= memory_scan_address_reg;
+		load_memory_scan_address <= '0';
+		increment_display_list_address <= '0';
+		
+		load_display_shift_from_memory <= '0';
+		display_list_address_low_temp_next <= display_list_address_low_temp_reg;		
+		
+		line_buffer_data_in <= (others=>'0');
+		line_buffer_write <= '0';
+		
+		if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
+			instruction_next <= (others=>'0');
+		end if;
+	
+		if (dma_fetch_reg='1' and memory_ready_both='1') then
+			case dma_fetch_destination_reg is 
+				when dma_fetch_line_buffer =>
+					line_buffer_data_in <= memory_data_in;					
+					line_buffer_write <= '1';
+				when dma_fetch_shiftreg =>
+					load_display_shift_from_memory <= '1';
+				when dma_fetch_null =>
+					-- nothing (C/G/MTIA listens to bus)
+				when dma_fetch_instruction =>
+					instruction_next <= memory_data_in;
+					
+					increment_display_list_address <= '1';
+					
+				when dma_fetch_list_low =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						--display_list_address_next_dma(7 downto 0) <= memory_data_in; Changing this so soon messes up next dma cycle
+						display_list_address_low_temp_next <= memory_data_in;
+						increment_display_list_address <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(7 downto 0) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				when dma_fetch_list_high =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						 display_list_address_next_dma <= memory_data_in&display_list_address_low_temp_reg;
+						 load_display_list_address_dma <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(15 downto 8) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				
+				when others =>
+					-- nothing
+				
+			end case;
+
+			dma_fetch_next <= '0';
+		end if;
+	end process;
+	
+	-- shift reg clock
+	playfield_reset <= hblank_reg;
+	
+	process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
+	begin
+		shiftclock_next <= shiftclock_reg;
+		enable_shift <= '0';
+	
+		if (colour_clock_selected = '1') then
+		
+			shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
+			
+			if (playfield_load='1') then
+				shiftclock_next <= "1000";
+			end if;
+			
+			if (playfield_reset='1') then
+				shiftclock_next <= "0000";
+			end if;			
+			
+			--shiftclock_next(0) <= shiftclock_reg(1);
+			--shiftclock_next(1) <= shiftclock_reg(2);
+			--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
+			--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;						
+			case shift_rate_reg is
+				when slow_shift =>
+					enable_shift <= shiftclock_reg(0);
+				when medium_shift =>
+					enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
+				when fast_shift =>			
+					enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
+				when others =>
+					-- nothing
+			end case;			
+		end if;
+	end process;
+
+	-- shift reg
+	process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, memory_data_in, line_buffer_data_out)
+	begin
+		display_shift_next <= display_shift_reg;
+		
+		if (enable_shift = '1') then
+			if (shift_twobit_reg = '1') then
+				display_shift_next <= display_shift_reg(5 downto 0)&"00";
+			else
+				display_shift_next <= display_shift_reg(6 downto 0)&"0";
+			end if;			
+		end if;
+		
+		if (load_display_shift_from_memory = '1') then
+			display_shift_next(7 downto 0) <= memory_data_in;
+		end if;
+
+		if (load_display_shift_from_line_buffer = '1') then
+			display_shift_next(7 downto 0) <= line_buffer_data_out;
+		end if;
+		
+	end process;
+	
+	-- delay shift reg output for n cycles, so we can match AN with antic output
+	process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg)
+	begin
+		delay_display_shift_next <= delay_display_shift_reg;
+		
+		if (colour_clock_selected = '1') then
+			delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
+		end if;
+		
+	end process;
+	
+	-- ANO-2
+	-- XXX - clean up!	
+	-- first process - AN with no blanking	
+	process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
+	begin
+		an_current <= (others=>'0');
+		data_live <= (others=>'0');
+		if (shift_twobit_reg = '1') then				
+			an_current(0) <= delay_display_shift_reg(0);
+			an_current(1) <= delay_display_shift_reg(1);
+			an_current(2) <= '1';
+			
+			if (instruction_type_reg = mode_character) then							
+				data_live(0) <= delay_display_shift_reg(0);
+				data_live(1) <= delay_display_shift_reg(1);
+								
+				if (descenders_reg = '1') then					
+					if (delay_display_shift_reg(3 downto 2) = "11") then
+						if (unsigned(row_count_reg)<2) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					else
+						if (unsigned(row_count_reg)>=8) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					end if;
+				end if;	
+			
+				if (delay_display_shift_reg(4)='1') then -- inverse/hidden
+					if (chactl_reg(1)='1') then
+						an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
+						an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
+					else
+						an_current(0) <= data_live(0) and not(chactl_reg(0));
+						an_current(1) <= data_live(1) and not(chactl_reg(0));					
+					end if;
+				else
+					an_current(0) <= data_live(0);
+					an_current(1) <= data_live(1);				
+				end if;
+			end if;		
+
+			if (multi_colour_character_reg = '1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "11"&delay_display_shift_reg(4);										
+				end case;				
+			end if;
+			
+			if (map_background_reg='1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "110";										
+				end case;
+			end if;
+		else
+			if (single_colour_character_reg = '1') then
+				-- i.e. antic 6,7
+				if (delay_display_shift_reg(1) = '1') then
+					an_current(0) <= delay_display_shift_reg(3);
+					an_current(1) <= delay_display_shift_reg(4);
+					an_current(2) <= '1';					
+				else
+					an_current(0) <= '0';
+					an_current(1) <= '0';
+					an_current(2) <= '0';
+				end if;			
+			end if;
+			
+			if (map_background_reg='1') then
+				if (delay_display_shift_reg(1)='1') then
+					an_current <= "100";
+				else
+					an_current <= "000";										
+				end if;
+			end if;				
+		end if;		
+	end process;
+	
+	process(colour_clock_selected, an_current, an_prev_reg)
+	begin
+		an_prev_next <= an_prev_reg;
+		
+		if (colour_clock_selected = '1') then
+			an_prev_next <= an_current;
+		end if;
+	end process;
+	
+	process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
+	begin
+		an_next <= an_reg;
+	
+		if (colour_clock_selected = '1') then	
+			an_next <= an_current;
+			
+			if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
+				an_next <= an_prev_reg;
+			end if;
+			
+			if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
+				an_next <= "000";
+			end if;
+			
+			if (vblank_reg = '1' or hblank_reg = '1') then				
+				an_next(0) <= vsync_reg or twopixel_reg;
+				an_next(1) <= not(vsync_reg);
+				an_next(2) <= not(hblank_reg) and twopixel_reg;
+				
+				--an_next <= 
+						--(twopixel_reg and not(vsync_reg or hblank_reg))
+						--&((hblank_reg or vblank_reg) and not(vsync_reg))
+						--&(vsync_reg or twopixel_reg);
+			end if;			
+			
+			-- TODO this is too simplistic:
+			-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
+			-- + odd behaviour seen during high res bug
+
+		end if;
+		
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+
+	-- wsync write takes 1 cycle to assert rdy
+	-- TODO - revisit antic delays in terms of cpu cycles
+	wsync_delay : delay_line
+		generic map (COUNT=>cycle_length+cycle_length/2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
+
+	-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
+	--dmactl_delay : wide_delay_line
+	--	generic map (COUNT=>cycle_length,WIDTH=>6)
+	--	port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
+	dmactl_delayed_reg <= dmactl_raw_next;
+	--dmactl_delayed_reg <= dmactl_raw_reg;
+		
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
+	begin		
+		nmien_raw_next <= nmien_raw_reg;
+		dmactl_raw_next <= dmactl_raw_reg;
+		chactl_next <= chactl_reg;
+		hscrol_next <= hscrol_reg;
+		vscrol_raw_next <= vscrol_raw_reg;
+		chbase_raw_next <= chbase_raw_reg;
+		pmbase_next <= pmbase_reg;
+		wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
+		nmist_reset <= '0';
+		wsync_write <= '0';
+		
+		load_display_list_address_cpu <= '0';
+		display_list_address_next_cpu <= display_list_address_reg;
+	
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				dmactl_raw_next <= cpu_data_in(6 downto 0);
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				chactl_next <= cpu_data_in(2 downto 0);
+			end if;	
+			
+			if(addr_decoded(2) = '1') then
+				display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;		
+			
+			if(addr_decoded(3) = '1') then
+				display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;
+
+			if(addr_decoded(4) = '1') then
+				hscrol_next <= cpu_data_in(3 downto 0);
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				vscrol_raw_next <= cpu_data_in(3 downto 0);
+			end if;
+			
+			if(addr_decoded(7) = '1') then
+				pmbase_next <= cpu_data_in(7 downto 2);
+			end if;		
+			
+			if(addr_decoded(9) = '1') then
+				chbase_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+
+			if(addr_decoded(10) = '1') then
+				wsync_write <= '1';
+			end if;		
+	
+			if(addr_decoded(14) = '1') then
+				nmien_raw_next <= cpu_data_in(7 downto 6);
+			end if;
+		
+			if(addr_decoded(15) = '1') then
+				nmist_reset <= '1';
+			end if;		
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
+	begin
+		data_out <= X"FF";
+
+		if (addr_decoded(8) = '1') then -- HCOUNT :-)
+			data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
+		end if;
+		
+		if(addr_decoded(11) = '1') then --VCOUNT
+			data_out <= vcount_reg(8 downto 1);
+		end if;
+		
+		if (addr_decoded(12) = '1') then -- PENH
+			data_out <= penh_reg;
+		end if;
+		
+		if (addr_decoded(13) = '1') then -- PENV
+			data_out <= penv_reg;
+		end if;
+
+		if(addr_decoded(15) = '1') then --NMIST
+			data_out <= nmist_reg&"00000";
+		end if;
+		
+	end process;
+	
+	-- nmi delay
+	nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
+	
+	-- light pen
+	process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
+	begin
+		penv_next <= penv_reg;
+		penh_next <= penh_reg;
+		
+		if (lightpen = '0') then
+			penv_next <= vcount_reg(8 downto 1);
+			penh_next <= hcount_reg;
+		end if;
+	end process;
+	
+	-- Use CPU data if virtual dma
+	MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
+	
+	-- output
+	nmi_n_out <= nmi_shiftreg_reg(0);
+	
+	dma_clock_out<=dma_clock_character_name;
+	
+	AN <= an_reg;
+	
+	antic_ready <= not(wsync_reg);
+	
+	dma_fetch_out <= refresh_fetch_reg or (allow_real_dma_reg and dma_fetch_reg);
+	dma_address_out <= dma_address_reg;
+	
+	refresh_out <= refresh_fetch_reg;
+	
+	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+	COLOUR_CLOCK_OUT <= colour_clock_selected;
+	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
+	
+END vhdl;
+
Index: unmerged/core/de1/atari800core.qpf
===================================================================
--- unmerged/core/de1/atari800core.qpf	(nonexistent)
+++ unmerged/core/de1/atari800core.qpf	(revision 1)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: unmerged/core/de1/atari800core.sdc
===================================================================
--- unmerged/core/de1/atari800core.sdc	(nonexistent)
+++ unmerged/core/de1/atari800core.sdc	(revision 1)
@@ -0,0 +1,6 @@
+create_clock -period 50MHz [get_ports CLOCK_50]
+derive_pll_clocks
+
+set_input_delay -max -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+set_input_delay -min -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+
Index: unmerged/core/de1/countdown_timer.vhdl
===================================================================
--- unmerged/core/de1/countdown_timer.vhdl	(nonexistent)
+++ unmerged/core/de1/countdown_timer.vhdl	(revision 1)
@@ -0,0 +1,102 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_countdown_timer IS
+generic(UNDERFLOW_DELAY : natural := 3);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	ENABLE_UNDERFLOW : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	WR_EN : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+	DATA_OUT : OUT STD_LOGIC
+);
+END pokey_countdown_timer;
+
+ARCHITECTURE vhdl OF pokey_countdown_timer IS
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal count_reg : std_logic_vector(7 downto 0);
+	signal count_next: std_logic_vector(7 downto 0);
+	
+	signal underflow : std_logic;
+	
+	signal count_command : std_logic_vector(1 downto 0);	
+	signal underflow_command: std_logic_vector(1 downto 0);	
+BEGIN
+	-- Instantiate delay (provides output)
+	underflow0_delay : delay_line
+		generic map (COUNT=>UNDERFLOW_DELAY)
+		port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+		end if;
+	end process;
+
+	-- count down on enable
+	process(count_reg,enable,wr_en,count_command,data_in)
+	begin	
+		count_command <= enable&wr_en;
+		case count_command is
+			when "10" =>
+				count_next <= std_logic_vector(unsigned(count_reg) -1);
+			when "01"|"11" =>
+				count_next <= data_in;
+			when others =>
+				count_next <= count_reg;
+		end case;
+	end process;
+		
+	-- underflow
+	process(count_reg,enable,underflow_command)
+	begin
+		underflow_command <= enable & To_Std_Logic(count_reg = X"00");
+		case underflow_command is
+			when "11" =>
+				underflow <= '1';
+			when others =>
+				underflow <= '0';
+		end case;
+	end process;
+		
+END vhdl;
Index: unmerged/core/de1/cpu_65xx_e.vhd
===================================================================
--- unmerged/core/de1/cpu_65xx_e.vhd	(nonexistent)
+++ unmerged/core/de1/cpu_65xx_e.vhd	(revision 1)
@@ -0,0 +1,52 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Interface to 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end entity;
Index: unmerged/core/de1/gpio.vhd
===================================================================
--- unmerged/core/de1/gpio.vhd	(nonexistent)
+++ unmerged/core/de1/gpio.vhd	(revision 1)
@@ -0,0 +1,413 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio is
+port
+(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal read_write_n : std_logic;	
+	signal cart_data_read_async : std_logic_vector(7 downto 0);
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+	
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0');
+	GPIO_0_OUT(7 downto 5) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= '1';
+	GPIO_0_OUT(4) <= MONITOR; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= read_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable;
+	GPIO_0_OUT(33) <= pbi_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable;
+	GPIO_0_OUT(32) <= pbi_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and pbi_write_enable; -- d7
+	GPIO_0_OUT(31) <= cart_data_write(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and pbi_write_enable; -- d3
+	GPIO_0_OUT(30) <= cart_data_write(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable;
+	GPIO_0_OUT(29) <= pbi_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable;
+	GPIO_0_OUT(28) <= pbi_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable;
+	GPIO_0_OUT(27) <= pbi_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable;
+	GPIO_0_OUT(26) <= pbi_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable;
+	GPIO_0_OUT(25) <= pbi_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable;
+	GPIO_0_OUT(24) <= pbi_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable;
+	GPIO_0_OUT(23) <= pbi_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable;
+	GPIO_0_OUT(21) <= S4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable;
+	GPIO_0_OUT(20) <= pbi_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable;
+	GPIO_0_OUT(19) <= pbi_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable;
+	GPIO_0_OUT(18) <= pbi_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable;
+	GPIO_0_OUT(17) <= pbi_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and pbi_write_enable; -- d4
+	GPIO_0_OUT(16) <= cart_data_write(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and pbi_write_enable; -- d5
+	GPIO_0_OUT(15) <= cart_data_write(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and pbi_write_enable; -- d2
+	GPIO_0_OUT(14) <= cart_data_write(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and pbi_write_enable; -- d1
+	GPIO_0_OUT(13) <= cart_data_write(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and pbi_write_enable; -- d0
+	GPIO_0_OUT(12) <= cart_data_write(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and pbi_write_enable; -- d6
+	GPIO_0_OUT(11) <= cart_data_write(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable;
+	GPIO_0_OUT(10) <= S5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
+	GPIO_0_OUT(8) <= CCTL_n; -- cart control
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0'); -- unused
+	GPIO_0_OUT(7 downto 5) <= (others=>'0'); -- unused	
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4) when virtual_stick_in(7 downto 4) = "1111" else virtual_stick_in(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0) when virtual_stick_in(3 downto 0) = "1111" else virtual_stick_in(3 downto 0);
+		
+	--trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&gpio_enable&gpio_enable) or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= GPIO_1_IN(7)& GPIO_1_IN(6);
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	process(gpio_enable, keyboard_scan, keyboard_response_gpio, virtual_keycode, virtual_keyheld, virtual_shift_pressed, virtual_control_pressed, virtual_break_pressed, virtual_stick_in, virtual_trig_in)
+	begin	
+		keyboard_response <= keyboard_response_gpio;
+		
+		if (gpio_enable = '0') then
+			keyboard_response <= (others=>'1');
+		end if;
+		
+		if (virtual_keyheld='1' and virtual_keycode = not(keyboard_scan)) then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and virtual_break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and virtual_shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and virtual_control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;	
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+	
+	read_write_n <= not(pbi_write_enable);
+	
+	cart_complete <= cart_request; -- TODO!
+	
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	cart_data_read_async <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+	cart_data0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+	cart_data1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+	cart_data2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+	cart_data3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+	cart_data4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+	cart_data5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+	cart_data6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+	cart_data7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: replay/out
===================================================================
--- replay/out	(nonexistent)
+++ replay/out	(revision 1)
@@ -0,0 +1,11394 @@
+. /home/markw/altera/xilinx/ise/14.7/ISE_DS/common/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/common
+. /home/markw/altera/xilinx/ise/14.7/ISE_DS/EDK/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/EDK
+. /home/markw/altera/xilinx/ise/14.7/ISE_DS/PlanAhead/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/PlanAhead
+. /home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.settings32.sh /home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE
+~/altera/replay/src/hw/replay/cores/atari_800xl/build ~/altera/replay/src/hw/replay/cores/atari_800xl
+Starting Synthesis...
+Release 14.7 - xst P.20131013 (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+--> 
+
+TABLE OF CONTENTS
+  1) Synthesis Options Summary
+  2) HDL Compilation
+  3) Design Hierarchy Analysis
+  4) HDL Analysis
+  5) HDL Synthesis
+     5.1) HDL Synthesis Report
+  6) Advanced HDL Synthesis
+     6.1) Advanced HDL Synthesis Report
+  7) Low Level Synthesis
+  8) Partition Report
+  9) Final Report
+	9.1) Device utilization summary
+	9.2) Partition Resource Summary
+	9.3) TIMING REPORT
+
+
+=========================================================================
+*                      Synthesis Options Summary                        *
+=========================================================================
+---- Source Parameters
+Input File Name                    : "Replay.prj"
+Input Format                       : VHDL
+
+---- Target Parameters
+Output File Name                   : "Replay.ngc"
+Output Format                      : NGC
+Target Device                      : XC3S1600E-FG320-4
+
+---- Source Options
+Top Module Name                    : Replay_Top
+
+---- General Options
+Optimization Goal                  : Area
+Optimization Effort                : 1
+Keep Hierarchy                     : yes
+
+=========================================================================
+
+
+=========================================================================
+*                          HDL Compilation                              *
+=========================================================================
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl" in Library work.
+Architecture vhdl of Entity delay_line is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Pack.vhd" in Library work.
+Architecture replay_pack of Entity replay_pack is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl" in Library work.
+Architecture tree of Entity complete_address_decoder is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/countdown_timer.vhdl" in Library work.
+Architecture vhdl of Entity pokey_countdown_timer is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_noise_filter.vhdl" in Library work.
+Architecture vhdl of Entity pokey_noise_filter is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/syncreset_enable_divider.vhd" in Library work.
+Architecture vhdl of Entity syncreset_enable_divider is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_17_9.vhdl" in Library work.
+Architecture vhdl of Entity poly_17_9 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_5.vhdl" in Library work.
+Architecture vhdl of Entity poly_5 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_4.vhdl" in Library work.
+Architecture vhdl of Entity poly_4 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/synchronizer.vhdl" in Library work.
+Architecture vhdl of Entity synchronizer is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_keyboard_scanner.vhdl" in Library work.
+Architecture vhdl of Entity pokey_keyboard_scanner is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpupkg.vhd" in Library work.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Pack.vhd" in Library work.
+Architecture replay_ddrctrl_pack of Entity replay_ddrctrl_pack is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoTiming_Pack.vhd" in Library work.
+Architecture replay_videotiming_pack of Entity replay_videotiming_pack is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/basic.vhdl" in Library work.
+Architecture syn of Entity basic is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/os16.vhdl" in Library work.
+Architecture syn of Entity os16 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/generic_ram_infer.vhdl" in Library work.
+Architecture rtl of Entity generic_ram_infer is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/simple_counter.vhdl" in Library work.
+Architecture vhdl of Entity simple_counter is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_player.vhdl" in Library work.
+Architecture vhdl of Entity gtia_player is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_priority.vhdl" in Library work.
+Architecture vhdl of Entity gtia_priority is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl" in Library work.
+Architecture vhdl of Entity wide_delay_line is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey.vhdl" in Library work.
+Architecture vhdl of Entity pokey is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/enable_divider.vhdl" in Library work.
+Architecture vhdl of Entity enable_divider is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" in Library work.
+Architecture behave of Entity zpumediumcore is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_counter.vhdl" in Library work.
+Architecture vhdl of Entity antic_counter is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_dma_clock.vhdl" in Library work.
+Architecture vhdl of Entity antic_dma_clock is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl" in Library work.
+Architecture vhdl of Entity reg_file is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_65xx_e.vhd" in Library work.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font0_rom.vhd" in Library work.
+Architecture rtl of Entity font0 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font1_rom.vhd" in Library work.
+Architecture rtl of Entity font1 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font2_rom.vhd" in Library work.
+Architecture rtl of Entity font2 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Datapath.vhd" in Library work.
+Architecture rtl of Entity replay_ddrctrl_datapath is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoTiming.vhd" in Library work.
+Architecture rtl of Entity replay_videotiming is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_TranslatePS2_Pack.vhd" in Library work.
+Architecture replay_translateps2_pack of Entity replay_translateps2_pack is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd" in Library work.
+Architecture vhdl of Entity cpu is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic.vhdl" in Library work.
+Architecture vhdl of Entity antic is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_mixer.vhdl" in Library work.
+Architecture vhdl of Entity pokey_mixer is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_glue.vhdl" in Library work.
+Architecture sticky of Entity zpu_glue is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pia.vhdl" in Library work.
+Architecture vhdl of Entity pia is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/shared_enable.vhdl" in Library work.
+Architecture vhdl of Entity shared_enable is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/address_decoder.vhdl" in Library work.
+Architecture vhdl of Entity address_decoder is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_rom.vhdl" in Library work.
+Architecture syn of Entity zpu_rom is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" in Library work.
+Architecture vhdl of Entity zpu_config_regs is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia.vhdl" in Library work.
+Architecture vhdl of Entity gtia is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_palette.vhdl" in Library work.
+Architecture altirra of Entity gtia_palette is up to date.
+Architecture laoo of Entity gtia_palette is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/irq_glue.vhdl" in Library work.
+Architecture vhdl of Entity irq_glue is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/internalromram.vhd" in Library work.
+Architecture vhdl of Entity internalromram is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/covox.vhd" in Library work.
+Architecture vhdl of Entity covox is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_I2C.vhd" in Library work.
+Architecture rtl of Entity replay_i2c is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_SPI8.vhd" in Library work.
+Architecture rtl of Entity replay_spi8 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncBlock_D2048_W8.vhd" in Library work.
+Architecture rtl of Entity fifo_syncblock_d2048_w8 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncSRL_D16.vhd" in Library work.
+Architecture rtl of Entity fifo_syncsrl_d16 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_OSD.vhd" in Library work.
+Architecture rtl of Entity replay_osd is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl.vhd" in Library work.
+Architecture rtl of Entity replay_ddrctrl is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" in Library work.
+Architecture low_level_definition of Entity kcpsm3 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" in Library work.
+Architecture low_level_definition of Entity ps2_rom is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" in Library work.
+Entity <atari800core> compiled.
+Entity <atari800core> (Architecture <bdf_type>) compiled.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_TranslatePS2.vhd" in Library work.
+Architecture rtl of Entity replay_translateps2 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoConverter.vhd" in Library work.
+Architecture rtl of Entity replay_videoconverter is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_ClockGen_Sync.vhd" in Library work.
+Architecture rtl of Entity replay_resetgen is up to date.
+Architecture rtl of Entity replay_clockgen is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Core_Top.vhd" in Library work.
+Architecture rtl of Entity core_top is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd" in Library work.
+Architecture rtl of Entity replay_joyps2_core is up to date.
+Architecture rtl of Entity replay_joyps2 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Top.vhd" in Library work.
+Architecture rtl of Entity replay_ddrctrl_top is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" in Library work.
+Architecture rtl of Entity replay_syscon is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_FileIO_Sync.vhd" in Library work.
+Architecture rtl of Entity replay_fileio is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" in Library work.
+Architecture rtl of Entity replay_video is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Audio.vhd" in Library work.
+Architecture rtl of Entity replay_audio is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" in Library work.
+Architecture rtl of Entity replay_top is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_6510.vhd" in Library work.
+Architecture rtl of Entity cpu_6510 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_65xx_a.vhd" in Library work.
+Architecture rtl of Entity cpu_65xx is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_MousePointer.vhd" in Library work.
+Architecture rtl of Entity replay_mousepointer is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/DPRAM_BE_D64.vhd" in Library work.
+Architecture rtl of Entity dpram_be_d64 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncBlock_D1024_W18.vhd" in Library work.
+Architecture rtl of Entity fifo_syncblock_d1024_w18 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_Async_D32.vhd" in Library work.
+Architecture rtl of Entity fifo_async_d32 is up to date.
+Compiling vhdl file "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_Async_D16.vhd" in Library work.
+Architecture rtl of Entity fifo_async_d16 is up to date.
+
+=========================================================================
+*                     Design Hierarchy Analysis                         *
+=========================================================================
+Analyzing hierarchy for entity <Replay_Top> in library <work> (architecture <rtl>).
+
+Analyzing hierarchy for entity <Replay_ClockGen> in library <work> (architecture <RTL>) with generics.
+	G_DIVIDER = 11
+
+Analyzing hierarchy for entity <Core_Top> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <Replay_JoyPS2> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <Replay_DDRCtrl_Top> in library <work> (architecture <rtl>) with generics.
+	g_lp_big_endian = '1'
+
+Analyzing hierarchy for entity <Replay_Syscon> in library <work> (architecture <RTL>) with generics.
+	g_cfg_ctrl = "0000000010000000"
+	g_cfg_dynamic = "00000000000000000000000000000000"
+	g_cfg_fileio = "00000000"
+	g_cfg_static = "00000000000000000000000000000000"
+	g_version = "0000000000000001"
+
+Analyzing hierarchy for entity <Replay_FileIO> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <Replay_Video> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <Replay_Audio> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <Replay_ResetGen> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <atari800core> in library <work> (architecture <bdf_type>).
+
+Analyzing hierarchy for entity <Replay_TranslatePS2> in library <work> (architecture <RTL>) with generics.
+	g_kb_map = ("11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01100111",
+	            "11111111",
+	            "01010111",
+	            "11111111",
+	            "01000111",
+	            "11111111",
+	            "01000110",
+	            "01000000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000110",
+	            "01110111",
+	            "01000110",
+	            "01100000",
+	            "01000110",
+	            "01010111",
+	            "00110000",
+	            "11111111",
+	            "00000110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110001",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00100000",
+	            "11111111",
+	            "01100000",
+	            "11111111",
+	            "00000000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000001",
+	            "11111111",
+	            "01010001",
+	            "11111111",
+	            "00100001",
+	            "11111111",
+	            "00010001",
+	            "11111111",
+	            "01110000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000010",
+	            "11111111",
+	            "00110010",
+	            "11111111",
+	            "00100010",
+	            "11111111",
+	            "01100001",
+	            "11111111",
+	            "01110001",
+	            "11111111",
+	            "00000001",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000000",
+	            "11111111",
+	            "00110011",
+	            "11111111",
+	            "01010010",
+	            "11111111",
+	            "01100010",
+	            "11111111",
+	            "00010010",
+	            "11111111",
+	            "00000010",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110100",
+	            "11111111",
+	            "01000011",
+	            "11111111",
+	            "01010011",
+	            "11111111",
+	            "00100011",
+	            "11111111",
+	            "00010011",
+	            "11111111",
+	            "01110010",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000100",
+	            "11111111",
+	            "00100100",
+	            "11111111",
+	            "01100011",
+	            "11111111",
+	            "00000011",
+	            "11111111",
+	            "01110011",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110101",
+	            "11111111",
+	            "01010100",
+	            "11111111",
+	            "00010100",
+	            "11111111",
+	            "01100100",
+	            "11111111",
+	            "01110100",
+	            "11111111",
+	            "00000100",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000101",
+	            "11111111",
+	            "00110110",
+	            "11111111",
+	            "00100101",
+	            "11111111",
+	            "00100110",
+	            "11111111",
+	            "00010101",
+	            "11111111",
+	            "00000101",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010101",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01100101",
+	            "11111111",
+	            "01110101",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11000000",
+	            "11111111",
+	            "01000110",
+	            "11111111",
+	            "00010111",
+	            "11111111",
+	            "00010110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01100110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00000111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "10000100",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "10000010",
+	            "11111111",
+	            "10010000",
+	            "11111111",
+	            "10001000",
+	            "11111111",
+	            "10000001",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01110111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00100000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00000111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000110",
+	            "00100111",
+	            "01110110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00100111",
+	            "11111111",
+	            "01000110",
+	            "00110111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "10100000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111")
+
+Analyzing hierarchy for entity <Replay_VideoConverter> in library <work> (architecture <RTL>) with generics.
+	g_b_bitwidth = 8
+	g_g_bitwidth = 8
+	g_hadr_width = 9
+	g_hoffset = 0
+	g_hscale = "010000000"
+	g_hsize = 900
+	g_loffset = 0
+	g_match_line = 0
+	g_r_bitwidth = 8
+	g_vadr_width = 2
+	g_vid_param_hd = (rep_h => '0'
+	                  total_h => 864
+	                  active_h => 720
+	                  syncp_h => 12
+	                  syncw_h => 64
+	                  total_v => 625
+	                  active_v => 576
+	                  fline_f1_v => 44
+	                  lline_f1_v => 620
+	                  fline_f2_v => 0
+	                  lline_f2_v => 0
+	                  start_f1_v => 625
+	                  start_f2_v => 0
+	                  fsync_f1_v => 625
+	                  lsync_f1_v => 5
+	                  fsync_f2_v => 0
+	                  lsync_f2_v => 0
+	                  syncpol_h => '0'
+	                  syncpol_v => '0'
+	                  progressive => '1')
+	g_vid_param_sd = (rep_h => '1'
+	                  total_h => 1728
+	                  active_h => 1440
+	                  syncp_h => 24
+	                  syncw_h => 126
+	                  total_v => 625
+	                  active_v => 576
+	                  fline_f1_v => 22
+	                  lline_f1_v => 310
+	                  fline_f2_v => 335
+	                  lline_f2_v => 623
+	                  start_f1_v => 623
+	                  start_f2_v => 310
+	                  fsync_f1_v => 625
+	                  lsync_f1_v => 3
+	                  fsync_f2_v => 312
+	                  lsync_f2_v => 315
+	                  syncpol_h => '0'
+	                  syncpol_v => '0'
+	                  progressive => '0')
+	g_voffset = 21
+	g_vres_half = 1
+	g_vsize = 248
+
+Analyzing hierarchy for entity <Replay_JoyPS2_Core> in library <work> (architecture <RTL>) with generics.
+	g_id = '0'
+
+Analyzing hierarchy for entity <Replay_JoyPS2_Core> in library <work> (architecture <RTL>) with generics.
+	g_id = '1'
+
+Analyzing hierarchy for entity <ps2_rom> in library <work> (architecture <low_level_definition>).
+
+Analyzing hierarchy for entity <Replay_DDRCtrl> in library <work> (architecture <rtl>).
+
+Analyzing hierarchy for entity <Replay_SPI8> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <FIFO_SyncSRL_D16> in library <work> (architecture <RTL>) with generics.
+	g_width = 8
+
+Analyzing hierarchy for entity <Replay_OSD> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <FIFO_SyncBlock_D2048_W8> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <Replay_I2C> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <cpu> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <antic> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <pokey_mixer> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <zpu_glue> in library <work> (architecture <sticky>).
+
+Analyzing hierarchy for entity <pokey> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <pia> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <shared_enable> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <address_decoder> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <zpu_rom> in library <work> (architecture <syn>).
+
+Analyzing hierarchy for entity <generic_ram_infer> in library <work> (architecture <rtl>) with generics.
+	ADDRESS_WIDTH = 10
+	DATA_WIDTH = 8
+	SPACE = 1024
+
+Analyzing hierarchy for entity <zpu_config_regs> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 3
+
+Analyzing hierarchy for entity <gtia> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <gtia_palette> in library <work> (architecture <altirra>).
+
+Analyzing hierarchy for entity <irq_glue> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <reg_file> in library <work> (architecture <vhdl>) with generics.
+	BYTES = 16
+	WIDTH = 4
+
+Analyzing hierarchy for entity <reg_file> in library <work> (architecture <vhdl>) with generics.
+	BYTES = 32
+	WIDTH = 5
+
+Analyzing hierarchy for entity <internalromram> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <covox> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <Replay_VideoTiming> in library <work> (architecture <RTL>) with generics.
+	g_enabledynamic = '1'
+	g_param = (rep_h => '0'
+	           total_h => 800
+	           active_h => 640
+	           syncp_h => 16
+	           syncw_h => 96
+	           total_v => 525
+	           active_v => 480
+	           fline_f1_v => 42
+	           lline_f1_v => 522
+	           fline_f2_v => 0
+	           lline_f2_v => 0
+	           start_f1_v => 525
+	           start_f2_v => 0
+	           fsync_f1_v => 7
+	           lsync_f1_v => 9
+	           fsync_f2_v => 0
+	           lsync_f2_v => 0
+	           syncpol_h => '0'
+	           syncpol_v => '0'
+	           progressive => '1')
+
+Analyzing hierarchy for entity <kcpsm3> in library <work> (architecture <low_level_definition>).
+
+Analyzing hierarchy for entity <Replay_DDRCtrl_Datapath> in library <work> (architecture <rtl>).
+
+Analyzing hierarchy for entity <FONT0> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <FONT1> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <FONT2> in library <work> (architecture <RTL>).
+
+Analyzing hierarchy for entity <cpu_65xx> in library <work> (architecture <rtl>) with generics.
+	pipelineAluMux = false
+	pipelineAluOut = false
+	pipelineOpcode = false
+
+Analyzing hierarchy for entity <antic_counter> in library <work> (architecture <vhdl>) with generics.
+	COUNT_WIDTH = 12
+	STORE_WIDTH = 16
+
+Analyzing hierarchy for entity <antic_counter> in library <work> (architecture <vhdl>) with generics.
+	COUNT_WIDTH = 10
+	STORE_WIDTH = 16
+
+Analyzing hierarchy for entity <simple_counter> in library <work> (architecture <vhdl>) with generics.
+	COUNT_WIDTH = 8
+
+Analyzing hierarchy for entity <simple_counter> in library <work> (architecture <vhdl>) with generics.
+	COUNT_WIDTH = 4
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 16
+	WIDTH = 2
+
+Analyzing hierarchy for entity <antic_dma_clock> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <reg_file> in library <work> (architecture <vhdl>) with generics.
+	BYTES = 48
+	WIDTH = 6
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 16
+	WIDTH = 4
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 32
+	WIDTH = 7
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 4
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 24
+
+Analyzing hierarchy for entity <ZPUMediumCore> in library <work> (architecture <behave>) with generics.
+	ADDR_W = 24
+	BINOP_PIPE = 0
+	D_CARE_VAL = 'D'
+	ENA_IDLE = false
+	ENA_LEVEL0 = true
+	ENA_LEVEL1 = true
+	ENA_LEVEL2 = true
+	ENA_LSHR = true
+	FAST_FETCH = true
+	MEM_W = 16
+	MULT_PIPE = false
+	WORD_SIZE = 32
+
+Analyzing hierarchy for entity <pokey_countdown_timer> in library <work> (architecture <vhdl>) with generics.
+	UNDERFLOW_DELAY = 3
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 3
+
+Analyzing hierarchy for entity <pokey_noise_filter> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 28
+	RESETCOUNT = 6
+
+Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 114
+	RESETCOUNT = 33
+
+Analyzing hierarchy for entity <poly_17_9> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <poly_5> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <poly_4> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 2
+
+Analyzing hierarchy for entity <synchronizer> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <pokey_keyboard_scanner> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 2
+
+Analyzing hierarchy for entity <enable_divider> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 2
+
+Analyzing hierarchy for entity <enable_divider> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 16
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 15
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 8
+
+Analyzing hierarchy for entity <pokey> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 5
+
+Analyzing hierarchy for entity <gtia_player> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <gtia_priority> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 2
+	WIDTH = 6
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 3
+	WIDTH = 2
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 4
+	WIDTH = 2
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 2
+	WIDTH = 7
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 5
+	WIDTH = 8
+
+Analyzing hierarchy for entity <wide_delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 4
+	WIDTH = 8
+
+Analyzing hierarchy for entity <basic> in library <work> (architecture <syn>).
+
+Analyzing hierarchy for entity <os16> in library <work> (architecture <syn>).
+
+Analyzing hierarchy for entity <generic_ram_infer> in library <work> (architecture <rtl>) with generics.
+	ADDRESS_WIDTH = 14
+	DATA_WIDTH = 8
+	SPACE = 16384
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 2
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 6
+
+Analyzing hierarchy for entity <complete_address_decoder> in library <work> (architecture <tree>) with generics.
+	width = 4
+
+Analyzing hierarchy for entity <pokey_countdown_timer> in library <work> (architecture <vhdl>) with generics.
+	UNDERFLOW_DELAY = 3
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 3
+
+Analyzing hierarchy for entity <pokey_noise_filter> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 28
+	RESETCOUNT = 6
+
+Analyzing hierarchy for entity <syncreset_enable_divider> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 114
+	RESETCOUNT = 33
+
+Analyzing hierarchy for entity <poly_17_9> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <poly_5> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <poly_4> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <delay_line> in library <work> (architecture <vhdl>) with generics.
+	COUNT = 2
+
+Analyzing hierarchy for entity <synchronizer> in library <work> (architecture <vhdl>).
+
+Analyzing hierarchy for entity <pokey_keyboard_scanner> in library <work> (architecture <vhdl>).
+
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 292: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1205: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 455: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 486: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 609: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 617: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 384: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 426: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 528: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 600: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 685: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1114: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1141: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1225: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1274: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 335: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 374: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 406: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 416: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 435: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 445: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 471: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 496: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 557: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 590: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 797: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 874: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 889: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 942: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 961: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1249: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1306: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1316: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1332: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1420: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1453: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 831: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 910: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd" line 1373: attribute on instance <INIT> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_00> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_01> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_02> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_03> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_04> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_05> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_06> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INITP_07> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_00> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_01> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_02> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_03> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_04> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_05> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_06> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_07> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_08> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_09> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_0F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_10> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_11> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_12> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_13> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_14> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_15> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_16> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_17> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_18> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_19> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_1F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_20> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_21> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_22> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_23> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_24> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_25> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_26> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_27> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_28> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_29> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_2F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_30> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_31> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_32> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_33> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_34> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_35> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_36> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_37> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_38> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_39> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3A> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3B> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3C> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3D> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3E> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+WARNING:Xst:2591 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd" line 186: attribute on instance <INIT_3F> overrides generic/parameter on component. It is possible that simulator will not take this attribute into account.
+
+=========================================================================
+*                            HDL Analysis                               *
+=========================================================================
+Analyzing Entity <Replay_Top> in library <work> (Architecture <rtl>).
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 300: Unconnected output port 'o_clk_sys' of component 'Replay_ClockGen'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 300: Unconnected output port 'o_rst_sys' of component 'Replay_ClockGen'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 444: Unconnected output port 'debug' of component 'Core_Top'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 534: Unconnected output port 'o_joy_a' of component 'Replay_JoyPS2'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 534: Unconnected output port 'o_joy_b' of component 'Replay_JoyPS2'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 611: Unconnected output port 'o_cfg_ready' of component 'Replay_DDRCtrl_Top'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 611: Unconnected output port 'o_cfg_present' of component 'Replay_DDRCtrl_Top'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 783: Unconnected output port 'o_fch_to_core' of component 'Replay_FileIO'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 783: Unconnected output port 'o_hch_to_core' of component 'Replay_FileIO'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd" line 783: Unconnected output port 'o_mch_flush' of component 'Replay_FileIO'.
+Entity <Replay_Top> analyzed. Unit <Replay_Top> generated.
+
+Analyzing generic Entity <Replay_ClockGen> in library <work> (Architecture <RTL>).
+	G_DIVIDER = 11
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <u_clk_a_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <u_clk_b_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <u_clk_c_ibufg> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKDV_DIVIDE =  4.0000000000000000" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_DIVIDE =  1" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLK_FEEDBACK =  1X" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DSS_MODE =  NONE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "FACTORY_JF =  C080" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "PHASE_SHIFT =  0" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <u_a_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_DIVIDE =  1" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLK_FEEDBACK =  1X" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DSS_MODE =  NONE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "FACTORY_JF =  C080" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "PHASE_SHIFT =  0" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <u_b_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_DIVIDE =  1" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKOUT_PHASE_SHIFT =  NONE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLK_FEEDBACK =  1X" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DSS_MODE =  NONE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "FACTORY_JF =  C080" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "PHASE_SHIFT =  0" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <u_c_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKDV_DIVIDE =  2.0000000000000000" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_DIVIDE =  1" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKFX_MULTIPLY =  4" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_DIVIDE_BY_2 =  FALSE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKIN_PERIOD =  10.0000000000000000" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLKOUT_PHASE_SHIFT =  VARIABLE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "CLK_FEEDBACK =  1X" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DESKEW_ADJUST =  SYSTEM_SYNCHRONOUS" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DFS_FREQUENCY_MODE =  LOW" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DLL_FREQUENCY_MODE =  LOW" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DSS_MODE =  NONE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "DUTY_CYCLE_CORRECTION =  TRUE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "FACTORY_JF =  C080" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "PHASE_SHIFT =  0" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+    Set user-defined property "STARTUP_WAIT =  FALSE" for instance <phase_ctrl.u_a2_dcm> in unit <Replay_ClockGen>.
+Entity <Replay_ClockGen> analyzed. Unit <Replay_ClockGen> generated.
+
+Analyzing Entity <Replay_ResetGen> in library <work> (Architecture <RTL>).
+Entity <Replay_ResetGen> analyzed. Unit <Replay_ResetGen> generated.
+
+Analyzing Entity <Core_Top> in library <work> (Architecture <RTL>).
+WARNING:Xst:819 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Core_Top.vhd" line 440: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
+   <hp_rdata>
+Entity <Core_Top> analyzed. Unit <Core_Top> generated.
+
+Analyzing Entity <atari800core> in library <work> (Architecture <bdf_type>).
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 716: Unconnected output port 'dma_clock_out' of component 'antic'.
+WARNING:Xst:754 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected inout port 'SIO_CLOCK' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'IRQ_N_OUT' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'SIO_OUT1' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'SIO_OUT2' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'SIO_OUT3' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'POT_RESET' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 788: Unconnected output port 'keyboard_scan' of component 'pokey'.
+WARNING:Xst:754 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 1076: Unconnected inout port 'SIO_CLOCK' of component 'pokey'.
+WARNING:Xst:819 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd" line 1120: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
+   <KEYBOARD_SCAN>
+Entity <atari800core> analyzed. Unit <atari800core> generated.
+
+Analyzing Entity <cpu> in library <work> (Architecture <vhdl>).
+WARNING:Xst:752 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd" line 89: Unconnected input port 'so_n' of component 'cpu_65xx' is tied to default value.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd" line 89: Unconnected output port 'debug_flags' of component 'cpu_65xx'.
+Entity <cpu> analyzed. Unit <cpu> generated.
+
+Analyzing generic Entity <cpu_65xx> in library <work> (Architecture <rtl>).
+	pipelineAluMux = false
+	pipelineAluOut = false
+	pipelineOpcode = false
+Entity <cpu_65xx> analyzed. Unit <cpu_65xx> generated.
+
+Analyzing Entity <antic> in library <work> (Architecture <vhdl>).
+Entity <antic> analyzed. Unit <antic> generated.
+
+Analyzing generic Entity <antic_counter.1> in library <work> (Architecture <vhdl>).
+	COUNT_WIDTH = 12
+	STORE_WIDTH = 16
+Entity <antic_counter.1> analyzed. Unit <antic_counter.1> generated.
+
+Analyzing generic Entity <antic_counter.2> in library <work> (Architecture <vhdl>).
+	COUNT_WIDTH = 10
+	STORE_WIDTH = 16
+Entity <antic_counter.2> analyzed. Unit <antic_counter.2> generated.
+
+Analyzing generic Entity <simple_counter.1> in library <work> (Architecture <vhdl>).
+	COUNT_WIDTH = 8
+Entity <simple_counter.1> analyzed. Unit <simple_counter.1> generated.
+
+Analyzing generic Entity <simple_counter.2> in library <work> (Architecture <vhdl>).
+	COUNT_WIDTH = 4
+Entity <simple_counter.2> analyzed. Unit <simple_counter.2> generated.
+
+Analyzing generic Entity <wide_delay_line.1> in library <work> (Architecture <vhdl>).
+	COUNT = 16
+	WIDTH = 2
+Entity <wide_delay_line.1> analyzed. Unit <wide_delay_line.1> generated.
+
+Analyzing Entity <antic_dma_clock> in library <work> (Architecture <vhdl>).
+Entity <antic_dma_clock> analyzed. Unit <antic_dma_clock> generated.
+
+Analyzing generic Entity <reg_file.3> in library <work> (Architecture <vhdl>).
+	BYTES = 48
+	WIDTH = 6
+Entity <reg_file.3> analyzed. Unit <reg_file.3> generated.
+
+Analyzing generic Entity <complete_address_decoder.5> in library <work> (Architecture <tree>).
+	width = 6
+Entity <complete_address_decoder.5> analyzed. Unit <complete_address_decoder.5> generated.
+
+Analyzing generic Entity <wide_delay_line.2> in library <work> (Architecture <vhdl>).
+	COUNT = 16
+	WIDTH = 4
+Entity <wide_delay_line.2> analyzed. Unit <wide_delay_line.2> generated.
+
+Analyzing generic Entity <wide_delay_line.3> in library <work> (Architecture <vhdl>).
+	COUNT = 32
+	WIDTH = 7
+Entity <wide_delay_line.3> analyzed. Unit <wide_delay_line.3> generated.
+
+Analyzing generic Entity <complete_address_decoder.2> in library <work> (Architecture <tree>).
+	width = 4
+Entity <complete_address_decoder.2> analyzed. Unit <complete_address_decoder.2> generated.
+
+Analyzing generic Entity <delay_line.1> in library <work> (Architecture <vhdl>).
+	COUNT = 24
+Entity <delay_line.1> analyzed. Unit <delay_line.1> generated.
+
+Analyzing Entity <pokey_mixer> in library <work> (Architecture <vhdl>).
+Entity <pokey_mixer> analyzed. Unit <pokey_mixer> generated.
+
+Analyzing Entity <zpu_glue> in library <work> (Architecture <sticky>).
+WARNING:Xst:819 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_glue.vhdl" line 208: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
+   <special_mem>
+Entity <zpu_glue> analyzed. Unit <zpu_glue> generated.
+
+Analyzing generic Entity <ZPUMediumCore> in library <work> (Architecture <behave>).
+	ADDR_W = 24
+	BINOP_PIPE = 0
+	D_CARE_VAL = 'D'
+	ENA_IDLE = false
+	ENA_LEVEL0 = true
+	ENA_LEVEL1 = true
+	ENA_LEVEL2 = true
+	ENA_LSHR = true
+	FAST_FETCH = true
+	MEM_W = 16
+	MULT_PIPE = false
+	WORD_SIZE = 32
+INFO:Xst:1749 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" line 339: report: read/write collision
+INFO:Xst:1749 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" line 857: report: Illegal decode instruction?!
+INFO:Xst:1749 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd" line 954: report: Illegal state?!
+INFO:Xst:2679 - Register <short_write_r> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <mult_a_r> in unit <ZPUMediumCore> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <mult_b_r> in unit <ZPUMediumCore> has a constant value of 00000000000000000000000000000000 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<31>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<30>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<29>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<28>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<27>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<26>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<25>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<24>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<1>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <dbg_o.sp<0>> in unit <ZPUMediumCore> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <insns<0>> in unit <ZPUMediumCore> has a constant value of 100101 during circuit operation. The register is replaced by logic.
+Entity <ZPUMediumCore> analyzed. Unit <ZPUMediumCore> generated.
+
+Analyzing Entity <pokey> in library <work> (Architecture <vhdl>).
+Entity <pokey> analyzed. Unit <pokey> generated.
+
+Analyzing generic Entity <pokey_countdown_timer> in library <work> (Architecture <vhdl>).
+	UNDERFLOW_DELAY = 3
+Entity <pokey_countdown_timer> analyzed. Unit <pokey_countdown_timer> generated.
+
+Analyzing generic Entity <delay_line.2> in library <work> (Architecture <vhdl>).
+	COUNT = 3
+Entity <delay_line.2> analyzed. Unit <delay_line.2> generated.
+
+Analyzing Entity <pokey_noise_filter> in library <work> (Architecture <vhdl>).
+Entity <pokey_noise_filter> analyzed. Unit <pokey_noise_filter> generated.
+
+Analyzing generic Entity <syncreset_enable_divider.1> in library <work> (Architecture <vhdl>).
+	COUNT = 28
+	RESETCOUNT = 6
+Entity <syncreset_enable_divider.1> analyzed. Unit <syncreset_enable_divider.1> generated.
+
+Analyzing generic Entity <syncreset_enable_divider.2> in library <work> (Architecture <vhdl>).
+	COUNT = 114
+	RESETCOUNT = 33
+Entity <syncreset_enable_divider.2> analyzed. Unit <syncreset_enable_divider.2> generated.
+
+Analyzing Entity <poly_17_9> in library <work> (Architecture <vhdl>).
+Entity <poly_17_9> analyzed. Unit <poly_17_9> generated.
+
+Analyzing Entity <poly_5> in library <work> (Architecture <vhdl>).
+Entity <poly_5> analyzed. Unit <poly_5> generated.
+
+Analyzing Entity <poly_4> in library <work> (Architecture <vhdl>).
+Entity <poly_4> analyzed. Unit <poly_4> generated.
+
+Analyzing generic Entity <delay_line.3> in library <work> (Architecture <vhdl>).
+	COUNT = 2
+Entity <delay_line.3> analyzed. Unit <delay_line.3> generated.
+
+Analyzing Entity <synchronizer> in library <work> (Architecture <vhdl>).
+Entity <synchronizer> analyzed. Unit <synchronizer> generated.
+
+Analyzing Entity <pokey_keyboard_scanner> in library <work> (Architecture <vhdl>).
+INFO:Xst:1561 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_keyboard_scanner.vhdl" line 151: Mux is complete : default of case is discarded
+Entity <pokey_keyboard_scanner> analyzed. Unit <pokey_keyboard_scanner> generated.
+
+Analyzing Entity <pia> in library <work> (Architecture <vhdl>).
+Entity <pia> analyzed. Unit <pia> generated.
+
+Analyzing generic Entity <complete_address_decoder.3> in library <work> (Architecture <tree>).
+	width = 2
+Entity <complete_address_decoder.3> analyzed. Unit <complete_address_decoder.3> generated.
+
+Analyzing Entity <shared_enable> in library <work> (Architecture <vhdl>).
+Entity <shared_enable> analyzed. Unit <shared_enable> generated.
+
+Analyzing generic Entity <enable_divider.1> in library <work> (Architecture <vhdl>).
+	COUNT = 2
+Entity <enable_divider.1> analyzed. Unit <enable_divider.1> generated.
+
+Analyzing generic Entity <enable_divider.2> in library <work> (Architecture <vhdl>).
+	COUNT = 16
+Entity <enable_divider.2> analyzed. Unit <enable_divider.2> generated.
+
+Analyzing generic Entity <delay_line.4> in library <work> (Architecture <vhdl>).
+	COUNT = 15
+Entity <delay_line.4> analyzed. Unit <delay_line.4> generated.
+
+Analyzing generic Entity <delay_line.5> in library <work> (Architecture <vhdl>).
+	COUNT = 8
+Entity <delay_line.5> analyzed. Unit <delay_line.5> generated.
+
+Analyzing Entity <address_decoder> in library <work> (Architecture <vhdl>).
+Entity <address_decoder> analyzed. Unit <address_decoder> generated.
+
+Analyzing Entity <zpu_rom> in library <work> (Architecture <syn>).
+Entity <zpu_rom> analyzed. Unit <zpu_rom> generated.
+
+Analyzing generic Entity <generic_ram_infer.1> in library <work> (Architecture <rtl>).
+	ADDRESS_WIDTH = 10
+	DATA_WIDTH = 8
+	SPACE = 1024
+Entity <generic_ram_infer.1> analyzed. Unit <generic_ram_infer.1> generated.
+
+Analyzing Entity <zpu_config_regs> in library <work> (Architecture <vhdl>).
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'keyboard_scan' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_0_OUT' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_1_OUT' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_2_OUT' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'CHANNEL_3_OUT' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'IRQ_N_OUT' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'SIO_OUT2' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'SIO_OUT3' of component 'pokey'.
+WARNING:Xst:754 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected inout port 'SIO_CLOCK' of component 'pokey'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl" line 270: Unconnected output port 'POT_RESET' of component 'pokey'.
+Entity <zpu_config_regs> analyzed. Unit <zpu_config_regs> generated.
+
+Analyzing generic Entity <complete_address_decoder.1> in library <work> (Architecture <tree>).
+	width = 3
+Entity <complete_address_decoder.1> analyzed. Unit <complete_address_decoder.1> generated.
+
+Analyzing Entity <gtia> in library <work> (Architecture <vhdl>).
+Entity <gtia> analyzed. Unit <gtia> generated.
+
+Analyzing generic Entity <complete_address_decoder.4> in library <work> (Architecture <tree>).
+	width = 5
+Entity <complete_address_decoder.4> analyzed. Unit <complete_address_decoder.4> generated.
+
+Analyzing Entity <gtia_player> in library <work> (Architecture <vhdl>).
+Entity <gtia_player> analyzed. Unit <gtia_player> generated.
+
+Analyzing Entity <gtia_priority> in library <work> (Architecture <vhdl>).
+Entity <gtia_priority> analyzed. Unit <gtia_priority> generated.
+
+Analyzing generic Entity <wide_delay_line.4> in library <work> (Architecture <vhdl>).
+	COUNT = 2
+	WIDTH = 6
+Entity <wide_delay_line.4> analyzed. Unit <wide_delay_line.4> generated.
+
+Analyzing generic Entity <wide_delay_line.5> in library <work> (Architecture <vhdl>).
+	COUNT = 3
+	WIDTH = 2
+Entity <wide_delay_line.5> analyzed. Unit <wide_delay_line.5> generated.
+
+Analyzing generic Entity <wide_delay_line.6> in library <work> (Architecture <vhdl>).
+	COUNT = 4
+	WIDTH = 2
+Entity <wide_delay_line.6> analyzed. Unit <wide_delay_line.6> generated.
+
+Analyzing generic Entity <wide_delay_line.7> in library <work> (Architecture <vhdl>).
+	COUNT = 2
+	WIDTH = 7
+Entity <wide_delay_line.7> analyzed. Unit <wide_delay_line.7> generated.
+
+Analyzing generic Entity <wide_delay_line.8> in library <work> (Architecture <vhdl>).
+	COUNT = 5
+	WIDTH = 8
+Entity <wide_delay_line.8> analyzed. Unit <wide_delay_line.8> generated.
+
+Analyzing generic Entity <wide_delay_line.9> in library <work> (Architecture <vhdl>).
+	COUNT = 4
+	WIDTH = 8
+Entity <wide_delay_line.9> analyzed. Unit <wide_delay_line.9> generated.
+
+Analyzing Entity <gtia_palette> in library <work> (Architecture <altirra>).
+Entity <gtia_palette> analyzed. Unit <gtia_palette> generated.
+
+Analyzing Entity <irq_glue> in library <work> (Architecture <vhdl>).
+Entity <irq_glue> analyzed. Unit <irq_glue> generated.
+
+Analyzing generic Entity <reg_file.1> in library <work> (Architecture <vhdl>).
+	BYTES = 16
+	WIDTH = 4
+Entity <reg_file.1> analyzed. Unit <reg_file.1> generated.
+
+Analyzing generic Entity <reg_file.2> in library <work> (Architecture <vhdl>).
+	BYTES = 32
+	WIDTH = 5
+Entity <reg_file.2> analyzed. Unit <reg_file.2> generated.
+
+Analyzing Entity <internalromram> in library <work> (Architecture <vhdl>).
+Entity <internalromram> analyzed. Unit <internalromram> generated.
+
+Analyzing Entity <basic> in library <work> (Architecture <syn>).
+Entity <basic> analyzed. Unit <basic> generated.
+
+Analyzing Entity <os16> in library <work> (Architecture <syn>).
+Entity <os16> analyzed. Unit <os16> generated.
+
+Analyzing generic Entity <generic_ram_infer.2> in library <work> (Architecture <rtl>).
+	ADDRESS_WIDTH = 14
+	DATA_WIDTH = 8
+	SPACE = 16384
+Entity <generic_ram_infer.2> analyzed. Unit <generic_ram_infer.2> generated.
+
+Analyzing Entity <covox> in library <work> (Architecture <vhdl>).
+Entity <covox> analyzed. Unit <covox> generated.
+
+Analyzing generic Entity <Replay_TranslatePS2> in library <work> (Architecture <RTL>).
+	g_kb_map = ("11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01100111",
+	            "11111111",
+	            "01010111",
+	            "11111111",
+	            "01000111",
+	            "11111111",
+	            "01000110",
+	            "01000000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000110",
+	            "01110111",
+	            "01000110",
+	            "01100000",
+	            "01000110",
+	            "01010111",
+	            "00110000",
+	            "11111111",
+	            "00000110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110001",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00100000",
+	            "11111111",
+	            "01100000",
+	            "11111111",
+	            "00000000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000001",
+	            "11111111",
+	            "01010001",
+	            "11111111",
+	            "00100001",
+	            "11111111",
+	            "00010001",
+	            "11111111",
+	            "01110000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000010",
+	            "11111111",
+	            "00110010",
+	            "11111111",
+	            "00100010",
+	            "11111111",
+	            "01100001",
+	            "11111111",
+	            "01110001",
+	            "11111111",
+	            "00000001",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000000",
+	            "11111111",
+	            "00110011",
+	            "11111111",
+	            "01010010",
+	            "11111111",
+	            "01100010",
+	            "11111111",
+	            "00010010",
+	            "11111111",
+	            "00000010",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110100",
+	            "11111111",
+	            "01000011",
+	            "11111111",
+	            "01010011",
+	            "11111111",
+	            "00100011",
+	            "11111111",
+	            "00010011",
+	            "11111111",
+	            "01110010",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000100",
+	            "11111111",
+	            "00100100",
+	            "11111111",
+	            "01100011",
+	            "11111111",
+	            "00000011",
+	            "11111111",
+	            "01110011",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110101",
+	            "11111111",
+	            "01010100",
+	            "11111111",
+	            "00010100",
+	            "11111111",
+	            "01100100",
+	            "11111111",
+	            "01110100",
+	            "11111111",
+	            "00000100",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000101",
+	            "11111111",
+	            "00110110",
+	            "11111111",
+	            "00100101",
+	            "11111111",
+	            "00100110",
+	            "11111111",
+	            "00010101",
+	            "11111111",
+	            "00000101",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010101",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01100101",
+	            "11111111",
+	            "01110101",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11000000",
+	            "11111111",
+	            "01000110",
+	            "11111111",
+	            "00010111",
+	            "11111111",
+	            "00010110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01100110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00000111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "10000100",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "10000010",
+	            "11111111",
+	            "10010000",
+	            "11111111",
+	            "10001000",
+	            "11111111",
+	            "10000001",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01110111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00100000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00000111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01000110",
+	            "00100111",
+	            "01110110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00110111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "00100111",
+	            "11111111",
+	            "01000110",
+	            "00110111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "01010110",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "10100000",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111",
+	            "11111111")
+Entity <Replay_TranslatePS2> analyzed. Unit <Replay_TranslatePS2> generated.
+
+Analyzing generic Entity <Replay_VideoConverter> in library <work> (Architecture <RTL>).
+	g_b_bitwidth = 8
+	g_g_bitwidth = 8
+	g_hadr_width = 9
+	g_hoffset = 0
+	g_hscale = "010000000"
+	g_hsize = 900
+	g_loffset = 0
+	g_match_line = 0
+	g_r_bitwidth = 8
+	g_vadr_width = 2
+	g_vid_param_hd = (rep_h => '0'
+	                  total_h => 864
+	                  active_h => 720
+	                  syncp_h => 12
+	                  syncw_h => 64
+	                  total_v => 625
+	                  active_v => 576
+	                  fline_f1_v => 44
+	                  lline_f1_v => 620
+	                  fline_f2_v => 0
+	                  lline_f2_v => 0
+	                  start_f1_v => 625
+	                  start_f2_v => 0
+	                  fsync_f1_v => 625
+	                  lsync_f1_v => 5
+	                  fsync_f2_v => 0
+	                  lsync_f2_v => 0
+	                  syncpol_h => '0'
+	                  syncpol_v => '0'
+	                  progressive => '1')
+	g_vid_param_sd = (rep_h => '1'
+	                  total_h => 1728
+	                  active_h => 1440
+	                  syncp_h => 24
+	                  syncw_h => 126
+	                  total_v => 625
+	                  active_v => 576
+	                  fline_f1_v => 22
+	                  lline_f1_v => 310
+	                  fline_f2_v => 335
+	                  lline_f2_v => 623
+	                  start_f1_v => 623
+	                  start_f2_v => 310
+	                  fsync_f1_v => 625
+	                  lsync_f1_v => 3
+	                  fsync_f2_v => 312
+	                  lsync_f2_v => 315
+	                  syncpol_h => '0'
+	                  syncpol_v => '0'
+	                  progressive => '0')
+	g_voffset = 21
+	g_vres_half = 1
+	g_vsize = 248
+WARNING:Xst:752 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoConverter.vhd" line 392: Unconnected input port 'i_f2_flip' of component 'Replay_VideoTiming' is tied to default value.
+Entity <Replay_VideoConverter> analyzed. Unit <Replay_VideoConverter> generated.
+
+Analyzing generic Entity <Replay_VideoTiming> in library <work> (Architecture <RTL>).
+	g_enabledynamic = '1'
+	g_param = (rep_h => '0'
+	           total_h => 800
+	           active_h => 640
+	           syncp_h => 16
+	           syncw_h => 96
+	           total_v => 525
+	           active_v => 480
+	           fline_f1_v => 42
+	           lline_f1_v => 522
+	           fline_f2_v => 0
+	           lline_f2_v => 0
+	           start_f1_v => 525
+	           start_f2_v => 0
+	           fsync_f1_v => 7
+	           lsync_f1_v => 9
+	           fsync_f2_v => 0
+	           lsync_f2_v => 0
+	           syncpol_h => '0'
+	           syncpol_v => '0'
+	           progressive => '1')
+Entity <Replay_VideoTiming> analyzed. Unit <Replay_VideoTiming> generated.
+
+Analyzing Entity <Replay_JoyPS2> in library <work> (Architecture <RTL>).
+Entity <Replay_JoyPS2> analyzed. Unit <Replay_JoyPS2> generated.
+
+Analyzing generic Entity <Replay_JoyPS2_Core.1> in library <work> (Architecture <RTL>).
+	g_id = '0'
+Entity <Replay_JoyPS2_Core.1> analyzed. Unit <Replay_JoyPS2_Core.1> generated.
+
+Analyzing Entity <kcpsm3> in library <work> (Architecture <low_level_definition>).
+    Set user-defined property "INIT =  1" for instance <t_state_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <toggle_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  1" for instance <reset_flop1> in unit <kcpsm3>.
+    Set user-defined property "INIT =  1" for instance <reset_flop2> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <int_capture_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0080" for instance <int_pulse_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <int_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <ack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shadow_carry_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shadow_zero_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  EAAA" for instance <int_update_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  04" for instance <int_value_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <int_enable_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  7400" for instance <move_group_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  5A3C" for instance <condition_met_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  2F" for instance <normal_count_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  1000" for instance <call_type_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  5400" for instance <push_pop_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  D" for instance <valid_move_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  41FC" for instance <flag_type_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <flag_write_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  8" for instance <flag_enable_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0001" for instance <low_zero_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0001" for instance <high_zero_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  3F" for instance <sel_shadow_zero_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <zero_flag_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6996" for instance <low_parity_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6996" for instance <high_parity_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  F3FF" for instance <sel_parity_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  F3" for instance <sel_arith_carry_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  C" for instance <sel_shift_carry_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  3" for instance <sel_shadow_carry_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <carry_flag_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[0].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[0].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[0].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[1].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[1].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[1].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[2].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[2].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[2].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[3].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[3].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[3].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[4].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[4].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[4].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[5].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[5].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[5].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[6].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[6].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[6].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[7].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[7].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[7].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[8].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[8].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[8].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[9].vector_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <pc_loop[9].value_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pc_loop[9].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0145" for instance <register_type_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <register_write_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  8" for instance <register_enable_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[0].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[0].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[1].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[1].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[2].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[2].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[3].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[3].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[4].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[4].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[5].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[5].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[6].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[6].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0000" for instance <reg_loop[7].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <reg_loop[7].operand_select_mux> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0400" for instance <memory_type_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <memory_write_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  8000" for instance <memory_enable_lut> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[0].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[0].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[0].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[1].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[1].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[1].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[2].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[2].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[2].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[3].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[3].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[3].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[4].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[4].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[4].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[5].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[5].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[5].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[6].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[6].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[6].store_flop> in unit <kcpsm3>.
+WARNING:Xst:1962 - The length of the hex value for the attribute INIT on instance store_loop[7].memory_bit should be 32 bits long. The current value set is 16 bits long.  Value has been extended
+    Set user-defined property "INIT =  00000000" for instance <store_loop[7].memory_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <store_loop[7].store_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FFE2" for instance <sel_logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[0].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[0].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[1].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[1].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[2].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[2].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[3].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[3].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[4].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[4].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[5].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[5].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[6].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[6].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6E8A" for instance <logical_loop[7].logical_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <logical_loop[7].logical_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <high_shift_in_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <low_shift_in_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_carry_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <pipeline_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[0].lsb_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[0].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[1].mid_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[1].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[2].mid_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[2].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[3].mid_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[3].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[4].mid_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[4].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[5].mid_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[5].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[6].mid_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[6].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <shift_loop[7].msb_shift.shift_mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <shift_loop[7].shift_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  1F" for instance <sel_arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6C" for instance <arith_loop[0].lsb_arith.arith_carry_in_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[0].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[0].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[1].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[1].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[2].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[2].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[3].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[3].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[4].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[4].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[5].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[5].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[6].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[6].arith_flop> in unit <kcpsm3>.
+WARNING:Xst:1961 - The length of the hex value for the attribute INIT on instance arith_loop[7].msb_arith.arith_carry_out_lut should be 2 bits long. The current value set is 4 bits long.  Value has been truncated
+    Set user-defined property "INIT =  2" for instance <arith_loop[7].msb_arith.arith_carry_out_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[7].msb_arith.arith_carry_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  96" for instance <arith_loop[7].arith_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <arith_loop[7].arith_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0002" for instance <input_fetch_type_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <sel_group_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[0].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[0].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[1].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[1].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[2].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[2].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[3].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[3].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[4].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[4].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[5].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[5].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[6].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[6].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  FE" for instance <alu_mux_loop[7].or_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  E4" for instance <alu_mux_loop[7].mux_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0010" for instance <io_decode_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  4000" for instance <write_active_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <write_strobe_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0100" for instance <read_active_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <read_strobe_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[0].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[0].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[1].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[1].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[2].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[2].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[3].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[3].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[4].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[4].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[5].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[5].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[6].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[6].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[7].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[7].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[8].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[8].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  00000000" for instance <stack_ram_loop[9].stack_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_ram_loop[9].stack_flop> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_count_loop[0].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  6555" for instance <stack_count_loop[0].lsb_stack_count.count_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_count_loop[1].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  A999" for instance <stack_count_loop[1].mid_stack_count.count_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_count_loop[2].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  A999" for instance <stack_count_loop[2].mid_stack_count.count_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_count_loop[3].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  A999" for instance <stack_count_loop[3].mid_stack_count.count_lut> in unit <kcpsm3>.
+    Set user-defined property "INIT =  0" for instance <stack_count_loop[4].register_bit> in unit <kcpsm3>.
+    Set user-defined property "INIT =  A999" for instance <stack_count_loop[4].msb_stack_count.count_lut> in unit <kcpsm3>.
+Entity <kcpsm3> analyzed. Unit <kcpsm3> generated.
+
+Analyzing generic Entity <Replay_JoyPS2_Core.2> in library <work> (Architecture <RTL>).
+	g_id = '1'
+Entity <Replay_JoyPS2_Core.2> analyzed. Unit <Replay_JoyPS2_Core.2> generated.
+
+Analyzing Entity <ps2_rom> in library <work> (Architecture <low_level_definition>).
+    Set user-defined property "INITP_00 =  E8F3CF3CF3CA3DDF0DDFC3CBCF2D34F4AA834F2B0F550C3F4DF8FC38D82AAAA3" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_01 =  E0213FF8E38E2822A80222940D08A940D08A8A3774AD22377FB78844903C2F28" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_02 =  37649AA08DAAAD2777748B72DCB4BC3B0B0BC2570E5C3F93F93F93A38FFE363F" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_03 =  00000000000000000000000000000000000300D23554348A50D2AA8A214228DA" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INITP_07 =  C000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_00 =  5C0DC101F0100000011FC083C082C081C080C010C008C004C002C0010000C000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_01 =  4100610110A74101008B0052C002000101200114014200D00107C001C0040001" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_02 =  61096008C00058364380F310D200A32763076206C00161096008C000401B5022" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_03 =  000E000E000E000E000EA0E04001581B20026000009C00E70FF4E107E006C001" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_04 =  00E76F05009C00E70FEDE005505121104101505121084101401B144450106105" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_05 =  00F40101548740AA54584101008B0135012600100127009C00E70FFFA000009C" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_06 =  009C00E70F02009C00E70FE8C008E00000030098547F4000547F4101008B0142" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_07 =  0098A000E00F0000009C00E70FF4009C00E70F64009C00E70FF3009C00E70FE6" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_08 =  B00050206204600301004000014200F40101A000009C00E70F00C008E0000001" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_09 =  4101008B0135013EA00050984101008BA0000101E204A2078201701091200110" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_0A =  410150B64100610FA000C04058AC21026100A0000001A000000054A540FA549D" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_0B =  50C122100100620EE10F0102A000E00EE10F0101A000E10F010050C8410250BA" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_0C =  620C01FF50CF22200100620EE10F0100A000E30BE20AB3109200630B620A01FF" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_0D =  010601060106A10F610DA00F600BC081600CC080600AE30DE20CF310D200630D" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_0E =  014CC11001030151C11001020114C0020000A000C083A007600EC082D0100106" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_0F =  0114C110E101A101EF800F0811F02FFF0E080148011A014801140148C1100101" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_10 =  C201020101200114011A01140148C11001005CFCCE010F0811F00148011A0148" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_11 =  411B0135B00021084101013A41150135B40021084101013AA000C00200010148" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_12 =  61096008C000A000B5109400C00165096408C00041210135B40021104101013A" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_13 =  00F40101A000012600FA0100A0005C00012D13501240A0004380F310D200C001" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_14 =  554DC10101480114A0005549C001000BA0005943012D135012400126A0000126" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_15 =  410B5187410A51764109516C41006101C2010201A0005552C101014801C8A000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_16 =  E101010155752004A000E202020FA000E202020E556920046202E10181015192" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_17 =  020B5581220155822004020022FF6202E1018101A000A000E107E00661096008" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_18 =  6102E203A2078201932003106203E1010100A000F2F0020B51862201A000F2F0" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_19 =  A10080016109600851B120024001E31FE21EE11DE01CA000E1010100A000F130" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_1A =  010059B14380F310D200A30082FA6307620651B142006201C2010202E109E008" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_1B =  00000000000000000000000000008001601C611D621E631F155620014001E101" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_3F =  4195000000000000000000000000000000000000000000000000000000000000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_A =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "INIT_B =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "SRVAL_A =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "SRVAL_B =  00000" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <ram_1024_x_18> in unit <ps2_rom>.
+    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <ram_1024_x_18> in unit <ps2_rom>.
+Entity <ps2_rom> analyzed. Unit <ps2_rom> generated.
+
+Analyzing generic Entity <Replay_DDRCtrl_Top> in library <work> (Architecture <rtl>).
+	g_lp_big_endian = '1'
+INFO:Xst:2679 - Register <o_cfg_present> in unit <Replay_DDRCtrl_Top> has a constant value of 1 during circuit operation. The register is replaced by logic.
+Entity <Replay_DDRCtrl_Top> analyzed. Unit <Replay_DDRCtrl_Top> generated.
+
+Analyzing Entity <Replay_DDRCtrl> in library <work> (Architecture <rtl>).
+    Set user-defined property "INIT =  0" for instance <u_ack_reg> in unit <Replay_DDRCtrl>.
+Entity <Replay_DDRCtrl> analyzed. Unit <Replay_DDRCtrl> generated.
+
+Analyzing Entity <Replay_DDRCtrl_Datapath> in library <work> (Architecture <rtl>).
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[0].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[0].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[1].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[1].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[2].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[2].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[3].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[3].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[4].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[4].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[5].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[5].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[6].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[6].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[7].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[7].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[8].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[8].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[9].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[9].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[10].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[10].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[11].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[11].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[12].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[12].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[13].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[13].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[14].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[14].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[15].fdp_dq_oe0_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_oe_l_t1[15].fdp_dq_oe1_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <fdp_ram_ras_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <fdp_ram_cas_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <fdp_ram_we_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <fdp_ram_cs_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdc_ram_cke> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_ras_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_cas_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_we_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_cs_l> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_cke> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_ba[0].fdc_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_ba[0].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_ba[1].fdc_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_ba[1].obuf_ram_ba> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[0].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[0].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[1].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[1].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[2].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[2].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[3].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[3].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[4].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[4].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[5].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[5].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[6].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[6].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[7].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[7].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[8].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[8].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[9].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[9].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[10].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[10].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[11].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[11].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fdcs_ram_addr[12].fdc_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <fdcs_ram_addr[12].obuf_ram_addr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_ck_p_oddr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <u_ck_p_oddr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <u_ck_p_oddr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_ck_n_oddr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <u_ck_n_oddr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <u_ck_n_oddr> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_ck_p> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <obuf_ck_n> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dm[0].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dm[0].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dm[0].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dm[0].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dm[1].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dm[1].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dm[1].oddr_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dm[1].obuf_dm> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[0].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dqs_w[0].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[0].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[0].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dqs_w[0].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[0].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dqs_w[0].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[1].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dqs_w[1].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[1].oddr_dqs_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_w[1].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dqs_w[1].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_w[1].oddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dqs_w[1].obuft_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[0].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[0].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[0].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[0].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[0].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[0].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[0].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[1].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[1].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[1].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[1].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[1].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[1].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[1].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[2].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[2].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[2].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[2].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[2].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[2].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[2].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[3].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[3].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[3].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[3].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[3].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[3].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[3].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[4].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[4].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[4].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[4].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[4].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[4].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[4].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[5].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[5].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[5].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[5].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[5].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[5].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[5].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[6].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[6].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[6].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[6].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[6].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[6].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[6].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[7].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[7].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[7].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[7].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[7].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[7].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[7].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[8].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[8].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[8].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[8].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[8].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[8].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[8].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[9].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[9].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[9].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[9].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[9].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[9].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[9].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[10].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[10].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[10].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[10].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[10].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[10].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[10].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[11].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[11].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[11].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[11].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[11].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[11].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[11].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[12].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[12].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[12].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[12].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[12].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[12].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[12].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[13].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[13].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[13].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[13].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[13].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[13].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[13].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[14].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[14].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[14].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[14].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[14].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[14].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[14].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[15].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[15].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[15].oddr_dq_oe> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_w[15].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  1" for instance <gen_dq_w[15].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_w[15].oddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DRIVE =  12" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SLEW =  SLOW" for instance <gen_dq_w[15].obuft_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_r[0].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_r[0].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dqs_r[1].ibuf_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dqs_r[1].iddr_dqs> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_t1_ena_1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t1_ena_1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X0Y0" for instance <fd_dq_t1_ena_1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_t1_ena> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t1_ena> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X1Y0" for instance <fd_dq_t1_ena> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_t2_ena_1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t2_ena_1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X0Y0" for instance <fd_dq_t2_ena_1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_t2_ena> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_t2_ena> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X1Y0" for instance <fd_dq_t2_ena> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_sel0> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_sel1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  F0CA" for instance <lut4_dq_mux1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <lut4_dq_mux1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X2Y0" for instance <lut4_dq_mux1> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  F0CA" for instance <lut4_dq_mux2> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <lut4_dq_mux2> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X2Y0" for instance <lut4_dq_mux2> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <muxf5_dq_mux> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X2Y0" for instance <muxf5_dq_mux> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_ena_cc> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "U_SET =  dram_mux" for instance <fd_dq_ena_cc> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "RLOC =  X2Y0" for instance <fd_dq_ena_cc> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[0].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[0].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[1].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[1].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[2].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[2].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[3].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[3].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[4].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[4].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[5].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[5].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[6].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[6].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[7].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[7].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[8].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[8].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[9].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[9].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[10].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[10].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[11].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[11].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[12].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[12].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[13].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[13].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[14].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[14].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "CAPACITANCE =  DONT_CARE" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_DELAY_VALUE =  0" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IBUF_LOW_PWR =  TRUE" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IFD_DELAY_VALUE =  AUTO" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "IOSTANDARD =  DEFAULT" for instance <gen_dq_r[15].ibuf_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q0 =  1" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT_Q1 =  1" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <gen_dq_r[15].iddr_dq> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_we> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0" for instance <fd_dq_st> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[0].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[1].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[2].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[3].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[4].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[5].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[6].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[7].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[8].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[9].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[10].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[11].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[12].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[13].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[14].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[15].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[16].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[17].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[18].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[19].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[20].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[21].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[22].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[23].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[24].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[25].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[26].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[27].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[28].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[29].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[30].inst> in unit <Replay_DDRCtrl_Datapath>.
+    Set user-defined property "INIT =  0000" for instance <rbuf[31].inst> in unit <Replay_DDRCtrl_Datapath>.
+Entity <Replay_DDRCtrl_Datapath> analyzed. Unit <Replay_DDRCtrl_Datapath> generated.
+
+Analyzing generic Entity <Replay_Syscon> in library <work> (Architecture <RTL>).
+	g_cfg_ctrl = "0000000010000000"
+	g_cfg_dynamic = "00000000000000000000000000000000"
+	g_cfg_fileio = "00000000"
+	g_cfg_static = "00000000000000000000000000000000"
+	g_version = "0000000000000001"
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 235: Unconnected output port 'o_rxbytecnt' of component 'Replay_SPI8'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 235: Unconnected output port 'o_first' of component 'Replay_SPI8'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 317: Unconnected output port 'o_w_full' of component 'FIFO_SyncSRL_D16'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd" line 317: Unconnected output port 'o_w_hfull' of component 'FIFO_SyncSRL_D16'.
+INFO:Xst:2679 - Register <osd_vexp> in unit <Replay_Syscon> has a constant value of 0 during circuit operation. The register is replaced by logic.
+Entity <Replay_Syscon> analyzed. Unit <Replay_Syscon> generated.
+
+Analyzing Entity <Replay_SPI8> in library <work> (Architecture <RTL>).
+Entity <Replay_SPI8> analyzed. Unit <Replay_SPI8> generated.
+
+Analyzing generic Entity <FIFO_SyncSRL_D16> in library <work> (Architecture <RTL>).
+	g_width = 8
+    Set user-defined property "INIT =  0000" for instance <ram[0].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[1].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[2].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[3].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[4].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[5].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[6].inst> in unit <FIFO_SyncSRL_D16>.
+    Set user-defined property "INIT =  0000" for instance <ram[7].inst> in unit <FIFO_SyncSRL_D16>.
+Entity <FIFO_SyncSRL_D16> analyzed. Unit <FIFO_SyncSRL_D16> generated.
+
+Analyzing Entity <Replay_OSD> in library <work> (Architecture <RTL>).
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[0].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[1].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[2].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[3].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[4].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[5].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[6].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_1[7].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_2[0].inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT =  0000" for instance <h_offset_ram_2[1].inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_A =  000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "INIT_B =  00000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "SRVAL_A =  000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "SRVAL_B =  00000" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <CharRam.u_CharRam_inst> in unit <Replay_OSD>.
+Entity <Replay_OSD> analyzed. Unit <Replay_OSD> generated.
+
+Analyzing Entity <FONT0> in library <work> (Architecture <RTL>).
+WARNING:Xst:2211 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font0_rom.vhd" line 269: Instantiating black box module <RAMB16_S2>.
+    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_02 =  0000F0000000F4000000F8000000F8000000F8000000F8000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_03 =  0000000000000000000000000002F8000001F800000050000000B0000000B000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_04 =  0000000000000000002E03C0002E03C0003F0BC0003F0BE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_06 =  2FFFFFFE003C0F00003C0F000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_07 =  000000000000000000000000003C0F00003C0F002FFFFFFE003C0F00003C0F00" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_08 =  002FFE000000FFE00000F0FC03D0F03C02F0F0FC00BFFFF0000AFA000000F000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_09 =  000000000000F000000AFA0000BFFFF403F0F0BD03C0F02E03E0F00001FEF000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_0A =  0002F000000BC000002E2FF800F8FC3F03E0F00F0F80F82F2D002FF800000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_0B =  0000000000000000000000000FFF00383E0BC1F03E0BC7C00FFF1F000000BC00" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_0C =  00000FF00002FEF4000BC07C000F003C000F80FC0002FFE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_0D =  0000000000000000000000000B87FFF40BFE407E02FF400F0BCBF01F0F40BE7D" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_0E =  00000000000000000000F0000000F4000000F8000001F8000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_10 =  000003C0000007C000000F8000001F0000003D000001F400000BC000002E0000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_11 =  002E0000000BC0000001F40000003C0000001F0000000F80000007C0000003C0" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_12 =  003C0000003D0000002F0000000F40000003C0000001F40000003E0000000B80" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_13 =  00000B8000003E000001F4000003C000000F4000002F0000003D0000003C0000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_14 =  03F8B2FD0240B0080000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_15 =  0000000000000000000000000000F0000240B00803F8B2FD001FFF80001FFF80" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_16 =  0000F0000000F0000000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_17 =  0000000000000000000000000000F0000000F0000000F0000000F0000FFFFFFF" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_19 =  00000B8000001F0000003D000000FC000003F000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_1B =  000000000000000000000000000000000000000000000000000000000FFFFFFF" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_1D =  0000000000000000000000000002F8000002F800000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_1E =  0002F0000007C000000F0000003D000000F8000002E0000003C0000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_1F =  000000000000002D000000BC000001F0000003C000000F4000003D000000B800" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_20 =  0F02F40F0F0F800F0FF8002F07D0003D01F802F4002FFF800000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_21 =  000000000000000000000000002FFF8001F801F807C0007D0F8003FF0F002E0F" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_22 =  0000F0000000F06F0000F3FE0000FF800000FC000000F4000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_23 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_24 =  00BF000002F4000003D0000F03C0002F02F801BC002FFFE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_25 =  00000000000000000000000003FFFFFE03C002F803C01FD00280FE00000BE000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_26 =  003FF80001FA000003D0003C03C000BC02F802F4007FFF800000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_27 =  000000000000000000000000006FFF8002F802F003D000BC03C0002802F80000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_28 =  003C02F0003C0BC0003C2F00003CF800003FE000003F40000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_29 =  0000000000000000000000000FFFF000003C0000003C00000FFFFFFE003C007D" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_2A =  0FC000A003F80BF000BFFDF0000000F0000000F00FFFFFF00000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_2B =  000000000000000000000000006FFFD002F402FC0B80003E0F00002A0F000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_2C =  0FC0003F03F806EF007FFE2E0000007C02D007F001FFFE400000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_2D =  000000000000000000000000007FFF8003F401F80F80002D0F00000F0F00000F" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_2E =  0003C000000F4000002E000000B8003C07D0003C0BFFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_2F =  0000000000000000000000000000F0000000F0000002F0000002F0000003E000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_30 =  03F802FC00BFFFE002F802F803C0003C03F401FC00BFFFE00000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_31 =  00000000000000000000000000BFFFE007E401BD0F80002F0F00000F0F80002F" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_32 =  0FC0003F0F00000F0F00000F0780002F01F401FC002FFFD00000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_33 =  000000000000000000000000001BFFF800FD007803D000000B8BFFD00FB902FC" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_34 =  000000000000F0000000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_35 =  0000000000000000000000000000F0000000F000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_36 =  000000000000F0000000F0000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_37 =  00000B4000001F0000007C000000F8000003F000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_38 =  00007E000002F000002F80000078000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_39 =  00000000000000000000000000780000002F80000002F00000007E0000000FC0" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_3A =  000000000FFFFFFF000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_3B =  00000000000000000000000000000000000000000FFFFFFF0000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_3C =  000BE0000000BD0000000F80000002E000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_3D =  000000000000000000000000000002E000000F800000BD00000BE000002F4000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_3E =  002F400000F8000003E0004003C002F003F00BD000BFFE000000000000000000" for instance <rom0.inst> in unit <FONT0>.
+    Set user-defined property "INIT_3F =  0000000000000000000000000000F0000000F0000000A0000001F0000007D000" for instance <rom0.inst> in unit <FONT0>.
+Entity <FONT0> analyzed. Unit <FONT0> generated.
+
+Analyzing Entity <FONT1> in library <work> (Architecture <RTL>).
+WARNING:Xst:2211 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font1_rom.vhd" line 269: Instantiating black box module <RAMB16_S2>.
+    Set user-defined property "INIT_00 =  3CF40F0F3CF01F0F3EF83E2F1FFFF83D0BE002F400BFFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_01 =  00000000000000000000000000BFFF4001E006F00000007C0FFBFC2E3EFD2F0F" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_02 =  02F00BC000F80F4000BC2E00003E7C00001FF800000BF0000000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_03 =  000000000000000000000000BC00003F3E00007C1F4000F80FFFFFF003E003E0" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_04 =  01F9003C003FFFFC02F8003C03C0003C03F8003C00BFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_05 =  000000000000000000000000002FFFFC01F9003C03E0003C03C0003C03E0003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_06 =  0000000F0000000F03C0002F03E0003D03FD02F803DFFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_07 =  000000000000000000000000002FFF8000FD02F803F0003D0180002F0000000F" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_08 =  0F00003C0F00003C0F80003C07D0003C01F9003C002FFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_09 =  000000000000000000000000002FFFFC02F9003C07D0003C0F80003C0F00003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_0A =  002FFFFC0000003C0000003C0000003C0000003C0BFFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_0B =  0000000000000000000000000BFFFFFC0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_0C =  002FFFFC0000003C0000003C0000003C0000003C0BFFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_0D =  0000000000000000000000000000003C0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_0E =  0FFF000F0000000F0F00002F0F80003D0FF402F40F7FFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_0F =  000000000000000000000000002FFF8001F802F807C0003D0F80002F0F00000F" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_10 =  03FFFFFC03C0003C03C0003C03C0003C03C0003C03C0003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_11 =  00000000000000000000000003C0003C03C0003C03C0003C03C0003C03C0003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_12 =  0000F0000000F0000000F0000000F0000000F000003FFFC00000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_13 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_14 =  03C0000003C0000003C0000003C0000003C0000003C000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_15 =  000000000000000000000000002FFFE000F801BC03E0002F03C0000903C00000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_16 =  0000BFFC00007F3C0002F83C001FC03C00BE003C0BF0003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_17 =  0000000000000000000000000BD0003C01F8003C003E003C000FC03C0002F0BC" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_18 =  0000003C0000003C0000003C0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_19 =  0000000000000000000000000BFFFFFC0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_1A =  03C3FC3C03CBAE3C03DF0F7C03FD03FC03F802FC03F000FC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_1B =  00000000000000000000000003C0003C03C0003C03C0003C03C0F03C03C2F83C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_1C =  03C2F03C03C0BC3C03C03F3C03C00FBC03C003FC03C001FC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_1D =  00000000000000000000000003F0003C03FC003C03FE003C03CF803C03C7D03C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_1E =  0F00000F0F00000F0F80002F07C0003D01F802F4002FFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_1F =  000000000000000000000000002FFF8001F802F807C0003D0F80002F0F00000F" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_20 =  00BFFFFC02F9003C03C0003C03C0003C02F8003C007FFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_21 =  0000000000000000000000000000003C0000003C0000003C0000003C0000003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_22 =  0F00000F0F00000F0F80002F07C0003D01F802F4002FFF800000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_23 =  0BFF40000007E0000000F000002FFF8002F906F807D0007D0F80002F0F00000F" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_24 =  006FFFFC02F8003C03C0003C03C0003C02F8003C007FFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_25 =  00000000000000000000000002F0003C00BC003C002F003C0007C03C0001F03C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_26 =  001BFF8000000BFC0000002F03D0000F03F900BE03DFFFE00000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_27 =  000000000000000000000000006FFF8F02F402FF03C0002F03E0000A01FE8000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_28 =  0000F0000000F0000F00F00F0F00F00F0F00F00F0FFFFFFF0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_29 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_2A =  03C0003C03C0003C03C0003C03C0003C03C0003C03C0003C0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_2B =  000000000000000000000000002FFF8001F802F403E000BC03C0003C03C0003C" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_2C =  02F00BC003D003E00BC002F01F0000F83E00007CBC00002F0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_2D =  000000000000000000000000000BF000001FF800003E7C0000BC2E0000F80F40" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_2E =  0F4FF0F41F0BF0FC2F03E0BC3E00003D7C00003EBC00002F0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_2F =  00000000000000000000000002F80FC003FC2FC003FD3FE007DE7EF00F8FB9F0" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_30 =  000BF000000FF400003E3D0000F81F4003F00BC03FFC2FFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_31 =  0000000000000000000000003FF80FFE03F00BD000F81F40003E3D00000FF800" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_32 =  0003FC00000BAE00002F0F8000BC03E001F401F40FFE0BFF0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_33 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_34 =  0000F8000003E000000F403C003D003C00F4003C02FFFFFC0000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_35 =  00000000000000000000000003FFFFFC03C000F803C003E003C00F8000003E00" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_36 =  00003C0000003C0000003C0000003C0000003C0000003C0000003C00000FFC00" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_37 =  000FFC0000003C0000003C0000003C0000003C0000003C0000003C0000003C00" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_38 =  0003D0000000F00000007C0000002F0000000B80000003D0000000F000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_39 =  000000002E0000000F40000003C0000001F0000000BC0000002E0000000F4000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_3A =  0000F0000000F0000000F0000000F0000000F0000000F0000000F0000000FFC0" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_3B =  0000FFC00000F0000000F0000000F0000000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_3C =  0BD0003F02F000FC00BC03F0002F0BC0000FEF000003FC000000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
+    Set user-defined property "INIT_3F =  000000000FFFFFFF000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT1>.
+Entity <FONT1> analyzed. Unit <FONT1> generated.
+
+Analyzing Entity <FONT2> in library <work> (Architecture <RTL>).
+WARNING:Xst:2211 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font2_rom.vhd" line 269: Instantiating black box module <RAMB16_S2>.
+    Set user-defined property "INIT_00 =  00000000000000000000000000000000000F80000002FE0000001B4000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_02 =  03C0000002F400B8007FFFE80000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_03 =  00000000000000000000000003CBFFF803FE003F03E0000F03C002BE03FFFFE4" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_04 =  03E0003C00F901FC002FFFBC0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_05 =  000000000000000000000000002FFFBC00F901FC03E0003C03C0003C03C0003C" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_06 =  03E0002F03F801FC03DFFFE00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_07 =  00000000000000000000000000BFFF9003E402FC0000003F0000000F0280000F" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_08 =  03C0002F03F401FC03EFFFD003C0000003C0000003FF00000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_09 =  00000000000000000000000003EFFFD003F801FC03C0002F03C0000F03C0000F" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_0A =  0BC0002F03F401BC007FFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_0B =  00000000000000000000000000BFFF9003E402FC0000003F0000001F0FFFFFFF" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_0C =  0000F0000000F0000FFFFFC00000F0000007E0000FFF80000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_0D =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_0E =  03C0003F03F801FC03EFFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_0F =  002FFFE002F902BD03D0000403EFFFE003F801BC03C0002F03C0000F03C0000F" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_10 =  03C000FC02F40BBC00BFFE3C0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_11 =  00000000000000000000000003C0003C03C0003C03C0003C03C0003C03C0007C" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_12 =  0000F0000000F0000000FFC0000000000000F0000000F0000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_13 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_14 =  003C0000003C0000003FF00000000000003C0000003C00000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_15 =  0007FFF4002F80BE003D0004003C0000003C0000003C0000003C0000003C0000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_16 =  000BF03C00BF403C0BF8003C0000003C0000003C0000003C0000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_17 =  0000000000000000000000000BF0003C00BE003C000FC0BC0002FBFC0000BE3C" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_18 =  0000F0000000F0000000F0000000F0000000F0000000FFC00000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_19 =  000000000000000000000000003FFFC00000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_1A =  0F01F01F0F83F83F07FE7FEF0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_1B =  0000000000000000000000000F00F00F0F00F00F0F00F00F0F00F00F0F00F00F" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_1C =  03C000FC02F40BBC00BFFE3C0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_1D =  00000000000000000000000003C0003C03C0003C03C0003C03C0003C03C0007C" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_1E =  0FC0003F03F801FC007FFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_1F =  000000000000000000000000007FFFD003F401FC0F80002F0F00000F0F00000F" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_20 =  03E0003C00F901FC002FFFBC0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_21 =  0000003C0000003C0000003C002FFFBC00F901FC03E0003C03C0003C03C0003C" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_22 =  03C0002F03F401FC03EFFFD00000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_23 =  03C0000003C0000003C0000003EFFFD003F401FC03C0002F03C0000F03C0000F" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_24 =  00000FC00000BBC007FFE3FF0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_25 =  0000000000000000000000000000FFFF000003C0000003C0000003C0000007C0" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_26 =  000001BF00E4006F00BFFFF80000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_27 =  00000000000000000000000000BFFFFA03F4006F03C0000003FA0000006FFFF8" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_28 =  000003C0000003C0003FFFFF000003C0000003C0000003C00000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_29 =  00000000000000000000000001FFFD0007E01F800B4007C0000003C0000003C0" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_2A =  03C0003C03C0003C03C0003C0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_2B =  00000000000000000000000003CBFFE003EE01F803F0003C03D0003C03C0003C" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_2C =  0BC003F00F8000F83F0000BD0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_2D =  000000000000000000000000000FF000002FBC00007D3E0000F81F4002F00BC0" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_2E =  1F0FF0FC3E0BF07C3D03E03E0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_2F =  00000000000000000000000003F40FC003FC2FD007FC3EE00FAE3DF00F0FB8F4" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_30 =  003E7E0001F80F803FFC2FFC0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_31 =  0000000000000000000000003FFC2FFE02F40FC0007D3E00000FF400000FF400" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_32 =  07C003F00F8000F83F0000BD0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_33 =  00003FFC0000FC040003F000000BF000001FB800003C3E0000F80F0002F00BC0" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_34 =  002F803C00FC003C02FFFFFC0000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_35 =  00000000000000000000000003FFFFFC03C002F803C00FC00280BE000003F028" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_36 =  00002F4000003C0000003C0000003C0000003C0000003C000000BC00000FE000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_37 =  000FF0000000BC0000003C0000003C0000003C0000003C0000003E0000000BF0" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_38 =  0000F0000000F0000000F0000000F0000000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_39 =  000000000000F0000000F0000000F0000000F0000000F0000000F0000000F000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_3A =  0007E0000000F0000000F0000000F0000000F0000000F0000000F80000002FC0" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_3B =  00003FC00000F8000000F0000000F0000000F0000000F0000002F000003F8000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_3C =  0F802FF800000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_3D =  000000000000000000000000000000000000000000BF800F03EBF02F0BC0FD7E" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <rom0.inst> in unit <FONT2>.
+Entity <FONT2> analyzed. Unit <FONT2> generated.
+
+Analyzing Entity <Replay_FileIO> in library <work> (Architecture <RTL>).
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_FileIO_Sync.vhd" line 628: Unconnected output port 'o_w_full' of component 'FIFO_SyncBlock_D2048_W8'.
+Entity <Replay_FileIO> analyzed. Unit <Replay_FileIO> generated.
+
+Analyzing Entity <FIFO_SyncBlock_D2048_W8> in library <work> (Architecture <RTL>).
+    Set user-defined property "INITP_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INITP_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_00 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_01 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_02 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_03 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_04 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_05 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_06 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_07 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_08 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_09 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_0A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_0B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_0C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_0D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_0E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_0F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_10 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_11 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_12 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_13 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_14 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_15 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_16 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_17 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_18 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_19 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_1A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_1B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_1C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_1D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_1E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_1F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_20 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_21 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_22 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_23 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_24 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_25 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_26 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_27 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_28 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_29 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_2A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_2B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_2C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_2D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_2E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_2F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_30 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_31 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_32 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_33 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_34 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_35 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_36 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_37 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_38 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_39 =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_3A =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_3B =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_3C =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_3D =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_3E =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_3F =  0000000000000000000000000000000000000000000000000000000000000000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_A =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "INIT_B =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "SIM_COLLISION_CHECK =  ALL" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "SRVAL_A =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "SRVAL_B =  000" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "WRITE_MODE_A =  WRITE_FIRST" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+    Set user-defined property "WRITE_MODE_B =  WRITE_FIRST" for instance <Ram.u_CharRam_inst> in unit <FIFO_SyncBlock_D2048_W8>.
+Entity <FIFO_SyncBlock_D2048_W8> analyzed. Unit <FIFO_SyncBlock_D2048_W8> generated.
+
+Analyzing Entity <Replay_Video> in library <work> (Architecture <RTL>).
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_devid' of component 'Replay_I2C'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_rw_l' of component 'Replay_I2C'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_rab' of component 'Replay_I2C'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_write_data' of component 'Replay_I2C'.
+WARNING:Xst:753 - "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd" line 114: Unconnected output port 'o_write_ena' of component 'Replay_I2C'.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[0].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[0].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[0].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[1].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[1].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[1].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[2].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[2].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[2].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[3].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[3].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[3].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[4].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[4].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[4].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[5].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[5].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[5].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[6].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[6].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[6].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[7].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[7].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[7].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[8].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[8].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[8].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[9].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[9].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[9].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[10].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[10].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[10].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <vidout[11].inst> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <vidout[11].inst> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  SYNC" for instance <vidout[11].inst> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_Clk_P> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <u_Clk_P> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <u_Clk_P> in unit <Replay_Video>.
+    Set user-defined property "DDR_ALIGNMENT =  NONE" for instance <u_Clk_N> in unit <Replay_Video>.
+    Set user-defined property "INIT =  0" for instance <u_Clk_N> in unit <Replay_Video>.
+    Set user-defined property "SRTYPE =  ASYNC" for instance <u_Clk_N> in unit <Replay_Video>.
+Entity <Replay_Video> analyzed. Unit <Replay_Video> generated.
+
+Analyzing Entity <Replay_I2C> in library <work> (Architecture <RTL>).
+INFO:Xst:2679 - Register <o_drive_scl_low> in unit <Replay_I2C> has a constant value of 0 during circuit operation. The register is replaced by logic.
+Entity <Replay_I2C> analyzed. Unit <Replay_I2C> generated.
+
+Analyzing Entity <Replay_Audio> in library <work> (Architecture <RTL>).
+Entity <Replay_Audio> analyzed. Unit <Replay_Audio> generated.
+
+
+=========================================================================
+*                           HDL Synthesis                               *
+=========================================================================
+
+Performing bidirectional port resolution...
+INFO:Xst:2561 - Always blocking tristate driving signal <b_Clk_Aux> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_FPGA_SPI_MOSI> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_2V5_IO_0> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_2V5_IO_1> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2561 - Always blocking tristate driving signal <b_Aux_IO> in unit <Replay_Top> is removed.
+INFO:Xst:2679 - Register <CART_CCTL_n> in unit <address_decoder> has a constant value of 1 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <PBI_WR_ENABLE> in unit <address_decoder> has a constant value of 0 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <CART_S4_n> in unit <address_decoder> has a constant value of 1 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <CART_S5_n> in unit <address_decoder> has a constant value of 1 during circuit operation. The register is replaced by logic.
+INFO:Xst:2679 - Register <CART_REQUEST> in unit <address_decoder> has a constant value of 0 during circuit operation. The register is replaced by logic.
+
+Synthesizing Unit <Replay_Audio>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Audio.vhd".
+    Found 1-bit register for signal <o_sample_taken>.
+    Found 1-bit register for signal <o_audio_din>.
+    Found 1-bit register for signal <o_audio_bckin>.
+    Found 1-bit register for signal <o_audio_mclk>.
+    Found 1-bit register for signal <o_audio_lrcin>.
+    Found 8-bit up counter for signal <cnt>.
+    Found 24-bit register for signal <shifter>.
+    Summary:
+	inferred   1 Counter(s).
+	inferred  29 D-type flip-flop(s).
+Unit <Replay_Audio> synthesized.
+
+
+Synthesizing Unit <Replay_ResetGen>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_ClockGen_Sync.vhd".
+    Found 1-bit register for signal <o_rst>.
+    Found 1-bit register for signal <o_rst_soft>.
+    Found 1-bit register for signal <por_l_meta1>.
+    Found 1-bit register for signal <por_l_meta2>.
+    Found 5-bit up counter for signal <por_rst_cnt>.
+    Found 5-bit up counter for signal <por_rst_soft_cnt>.
+    Found 1-bit register for signal <rst_soft>.
+    Summary:
+	inferred   2 Counter(s).
+	inferred   5 D-type flip-flop(s).
+Unit <Replay_ResetGen> synthesized.
+
+
+Synthesizing Unit <Replay_TranslatePS2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_TranslatePS2.vhd".
+WARNING:Xst:647 - Input <i_ena_sys> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1780 - Signal <matrix_adr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+    Found 512x8-bit dual-port RAM <Mram_keylut> for signal <keylut>.
+    Found finite state machine <FSM_0> for signal <key_state>.
+    -----------------------------------------------------------------------
+    | States             | 13                                             |
+    | Transitions        | 32                                             |
+    | Inputs             | 4                                              |
+    | Outputs            | 8                                              |
+    | Clock              | i_clk_sys                 (rising_edge)        |
+    | Reset              | key_state$or0000          (positive)           |
+    | Reset type         | asynchronous                                   |
+    | Reset State        | normal                                         |
+    | Power Up State     | normal                                         |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 1-bit register for signal <key_break>.
+    Found 8-bit register for signal <key_code>.
+    Found 1-bit register for signal <key_opt>.
+    Found 1-bit register for signal <key_pause>.
+    Found 1-bit register for signal <key_trans_en>.
+    Found 8-bit register for signal <key_translated>.
+    Found 128-bit register for signal <matrix>.
+    Found 1-of-16 decoder for signal <matrix_mask>.
+    Found 7-bit register for signal <static_out>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   1 RAM(s).
+	inferred 155 D-type flip-flop(s).
+	inferred   1 Decoder(s).
+Unit <Replay_TranslatePS2> synthesized.
+
+
+Synthesizing Unit <pokey_mixer>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_mixer.vhdl".
+WARNING:Xst:647 - Input <CHANNEL_ENABLE> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <volume_next<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 64x16-bit ROM for signal <volume_next>.
+    Found 16-bit adder for signal <volume_next_real>.
+    Found 16-bit adder for signal <volume_next_real$addsub0000> created at line 237.
+    Found 16-bit adder for signal <volume_next_real$addsub0001> created at line 237.
+    Found 16-bit register for signal <volume_reg>.
+    Found 6-bit adder for signal <volume_sum>.
+    Found 5-bit adder for signal <volume_sum$add0000> created at line 82.
+    Found 5-bit adder for signal <volume_sum$add0001> created at line 82.
+    Summary:
+	inferred   1 ROM(s).
+	inferred  16 D-type flip-flop(s).
+	inferred   6 Adder/Subtractor(s).
+Unit <pokey_mixer> synthesized.
+
+
+Synthesizing Unit <address_decoder>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/address_decoder.vhdl".
+WARNING:Xst:647 - Input <cart_activate> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <antic_refresh> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <SDRAM_OS_ROM_ADDR<13:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SDRAM_CART_ADDR> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found finite state machine <FSM_1> for signal <state_reg>.
+    -----------------------------------------------------------------------
+    | States             | 4                                              |
+    | Transitions        | 21                                             |
+    | Inputs             | 8                                              |
+    | Outputs            | 4                                              |
+    | Clock              | CLK                       (rising_edge)        |
+    | Reset              | reset_n                   (negative)           |
+    | Reset type         | asynchronous                                   |
+    | Reset State        | 00                                             |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 24-bit register for signal <ADDR_reg>.
+    Found 24-bit 8-to-1 multiplexer for signal <ADDR_reg$mux0000> created at line 277.
+    Found 1-bit register for signal <antic_fetch_real_reg>.
+    Found 1-bit register for signal <cpu_fetch_real_reg>.
+    Found 32-bit register for signal <DATA_WRITE_reg>.
+    Found 9-bit 8-to-1 multiplexer for signal <extended_bank>.
+    Found 1-bit 8-to-1 multiplexer for signal <extended_self_test>.
+    Found 9-bit adder for signal <fetch_wait_next$addsub0000>.
+    Found 9-bit register for signal <fetch_wait_reg>.
+    Found 1-bit register for signal <width_16bit_reg>.
+    Found 1-bit register for signal <width_32bit_reg>.
+    Found 1-bit register for signal <width_8bit_reg>.
+    Found 1-bit register for signal <write_enable_reg>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred  71 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred  34 Multiplexer(s).
+Unit <address_decoder> synthesized.
+
+
+Synthesizing Unit <zpu_rom>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_rom.vhdl".
+WARNING:Xst:1781 - Signal <ROM> is used but never assigned. Tied to default value.
+    Found 4096x32-bit ROM for signal <rdata>.
+    Found 32-bit register for signal <q>.
+    Summary:
+	inferred   1 ROM(s).
+	inferred  32 D-type flip-flop(s).
+Unit <zpu_rom> synthesized.
+
+
+Synthesizing Unit <generic_ram_infer_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/generic_ram_infer.vhdl".
+    Found 1024x8-bit single-port RAM <Mram_ram_block> for signal <ram_block>.
+    Found 8-bit register for signal <q>.
+    Summary:
+	inferred   1 RAM(s).
+	inferred   8 D-type flip-flop(s).
+Unit <generic_ram_infer_1> synthesized.
+
+
+Synthesizing Unit <complete_address_decoder_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
+WARNING:Xst:1780 - Signal <p<3><7:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<2><7:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<1><7:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+Unit <complete_address_decoder_1> synthesized.
+
+
+Synthesizing Unit <gtia_palette>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_palette.vhdl".
+    Found 256x24-bit ROM for signal <ATARI_COLOUR$rom0000>.
+    Summary:
+	inferred   1 ROM(s).
+Unit <gtia_palette> synthesized.
+
+
+Synthesizing Unit <irq_glue>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/irq_glue.vhdl".
+Unit <irq_glue> synthesized.
+
+
+Synthesizing Unit <cpu_65xx>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu_65xx_a.vhd".
+WARNING:Xst:646 - Signal <nextOpcInfoReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluZReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluVReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluRmwReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluNineReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluNReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluInputReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluCmpInputReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <aluCReg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 256x44-bit ROM for signal <nextOpcInfo$rom0000> created at line 911.
+    Found finite state machine <FSM_2> for signal <theCpuCycle>.
+    -----------------------------------------------------------------------
+    | States             | 19                                             |
+    | Transitions        | 97                                             |
+    | Inputs             | 25                                             |
+    | Outputs            | 43                                             |
+    | Clock              | clk                       (rising_edge)        |
+    | Clock enable       | enable                    (positive)           |
+    | Reset              | reset                     (positive)           |
+    | Reset type         | synchronous                                    |
+    | Reset State        | cycle2                                         |
+    | Power Up State     | opcodefetch                                    |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Using one-hot encoding for signal <nextAddr>.
+    Found 8-bit register for signal <A>.
+    Found 1-bit register for signal <Creg>.
+    Found 8-bit register for signal <doReg>.
+    Found 1-bit register for signal <Dreg>.
+    Found 1-bit register for signal <halt_dly>.
+    Found 9-bit adder for signal <indexOut$share0000> created at line 1535.
+    Found 1-bit register for signal <Ireg>.
+    Found 1-bit register for signal <irqActive>.
+    Found 1-bit register for signal <irqReg>.
+    Found 6-bit adder for signal <lowBits$add0000> created at line 758.
+    Found 6-bit adder for signal <lowBits$addsub0000> created at line 755.
+    Found 16-bit register for signal <myAddr>.
+    Found 8-bit subtractor for signal <myAddrDecrH>.
+    Found 16-bit adder for signal <myAddrIncr>.
+    Found 8-bit adder for signal <myAddrIncrH$addsub0000> created at line 1585.
+    Found 9-bit adder carry in for signal <nineBits$addsub0000>.
+    Found 9-bit adder for signal <nineBits$addsub0001>.
+    Found 8-bit xor2 for signal <nineBits$xor0000> created at line 765.
+    Found 5-bit adder for signal <nineBits_0$add0000> created at line 831.
+    Found 5-bit comparator greater for signal <nineBits_0$cmp_gt0000> created at line 831.
+    Found 5-bit comparator greater for signal <nineBits_0$cmp_gt0001> created at line 784.
+    Found 4-bit adder for signal <nineBits_3_0$add0000> created at line 785.
+    Found 4-bit adder for signal <nineBits_3_0$add0001> created at line 832.
+    Found 4-bit subtractor for signal <nineBits_3_0$sub0000> created at line 822.
+    Found 5-bit adder for signal <nineBits_4$add0000> created at line 834.
+    Found 5-bit comparator greater for signal <nineBits_4$cmp_gt0000> created at line 812.
+    Found 5-bit comparator greater for signal <nineBits_4$cmp_gt0001> created at line 834.
+    Found 5-bit adder for signal <nineBits_8_4$add0000> created at line 787.
+    Found 5-bit adder for signal <nineBits_8_4$add0001> created at line 813.
+    Found 5-bit subtractor for signal <nineBits_8_4$sub0000> created at line 826.
+    Found 1-bit register for signal <nmiEdge>.
+    Found 1-bit register for signal <nmiReg>.
+    Found 1-bit register for signal <Nreg>.
+    Found 44-bit register for signal <opcInfo>.
+    Found 16-bit register for signal <PC>.
+    Found 1-bit register for signal <processInt>.
+    Found 1-bit register for signal <processIrq>.
+    Found 1-bit register for signal <processNmi>.
+    Found 8-bit adder for signal <rmwBits$add0000> created at line 733.
+    Found 8-bit subtractor for signal <rmwBits$sub0000> created at line 735.
+    Found 8-bit register for signal <S>.
+    Found 8-bit addsub for signal <sIncDec$mux0000> created at line 1295.
+    Found 1-bit register for signal <so_reg>.
+    Found 8-bit register for signal <T>.
+    Found 8-bit register for signal <theOpcode>.
+    Found 1-bit register for signal <theWe>.
+    Found 1-bit xor2 for signal <varV$xor0000> created at line 804.
+    Found 1-bit xor2 for signal <varV$xor0001> created at line 810.
+    Found 1-bit xor2 for signal <varV$xor0002> created at line 810.
+    Found 1-bit xor2 for signal <varV$xor0003> created at line 818.
+    Found 1-bit register for signal <Vreg>.
+    Found 8-bit register for signal <X>.
+    Found 8-bit register for signal <Y>.
+    Found 1-bit register for signal <Zreg>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   1 ROM(s).
+	inferred 148 D-type flip-flop(s).
+	inferred  19 Adder/Subtractor(s).
+	inferred   4 Comparator(s).
+Unit <cpu_65xx> synthesized.
+
+
+Synthesizing Unit <antic_counter_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_counter.vhdl".
+    Found 12-bit adder for signal <value_next$add0000> created at line 51.
+    Found 16-bit register for signal <value_reg>.
+    Summary:
+	inferred  16 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+Unit <antic_counter_1> synthesized.
+
+
+Synthesizing Unit <antic_counter_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_counter.vhdl".
+    Found 10-bit adder for signal <value_next$add0000> created at line 51.
+    Found 16-bit register for signal <value_reg>.
+    Summary:
+	inferred  16 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+Unit <antic_counter_2> synthesized.
+
+
+Synthesizing Unit <simple_counter_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/simple_counter.vhdl".
+    Found 8-bit up counter for signal <value_reg>.
+    Summary:
+	inferred   1 Counter(s).
+Unit <simple_counter_1> synthesized.
+
+
+Synthesizing Unit <simple_counter_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/simple_counter.vhdl".
+    Found 4-bit up counter for signal <value_reg>.
+    Summary:
+	inferred   1 Counter(s).
+Unit <simple_counter_2> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 32-bit register for signal <shift_reg>.
+    Summary:
+	inferred  32 D-type flip-flop(s).
+Unit <wide_delay_line_1> synthesized.
+
+
+Synthesizing Unit <antic_dma_clock>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic_dma_clock.vhdl".
+    Found 8-bit register for signal <dma_shiftreg_reg>.
+    Summary:
+	inferred   8 D-type flip-flop(s).
+Unit <antic_dma_clock> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 64-bit register for signal <shift_reg>.
+    Summary:
+	inferred  64 D-type flip-flop(s).
+Unit <wide_delay_line_2> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_3>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 224-bit register for signal <shift_reg>.
+    Summary:
+	inferred 224 D-type flip-flop(s).
+Unit <wide_delay_line_3> synthesized.
+
+
+Synthesizing Unit <complete_address_decoder_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
+WARNING:Xst:1780 - Signal <p<4><15:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<3><15:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<2><15:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<1><15:8>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+Unit <complete_address_decoder_2> synthesized.
+
+
+Synthesizing Unit <delay_line_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
+    Found 24-bit register for signal <shift_reg>.
+    Summary:
+	inferred  24 D-type flip-flop(s).
+Unit <delay_line_1> synthesized.
+
+
+Synthesizing Unit <complete_address_decoder_5>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
+WARNING:Xst:1780 - Signal <p<6><63:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<5><63:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<4><63:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<3><63:8>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<2><63:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<1><63:32>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+Unit <complete_address_decoder_5> synthesized.
+
+
+Synthesizing Unit <ZPUMediumCore>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_core.vhd".
+WARNING:Xst:1780 - Signal <mult_res3_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <mult_res2_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <mult_b_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <mult_a_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <bin_op_res2_r> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <bin_op_res1_r> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
+INFO:Xst:1799 - State st_idle is never reached in FSM <state>.
+INFO:Xst:1799 - State st_mult3 is never reached in FSM <state>.
+INFO:Xst:1799 - State st_mult2 is never reached in FSM <state>.
+INFO:Xst:1799 - State st_mult4 is never reached in FSM <state>.
+INFO:Xst:1799 - State st_binary_op_res2 is never reached in FSM <state>.
+INFO:Xst:1799 - State st_binary_op_res is never reached in FSM <state>.
+    Found finite state machine <FSM_3> for signal <state>.
+    -----------------------------------------------------------------------
+    | States             | 15                                             |
+    | Transitions        | 58                                             |
+    | Inputs             | 30                                             |
+    | Outputs            | 18                                             |
+    | Clock              | clk_i                     (rising_edge)        |
+    | Reset              | reset_i                   (positive)           |
+    | Reset type         | synchronous                                    |
+    | Reset State        | st_resync                                      |
+    | Power Up State     | st_resync                                      |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 32x6-bit ROM for signal <tdecoded$mux0111>.
+    Found 32x6-bit ROM for signal <tdecoded$mux0112>.
+    Found 32x6-bit ROM for signal <tdecoded$mux0113>.
+    Found 32x6-bit ROM for signal <insn$mux0002>.
+    Found 1-bit register for signal <break_o>.
+    Found 22-bit register for signal <dbg_o.sp<23:2>>.
+    Found 8-bit register for signal <dbg_o.opcode>.
+    Found 32-bit register for signal <data_o>.
+    Found 32-bit register for signal <dbg_o.stk_a>.
+    Found 32-bit register for signal <dbg_o.stk_b>.
+    Found 1-bit register for signal <dbg_o.b_inst>.
+    Found 32-bit register for signal <dbg_o.pc>.
+    Found 6-bit 4-to-1 multiplexer for signal <$varindex0000> created at line 508.
+    Found 32-bit register for signal <a_r>.
+    Found 32-bit adder for signal <a_r$add0000> created at line 625.
+    Found 32-bit adder for signal <a_r$add0001> created at line 887.
+    Found 32-bit subtractor for signal <a_r$sub0000> created at line 633.
+    Found 22-bit adder for signal <a_r_23_2$add0000> created at line 772.
+    Found 6-bit subtractor for signal <a_r_5_0$sub0000> created at line 849.
+    Found 22-bit register for signal <addr_r>.
+    Found 22-bit adder carry in for signal <addr_r$share0000> created at line 356.
+    Found 2-bit register for signal <addrl_r>.
+    Found 32-bit register for signal <b_r>.
+    Found 1-bit register for signal <byte_read_r>.
+    Found 1-bit register for signal <byte_write_r>.
+    Found 32-bit register for signal <fetched_w_r>.
+    Found 1-bit register for signal <idim_r>.
+    Found 22-bit adder for signal <inc_inc_sp$add0000> created at line 276.
+    Found 22-bit adder for signal <inc_sp$add0000> created at line 275.
+    Found 6-bit register for signal <insn>.
+    Found 18-bit register for signal <insns<1:3>>.
+    Found 32x32-bit multiplier for signal <mult_res$mult0000> created at line 796.
+    Found 32-bit register for signal <mult_res1_r>.
+    Found 24-bit adder for signal <next_pc$add0000> created at line 345.
+    Found 1-bit register for signal <not_lshr>.
+    Found 32-bit register for signal <opcode_r>.
+    Found 24-bit register for signal <pc_r>.
+    Found 24-bit adder for signal <pc_r$add0000> created at line 578.
+    Found 1-bit register for signal <read_en_r>.
+    Found 32-bit comparator equal for signal <res$cmp_eq0000> created at line 674.
+    Found 32-bit comparator less for signal <res0$cmp_lt0000> created at line 680.
+    Found 32-bit comparator lessequal for signal <res1$cmp_le0000> created at line 686.
+    Found 32-bit comparator less for signal <res2$cmp_lt0000> created at line 692.
+    Found 32-bit comparator lessequal for signal <res3$cmp_le0000> created at line 699.
+    Found 8-bit 4-to-1 multiplexer for signal <sp_offset_4$varindex0000> created at line 343.
+    Found 22-bit register for signal <sp_r>.
+    Found 22-bit subtractor for signal <sp_r$share0000> created at line 516.
+    Found 1-bit register for signal <write_en_r>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   4 ROM(s).
+	inferred 420 D-type flip-flop(s).
+	inferred  11 Adder/Subtractor(s).
+	inferred   1 Multiplier(s).
+	inferred   5 Comparator(s).
+	inferred  14 Multiplexer(s).
+Unit <ZPUMediumCore> synthesized.
+
+
+Synthesizing Unit <delay_line_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
+    Found 3-bit register for signal <shift_reg>.
+    Summary:
+	inferred   3 D-type flip-flop(s).
+Unit <delay_line_2> synthesized.
+
+
+Synthesizing Unit <pokey_noise_filter>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_noise_filter.vhdl".
+Unit <pokey_noise_filter> synthesized.
+
+
+Synthesizing Unit <syncreset_enable_divider_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/syncreset_enable_divider.vhd".
+    Found 5-bit register for signal <count_reg>.
+    Found 5-bit adder for signal <count_reg$addsub0000> created at line 64.
+    Found 1-bit register for signal <enabled_out_reg>.
+    Summary:
+	inferred   6 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+Unit <syncreset_enable_divider_1> synthesized.
+
+
+Synthesizing Unit <syncreset_enable_divider_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/syncreset_enable_divider.vhd".
+    Found 7-bit register for signal <count_reg>.
+    Found 7-bit adder for signal <count_reg$addsub0000> created at line 64.
+    Found 1-bit register for signal <enabled_out_reg>.
+    Summary:
+	inferred   8 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+Unit <syncreset_enable_divider_2> synthesized.
+
+
+Synthesizing Unit <poly_17_9>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_17_9.vhdl".
+    Found 1-bit xor2 for signal <feedback$xor0000>.
+    Found 17-bit register for signal <shift_reg>.
+Unit <poly_17_9> synthesized.
+
+
+Synthesizing Unit <poly_5>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_5.vhdl".
+    Found 1-bit xor2 for signal <shift_next$xor0000>.
+    Found 5-bit register for signal <shift_reg>.
+Unit <poly_5> synthesized.
+
+
+Synthesizing Unit <poly_4>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/poly_4.vhdl".
+    Found 1-bit xor2 for signal <shift_next$xor0000>.
+    Found 4-bit register for signal <shift_reg>.
+Unit <poly_4> synthesized.
+
+
+Synthesizing Unit <delay_line_3>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
+    Found 2-bit register for signal <shift_reg>.
+    Summary:
+	inferred   2 D-type flip-flop(s).
+Unit <delay_line_3> synthesized.
+
+
+Synthesizing Unit <synchronizer>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/synchronizer.vhdl".
+    Found 3-bit register for signal <ff_reg>.
+    Summary:
+	inferred   3 D-type flip-flop(s).
+Unit <synchronizer> synthesized.
+
+
+Synthesizing Unit <pokey_keyboard_scanner>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey_keyboard_scanner.vhdl".
+    Found finite state machine <FSM_4> for signal <state_reg>.
+    -----------------------------------------------------------------------
+    | States             | 4                                              |
+    | Transitions        | 11                                             |
+    | Inputs             | 2                                              |
+    | Outputs            | 6                                              |
+    | Clock              | clk                       (rising_edge)        |
+    | Clock enable       | state_reg$and0000         (positive)           |
+    | Reset              | reset_n                   (negative)           |
+    | Reset type         | asynchronous                                   |
+    | Reset State        | 00                                             |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 6-bit up counter for signal <bincnt_reg>.
+    Found 1-bit register for signal <break_pressed_reg>.
+    Found 6-bit register for signal <compare_latch_reg>.
+    Found 1-bit register for signal <control_pressed_reg>.
+    Found 1-bit register for signal <irq_reg>.
+    Found 1-bit register for signal <key_held_reg>.
+    Found 6-bit register for signal <keycode_latch_reg>.
+    Found 6-bit comparator equal for signal <my_key$cmp_eq0000> created at line 109.
+    Found 1-bit register for signal <shift_pressed_reg>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   1 Counter(s).
+	inferred  17 D-type flip-flop(s).
+	inferred   1 Comparator(s).
+Unit <pokey_keyboard_scanner> synthesized.
+
+
+Synthesizing Unit <complete_address_decoder_3>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
+WARNING:Xst:1780 - Signal <p<2><3:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<1><3:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+Unit <complete_address_decoder_3> synthesized.
+
+
+Synthesizing Unit <enable_divider_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/enable_divider.vhdl".
+    Found 1-bit register for signal <count_reg<0>>.
+    Found 1-bit register for signal <enabled_out_reg>.
+    Summary:
+	inferred   2 D-type flip-flop(s).
+Unit <enable_divider_1> synthesized.
+
+
+Synthesizing Unit <enable_divider_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/enable_divider.vhdl".
+    Found 4-bit up counter for signal <count_reg>.
+    Found 1-bit register for signal <enabled_out_reg>.
+    Summary:
+	inferred   1 Counter(s).
+	inferred   1 D-type flip-flop(s).
+Unit <enable_divider_2> synthesized.
+
+
+Synthesizing Unit <delay_line_4>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
+    Found 15-bit register for signal <shift_reg>.
+    Summary:
+	inferred  15 D-type flip-flop(s).
+Unit <delay_line_4> synthesized.
+
+
+Synthesizing Unit <delay_line_5>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/delay_line.vhdl".
+    Found 8-bit register for signal <shift_reg>.
+    Summary:
+	inferred   8 D-type flip-flop(s).
+Unit <delay_line_5> synthesized.
+
+
+Synthesizing Unit <complete_address_decoder_4>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/complete_address_decoder.vhdl".
+WARNING:Xst:1780 - Signal <p<5><31:1>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<4><31:2>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<3><31:4>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<2><31:8>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <p<1><31:16>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+Unit <complete_address_decoder_4> synthesized.
+
+
+Synthesizing Unit <gtia_player>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_player.vhdl".
+    Found finite state machine <FSM_5> for signal <count_reg>.
+    -----------------------------------------------------------------------
+    | States             | 4                                              |
+    | Transitions        | 16                                             |
+    | Inputs             | 5                                              |
+    | Outputs            | 4                                              |
+    | Clock              | CLK                       (rising_edge)        |
+    | Clock enable       | COLOUR_ENABLE             (positive)           |
+    | Reset              | RESET_N                   (negative)           |
+    | Reset type         | asynchronous                                   |
+    | Reset State        | 00                                             |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 8-bit comparator equal for signal <count_reg$cmp_eq0000> created at line 108.
+    Found 8-bit register for signal <shift_reg>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   8 D-type flip-flop(s).
+	inferred   1 Comparator(s).
+Unit <gtia_player> synthesized.
+
+
+Synthesizing Unit <gtia_priority>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia_priority.vhdl".
+WARNING:Xst:647 - Input <BK> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <PRIOR<7:6>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <PRIOR<4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Found 1-bit register for signal <SB_reg>.
+    Found 1-bit register for signal <SF0_reg>.
+    Found 1-bit register for signal <SF1_reg>.
+    Found 1-bit register for signal <SF2_reg>.
+    Found 1-bit register for signal <SF3_reg>.
+    Found 1-bit register for signal <SP0_reg>.
+    Found 1-bit register for signal <SP1_reg>.
+    Found 1-bit register for signal <SP2_reg>.
+    Found 1-bit register for signal <SP3_reg>.
+    Summary:
+	inferred   9 D-type flip-flop(s).
+Unit <gtia_priority> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_4>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 12-bit register for signal <shift_reg>.
+    Summary:
+	inferred  12 D-type flip-flop(s).
+Unit <wide_delay_line_4> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_5>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 6-bit register for signal <shift_reg>.
+    Summary:
+	inferred   6 D-type flip-flop(s).
+Unit <wide_delay_line_5> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_6>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 8-bit register for signal <shift_reg>.
+    Summary:
+	inferred   8 D-type flip-flop(s).
+Unit <wide_delay_line_6> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_7>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 14-bit register for signal <shift_reg>.
+    Summary:
+	inferred  14 D-type flip-flop(s).
+Unit <wide_delay_line_7> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_8>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 40-bit register for signal <shift_reg>.
+    Summary:
+	inferred  40 D-type flip-flop(s).
+Unit <wide_delay_line_8> synthesized.
+
+
+Synthesizing Unit <wide_delay_line_9>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/wide_delay_line.vhdl".
+    Found 32-bit register for signal <shift_reg>.
+    Summary:
+	inferred  32 D-type flip-flop(s).
+Unit <wide_delay_line_9> synthesized.
+
+
+Synthesizing Unit <basic>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/basic.vhdl".
+WARNING:Xst:1781 - Signal <ROM> is used but never assigned. Tied to default value.
+    Found 8192x8-bit ROM for signal <rdata>.
+    Found 8-bit register for signal <q>.
+    Summary:
+	inferred   1 ROM(s).
+	inferred   8 D-type flip-flop(s).
+Unit <basic> synthesized.
+
+
+Synthesizing Unit <os16>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/os16.vhdl".
+WARNING:Xst:1781 - Signal <ROM> is used but never assigned. Tied to default value.
+    Found 16384x8-bit ROM for signal <rdata>.
+    Found 8-bit register for signal <q>.
+    Summary:
+	inferred   1 ROM(s).
+	inferred   8 D-type flip-flop(s).
+Unit <os16> synthesized.
+
+
+Synthesizing Unit <generic_ram_infer_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/generic_ram_infer.vhdl".
+    Found 16384x8-bit single-port RAM <Mram_ram_block> for signal <ram_block>.
+    Found 8-bit register for signal <q>.
+    Summary:
+	inferred   1 RAM(s).
+	inferred   8 D-type flip-flop(s).
+Unit <generic_ram_infer_2> synthesized.
+
+
+Synthesizing Unit <Replay_VideoTiming>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoTiming.vhd".
+    Register <h_sync_l> equivalent to <h_sync> has been removed
+    Register <v_sync_l> equivalent to <v_sync> has been removed
+    Using one-hot encoding for signal <standard_ana>.
+    Found 15-bit subtractor for signal <$sub0000> created at line 181.
+    Found 15-bit subtractor for signal <$sub0001> created at line 185.
+    Found 14-bit register for signal <act_h_cnt>.
+    Found 14-bit adder for signal <act_h_cnt$addsub0000> created at line 526.
+    Found 14-bit register for signal <act_v_cnt>.
+    Found 14-bit adder for signal <act_v_cnt$addsub0000> created at line 534.
+    Found 14-bit adder carry out for signal <add0000$addsub0000> created at line 188.
+    Found 1-bit register for signal <ana_cs>.
+    Found 1-bit register for signal <ana_de>.
+    Found 1-bit register for signal <ana_hs>.
+    Found 1-bit register for signal <ana_vs>.
+    Found 5-bit register for signal <cs_gate>.
+    Found 1-bit register for signal <dig_de>.
+    Found 1-bit register for signal <dig_ha>.
+    Found 1-bit register for signal <dig_hs>.
+    Found 1-bit register for signal <dig_sof>.
+    Found 1-bit register for signal <dig_sol>.
+    Found 1-bit register for signal <dig_va>.
+    Found 1-bit register for signal <dig_vs>.
+    Found 1-bit register for signal <h_act>.
+    Found 14-bit comparator equal for signal <h_act$cmp_eq0000> created at line 246.
+    Found 1-bit register for signal <h_ana_act>.
+    Found 14-bit comparator equal for signal <h_ana_act$cmp_eq0000> created at line 278.
+    Found 14-bit comparator equal for signal <h_ana_act$cmp_eq0001> created at line 277.
+    Found 1-bit register for signal <h_ana_b1>.
+    Found 14-bit comparator equal for signal <h_ana_b1$cmp_eq0000> created at line 296.
+    Found 1-bit register for signal <h_ana_b2>.
+    Found 14-bit comparator equal for signal <h_ana_b2$cmp_eq0000> created at line 302.
+    Found 14-bit comparator equal for signal <h_ana_b2$cmp_eq0001> created at line 301.
+    Found 1-bit register for signal <h_ana_n1>.
+    Found 14-bit comparator equal for signal <h_ana_n1$cmp_eq0000> created at line 284.
+    Found 1-bit register for signal <h_ana_n2>.
+    Found 14-bit comparator equal for signal <h_ana_n2$cmp_eq0000> created at line 290.
+    Found 14-bit register for signal <h_cnt>.
+    Found 14-bit adder for signal <h_cnt$addsub0000> created at line 242.
+    Found 1-bit register for signal <h_eol>.
+    Found 14-bit comparator equal for signal <h_eol$cmp_eq0000> created at line 237.
+    Found 1-bit register for signal <h_eol_t1>.
+    Found 1-bit register for signal <h_sol>.
+    Found 1-bit register for signal <h_sync>.
+    Found 14-bit comparator equal for signal <h_sync$cmp_eq0000> created at line 254.
+    Found 14-bit comparator equal for signal <h_sync$cmp_eq0001> created at line 252.
+    Found 1-bit register for signal <h_vgate_f1>.
+    Found 1-bit register for signal <h_vgate_f2>.
+    Found 14-bit register for signal <param_c.h_len>.
+    Found 14-bit subtractor for signal <param_c.h_len$sub0000> created at line 180.
+    Found 14-bit register for signal <param_c.h_start_2nd>.
+    Found 14-bit adder for signal <param_c.h_start_2nd$addsub0000> created at line 192.
+    Found 14-bit subtractor for signal <param_c.h_start_2nd$sub0001> created at line 192.
+    Found 14-bit register for signal <param_c.h_start_act>.
+    Found 14-bit subtractor for signal <param_c.h_start_act$sub0001> created at line 181.
+    Found 14-bit register for signal <param_c.h_start_ana>.
+    Found 14-bit adder for signal <param_c.h_start_ana$add0000> created at line 184.
+    Found 14-bit register for signal <param_c.h_start_sync>.
+    Found 14-bit subtractor for signal <param_c.h_start_sync$sub0000> created at line 187.
+    Found 14-bit register for signal <param_c.h_stop_ana>.
+    Found 14-bit subtractor for signal <param_c.h_stop_ana$sub0000> created at line 185.
+    Found 14-bit register for signal <param_c.h_stop_bd1>.
+    Found 14-bit adder for signal <param_c.h_stop_bd1$add0000> created at line 197.
+    Found 14-bit register for signal <param_c.h_stop_bd2>.
+    Found 14-bit adder for signal <param_c.h_stop_bd2$add0000> created at line 198.
+    Found 14-bit register for signal <param_c.h_stop_eq1>.
+    Found 14-bit adder for signal <param_c.h_stop_eq1$add0000> created at line 195.
+    Found 14-bit register for signal <param_c.h_stop_eq2>.
+    Found 14-bit adder for signal <param_c.h_stop_eq2$add0000> created at line 196.
+    Found 14-bit register for signal <param_c.h_stop_sync>.
+    Found 14-bit subtractor for signal <param_c.h_stop_sync$sub0000> created at line 188.
+    Found 2-bit register for signal <standard_ana>.
+    Found 1-bit register for signal <v_act>.
+    Found 14-bit comparator equal for signal <v_act$cmp_eq0000> created at line 366.
+    Found 14-bit comparator equal for signal <v_act$cmp_eq0001> created at line 367.
+    Found 14-bit comparator equal for signal <v_act$cmp_eq0002> created at line 369.
+    Found 14-bit comparator not equal for signal <v_act$cmp_ne0000> created at line 371.
+    Found 14-bit comparator not equal for signal <v_act$cmp_ne0001> created at line 369.
+    Found 14-bit comparator not equal for signal <v_act$cmp_ne0002> created at line 367.
+    Found 14-bit comparator not equal for signal <v_act$cmp_ne0003> created at line 366.
+    Found 14-bit register for signal <v_cnt>.
+    Found 14-bit adder for signal <v_cnt$addsub0000> created at line 346.
+    Found 1-bit register for signal <v_f2>.
+    Found 14-bit comparator equal for signal <v_f2$cmp_eq0000> created at line 376.
+    Found 14-bit comparator not equal for signal <v_f2$cmp_ne0000> created at line 377.
+    Found 14-bit comparator not equal for signal <v_f2$cmp_ne0001> created at line 376.
+    Found 1-bit register for signal <v_sof>.
+    Found 1-bit register for signal <v_sync>.
+    Found 14-bit comparator equal for signal <v_sync$cmp_eq0001> created at line 384.
+    Found 14-bit comparator equal for signal <v_sync$cmp_eq0002> created at line 387.
+    Found 14-bit comparator not equal for signal <v_sync$cmp_ne0000> created at line 390.
+    Found 14-bit comparator not equal for signal <v_sync$cmp_ne0001> created at line 387.
+    Found 14-bit comparator not equal for signal <v_sync$cmp_ne0002> created at line 384.
+    Summary:
+	inferred 230 D-type flip-flop(s).
+	inferred  19 Adder/Subtractor(s).
+	inferred  26 Comparator(s).
+Unit <Replay_VideoTiming> synthesized.
+
+
+Synthesizing Unit <Replay_SPI8>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_SPI8.vhd".
+    Found 4-bit register for signal <o_rxbytecnt>.
+    Found 1-bit register for signal <o_rdy>.
+    Found 8-bit register for signal <o_rxdata>.
+    Found 8-bit register for signal <o_rxcmd>.
+    Found 1-bit register for signal <o_sof>.
+    Found 8-bit register for signal <o_rxbytesel>.
+    Found 3-bit up counter for signal <bit_cnt>.
+    Found 8-bit register for signal <byte>.
+    Found 4-bit up counter for signal <byte_cnt>.
+    Found 7-bit register for signal <din>.
+    Found 8-bit register for signal <dout>.
+    Summary:
+	inferred   2 Counter(s).
+	inferred  45 D-type flip-flop(s).
+Unit <Replay_SPI8> synthesized.
+
+
+Synthesizing Unit <Replay_I2C>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_I2C.vhd".
+WARNING:Xst:647 - Input <i_spc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Found finite state machine <FSM_6> for signal <State>.
+    -----------------------------------------------------------------------
+    | States             | 8                                              |
+    | Transitions        | 28                                             |
+    | Inputs             | 4                                              |
+    | Outputs            | 8                                              |
+    | Clock              | i_clk                     (rising_edge)        |
+    | Clock enable       | State$not0000             (positive)           |
+    | Reset              | i_rst                     (positive)           |
+    | Reset type         | asynchronous                                   |
+    | Reset State        | s_idle                                         |
+    | Power Up State     | s_idle                                         |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 1-bit register for signal <o_drive_spc_low>.
+    Found 1-bit register for signal <o_drive_sda_low>.
+    Found 1-bit register for signal <o_drive_spd_low>.
+    Found 1-bit register for signal <actv>.
+    Found 7-bit register for signal <devid>.
+    Found 9-bit register for signal <din_shift>.
+    Found 8-bit register for signal <rab>.
+    Found 1-bit register for signal <rw_l>.
+    Found 1-bit register for signal <scl_falling<0>>.
+    Found 4-bit register for signal <scl_in>.
+    Found 1-bit register for signal <scl_r>.
+    Found 1-bit 4-to-1 multiplexer for signal <scl_r$mux0000>.
+    Found 1-bit register for signal <scl_rising<0>>.
+    Found 1-bit register for signal <sda_falling<0>>.
+    Found 4-bit register for signal <sda_in>.
+    Found 1-bit register for signal <sda_r>.
+    Found 1-bit 4-to-1 multiplexer for signal <sda_r$mux0000>.
+    Found 1-bit register for signal <sda_rising<0>>.
+    Found 2-bit register for signal <spd_in>.
+    Found 8-bit register for signal <write_data>.
+    Found 1-bit register for signal <write_ena>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred  45 D-type flip-flop(s).
+	inferred   2 Multiplexer(s).
+Unit <Replay_I2C> synthesized.
+
+
+Synthesizing Unit <Replay_ClockGen>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_ClockGen_Sync.vhd".
+WARNING:Xst:646 - Signal <status> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <ps_rst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <clk_b_dcm_div> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 1-bit register for signal <o_rst_ram_capture>.
+    Found 8-bit down counter for signal <ctl_divider_100us>.
+    Found 8-bit down counter for signal <ctl_divider_1us>.
+    Found 8-bit comparator equal for signal <new_phase$cmp_eq0000> created at line 530.
+    Found 8-bit comparator greater for signal <new_phase$cmp_gt0000> created at line 531.
+    Found 1-bit register for signal <ps_en>.
+    Found 1-bit register for signal <ps_eq>.
+    Found 1-bit register for signal <ps_eq_meta>.
+    Found 1-bit register for signal <ps_inc>.
+    Found 8-bit up accumulator for signal <ps_phase>.
+    Found 1-bit register for signal <ps_state>.
+    Found 1-bit register for signal <rst_aux>.
+    Found 1-bit register for signal <rst_ctl>.
+    Found 1-bit register for signal <rst_ctl_hard>.
+    Found 1-bit register for signal <rst_ram>.
+    Found 1-bit register for signal <rst_video>.
+    Found 1-bit register for signal <rst_video_hard>.
+    Found 1-bit register for signal <tick_ctl_100us>.
+    Found 1-bit register for signal <tick_ctl_1us>.
+    Summary:
+	inferred   2 Counter(s).
+	inferred   1 Accumulator(s).
+	inferred  14 D-type flip-flop(s).
+	inferred   2 Comparator(s).
+Unit <Replay_ClockGen> synthesized.
+
+
+Synthesizing Unit <Replay_Video>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Video.vhd".
+WARNING:Xst:647 - Input <i_video_int> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <vidout_debug_r> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <vidout_debug_g> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <vidout_debug_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 1-bit register for signal <o_video_de>.
+    Found 1-bit register for signal <o_video_hsync>.
+    Found 1-bit register for signal <o_video_rst_l>.
+    Found 1-bit tristate buffer for signal <b_video_ddc_clk>.
+    Found 1-bit register for signal <o_video_vsync>.
+    Found 1-bit tristate buffer for signal <b_video_ddc_data>.
+    Found 1-bit register for signal <o_video_h>.
+    Found 1-bit register for signal <o_video_v>.
+    Found 4-bit register for signal <ana_hs_dac_t>.
+    Found 4-bit register for signal <ana_vs_dac_t>.
+    Found 1-bit register for signal <vidout_clamp>.
+    Found 12-bit register for signal <vidout_falling_t1>.
+    Summary:
+	inferred  27 D-type flip-flop(s).
+	inferred   2 Tristate(s).
+Unit <Replay_Video> synthesized.
+
+
+Synthesizing Unit <Replay_VideoConverter>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_VideoConverter.vhd".
+WARNING:Xst:646 - Signal <vidin_match_n_s> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+    Found 2048x24-bit dual-port RAM <Mram_dupo_buf_s> for signal <dupo_buf_s>.
+    Found 1-bit register for signal <o_vid_sync.ana_vs>.
+    Found 1-bit register for signal <o_vid_sync.dig_vs>.
+    Found 24-bit register for signal <o_vid_rgb>.
+    Found 1-bit register for signal <o_vid_sync.ana_de>.
+    Found 1-bit register for signal <o_vid_sync.ana_hs>.
+    Found 1-bit register for signal <o_vid_sync.dig_de>.
+    Found 1-bit register for signal <o_vid_sync.dig_hs>.
+    Found 24-bit register for signal <bufout_dat_s>.
+    Found 32-bit comparator greater for signal <bufout_en_s$cmp_gt0000> created at line 456.
+    Found 32-bit comparator greater for signal <bufout_en_s$cmp_gt0001> created at line 456.
+    Found 14-bit comparator lessequal for signal <bufout_en_s$cmp_le0000> created at line 456.
+    Found 14-bit comparator lessequal for signal <bufout_en_s$cmp_le0001> created at line 456.
+    Found 3-bit register for signal <vidin_fsync_s>.
+    Found 1-bit register for signal <vidin_fsyncd_s>.
+    Found 14-bit up counter for signal <vidin_hcnt_s>.
+    Found 1-bit register for signal <vidin_hsyncdn_s>.
+    Found 1-bit register for signal <vidin_sof_detected_s>.
+    Found 14-bit up counter for signal <vidin_vcnt_s>.
+    Found 1-bit register for signal <vidin_vsyncdn_s>.
+    Found 1-bit register for signal <vidout_sync_1st_s.ana_de>.
+    Found 1-bit register for signal <vidout_sync_1st_s.ana_hs>.
+    Found 1-bit register for signal <vidout_sync_1st_s.ana_vs>.
+    Found 1-bit register for signal <vidout_sync_1st_s.dig_de>.
+    Found 1-bit register for signal <vidout_sync_1st_s.dig_hs>.
+    Found 1-bit register for signal <vidout_sync_1st_s.dig_vs>.
+    Found 28-bit register for signal <vidout_watchdogcnt_s>.
+    Found 28-bit subtractor for signal <vidout_watchdogcnt_s$addsub0000> created at line 376.
+    Found 14x14-bit multiplier for signal <vidout_watchdogcnt_s$mult0001> created at line 364.
+    Found 28-bit adder for signal <vidout_watchdogcnt_s$mux0000> created at line 370.
+    Summary:
+	inferred   1 RAM(s).
+	inferred   2 Counter(s).
+	inferred  95 D-type flip-flop(s).
+	inferred   2 Adder/Subtractor(s).
+	inferred   1 Multiplier(s).
+	inferred   4 Comparator(s).
+Unit <Replay_VideoConverter> synthesized.
+
+
+Synthesizing Unit <cpu>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/cpu.vhd".
+WARNING:Xst:646 - Signal <not_rdy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <debugY> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <debugX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <debugS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <debugPc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <debugOpcode> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <debugA> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <CPU_ENABLE_RESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 1-bit register for signal <nmi_n_reg>.
+    Found 1-bit register for signal <nmi_pending_reg>.
+    Summary:
+	inferred   2 D-type flip-flop(s).
+Unit <cpu> synthesized.
+
+
+Synthesizing Unit <zpu_glue>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_glue.vhdl".
+WARNING:Xst:646 - Signal <zpu_debug.stk_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <zpu_debug.stk_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <zpu_debug.sp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <zpu_debug.pc> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <zpu_debug.opcode> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <zpu_debug.b_inst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <zpu_break> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Using one-hot encoding for signal <result_reg>.
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <result_reg> of Case statement line 334 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <result_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+    Found 1-bit register for signal <memory_ready_reg>.
+    Found 18-bit register for signal <result_reg>.
+    Found 1-bit register for signal <ZPU_16BIT_WRITE_ENABLE_reg>.
+    Found 1-bit register for signal <ZPU_32BIT_WRITE_ENABLE_reg>.
+    Found 1-bit register for signal <ZPU_8BIT_WRITE_ENABLE_reg>.
+    Found 24-bit register for signal <zpu_addr_reg>.
+    Found 32-bit register for signal <zpu_di_reg>.
+    Found 32-bit register for signal <ZPU_DO_reg>.
+    Found 1-bit register for signal <zpu_memory_fetch_pending_reg>.
+    Found 1-bit register for signal <ZPU_READ_reg>.
+    Summary:
+	inferred  94 D-type flip-flop(s).
+Unit <zpu_glue> synthesized.
+
+
+Synthesizing Unit <pia>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pia.vhdl".
+WARNING:Xst:646 - Signal <write_ora> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Register <CB1_reg> equivalent to <CA1_reg> has been removed
+    Found 1-bit register for signal <ca1_edge_reg>.
+    Found 1-bit register for signal <CA1_reg>.
+    Found 1-bit register for signal <ca2_edge_reg>.
+    Found 1-bit register for signal <CA2_output_reg>.
+    Found 1-bit 4-to-1 multiplexer for signal <CA2_output_reg$mux0000> created at line 294.
+    Found 1-bit register for signal <CA2_reg>.
+    Found 1-bit register for signal <cb1_edge_reg>.
+    Found 1-bit register for signal <cb2_edge_reg>.
+    Found 1-bit register for signal <CB2_output_reg>.
+    Found 1-bit 4-to-1 multiplexer for signal <CB2_output_reg$mux0000> created at line 349.
+    Found 1-bit register for signal <CB2_reg>.
+    Found 2-bit register for signal <irqa_reg>.
+    Found 2-bit register for signal <irqb_reg>.
+    Found 6-bit register for signal <porta_control_reg>.
+    Found 8-bit register for signal <porta_direction_reg>.
+    Found 8-bit register for signal <porta_input_reg>.
+    Found 8-bit register for signal <porta_output_reg>.
+    Found 6-bit register for signal <portb_control_reg>.
+    Found 8-bit register for signal <portb_direction_reg>.
+    Found 8-bit register for signal <portb_input_reg>.
+    Found 8-bit register for signal <portb_output_reg>.
+    Summary:
+	inferred  73 D-type flip-flop(s).
+	inferred   2 Multiplexer(s).
+Unit <pia> synthesized.
+
+
+Synthesizing Unit <shared_enable>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/shared_enable.vhdl".
+    Found 1-bit register for signal <cpu_extra_enable_reg>.
+    Found 1-bit register for signal <oldcpu_extra_enable_reg>.
+    Found 6-bit adder for signal <throttle_count_next$addsub0000> created at line 99.
+    Found 6-bit comparator equal for signal <throttle_count_next$cmp_eq0000> created at line 103.
+    Found 6-bit register for signal <throttle_count_reg>.
+    Found 1-bit register for signal <turbo_reg>.
+    Summary:
+	inferred   9 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred   1 Comparator(s).
+Unit <shared_enable> synthesized.
+
+
+Synthesizing Unit <gtia>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/gtia.vhdl".
+WARNING:Xst:646 - Signal <an_prev3_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found finite state machine <FSM_7> for signal <pmg_dma_state_reg>.
+    -----------------------------------------------------------------------
+    | States             | 7                                              |
+    | Transitions        | 38                                             |
+    | Inputs             | 7                                              |
+    | Outputs            | 5                                              |
+    | Clock              | CLK                       (rising_edge)        |
+    | Reset              | RESET_N                   (negative)           |
+    | Reset type         | asynchronous                                   |
+    | Reset State        | 101                                            |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 8-bit register for signal <active_bk_modify_reg>.
+    Found 8-bit register for signal <active_bk_valid_reg>.
+    Found 2-bit register for signal <active_hr_reg>.
+    Found 1-bit 4-to-1 multiplexer for signal <active_pf2_collision_live$mux0002> created at line 687.
+    Found 3-bit register for signal <an_prev2_reg>.
+    Found 3-bit register for signal <an_prev_reg>.
+    Found 7-bit register for signal <colbk_raw_reg>.
+    Found 8-bit register for signal <COLOUR_REG>.
+    Found 7-bit register for signal <colpf0_raw_reg>.
+    Found 7-bit register for signal <colpf1_raw_reg>.
+    Found 7-bit register for signal <colpf2_raw_reg>.
+    Found 7-bit register for signal <colpf3_raw_reg>.
+    Found 7-bit register for signal <colpm0_raw_reg>.
+    Found 7-bit register for signal <colpm1_raw_reg>.
+    Found 7-bit register for signal <colpm2_raw_reg>.
+    Found 7-bit register for signal <colpm3_raw_reg>.
+    Found 4-bit register for signal <consol_output_reg>.
+    Found 3-bit register for signal <gractl_reg>.
+    Found 8-bit register for signal <grafm_reg>.
+    Found 8-bit register for signal <grafp0_reg>.
+    Found 8-bit register for signal <grafp1_reg>.
+    Found 8-bit register for signal <grafp2_reg>.
+    Found 8-bit register for signal <grafp3_reg>.
+    Found 1-bit register for signal <hblank_reg>.
+    Found 1-bit register for signal <highres_reg>.
+    Found 8-bit register for signal <hposm0_raw_reg>.
+    Found 8-bit register for signal <hposm1_raw_reg>.
+    Found 8-bit register for signal <hposm2_raw_reg>.
+    Found 8-bit register for signal <hposm3_raw_reg>.
+    Found 8-bit register for signal <hposp0_raw_reg>.
+    Found 8-bit register for signal <hposp1_raw_reg>.
+    Found 8-bit register for signal <hposp2_raw_reg>.
+    Found 8-bit register for signal <hposp3_raw_reg>.
+    Found 8-bit register for signal <HRCOLOUR_REG>.
+    Found 1-bit register for signal <hsync_reg>.
+    Found 4-bit register for signal <m0pf_reg>.
+    Found 4-bit register for signal <m0pl_reg>.
+    Found 4-bit register for signal <m1pf_reg>.
+    Found 4-bit register for signal <m1pl_reg>.
+    Found 4-bit register for signal <m2pf_reg>.
+    Found 4-bit register for signal <m2pl_reg>.
+    Found 4-bit register for signal <m3pf_reg>.
+    Found 4-bit register for signal <m3pl_reg>.
+    Found 1-bit register for signal <odd_scanline_reg>.
+    Found 4-bit register for signal <p0pf_reg>.
+    Found 4-bit register for signal <p0pl_reg>.
+    Found 4-bit register for signal <p1pf_reg>.
+    Found 4-bit register for signal <p1pl_reg>.
+    Found 4-bit register for signal <p2pf_reg>.
+    Found 4-bit register for signal <p2pl_reg>.
+    Found 4-bit register for signal <p3pf_reg>.
+    Found 4-bit register for signal <p3pl_reg>.
+    Found 8-bit register for signal <prior_raw_reg>.
+    Found 8-bit register for signal <sizem_raw_reg>.
+    Found 2-bit register for signal <sizep0_raw_reg>.
+    Found 2-bit register for signal <sizep1_raw_reg>.
+    Found 2-bit register for signal <sizep2_raw_reg>.
+    Found 2-bit register for signal <sizep3_raw_reg>.
+    Found 1-bit register for signal <trig0_reg>.
+    Found 1-bit register for signal <trig1_reg>.
+    Found 1-bit register for signal <trig2_reg>.
+    Found 1-bit register for signal <trig3_reg>.
+    Found 8-bit register for signal <vdelay_reg>.
+    Found 1-bit register for signal <vsync_reg>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred 319 D-type flip-flop(s).
+	inferred   1 Multiplexer(s).
+Unit <gtia> synthesized.
+
+
+Synthesizing Unit <reg_file_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl".
+    Found 128-bit register for signal <digit_reg>.
+    Summary:
+	inferred 128 D-type flip-flop(s).
+Unit <reg_file_1> synthesized.
+
+
+Synthesizing Unit <reg_file_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl".
+    Found 256-bit register for signal <digit_reg>.
+INFO:Xst:738 - HDL ADVISOR - 256 flip-flops were inferred for signal <digit_reg>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
+    Summary:
+	inferred 256 D-type flip-flop(s).
+Unit <reg_file_2> synthesized.
+
+
+Synthesizing Unit <internalromram>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/internalromram.vhd".
+WARNING:Xst:647 - Input <ROM_ADDR<21:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <ROM_ADDR<14>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <RAM_ADDR<18:16>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Found 1-bit register for signal <ram_request_reg>.
+    Found 1-bit register for signal <rom_request_reg>.
+    Summary:
+	inferred   2 D-type flip-flop(s).
+Unit <internalromram> synthesized.
+
+
+Synthesizing Unit <covox>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/covox.vhd".
+    Found 8-bit register for signal <channel0_reg>.
+    Found 8-bit register for signal <channel1_reg>.
+    Found 8-bit register for signal <channel2_reg>.
+    Found 8-bit register for signal <channel3_reg>.
+    Summary:
+	inferred  32 D-type flip-flop(s).
+Unit <covox> synthesized.
+
+
+Synthesizing Unit <reg_file_3>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/reg_file.vhdl".
+WARNING:Xst:646 - Signal <addr_decoded<63:48>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 384-bit register for signal <digit_reg>.
+INFO:Xst:738 - HDL ADVISOR - 384 flip-flops were inferred for signal <digit_reg>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time.
+    Summary:
+	inferred 384 D-type flip-flop(s).
+Unit <reg_file_3> synthesized.
+
+
+Synthesizing Unit <pokey_countdown_timer>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/countdown_timer.vhdl".
+    Found 8-bit 4-to-1 multiplexer for signal <count_next>.
+    Found 8-bit subtractor for signal <count_next$addsub0000> created at line 82.
+    Found 8-bit register for signal <count_reg>.
+    Summary:
+	inferred   8 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred   8 Multiplexer(s).
+Unit <pokey_countdown_timer> synthesized.
+
+
+Synthesizing Unit <ps2_rom>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/ps2_rom.vhd".
+Unit <ps2_rom> synthesized.
+
+
+Synthesizing Unit <kcpsm3>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/kcpsm3.vhd".
+Unit <kcpsm3> synthesized.
+
+
+Synthesizing Unit <Replay_DDRCtrl_Datapath>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Datapath.vhd".
+WARNING:Xst:646 - Signal <wpipe<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <rpipe<2>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <r_valid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <r_ena> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <r_empty> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dqs_q1> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dqs_q0> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dq_rst> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Register <dqs_oe0_l> equivalent to <dq_oe0_m1_l> has been removed
+    Found 2-bit register for signal <dm_d0>.
+    Found 2-bit register for signal <dm_d0_r90>.
+    Found 2-bit register for signal <dm_d1>.
+    Found 2-bit register for signal <dm_d1_r90>.
+    Found 16-bit register for signal <dq_d0>.
+    Found 16-bit register for signal <dq_d0_r90>.
+    Found 16-bit register for signal <dq_d1>.
+    Found 16-bit register for signal <dq_d1_r90>.
+    Found 1-bit register for signal <dq_ena>.
+    Found 1-bit register for signal <dq_oe0_m1_l>.
+    Found 1-bit register for signal <dq_oe1_m1_l>.
+    Found 1-bit register for signal <dq_st_hold>.
+    Found 1-bit register for signal <dqs_enable>.
+    Found 1-bit register for signal <dqs_oe1_l>.
+    Found 13-bit register for signal <ram_addr>.
+    Found 2-bit register for signal <ram_ba>.
+    Found 1-bit register for signal <ram_cas_l>.
+    Found 1-bit register for signal <ram_cke>.
+    Found 1-bit register for signal <ram_cs_l>.
+    Found 1-bit register for signal <ram_ras_l>.
+    Found 1-bit register for signal <ram_we_l>.
+    Found 4-bit up counter for signal <rbuf_w_addr>.
+    Found 3-bit register for signal <rpipe>.
+    Found 3-bit register for signal <wpipe>.
+    Summary:
+	inferred   1 Counter(s).
+	inferred 104 D-type flip-flop(s).
+Unit <Replay_DDRCtrl_Datapath> synthesized.
+
+
+Synthesizing Unit <FIFO_SyncSRL_D16>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncSRL_D16.vhd".
+    Found 4-bit up accumulator for signal <r_addr>.
+    Found 1-bit register for signal <valid>.
+    Summary:
+	inferred   1 Accumulator(s).
+	inferred   1 D-type flip-flop(s).
+Unit <FIFO_SyncSRL_D16> synthesized.
+
+
+Synthesizing Unit <FONT0>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font0_rom.vhd".
+Unit <FONT0> synthesized.
+
+
+Synthesizing Unit <FONT1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font1_rom.vhd".
+Unit <FONT1> synthesized.
+
+
+Synthesizing Unit <FONT2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/font2_rom.vhd".
+Unit <FONT2> synthesized.
+
+
+Synthesizing Unit <FIFO_SyncBlock_D2048_W8>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/FIFO_SyncBlock_D2048_W8.vhd".
+    Found 4x12-bit ROM for signal <offset$mux0000> created at line 109.
+    Found 1-bit register for signal <empty_i>.
+    Found 1-bit 4-to-1 multiplexer for signal <empty_i$mux0000> created at line 109.
+    Found 1-bit register for signal <full_i>.
+    Found 1-bit 4-to-1 multiplexer for signal <full_i$mux0000> created at line 109.
+    Found 12-bit up accumulator for signal <level>.
+    Found 11-bit up counter for signal <r_addr>.
+    Found 1-bit register for signal <valid>.
+    Found 11-bit up counter for signal <w_addr>.
+    Summary:
+	inferred   1 ROM(s).
+	inferred   2 Counter(s).
+	inferred   1 Accumulator(s).
+	inferred   3 D-type flip-flop(s).
+	inferred   2 Multiplexer(s).
+Unit <FIFO_SyncBlock_D2048_W8> synthesized.
+
+
+Synthesizing Unit <Replay_FileIO>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_FileIO_Sync.vhd".
+WARNING:Xst:647 - Input <i_fch_fm_core.data_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_hch_fm_core.data_valid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <spi_rx_cmd<3:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <spi_data_t> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_low<15:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_byte_sel<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_byte_cnt> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <mem_fifo_level<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <mem_fifo_level<9:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Register <o_hch_to_core.pos> equivalent to <o_fch_to_core.pos> has been removed
+    Register <o_hch_to_core.update> equivalent to <o_fch_to_core.update> has been removed
+    Register <spi_hch_tx> equivalent to <spi_fch_tx> has been removed
+    Found 4-bit register for signal <o_fch_to_core.inserted>.
+    Found 1-bit register for signal <o_fch_to_core.data_taken>.
+    Found 1-bit register for signal <o_hch_to_core.cmd_err>.
+    Found 1-bit register for signal <o_fch_to_core.cmd_done>.
+    Found 1-bit register for signal <o_hch_to_core.cmd_ack>.
+    Found 1-bit register for signal <o_fch_to_core.cmd_err>.
+    Found 1-bit register for signal <o_hch_to_core.status_we>.
+    Found 1-bit register for signal <o_fch_to_core.cmd_ack>.
+    Found 8-bit register for signal <o_hch_to_core.data>.
+    Found 1-bit register for signal <o_hch_to_core.cmd_done>.
+    Found 4-bit register for signal <o_fch_to_core.writable>.
+    Found 1-bit register for signal <o_hch_to_core.data_we>.
+    Found 1-bit register for signal <o_fch_to_core.data_we>.
+    Found 1-bit register for signal <o_fch_to_core.update>.
+    Found 1-bit register for signal <o_hch_to_core.data_taken>.
+    Found 4-bit register for signal <o_fch_to_core.pos>.
+    Found 8-bit register for signal <o_hch_to_core.status>.
+    Found 8-bit register for signal <o_fch_to_core.data>.
+    Found 32-bit register for signal <mem_addr>.
+    Found 32-bit adder for signal <mem_addr$add0000> created at line 495.
+    Found 1-bit register for signal <mem_fifo_rst>.
+    Found 10-bit register for signal <mem_len>.
+    Found 10-bit subtractor for signal <mem_len$sub0000> created at line 517.
+    Found 1-bit register for signal <mem_rd>.
+    Found 1-bit register for signal <mem_rd_ena>.
+    Found 8-bit register for signal <spi_byte_sel>.
+    Found 16-bit register for signal <spi_cmd_high>.
+    Found 16-bit register for signal <spi_cmd_low>.
+    Found 4-bit register for signal <spi_cs_meta>.
+    Found 8-bit register for signal <spi_data>.
+    Found 1-bit register for signal <spi_done>.
+    Found 8-bit register for signal <spi_fch_tx>.
+    Found 1-bit register for signal <spi_first>.
+    Found 1-bit register for signal <spi_mem_fifo_hfull>.
+    Found 8-bit register for signal <spi_mem_fifo_tx>.
+    Found 1-bit register for signal <spi_mem_fifo_valid>.
+    Found 1-bit register for signal <spi_mem_rd_ena>.
+    Found 4-bit up counter for signal <spi_pos_cnt>.
+    Found 1-bit register for signal <spi_rx_rdy_meta_1>.
+    Found 1-bit register for signal <spi_rx_rdy_meta_2>.
+    Found 1-bit register for signal <spi_rx_sof_meta_1>.
+    Found 1-bit register for signal <spi_rx_sof_meta_2>.
+    Found 1-bit register for signal <spi_sof>.
+    Found 48-bit register for signal <spi_stat_gen<6:1>>.
+    Found 1-bit register for signal <spi_stb>.
+    Summary:
+	inferred   1 Counter(s).
+	inferred 228 D-type flip-flop(s).
+	inferred   2 Adder/Subtractor(s).
+Unit <Replay_FileIO> synthesized.
+
+
+Synthesizing Unit <antic>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/antic.vhdl".
+WARNING:Xst:1780 - Signal <nmi_reset> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <line_buffer_address_reg<7:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <displayed_character_reg<4:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <addr_decoded<6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Using one-hot encoding for signal <dma_fetch_destination_reg>.
+    Using one-hot encoding for signal <instruction_type_reg>.
+INFO:Xst:2117 - HDL ADVISOR - Mux Selector <shift_rate_reg> of Case statement line 1502 was re-encoded using one-hot encoding. The case statement will be optimized (default statement optimization), but this optimization may lead to design initialization problems. To ensure the design works safely, you can:
+   	- add an 'INIT' attribute on signal <shift_rate_reg> (optimization is then done without any risk)
+   	- use the attribute 'signal_encoding user' to avoid onehot optimization
+   	- use the attribute 'safe_implementation yes' to force XST to perform a safe (but less efficient) optimization
+    Using one-hot encoding for signal <shift_rate_reg>.
+    Using one-hot encoding for signal <dma_speed_reg>.
+    Found 16x15-bit ROM for signal <instruction_reg_3_0$rom0000>.
+    Found 4x8-bit ROM for signal <playfield_display_end_cycle>.
+    Found 4x1-bit ROM for signal <dmactl_delayed_enabled>.
+    Found 8-bit adder for signal <$add0000> created at line 750.
+    Found 1-bit register for signal <allow_real_dma_reg>.
+    Found 3-bit register for signal <an_prev_reg>.
+    Found 3-bit register for signal <an_reg>.
+    Found 3-bit register for signal <chactl_reg>.
+    Found 8-bit register for signal <character_reg>.
+    Found 7-bit register for signal <chbase_raw_reg>.
+    Found 4-bit adder for signal <colour_clock_count_next$addsub0000> created at line 658.
+    Found 4-bit register for signal <colour_clock_count_reg>.
+    Found 4-bit comparator greatequal for signal <data_live_0$cmp_ge0000> created at line 1571.
+    Found 4-bit comparator less for signal <data_live_0$cmp_lt0000> created at line 1567.
+    Found 25-bit register for signal <delay_display_shift_reg>.
+    Found 1-bit register for signal <descenders_reg>.
+    Found 8-bit register for signal <display_list_address_low_temp_reg>.
+    Found 8-bit register for signal <display_shift_reg>.
+    Found 8-bit register for signal <displayed_character_reg>.
+    Found 1-bit register for signal <dli_enabled_reg>.
+    Found 1-bit register for signal <dli_nmi_reg>.
+    Found 3-bit adder for signal <dma_address_next$add0000> created at line 1011.
+    Found 3-bit xor2 for signal <dma_address_next$xor0000> created at line 954.
+    Found 3-bit xor2 for signal <dma_address_next$xor0001> created at line 960.
+    Found 16-bit register for signal <dma_address_reg>.
+    Found 6-bit register for signal <dma_fetch_destination_reg>.
+    Found 1-bit register for signal <dma_fetch_reg>.
+    Found 4-bit register for signal <dma_speed_reg>.
+    Found 7-bit register for signal <dmactl_raw_reg>.
+    Found 1-bit register for signal <first_line_of_instruction_reg>.
+    Found 1-bit 16-to-1 multiplexer for signal <force_final_row>.
+    Found 1-bit register for signal <hblank_reg>.
+    Found 8-bit register for signal <hcount_reg>.
+    Found 1-bit 16-to-1 multiplexer for signal <hscrol_enabled_next>.
+    Found 1-bit register for signal <hscrol_enabled_reg>.
+    Found 4-bit register for signal <hscrol_reg>.
+    Found 1-bit register for signal <instruction_blank_reg>.
+    Found 4-bit 16-to-1 multiplexer for signal <instruction_final_row_next>.
+    Found 4-bit register for signal <instruction_final_row_reg>.
+    Found 8-bit register for signal <instruction_reg>.
+    Found 5-bit 16-to-1 multiplexer for signal <instruction_type_next>.
+    Found 5-bit register for signal <instruction_type_reg>.
+    Found 4-bit comparator equal for signal <last_line_of_instruction_live$cmp_eq0000> created at line 1205.
+    Found 4-bit comparator equal for signal <last_line_of_instruction_live$cmp_eq0001> created at line 1209.
+    Found 1-bit register for signal <last_line_of_instruction_reg>.
+    Found 1-bit register for signal <map_background_reg>.
+    Found 1-bit register for signal <multi_colour_character_reg>.
+    Found 1-bit register for signal <nmi_reg>.
+    Found 16-bit register for signal <nmi_shiftreg_reg>.
+    Found 2-bit register for signal <nmien_raw_reg>.
+    Found 3-bit register for signal <nmist_reg>.
+    Found 8-bit register for signal <penh_reg>.
+    Found 8-bit register for signal <penv_reg>.
+    Found 1-bit register for signal <playfield_display_active_reg>.
+    Found 8-bit comparator equal for signal <playfield_display_active_reg$cmp_eq0000> created at line 943.
+    Found 8-bit comparator not equal for signal <playfield_display_active_reg$cmp_ne0000> created at line 939.
+    Found 8-bit comparator not equal for signal <playfield_display_active_reg$cmp_ne0001> created at line 943.
+    Found 8-bit 4-to-1 multiplexer for signal <playfield_display_start_cycle>.
+    Found 4-bit comparator greater for signal <playfield_display_start_cycle$cmp_gt0000> created at line 869.
+    Found 8-bit comparator equal for signal <playfield_dma_end$cmp_eq0000> created at line 935.
+    Found 8-bit comparator equal for signal <playfield_dma_start$cmp_eq0000> created at line 930.
+    Found 6-bit register for signal <pmbase_reg>.
+    Found 4-bit comparator less for signal <refresh_fetch_next$cmp_lt0000> created at line 1120.
+    Found 1-bit register for signal <refresh_fetch_reg>.
+    Found 1-bit register for signal <refresh_pending_reg>.
+    Found 4-bit comparator greatequal for signal <refresh_pending_reg$cmp_ge0000> created at line 1120.
+    Found 3-bit register for signal <shift_rate_reg>.
+    Found 1-bit register for signal <shift_twobit_reg>.
+    Found 4-bit register for signal <shiftclock_reg>.
+    Found 1-bit register for signal <single_colour_character_reg>.
+    Found 1-bit 16-to-1 multiplexer for signal <two_part_instruction_next>.
+    Found 1-bit register for signal <two_part_instruction_reg>.
+    Found 1-bit register for signal <twoline_character_reg>.
+    Found 1-bit register for signal <twopixel_reg>.
+    Found 1-bit register for signal <vbi_nmi_reg>.
+    Found 1-bit register for signal <vblank_reg>.
+    Found 9-bit up counter for signal <vcount_reg>.
+    Found 1-bit 16-to-1 multiplexer for signal <vscrol_enabled_next>.
+    Found 1-bit register for signal <vscrol_enabled_reg>.
+    Found 1-bit register for signal <vscrol_last_enabled_reg>.
+    Found 4-bit register for signal <vscrol_raw_reg>.
+    Found 1-bit register for signal <vsync_reg>.
+    Found 1-bit register for signal <wsync_reg>.
+    Summary:
+	inferred   3 ROM(s).
+	inferred   1 Counter(s).
+	inferred 202 D-type flip-flop(s).
+	inferred   3 Adder/Subtractor(s).
+	inferred  12 Comparator(s).
+	inferred  21 Multiplexer(s).
+Unit <antic> synthesized.
+
+
+Synthesizing Unit <pokey>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/pokey.vhdl".
+WARNING:Xst:646 - Signal <serout_shift_reg<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <serin_shift_reg<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <addr_decoded<12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 8x1-bit ROM for signal <clock_input>.
+    Found 1-bit tristate buffer for signal <SIO_CLOCK>.
+    Found 8-bit register for signal <audc0_reg>.
+    Found 8-bit register for signal <audc1_reg>.
+    Found 8-bit register for signal <audc2_reg>.
+    Found 8-bit register for signal <audc3_reg>.
+    Found 8-bit register for signal <audctl_reg>.
+    Found 8-bit register for signal <audf0_reg>.
+    Found 8-bit register for signal <audf1_reg>.
+    Found 8-bit register for signal <audf2_reg>.
+    Found 8-bit register for signal <audf3_reg>.
+    Found 1-bit register for signal <chan0_output_reg>.
+    Found 1-bit register for signal <chan1_output_reg>.
+    Found 1-bit register for signal <chan2_output_reg>.
+    Found 1-bit register for signal <chan3_output_reg>.
+    Found 1-bit register for signal <clock_reg>.
+    Found 1-bit register for signal <clock_sync_reg>.
+    Found 1-bit register for signal <highpass0_reg>.
+    Found 1-bit register for signal <highpass1_reg>.
+    Found 1-bit register for signal <irq_n_reg>.
+    Found 8-bit register for signal <irqen_reg>.
+    Found 8-bit register for signal <irqst_reg>.
+    Found 1-bit register for signal <keyboard_overrun_reg>.
+    Found 8-bit register for signal <pot0_reg>.
+    Found 8-bit register for signal <pot1_reg>.
+    Found 8-bit register for signal <pot2_reg>.
+    Found 8-bit register for signal <pot3_reg>.
+    Found 8-bit register for signal <pot4_reg>.
+    Found 8-bit register for signal <pot5_reg>.
+    Found 8-bit register for signal <pot6_reg>.
+    Found 8-bit register for signal <pot7_reg>.
+    Found 8-bit up counter for signal <pot_counter_reg>.
+    Found 1-bit register for signal <pot_reset_reg>.
+    Found 1-bit register for signal <serial_ip_framing_reg>.
+    Found 1-bit register for signal <serial_ip_overrun_reg>.
+    Found 1-bit register for signal <serial_out_reg>.
+    Found 4-bit register for signal <serin_bitcount_reg>.
+    Found 4-bit subtractor for signal <serin_bitcount_reg$addsub0000> created at line 1082.
+    Found 1-bit register for signal <serin_clock_last_reg>.
+    Found 1-bit register for signal <serin_clock_reg>.
+    Found 1-bit 8-to-1 multiplexer for signal <serin_enable>.
+    Found 8-bit register for signal <serin_reg>.
+    Found 10-bit register for signal <serin_shift_reg>.
+    Found 1-bit register for signal <serout_active_reg>.
+    Found 4-bit register for signal <serout_bitcount_reg>.
+    Found 4-bit subtractor for signal <serout_bitcount_reg$addsub0000> created at line 1003.
+    Found 1-bit register for signal <serout_clock_last_reg>.
+    Found 1-bit register for signal <serout_clock_reg>.
+    Found 1-bit 8-to-1 multiplexer for signal <serout_enable>.
+    Found 1-bit register for signal <serout_holding_full_reg>.
+    Found 8-bit register for signal <serout_holding_reg>.
+    Found 10-bit register for signal <serout_shift_reg>.
+    Found 1-bit register for signal <sio_in_reg>.
+    Found 1-bit register for signal <sio_out_reg>.
+    Found 8-bit register for signal <skctl_reg>.
+    Found 1-bit register for signal <twotone_reg>.
+    Found 1-bit xor2 for signal <volume_channel_0_next$xor0000> created at line 920.
+    Found 4-bit register for signal <volume_channel_0_reg>.
+    Found 1-bit xor2 for signal <volume_channel_1_next$xor0000> created at line 924.
+    Found 4-bit register for signal <volume_channel_1_reg>.
+    Found 4-bit register for signal <volume_channel_2_reg>.
+    Found 4-bit register for signal <volume_channel_3_reg>.
+    Summary:
+	inferred   1 ROM(s).
+	inferred   1 Counter(s).
+	inferred 243 D-type flip-flop(s).
+	inferred   2 Adder/Subtractor(s).
+	inferred   2 Multiplexer(s).
+	inferred   1 Tristate(s).
+Unit <pokey> synthesized.
+
+
+Synthesizing Unit <Replay_JoyPS2_Core_1>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd".
+WARNING:Xst:647 - Input <i_joy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1780 - Signal <msy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <msx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <msb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cpu_r_stb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cpu_port_id<5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cpu_int_ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 4-bit register for signal <clk_in>.
+    Found 1-bit register for signal <clk_in_falling>.
+    Found 1-bit register for signal <clk_in_r>.
+    Found 1-bit 4-to-1 multiplexer for signal <clk_in_r$mux0000>.
+    Found 8-bit register for signal <cpu_in_port>.
+    Found 4-bit register for signal <data_in>.
+    Found 1-bit register for signal <data_in_r>.
+    Found 1-bit 4-to-1 multiplexer for signal <data_in_r$mux0000>.
+    Found 1-bit register for signal <ps2_drive_clk_low>.
+    Found 1-bit register for signal <ps2_drive_data_low>.
+    Found 1-bit register for signal <rx_data>.
+    Found 1-bit register for signal <rx_falling_int>.
+    Found 1-bit register for signal <rx_falling_int_ack>.
+    Found 1-bit register for signal <rx_falling_int_ena>.
+    Found 2-bit register for signal <status>.
+    Found 1-bit register for signal <timer_int>.
+    Found 1-bit register for signal <timer_int_ack>.
+    Found 1-bit register for signal <timer_int_ena>.
+    Summary:
+	inferred  30 D-type flip-flop(s).
+	inferred   2 Multiplexer(s).
+Unit <Replay_JoyPS2_Core_1> synthesized.
+
+
+Synthesizing Unit <Replay_JoyPS2_Core_2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd".
+WARNING:Xst:647 - Input <i_joy> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1780 - Signal <msy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <msx> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <msb> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cpu_r_stb> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cpu_port_id<5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cpu_int_ack> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 4-bit register for signal <clk_in>.
+    Found 1-bit register for signal <clk_in_falling>.
+    Found 1-bit register for signal <clk_in_r>.
+    Found 1-bit 4-to-1 multiplexer for signal <clk_in_r$mux0000>.
+    Found 8-bit register for signal <cpu_in_port>.
+    Found 4-bit register for signal <data_in>.
+    Found 1-bit register for signal <data_in_r>.
+    Found 1-bit 4-to-1 multiplexer for signal <data_in_r$mux0000>.
+    Found 1-bit register for signal <ps2_drive_clk_low>.
+    Found 1-bit register for signal <ps2_drive_data_low>.
+    Found 1-bit register for signal <rx_data>.
+    Found 1-bit register for signal <rx_falling_int>.
+    Found 1-bit register for signal <rx_falling_int_ack>.
+    Found 1-bit register for signal <rx_falling_int_ena>.
+    Found 2-bit register for signal <status>.
+    Found 1-bit register for signal <timer_int>.
+    Found 1-bit register for signal <timer_int_ack>.
+    Found 1-bit register for signal <timer_int_ena>.
+    Summary:
+	inferred  30 D-type flip-flop(s).
+	inferred   2 Multiplexer(s).
+Unit <Replay_JoyPS2_Core_2> synthesized.
+
+
+Synthesizing Unit <Replay_DDRCtrl>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl.vhd".
+WARNING:Xst:646 - Signal <cur_w_l> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cur_addr<23:11>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+INFO:Xst:1799 - State 1101 is never reached in FSM <b0_state>.
+INFO:Xst:1799 - State 1100 is never reached in FSM <b0_state>.
+INFO:Xst:1799 - State 1110 is never reached in FSM <b0_state>.
+    Found finite state machine <FSM_8> for signal <b0_state>.
+    -----------------------------------------------------------------------
+    | States             | 11                                             |
+    | Transitions        | 14                                             |
+    | Inputs             | 3                                              |
+    | Outputs            | 3                                              |
+    | Clock              | i_clk                     (rising_edge)        |
+    | Reset              | ram_startup_done          (negative)           |
+    | Reset type         | synchronous                                    |
+    | Reset State        | 1111                                           |
+    | Power Up State     | 0000                                           |
+    | Encoding           | automatic                                      |
+    | Implementation     | automatic                                      |
+    -----------------------------------------------------------------------
+    Found 16x7-bit ROM for signal <ram_startup_cnt$rom0000>.
+    Found 24-bit register for signal <cur_addr>.
+    Found 4-bit register for signal <cur_w_be>.
+    Found 32-bit register for signal <cur_w_data>.
+    Found 1-bit 16-to-1 multiplexer for signal <inc$mux0001> created at line 218.
+    Found 1-bit register for signal <ram_cke_enable>.
+    Found 3-bit register for signal <ram_cmd_s>.
+    Found 4-bit register for signal <ram_mux_s>.
+    Found 4-bit up counter for signal <ram_startup_cnt>.
+    Found 9-bit up counter for signal <ram_startup_delay>.
+    Found 1-bit register for signal <ram_startup_done>.
+    Found 1-bit 16-to-1 multiplexer for signal <ram_startup_done$mux0000> created at line 218.
+    Found 4-bit up accumulator for signal <ref_cnt>.
+    Found 12-bit down counter for signal <ref_div>.
+    Found 1-bit register for signal <ref_req>.
+    Found 16-bit up counter for signal <start_up_cnt>.
+    Found 1-bit register for signal <start_up_wait>.
+    Summary:
+	inferred   1 Finite State Machine(s).
+	inferred   1 ROM(s).
+	inferred   4 Counter(s).
+	inferred   1 Accumulator(s).
+	inferred  71 D-type flip-flop(s).
+	inferred   2 Multiplexer(s).
+Unit <Replay_DDRCtrl> synthesized.
+
+
+Synthesizing Unit <Replay_OSD>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_OSD.vhd".
+WARNING:Xst:1780 - Signal <pix_ena_t> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <pix_active_t<3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <osd_sol> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <font_addr_t1<12:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <char_vid_dout_t1<6:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 8x8-bit ROM for signal <op0$mux0000> created at line 153.
+    Found 8x8-bit ROM for signal <pix_op_0$mux0000> created at line 452.
+    Found 8x8-bit ROM for signal <pix_op_1$mux0000> created at line 452.
+    Found 8x8-bit ROM for signal <pix_op_2$mux0000> created at line 452.
+    Found 24-bit register for signal <o_vid_rgb>.
+    Found 4-bit register for signal <attrib.bg>.
+    Found 4-bit register for signal <attrib.fg>.
+    Found 1-bit register for signal <attrib.invert>.
+    Found 16-bit register for signal <char_vid_dout_t1>.
+    Found 15-bit register for signal <font_addr_t1>.
+    Found 2-bit 4-to-1 multiplexer for signal <font_dout>.
+    Found 10-bit register for signal <osd_cpos>.
+    Found 10-bit adder for signal <osd_cpos$addsub0000> created at line 209.
+    Found 1-bit register for signal <osd_eol>.
+    Found 1-bit register for signal <osd_hactive>.
+    Found 10-bit register for signal <osd_hpos>.
+    Found 10-bit adder for signal <osd_hpos$addsub0000> created at line 208.
+    Found 1-bit register for signal <osd_htog>.
+    Found 1-bit register for signal <osd_vactive>.
+    Found 9-bit register for signal <osd_vpos>.
+    Found 9-bit adder for signal <osd_vpos_8$add0000> created at line 232.
+    Found 4-bit adder for signal <osd_vpos_o>.
+    Found 1-bit register for signal <osd_vtog>.
+    Found 4-bit register for signal <pix_active_t>.
+    Found 2-bit 4-to-1 multiplexer for signal <pix_bg$mux0001> created at line 449.
+    Found 2-bit 4-to-1 multiplexer for signal <pix_bg$mux0002> created at line 449.
+    Found 2-bit 4-to-1 multiplexer for signal <pix_bg$mux0003> created at line 449.
+    Found 4-bit register for signal <pix_h_t1>.
+    Found 24-bit 4-to-1 multiplexer for signal <pix_op>.
+    Found 4-bit register for signal <pix_v_t1>.
+    Found 2-bit register for signal <shifter_data>.
+    Found 4-bit register for signal <voffset>.
+    Found 4-bit register for signal <voffset_sync>.
+    Summary:
+	inferred   4 ROM(s).
+	inferred 120 D-type flip-flop(s).
+	inferred   4 Adder/Subtractor(s).
+	inferred  32 Multiplexer(s).
+Unit <Replay_OSD> synthesized.
+
+
+Synthesizing Unit <Replay_JoyPS2>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_JoyPS2.vhd".
+WARNING:Xst:646 - Signal <status_a> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 3-bit register for signal <o_ms_butn>.
+    Found 1-bit register for signal <o_kb_ps2_we>.
+    Found 8-bit register for signal <o_kb_ps2_data>.
+    Found 12-bit register for signal <o_ms_posx>.
+    Found 12-bit register for signal <o_ms_posy>.
+    Found 1-bit register for signal <o_ms_we>.
+    Found 6-bit register for signal <joy_a_reg>.
+    Found 6-bit register for signal <joy_b_reg>.
+    Summary:
+	inferred  49 D-type flip-flop(s).
+Unit <Replay_JoyPS2> synthesized.
+
+
+Synthesizing Unit <Replay_DDRCtrl_Top>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_DDRCtrl_Top.vhd".
+WARNING:Xst:646 - Signal <start_b> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Register <lp_w_data<16>> equivalent to <lp_w_data<0>> has been removed
+    Register <lp_w_data<24>> equivalent to <lp_w_data<0>> has been removed
+    Register <lp_w_data<8>> equivalent to <lp_w_data<0>> has been removed
+    Register <lp_w_data<18>> equivalent to <lp_w_data<10>> has been removed
+    Register <lp_w_data<26>> equivalent to <lp_w_data<10>> has been removed
+    Register <lp_w_data<2>> equivalent to <lp_w_data<10>> has been removed
+    Register <lp_w_data<19>> equivalent to <lp_w_data<11>> has been removed
+    Register <lp_w_data<27>> equivalent to <lp_w_data<11>> has been removed
+    Register <lp_w_data<3>> equivalent to <lp_w_data<11>> has been removed
+    Register <lp_w_data<20>> equivalent to <lp_w_data<12>> has been removed
+    Register <lp_w_data<28>> equivalent to <lp_w_data<12>> has been removed
+    Register <lp_w_data<4>> equivalent to <lp_w_data<12>> has been removed
+    Register <lp_w_data<21>> equivalent to <lp_w_data<13>> has been removed
+    Register <lp_w_data<29>> equivalent to <lp_w_data<13>> has been removed
+    Register <lp_w_data<5>> equivalent to <lp_w_data<13>> has been removed
+    Register <lp_w_data<22>> equivalent to <lp_w_data<14>> has been removed
+    Register <lp_w_data<30>> equivalent to <lp_w_data<14>> has been removed
+    Register <lp_w_data<6>> equivalent to <lp_w_data<14>> has been removed
+    Register <lp_w_data<23>> equivalent to <lp_w_data<15>> has been removed
+    Register <lp_w_data<31>> equivalent to <lp_w_data<15>> has been removed
+    Register <lp_w_data<7>> equivalent to <lp_w_data<15>> has been removed
+    Register <lp_w_data<1>> equivalent to <lp_w_data<17>> has been removed
+    Register <lp_w_data<25>> equivalent to <lp_w_data<17>> has been removed
+    Register <lp_w_data<9>> equivalent to <lp_w_data<17>> has been removed
+    Found 4x4-bit ROM for signal <lp_w_be$mux0001> created at line 240.
+    Found 8-bit register for signal <o_lp_r_data>.
+    Found 1-bit register for signal <o_lp_r_we>.
+    Found 32-bit register for signal <o_hp_r_data>.
+    Found 1-bit register for signal <o_cfg_ready>.
+    Found 1-bit register for signal <cur_hp>.
+    Found 1-bit register for signal <cur_lp>.
+    Found 1-bit register for signal <cur_read>.
+    Found 1-bit register for signal <ena_sys_t1>.
+    Found 1-bit register for signal <ena_sys_t2>.
+    Found 1-bit register for signal <ena_sys_t3>.
+    Found 24-bit register for signal <hp_addr>.
+    Found 1-bit register for signal <hp_rw_l>.
+    Found 1-bit register for signal <hp_valid>.
+    Found 4-bit register for signal <hp_w_be>.
+    Found 32-bit register for signal <hp_w_data>.
+    Found 24-bit register for signal <lp_addr>.
+    Found 2-bit register for signal <lp_r_sel>.
+    Found 1-bit register for signal <lp_rw_l>.
+    Found 1-bit register for signal <lp_valid>.
+    Found 4-bit register for signal <lp_w_be>.
+    Found 1-bit register for signal <lp_w_data<17>>.
+    Found 6-bit register for signal <lp_w_data<15:10>>.
+    Found 1-bit register for signal <lp_w_data<0>>.
+    Found 8-bit 4-to-1 multiplexer for signal <o_lp_r_data$mux0001> created at line 422.
+    Found 4-bit up counter for signal <phase>.
+    Found 1-bit xor2 for signal <phase$xor0000> created at line 194.
+    Found 1-bit register for signal <r_buf_ena>.
+    Found 1-bit register for signal <r_we_hp>.
+    Found 1-bit register for signal <r_we_lp>.
+    Found 1-bit register for signal <start_a>.
+    Found 1-bit register for signal <sys_cur_hp>.
+    Found 1-bit register for signal <sys_cur_lp>.
+    Found 1-bit register for signal <sys_cur_read>.
+    Found 1-bit register for signal <sys_taken>.
+    Found 1-bit register for signal <sys_taken_meta1>.
+    Summary:
+	inferred   1 ROM(s).
+	inferred   1 Counter(s).
+	inferred 159 D-type flip-flop(s).
+	inferred   8 Multiplexer(s).
+Unit <Replay_DDRCtrl_Top> synthesized.
+
+
+Synthesizing Unit <Replay_Syscon>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Syscon.vhd".
+WARNING:Xst:646 - Signal <spi_rx_cmd<7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_low<15:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_low<7:4>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<15:13>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<11:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<4:3>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_cmd_high<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_byte_sel<7:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <h_size<0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+    Register <o_vid_sync.dig_vs> equivalent to <o_vbl> has been removed
+    Found 8-bit register for signal <o_cfg_fileio>.
+    Found 1-bit register for signal <o_vid_sync.ana_vs>.
+    Found 1-bit register for signal <o_vid_sync.ana_de>.
+    Found 1-bit register for signal <o_vbl>.
+    Found 1-bit register for signal <o_vid_sync.ana_hs>.
+    Found 1-bit register for signal <o_vid_sync.dig_de>.
+    Found 32-bit register for signal <o_cfg_static>.
+    Found 1-bit register for signal <o_vid_sync.dig_hs>.
+    Found 11-bit register for signal <char_addr>.
+    Found 11-bit adder for signal <char_addr$add0000> created at line 396.
+    Found 12-bit up counter for signal <h_count>.
+    Found 12-bit register for signal <h_size>.
+    Found 12-bit subtractor for signal <h_start_pos>.
+    Found 12-bit subtractor for signal <h_start_pos$mux0000> created at line 535.
+    Found 2-bit register for signal <hs_t>.
+    Found 1-bit register for signal <osd_ena>.
+    Found 1-bit register for signal <osd_hexp>.
+    Found 1-bit register for signal <osd_hstart>.
+    Found 12-bit comparator equal for signal <osd_hstart$cmp_eq0000> created at line 554.
+    Found 1-bit register for signal <osd_oddline>.
+    Found 1-bit register for signal <osd_prog>.
+    Found 1-bit xor2 for signal <osd_prog$xor0000> created at line 518.
+    Found 1-bit register for signal <osd_vstart>.
+    Found 12-bit comparator equal for signal <osd_vstart$cmp_eq0000> created at line 559.
+    Found 8-bit register for signal <spi_byte_sel>.
+    Found 16-bit register for signal <spi_cmd_high>.
+    Found 16-bit register for signal <spi_cmd_low>.
+    Found 16-bit register for signal <spi_ctrl.cfg_ctrl>.
+    Found 32-bit register for signal <spi_ctrl.cfg_dynamic>.
+    Found 8-bit register for signal <spi_ctrl.cfg_fileio>.
+    Found 32-bit register for signal <spi_ctrl.cfg_static>.
+    Found 1-bit register for signal <spi_ctrl.halt>.
+    Found 1-bit register for signal <spi_ctrl.keyboard_dis>.
+    Found 1-bit register for signal <spi_ctrl.osd_ena>.
+    Found 1-bit register for signal <spi_ctrl.reset>.
+    Found 8-bit register for signal <spi_data>.
+    Found 1-bit register for signal <spi_rx_rdy_meta_1>.
+    Found 1-bit register for signal <spi_rx_rdy_meta_2>.
+    Found 1-bit register for signal <spi_rx_sof_meta_1>.
+    Found 1-bit register for signal <spi_rx_sof_meta_2>.
+    Found 1-bit register for signal <spi_sof>.
+    Found 1-bit register for signal <spi_stb>.
+    Found 8-bit register for signal <spi_tx_cfg_fileio>.
+    Found 16-bit register for signal <spi_tx_cfg_status>.
+    Found 8-bit register for signal <spi_tx_kbd>.
+    Found 8-bit register for signal <spi_tx_status>.
+    Found 12-bit up counter for signal <v_count>.
+    Found 12-bit register for signal <v_size>.
+    Found 12-bit subtractor for signal <v_start_pos>.
+    Found 2-bit register for signal <vs_t>.
+    Summary:
+	inferred   2 Counter(s).
+	inferred 277 D-type flip-flop(s).
+	inferred   4 Adder/Subtractor(s).
+	inferred   2 Comparator(s).
+Unit <Replay_Syscon> synthesized.
+
+
+Synthesizing Unit <zpu_config_regs>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/zpu_config_regs.vhdl".
+WARNING:Xst:647 - Input <SWITCH> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <spi_tx_data> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <spi_speed_reg_integer> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_speed_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <spi_rx_data> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
+WARNING:Xst:653 - Signal <spi_mosi> is used but never assigned. This sourceless signal will be automatically connected to value 0.
+WARNING:Xst:646 - Signal <spi_miso> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_enable> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <spi_clk_out> is used but never assigned. This sourceless signal will be automatically connected to value 0.
+WARNING:Xst:653 - Signal <spi_chip_select<0>> is used but never assigned. This sourceless signal will be automatically connected to value 0.
+WARNING:Xst:653 - Signal <spi_busy> is used but never assigned. This sourceless signal will be automatically connected to value 0.
+WARNING:Xst:1780 - Signal <spi_addr_reg_integer> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <spi_addr_reg> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <addr_decoded<15:12>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 8-bit register for signal <config_6502_reg>.
+    Found 1-bit register for signal <gpio_enable_reg>.
+    Found 8-bit register for signal <ledg_reg>.
+    Found 10-bit register for signal <ledr_reg>.
+    Found 32-bit 4-to-1 multiplexer for signal <pause_next>.
+    Found 32-bit subtractor for signal <pause_next$addsub0000> created at line 355.
+    Found 32-bit register for signal <pause_reg>.
+    Found 1-bit register for signal <paused_reg>.
+    Found 3-bit register for signal <ram_select_reg>.
+    Found 1-bit register for signal <reset_6502_cpu_reg>.
+    Found 1-bit register for signal <reset_n_reg>.
+    Found 1-bit register for signal <reset_zpu_reg>.
+    Found 2-bit register for signal <rom_select_reg>.
+    Found 32-bit register for signal <sector_reg>.
+    Found 1-bit register for signal <sector_request_reg>.
+    Found 16-bit register for signal <zpu_hex_reg>.
+    Summary:
+	inferred 117 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred  32 Multiplexer(s).
+Unit <zpu_config_regs> synthesized.
+
+
+Synthesizing Unit <atari800core>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/atari800core.vhd".
+WARNING:Xst:647 - Input <JOY2_n<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <matrix_out<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <JOY1_n<5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <vcount_temp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <mist_switches> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <mist_buttons> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <hcount_temp> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <gtia_blank> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dummy_sector_request> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <dummy_sector> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <ZPU_SECTOR_DATA> is used but never assigned. This sourceless signal will be automatically connected to value 00000000000000000000000000000000.
+WARNING:Xst:646 - Signal <ZPU_HEX> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <ZPU_ADDR_ROM_RAM<23:14>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <ZPU_ADDR_ROM_RAM<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <VIRTUAL_TRIGGERS<1:0>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <VIRTUAL_STICKS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <VGA_G_dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <VGA_B_dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <VGA> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <UART_TXD_dummy> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <TRIGGERS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SYNC_KEYS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <SHIFT_PRESSED_DUMMY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <SHIFT_PRESSED> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SD_DAT3> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <SD_DAT0> is used but never assigned. This sourceless signal will be automatically connected to value 0.
+WARNING:Xst:646 - Signal <SD_CMD> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SD_CLK> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SDRAM_REFRESH> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SCANDOUBLER_SHARED_ENABLE_LOW> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SCANDOUBLER_SHARED_ENABLE_HIGH> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <ROM_SELECT_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <RAM_SELECT_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <RAM_DO<15:8>> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
+WARNING:Xst:646 - Signal <POT_RESET> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <POT_IN> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
+WARNING:Xst:646 - Signal <PORTB_DIR_OUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <PBI_WRITE_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <PBI_ADDR<15:5>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <LEDR_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <LEDG_dummy> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <KEY_INTERRUPT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <KEY_HELD> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <KBCODE> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GREREN_LEDS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GREEN_LEDS> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <GPIO_SIO_OUT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_SIO_IN> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <GPIO_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_1_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_1_IN> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_1_DIR_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_0_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_0_IN> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <GPIO_0_DIR_OUT> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <CONTROL_PRESSED> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <COMPOSITE_ON_HSYNC> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <CART_S5_N> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <CART_S4_n> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <CART_REQUEST> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <CART_CCTL_N> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <BREAK_PRESSED_DUMMY> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <BREAK_PRESSED> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+Unit <atari800core> synthesized.
+
+
+Synthesizing Unit <Core_Top>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Core_Top.vhd".
+WARNING:Xst:1305 - Output <debug> is never assigned. Tied to value 000000000000000000000000000000000000.
+WARNING:Xst:1305 - Output <o_act_led_n> is never assigned. Tied to value 0.
+WARNING:Xst:647 - Input <I_CART_RO> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <drive_address> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <CONF_WR_1541> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <hp_ddr_wr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_Ms_We> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <I_RAM_EXT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <CONF_WR> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <floppy_inserted> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1305 - Output <media_read_o> is never assigned. Tied to value 0.
+WARNING:Xst:647 - Input <i_Ms_Butn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <debugi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <hp_ddr_taken> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <diskid_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_Ena_Sub1> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <media_dat_i> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:1305 - Output <media_adr_o> is never assigned. Tied to value 000000000000000000.
+WARNING:Xst:647 - Input <core_ps2_clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_Ena_Sub4> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <CONF_AI<15:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_Ms_PosX> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_Ms_PosY> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <core_ps2_data> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_Audio_Taken> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <I_CART_EN> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <i_RS232_CTS> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:647 - Input <write_prot_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <matrix_out_mix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <joy_mix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <fdata_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <fclk_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <fatn_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <data_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <core_blankn_ds> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <core_blank> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <clk_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cdata_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cclk_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <catn_o> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <atn_i> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SDRAM_WIDTH_16bit_ACCESS> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <SDRAM_READ_ENABLE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 24-bit up counter for signal <core_blank_count_reg>.
+    Found 24-bit comparator less for signal <core_blankn_s$cmp_lt0000> created at line 350.
+    Found 1-bit register for signal <ddr_request_pending_reg>.
+    Found 1-bit register for signal <ddr_response_pending_reg>.
+    Found 24-bit 4-to-1 multiplexer for signal <lsample_s>.
+    Found 24-bit 4-to-1 multiplexer for signal <rsample_s>.
+    Found 1-bit register for signal <sh_lock_key>.
+    Found 1-bit register for signal <stat6_del>.
+    Summary:
+	inferred   1 Counter(s).
+	inferred   4 D-type flip-flop(s).
+	inferred   1 Comparator(s).
+	inferred  48 Multiplexer(s).
+Unit <Core_Top> synthesized.
+
+
+Synthesizing Unit <Replay_Top>.
+    Related source file is "/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay_Top.vhd".
+WARNING:Xst:647 - Input <i_Aux_IP> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+WARNING:Xst:646 - Signal <tick> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <ram_valid> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <ram_r_w_l> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <ram_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <ram_addr> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <media_read> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:653 - Signal <media_dat> is used but never assigned. This sourceless signal will be automatically connected to value 00000000.
+WARNING:Xst:646 - Signal <media_adr> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <mch_ram_taken> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <mch_ram_rd_we> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <mch_ram_rd_data> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <led> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <hp_ddr_addr<1:0>> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_trig> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_control0> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <cs_clk> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.v_pix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.v_oddline> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.h_pix> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.f2> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.dig_sol> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.dig_sof> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.dig_act_v> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_timing.dig_act_h> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_std.v_active> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_std.prog> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_std.h_rep> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <core_vid_std.h_active> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:1780 - Signal <conf_taken> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cfg_static<31:6>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cfg_fileio_i> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cfg_dynamic<31:19>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cfg_dynamic<15:9>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+WARNING:Xst:646 - Signal <cfg_ctrl<15:10>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
+    Found 1-bit tristate buffer for signal <b_Video_SPC>.
+    Found 1-bit tristate buffer for signal <b_Video_SPD>.
+    Found 1-bit tristate buffer for signal <b_PS2A_Clk>.
+    Found 1-bit tristate buffer for signal <b_PS2A_Data>.
+    Found 1-bit tristate buffer for signal <b_PS2B_Clk>.
+    Found 1-bit tristate buffer for signal <b_PS2B_Data>.
+    Found 1-bit tristate buffer for signal <b_SCL>.
+    Found 1-bit tristate buffer for signal <b_SDA>.
+    Found 1-bit tristate buffer for signal <b_FPGA_SPI_MISO>.
+    Found 1-bit tristate buffer for signal <o_Clk_68K>.
+    Found 16-bit register for signal <diskid_s>.
+    Found 1-bit register for signal <ena_sub1>.
+    Found 1-bit register for signal <ena_sub4>.
+    Found 1-bit register for signal <ena_sys>.
+    Found 1-bit register for signal <ena_sys_ddr>.
+    Found 1-bit register for signal <init_diskinsert_s>.
+    Found 19-bit register for signal <inscnt_s>.
+    Found 19-bit subtractor for signal <inscnt_s$addsub0000> created at line 693.
+    Found 16-bit down counter for signal <PreCounter1>.
+    Found 12-bit down counter for signal <PreCounter2>.
+    Found 5-bit up counter for signal <sub_cnt>.
+    Found 2-bit up counter for signal <sys_cnt>.
+    Found 1-bit register for signal <tick_pre1>.
+    Found 1-bit register for signal <writeprotn_s>.
+    Summary:
+	inferred   4 Counter(s).
+	inferred  42 D-type flip-flop(s).
+	inferred   1 Adder/Subtractor(s).
+	inferred  11 Tristate(s).
+Unit <Replay_Top> synthesized.
+
+
+=========================================================================
+HDL Synthesis Report
+
+Macro Statistics
+# RAMs                                                 : 7
+ 1024x8-bit single-port RAM                            : 4
+ 16384x8-bit single-port RAM                           : 1
+ 2048x24-bit dual-port RAM                             : 1
+ 512x8-bit dual-port RAM                               : 1
+# ROMs                                                 : 24
+ 16384x8-bit ROM                                       : 1
+ 16x15-bit ROM                                         : 1
+ 16x7-bit ROM                                          : 1
+ 256x24-bit ROM                                        : 1
+ 256x44-bit ROM                                        : 1
+ 32x6-bit ROM                                          : 4
+ 4096x32-bit ROM                                       : 1
+ 4x1-bit ROM                                           : 1
+ 4x12-bit ROM                                          : 1
+ 4x4-bit ROM                                           : 1
+ 4x8-bit ROM                                           : 1
+ 64x16-bit ROM                                         : 2
+ 8192x8-bit ROM                                        : 1
+ 8x1-bit ROM                                           : 3
+ 8x8-bit ROM                                           : 4
+# Multipliers                                          : 2
+ 14x14-bit multiplier                                  : 1
+ 32x32-bit multiplier                                  : 1
+# Adders/Subtractors                                   : 105
+ 10-bit adder                                          : 3
+ 10-bit subtractor                                     : 1
+ 11-bit adder                                          : 1
+ 12-bit adder                                          : 1
+ 12-bit subtractor                                     : 3
+ 14-bit adder                                          : 10
+ 14-bit adder carry out                                : 1
+ 14-bit subtractor                                     : 6
+ 15-bit subtractor                                     : 2
+ 16-bit adder                                          : 7
+ 19-bit subtractor                                     : 1
+ 22-bit adder                                          : 3
+ 22-bit adder carry in                                 : 1
+ 22-bit subtractor                                     : 1
+ 24-bit adder                                          : 2
+ 28-bit adder                                          : 1
+ 28-bit subtractor                                     : 1
+ 3-bit adder                                           : 1
+ 32-bit adder                                          : 3
+ 32-bit subtractor                                     : 2
+ 4-bit adder                                           : 4
+ 4-bit subtractor                                      : 7
+ 5-bit adder                                           : 11
+ 5-bit subtractor                                      : 1
+ 6-bit adder                                           : 5
+ 6-bit subtractor                                      : 1
+ 7-bit adder                                           : 3
+ 8-bit adder                                           : 3
+ 8-bit addsub                                          : 1
+ 8-bit subtractor                                      : 14
+ 9-bit adder                                           : 3
+ 9-bit adder carry in                                  : 1
+# Counters                                             : 39
+ 11-bit up counter                                     : 2
+ 12-bit down counter                                   : 2
+ 12-bit up counter                                     : 2
+ 14-bit up counter                                     : 2
+ 16-bit down counter                                   : 1
+ 16-bit up counter                                     : 1
+ 2-bit up counter                                      : 1
+ 24-bit up counter                                     : 1
+ 3-bit up counter                                      : 2
+ 4-bit up counter                                      : 9
+ 5-bit up counter                                      : 3
+ 6-bit up counter                                      : 3
+ 8-bit down counter                                    : 2
+ 8-bit up counter                                      : 6
+ 9-bit up counter                                      : 2
+# Accumulators                                         : 4
+ 12-bit up accumulator                                 : 1
+ 4-bit up accumulator                                  : 2
+ 8-bit up accumulator                                  : 1
+# Registers                                            : 1508
+ 1-bit register                                        : 785
+ 10-bit register                                       : 9
+ 12-bit register                                       : 3
+ 13-bit register                                       : 1
+ 14-bit register                                       : 15
+ 15-bit register                                       : 3
+ 16-bit register                                       : 26
+ 17-bit register                                       : 3
+ 18-bit register                                       : 1
+ 19-bit register                                       : 1
+ 2-bit register                                        : 64
+ 22-bit register                                       : 2
+ 24-bit register                                       : 9
+ 25-bit register                                       : 1
+ 28-bit register                                       : 1
+ 3-bit register                                        : 38
+ 32-bit register                                       : 17
+ 4-bit register                                        : 77
+ 44-bit register                                       : 1
+ 5-bit register                                        : 8
+ 6-bit register                                        : 19
+ 7-bit register                                        : 68
+ 8-bit register                                        : 355
+ 9-bit register                                        : 1
+# Comparators                                          : 68
+ 12-bit comparator equal                               : 2
+ 14-bit comparator equal                               : 17
+ 14-bit comparator lessequal                           : 2
+ 14-bit comparator not equal                           : 9
+ 24-bit comparator less                                : 1
+ 32-bit comparator equal                               : 1
+ 32-bit comparator greater                             : 2
+ 32-bit comparator less                                : 2
+ 32-bit comparator lessequal                           : 2
+ 4-bit comparator equal                                : 2
+ 4-bit comparator greatequal                           : 2
+ 4-bit comparator greater                              : 1
+ 4-bit comparator less                                 : 2
+ 5-bit comparator greater                              : 4
+ 6-bit comparator equal                                : 4
+ 8-bit comparator equal                                : 12
+ 8-bit comparator greater                              : 1
+ 8-bit comparator not equal                            : 2
+# Multiplexers                                         : 62
+ 1-bit 16-to-1 multiplexer                             : 6
+ 1-bit 4-to-1 multiplexer                              : 11
+ 1-bit 8-to-1 multiplexer                              : 16
+ 2-bit 4-to-1 multiplexer                              : 4
+ 24-bit 4-to-1 multiplexer                             : 2
+ 24-bit 8-to-1 multiplexer                             : 1
+ 32-bit 4-to-1 multiplexer                             : 1
+ 4-bit 16-to-1 multiplexer                             : 1
+ 5-bit 16-to-1 multiplexer                             : 1
+ 6-bit 4-to-1 multiplexer                              : 1
+ 8-bit 4-to-1 multiplexer                              : 18
+# Decoders                                             : 1
+ 1-of-16 decoder                                       : 1
+# Tristates                                            : 16
+ 1-bit tristate buffer                                 : 16
+# Xors                                                 : 24
+ 1-bit xor2                                            : 21
+ 3-bit xor2                                            : 2
+ 8-bit xor2                                            : 1
+
+=========================================================================
+
+=========================================================================
+*                       Advanced HDL Synthesis                          *
+=========================================================================
+
+Analyzing FSM <FSM_8> for best encoding.
+Optimizing FSM <u_DDRCtrl/u_ddr_ctrl/b0_state/FSM> on signal <b0_state[1:11]> with one-hot encoding.
+----------------------
+ State | Encoding
+----------------------
+ 0000  | 00000000001
+ 0001  | 00000000100
+ 0010  | 00000100000
+ 0011  | 00000010000
+ 0100  | 00001000000
+ 0101  | 00010000000
+ 0110  | 00100000000
+ 0111  | 01000000000
+ 1010  | 00000001000
+ 1011  | 10000000000
+ 1100  | unreached
+ 1101  | unreached
+ 1110  | unreached
+ 1111  | 00000000010
+----------------------
+Analyzing FSM <FSM_7> for best encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/pmg_dma_state_reg/FSM> on signal <pmg_dma_state_reg[1:3]> with gray encoding.
+-------------------
+ State | Encoding
+-------------------
+ 000   | 011
+ 001   | 010
+ 010   | 110
+ 011   | 111
+ 100   | 101
+ 101   | 000
+ 110   | 001
+-------------------
+Analyzing FSM <FSM_6> for best encoding.
+Optimizing FSM <u_Video/u_I2C/State/FSM> on signal <State[1:3]> with gray encoding.
+------------------------
+ State      | Encoding
+------------------------
+ s_idle     | 000
+ s_devid    | 001
+ s_ack1     | 011
+ s_rab      | 010
+ s_ack2     | 111
+ s_data     | 101
+ s_read     | 110
+ s_ack_read | 100
+------------------------
+Analyzing FSM <FSM_5> for best encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/player0/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/player1/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/player2/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/player3/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/missile0/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/missile1/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/missile2/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+Optimizing FSM <u_Core/atari800core/gtia1/missile3/count_reg/FSM> on signal <count_reg[1:2]> with user encoding.
+-------------------
+ State | Encoding
+-------------------
+ 00    | 00
+ 01    | 01
+ 10    | 10
+ 11    | 11
+-------------------
+Analyzing FSM <FSM_4> for best encoding.
+Optimizing FSM <u_Core/atari800core/zpu_config1/uart1/pokey_keyboard_scanner1/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
+Optimizing FSM <u_Core/atari800core/pokey2/pokey_keyboard_scanner1/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
+Optimizing FSM <u_Core/atari800core/pokey1/pokey_keyboard_scanner1/state_reg/FSM> on signal <state_reg[1:2]> with gray encoding.
+-------------------
+ State | Encoding
+-------------------
+ 00    | 00
+ 01    | 01
+ 10    | 11
+ 11    | 10
+-------------------
+Analyzing FSM <FSM_3> for best encoding.
+Optimizing FSM <u_Core/atari800core/zpu_glue1/myzpu/state/FSM> on signal <state[1:4]> with gray encoding.
+-------------------------------
+ State             | Encoding
+-------------------------------
+ st_load2          | 1110
+ st_popped         | 1111
+ st_load_sp2       | 0100
+ st_load_sp3       | 1001
+ st_add_sp2        | 1101
+ st_fetch          | 1100
+ st_execute        | 0111
+ st_decode         | 0010
+ st_decode2        | 0110
+ st_resync         | 0000
+ st_store_sp2      | 0101
+ st_resync2        | 0001
+ st_resync3        | 0011
+ st_loadb2         | 1011
+ st_mult2          | unreached
+ st_mult3          | unreached
+ st_mult5          | 1010
+ st_mult4          | unreached
+ st_binary_op_res2 | unreached
+ st_binary_op_res  | unreached
+ st_idle           | unreached
+-------------------------------
+Analyzing FSM <FSM_2> for best encoding.
+Optimizing FSM <u_Core/atari800core/cpu6502/cpu_6502_peter/theCpuCycle/FSM> on signal <theCpuCycle[1:19]> with one-hot encoding.
+-----------------------------------------
+ State            | Encoding
+-----------------------------------------
+ opcodefetch      | 0000000000000000001
+ cycle2           | 0000000000000000010
+ cycle3           | 0000000000001000000
+ cyclepreindirect | 0000000000010000000
+ cycleindirect    | 0000000000100000000
+ cyclebranchtaken | 0000000000000000100
+ cyclebranchpage  | 0000100000000000000
+ cyclepreread     | 0000000010000000000
+ cycleread        | 0000010000000000000
+ cycleread2       | 0000000100000000000
+ cyclermw         | 0001000000000000000
+ cycleprewrite    | 0000000001000000000
+ cyclewrite       | 0000000000000100000
+ cyclestack1      | 0000000000000001000
+ cyclestack2      | 0000000000000010000
+ cyclestack3      | 0010000000000000000
+ cyclestack4      | 0100000000000000000
+ cyclejump        | 0000001000000000000
+ cycleend         | 1000000000000000000
+-----------------------------------------
+Analyzing FSM <FSM_1> for best encoding.
+Optimizing FSM <u_Core/atari800core/mmu1/state_reg/FSM> on signal <state_reg[1:2]> with sequential encoding.
+-------------------
+ State | Encoding
+-------------------
+ 00    | 00
+ 01    | 11
+ 10    | 10
+ 11    | 01
+-------------------
+Analyzing FSM <FSM_0> for best encoding.
+Optimizing FSM <u_Core/u_Kbd/key_state/FSM> on signal <key_state[1:13]> with one-hot encoding.
+-----------------------------
+ State      | Encoding
+-----------------------------
+ normal     | 0000000000001
+ extended   | 0000000000100
+ pending    | 0000000001000
+ translate1 | 0010000000000
+ translate2 | 0100000000000
+ done       | 1000000000000
+ pause0     | 0000000000010
+ pause1     | 0000000010000
+ pause2     | 0000000100000
+ pause3     | 0000001000000
+ pause4     | 0000010000000
+ pause5     | 0000100000000
+ pause6     | 0001000000000
+-----------------------------
+WARNING:Xst:2404 -  FFs/Latches <dbg_o.pc<31:24>> (without init value) have a constant value of 0 in block <ZPUMediumCore>.
+WARNING:Xst:2404 -  FFs/Latches <penv_reg<7:0>> (without init value) have a constant value of 0 in block <antic>.
+WARNING:Xst:2404 -  FFs/Latches <penh_reg<7:0>> (without init value) have a constant value of 0 in block <antic>.
+WARNING:Xst:2404 -  FFs/Latches <spi_fch_tx<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
+WARNING:Xst:2404 -  FFs/Latches <spi_stat_gen_6<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
+WARNING:Xst:2404 -  FFs/Latches <spi_tx_status<7:1>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
+WARNING:Xst:2404 -  FFs/Latches <spi_tx_cfg_fileio<7:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
+WARNING:Xst:2404 -  FFs/Latches <spi_tx_cfg_status<15:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
+WARNING:Xst:2404 -  FFs/Latches <spi_ctrl.cfg_fileio<7:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
+WARNING:Xst:2404 -  FFs/Latches <spi_stat_gen_5<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
+WARNING:Xst:2404 -  FFs/Latches <o_cfg_fileio<7:0>> (without init value) have a constant value of 0 in block <Replay_Syscon>.
+WARNING:Xst:2404 -  FFs/Latches <spi_stat_gen_4<7:0>> (without init value) have a constant value of 0 in block <Replay_FileIO>.
+
+Synthesizing (advanced) Unit <Replay_DDRCtrl_Top>.
+INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_lp_w_be_mux0001> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
+Unit <Replay_DDRCtrl_Top> synthesized (advanced).
+
+Synthesizing (advanced) Unit <Replay_TranslatePS2>.
+INFO:Xst:3230 - The RAM description <Mram_keylut> will not be implemented on the device block RAM because of limited available resources. If you would like this RAM to be implemented in block RAM, please select a larger device or increase the value specified by the BRAM_Utilization_Ratio constraint.
+    -----------------------------------------------------------------------
+    | ram_type           | Distributed                         |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 512-word x 8-bit                    |          |
+    |     clkA           | connected to signal <i_clk_sys>     | rise     |
+    |     weA            | connected to signal <i_conf_wr>     | high     |
+    |     addrA          | connected to signal <i_conf_adr>    |          |
+    |     diA            | connected to signal <i_conf_dat>    |          |
+    -----------------------------------------------------------------------
+    | Port B                                                              |
+    |     aspect ratio   | 512-word x 8-bit                    |          |
+    |     addrB          | connected to signal <key_opt>       |          |
+    |     doB            | connected to internal node          |          |
+    -----------------------------------------------------------------------
+Unit <Replay_TranslatePS2> synthesized (advanced).
+
+Synthesizing (advanced) Unit <Replay_VideoConverter>.
+INFO:Xst:3230 - The RAM description <Mram_dupo_buf_s> will not be implemented on the device block RAM because of limited available resources. If you would like this RAM to be implemented in block RAM, please select a larger device or increase the value specified by the BRAM_Utilization_Ratio constraint.
+    -----------------------------------------------------------------------
+    | ram_type           | Distributed                         |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 2048-word x 24-bit                  |          |
+    |     clkA           | connected to signal <i_clk_sys>     | rise     |
+    |     weA            | connected to signal <bufin_wr_en_s> | high     |
+    |     addrA          | connected to signal <vidin_hcnt_s>  |          |
+    |     diA            | connected to signal <i_vid_b>       |          |
+    -----------------------------------------------------------------------
+    | Port B                                                              |
+    |     aspect ratio   | 2048-word x 24-bit                  |          |
+    |     addrB          | connected to signal <vidout_hpix_s> |          |
+    |     doB            | connected to internal node          |          |
+    -----------------------------------------------------------------------
+Unit <Replay_VideoConverter> synthesized (advanced).
+
+Synthesizing (advanced) Unit <ZPUMediumCore>.
+	Found pipelined multiplier on signal <mult_res_mult0000>:
+		- 1 pipeline level(s) found in a register connected to the multiplier macro output.
+		Pushing register(s) into the multiplier macro.
+
+		- 1 pipeline level(s) found in a register on signal <b_r>.
+		Pushing register(s) into the multiplier macro.
+INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_tdecoded_mux0111> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
+INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_tdecoded_mux0112> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
+INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_tdecoded_mux0113> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
+INFO:Xst:3034 - In order to maximize performance and save block RAM resources, the small ROM <Mrom_insn_mux0002> will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.
+INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_mult_res_mult0000 by adding 2 register level(s).
+Unit <ZPUMediumCore> synthesized (advanced).
+
+Synthesizing (advanced) Unit <basic>.
+INFO:Xst:3044 - The ROM <Mrom_rdata> will be implemented as a read-only BLOCK RAM, absorbing the register: <q>.
+INFO:Xst:3225 - The RAM <Mrom_rdata> will be implemented as BLOCK RAM
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 8192-word x 8-bit                   |          |
+    |     mode           | write-first                         |          |
+    |     clkA           | connected to signal <clock>         | rise     |
+    |     weA            | connected to internal node          | high     |
+    |     addrA          | connected to signal <address>       |          |
+    |     diA            | connected to internal node          |          |
+    |     doA            | connected to signal <q>             |          |
+    -----------------------------------------------------------------------
+    | optimization       | area                                |          |
+    -----------------------------------------------------------------------
+Unit <basic> synthesized (advanced).
+
+Synthesizing (advanced) Unit <cpu_65xx>.
+INFO:Xst:3044 - The ROM <Mrom_nextOpcInfo_rom0000> will be implemented as a read-only BLOCK RAM, absorbing the register: <opcInfo>.
+INFO:Xst:3225 - The RAM <Mrom_nextOpcInfo_rom0000> will be implemented as BLOCK RAM
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 256-word x 44-bit                   |          |
+    |     mode           | write-first                         |          |
+    |     clkA           | connected to signal <clk>           | rise     |
+    |     enA            | connected to signal <opcInfo_not0001> | high     |
+    |     weA            | connected to signal <GND>           | high     |
+    |     addrA          | connected to signal <nextOpcode>    |          |
+    |     diA            | connected to signal <GND>           |          |
+    |     doA            | connected to signal <opcInfo>       |          |
+    -----------------------------------------------------------------------
+    | optimization       | area                                |          |
+    -----------------------------------------------------------------------
+Unit <cpu_65xx> synthesized (advanced).
+
+Synthesizing (advanced) Unit <generic_ram_infer_1>.
+INFO:Xst:3230 - The RAM description <Mram_ram_block> will not be implemented on the device block RAM because of limited available resources. If you would like this RAM to be implemented in block RAM, please select a larger device or increase the value specified by the BRAM_Utilization_Ratio constraint.
+    -----------------------------------------------------------------------
+    | ram_type           | Distributed                         |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 1024-word x 8-bit                   |          |
+    |     clkA           | connected to signal <clock>         | rise     |
+    |     weA            | connected to signal <we>            | high     |
+    |     addrA          | connected to signal <address>       |          |
+    |     diA            | connected to signal <data>          |          |
+    |     doA            | connected to internal node          |          |
+    -----------------------------------------------------------------------
+Unit <generic_ram_infer_1> synthesized (advanced).
+
+Synthesizing (advanced) Unit <generic_ram_infer_2>.
+INFO:Xst:3226 - The RAM <Mram_ram_block> will be implemented as a BLOCK RAM, absorbing the following register(s): <q>
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 16384-word x 8-bit                  |          |
+    |     mode           | read-first                          |          |
+    |     clkA           | connected to signal <clock>         | rise     |
+    |     weA            | connected to signal <we>            | high     |
+    |     addrA          | connected to signal <address>       |          |
+    |     diA            | connected to signal <data>          |          |
+    |     doA            | connected to signal <q>             |          |
+    -----------------------------------------------------------------------
+    | optimization       | area                                |          |
+    -----------------------------------------------------------------------
+Unit <generic_ram_infer_2> synthesized (advanced).
+
+Synthesizing (advanced) Unit <os16>.
+INFO:Xst:3044 - The ROM <Mrom_rdata> will be implemented as a read-only BLOCK RAM, absorbing the register: <q>.
+INFO:Xst:3225 - The RAM <Mrom_rdata> will be implemented as BLOCK RAM
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 16384-word x 8-bit                  |          |
+    |     mode           | write-first                         |          |
+    |     clkA           | connected to signal <clock>         | rise     |
+    |     weA            | connected to internal node          | high     |
+    |     addrA          | connected to signal <address>       |          |
+    |     diA            | connected to internal node          |          |
+    |     doA            | connected to signal <q>             |          |
+    -----------------------------------------------------------------------
+    | optimization       | area                                |          |
+    -----------------------------------------------------------------------
+Unit <os16> synthesized (advanced).
+
+Synthesizing (advanced) Unit <zpu_rom>.
+INFO:Xst:3044 - The ROM <Mrom_rdata> will be implemented as a read-only BLOCK RAM, absorbing the register: <q>.
+INFO:Xst:3225 - The RAM <Mrom_rdata> will be implemented as BLOCK RAM
+    -----------------------------------------------------------------------
+    | ram_type           | Block                               |          |
+    -----------------------------------------------------------------------
+    | Port A                                                              |
+    |     aspect ratio   | 4096-word x 32-bit                  |          |
+    |     mode           | write-first                         |          |
+    |     clkA           | connected to signal <clock>         | rise     |
+    |     weA            | connected to internal node          | high     |
+    |     addrA          | connected to signal <address>       |          |
+    |     diA            | connected to internal node          |          |
+    |     doA            | connected to signal <q>             |          |
+    -----------------------------------------------------------------------
+    | optimization       | area                                |          |
+    -----------------------------------------------------------------------
+Unit <zpu_rom> synthesized (advanced).
+WARNING:Xst:2677 - Node <rpipe_1> of sequential type is unconnected in block <Replay_DDRCtrl_Datapath>.
+WARNING:Xst:2677 - Node <rpipe_2> of sequential type is unconnected in block <Replay_DDRCtrl_Datapath>.
+WARNING:Xst:2677 - Node <wpipe_2> of sequential type is unconnected in block <Replay_DDRCtrl_Datapath>.
+WARNING:Xst:2677 - Node <an_prev2_reg_2> of sequential type is unconnected in block <gtia>.
+WARNING:Xst:2677 - Node <displayed_character_reg_0> of sequential type is unconnected in block <antic>.
+WARNING:Xst:2677 - Node <displayed_character_reg_1> of sequential type is unconnected in block <antic>.
+WARNING:Xst:2677 - Node <displayed_character_reg_2> of sequential type is unconnected in block <antic>.
+WARNING:Xst:2677 - Node <displayed_character_reg_3> of sequential type is unconnected in block <antic>.
+WARNING:Xst:2677 - Node <displayed_character_reg_4> of sequential type is unconnected in block <antic>.
+WARNING:Xst:2677 - Node <cur_addr_11> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_12> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_13> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_14> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_15> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_16> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_17> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_18> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_19> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_20> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_21> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_22> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_addr_23> of sequential type is unconnected in block <Replay_DDRCtrl>.
+WARNING:Xst:2677 - Node <pix_active_t_3> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_0> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_1> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_2> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_3> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_4> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_5> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <char_vid_dout_t1_6> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_0> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_1> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_2> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_3> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_4> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_5> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_6> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_7> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_8> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_9> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_10> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_11> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <font_addr_t1_12> of sequential type is unconnected in block <Replay_OSD>.
+WARNING:Xst:2677 - Node <spi_cmd_low_5> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_6> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_7> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_8> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_9> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_10> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_11> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_12> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_13> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_14> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_15> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_0> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_1> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_3> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_9> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_12> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_13> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_14> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_15> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_byte_sel_5> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_byte_sel_6> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <spi_byte_sel_7> of sequential type is unconnected in block <Replay_FileIO>.
+WARNING:Xst:2677 - Node <serin_shift_reg_0> of sequential type is unconnected in block <pokey>.
+WARNING:Xst:2677 - Node <serin_shift_reg_1> of sequential type is unconnected in block <pokey>.
+WARNING:Xst:2677 - Node <serout_shift_reg_0> of sequential type is unconnected in block <pokey>.
+WARNING:Xst:2677 - Node <spi_cmd_low_2> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_4> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_5> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_6> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_7> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_9> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_10> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_11> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_12> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_13> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_14> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_low_15> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_1> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_3> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_4> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_6> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_7> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_8> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_9> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_10> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_11> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_13> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_14> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_cmd_high_15> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <h_size_0> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_byte_sel_5> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_byte_sel_6> of sequential type is unconnected in block <Replay_Syscon>.
+WARNING:Xst:2677 - Node <spi_byte_sel_7> of sequential type is unconnected in block <Replay_Syscon>.
+
+=========================================================================
+Advanced HDL Synthesis Report
+
+Macro Statistics
+# FSMs                                                 : 9
+# RAMs                                                 : 11
+ 1024x8-bit single-port distributed RAM                : 4
+ 16384x8-bit single-port block RAM                     : 2
+ 2048x24-bit dual-port distributed RAM                 : 1
+ 256x44-bit single-port block RAM                      : 1
+ 4096x32-bit single-port block RAM                     : 1
+ 512x8-bit dual-port distributed RAM                   : 1
+ 8192x8-bit single-port block RAM                      : 1
+# ROMs                                                 : 20
+ 16x15-bit ROM                                         : 1
+ 16x7-bit ROM                                          : 1
+ 256x24-bit ROM                                        : 1
+ 32x6-bit ROM                                          : 4
+ 4x1-bit ROM                                           : 1
+ 4x12-bit ROM                                          : 1
+ 4x4-bit ROM                                           : 1
+ 4x8-bit ROM                                           : 1
+ 64x16-bit ROM                                         : 2
+ 8x1-bit ROM                                           : 3
+ 8x8-bit ROM                                           : 4
+# Multipliers                                          : 2
+ 14x14-bit multiplier                                  : 1
+ 32x32-bit registered multiplier                       : 1
+# Adders/Subtractors                                   : 104
+ 10-bit adder                                          : 3
+ 10-bit subtractor                                     : 1
+ 11-bit adder                                          : 1
+ 12-bit adder                                          : 1
+ 12-bit subtractor                                     : 3
+ 14-bit adder                                          : 10
+ 14-bit adder carry out                                : 1
+ 14-bit subtractor                                     : 6
+ 14-bit subtractor borrow in                           : 1
+ 16-bit adder                                          : 7
+ 19-bit subtractor                                     : 1
+ 22-bit adder                                          : 3
+ 22-bit adder carry in                                 : 1
+ 22-bit subtractor                                     : 1
+ 24-bit adder                                          : 2
+ 28-bit adder                                          : 1
+ 28-bit subtractor                                     : 1
+ 3-bit adder                                           : 1
+ 32-bit adder                                          : 3
+ 32-bit subtractor                                     : 2
+ 4-bit adder                                           : 5
+ 4-bit subtractor                                      : 8
+ 5-bit adder                                           : 10
+ 6-bit adder                                           : 5
+ 6-bit subtractor                                      : 1
+ 7-bit adder                                           : 3
+ 8-bit adder                                           : 3
+ 8-bit addsub                                          : 1
+ 8-bit subtractor                                      : 14
+ 9-bit adder                                           : 3
+ 9-bit adder carry in                                  : 1
+# Counters                                             : 37
+ 11-bit up counter                                     : 2
+ 12-bit down counter                                   : 1
+ 12-bit up counter                                     : 2
+ 14-bit up counter                                     : 2
+ 16-bit up counter                                     : 1
+ 2-bit up counter                                      : 1
+ 24-bit up counter                                     : 1
+ 3-bit up counter                                      : 2
+ 4-bit up counter                                      : 9
+ 5-bit up counter                                      : 3
+ 6-bit up counter                                      : 3
+ 8-bit down counter                                    : 2
+ 8-bit up counter                                      : 6
+ 9-bit up counter                                      : 2
+# Accumulators                                         : 4
+ 12-bit up accumulator                                 : 1
+ 4-bit up accumulator                                  : 2
+ 8-bit up accumulator                                  : 1
+# Registers                                            : 6488
+ Flip-Flops                                            : 6488
+# Comparators                                          : 68
+ 12-bit comparator equal                               : 2
+ 14-bit comparator equal                               : 17
+ 14-bit comparator lessequal                           : 2
+ 14-bit comparator not equal                           : 9
+ 24-bit comparator less                                : 1
+ 32-bit comparator equal                               : 1
+ 32-bit comparator greater                             : 2
+ 32-bit comparator less                                : 2
+ 32-bit comparator lessequal                           : 2
+ 4-bit comparator equal                                : 2
+ 4-bit comparator greatequal                           : 2
+ 4-bit comparator greater                              : 1
+ 4-bit comparator less                                 : 2
+ 5-bit comparator greater                              : 4
+ 6-bit comparator equal                                : 4
+ 8-bit comparator equal                                : 12
+ 8-bit comparator greater                              : 1
+ 8-bit comparator not equal                            : 2
+# Multiplexers                                         : 62
+ 1-bit 16-to-1 multiplexer                             : 6
+ 1-bit 4-to-1 multiplexer                              : 11
+ 1-bit 8-to-1 multiplexer                              : 16
+ 2-bit 4-to-1 multiplexer                              : 4
+ 24-bit 4-to-1 multiplexer                             : 2
+ 24-bit 8-to-1 multiplexer                             : 1
+ 32-bit 4-to-1 multiplexer                             : 1
+ 4-bit 16-to-1 multiplexer                             : 1
+ 5-bit 16-to-1 multiplexer                             : 1
+ 6-bit 4-to-1 multiplexer                              : 1
+ 8-bit 4-to-1 multiplexer                              : 18
+# Decoders                                             : 1
+ 1-of-16 decoder                                       : 1
+# Xors                                                 : 24
+ 1-bit xor2                                            : 21
+ 3-bit xor2                                            : 2
+ 8-bit xor2                                            : 1
+
+=========================================================================
+
+=========================================================================
+*                         Low Level Synthesis                           *
+=========================================================================
+WARNING:Xst:1293 - FF/Latch <halt_dly> has a constant value of 0 in block <cpu_65xx>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <p0pl_reg_0> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p1pl_reg_1> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p2pl_reg_2> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <p3pl_reg_3> (without init value) has a constant value of 0 in block <gtia>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <nmist_reg_5> (without init value) has a constant value of 0 in block <antic>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <spi_stat_gen_3_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_3_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_2_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen_1_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_7> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_6> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_5> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_4> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_3> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_2> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_1> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <spi_stat_gen<0>_0> (without init value) has a constant value of 0 in block <Replay_FileIO>. This FF/Latch will be trimmed during the optimization process.
+INFO:Xst:2261 - The FF/Latch <wpipe_1> in Unit <Replay_DDRCtrl_Datapath> is equivalent to the following FF/Latch, which will be removed : <dqs_enable> 
+INFO:Xst:2261 - The FF/Latch <ana_vs> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <dig_vs> 
+INFO:Xst:2261 - The FF/Latch <ana_hs> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <dig_hs> 
+INFO:Xst:2261 - The FF/Latch <active_bk_valid_reg_0> in Unit <gtia> is equivalent to the following 3 FFs/Latches, which will be removed : <active_bk_valid_reg_1> <active_bk_valid_reg_2> <active_bk_valid_reg_3> 
+INFO:Xst:2261 - The FF/Latch <active_bk_valid_reg_4> in Unit <gtia> is equivalent to the following 3 FFs/Latches, which will be removed : <active_bk_valid_reg_5> <active_bk_valid_reg_6> <active_bk_valid_reg_7> 
+INFO:Xst:2261 - The FF/Latch <o_vbl> in Unit <Replay_Syscon> is equivalent to the following FF/Latch, which will be removed : <vs_t_0> 
+INFO:Xst:2261 - The FF/Latch <osd_hexp> in Unit <Replay_Syscon> is equivalent to the following FF/Latch, which will be removed : <h_size_10> 
+INFO:Xst:2261 - The FF/Latch <hs_t_0> in Unit <Replay_Syscon> is equivalent to the following FF/Latch, which will be removed : <o_vid_sync.dig_hs> 
+WARNING:Xst:1710 - FF/Latch <volume_reg_15> (without init value) has a constant value of 0 in block <pokey_mixer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:2677 - Node <Mmult_mult_res_mult0000_submult_11> of sequential type is unconnected in block <ZPUMediumCore>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_2> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_3> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_4> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_5> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_6> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_7> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_8> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_9> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_10> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_11> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_12> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_vcnt_s_13> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_hcnt_s_9> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_hcnt_s_10> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_hcnt_s_11> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_hcnt_s_12> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <vidin_hcnt_s_13> of sequential type is unconnected in block <Replay_VideoConverter>.
+WARNING:Xst:2677 - Node <instruction_type_reg_4> of sequential type is unconnected in block <antic>.
+WARNING:Xst:2677 - Node <dma_speed_reg_0> of sequential type is unconnected in block <antic>.
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_0> in Unit <Replay_VideoTiming> is equivalent to the following 2 FFs/Latches, which will be removed : <param_c.h_stop_eq2_0> <param_c.h_stop_bd2_0> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_act_0> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_start_ana_0> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_1> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_1> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_2> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_2> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_3> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_3> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_2nd_4> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd2_4> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_0> in Unit <Replay_VideoTiming> is equivalent to the following 2 FFs/Latches, which will be removed : <param_c.h_stop_eq1_0> <param_c.h_stop_bd1_0> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_1> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_1> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_2> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_2> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_3> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_3> 
+INFO:Xst:2261 - The FF/Latch <param_c.h_start_sync_4> in Unit <Replay_VideoTiming> is equivalent to the following FF/Latch, which will be removed : <param_c.h_stop_bd1_4> 
+WARNING:Xst:2039 - Unit Replay_Top: 1 multi-source signal is replaced by logic (pull-up yes): b_FPGA_SPI_MISO_MLTSRCEDGE.
+WARNING:Xst:2041 - Unit pokey: 1 internal tristate is replaced by logic (pull-up yes): SIO_CLOCK.
+
+Optimizing unit <Replay_Top> ...
+
+Optimizing unit <complete_address_decoder_1> ...
+
+Optimizing unit <irq_glue> ...
+
+Optimizing unit <complete_address_decoder_2> ...
+
+Optimizing unit <complete_address_decoder_5> ...
+
+Optimizing unit <pokey_noise_filter> ...
+
+Optimizing unit <complete_address_decoder_3> ...
+
+Optimizing unit <complete_address_decoder_4> ...
+
+Optimizing unit <Replay_Audio> ...
+
+Optimizing unit <Replay_ResetGen> ...
+
+Optimizing unit <Replay_TranslatePS2> ...
+
+Optimizing unit <pokey_mixer> ...
+
+Optimizing unit <address_decoder> ...
+
+Optimizing unit <zpu_rom> ...
+
+Optimizing unit <generic_ram_infer_1> ...
+
+Optimizing unit <gtia_palette> ...
+
+Optimizing unit <cpu_65xx> ...
+
+Optimizing unit <antic_counter_1> ...
+
+Optimizing unit <antic_counter_2> ...
+
+Optimizing unit <simple_counter_1> ...
+
+Optimizing unit <simple_counter_2> ...
+
+Optimizing unit <wide_delay_line_1> ...
+
+Optimizing unit <antic_dma_clock> ...
+
+Optimizing unit <wide_delay_line_2> ...
+
+Optimizing unit <wide_delay_line_3> ...
+
+Optimizing unit <delay_line_1> ...
+
+Optimizing unit <ZPUMediumCore> ...
+
+Optimizing unit <delay_line_2> ...
+
+Optimizing unit <syncreset_enable_divider_1> ...
+
+Optimizing unit <syncreset_enable_divider_2> ...
+
+Optimizing unit <delay_line_3> ...
+
+Optimizing unit <synchronizer> ...
+
+Optimizing unit <pokey_keyboard_scanner> ...
+
+Optimizing unit <enable_divider_1> ...
+
+Optimizing unit <enable_divider_2> ...
+
+Optimizing unit <delay_line_4> ...
+
+Optimizing unit <delay_line_5> ...
+
+Optimizing unit <gtia_player> ...
+
+Optimizing unit <gtia_priority> ...
+
+Optimizing unit <wide_delay_line_4> ...
+
+Optimizing unit <wide_delay_line_5> ...
+
+Optimizing unit <wide_delay_line_6> ...
+
+Optimizing unit <wide_delay_line_7> ...
+
+Optimizing unit <wide_delay_line_8> ...
+
+Optimizing unit <wide_delay_line_9> ...
+
+Optimizing unit <basic> ...
+
+Optimizing unit <os16> ...
+
+Optimizing unit <generic_ram_infer_2> ...
+
+Optimizing unit <pia> ...
+
+Optimizing unit <reg_file_1> ...
+
+Optimizing unit <reg_file_2> ...
+
+Optimizing unit <covox> ...
+
+Optimizing unit <reg_file_3> ...
+
+Optimizing unit <ps2_rom> ...
+
+Optimizing unit <kcpsm3> ...
+
+Optimizing unit <Replay_DDRCtrl_Datapath> ...
+
+Optimizing unit <FIFO_SyncSRL_D16> ...
+
+Optimizing unit <FONT0> ...
+
+Optimizing unit <FONT1> ...
+
+Optimizing unit <FONT2> ...
+
+Optimizing unit <FIFO_SyncBlock_D2048_W8> ...
+
+Optimizing unit <poly_17_9> ...
+
+Optimizing unit <poly_5> ...
+
+Optimizing unit <poly_4> ...
+
+Optimizing unit <Replay_VideoTiming> ...
+
+Optimizing unit <Replay_SPI8> ...
+
+Optimizing unit <Replay_I2C> ...
+
+Optimizing unit <Replay_ClockGen> ...
+
+Optimizing unit <cpu> ...
+
+Optimizing unit <zpu_glue> ...
+
+Optimizing unit <shared_enable> ...
+
+Optimizing unit <gtia> ...
+
+Optimizing unit <internalromram> ...
+
+Optimizing unit <pokey_countdown_timer> ...
+
+Optimizing unit <antic> ...
+
+Optimizing unit <Replay_JoyPS2_Core_1> ...
+
+Optimizing unit <Replay_JoyPS2_Core_2> ...
+
+Optimizing unit <Replay_DDRCtrl> ...
+
+Optimizing unit <Replay_OSD> ...
+
+Optimizing unit <Replay_Video> ...
+
+Optimizing unit <Replay_VideoConverter> ...
+
+Optimizing unit <Replay_FileIO> ...
+
+Optimizing unit <pokey> ...
+
+Optimizing unit <Replay_JoyPS2> ...
+
+Optimizing unit <Replay_DDRCtrl_Top> ...
+
+Optimizing unit <Replay_Syscon> ...
+
+Optimizing unit <zpu_config_regs> ...
+
+Optimizing unit <atari800core> ...
+
+Optimizing unit <Core_Top> ...
+WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile2>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile3>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <trig2_reg> (without init value) has a constant value of 0 in block <gtia1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <trig3_reg> (without init value) has a constant value of 0 in block <gtia1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq2_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_sync_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_ana_3> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_ana_2> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_ana_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_10> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_9> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <state_reg_FSM_FFd2> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <state_reg_FSM_FFd1> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <compare_latch_reg_5> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <compare_latch_reg_4> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <compare_latch_reg_3> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <compare_latch_reg_2> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <compare_latch_reg_1> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <compare_latch_reg_0> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <break_pressed_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <control_pressed_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <irq_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <key_held_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_pressed_reg> (without init value) has a constant value of 0 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in1_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <ff_reg_2> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_2> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_1> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_0> (without init value) has a constant value of 0 in block <missile0>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_5> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_4> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shift_reg_3> (without init value) has a constant value of 0 in block <missile1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_10> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_9> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_8> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_7> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_6> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_5> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_3> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_2> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_act_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_9> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_4> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_3> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_2> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_len_0> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <hp_addr_25> (without init value) has a constant value of 0 in block <u_DDRCtrl>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <hp_addr_24> (without init value) has a constant value of 0 in block <u_DDRCtrl>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <hp_addr_23> (without init value) has a constant value of 0 in block <u_DDRCtrl>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <cpu_in_port_6> (without init value) has a constant value of 0 in block <u_PSB>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <cpu_in_port_6> (without init value) has a constant value of 0 in block <u_PSA>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <shifter_0> (without init value) has a constant value of 0 in block <u_Audio>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_5> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_6> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_7> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_8> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_9> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_10> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_eq1_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_2nd_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_2nd_1> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_5> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_6> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_7> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_bd1_8> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_start_sync_13> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_0> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_1> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_2> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_3> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_4> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_9> (without init value) has a constant value of 1 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_11> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1710 - FF/Latch <param_c.h_stop_ana_12> (without init value) has a constant value of 0 in block <u_VideoTiming>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_5> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_4> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_3> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_1> (without init value) has a constant value of 1 in block <sio_in1_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_0> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_1> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <keycode_latch_reg_2> (without init value) has a constant value of 1 in block <pokey_keyboard_scanner1>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in1_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in2_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <ff_reg_0> (without init value) has a constant value of 1 in block <sio_in3_synchronizer>. This FF/Latch will be trimmed during the optimization process.
+WARNING:Xst:2677 - Node <writeprotn_s> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <ena_sub4> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_2> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_0> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_1> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_3> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_4> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_5> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_6> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_7> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_8> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_9> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_10> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_11> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_12> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_13> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_14> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <diskid_s_15> of sequential type is unconnected in block <Replay_Top>.
+WARNING:Xst:2677 - Node <o_sample_taken> of sequential type is unconnected in block <u_Audio>.
+WARNING:Xst:2677 - Node <ps_eq> of sequential type is unconnected in block <u_ClockGen>.
+WARNING:Xst:2677 - Node <ps_eq_meta> of sequential type is unconnected in block <u_ClockGen>.
+WARNING:Xst:2677 - Node <o_rst_ram_capture> of sequential type is unconnected in block <u_ClockGen>.
+WARNING:Xst:2677 - Node <write_ena> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_0> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_1> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_2> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_3> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_4> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_5> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_6> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <write_data_7> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_0> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_1> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_2> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_3> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_4> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_5> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <devid_6> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_0> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_1> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_2> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_3> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_4> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_5> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_6> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <rab_7> of sequential type is unconnected in block <u_I2C>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_we> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.cmd_ack> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.cmd_done> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_taken> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.cmd_done> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_low_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_we> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cs_meta_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cs_meta_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cs_meta_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cs_meta_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.cmd_err> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.cmd_ack> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_we> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.cmd_err> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_taken> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_4> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_5> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_6> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_cmd_high_7> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.update> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_done> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.writable_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.writable_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_4> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_5> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_6> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.status_7> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_4> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_5> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_6> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.data_7> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_4> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_5> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_6> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_hch_to_core.data_7> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.inserted_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.inserted_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.inserted_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.inserted_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.writable_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.writable_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.pos_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.pos_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.pos_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_fch_to_core.pos_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_pos_cnt_0> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_pos_cnt_1> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_pos_cnt_2> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <spi_pos_cnt_3> of sequential type is unconnected in block <u_FileIO>.
+WARNING:Xst:2677 - Node <o_rxbytesel_5> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytesel_6> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytesel_7> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_0> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_1> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_2> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_3> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_0> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_1> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_2> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_3> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_0> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_1> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_2> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_3> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_7> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_6> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_5> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <joy_b_reg_0> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_b_reg_1> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_b_reg_2> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_b_reg_3> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_b_reg_4> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_b_reg_5> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_0> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_1> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_2> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_3> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_4> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_5> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_6> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_7> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_8> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_9> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_0> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_1> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_2> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_3> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_4> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_butn_0> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_butn_1> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_butn_2> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_10> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_5> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_11> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_6> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_7> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_8> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posx_9> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_10> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_a_reg_0> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_a_reg_1> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_a_reg_2> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_a_reg_3> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_a_reg_4> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <joy_a_reg_5> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_posy_11> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <o_ms_we> of sequential type is unconnected in block <u_JoyPS2>.
+WARNING:Xst:2677 - Node <status_0> of sequential type is unconnected in block <u_PSA>.
+WARNING:Xst:2677 - Node <status_1> of sequential type is unconnected in block <u_PSA>.
+WARNING:Xst:2677 - Node <status_0> of sequential type is unconnected in block <u_PSB>.
+WARNING:Xst:2677 - Node <status_1> of sequential type is unconnected in block <u_PSB>.
+WARNING:Xst:2677 - Node <r_we_hp> of sequential type is unconnected in block <u_DDRCtrl>.
+WARNING:Xst:2677 - Node <cur_hp> of sequential type is unconnected in block <u_DDRCtrl>.
+WARNING:Xst:2677 - Node <o_cfg_ready> of sequential type is unconnected in block <u_DDRCtrl>.
+WARNING:Xst:2677 - Node <sys_cur_hp> of sequential type is unconnected in block <u_DDRCtrl>.
+WARNING:Xst:2677 - Node <spi_rx_sof_meta_1> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_rx_sof_meta_2> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_byte_sel_4> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_24> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_19> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_30> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_25> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_31> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_26> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_27> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_28> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_29> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_10> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_11> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_12> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_13> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_14> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_9> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_20> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_15> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_21> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_22> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_23> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_24> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_19> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_0> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_30> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_10> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_25> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_1> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_11> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_31> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_26> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_2> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_27> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_12> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_3> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_28> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_13> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_10> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_4> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_dynamic_29> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_14> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_11> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_5> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_ctrl_15> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_12> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_6> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_13> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_7> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_8> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_14> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_20> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_9> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_15> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_21> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_16> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_22> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_17> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_23> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <spi_ctrl.cfg_static_18> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_0> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_1> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_2> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_3> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_4> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_5> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_6> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_7> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_8> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_9> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_10> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_11> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_12> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_13> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_14> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_15> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_16> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_17> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_18> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_19> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_20> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_21> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_22> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_23> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_24> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_25> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_26> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_27> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_28> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_29> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_30> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_cfg_static_31> of sequential type is unconnected in block <u_Syscon>.
+WARNING:Xst:2677 - Node <o_sof> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytesel_4> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytesel_5> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytesel_6> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytesel_7> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_0> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_1> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_2> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxbytecnt_3> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_4> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_5> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_6> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <o_rxcmd_7> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_0> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_1> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_2> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_cnt_3> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_7> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_6> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_5> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <byte_4> of sequential type is unconnected in block <u_spi>.
+WARNING:Xst:2677 - Node <matrix_0_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_0_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_1_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_2_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_3_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_4_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_7_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_5_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_8> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_9> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_10> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_11> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_12> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_13> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_14> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <matrix_6_15> of sequential type is unconnected in block <u_Kbd>.
+WARNING:Xst:2677 - Node <dig_sof> of sequential type is unconnected in block <u_VideoTiming>.
+WARNING:Xst:2677 - Node <dig_sol> of sequential type is unconnected in block <u_VideoTiming>.
+WARNING:Xst:2677 - Node <dig_ha> of sequential type is unconnected in block <u_VideoTiming>.
+WARNING:Xst:2677 - Node <dig_va> of sequential type is unconnected in block <u_VideoTiming>.
+WARNING:Xst:2677 - Node <width_16bit_reg> of sequential type is unconnected in block <mmu1>.
+WARNING:Xst:2677 - Node <theOpcode_0> of sequential type is unconnected in block <cpu_6502_peter>.
+WARNING:Xst:2677 - Node <theOpcode_1> of sequential type is unconnected in block <cpu_6502_peter>.
+WARNING:Xst:2677 - Node <theOpcode_2> of sequential type is unconnected in block <cpu_6502_peter>.
+WARNING:Xst:2677 - Node <theOpcode_3> of sequential type is unconnected in block <cpu_6502_peter>.
+WARNING:Xst:2677 - Node <theOpcode_4> of sequential type is unconnected in block <cpu_6502_peter>.
+WARNING:Xst:2677 - Node <ZPU_16BIT_WRITE_ENABLE_reg> of sequential type is unconnected in block <zpu_glue1>.
+WARNING:Xst:2677 - Node <dbg_o.b_inst> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <break_o> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <not_lshr> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <opcode_r_0_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <opcode_r_1_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <opcode_r_2_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <opcode_r_3_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_2> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_10> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_0> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_1> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_2> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_3> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_4> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_5> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_6> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_8> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_9> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_10> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_11> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_12> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_13> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_14> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_15> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_16> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_17> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_18> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_19> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_20> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_21> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_22> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_23> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_24> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_25> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_26> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_27> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_28> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_29> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_30> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_a_31> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_3> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_0> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_1> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_2> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_3> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_4> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_5> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_6> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_8> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_9> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_10> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_11> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_12> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_13> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_14> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_15> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_16> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_17> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_18> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_19> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_20> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_21> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_22> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_23> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_24> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_25> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_26> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_27> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_28> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_29> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_30> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.stk_b_31> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_11> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_4> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_12> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_5> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_13> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_6> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_14> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_20> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_15> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_8> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_16> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_21> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_9> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_22> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_17> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_23> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_18> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.sp_19> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_0> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_1> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_2> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_3> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_4> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_5> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_6> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_8> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_9> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_10> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_11> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_12> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_13> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_14> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_15> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_16> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_17> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_18> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_19> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_20> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_21> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_22> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.pc_23> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_0> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_1> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_2> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_3> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_4> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_5> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_6> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:2677 - Node <dbg_o.opcode_7> of sequential type is unconnected in block <myzpu>.
+WARNING:Xst:1290 - Hierarchical block <sl_enable_colour_clock_div> is unconnected in block <enables>.
+   It will be removed from the design.
+WARNING:Xst:2677 - Node <value_reg_6> of sequential type is unconnected in block <antic_counter_line_buffer>.
+WARNING:Xst:2677 - Node <value_reg_7> of sequential type is unconnected in block <antic_counter_line_buffer>.
+WARNING:Xst:2677 - Node <twotone_reg> of sequential type is unconnected in block <pokey2>.
+WARNING:Xst:2677 - Node <irq_n_reg> of sequential type is unconnected in block <pokey2>.
+WARNING:Xst:2677 - Node <sio_out_reg> of sequential type is unconnected in block <pokey2>.
+WARNING:Xst:2677 - Node <irqen_reg_3> of sequential type is unconnected in block <pokey2>.
+WARNING:Xst:2677 - Node <skctl_reg_7> of sequential type is unconnected in block <pokey2>.
+WARNING:Xst:2677 - Node <sector_reg_0> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_1> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_2> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_3> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_4> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_5> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_6> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_7> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_8> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_9> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_10> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_11> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_12> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_13> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_14> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_15> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_16> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_17> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_18> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_19> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_20> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_21> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_22> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_23> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_24> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_25> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_26> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_27> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_28> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_29> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_30> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <sector_reg_31> of sequential type is unconnected in block <zpu_config1>.
+WARNING:Xst:2677 - Node <volume_channel_0_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_0_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_0_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_0_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_4> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_5> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_6> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc1_reg_7> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_1_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_1_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_1_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_1_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <highpass0_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_4> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_5> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_6> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc2_reg_7> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_2_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_2_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_2_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_2_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <highpass1_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_4> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_5> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_6> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc3_reg_7> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_3_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_3_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_3_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <volume_channel_3_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <irq_n_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audctl_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audctl_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <irqen_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_0> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_1> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_2> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_3> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_4> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_5> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_6> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <audc0_reg_7> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <chan1_output_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <chan2_output_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <chan0_output_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:2677 - Node <chan3_output_reg> of sequential type is unconnected in block <uart1>.
+WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter3> is unconnected in block <uart1>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter2> is unconnected in block <uart1>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter1> is unconnected in block <uart1>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <pokey_noise_filter0> is unconnected in block <uart1>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <poly_5_lfsr> is unconnected in block <uart1>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <poly_4_lfsr> is unconnected in block <uart1>.
+   It will be removed from the design.
+WARNING:Xst:2677 - Node <result_reg_17> of sequential type is unconnected in block <zpu_glue1>.
+WARNING:Xst:2677 - Node <result_reg_16> of sequential type is unconnected in block <zpu_glue1>.
+WARNING:Xst:2677 - Node <result_reg_15> of sequential type is unconnected in block <zpu_glue1>.
+WARNING:Xst:2677 - Node <result_reg_14> of sequential type is unconnected in block <zpu_glue1>.
+WARNING:Xst:2677 - Node <result_reg_13> of sequential type is unconnected in block <zpu_glue1>.
+WARNING:Xst:1290 - Hierarchical block <sio_in3_synchronizer> is unconnected in block <pokey2>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <sio_in2_synchronizer> is unconnected in block <pokey2>.
+   It will be removed from the design.
+WARNING:Xst:1290 - Hierarchical block <sio_in1_synchronizer> is unconnected in block <pokey2>.
+   It will be removed from the design.
+WARNING:Xst:2677 - Node <bincnt_reg_0> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
+WARNING:Xst:2677 - Node <bincnt_reg_1> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
+WARNING:Xst:2677 - Node <bincnt_reg_2> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
+WARNING:Xst:2677 - Node <bincnt_reg_3> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
+WARNING:Xst:2677 - Node <bincnt_reg_4> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
+WARNING:Xst:2677 - Node <bincnt_reg_5> of sequential type is unconnected in block <pokey_keyboard_scanner1>.
+
+Mapping all equations...
+Building and optimizing final netlist ...
+INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe1_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe1_l> <gen_dq_oe_l_t1[2].fdp_dq_oe1_l> <gen_dq_oe_l_t1[3].fdp_dq_oe1_l> <gen_dq_oe_l_t1[4].fdp_dq_oe1_l> <gen_dq_oe_l_t1[5].fdp_dq_oe1_l> <gen_dq_oe_l_t1[6].fdp_dq_oe1_l> <gen_dq_oe_l_t1[7].fdp_dq_oe1_l> <gen_dq_oe_l_t1[8].fdp_dq_oe1_l> <gen_dq_oe_l_t1[9].fdp_dq_oe1_l> <gen_dq_oe_l_t1[10].fdp_dq_oe1_l> <gen_dq_oe_l_t1[11].fdp_dq_oe1_l> <gen_dq_oe_l_t1[12].fdp_dq_oe1_l> <gen_dq_oe_l_t1[13].fdp_dq_oe1_l> <gen_dq_oe_l_t1[14].fdp_dq_oe1_l> <gen_dq_oe_l_t1[15].fdp_dq_oe1_l> 
+INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe0_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe0_l> <gen_dq_oe_l_t1[2].fdp_dq_oe0_l> <gen_dq_oe_l_t1[3].fdp_dq_oe0_l> <gen_dq_oe_l_t1[4].fdp_dq_oe0_l> <gen_dq_oe_l_t1[5].fdp_dq_oe0_l> <gen_dq_oe_l_t1[6].fdp_dq_oe0_l> <gen_dq_oe_l_t1[7].fdp_dq_oe0_l> <gen_dq_oe_l_t1[8].fdp_dq_oe0_l> <gen_dq_oe_l_t1[9].fdp_dq_oe0_l> <gen_dq_oe_l_t1[10].fdp_dq_oe0_l> <gen_dq_oe_l_t1[11].fdp_dq_oe0_l> <gen_dq_oe_l_t1[12].fdp_dq_oe0_l> <gen_dq_oe_l_t1[13].fdp_dq_oe0_l> <gen_dq_oe_l_t1[14].fdp_dq_oe0_l> <gen_dq_oe_l_t1[15].fdp_dq_oe0_l> 
+INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe1_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe1_l> <gen_dq_oe_l_t1[2].fdp_dq_oe1_l> <gen_dq_oe_l_t1[3].fdp_dq_oe1_l> <gen_dq_oe_l_t1[4].fdp_dq_oe1_l> <gen_dq_oe_l_t1[5].fdp_dq_oe1_l> <gen_dq_oe_l_t1[6].fdp_dq_oe1_l> <gen_dq_oe_l_t1[7].fdp_dq_oe1_l> <gen_dq_oe_l_t1[8].fdp_dq_oe1_l> <gen_dq_oe_l_t1[9].fdp_dq_oe1_l> <gen_dq_oe_l_t1[10].fdp_dq_oe1_l> <gen_dq_oe_l_t1[11].fdp_dq_oe1_l> <gen_dq_oe_l_t1[12].fdp_dq_oe1_l> <gen_dq_oe_l_t1[13].fdp_dq_oe1_l> <gen_dq_oe_l_t1[14].fdp_dq_oe1_l> <gen_dq_oe_l_t1[15].fdp_dq_oe1_l> 
+INFO:Xst:2260 - The FF/Latch <gen_dq_oe_l_t1[0].fdp_dq_oe0_l> in Unit <u_datapath> is equivalent to the following 15 FFs/Latches : <gen_dq_oe_l_t1[1].fdp_dq_oe0_l> <gen_dq_oe_l_t1[2].fdp_dq_oe0_l> <gen_dq_oe_l_t1[3].fdp_dq_oe0_l> <gen_dq_oe_l_t1[4].fdp_dq_oe0_l> <gen_dq_oe_l_t1[5].fdp_dq_oe0_l> <gen_dq_oe_l_t1[6].fdp_dq_oe0_l> <gen_dq_oe_l_t1[7].fdp_dq_oe0_l> <gen_dq_oe_l_t1[8].fdp_dq_oe0_l> <gen_dq_oe_l_t1[9].fdp_dq_oe0_l> <gen_dq_oe_l_t1[10].fdp_dq_oe0_l> <gen_dq_oe_l_t1[11].fdp_dq_oe0_l> <gen_dq_oe_l_t1[12].fdp_dq_oe0_l> <gen_dq_oe_l_t1[13].fdp_dq_oe0_l> <gen_dq_oe_l_t1[14].fdp_dq_oe0_l> <gen_dq_oe_l_t1[15].fdp_dq_oe0_l> 
+FlipFlop u_Core/vconv/vidin_hcnt_s_0 has been replicated 18 time(s)
+FlipFlop u_Core/vconv/vidin_hcnt_s_1 has been replicated 18 time(s)
+FlipFlop u_Core/vconv/vidin_hcnt_s_2 has been replicated 18 time(s)
+FlipFlop u_Core/vconv/vidin_hcnt_s_3 has been replicated 18 time(s)
+FlipFlop u_FileIO/mem_addr_0 has been replicated 1 time(s)
+FlipFlop u_FileIO/mem_addr_1 has been replicated 1 time(s)
+FlipFlop u_FileIO/mem_addr_2 has been replicated 1 time(s)
+FlipFlop u_FileIO/mem_addr_3 has been replicated 1 time(s)
+
+Final Macro Processing ...
+
+Processing Unit <antic1> :
+	Found 16-bit shift register for signal <nmi_shiftreg_reg_0>.
+	Found 5-bit shift register for signal <delay_display_shift_reg_0>.
+	Found 5-bit shift register for signal <delay_display_shift_reg_1>.
+	Found 5-bit shift register for signal <delay_display_shift_reg_2>.
+	Found 5-bit shift register for signal <delay_display_shift_reg_3>.
+	Found 5-bit shift register for signal <delay_display_shift_reg_4>.
+Unit <antic1> processed.
+
+Processing Unit <chbase_delay> :
+	Found 32-bit shift register for signal <shift_reg_0_0>.
+	Found 32-bit shift register for signal <shift_reg_0_1>.
+	Found 32-bit shift register for signal <shift_reg_0_2>.
+	Found 32-bit shift register for signal <shift_reg_0_3>.
+	Found 32-bit shift register for signal <shift_reg_0_4>.
+	Found 32-bit shift register for signal <shift_reg_0_5>.
+	Found 32-bit shift register for signal <shift_reg_0_6>.
+Unit <chbase_delay> processed.
+
+Processing Unit <delay_line_phase> :
+INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal <shift_reg_0> and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
+Unit <delay_line_phase> processed.
+
+Processing Unit <delay_line_phase2> :
+INFO:Xst:741 - HDL ADVISOR - A 8-bit shift register was found for signal <shift_reg_0> and currently occupies 8 logic cells (4 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
+Unit <delay_line_phase2> processed.
+
+Processing Unit <hposm0_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposm0_delay> processed.
+
+Processing Unit <hposm1_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposm1_delay> processed.
+
+Processing Unit <hposm2_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposm2_delay> processed.
+
+Processing Unit <hposm3_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposm3_delay> processed.
+
+Processing Unit <hposp0_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposp0_delay> processed.
+
+Processing Unit <hposp1_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposp1_delay> processed.
+
+Processing Unit <hposp2_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposp2_delay> processed.
+
+Processing Unit <hposp3_delay> :
+	Found 5-bit shift register for signal <shift_reg_0_0>.
+	Found 5-bit shift register for signal <shift_reg_0_1>.
+	Found 5-bit shift register for signal <shift_reg_0_2>.
+	Found 5-bit shift register for signal <shift_reg_0_3>.
+	Found 5-bit shift register for signal <shift_reg_0_4>.
+	Found 5-bit shift register for signal <shift_reg_0_5>.
+	Found 5-bit shift register for signal <shift_reg_0_6>.
+	Found 5-bit shift register for signal <shift_reg_0_7>.
+Unit <hposp3_delay> processed.
+
+Processing Unit <hsync_delay> :
+INFO:Xst:741 - HDL ADVISOR - A 15-bit shift register was found for signal <shift_reg_0> and currently occupies 15 logic cells (7 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
+Unit <hsync_delay> processed.
+
+Processing Unit <nmien_delay> :
+	Found 16-bit shift register for signal <shift_reg_0_0>.
+	Found 16-bit shift register for signal <shift_reg_0_1>.
+Unit <nmien_delay> processed.
+
+Processing Unit <prior_longer_delay> :
+	Found 4-bit shift register for signal <shift_reg_0_0>.
+	Found 4-bit shift register for signal <shift_reg_0_1>.
+Unit <prior_longer_delay> processed.
+
+Processing Unit <sio_in1_synchronizer> :
+	Found 3-bit shift register for signal <ff_reg_0>.
+	Found 3-bit shift register for signal <ff_reg_0>.
+Unit <sio_in1_synchronizer> processed.
+
+Processing Unit <sio_in3_synchronizer> :
+	Found 3-bit shift register for signal <ff_reg_0>.
+Unit <sio_in3_synchronizer> processed.
+
+Processing Unit <sizem_delay> :
+	Found 4-bit shift register for signal <shift_reg_0_0>.
+	Found 4-bit shift register for signal <shift_reg_0_1>.
+	Found 4-bit shift register for signal <shift_reg_0_2>.
+	Found 4-bit shift register for signal <shift_reg_0_3>.
+	Found 4-bit shift register for signal <shift_reg_0_4>.
+	Found 4-bit shift register for signal <shift_reg_0_5>.
+	Found 4-bit shift register for signal <shift_reg_0_6>.
+	Found 4-bit shift register for signal <shift_reg_0_7>.
+Unit <sizem_delay> processed.
+
+Processing Unit <sizep0_delay> :
+	Found 4-bit shift register for signal <shift_reg_0_0>.
+	Found 4-bit shift register for signal <shift_reg_0_1>.
+Unit <sizep0_delay> processed.
+
+Processing Unit <sizep1_delay> :
+	Found 4-bit shift register for signal <shift_reg_0_0>.
+	Found 4-bit shift register for signal <shift_reg_0_1>.
+Unit <sizep1_delay> processed.
+
+Processing Unit <sizep2_delay> :
+	Found 4-bit shift register for signal <shift_reg_0_0>.
+	Found 4-bit shift register for signal <shift_reg_0_1>.
+Unit <sizep2_delay> processed.
+
+Processing Unit <sizep3_delay> :
+	Found 4-bit shift register for signal <shift_reg_0_0>.
+	Found 4-bit shift register for signal <shift_reg_0_1>.
+Unit <sizep3_delay> processed.
+
+Processing Unit <u_DDRCtrl> :
+	Found 2-bit shift register for signal <ena_sys_t3>.
+Unit <u_DDRCtrl> processed.
+
+Processing Unit <u_FileIO> :
+	Found 2-bit shift register for signal <spi_rx_rdy_meta_2>.
+	Found 2-bit shift register for signal <spi_rx_sof_meta_2>.
+Unit <u_FileIO> processed.
+
+Processing Unit <u_I2C> :
+	Found 2-bit shift register for signal <scl_in_2>.
+	Found 2-bit shift register for signal <sda_in_2>.
+Unit <u_I2C> processed.
+
+Processing Unit <u_Kbd> :
+	Found 7-bit shift register for signal <key_state_FSM_FFd4>.
+Unit <u_Kbd> processed.
+
+Processing Unit <u_OSD> :
+	Found 2-bit shift register for signal <pix_active_t_2>.
+Unit <u_OSD> processed.
+
+Processing Unit <u_PSA> :
+	Found 2-bit shift register for signal <data_in_2>.
+	Found 2-bit shift register for signal <clk_in_2>.
+Unit <u_PSA> processed.
+
+Processing Unit <u_PSB> :
+	Found 2-bit shift register for signal <data_in_2>.
+	Found 2-bit shift register for signal <clk_in_2>.
+Unit <u_PSB> processed.
+
+Processing Unit <u_Syscon> :
+	Found 2-bit shift register for signal <spi_rx_rdy_meta_2>.
+Unit <u_Syscon> processed.
+
+Processing Unit <u_Video> :
+	Found 5-bit shift register for signal <o_video_hsync>.
+	Found 5-bit shift register for signal <o_video_vsync>.
+Unit <u_Video> processed.
+
+Processing Unit <u_ddr_ctrl> :
+	Found 4-bit shift register for signal <b0_state_FSM_FFd2>.
+Unit <u_ddr_ctrl> processed.
+
+Processing Unit <u_reset> :
+	Found 2-bit shift register for signal <por_l_meta2>.
+Unit <u_reset> processed.
+
+Processing Unit <vconv> :
+	Found 2-bit shift register for signal <o_vid_sync.dig_vs>.
+	Found 2-bit shift register for signal <o_vid_sync.ana_de>.
+	Found 2-bit shift register for signal <o_vid_sync.ana_hs>.
+	Found 2-bit shift register for signal <o_vid_sync.dig_de>.
+	Found 2-bit shift register for signal <o_vid_sync.dig_hs>.
+	Found 2-bit shift register for signal <o_vid_sync.ana_vs>.
+Unit <vconv> processed.
+
+Processing Unit <vscrol_delay> :
+	Found 16-bit shift register for signal <shift_reg_0_0>.
+	Found 16-bit shift register for signal <shift_reg_0_1>.
+	Found 16-bit shift register for signal <shift_reg_0_2>.
+	Found 16-bit shift register for signal <shift_reg_0_3>.
+Unit <vscrol_delay> processed.
+
+Processing Unit <wsync_delay> :
+INFO:Xst:741 - HDL ADVISOR - A 24-bit shift register was found for signal <shift_reg_0> and currently occupies 24 logic cells (12 slices). Removing the set/reset logic would take advantage of SRL16 (and derived) primitives and reduce this to 1 logic cells (1 slices). Evaluate if the set/reset can be removed for this simple shift register. The majority of simple pipeline structures do not need to be set/reset operationally.
+Unit <wsync_delay> processed.
+
+=========================================================================
+Final Register Report
+
+Macro Statistics
+# Registers                                            : 5346
+ Flip-Flops                                            : 5346
+# Shift Registers                                      : 126
+ 16-bit shift register                                 : 7
+ 2-bit shift register                                  : 18
+ 3-bit shift register                                  : 3
+ 32-bit shift register                                 : 7
+ 4-bit shift register                                  : 19
+ 5-bit shift register                                  : 71
+ 7-bit shift register                                  : 1
+
+=========================================================================
+
+=========================================================================
+*                           Partition Report                            *
+=========================================================================
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+=========================================================================
+*                            Final Report                               *
+=========================================================================
+Final Results
+Top Level Output File Name         : Replay.ngc
+Output Format                      : NGC
+Optimization Goal                  : Area
+Keep Hierarchy                     : yes
+
+Design Statistics
+# IOs                              : 227
+
+Cell Usage :
+# BELS                             : 18452
+#      BUF                         : 57
+#      GND                         : 76
+#      INV                         : 466
+#      LUT1                        : 340
+#      LUT2                        : 1570
+#      LUT3                        : 4230
+#      LUT4                        : 6145
+#      MUXCY                       : 1341
+#      MUXF5                       : 2137
+#      MUXF6                       : 592
+#      MUXF7                       : 278
+#      MUXF8                       : 136
+#      VCC                         : 65
+#      XORCY                       : 1019
+# FlipFlops/Latches                : 5786
+#      FD                          : 394
+#      FD_1                        : 2
+#      FDC                         : 648
+#      FDCE                        : 2175
+#      FDE                         : 1817
+#      FDP                         : 105
+#      FDPE                        : 126
+#      FDR                         : 192
+#      FDR_1                       : 16
+#      FDRE                        : 112
+#      FDRS                        : 32
+#      FDRSE                       : 21
+#      FDS                         : 60
+#      FDSE                        : 14
+#      IDDR2                       : 18
+#      ODDR2                       : 54
+# RAMS                             : 4482
+#      RAM16X1D                    : 3386
+#      RAM32X1S                    : 1060
+#      RAMB16_S1                   : 16
+#      RAMB16_S18_S18              : 1
+#      RAMB16_S2                   : 7
+#      RAMB16_S36                  : 1
+#      RAMB16_S4                   : 8
+#      RAMB16_S9                   : 1
+#      RAMB16_S9_S18               : 1
+#      RAMB16_S9_S9                : 1
+# Shift Registers                  : 141
+#      SRL16                       : 34
+#      SRL16E                      : 100
+#      SRLC16                      : 7
+# Clock Buffers                    : 8
+#      BUFG                        : 8
+# IO Buffers                       : 156
+#      IBUF                        : 33
+#      IBUFG                       : 4
+#      IOBUF                       : 7
+#      OBUF                        : 89
+#      OBUFT                       : 23
+# DCMs                             : 4
+#      DCM_SP                      : 4
+# MULTs                            : 4
+#      MULT18X18SIO                : 4
+# Others                           : 94
+#      PULLUP                      : 94
+=========================================================================
+
+Device utilization summary:
+---------------------------
+
+Selected Device : 3s1600efg320-4 
+
+ Number of Slices:                     8867  out of  14752    60%  
+ Number of Slice Flip Flops:           5766  out of  29504    19%  
+ Number of 4 input LUTs:              21784  out of  29504    73%  
+    Number used as logic:             12751
+    Number used as Shift registers:     141
+    Number used as RAMs:               8892
+ Number of IOs:                         227
+ Number of bonded IOBs:                 135  out of    250    54%  
+    IOB Flip Flops:                      20
+ Number of BRAMs:                        36  out of     36   100%  
+ Number of MULT18X18SIOs:                 4  out of     36    11%  
+ Number of GCLKs:                         8  out of     24    33%  
+ Number of DCMs:                          4  out of      8    50%  
+
+---------------------------
+Partition Resource Summary:
+---------------------------
+
+  No Partitions were found in this design.
+
+---------------------------
+
+
+=========================================================================
+TIMING REPORT
+
+NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
+      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
+      GENERATED AFTER PLACE-and-ROUTE.
+
+Clock Information:
+------------------
+-----------------------------------+-------------------------+-------+
+Clock Signal                       | Clock buffer(FF name)   | Load  |
+-----------------------------------+-------------------------+-------+
+ClK_A                              | u_a_dcm:CLKDV           | 9393  |
+ClK_B                              | u_b_dcm:CLK0            | 36    |
+ClK_A                              | phase_ctrl.u_a2_dcm:CLK0| 367   |
+ClK_C                              | u_c_dcm:CLK0            | 479   |
+ClK_C                              | u_c_dcm:CLK90           | 4     |
+i_FPGA_SPI_Clk                     | IBUFG+BUFG              | 101   |
+ClK_A                              | u_a_dcm:CLK90           | 104   |
+-----------------------------------+-------------------------+-------+
+
+Asynchronous Control Signals Information:
+----------------------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------+
+Control Signal                                                                                                                                               | Buffer(FF name)                                                                | Load  |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------+
+u_Core/atari800core/gtia1/RESET_N_inv(u_Core/atari800core/gtia1/RESET_N_inv631_INV_0:O)                                                                      | NONE(u_Core/atari800core/gtia1/COLOUR_REG_0)                                   | 309   |
+u_Core/atari800core/pokey1/RESET_N_inv(u_Core/atari800core/pokey1/RESET_N_inv531_INV_0:O)                                                                    | NONE(u_Core/atari800core/pokey1/audc0_reg_0)                                   | 244   |
+u_Core/atari800core/pokey2/RESET_N_inv(u_Core/atari800core/pokey2/RESET_N_inv531_INV_0:O)                                                                    | NONE(u_Core/atari800core/pokey2/audc0_reg_0)                                   | 239   |
+u_ClockGen/rst_ctl(u_ClockGen/rst_ctl:Q)                                                                                                                     | NONE(init_diskinsert_s)                                                        | 231   |
+u_Core/atari800core/antic1/RESET_N_inv(u_Core/atari800core/antic1/RESET_N_inv491_INV_0:O)                                                                    | NONE(u_Core/atari800core/antic1/RESET_N_inv_shift1)                            | 187   |
+u_Core/atari800core/zpu_config1/uart1/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/RESET_N_inv531_INV_0:O)                                              | NONE(u_Core/atari800core/zpu_config1/uart1/audctl_reg_0)                       | 186   |
+u_ClockGen/rst_ram(u_ClockGen/rst_ram:Q)                                                                                                                     | NONE(u_DDRCtrl/cur_lp)                                                         | 174   |
+u_ClockGen/rst_video(u_ClockGen/rst_video:Q)                                                                                                                 | NONE(u_Core/vconv/u_VideoTiming/act_h_cnt_0)                                   | 159   |
+u_Core/atari800core/zpu_config1/reset_zpu_reg(u_Core/atari800core/zpu_config1/reset_zpu_reg:Q)                                                               | NONE(u_Core/atari800core/zpu_glue1/ZPU_32BIT_WRITE_ENABLE_reg)                 | 106   |
+u_Core/u_Kbd/key_state_or0000(u_Core/u_Kbd/key_state_or00001:O)                                                                                              | NONE(u_Core/u_Kbd/key_break)                                                   | 95    |
+u_Core/atari800core/pia1/RESET_N_inv(u_Core/atari800core/pia1/RESET_N_inv1_INV_0:O)                                                                          | NONE(u_Core/atari800core/pia1/CA1_reg)                                         | 73    |
+u_Core/atari800core/mmu1/reset_n_inv(u_Core/atari800core/mmu1/reset_n_inv1_INV_0:O)                                                                          | NONE(u_Core/atari800core/mmu1/ADDR_reg_0)                                      | 63    |
+u_ClockGen/rst_ctl_hard(u_ClockGen/rst_ctl_hard:Q)                                                                                                           | NONE(u_Syscon/char_addr_0)                                                     | 45    |
+u_Core/atari800core/antic1/chbase_delay/RESET_N_inv(u_Core/atari800core/antic1/chbase_delay/RESET_N_inv321_INV_0:O)                                          | NONE(u_Core/atari800core/antic1/chbase_delay/RESET_N_inv_shift1)               | 38    |
+u_ClockGen/rst_aux(u_ClockGen/rst_aux:Q)                                                                                                                     | NONE(u_Audio/cnt_0)                                                            | 35    |
+u_Core/atari800core/pokey1/pokey_keyboard_scanner1/reset_n_inv(u_Core/atari800core/pokey1/pokey_keyboard_scanner1/reset_n_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/pokey_keyboard_scanner1/bincnt_reg_0)          | 25    |
+u_Core/atari800core/pokey2/pokey_keyboard_scanner1/reset_n_inv(u_Core/atari800core/pokey2/pokey_keyboard_scanner1/reset_n_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/pokey_keyboard_scanner1/bincnt_reg_0)          | 25    |
+u_Core/atari800core/antic1/wsync_delay/RESET_N_inv(u_Core/atari800core/antic1/wsync_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/antic1/wsync_delay/shift_reg_0)                       | 24    |
+u_Core/atari800core/antic1/vscrol_delay/RESET_N_inv(u_Core/atari800core/antic1/vscrol_delay/RESET_N_inv1_INV_0:O)                                            | NONE(u_Core/atari800core/antic1/vscrol_delay/RESET_N_inv_shift1)               | 19    |
+u_Core/atari800core/antic1/nmien_delay/RESET_N_inv(u_Core/atari800core/antic1/nmien_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/antic1/nmien_delay/RESET_N_inv_shift1)                | 17    |
+u_Core/atari800core/pokey1/poly_17_19_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey1/poly_17_19_lfsr/shift_reg_Acst_inv1_INV_0:O)                        | NONE(u_Core/atari800core/pokey1/poly_17_19_lfsr/shift_reg_0)                   | 17    |
+u_Core/atari800core/pokey2/poly_17_19_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey2/poly_17_19_lfsr/shift_reg_Acst_inv1_INV_0:O)                        | NONE(u_Core/atari800core/pokey2/poly_17_19_lfsr/shift_reg_0)                   | 17    |
+u_Core/atari800core/zpu_config1/uart1/poly_17_19_lfsr/shift_reg_Acst_inv(u_Core/atari800core/zpu_config1/uart1/poly_17_19_lfsr/shift_reg_Acst_inv1_INV_0:O)  | NONE(u_Core/atari800core/zpu_config1/uart1/poly_17_19_lfsr/shift_reg_0)        | 17    |
+u_Core/atari800core/antic1/antic_counter_display_list/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_display_list/RESET_n_inv1_INV_0:O)                | NONE(u_Core/atari800core/antic1/antic_counter_display_list/value_reg_0)        | 16    |
+u_Core/atari800core/antic1/antic_counter_memory_scan/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_memory_scan/RESET_n_inv1_INV_0:O)                  | NONE(u_Core/atari800core/antic1/antic_counter_memory_scan/value_reg_0)         | 16    |
+u_Core/atari800core/enables/delay_line_phase/RESET_N_inv(u_Core/atari800core/enables/delay_line_phase/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/enables/delay_line_phase/shift_reg_0)                 | 15    |
+u_Core/atari800core/gtia1/hsync_delay/RESET_N_inv(u_Core/atari800core/gtia1/hsync_delay/RESET_N_inv1_INV_0:O)                                                | NONE(u_Core/atari800core/gtia1/hsync_delay/shift_reg_0)                        | 15    |
+u_ClockGen/u_reset/o_rst(u_ClockGen/u_reset/o_rst:Q)                                                                                                         | NONE(u_ClockGen/ps_en)                                                         | 14    |
+u_Core/atari800core/gtia1/colbk_delay/RESET_N_inv(u_Core/atari800core/gtia1/colbk_delay/RESET_N_inv1_INV_0:O)                                                | NONE(u_Core/atari800core/gtia1/colbk_delay/shift_reg_0_0)                      | 14    |
+u_Core/atari800core/gtia1/colpf0_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf0_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpf1_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf1_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpf2_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf2_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpf3_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpf3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpf3_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpm0_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm0_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpm1_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm1_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpm2_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm2_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/colpm3_delay/RESET_N_inv(u_Core/atari800core/gtia1/colpm3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/colpm3_delay/shift_reg_0_0)                     | 14    |
+u_Core/atari800core/gtia1/hposm0_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm0_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposm1_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm1_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposm2_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm2_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposm3_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposm3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposm3_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposp0_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp0_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposp1_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp1_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposp2_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp2_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/hposp3_delay/RESET_N_inv(u_Core/atari800core/gtia1/hposp3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/hposp3_delay/RESET_N_inv_shift1)                | 12    |
+u_Core/atari800core/gtia1/prior_short_delay/RESET_N_inv(u_Core/atari800core/gtia1/prior_short_delay/RESET_N_inv1_INV_0:O)                                    | NONE(u_Core/atari800core/gtia1/prior_short_delay/shift_reg_0_0)                | 12    |
+u_Core/atari800core/gtia1/sizem_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizem_delay/RESET_N_inv1_INV_0:O)                                                | NONE(u_Core/atari800core/gtia1/sizem_delay/RESET_N_inv_shift1)                 | 11    |
+u_Core/atari800core/gtia1/player0/RESET_N_inv(u_Core/atari800core/gtia1/player0/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player0/count_reg_FSM_FFd1)                     | 10    |
+u_Core/atari800core/gtia1/player1/RESET_N_inv(u_Core/atari800core/gtia1/player1/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player1/count_reg_FSM_FFd1)                     | 10    |
+u_Core/atari800core/gtia1/player2/RESET_N_inv(u_Core/atari800core/gtia1/player2/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player2/count_reg_FSM_FFd1)                     | 10    |
+u_Core/atari800core/gtia1/player3/RESET_N_inv(u_Core/atari800core/gtia1/player3/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/gtia1/player3/count_reg_FSM_FFd1)                     | 10    |
+u_Core/atari800core/enables/RESET_N_inv(u_Core/atari800core/enables/RESET_N_inv1_INV_0:O)                                                                    | NONE(u_Core/atari800core/enables/cpu_extra_enable_reg)                         | 9     |
+i_FPGA_Ctrl0                                                                                                                                                 | IBUF                                                                           | 8     |
+u_Core/atari800core/antic1/antic_dma_clock1/RESET_n_inv(u_Core/atari800core/antic1/antic_dma_clock1/RESET_n_inv1_INV_0:O)                                    | NONE(u_Core/atari800core/antic1/antic_dma_clock1/dma_shiftreg_reg_0)           | 8     |
+u_Core/atari800core/enables/delay_line_phase2/RESET_N_inv(u_Core/atari800core/enables/delay_line_phase2/RESET_N_inv1_INV_0:O)                                | NONE(u_Core/atari800core/enables/delay_line_phase2/shift_reg_0)                | 8     |
+u_Core/atari800core/gtia1/counter_hpos/RESET_n_inv(u_Core/atari800core/gtia1/counter_hpos/RESET_n_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/counter_hpos/value_reg_0)                       | 8     |
+u_Core/atari800core/pokey1/enable_15_div/RESET_N_inv(u_Core/atari800core/pokey1/enable_15_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey1/enable_15_div/count_reg_0)                     | 8     |
+u_Core/atari800core/pokey1/timer0/RESET_N_inv(u_Core/atari800core/pokey1/timer0/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer0/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey1/timer1/RESET_N_inv(u_Core/atari800core/pokey1/timer1/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer1/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey1/timer2/RESET_N_inv(u_Core/atari800core/pokey1/timer2/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer2/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey1/timer3/RESET_N_inv(u_Core/atari800core/pokey1/timer3/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey1/timer3/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey2/enable_15_div/RESET_N_inv(u_Core/atari800core/pokey2/enable_15_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey2/enable_15_div/count_reg_0)                     | 8     |
+u_Core/atari800core/pokey2/timer0/RESET_N_inv(u_Core/atari800core/pokey2/timer0/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer0/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey2/timer1/RESET_N_inv(u_Core/atari800core/pokey2/timer1/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer1/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey2/timer2/RESET_N_inv(u_Core/atari800core/pokey2/timer2/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer2/count_reg_0)                            | 8     |
+u_Core/atari800core/pokey2/timer3/RESET_N_inv(u_Core/atari800core/pokey2/timer3/RESET_N_inv1_INV_0:O)                                                        | NONE(u_Core/atari800core/pokey2/timer3/count_reg_0)                            | 8     |
+u_Core/atari800core/zpu_config1/uart1/enable_15_div/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/enable_15_div/RESET_N_inv1_INV_0:O)                    | NONE(u_Core/atari800core/zpu_config1/uart1/enable_15_div/count_reg_0)          | 8     |
+u_Core/atari800core/zpu_config1/uart1/timer0/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer0/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer0/count_reg_0)                 | 8     |
+u_Core/atari800core/zpu_config1/uart1/timer1/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer1/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer1/count_reg_0)                 | 8     |
+u_Core/atari800core/zpu_config1/uart1/timer2/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer2/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer2/count_reg_0)                 | 8     |
+u_Core/atari800core/zpu_config1/uart1/timer3/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer3/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/zpu_config1/uart1/timer3/count_reg_0)                 | 8     |
+i_FPGA_Ctrl1                                                                                                                                                 | IBUF                                                                           | 7     |
+u_ClockGen/u_reset/o_rst_soft_or0000(u_ClockGen/u_reset/o_rst_soft_or00001:O)                                                                                | NONE(u_ClockGen/u_reset/o_rst_soft)                                            | 6     |
+u_ClockGen/u_reset/por_l_meta2_inv(u_ClockGen/u_reset/por_l_meta2_inv1_INV_0:O)                                                                              | NONE(u_ClockGen/u_reset/o_rst)                                                 | 6     |
+u_Core/atari800core/antic1/antic_counter_line_buffer/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_line_buffer/RESET_n_inv1_INV_0:O)                  | NONE(u_Core/atari800core/antic1/antic_counter_line_buffer/value_reg_0)         | 6     |
+u_Core/atari800core/gtia1/prior_long_delay/RESET_N_inv(u_Core/atari800core/gtia1/prior_long_delay/RESET_N_inv1_INV_0:O)                                      | NONE(u_Core/atari800core/gtia1/prior_long_delay/shift_reg_0_0)                 | 6     |
+u_Core/atari800core/pokey1/enable_64_div/RESET_N_inv(u_Core/atari800core/pokey1/enable_64_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey1/enable_64_div/count_reg_0)                     | 6     |
+u_Core/atari800core/pokey2/enable_64_div/RESET_N_inv(u_Core/atari800core/pokey2/enable_64_div/RESET_N_inv1_INV_0:O)                                          | NONE(u_Core/atari800core/pokey2/enable_64_div/count_reg_0)                     | 6     |
+u_Core/atari800core/zpu_config1/uart1/enable_64_div/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/enable_64_div/RESET_N_inv1_INV_0:O)                    | NONE(u_Core/atari800core/zpu_config1/uart1/enable_64_div/count_reg_0)          | 6     |
+u_Core/atari800core/enables/enable_179_clock_div/RESET_N_inv(u_Core/atari800core/enables/enable_179_clock_div/RESET_N_inv1_INV_0:O)                          | NONE(u_Core/atari800core/enables/enable_179_clock_div/count_reg_0)             | 5     |
+u_Core/atari800core/gtia1/prior_longer_delay/RESET_N_inv(u_Core/atari800core/gtia1/prior_longer_delay/RESET_N_inv1_INV_0:O)                                  | NONE(u_Core/atari800core/gtia1/prior_longer_delay/RESET_N_inv_shift1)          | 5     |
+u_Core/atari800core/gtia1/sizep0_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep0_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep0_delay/RESET_N_inv_shift1)                | 5     |
+u_Core/atari800core/gtia1/sizep1_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep1_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep1_delay/RESET_N_inv_shift1)                | 5     |
+u_Core/atari800core/gtia1/sizep2_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep2_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep2_delay/RESET_N_inv_shift1)                | 5     |
+u_Core/atari800core/gtia1/sizep3_delay/RESET_N_inv(u_Core/atari800core/gtia1/sizep3_delay/RESET_N_inv1_INV_0:O)                                              | NONE(u_Core/atari800core/gtia1/sizep3_delay/RESET_N_inv_shift1)                | 5     |
+u_Core/atari800core/pokey1/poly_5_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey1/poly_5_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey1/poly_5_lfsr/shift_reg_0)                       | 5     |
+u_Core/atari800core/pokey2/poly_5_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey2/poly_5_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey2/poly_5_lfsr/shift_reg_0)                       | 5     |
+u_Core/atari800core/antic1/antic_counter_refresh_count/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_refresh_count/RESET_n_inv1_INV_0:O)              | NONE(u_Core/atari800core/antic1/antic_counter_refresh_count/value_reg_0)       | 4     |
+u_Core/atari800core/antic1/antic_counter_row_count/RESET_n_inv(u_Core/atari800core/antic1/antic_counter_row_count/RESET_n_inv1_INV_0:O)                      | NONE(u_Core/atari800core/antic1/antic_counter_row_count/value_reg_0)           | 4     |
+u_Core/atari800core/gtia1/missile0/RESET_N_inv(u_Core/atari800core/gtia1/missile0/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile0/count_reg_FSM_FFd1)                    | 4     |
+u_Core/atari800core/gtia1/missile1/RESET_N_inv(u_Core/atari800core/gtia1/missile1/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile1/count_reg_FSM_FFd1)                    | 4     |
+u_Core/atari800core/gtia1/missile2/RESET_N_inv(u_Core/atari800core/gtia1/missile2/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile2/count_reg_FSM_FFd1)                    | 4     |
+u_Core/atari800core/gtia1/missile3/RESET_N_inv(u_Core/atari800core/gtia1/missile3/RESET_N_inv1_INV_0:O)                                                      | NONE(u_Core/atari800core/gtia1/missile3/count_reg_FSM_FFd1)                    | 4     |
+u_Core/atari800core/pokey1/poly_4_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey1/poly_4_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey1/poly_4_lfsr/shift_reg_0)                       | 4     |
+u_Core/atari800core/pokey2/poly_4_lfsr/shift_reg_Acst_inv(u_Core/atari800core/pokey2/poly_4_lfsr/shift_reg_Acst_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey2/poly_4_lfsr/shift_reg_0)                       | 4     |
+u_ClockGen/u_reset/o_rst_soft(u_ClockGen/u_reset/o_rst_soft:Q)                                                                                               | NONE(u_ClockGen/rst_aux)                                                       | 3     |
+u_Core/atari800core/pokey1/stimer_delay/RESET_N_inv(u_Core/atari800core/pokey1/stimer_delay/RESET_N_inv1_INV_0:O)                                            | NONE(u_Core/atari800core/pokey1/stimer_delay/shift_reg_0)                      | 3     |
+u_Core/atari800core/pokey1/timer0/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer0/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer0/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey1/timer1/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer1/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer1/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey1/timer2/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer2/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer2/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey1/timer3/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey1/timer3/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey1/timer3/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey2/stimer_delay/RESET_N_inv(u_Core/atari800core/pokey2/stimer_delay/RESET_N_inv1_INV_0:O)                                            | NONE(u_Core/atari800core/pokey2/stimer_delay/shift_reg_0)                      | 3     |
+u_Core/atari800core/pokey2/timer0/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer0/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer0/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey2/timer1/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer1/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer1/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey2/timer2/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer2/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer2/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/pokey2/timer3/underflow0_delay/RESET_N_inv(u_Core/atari800core/pokey2/timer3/underflow0_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/pokey2/timer3/underflow0_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/zpu_config1/uart1/stimer_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/stimer_delay/RESET_N_inv1_INV_0:O)                      | NONE(u_Core/atari800core/zpu_config1/uart1/stimer_delay/shift_reg_0)           | 3     |
+u_Core/atari800core/zpu_config1/uart1/timer0/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer0/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer0/underflow0_delay/shift_reg_0)| 3     |
+u_Core/atari800core/zpu_config1/uart1/timer1/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer1/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer1/underflow0_delay/shift_reg_0)| 3     |
+u_Core/atari800core/zpu_config1/uart1/timer2/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer2/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer2/underflow0_delay/shift_reg_0)| 3     |
+u_Core/atari800core/zpu_config1/uart1/timer3/underflow0_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/timer3/underflow0_delay/RESET_N_inv1_INV_0:O)| NONE(u_Core/atari800core/zpu_config1/uart1/timer3/underflow0_delay/shift_reg_0)| 3     |
+u_ClockGen/rst_video_hard(u_ClockGen/rst_video_hard:Q)                                                                                                       | NONE(u_Video/o_video_rst_l)                                                    | 2     |
+u_Core/atari800core/internalromram1/reset_n_inv(u_Core/atari800core/internalromram1/reset_n_inv1_INV_0:O)                                                    | NONE(u_Core/atari800core/internalromram1/ram_request_reg)                      | 2     |
+u_Core/atari800core/pokey1/serout_clock_delay/RESET_N_inv(u_Core/atari800core/pokey1/serout_clock_delay/RESET_N_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey1/serout_clock_delay/shift_reg_0)                | 2     |
+u_Core/atari800core/pokey2/serout_clock_delay/RESET_N_inv(u_Core/atari800core/pokey2/serout_clock_delay/RESET_N_inv1_INV_0:O)                                | NONE(u_Core/atari800core/pokey2/serout_clock_delay/shift_reg_0)                | 2     |
+u_Core/atari800core/zpu_config1/reset_6502_cpu_reg(u_Core/atari800core/zpu_config1/reset_6502_cpu_reg:Q)                                                     | NONE(u_Core/atari800core/cpu6502/nmi_n_reg)                                    | 2     |
+u_Core/atari800core/zpu_config1/uart1/serout_clock_delay/RESET_N_inv(u_Core/atari800core/zpu_config1/uart1/serout_clock_delay/RESET_N_inv1_INV_0:O)          | NONE(u_Core/atari800core/zpu_config1/uart1/serout_clock_delay/shift_reg_0)     | 2     |
+u_DDRCtrl/u_ddr_ctrl/o_taken(u_DDRCtrl/u_ddr_ctrl/u_ack_reg:Q)                                                                                               | NONE(u_DDRCtrl/sys_taken_meta1)                                                | 1     |
+u_DDRCtrl/u_ddr_ctrl/u_datapath/dq_st(u_DDRCtrl/u_ddr_ctrl/u_datapath/fd_dq_st:Q)                                                                            | NONE(u_DDRCtrl/u_ddr_ctrl/u_datapath/dq_st_hold)                               | 1     |
+u_FileIO/spi_rx_rdy_meta_2(u_FileIO/spi_rx_rdy_meta_2:Q)                                                                                                     | NONE(u_FileIO/u_spi/o_rdy)                                                     | 1     |
+u_FileIO/spi_rx_sof_meta_2(u_FileIO/spi_rx_sof_meta_2:Q)                                                                                                     | NONE(u_FileIO/u_spi/o_sof)                                                     | 1     |
+u_Syscon/spi_ctrl.reset(u_Syscon/spi_ctrl.reset:Q)                                                                                                           | NONE(u_ClockGen/u_reset/rst_soft)                                              | 1     |
+u_Syscon/spi_rx_rdy_meta_2(u_Syscon/spi_rx_rdy_meta_2:Q)                                                                                                     | NONE(u_Syscon/u_spi/o_rdy)                                                     | 1     |
+-------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+-------+
+
+Timing Summary:
+---------------
+Speed Grade: -4
+
+   Minimum period: 11.410ns (Maximum Frequency: 87.640MHz)
+   Minimum input arrival time before clock: 3.673ns
+   Maximum output required time after clock: 11.067ns
+   Maximum combinational path delay: 6.671ns
+
+Timing Detail:
+--------------
+All values displayed in nanoseconds (ns)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'ClK_A'
+  Clock period: 11.410ns (frequency: 87.640MHz)
+  Total number of paths / destination ports: 16152102 / 51567
+-------------------------------------------------------------------------
+Delay:               2.853ns (Levels of Logic = 2)
+  Source:            u_ClockGen/rst_ram (FF)
+  Destination:       u_DDRCtrl/u_ddr_ctrl/u_datapath/gen_dm[0].oddr_dm (FF)
+  Source Clock:      ClK_A rising
+  Destination Clock: ClK_A rising +90
+
+  Data Path: u_ClockGen/rst_ram to u_DDRCtrl/u_ddr_ctrl/u_datapath/gen_dm[0].oddr_dm
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDPE:C->Q           182   0.591   1.310  rst_ram (rst_ram)
+     end scope: 'u_ClockGen'
+     begin scope: 'u_DDRCtrl'
+     begin scope: 'u_ddr_ctrl'
+     begin scope: 'u_datapath'
+     ODDR2:S                   0.952          gen_dm[0].oddr_dm
+    ----------------------------------------
+    Total                      2.853ns (1.543ns logic, 1.310ns route)
+                                       (54.1% logic, 45.9% route)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'ClK_B'
+  Clock period: 5.012ns (frequency: 199.534MHz)
+  Total number of paths / destination ports: 364 / 58
+-------------------------------------------------------------------------
+Delay:               5.012ns (Levels of Logic = 4)
+  Source:            u_Audio/cnt_3 (FF)
+  Destination:       u_Audio/shifter_2 (FF)
+  Source Clock:      ClK_B rising
+  Destination Clock: ClK_B rising
+
+  Data Path: u_Audio/cnt_3 to u_Audio/shifter_2
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDC:C->Q              2   0.591   0.622  cnt_3 (cnt_3)
+     LUT4:I0->O            1   0.704   0.000  o_sample_taken_cmp_eq00001 (o_sample_taken_cmp_eq00001)
+     MUXF5:I0->O          43   0.321   1.441  o_sample_taken_cmp_eq0000_f5 (o_sample_taken_cmp_eq0000)
+     LUT4:I0->O            1   0.704   0.000  shifter_mux0002<9>2 (shifter_mux0002<9>2)
+     MUXF5:I0->O           1   0.321   0.000  shifter_mux0002<9>_f5 (shifter_mux0002<9>)
+     FDCE:D                    0.308          shifter_9
+    ----------------------------------------
+    Total                      5.012ns (2.949ns logic, 2.063ns route)
+                                       (58.8% logic, 41.2% route)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'ClK_C'
+  Clock period: 10.700ns (frequency: 93.458MHz)
+  Total number of paths / destination ports: 40688 / 677
+-------------------------------------------------------------------------
+Delay:               10.700ns (Levels of Logic = 8)
+  Source:            u_Core/vconv/u_VideoTiming/v_cnt_9 (FF)
+  Destination:       u_Core/vconv/u_VideoTiming/cs_gate_2 (FF)
+  Source Clock:      ClK_C rising
+  Destination Clock: ClK_C rising
+
+  Data Path: u_Core/vconv/u_VideoTiming/v_cnt_9 to u_Core/vconv/u_VideoTiming/cs_gate_2
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDCE:C->Q            25   0.591   1.435  v_cnt_9 (v_cnt_9)
+     LUT3:I0->O            2   0.704   0.526  cs_gate_or0000311 (N57)
+     LUT3:I1->O            1   0.704   0.424  cs_gate_or00002_SW0 (N72)
+     LUT4:I3->O            4   0.704   0.666  cs_gate_or00002 (N8)
+     LUT4:I1->O            1   0.704   0.000  cs_gate_or00004112 (cs_gate_or00004111)
+     MUXF5:I0->O           2   0.321   0.622  cs_gate_or0000411_f5 (cs_gate_or000041)
+     LUT4:I0->O            1   0.704   0.424  cs_gate_mux0036<2>12_SW0 (N161)
+     LUT4:I3->O            1   0.704   0.455  cs_gate_mux0036<2>12 (cs_gate_mux0036<2>12)
+     LUT3:I2->O            1   0.704   0.000  cs_gate_mux0036<2>35 (cs_gate_mux0036<2>)
+     FDCE:D                    0.308          cs_gate_2
+    ----------------------------------------
+    Total                     10.700ns (6.148ns logic, 4.552ns route)
+                                       (57.5% logic, 42.5% route)
+
+=========================================================================
+Timing constraint: Default period analysis for Clock 'i_FPGA_SPI_Clk'
+  Clock period: 11.320ns (frequency: 88.339MHz)
+  Total number of paths / destination ports: 397 / 132
+-------------------------------------------------------------------------
+Delay:               5.660ns (Levels of Logic = 6)
+  Source:            u_Syscon/u_spi/o_rxcmd_0 (FF)
+  Destination:       u_Syscon/u_spi/dout_0 (FF)
+  Source Clock:      i_FPGA_SPI_Clk rising
+  Destination Clock: i_FPGA_SPI_Clk falling
+
+  Data Path: u_Syscon/u_spi/o_rxcmd_0 to u_Syscon/u_spi/dout_0
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDE:C->Q             10   0.591   1.057  o_rxcmd_0 (o_rxcmd_0)
+     end scope: 'u_spi'
+     LUT4:I0->O            1   0.704   0.000  spi_tx_data<0>82_SW02 (spi_tx_data<0>82_SW01)
+     MUXF5:I0->O           2   0.321   0.526  spi_tx_data<0>82_SW0_f5 (N12)
+     LUT4:I1->O            1   0.704   0.000  spi_tx_data<0>82_F (N18)
+     MUXF5:I0->O           1   0.321   0.424  spi_tx_data<0>82 (spi_tx_data<0>)
+     begin scope: 'u_spi'
+     LUT4:I3->O            1   0.704   0.000  dout_mux0002<0>1 (dout_mux0002<0>)
+     FDR_1:D                   0.308          dout_0
+    ----------------------------------------
+    Total                      5.660ns (3.653ns logic, 2.007ns route)
+                                       (64.5% logic, 35.5% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'ClK_C'
+  Total number of paths / destination ports: 1 / 1
+-------------------------------------------------------------------------
+Offset:              2.059ns (Levels of Logic = 2)
+  Source:            i_Ext_Rst_L (PAD)
+  Destination:       u_ClockGen/u_reset/Mshreg_por_l_meta2 (FF)
+  Destination Clock: ClK_C rising
+
+  Data Path: i_Ext_Rst_L to u_ClockGen/u_reset/Mshreg_por_l_meta2
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O             1   1.218   0.420  i_Ext_Rst_L_IBUF (i_Ext_Rst_L_IBUF)
+     begin scope: 'u_ClockGen'
+     begin scope: 'u_reset'
+     SRL16:D                   0.421          Mshreg_por_l_meta2
+    ----------------------------------------
+    Total                      2.059ns (1.639ns logic, 0.420ns route)
+                                       (79.6% logic, 20.4% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'ClK_A'
+  Total number of paths / destination ports: 18 / 18
+-------------------------------------------------------------------------
+Offset:              3.673ns (Levels of Logic = 3)
+  Source:            b_Video_SPD (PAD)
+  Destination:       u_Video/u_I2C/spd_in_0 (FF)
+  Destination Clock: ClK_A rising 0.2X
+
+  Data Path: b_Video_SPD to u_Video/u_I2C/spd_in_0
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IOBUF:IO->O           1   1.218   0.420  b_Video_SPD_IOBUF (N9)
+     begin scope: 'u_Video'
+     begin scope: 'u_I2C'
+     INV:I->O              1   0.704   0.420  i_spd_inv1_INV_0 (i_spd_inv)
+     FDR:R                     0.911          spd_in_0
+    ----------------------------------------
+    Total                      3.673ns (2.833ns logic, 0.840ns route)
+                                       (77.1% logic, 22.9% route)
+
+=========================================================================
+Timing constraint: Default OFFSET IN BEFORE for Clock 'i_FPGA_SPI_Clk'
+  Total number of paths / destination ports: 5 / 5
+-------------------------------------------------------------------------
+Offset:              2.159ns (Levels of Logic = 2)
+  Source:            b_FPGA_SPI_MOSI (PAD)
+  Destination:       u_FileIO/u_spi/din_0 (FF)
+  Destination Clock: i_FPGA_SPI_Clk rising
+
+  Data Path: b_FPGA_SPI_MOSI to u_FileIO/u_spi/din_0
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O             5   1.218   0.633  b_FPGA_SPI_MOSI_IBUF (b_FPGA_SPI_MOSI_IBUF)
+     begin scope: 'u_FileIO'
+     begin scope: 'u_spi'
+     FD:D                      0.308          din_0
+    ----------------------------------------
+    Total                      2.159ns (1.526ns logic, 0.633ns route)
+                                       (70.7% logic, 29.3% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'ClK_A'
+  Total number of paths / destination ports: 143 / 65
+-------------------------------------------------------------------------
+Offset:              11.067ns (Levels of Logic = 7)
+  Source:            u_FileIO/u_mem_FIFO/level_11 (FF)
+  Destination:       b_Aux_IO<10> (PAD)
+  Source Clock:      ClK_A rising 0.2X
+
+  Data Path: u_FileIO/u_mem_FIFO/level_11 to b_Aux_IO<10>
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDR:C->Q              6   0.591   0.844  level_11 (level_11)
+     end scope: 'u_mem_FIFO'
+     LUT2:I0->O            2   0.704   0.482  mem_fifo_hfull1 (mem_fifo_hfull)
+     LUT4:I2->O            3   0.704   0.706  o_mch_valid1 (o_mch_valid)
+     end scope: 'u_FileIO'
+     LUT4:I0->O            3   0.704   0.566  writeprotn_s_not0001163 (N0)
+     LUT4:I2->O            4   0.704   0.666  conf_wr_core11 (b_Aux_IO_8_OBUF)
+     LUT2:I1->O            1   0.704   0.420  conf_wr_15411 (b_Aux_IO_11_OBUF)
+     OBUF:I->O                 3.272          b_Aux_IO_11_OBUF (b_Aux_IO<11>)
+    ----------------------------------------
+    Total                     11.067ns (7.383ns logic, 3.684ns route)
+                                       (66.7% logic, 33.3% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'i_FPGA_SPI_Clk'
+  Total number of paths / destination ports: 2 / 1
+-------------------------------------------------------------------------
+Offset:              5.486ns (Levels of Logic = 3)
+  Source:            u_Syscon/u_spi/dout_7 (FF)
+  Destination:       b_FPGA_SPI_MISO (PAD)
+  Source Clock:      i_FPGA_SPI_Clk falling
+
+  Data Path: u_Syscon/u_spi/dout_7 to b_FPGA_SPI_MISO
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDR_1:C->Q            1   0.591   0.499  dout_7 (dout_7)
+     end scope: 'u_spi'
+     end scope: 'u_Syscon'
+     LUT4:I1->O            1   0.704   0.420  b_FPGA_SPI_MISO_MLTSRCEDGELogicTrst1 (b_FPGA_SPI_MISO_MLTSRCEDGE)
+     OBUFT:I->O                3.272          b_FPGA_SPI_MISO_OBUFT (b_FPGA_SPI_MISO)
+    ----------------------------------------
+    Total                      5.486ns (4.567ns logic, 0.919ns route)
+                                       (83.2% logic, 16.8% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'ClK_C'
+  Total number of paths / destination ports: 7 / 7
+-------------------------------------------------------------------------
+Offset:              4.450ns (Levels of Logic = 2)
+  Source:            u_Syscon/o_vbl (FF)
+  Destination:       o_SSC_RD (PAD)
+  Source Clock:      ClK_C rising
+
+  Data Path: u_Syscon/o_vbl to o_SSC_RD
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FD:C->Q               4   0.591   0.587  o_vbl (o_vbl)
+     end scope: 'u_Syscon'
+     OBUF:I->O                 3.272          o_SSC_RD_OBUF (o_SSC_RD)
+    ----------------------------------------
+    Total                      4.450ns (3.863ns logic, 0.587ns route)
+                                       (86.8% logic, 13.2% route)
+
+=========================================================================
+Timing constraint: Default OFFSET OUT AFTER for Clock 'ClK_B'
+  Total number of paths / destination ports: 4 / 4
+-------------------------------------------------------------------------
+Offset:              4.283ns (Levels of Logic = 2)
+  Source:            u_Audio/o_audio_din (FF)
+  Destination:       o_Audio_DIN (PAD)
+  Source Clock:      ClK_B rising
+
+  Data Path: u_Audio/o_audio_din to o_Audio_DIN
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     FDC:C->Q              1   0.591   0.420  o_audio_din (o_audio_din)
+     end scope: 'u_Audio'
+     OBUF:I->O                 3.272          o_Audio_DIN_OBUF (o_Audio_DIN)
+    ----------------------------------------
+    Total                      4.283ns (3.863ns logic, 0.420ns route)
+                                       (90.2% logic, 9.8% route)
+
+=========================================================================
+Timing constraint: Default path analysis
+  Total number of paths / destination ports: 4 / 1
+-------------------------------------------------------------------------
+Delay:               6.671ns (Levels of Logic = 3)
+  Source:            i_FPGA_Ctrl0 (PAD)
+  Destination:       b_FPGA_SPI_MISO (PAD)
+
+  Data Path: i_FPGA_Ctrl0 to b_FPGA_SPI_MISO
+                                Gate     Net
+    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
+    ----------------------------------------  ------------
+     IBUF:I->O            10   1.218   1.057  i_FPGA_Ctrl0_IBUF (b_FPGA_SPI_MISO_spi_fileio_miso_not0000_inv)
+     LUT2:I0->O            1   0.704   0.420  b_FPGA_SPI_MISOControl1 (N5)
+     OBUFT:T->O                3.272          b_FPGA_SPI_MISO_OBUFT (b_FPGA_SPI_MISO)
+    ----------------------------------------
+    Total                      6.671ns (5.194ns logic, 1.477ns route)
+                                       (77.9% logic, 22.1% route)
+
+=========================================================================
+
+
+Total REAL time to Xst completion: 461.00 secs
+Total CPU time to Xst completion: 458.88 secs
+ 
+--> 
+
+
+Total memory usage is 506540 kilobytes
+
+Number of errors   :    0 (   0 filtered)
+Number of warnings : 1376 (   0 filtered)
+Number of infos    :  154 (   0 filtered)
+
+Starting Translate...
+Release 14.7 - ngdbuild P.20131013 (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+Command Line:
+/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/bin/lin/unwrapped/ngdbuild -nt on
+-uc Replay.ucf Replay.ngc Replay.ngd
+
+Reading NGO file
+"/home/markw/altera/replay/src/hw/replay/cores/atari_800xl/build/Replay.ngc" ...
+Gathering constraint information from source properties...
+Done.
+
+Annotating constraints to design from ucf file "Replay.ucf" ...
+Resolving constraint associations...
+Checking Constraint Associations...
+WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(37)"              LOC =
+   "C3"  |> [Replay.ucf(79)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_Aux_IO(37)"' because those design objects do
+   not contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_Aux_IO(37)"              LOC = "C3"  |> [Replay.ucf(79)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(79)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_Aux_IO(37)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(79)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_Aux_IO(37)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(38)"              LOC =
+   "B6"  |> [Replay.ucf(101)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_Aux_IO(38)"' because those design objects do
+   not contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_Aux_IO(38)"              LOC = "B6"  |> [Replay.ucf(101)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(101)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_Aux_IO(38)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(101)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_Aux_IO(38)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(36)"              LOC =
+   "F11" |> [Replay.ucf(128)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_Aux_IO(36)"' because those design objects do
+   not contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_Aux_IO(36)"              LOC = "F11" |> [Replay.ucf(128)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(128)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_Aux_IO(36)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(128)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_Aux_IO(36)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_2V5_IO_1"                LOC =
+   "E16" |> [Replay.ucf(160)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_2V5_IO_1"' because those design objects do
+   not contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_2V5_IO_1"                LOC = "E16" |> [Replay.ucf(160)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVCMOS25;>
+   [Replay.ucf(160)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_2V5_IO_1"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_2V5_IO_0"                LOC =
+   "E15" |> [Replay.ucf(161)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_2V5_IO_0"' because those design objects do
+   not contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_2V5_IO_0"                LOC = "E15" |> [Replay.ucf(161)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVCMOS25;>
+   [Replay.ucf(161)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_2V5_IO_0"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_Clk_Aux"                 LOC =
+   "N9"  |> [Replay.ucf(258)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_Clk_Aux"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_Clk_Aux"                 LOC = "N9"  |> [Replay.ucf(258)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(258)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_Clk_Aux"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(258)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_Clk_Aux"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(15)"                  LOC =
+   "N7"  |> [Replay.ucf(272)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(15)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(15)"                  LOC = "N7"  |> [Replay.ucf(272)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(272)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(15)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(272)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(15)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(3)"                   LOC =
+   "V5"  |> [Replay.ucf(277)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(3)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(3)"                   LOC = "V5"  |> [Replay.ucf(277)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(277)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(3)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(277)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(3)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(4)"                   LOC =
+   "U5"  |> [Replay.ucf(278)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(4)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(4)"                   LOC = "U5"  |> [Replay.ucf(278)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(278)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(4)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(278)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(4)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(5)"                   LOC =
+   "T5"  |> [Replay.ucf(279)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(5)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(5)"                   LOC = "T5"  |> [Replay.ucf(279)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(279)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(5)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(279)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(5)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(6)"                   LOC =
+   "R5"  |> [Replay.ucf(281)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(6)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(6)"                   LOC = "R5"  |> [Replay.ucf(281)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(281)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(6)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(281)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(6)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(7)"                   LOC =
+   "T4"  |> [Replay.ucf(283)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(7)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(7)"                   LOC = "T4"  |> [Replay.ucf(283)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(283)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(7)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(283)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(7)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(8)"                   LOC =
+   "U3"  |> [Replay.ucf(285)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(8)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(8)"                   LOC = "U3"  |> [Replay.ucf(285)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(285)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(8)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(285)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(8)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(9)"                   LOC =
+   "T1"  |> [Replay.ucf(291)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(9)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(9)"                   LOC = "T1"  |> [Replay.ucf(291)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(291)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(9)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(291)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(9)"' because those design objects do not contain or drive any instances
+   of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(10)"                  LOC =
+   "T2"  |> [Replay.ucf(292)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(10)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(10)"                  LOC = "T2"  |> [Replay.ucf(292)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(292)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(10)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(292)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(10)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(11)"                  LOC =
+   "R2"  |> [Replay.ucf(294)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(11)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(11)"                  LOC = "R2"  |> [Replay.ucf(294)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(294)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(11)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(294)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(11)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(12)"                  LOC =
+   "R3"  |> [Replay.ucf(295)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(12)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(12)"                  LOC = "R3"  |> [Replay.ucf(295)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(295)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(12)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(295)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(12)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(13)"                  LOC =
+   "P1"  |> [Replay.ucf(297)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(13)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(13)"                  LOC = "P1"  |> [Replay.ucf(297)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(297)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(13)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(297)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(13)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(14)"                  LOC =
+   "P2"  |> [Replay.ucf(299)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(14)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(14)"                  LOC = "P2"  |> [Replay.ucf(299)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(299)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(14)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(299)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(14)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(43)"                  LOC =
+   "P4"  |> [Replay.ucf(301)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(43)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(43)"                  LOC = "P4"  |> [Replay.ucf(301)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(301)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(43)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(301)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(43)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(42)"                  LOC =
+   "N4"  |> [Replay.ucf(304)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(42)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(42)"                  LOC = "N4"  |> [Replay.ucf(304)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(304)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(42)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(304)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(42)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(41)"                  LOC =
+   "N5"  |> [Replay.ucf(305)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(41)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(41)"                  LOC = "N5"  |> [Replay.ucf(305)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(305)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(41)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(305)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(41)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(40)"                  LOC =
+   "M3"  |> [Replay.ucf(308)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(40)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(40)"                  LOC = "M3"  |> [Replay.ucf(308)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(308)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(40)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(308)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(40)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(27)"                  LOC =
+   "M4"  |> [Replay.ucf(309)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(27)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(27)"                  LOC = "M4"  |> [Replay.ucf(309)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(309)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(27)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(309)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(27)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(26)"                  LOC =
+   "M5"  |> [Replay.ucf(310)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(26)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(26)"                  LOC = "M5"  |> [Replay.ucf(310)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(310)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(26)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(310)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(26)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(25)"                  LOC =
+   "M6"  |> [Replay.ucf(311)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(25)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(25)"                  LOC = "M6"  |> [Replay.ucf(311)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(311)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(25)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(311)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(25)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(24)"                  LOC =
+   "L1"  |> [Replay.ucf(312)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(24)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(24)"                  LOC = "L1"  |> [Replay.ucf(312)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(312)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(24)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(312)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(24)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(23)"                  LOC =
+   "L2"  |> [Replay.ucf(313)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(23)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(23)"                  LOC = "L2"  |> [Replay.ucf(313)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(313)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(23)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(313)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(23)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(22)"                  LOC =
+   "L3"  |> [Replay.ucf(314)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(22)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(22)"                  LOC = "L3"  |> [Replay.ucf(314)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(314)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(22)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(314)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(22)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(21)"                  LOC =
+   "L4"  |> [Replay.ucf(315)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(21)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(21)"                  LOC = "L4"  |> [Replay.ucf(315)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(315)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(21)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(315)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(21)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(20)"                  LOC =
+   "L5"  |> [Replay.ucf(317)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(20)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(20)"                  LOC = "L5"  |> [Replay.ucf(317)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(317)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(20)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(317)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(20)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(19)"                  LOC =
+   "L6"  |> [Replay.ucf(318)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(19)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(19)"                  LOC = "L6"  |> [Replay.ucf(318)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(318)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(19)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(318)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(19)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(18)"                  LOC =
+   "K3"  |> [Replay.ucf(320)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(18)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(18)"                  LOC = "K3"  |> [Replay.ucf(320)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(320)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(18)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(320)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(18)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(17)"                  LOC =
+   "K4"  |> [Replay.ucf(321)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(17)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(17)"                  LOC = "K4"  |> [Replay.ucf(321)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(321)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(17)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(321)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(17)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(16)"                  LOC =
+   "K5"  |> [Replay.ucf(322)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(16)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(16)"                  LOC = "K5"  |> [Replay.ucf(322)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(322)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(16)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(322)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(16)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(44)"                  LOC =
+   "K6"  |> [Replay.ucf(323)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(44)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(44)"                  LOC = "K6"  |> [Replay.ucf(323)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(323)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(44)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(323)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(44)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(45)"                  LOC =
+   "J1"  |> [Replay.ucf(326)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(45)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(45)"                  LOC = "J1"  |> [Replay.ucf(326)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(326)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(45)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(326)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(45)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(46)"                  LOC =
+   "J2"  |> [Replay.ucf(327)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(46)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(46)"                  LOC = "J2"  |> [Replay.ucf(327)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(327)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(46)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(327)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(46)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(47)"                  LOC =
+   "J4"  |> [Replay.ucf(328)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(47)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(47)"                  LOC = "J4"  |> [Replay.ucf(328)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(328)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(47)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(328)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(47)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(48)"                  LOC =
+   "J5"  |> [Replay.ucf(329)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(48)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(48)"                  LOC = "J5"  |> [Replay.ucf(329)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(329)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(48)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(329)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(48)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(49)"                  LOC =
+   "H1"  |> [Replay.ucf(332)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(49)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(49)"                  LOC = "H1"  |> [Replay.ucf(332)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(332)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(49)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(332)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(49)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(50)"                  LOC =
+   "H2"  |> [Replay.ucf(333)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(50)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(50)"                  LOC = "H2"  |> [Replay.ucf(333)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(333)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(50)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(333)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(50)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(51)"                  LOC =
+   "H3"  |> [Replay.ucf(335)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(51)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(51)"                  LOC = "H3"  |> [Replay.ucf(335)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(335)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(51)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(335)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(51)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(52)"                  LOC =
+   "H4"  |> [Replay.ucf(336)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(52)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(52)"                  LOC = "H4"  |> [Replay.ucf(336)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(336)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(52)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(336)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(52)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(53)"                  LOC =
+   "H5"  |> [Replay.ucf(337)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(53)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(53)"                  LOC = "H5"  |> [Replay.ucf(337)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(337)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(53)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(337)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(53)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(54)"                  LOC =
+   "H6"  |> [Replay.ucf(338)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(54)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(54)"                  LOC = "H6"  |> [Replay.ucf(338)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(338)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(54)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(338)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(54)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(39)"                  LOC =
+   "G3"  |> [Replay.ucf(340)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(39)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(39)"                  LOC = "G3"  |> [Replay.ucf(340)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(340)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(39)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(340)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(39)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(38)"                  LOC =
+   "G4"  |> [Replay.ucf(341)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(38)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(38)"                  LOC = "G4"  |> [Replay.ucf(341)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(341)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(38)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(341)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(38)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(37)"                  LOC =
+   "G5"  |> [Replay.ucf(342)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(37)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(37)"                  LOC = "G5"  |> [Replay.ucf(342)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(342)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(37)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(342)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(37)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(36)"                  LOC =
+   "G6"  |> [Replay.ucf(344)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(36)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(36)"                  LOC = "G6"  |> [Replay.ucf(344)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(344)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(36)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(344)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(36)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(35)"                  LOC =
+   "F1"  |> [Replay.ucf(345)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(35)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(35)"                  LOC = "F1"  |> [Replay.ucf(345)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(345)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(35)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(345)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(35)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(34)"                  LOC =
+   "F2"  |> [Replay.ucf(346)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(34)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(34)"                  LOC = "F2"  |> [Replay.ucf(346)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(346)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(34)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(346)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(34)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(33)"                  LOC =
+   "E1"  |> [Replay.ucf(349)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(33)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(33)"                  LOC = "E1"  |> [Replay.ucf(349)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(349)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(33)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(349)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(33)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(32)"                  LOC =
+   "E2"  |> [Replay.ucf(350)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(32)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(32)"                  LOC = "E2"  |> [Replay.ucf(350)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(350)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(32)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(350)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(32)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(31)"                  LOC =
+   "E3"  |> [Replay.ucf(351)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(31)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(31)"                  LOC = "E3"  |> [Replay.ucf(351)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(351)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(31)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(351)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(31)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(30)"                  LOC =
+   "E4"  |> [Replay.ucf(353)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(30)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(30)"                  LOC = "E4"  |> [Replay.ucf(353)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(353)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(30)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(353)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(30)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(29)"                  LOC =
+   "D1"  |> [Replay.ucf(354)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(29)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(29)"                  LOC = "D1"  |> [Replay.ucf(354)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(354)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(29)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(354)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(29)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_IO(28)"                  LOC =
+   "D2"  |> [Replay.ucf(355)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_IO(28)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_IO(28)"                  LOC = "D2"  |> [Replay.ucf(355)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(355)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_IO(28)"' because those design objects do not contain
+   or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(355)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_IO(28)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <NET "b_Aux_IO(39)"              LOC =
+   "C1"  |> [Replay.ucf(358)]: This constraint cannot be distributed from the
+   design objects matching 'NET "b_Aux_IO(39)"' because those design objects do
+   not contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem - A target design object for the Locate constraint
+   '<NET "b_Aux_IO(39)"              LOC = "C1"  |> [Replay.ucf(358)]' could not
+   be found and so the Locate constraint will be removed.
+
+WARNING:ConstraintSystem:119 - Constraint <IOSTANDARD = LVTTL |>
+   [Replay.ucf(358)]: This constraint cannot be distributed from the design
+   objects matching 'NET "b_Aux_IO(39)"' because those design objects do not
+   contain or drive any instances of the correct type.
+
+WARNING:ConstraintSystem:119 - Constraint <DRIVE = 8;> [Replay.ucf(358)]: This
+   constraint cannot be distributed from the design objects matching 'NET
+   "b_Aux_IO(39)"' because those design objects do not contain or drive any
+   instances of the correct type.
+
+INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
+   'TS03', was traced into DCM_SP instance u_a_dcm. The following new TNM groups
+   and period specifications were generated at the DCM_SP output(s): 
+   CLK0: <TIMESPEC TS_u_ClockGen_clk_a_dcm_0 = PERIOD "u_ClockGen_clk_a_dcm_0"
+   TS03 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
+   'TS03', was traced into DCM_SP instance u_a_dcm. The following new TNM groups
+   and period specifications were generated at the DCM_SP output(s): 
+   CLK90: <TIMESPEC TS_u_ClockGen_clk_a_dcm_90 = PERIOD
+   "u_ClockGen_clk_a_dcm_90" TS03 PHASE 2.3475 ns HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
+   'TS03', was traced into DCM_SP instance u_a_dcm. The following new TNM groups
+   and period specifications were generated at the DCM_SP output(s): 
+   CLKDV: <TIMESPEC TS_u_ClockGen_clk_a_dcm_div = PERIOD
+   "u_ClockGen_clk_a_dcm_div" TS03 * 4 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'clk_a_grp', used in period specification
+   'TS03', was traced into DCM_SP instance phase_ctrl.u_a2_dcm. The following
+   new TNM groups and period specifications were generated at the DCM_SP
+   output(s): 
+   CLK0: <TIMESPEC TS_u_ClockGen_clk_a2_dcm_0 = PERIOD "u_ClockGen_clk_a2_dcm_0"
+   TS03 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'clk_b_grp', used in period specification
+   'TS02', was traced into DCM_SP instance u_b_dcm. The following new TNM groups
+   and period specifications were generated at the DCM_SP output(s): 
+   CLK0: <TIMESPEC TS_u_ClockGen_clk_b_dcm_0 = PERIOD "u_ClockGen_clk_b_dcm_0"
+   TS02 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'clk_c_grp', used in period specification
+   'TS01', was traced into DCM_SP instance u_c_dcm. The following new TNM groups
+   and period specifications were generated at the DCM_SP output(s): 
+   CLK0: <TIMESPEC TS_u_ClockGen_clk_c_dcm_0 = PERIOD "u_ClockGen_clk_c_dcm_0"
+   TS01 HIGH 50%>
+
+INFO:ConstraintSystem:178 - TNM 'clk_c_grp', used in period specification
+   'TS01', was traced into DCM_SP instance u_c_dcm. The following new TNM groups
+   and period specifications were generated at the DCM_SP output(s): 
+   CLK90: <TIMESPEC TS_u_ClockGen_clk_c_dcm_90 = PERIOD
+   "u_ClockGen_clk_c_dcm_90" TS01 PHASE 9.245 ns HIGH 50%>
+
+Done...
+
+INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
+   u_a_dcm to 9.390000 ns based on the period specification (<TIMESPEC TS03 =
+   PERIOD : clk_a_grp :  9.39 ;> [Replay.ucf(16)]).
+INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
+   u_b_dcm to 20.130000 ns based on the period specification (<TIMESPEC TS02 =
+   PERIOD : clk_b_grp : 20.13 ;> [Replay.ucf(17)]).
+INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
+   u_c_dcm to 36.980000 ns based on the period specification (<TIMESPEC TS01 =
+   PERIOD : clk_c_grp : 36.98 ;> [Replay.ucf(18)]).
+INFO:NgdBuild:1222 - Setting CLKIN_PERIOD attribute associated with DCM instance
+   phase_ctrl.u_a2_dcm to 9.390000 ns based on the period specification
+   (<TIMESPEC TS03 = PERIOD : clk_a_grp :  9.39 ;> [Replay.ucf(16)]).
+Checking expanded design ...
+WARNING:NgdBuild:452 - logical net 'N207' has no driver
+WARNING:NgdBuild:452 - logical net 'N228' has no driver
+WARNING:NgdBuild:452 - logical net 'N252' has no driver
+WARNING:NgdBuild:452 - logical net 'N253' has no driver
+WARNING:NgdBuild:452 - logical net 'N254' has no driver
+WARNING:NgdBuild:452 - logical net 'N255' has no driver
+WARNING:NgdBuild:452 - logical net 'N256' has no driver
+WARNING:NgdBuild:452 - logical net 'N257' has no driver
+WARNING:NgdBuild:452 - logical net 'N258' has no driver
+WARNING:NgdBuild:452 - logical net 'N259' has no driver
+WARNING:NgdBuild:452 - logical net 'N260' has no driver
+WARNING:NgdBuild:452 - logical net 'N261' has no driver
+WARNING:NgdBuild:452 - logical net 'N262' has no driver
+WARNING:NgdBuild:452 - logical net 'N263' has no driver
+WARNING:NgdBuild:452 - logical net 'N264' has no driver
+WARNING:NgdBuild:452 - logical net 'N265' has no driver
+WARNING:NgdBuild:452 - logical net 'N266' has no driver
+WARNING:NgdBuild:452 - logical net 'N267' has no driver
+WARNING:NgdBuild:452 - logical net 'cfg_static<0>' has no driver
+WARNING:NgdBuild:452 - logical net 'cfg_static<1>' has no driver
+WARNING:NgdBuild:452 - logical net 'cfg_static<2>' has no driver
+WARNING:NgdBuild:452 - logical net 'cfg_static<3>' has no driver
+WARNING:NgdBuild:452 - logical net 'cfg_static<4>' has no driver
+WARNING:NgdBuild:452 - logical net 'cfg_static<5>' has no driver
+WARNING:NgdBuild:452 - logical net 'hp_ddr_taken' has no driver
+WARNING:NgdBuild:452 - logical net 'hp_ddr_we' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_butn<0>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_butn<1>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_butn<2>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<0>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<10>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<11>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<1>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<2>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<3>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<4>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<5>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<6>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<7>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<8>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posx<9>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<0>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<10>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<11>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<1>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<2>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<3>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<4>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<5>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<6>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<7>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<8>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_posy<9>' has no driver
+WARNING:NgdBuild:452 - logical net 'ms_we' has no driver
+WARNING:NgdBuild:452 - logical net 'phy_audio_taken' has no driver
+WARNING:NgdBuild:452 - logical net 'rst_capture' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Video/o_drive_scl_low' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/i_Joy_A<5>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/i_Joy_B<5>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<10>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<11>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<12>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<13>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<14>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<15>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<8>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/matrix_out<9>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_act_h' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_act_v' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_sof' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_dig_sol' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_v_oddline' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/o_Vid_Timing_v_pix<0>' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/RAM_ADDR<16>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/RAM_ADDR<17>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/RAM_ADDR<18>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<14>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<16>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<17>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<18>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<19>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<20>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ROM_ADDR<21>' has no
+   driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/SDRAM_READ_ENABLE' has
+   no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/SDRAM_WIDTH_16bit_ACCESS' has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/ZPU_16BIT_WRITE_ENABLE'
+   has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<1>'
+   has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<2>'
+   has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<3>'
+   has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<4>'
+   has no driver
+WARNING:NgdBuild:452 - logical net 'u_Core/atari800core/pokey2/keyboard_scan<5>'
+   has no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<0>' has no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<1>' has no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<2>' has no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<3>' has no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<4>' has no driver
+WARNING:NgdBuild:452 - logical net
+   'u_Core/atari800core/zpu_config1/uart1/keyboard_scan<5>' has no driver
+WARNING:NgdBuild:470 - bidirect pad net 'b_IO<0>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'b_IO<1>' has no legal driver
+WARNING:NgdBuild:470 - bidirect pad net 'b_IO<2>' has no legal driver
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+NGDBUILD Design Results Summary:
+  Number of errors:     0
+  Number of warnings: 334
+
+Writing NGD file "Replay.ngd" ...
+Total REAL time to NGDBUILD completion:  46 sec
+Total CPU time to NGDBUILD completion:   46 sec
+
+Writing NGDBUILD log file "Replay.bld"...
+
+NGDBUILD done.
+Starting Map...
+Release 14.7 - Map P.20131013 (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Using target part "3s1600efg320-4".
+Mapping design into LUTs...
+WARNING:MapLib:701 - Signal b_Video_SPC connected to top level port b_Video_SPC
+   has been removed.
+WARNING:MapLib:701 - Signal b_IO<3> connected to top level port b_IO<3> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<4> connected to top level port b_IO<4> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<5> connected to top level port b_IO<5> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<6> connected to top level port b_IO<6> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<7> connected to top level port b_IO<7> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<8> connected to top level port b_IO<8> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<9> connected to top level port b_IO<9> has been
+   removed.
+WARNING:MapLib:701 - Signal b_IO<10> connected to top level port b_IO<10> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<11> connected to top level port b_IO<11> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<12> connected to top level port b_IO<12> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<13> connected to top level port b_IO<13> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<14> connected to top level port b_IO<14> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<15> connected to top level port b_IO<15> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<16> connected to top level port b_IO<16> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<17> connected to top level port b_IO<17> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<18> connected to top level port b_IO<18> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<19> connected to top level port b_IO<19> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<20> connected to top level port b_IO<20> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<21> connected to top level port b_IO<21> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<22> connected to top level port b_IO<22> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<23> connected to top level port b_IO<23> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<24> connected to top level port b_IO<24> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<25> connected to top level port b_IO<25> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<26> connected to top level port b_IO<26> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<27> connected to top level port b_IO<27> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<28> connected to top level port b_IO<28> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<29> connected to top level port b_IO<29> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<30> connected to top level port b_IO<30> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<31> connected to top level port b_IO<31> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<32> connected to top level port b_IO<32> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<33> connected to top level port b_IO<33> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<34> connected to top level port b_IO<34> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<35> connected to top level port b_IO<35> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<36> connected to top level port b_IO<36> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<37> connected to top level port b_IO<37> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<38> connected to top level port b_IO<38> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<39> connected to top level port b_IO<39> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<40> connected to top level port b_IO<40> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<41> connected to top level port b_IO<41> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<42> connected to top level port b_IO<42> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<43> connected to top level port b_IO<43> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<44> connected to top level port b_IO<44> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<45> connected to top level port b_IO<45> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<46> connected to top level port b_IO<46> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<47> connected to top level port b_IO<47> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<48> connected to top level port b_IO<48> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<49> connected to top level port b_IO<49> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<50> connected to top level port b_IO<50> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<51> connected to top level port b_IO<51> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<52> connected to top level port b_IO<52> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<53> connected to top level port b_IO<53> has
+   been removed.
+WARNING:MapLib:701 - Signal b_IO<54> connected to top level port b_IO<54> has
+   been removed.
+WARNING:MapLib:701 - Signal b_Aux_IO<36> connected to top level port
+   b_Aux_IO<36> has been removed.
+WARNING:MapLib:701 - Signal b_Aux_IO<37> connected to top level port
+   b_Aux_IO<37> has been removed.
+WARNING:MapLib:701 - Signal b_Aux_IO<38> connected to top level port
+   b_Aux_IO<38> has been removed.
+WARNING:MapLib:701 - Signal b_Aux_IO<39> connected to top level port
+   b_Aux_IO<39> has been removed.
+WARNING:MapLib:701 - Signal b_Clk_Aux connected to top level port b_Clk_Aux has
+   been removed.
+WARNING:MapLib:701 - Signal b_2V5_IO_1 connected to top level port b_2V5_IO_1
+   has been removed.
+WARNING:MapLib:701 - Signal b_2V5_IO_0 connected to top level port b_2V5_IO_0
+   has been removed.
+WARNING:MapLib:701 - Signal o_Clk_68K connected to top level port o_Clk_68K has
+   been removed.
+WARNING:LIT:176 - Clock buffer is designated to drive clock loads. BUFGMUX
+   symbol "u_ClockGen/physical_group_o_clk_ctl/u_dcm_a_clk_div_bufg" (output
+   signal=clk_ctl) has a mix of clock and non-clock loads. The non-clock loads
+   are:
+   Pin PSCLK of u_ClockGen/physical_group_clk_a2_dcm_0/phase_ctrl.u_a2_dcm
+Writing file Replay.ngm...
+Running directed packing...
+WARNING:Pack:1237 - The register u_Core/atari800core/pia1/CB2_output_reg failed
+   to join the output side of an I/O component. Symbol
+   u_Core/atari800core/pia1/CB2_output_reg is not under the same hierarchy
+   region as symbol o_RS232_RTS_OBUF. There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Core/atari800core/pia1 in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_Video/u_I2C/o_drive_sda_low failed to join
+   the output side of an I/O component. Symbol u_Video/u_I2C/o_drive_sda_low is
+   not under the same hierarchy region as symbol b_SDA_IOBUF/OBUFT. There are
+   three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Video/u_I2C in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_0_1 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_0_1 is not under the same
+   hierarchy region as symbol b_Aux_IO_0_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_1_1 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_1_1 is not under the same
+   hierarchy region as symbol b_Aux_IO_1_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_rd failed to join the output side
+   of an I/O component. Symbol u_FileIO/mem_rd is not under the same hierarchy
+   region as symbol b_Aux_IO_2_OBUF. There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_rd failed to join the output side
+   of an I/O component. Symbol u_FileIO/mem_rd is not under the same hierarchy
+   region as symbol b_Aux_IO_3_OBUF. There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_18 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_18 is not under the same
+   hierarchy region as symbol b_Aux_IO_6_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1239 - The register u_FileIO/u_spi/din_0 failed to join the input
+   side of an I/O component. Symbol u_FileIO/u_spi/din_0 is not under the same
+   hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three ways to fix
+   the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO/u_spi in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1239 - The register u_FileIO/u_spi/o_rxdata_0 failed to join the
+   input side of an I/O component. Symbol u_FileIO/u_spi/o_rxdata_0 is not under
+   the same hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three
+   ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO/u_spi in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1239 - The register u_Syscon/u_spi/din_0 failed to join the input
+   side of an I/O component. Symbol u_Syscon/u_spi/din_0 is not under the same
+   hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three ways to fix
+   the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Syscon/u_spi in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1239 - The register u_Syscon/u_spi/o_rxdata_0 failed to join the
+   input side of an I/O component. Symbol u_Syscon/u_spi/o_rxdata_0 is not under
+   the same hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three
+   ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Syscon/u_spi in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1239 - The register u_Syscon/u_spi/o_rxcmd_0 failed to join the
+   input side of an I/O component. Symbol u_Syscon/u_spi/o_rxcmd_0 is not under
+   the same hierarchy region as symbol b_FPGA_SPI_MOSI_IBUF. There are three
+   ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Syscon/u_spi in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_JoyPS2/u_PSA/ps2_drive_clk_low failed to join
+   the output side of an I/O component. Symbol u_JoyPS2/u_PSA/ps2_drive_clk_low
+   is not under the same hierarchy region as symbol b_PS2A_Clk_IOBUF/OBUFT.
+   There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_JoyPS2/u_PSA in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_JoyPS2/u_PSB/ps2_drive_clk_low failed to join
+   the output side of an I/O component. Symbol u_JoyPS2/u_PSB/ps2_drive_clk_low
+   is not under the same hierarchy region as symbol b_PS2B_Clk_IOBUF/OBUFT.
+   There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_JoyPS2/u_PSB in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_Syscon/o_vbl failed to join the output side
+   of an I/O component. Symbol u_Syscon/o_vbl is not under the same hierarchy
+   region as symbol o_SSC_RD_OBUF. There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Syscon in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_8 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_8 is not under the same
+   hierarchy region as symbol b_Aux_IO_20_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_0_1 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_0_1 is not under the same
+   hierarchy region as symbol b_Aux_IO_12_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_9 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_9 is not under the same
+   hierarchy region as symbol b_Aux_IO_21_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_1_1 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_1_1 is not under the same
+   hierarchy region as symbol b_Aux_IO_13_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_10 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_10 is not under the same
+   hierarchy region as symbol b_Aux_IO_22_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_2_1 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_2_1 is not under the same
+   hierarchy region as symbol b_Aux_IO_14_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_11 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_11 is not under the same
+   hierarchy region as symbol b_Aux_IO_23_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_3_1 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_3_1 is not under the same
+   hierarchy region as symbol b_Aux_IO_15_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_12 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_12 is not under the same
+   hierarchy region as symbol b_Aux_IO_24_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_4 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_4 is not under the same
+   hierarchy region as symbol b_Aux_IO_16_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_13 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_13 is not under the same
+   hierarchy region as symbol b_Aux_IO_25_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_5 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_5 is not under the same
+   hierarchy region as symbol b_Aux_IO_17_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_14 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_14 is not under the same
+   hierarchy region as symbol b_Aux_IO_26_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_6 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_6 is not under the same
+   hierarchy region as symbol b_Aux_IO_18_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_15 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_15 is not under the same
+   hierarchy region as symbol b_Aux_IO_27_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_FileIO/mem_addr_7 failed to join the output
+   side of an I/O component. Symbol u_FileIO/mem_addr_7 is not under the same
+   hierarchy region as symbol b_Aux_IO_19_OBUF. There are three ways to fix the
+   problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_FileIO in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_Video/u_I2C/o_drive_spc_low failed to join
+   the output side of an I/O component. Symbol u_Video/u_I2C/o_drive_spc_low is
+   not under the same hierarchy region as symbol b_Video_SPC_OBUFT. There are
+   three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Video/u_I2C in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_Video/u_I2C/o_drive_spd_low failed to join
+   the output side of an I/O component. Symbol u_Video/u_I2C/o_drive_spd_low is
+   not under the same hierarchy region as symbol b_Video_SPD_IOBUF/OBUFT. There
+   are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_Video/u_I2C in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_JoyPS2/u_PSA/ps2_drive_data_low failed to
+   join the output side of an I/O component. Symbol
+   u_JoyPS2/u_PSA/ps2_drive_data_low is not under the same hierarchy region as
+   symbol b_PS2A_Data_IOBUF/OBUFT. There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_JoyPS2/u_PSA in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:1237 - The register u_JoyPS2/u_PSB/ps2_drive_data_low failed to
+   join the output side of an I/O component. Symbol
+   u_JoyPS2/u_PSB/ps2_drive_data_low is not under the same hierarchy region as
+   symbol b_PS2B_Data_IOBUF/OBUFT. There are three ways to fix the problem:
+   1. Put both symbols under the same hierarchy region and process the design.
+   If the I/O buffer is being inferred by the synthesis tool, it is suggested to
+   code I/O registers on the top level of code. If this can not be done, it is
+   suggested to instantiate the proper I/O buffer in the lower level of code and
+   disable I/O buffer inference for that port in the design.
+   2. Remove KEEP_HIERARCHY constraint or add KEEP_HIERARCHY = FALSE to block
+   u_JoyPS2/u_PSB in the UCF file.
+   3. Run map with the option -ignore_keep_hierarchy (TCL/ProjNav command:
+   process set "Allow Logic Optimization Across Hierarchy" TRUE). This option
+   will dissolve all hierarchy in the design.
+
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf2_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer2/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf1_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer1/Mmux_count_next6_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf1_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer1/Mmux_count_next9_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf1_next<5>11 failed to merge with F5
+   multiplexer
+   u_Core/atari800core/zpu_config1/uart1/timer1/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf2_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer2/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf2_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer2/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf0_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer0/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001081 failed to merge
+   with F5 multiplexer
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom0000651_7_f5_f5.  There is
+   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/cpu6502/CPU_ENABLE_RDY1 failed to merge with F5
+   multiplexer u_Core/atari800core/cpu6502/cpu_6502_peter/nmiReg_not0001_f5. 
+   Two or more symbols belong to different KEEP_HIERARCHY boundaries and can not
+   be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf3_next<5>11 failed to merge with F5
+   multiplexer
+   u_Core/atari800core/zpu_config1/uart1/timer3/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf0_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer0/Mmux_count_next6_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf0_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer0/Mmux_count_next9_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf2_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer2/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf3_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer3/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf3_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer3/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf1_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer1/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf1_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer1/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001631 failed to merge
+   with F5 multiplexer
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00002451_8_f5_0_f5.  There
+   is a conflict for the FXMUX.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf1_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer1/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/antic1/row_count_next<3>1 failed to merge with F5
+   multiplexer
+   u_Core/atari800core/antic1/antic_counter_row_count/Mcount_value_reg_xor<3>1_f
+   5.  Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/antic1/refresh_count_next<0>1 failed to merge with F5
+   multiplexer
+   u_Core/atari800core/antic1/antic_counter_refresh_count/Mcount_value_reg_xor<3
+   >1_f5.  Two or more symbols belong to different KEEP_HIERARCHY boundaries and
+   can not be merged into the same component.  The design will exhibit
+   suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf2_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer2/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf2_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer2/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf0_next<5>11 failed to merge with F5
+   multiplexer
+   u_Core/atari800core/zpu_config1/uart1/timer0/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf0_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer0/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf0_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer0/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf3_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer3/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf3_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer3/Mmux_count_next6_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf3_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer3/Mmux_count_next9_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/cpu6502/cpu_6502_peter/nineBits_mux0000<0>42 failed to
+   merge with F5 multiplexer
+   u_Core/atari800core/cpu6502/cpu_6502_peter/varZ_mux000128_f5.  There is a
+   conflict for the FXMUX.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf2_next<5>11 failed to merge with F5
+   multiplexer
+   u_Core/atari800core/zpu_config1/uart1/timer2/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom0000105 failed to merge
+   with F5 multiplexer
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001811_5_f5_f5.  There is
+   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf1_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer1/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf1_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer1/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf1_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer1/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf2_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer2/Mmux_count_next6_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/zpu_config1/uart1/audf2_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/zpu_config1/uart1/timer2/Mmux_count_next9_f5.
+    Two or more symbols belong to different KEEP_HIERARCHY boundaries and can
+   not be merged into the same component.  The design will exhibit suboptimal
+   timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf3_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer3/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001551 failed to merge
+   with F5 multiplexer
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001921_5_f5_f5.  There is
+   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom0000571 failed to merge
+   with F5 multiplexer
+   u_Core/atari800core/palette1/Mrom_ATARI_COLOUR_rom00001001_5_f5_1.  There is
+   a conflict for the FXMUX.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf0_next<5>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer0/Mmux_count_next18_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf3_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer3/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey1/audf3_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey1/timer3/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf0_next<1>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer0/Mmux_count_next6_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+WARNING:Pack:266 - The function generator
+   u_Core/atari800core/pokey2/audf0_next<2>11 failed to merge with F5
+   multiplexer u_Core/atari800core/pokey2/timer0/Mmux_count_next9_f5.  Two or
+   more symbols belong to different KEEP_HIERARCHY boundaries and can not be
+   merged into the same component.  The design will exhibit suboptimal timing.
+Running delay-based LUT packing...
+Running related packing...
+Updating timing models...
+Writing design file "Replay.ncd"...
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<0>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<1>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<2>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<3>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<4>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<5>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<6>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<7>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<8>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<9>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Joy_A<5>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Joy_B<5>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<10>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<11>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<12>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<20>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<13>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<21>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<14>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<22>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<15>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<16>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<17>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<18>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<19>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <b_IO<0>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <b_IO<1>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <b_IO<2>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Video_Int_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_RS232_CTS_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/gtia1/counter_hpos/GLOBAL_LOGIC0> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/antic1/antic_counter_line_buffer/GLOBAL_LOGIC0> is
+   incomplete. The signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/pokey1/GLOBAL_LOGIC0> is incomplete. The signal does not
+   drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/pokey2/GLOBAL_LOGIC0> is incomplete. The signal does not
+   drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/zpu_config1/uart1/GLOBAL_LOGIC0> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<0> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<1> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<2> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<3> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<20> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<12> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<21> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<13> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<30> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<22> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<14> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<31> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<23> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<15> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<32> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<24> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<16> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<33> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<25> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<17> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<34> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<26> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<18> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<35> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<27> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<19> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<28> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<29> is set but the tri state is not configured. 
+
+Design Summary:
+Number of errors:      0
+Number of warnings:  205
+Logic Utilization:
+  Number of Slice Flip Flops:         5,682 out of  29,504   19%
+  Number of 4 input LUTs:            21,508 out of  29,504   72%
+Logic Distribution:
+  Number of occupied Slices:         13,191 out of  14,752   89%
+    Number of Slices containing only related logic:  13,191 out of  13,191 100%
+    Number of Slices containing unrelated logic:          0 out of  13,191   0%
+      *See NOTES below for an explanation of the effects of unrelated logic.
+  Total Number of 4 input LUTs:      22,011 out of  29,504   74%
+    Number used as logic:            12,475
+    Number used as a route-thru:        503
+    Number used for Dual Port RAMs:   6,772
+      (Two LUTs used per Dual Port RAM)
+    Number used for 32x1 RAMs:        2,120
+      (Two LUTs used per 32x1 RAM)
+    Number used as Shift registers:     141
+
+  The Slice Logic Distribution report is not meaningful if the design is
+  over-mapped for a non-slice resource or if Placement fails.
+
+  Number of bonded IOBs:                167 out of     250   66%
+    IOB Flip Flops:                      30
+  Number of IDDR2s used:                 16
+    Number of DDR_ALIGNMENT = NONE       16
+    Number of DDR_ALIGNMENT = C0          0
+    Number of DDR_ALIGNMENT = C1          0
+  Number of ODDR2s used:                 54
+    Number of DDR_ALIGNMENT = NONE       54
+    Number of DDR_ALIGNMENT = C0          0
+    Number of DDR_ALIGNMENT = C1          0
+  Number of RAMB16s:                     36 out of      36  100%
+  Number of BUFGMUXs:                     8 out of      24   33%
+  Number of DCMs:                         4 out of       8   50%
+  Number of MULT18X18SIOs:                4 out of      36   11%
+
+  Number of RPM macros:            1
+Average Fanout of Non-Clock Nets:                4.87
+
+Peak Memory Usage:  312 MB
+Total REAL time to MAP completion:  44 secs 
+Total CPU time to MAP completion:   44 secs 
+
+NOTES:
+
+   Related logic is defined as being logic that shares connectivity - e.g. two
+   LUTs are "related" if they share common inputs.  When assembling slices,
+   Map gives priority to combine logic that is related.  Doing so results in
+   the best timing performance.
+
+   Unrelated logic shares no connectivity.  Map will only begin packing
+   unrelated logic into a slice once 99% of the slices are occupied through
+   related logic packing.
+
+   Note that once logic distribution reaches the 99% level through related
+   logic packing, this does not mean the device is completely utilized.
+   Unrelated logic packing will then begin, continuing until all usable LUTs
+   and FFs are occupied.  Depending on your timing budget, increased levels of
+   unrelated logic packing may adversely affect the overall timing performance
+   of your design.
+
+Mapping completed.
+See MAP report file "Replay.mrp" for details.
+Starting Place & Route...
+Release 14.7 - par P.20131013 (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+
+
+Constraints file: Replay.pcf.
+Loading device for application Rf_Device from file '3s1600e.nph' in environment
+/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.
+   "Replay_Top" is an NCD, version 3.2, device xc3s1600e, package fg320, speed -4
+INFO:Par:469 - Although the Overall Effort Level (-ol) for this implementation has been set to Standard, Placer will run
+   at effort level High. To override this, please set the Placer Effort Level (-pl) to Standard.
+
+Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
+Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
+
+
+Device speed data version:  "PRODUCTION 1.27 2013-10-13".
+
+
+Design Summary Report:
+
+ Number of External IOBs                         167 out of 250    66%
+
+   Number of External Input IOBs                 50
+
+      Number of External Input IBUFs             50
+        Number of LOCed External Input IBUFs     50 out of 50    100%
+
+
+   Number of External Output IOBs                93
+
+      Number of External Output IOBs             93
+        Number of LOCed External Output IOBs     93 out of 93    100%
+
+
+   Number of External Bidir IOBs                 24
+
+      Number of External Bidir IOBs              24
+        Number of LOCed External Bidir IOBs      24 out of 24    100%
+
+
+   Number of BUFGMUXs                        8 out of 24     33%
+      Number of LOCed BUFGMUXs               7 out of 8      87%
+
+   Number of DCMs                            4 out of 8      50%
+      Number of LOCed DCMs                   4 out of 4     100%
+
+   Number of MULT18X18SIOs                   4 out of 36     11%
+   Number of RAMB16s                        36 out of 36    100%
+   Number of Slices                      13191 out of 14752  89%
+      Number of SLICEMs                   5087 out of 7376   68%
+
+
+
+Overall effort level (-ol):   Standard 
+Placer effort level (-pl):    High 
+Placer cost table entry (-t): 1
+Router effort level (-rl):    Standard 
+
+WARNING:Timing:3223 - Timing constraint PATH "TS_20_path" TIG; ignored during timing analysis.
+INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more information, see the TSI report.  Please
+   consult the Xilinx Command Line Tools User Guide for information on generating a TSI report.
+Starting initial Timing Analysis.  REAL time: 20 secs 
+Finished initial Timing Analysis.  REAL time: 23 secs 
+
+WARNING:Par:288 - The signal i_Aux_IP<0>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<1>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<2>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<3>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<4>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<5>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<6>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<7>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<8>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<9>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Joy_A<5>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Joy_B<5>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<10>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<11>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<12>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<20>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<13>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<21>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<14>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<22>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<15>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<16>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<17>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<18>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Aux_IP<19>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal b_IO<0>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal b_IO<1>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal b_IO<2>_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_Video_Int_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal i_RS232_CTS_IBUF has no load.  PAR will not attempt to route this signal.
+WARNING:Par:288 - The signal u_DDRCtrl/u_ddr_ctrl/u_datapath/dqs_ip<0> has no load.  PAR will not attempt to route this
+   signal.
+WARNING:Par:288 - The signal u_DDRCtrl/u_ddr_ctrl/u_datapath/dqs_ip<1> has no load.  PAR will not attempt to route this
+   signal.
+
+Starting Placer
+Total REAL time at the beginning of Placer: 23 secs 
+Total CPU  time at the beginning of Placer: 23 secs 
+
+Phase 1.1  Initial Placement Analysis
+Phase 1.1  Initial Placement Analysis (Checksum:6f14fc81) REAL time: 28 secs 
+
+Phase 2.7  Design Feasibility Check
+Phase 2.7  Design Feasibility Check (Checksum:6f14fc81) REAL time: 28 secs 
+
+Phase 3.31  Local Placement Optimization
+Phase 3.31  Local Placement Optimization (Checksum:6f14fc81) REAL time: 28 secs 
+
+Phase 4.2  Initial Clock and IO Placement
+
+..........
+WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
+   site pair.  The clock component <u_ClockGen/u_c_dcm> is placed at site <DCM_X1Y3>.  The clock IO/DCM site can be
+   paired if they are placed/locked in the same quadrant.  The IO component <ClK_C> is placed at site <D10>.  This will
+   not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the
+   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <u_ClockGen/ClK_C.PAD> allowing your design to continue.
+   This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
+   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
+   the design.
+WARNING:Place:1013 - A clock IOB / DCM component pair have been found that are not placed at an optimal clock IOB / DCM
+   site pair.  The clock component <u_ClockGen/phase_ctrl.u_a2_dcm> is placed at site <DCM_X1Y0>.  The clock IO/DCM site
+   can be paired if they are placed/locked in the same quadrant.  The IO component <ClK_A> is placed at site <IPAD244>. 
+   This will not allow the use of the fast path between the IO and the Clock buffer. This is normally an ERROR but the
+   CLOCK_DEDICATED_ROUTE constraint was applied on COMP.PIN <u_ClockGen/ClK_A.PAD> allowing your design to continue.
+   This constraint disables all clock placer rules related to the specified COMP.PIN. The use of this override is highly
+   discouraged as it may lead to very poor timing results. It is recommended that this error condition be corrected in
+   the design.
+Phase 4.2  Initial Clock and IO Placement (Checksum:675a3311) REAL time: 38 secs 
+
+Phase 5.30  Global Clock Region Assignment
+Phase 5.30  Global Clock Region Assignment (Checksum:675a3311) REAL time: 38 secs 
+
+Phase 6.36  Local Placement Optimization
+Phase 6.36  Local Placement Optimization (Checksum:675a3311) REAL time: 38 secs 
+
+Phase 7.8  Global Placement
+................................
+..........................................................................................................................
+.....................................
+..................................................................................................................
+.................................................
+................................................
+.................................
+..........................................
+Phase 7.8  Global Placement (Checksum:5eee4f94) REAL time: 4 mins 35 secs 
+
+Phase 8.5  Local Placement Optimization
+Phase 8.5  Local Placement Optimization (Checksum:5eee4f94) REAL time: 4 mins 36 secs 
+
+Phase 9.18  Placement Optimization
+Phase 9.18  Placement Optimization (Checksum:355031c8) REAL time: 5 mins 39 secs 
+
+Phase 10.5  Local Placement Optimization
+Phase 10.5  Local Placement Optimization (Checksum:355031c8) REAL time: 5 mins 40 secs 
+
+Total REAL time to Placer completion: 5 mins 43 secs 
+Total CPU  time to Placer completion: 5 mins 42 secs 
+Writing design to file Replay.ncd
+
+
+
+Starting Router
+
+
+Phase  1  : 108359 unrouted;      REAL time: 6 mins 23 secs 
+
+Phase  2  : 99316 unrouted;      REAL time: 6 mins 34 secs 
+
+Phase  3  : 30271 unrouted;      REAL time: 7 mins 10 secs 
+
+Phase  4  : 30355 unrouted; (Setup:5838, Hold:0, Component Switching Limit:0)     REAL time: 7 mins 33 secs 
+
+Phase  5  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 8 mins 43 secs 
+
+Updating file: Replay.ncd with current fully routed design.
+
+Phase  6  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 11 secs 
+
+Phase  7  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 9 mins 57 secs 
+
+Phase  8  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 10 mins 10 secs 
+
+Phase  9  : 0 unrouted; (Setup:7081, Hold:0, Component Switching Limit:0)     REAL time: 10 mins 10 secs 
+
+Phase 10  : 0 unrouted; (Setup:6386, Hold:0, Component Switching Limit:0)     REAL time: 10 mins 20 secs 
+WARNING:Route:455 - CLK Net:u_ClockGen/clk_c_ibuf may have excessive skew because 
+      1 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
+
+Total REAL time to Router completion: 10 mins 21 secs 
+Total CPU time to Router completion: 10 mins 20 secs 
+
+Partition Implementation Status
+-------------------------------
+
+  No Partitions were found in this design.
+
+-------------------------------
+
+Generating "PAR" statistics.
+
+**************************
+Generating Clock Report
+**************************
+
++---------------------+--------------+------+------+------------+-------------+
+|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
++---------------------+--------------+------+------+------------+-------------+
+|             clk_aud | BUFGMUX_X1Y10| No   |   32 |  0.192     |  0.549      |
++---------------------+--------------+------+------+------------+-------------+
+|             clk_ctl |  BUFGMUX_X1Y1|Yes   | 7403 |  0.507     |  0.768      |
++---------------------+--------------+------+------+------------+-------------+
+|             clk_vid | BUFGMUX_X2Y10|Yes   |  307 |  0.280     |  0.549      |
++---------------------+--------------+------+------+------------+-------------+
+|             clk_ram |  BUFGMUX_X2Y1|Yes   |  193 |  0.289     |  0.549      |
++---------------------+--------------+------+------+------------+-------------+
+|          clk_vid_90 | BUFGMUX_X2Y11|Yes   |    4 |  0.000     |  0.552      |
++---------------------+--------------+------+------+------------+-------------+
+|         clk_capture |  BUFGMUX_X2Y0|Yes   |   70 |  0.179     |  0.552      |
++---------------------+--------------+------+------+------------+-------------+
+|          clk_ram_90 |  BUFGMUX_X1Y0|Yes   |   54 |  0.179     |  0.552      |
++---------------------+--------------+------+------+------------+-------------+
+|             clk_spi | BUFGMUX_X1Y11|Yes   |   59 |  0.115     |  0.535      |
++---------------------+--------------+------+------+------------+-------------+
+|u_ClockGen/clk_c_ibu |              |      |      |            |             |
+|                   f |         Local|      |   11 |  0.150     |  1.839      |
++---------------------+--------------+------+------+------------+-------------+
+
+* Net Skew is the difference between the minimum and maximum routing
+only delays for the net. Note this is different from Clock Skew which
+is reported in TRCE timing report. Clock Skew is the difference between
+the minimum and maximum path delays which includes logic delays.
+
+* The fanout is the number of component pins not the individual BEL loads,
+for example SLICE loads not FF loads.
+
+Timing Score: 6386 (Setup: 6386, Hold: 0, Component Switching Limit: 0)
+
+WARNING:Par:468 - Your design did not meet timing.  The following are some suggestions to assist you to meet timing in
+   your design.
+
+   Review the timing report using Timing Analyzer (In ISE select "Post-Place &
+   Route Static Timing Report"). Go to the failing constraint(s) and evaluate the failing paths for each constraint.
+
+   Try the Design Goal and Strategies for Timing Performance(In ISE select Project -> Design Goals & Strategies) to
+   ensure the best options are set in the tools for timing closure.
+
+   Increase the PAR Effort Level setting to "high"
+
+   Use the Xilinx "SmartXplorer" script to try special combinations of
+   options known to produce very good results.
+
+   Visit the Xilinx technical support web at http://support.xilinx.com and go to
+   either "Troubleshoot->Tech Tips->Timing & Constraints" or "
+   TechXclusives->Timing Closure" for tips and suggestions for meeting timing
+   in your design.
+
+Number of Timing Constraints that were not applied: 4
+
+Asterisk (*) preceding a constraint indicates it was not met.
+   This may be due to a setup or hold violation.
+
+----------------------------------------------------------------------------------------------------------
+  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
+                                            |             |    Slack   | Achievable | Errors |    Score   
+----------------------------------------------------------------------------------------------------------
+* TS_u_ClockGen_clk_a_dcm_div = PERIOD TIME | SETUP       |    -0.436ns|    39.304ns|      32|        6386
+  GRP "u_ClockGen_clk_a_dcm_div" TS03 *     | HOLD        |     0.678ns|            |       0|           0
+       4 HIGH 50%                           |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  NET "u_ClockGen/clk_a_ibuf" MAXSKEW = 0.3 | NETSKEW     |     0.064ns|     0.236ns|       0|           0
+   ns                                       |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_u_ClockGen_clk_a_dcm_90 = PERIOD TIMEG | SETUP       |     0.236ns|     8.445ns|       0|           0
+  RP "u_ClockGen_clk_a_dcm_90" TS03         | HOLD        |     1.240ns|            |       0|           0
+   PHASE 2.3475 ns HIGH 50%                 |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_u_ClockGen_clk_a_dcm_0 = PERIOD TIMEGR | SETUP       |     0.278ns|     9.112ns|       0|           0
+  P "u_ClockGen_clk_a_dcm_0" TS03 HIGH      | HOLD        |     0.917ns|            |       0|           0
+      50%                                   |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_u_ClockGen_clk_a2_dcm_0 = PERIOD TIMEG | SETUP       |     0.606ns|     8.178ns|       0|           0
+  RP "u_ClockGen_clk_a2_dcm_0" TS03         | HOLD        |     0.928ns|            |       0|           0
+   HIGH 50%                                 |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS03 = PERIOD TIMEGRP "clk_a_grp" 9.39 ns | MINLOWPULSE |     4.590ns|     4.800ns|       0|           0
+   HIGH 50%                                 |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_i_FPGA_SPI_Clk = PERIOD TIMEGRP "i_FPG | SETUP       |     8.508ns|    12.984ns|       0|           0
+  A_SPI_Clk" 30 ns HIGH 50%                 | HOLD        |     0.960ns|            |       0|           0
+----------------------------------------------------------------------------------------------------------
+  TS02 = PERIOD TIMEGRP "clk_b_grp" 20.13 n | MINLOWPULSE |    10.130ns|    10.000ns|       0|           0
+  s HIGH 50%                                |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_u_ClockGen_clk_b_dcm_0 = PERIOD TIMEGR | SETUP       |    13.229ns|     6.901ns|       0|           0
+  P "u_ClockGen_clk_b_dcm_0" TS02 HIGH      | HOLD        |     1.367ns|            |       0|           0
+      50%                                   |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS_u_ClockGen_clk_c_dcm_0 = PERIOD TIMEGR | SETUP       |    14.051ns|    21.023ns|       0|           0
+  P "u_ClockGen_clk_c_dcm_0" TS01 HIGH      | HOLD        |     0.761ns|            |       0|           0
+      50%                                   |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS12 = MAXDELAY FROM TIMEGRP "FFS" TO TIM | MAXDELAY    |    15.749ns|    14.251ns|       0|           0
+  EGRP "PADS" 30 ns                         |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS11 = MAXDELAY FROM TIMEGRP "PADS" TO TI | SETUP       |    22.188ns|     7.812ns|       0|           0
+  MEGRP "FFS" 30 ns                         |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  TS01 = PERIOD TIMEGRP "clk_c_grp" 36.98 n | SETUP       |    33.315ns|     3.665ns|       0|           0
+  s HIGH 50%                                | HOLD        |     0.973ns|            |       0|           0
+                                            | MINLOWPULSE |    26.980ns|    10.000ns|       0|           0
+----------------------------------------------------------------------------------------------------------
+  TS_u_ClockGen_clk_c_dcm_90 = PERIOD TIMEG | MINPERIOD   |    35.384ns|     1.596ns|       0|           0
+  RP "u_ClockGen_clk_c_dcm_90" TS01         |             |            |            |        |            
+   PHASE 9.245 ns HIGH 50%                  |             |            |            |        |            
+----------------------------------------------------------------------------------------------------------
+  PATH "TS_22_path" TIG                     | SETUP       |         N/A|     6.220ns|     N/A|           0
+----------------------------------------------------------------------------------------------------------
+  PATH "TS_21_path" TIG                     | MAXDELAY    |         N/A|     5.001ns|     N/A|           0
+----------------------------------------------------------------------------------------------------------
+  PATH "TS_20_path" TIG                     | N/A         |         N/A|         N/A|     N/A|         N/A
+----------------------------------------------------------------------------------------------------------
+
+
+Derived Constraint Report
+Review Timing Report for more details on the following derived constraints.
+To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
+or "Run Timing Analysis" from Timing Analyzer (timingan).
+Derived Constraints for TS03
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS03                           |      9.390ns|      4.800ns|      9.826ns|            0|           32|            0|     16440849|
+| TS_u_ClockGen_clk_a_dcm_0     |      9.390ns|      9.112ns|          N/A|            0|            0|         3628|            0|
+| TS_u_ClockGen_clk_a_dcm_90    |      9.390ns|      8.445ns|          N/A|            0|            0|          104|            0|
+| TS_u_ClockGen_clk_a_dcm_div   |     37.560ns|     39.304ns|          N/A|           32|            0|     16436746|            0|
+| TS_u_ClockGen_clk_a2_dcm_0    |      9.390ns|      8.178ns|          N/A|            0|            0|          371|            0|
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+Derived Constraints for TS02
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS02                           |     20.130ns|     10.000ns|      6.901ns|            0|            0|            0|          364|
+| TS_u_ClockGen_clk_b_dcm_0     |     20.130ns|      6.901ns|          N/A|            0|            0|          364|            0|
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+Derived Constraints for TS01
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|                               |   Period    |       Actual Period       |      Timing Errors        |      Paths Analyzed       |
+|           Constraint          | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
+|                               |             |   Direct    | Derivative  |   Direct    | Derivative  |   Direct    | Derivative  |
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+|TS01                           |     36.980ns|     10.000ns|     21.023ns|            0|            0|           50|        40640|
+| TS_u_ClockGen_clk_c_dcm_0     |     36.980ns|     21.023ns|          N/A|            0|            0|        40640|            0|
+| TS_u_ClockGen_clk_c_dcm_90    |     36.980ns|      1.596ns|          N/A|            0|            0|            0|            0|
++-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
+
+1 constraint not met.
+INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
+   constraint is not analyzed due to the following: No paths covered by this 
+   constraint; Other constraints intersect with this constraint; or This 
+   constraint was disabled by a Path Tracing Control. Please run the Timespec 
+   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
+
+
+Generating Pad Report.
+
+All signals are completely routed.
+
+WARNING:Par:283 - There are 32 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
+
+Total REAL time to PAR completion: 10 mins 31 secs 
+Total CPU time to PAR completion: 10 mins 29 secs 
+
+Peak Memory Usage:  455 MB
+
+Placement: Completed - No errors found.
+Routing: Completed - No errors found.
+Timing: Completed - 32 errors found.
+
+Number of error messages: 0
+Number of warning messages: 39
+Number of info messages: 2
+
+Writing design to file Replay.ncd
+
+
+
+PAR done!
+Starting Timing Analysis...
+Release 14.7 - Trace  (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+
+Loading device for application Rf_Device from file '3s1600e.nph' in environment
+/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.
+   "Replay_Top" is an NCD, version 3.2, device xc3s1600e, package fg320, speed
+-4
+WARNING:Timing:3223 - Timing constraint PATH "TS_20_path" TIG; ignored during
+   timing analysis.
+INFO:Timing:3386 - Intersecting Constraints found and resolved.  For more
+   information, see the TSI report.  Please consult the Xilinx Command Line
+   Tools User Guide for information on generating a TSI report.
+--------------------------------------------------------------------------------
+Release 14.7 Trace  (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+
+/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/bin/lin/unwrapped/trce -v 10 -o
+Replay.twr Replay.ncd Replay.pcf
+
+
+Design file:              Replay.ncd
+Physical constraint file: Replay.pcf
+Device,speed:             xc3s1600e,-4 (PRODUCTION 1.27 2013-10-13)
+Report level:             verbose report, limited to 10 items per constraint
+--------------------------------------------------------------------------------
+
+INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
+INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
+   option. All paths that are not constrained will be reported in the
+   unconstrained paths section(s) of the report.
+INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a
+   50 Ohm transmission line loading model.  For the details of this model, and
+   for more information on accounting for different loading conditions, please
+   see the device datasheet.
+INFO:Timing:3390 - This architecture does not support a default System Jitter
+   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
+   Uncertainty calculation.
+INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
+   'Phase Error' calculations, these terms will be zero in the Clock Uncertainty
+   calculation.  Please make appropriate modification to SYSTEM_JITTER to
+   account for the unsupported Discrete Jitter and Phase Error.
+
+
+Timing summary:
+---------------
+
+Timing errors: 32  Score: 6386 (Setup/Max: 6386, Hold: 0)
+
+Constraints cover 16489089 paths, 1 nets, and 106512 connections
+
+Design statistics:
+   Minimum period:  39.304ns (Maximum frequency:  25.443MHz)
+   Maximum path delay from/to any node:  14.251ns
+   Maximum net skew:   0.236ns
+
+
+Analysis completed Fri Mar 21 21:39:00 2014
+--------------------------------------------------------------------------------
+
+Generating Report ...
+
+Number of warnings: 1
+Number of info messages: 6
+Total time: 1 mins 4 secs 
+Starting Bitgen...
+Release 14.7 - Bitgen P.20131013 (lin)
+Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
+Loading device for application Rf_Device from file '3s1600e.nph' in environment
+/home/markw/altera/xilinx/ise/14.7/ISE_DS/ISE/.
+   "Replay_Top" is an NCD, version 3.2, device xc3s1600e, package fg320, speed
+-4
+Opened constraints file Replay.pcf.
+
+Fri Mar 21 21:39:14 2014
+
+Running DRC.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<0>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<1>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<2>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<3>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<4>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<5>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<6>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<7>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<8>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<9>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Joy_A<5>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Joy_B<5>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<10>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<11>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<12>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<20>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<13>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<21>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<14>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<22>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<15>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<16>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<17>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<18>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Aux_IP<19>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <b_IO<0>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <b_IO<1>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <b_IO<2>_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_Video_Int_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal <i_RS232_CTS_IBUF> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/gtia1/counter_hpos/GLOBAL_LOGIC0> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/antic1/antic_counter_line_buffer/GLOBAL_LOGIC0> is
+   incomplete. The signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/pokey1/GLOBAL_LOGIC0> is incomplete. The signal does not
+   drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/pokey2/GLOBAL_LOGIC0> is incomplete. The signal does not
+   drive any load pins in the design.
+WARNING:PhysDesignRules:367 - The signal
+   <u_Core/atari800core/zpu_config1/uart1/GLOBAL_LOGIC0> is incomplete. The
+   signal does not drive any load pins in the design.
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<0> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<1> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<2> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<3> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<20> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<12> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<21> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<13> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<30> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<22> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<14> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<31> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<23> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<15> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<32> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<24> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<16> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<33> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<25> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<17> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<34> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<26> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<18> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<35> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<27> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<19> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<28> is set but the tri state is not configured. 
+WARNING:PhysDesignRules:781 - PULLUP on an active net. PULLUP of comp
+   b_Aux_IO<29> is set but the tri state is not configured. 
+DRC detected 0 errors and 63 warnings.  Please see the previously displayed
+individual error or warning messages for more details.
+Creating bit map...
+Saving bit stream in "Replay.bit".
+Saving bit stream in "Replay.bin".
+Bitstream generation is complete.
+~/altera/replay/src/hw/replay/cores/atari_800xl
Index: replay/sdcard/osbhias.rom
===================================================================
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___________________________________________________________________
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+application/octet-stream
\ No newline at end of property
Index: replay/sdcard/xlhias.rom
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/xlhias.rom
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## -0,0 +1 ##
+application/octet-stream
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Index: replay/source/Replay_Top.vhd
===================================================================
--- replay/source/Replay_Top.vhd	(nonexistent)
+++ replay/source/Replay_Top.vhd	(revision 1)
@@ -0,0 +1,953 @@
+-- WWW.FPGAArcade.COM
+-- REPLAY 1.0
+-- Retro Gaming Platform
+-- No Emulation No Compromise
+--
+-- All rights reserved
+-- Mike Johnson 2008/2009
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- Redistributions of source code must retain the above copyright notice,
+-- this list of conditions and the following disclaimer.
+--
+-- Redistributions in synthesized form must reproduce the above copyright
+-- notice, this list of conditions and the following disclaimer in the
+-- documentation and/or other materials provided with the distribution.
+--
+-- Neither the name of the author nor the names of other contributors may
+-- be used to endorse or promote products derived from this software without
+-- specific prior written permission.
+--
+-- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+-- You are responsible for any legal issues arising from your use of this code.
+--
+-- The latest version of this file can be found at: www.FPGAArcade.com
+--
+-- Email support@fpgaarcade.com
+--
+-- ===================================================================
+--
+-- This file was modified to embed Mikes VIC-20 core by W. Scherr
+-- Email ws_arcade <at> pin4.at
+--
+-- $Id: Replay_Top.vhd 387 2014-03-01 21:30:37Z wolfgang.scherr $
+--
+-- Latest version can be found at: www.pin4.at
+--
+-- ===================================================================
+
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+
+  use work.Replay_Pack.all;
+  use work.Replay_VideoTiming_Pack.all;
+
+library UNISIM;
+  use UNISIM.Vcomponents.all;
+
+entity Replay_Top is
+  port (
+    -- RS232 debug port
+    i_RS232_RXD           : in    bit1;
+    o_RS232_TXD           : out   bit1;
+    i_RS232_CTS           : in    bit1;
+    o_RS232_RTS           : out   bit1;
+    -- Joysticks
+    i_Joy_A               : in    word( 5 downto 0);
+    i_Joy_B               : in    word( 5 downto 0);
+    -- IO
+    b_IO                  : inout word(54 downto 0);
+    b_Aux_IO              : inout word(39 downto 0);
+
+    i_Aux_IP              : in    word(22 downto 0);
+    -- DRAM
+    o_Mem_Addr            : out   word(14 downto 0);
+    b_Mem_DQ              : inout word(15 downto 0);
+    b_Mem_UDQS            : inout bit1; -- Ctrl8
+    b_Mem_LDQS            : inout bit1; -- Ctrl7
+    o_Mem_UDM             : out   bit1; -- Ctrl6
+    o_Mem_LDM             : out   bit1; -- Ctrl5
+    o_Mem_CS              : out   bit1; -- Ctrl4
+    o_Mem_RAS             : out   bit1; -- Ctrl3
+    o_Mem_CAS             : out   bit1; -- Ctrl2
+    o_Mem_WE              : out   bit1; -- Ctrl1
+    o_Mem_CKE             : out   bit1; -- Ctrl0
+    o_Mem_Clk_P           : out   bit1;
+    o_Mem_Clk_N           : out   bit1;
+    --
+    o_Disk_Led            : out   bit1;
+    o_Pwr_Led             : out   bit1;
+    --
+    i_Ext_Rst_L           : in    bit1; -- pullup
+    b_2V5_IO_1            : inout bit1;
+    b_2V5_IO_0            : inout bit1;
+    -- Video
+    o_Video_Clk_P         : out   bit1;
+    o_Video_Clk_N         : out   bit1;
+    o_Video_Rst_L         : out   bit1; -- Video16
+    i_Video_Int           : in    bit1; -- Video15
+    o_Video_DE            : out   bit1; -- Video14
+    o_Video_V             : out   bit1; -- Video13
+    o_Video_H             : out   bit1; -- Video12
+    o_Video_Data          : out   word(11 downto 0);  --Video11..0
+    b_Video_DDC_Clk       : out   bit1;
+    b_Video_DDC_Data      : out   bit1;
+    o_Video_HSync         : out   bit1;
+    o_Video_VSync         : out   bit1;
+    b_Video_SPC           : inout bit1;
+    b_Video_SPD           : inout bit1;
+    -- Audio
+    o_Audio_LRCIN         : out   bit1; -- Audio3
+    o_Audio_MCLK          : out   bit1; -- Audio2
+    o_Audio_BCKIN         : out   bit1; -- Audio1
+    o_Audio_DIN           : out   bit1; -- Audio0
+    --
+    b_PS2A_Clk            : inout bit1;
+    b_PS2A_Data           : inout bit1;
+    b_PS2B_Clk            : inout bit1;
+    b_PS2B_Data           : inout bit1;
+
+    b_SCL                 : inout bit1;
+    b_SDA                 : inout bit1;
+
+    -- System control
+    i_FPGA_Ctrl0          : in    bit1;
+    i_FPGA_Ctrl1          : in    bit1;
+    i_FPGA_SPI_Clk        : in    bit1;
+    b_FPGA_SPI_MOSI       : inout bit1;
+    b_FPGA_SPI_MISO       : inout bit1;
+
+    -- SSC & config pins
+    --i_SSC_TF              : in    bit1; --io_init input during config
+    --i_SSC_TD              : in    bit1; --io_din  input during config
+    --i_SSC_RK              : in    bit1; --io_cclk input during config
+    o_SSC_RD              : out   bit1; --io_dout output during config -- vertical sync for MCU (sync OSD update)
+    --
+    -- Clocks
+    --
+    o_Clk_68K             : out   bit1; -- source terminated to connector
+    b_Clk_Aux             : inout bit1; -- direct to connector
+    ClK_A                 : in    bit1;
+    ClK_B                 : in    bit1;
+    ClK_C                 : in    bit1
+
+    );
+end;
+
+architecture RTL of Replay_Top is
+
+  constant dla_mem_enable : boolean := false;
+
+  signal clk_spi                : bit1;
+
+  signal clk_vid                : bit1;
+  signal clk_vid_90             : bit1;
+  signal ena_vid                : bit1;
+  signal rst_vid                : bit1;
+  signal rst_vid_hard           : bit1;
+
+  signal clk_sys                : bit1; -- note, same at clk_ctl
+  signal ena_sys                : bit1;
+  signal ena_sub1               : bit1;
+  signal ena_sub4               : bit1;
+  signal rst_sys                : bit1;
+
+  signal clk_ctl                : bit1;
+  signal rst_ctl                : bit1;
+  signal rst_ctl_hard           : bit1;
+  signal tick_ctl_1us           : bit1;
+  signal tick_ctl_100us         : bit1;
+
+  signal rst_aud                : bit1;
+  signal clk_aud                : bit1;
+
+  signal clk_ram                : bit1;
+  signal clk_ram_90             : bit1;
+  signal clk_capture            : bit1;
+  signal rst_ram                : bit1;
+  signal rst_capture            : bit1;
+  signal rst_soft               : bit1;
+  signal halt_soft              : bit1;
+  --
+  signal drive_scl_low          : bit1;
+  signal drive_sda_low          : bit1;
+  signal drive_spc_low          : bit1;
+  signal drive_spd_low          : bit1;
+
+  signal cfg_phase              : word(7 downto 0);
+  signal cfg_cal_sel            : word(1 downto 0);
+
+  signal core_ps2_clk           : bit1;
+  signal core_ps2_data          : bit1;
+
+  signal ps2a_drive_clk_low     : bit1;
+  signal ps2a_drive_data_low    : bit1;
+  signal ps2b_drive_clk_low     : bit1;
+  signal ps2b_drive_data_low    : bit1;
+
+  signal led : bit1;
+  signal tick_pre1 : bit1;
+  signal tick : bit1;
+
+  signal ram_addr             :   word(24 downto 2);
+  signal ram_data             :    word(63 downto 0);
+  signal ram_r_w_l            :    bit1;
+  signal ram_valid            :   bit1;
+
+  signal core_audio_l : word(23 downto 0);
+  signal core_audio_r : word(23 downto 0);
+  signal phy_audio_taken : bit1;
+
+  signal core_vid_rgb             : word(23 downto 0);
+  signal core_vid_sync            : r_Vidsync;
+  signal core_vid_timing          : r_Vidtiming;
+  signal core_vid_std             : r_Vidstd;
+
+  signal cfg_static : word(31 downto 0);
+  signal cfg_dynamic : word(31 downto 0);
+  signal cfg_ctrl : word(15 downto 0);
+  signal cfg_fileio_i : word(7 downto 0);
+  signal cfg_fileio : word(7 downto 0);
+
+  signal mode_1541  : bit1;
+  signal mode_key   : bit1;
+
+  signal conf_valid : bit1;
+  signal conf_taken : bit1;
+  signal conf_write : bit1;
+  signal conf_wr_core              : bit1 := '0';
+  signal conf_wr_1541              : bit1 := '0';
+  signal conf_wr_key               : bit1 := '0';
+
+  --
+  -- MCH
+  --
+  signal mch_addr : word(31 downto 0);
+  signal mch_read : bit1;
+  signal mch_data : word(7 downto 0);
+  signal mch_valid : bit1;
+  signal mch_taken : bit1;
+  signal mch_rd_data : word(7 downto 0);
+  signal mch_rd_we : bit1;
+
+  signal mch_ram_taken : word(0 downto 0);
+  signal mch_ram_rd_data : array8(0 downto 0);
+  signal mch_ram_rd_we : word(0 downto 0);
+
+  signal mch_ddr_taken : bit1;
+  signal mch_ddr_rd_data : word(7 downto 0);
+  signal mch_ddr_rd_we : bit1;
+
+  signal hp_ddr_taken : bit1;
+  signal hp_ddr_valid : bit1;
+  signal hp_ddr_we : bit1;
+  signal hp_wl : bit1;
+  signal hp_ddr_addr : word(25 downto 0);
+  signal hp_rdata : word(31 downto 0);
+  signal hp_wdata : word(31 downto 0);
+  signal hp_wbe   : word(3 downto 0);
+
+  signal media_adr : unsigned(17 downto 0);
+  signal media_read : bit1;
+  signal media_dat : word(7 downto 0);
+  signal diskid_s : word(15 downto 0);
+  signal inscnt_s : unsigned(18 downto 0);
+
+  signal init_diskinsert_s : bit1;
+  signal writeprotn_s : bit1;
+
+  --
+  --
+  --
+  signal syscon_vid_rgb           : word(23 downto 0);
+  signal syscon_vid_sync          : r_Vidsync;
+  signal spi_syscon_cs_l : bit1;
+  signal spi_fileio_cs_l : bit1;
+  signal spi_syscon_miso : bit1;
+  signal spi_fileio_miso : bit1;
+
+  signal kb_inhibit : bit1;
+  signal kb_we : bit1;
+  signal kb_ps2 : word(7 downto 0);
+  signal kb_led : word(2 downto 0);
+
+  signal ms_we               : bit1;
+  signal ms_posx             : word(11 downto 0);
+  signal ms_posy             : word(11 downto 0);
+  signal ms_butn             : word( 2 downto 0);
+
+  signal ena_sys_c1 : bit1;
+  signal ena_sys_ddr : bit1;
+
+begin
+  u_spi_bufg  : BUFG  port map (I => i_FPGA_SPI_Clk, O => clk_spi);
+
+  u_ClockGen : entity work.Replay_ClockGen
+  generic map (
+    G_DIVIDER             => 11
+    )
+  port map (
+    i_ClK_A               => Clk_A,
+    i_ClK_B               => Clk_B,
+    i_ClK_C               => Clk_C,
+    --
+    i_Rst_L               => i_Ext_Rst_L, -- hard reset
+    i_Rst_Soft            => rst_soft,    -- NOT DRAM!
+    --
+    i_Ctl_Phase           => cfg_phase,
+    i_Clk_Ctl             => clk_ctl,
+    --
+    o_Clk_Vid             => clk_vid,
+    o_Clk_Vid_90          => clk_vid_90,
+    o_Rst_Vid             => rst_vid,
+    o_Rst_Vid_Hard        => rst_vid_hard,
+    --
+    o_Clk_Ctl             => clk_ctl,
+    o_Rst_Ctl             => rst_ctl,
+    o_Rst_Ctl_Hard        => rst_ctl_hard,
+    --
+    o_Tick_Ctl_1us        => tick_ctl_1us,
+    o_Tick_Ctl_100us      => tick_ctl_100us,
+    --
+    o_Clk_Aux             => clk_aud,
+    o_Rst_Aux             => rst_aud,
+    --
+    o_Clk_Ram             => clk_ram,
+    o_Clk_Ram_90          => clk_ram_90,
+    o_Clk_Ram_Capture     => clk_capture,
+    o_Rst_Ram             => rst_ram,
+    o_Rst_Ram_Capture     => rst_capture
+    );
+
+  enas : block
+    signal sys_cnt : word(1 downto 0) := (others => '0');
+    signal sub_cnt : word(4 downto 0) := (others => '0');
+  begin
+    -- clk_ram and clk_sys are edge aligned.
+    p_sys_cnt : process
+    begin
+      wait until rising_edge(clk_sys);
+      sys_cnt <= sys_cnt + "1";
+      sub_cnt <= sub_cnt + "1";
+
+      ena_sys  <= '0';
+      if (sys_cnt = "11" ) then -- 0...3 --> divdes by 4 
+        ena_sys <= '1';
+        sys_cnt <= "00";
+      end if;
+      ena_sub1 <= '0';
+      ena_sub4 <= '0';
+      if (sub_cnt = "00101" ) then -- 0...5 --> divdes by 6
+        ena_sub4 <= '1';
+      end if;
+      if (sub_cnt = "01011" ) then -- 6...11 --> divdes by 6
+        ena_sub4 <= '1';
+      end if;
+      if (sub_cnt = "10001" ) then -- 12...17 --> divdes by 6
+        ena_sub4 <= '1';
+      end if;
+      if (sub_cnt = "10111" ) then -- 0...23 --> divdes by 24, -- 18...23 --> divdes by 6 
+        ena_sub1 <= '1';
+        ena_sub4 <= '1';
+        sub_cnt <= "00000";
+      end if;
+      -- DDR needs divison by 4
+      if sub_cnt(1 downto 0)="10" then
+        ena_sys_ddr <= '1';
+      else
+        ena_sys_ddr <= '0';
+      end if;
+    end process;
+    --ena_sys_c1 <= not ena_sub4; --sys_cnt(1);
+    ena_sys_c1 <= not sub_cnt(1);
+
+    ena_vid <= '1';
+  end block;
+  --
+  -- clk_ctl is the same as clk_sys, but used with no clock enable
+  -- names are to keep domains apart
+  --
+  clk_sys <= clk_ctl;
+  rst_sys <= rst_ctl;
+  --
+  --
+  --
+
+  b_2V5_IO_1   <= 'Z';
+  b_2V5_IO_0   <= 'Z';
+
+  o_Clk_68K  <= 'Z';
+  b_Clk_Aux  <= 'Z';
+
+  b_tick : block
+    signal PreCounter1 : word(15 downto 0);
+    signal PreCounter2 : word(11 downto 0);
+  begin
+    p_count : process
+    begin
+      wait until rising_edge(clk_vid);
+      if (ena_vid = '1') then
+        PreCounter1 <= PreCounter1 - "1";
+
+        tick_pre1 <= '0';
+        if (PreCounter1 = x"0000") then
+          tick_pre1 <= '1';
+        end if;
+        -- synopsys translate_off
+        tick_pre1 <= '1';
+        -- synopsys translate_on
+
+        tick <= '0';
+        if (tick_pre1 = '1') then
+          if (PreCounter2 = x"000") then
+            PreCounter2 <= x"19B";
+            tick <= '1';
+          else
+            PreCounter2 <= PreCounter2 - "1";
+          end if;
+        end if;
+      end if;
+    end process;
+  end block;
+
+  o_Pwr_Led <= not init_diskinsert_s;
+
+  b_IO(22 downto  0) <= (others => 'Z');
+  b_IO(28 downto 23) <= (others => 'Z');
+  b_IO(34 downto 29) <= (others => 'Z');
+  b_IO(54 downto 35) <= (others => 'Z');
+
+  b_Aux_IO(39 downto 36)  <=  (others => 'Z');
+
+  -- prevent forwarding PS/2 to core when OSD is activated
+  core_ps2_clk <= b_PS2B_Clk when kb_inhibit='0' else '1';
+  core_ps2_data <= b_PS2B_Data when kb_inhibit='0' else '1';
+
+  --
+  -- CORE
+  --
+  u_Core : entity work.Core_Top
+  port map (
+    i_Clk_Vid             => clk_vid,
+    i_Ena_Vid             => ena_vid,
+    i_Rst_Vid             => rst_vid,
+    --
+    i_ClK_Sys             => clk_sys,
+    i_Ena_Sys             => ena_sys,
+    i_Ena_Sub1            => ena_sub1,
+    i_Ena_Sub4            => ena_sub4,
+    i_Rst_Sys             => rst_sys,
+    --
+    i_Joy_A               => i_Joy_A,
+    i_Joy_B               => i_Joy_B,
+    --
+    i_Ms_We               => ms_we,
+    i_Ms_PosX             => ms_posx,
+    i_Ms_PosY             => ms_posy,
+    i_Ms_Butn             => ms_butn,
+    --
+    i_kb_osd_inhibit      => kb_inhibit,
+    i_kb_ps2_we           => kb_we,
+    i_kb_ps2              => kb_ps2,
+    o_kb_led              => kb_led,
+    --
+    core_ps2_data => core_ps2_data,
+    core_ps2_clk => core_ps2_clk,
+    --
+    i_Rst_Core            => rst_soft,
+    i_Halt_Core           => halt_soft,
+    i_HD_Mode             => cfg_dynamic(16),
+    o_act_led_n           => o_Disk_Led,
+    --
+    i_Audio_lvl           => cfg_dynamic(18 downto 17),
+    o_Audio_l             => core_audio_l,
+    o_Audio_R             => core_audio_r,
+    i_Audio_Taken         => phy_audio_taken,
+    --
+    i_cart_ro             => cfg_static(5),          -- readonly-enable
+    i_cart_en             => cfg_static(0),          -- at $A000(8k)     '1', --
+    i_ram_ext             => cfg_static(4 downto 1), -- at $6000(8k),$4000(8k),$2000(8k),$0400(3k)  "1111", --
+    drive_address         => "00",
+    --
+    o_Vid_RGB             => core_vid_rgb,
+    o_Vid_Sync            => core_vid_sync,
+    -- sideband info
+    o_Vid_Timing          => core_vid_timing,
+    o_Vid_Std             => core_Vid_Std,
+    -- d64 reader
+    diskid_i              => diskid_s,
+    media_adr_o           => media_adr,
+    media_read_o          => media_read,
+    media_dat_i           => media_dat,
+    write_prot_n          => writeprotn_s,
+    floppy_inserted       => init_diskinsert_s,
+    --
+    hp_ddr_valid        => hp_ddr_valid,
+    hp_ddr_taken        => hp_ddr_taken,
+    hp_ddr_addr         => hp_ddr_addr(25 downto 2),
+    hp_wl               => hp_wl,
+    hp_wbe              => hp_wbe,
+    hp_wdata            => hp_wdata,
+    hp_rdata            => hp_rdata,
+    hp_ddr_wr           => hp_ddr_we,
+    --
+    i_RS232_RXD         => i_RS232_RXD,
+    o_RS232_TXD         => o_RS232_TXD,
+    i_RS232_CTS         => i_RS232_CTS,
+    o_RS232_RTS         => o_RS232_RTS,
+    --debug                 => b_Aux_IO(35 downto 0), -- from 1541 core:   addr(16), di(8), do(8), wrn, ph2, motor, led
+                                                      -- from 1541 stream: track(7), sector(8), region(2), bdata(8), byteready, sync, gdata(8), led
+    --debug                 => b_Aux_IO(35 downto 0), -- from VIC20:       addr(16), dio(8), hs, vs, atn, clk, dat, <mode(3)>, r_wn, nmi, irq, res
+    debug                 => open,
+    debugi                => b_IO(2 downto 0),
+    -- ROM config
+    CONF_WR_KEY           => conf_wr_key,
+    CONF_WR_1541          => conf_wr_1541,
+    CONF_WR               => conf_wr_core,
+    CONF_AI               => mch_addr(15 downto 0),
+    CONF_DI               => mch_data,
+    -- 
+    ram_select            => cfg_dynamic(2 downto 0),
+    rom_select           => cfg_dynamic(8 downto 3)
+    );
+
+  --                            8                16              1             1           1            1           1           1            1        1          1           1                 2
+  b_Aux_IO(35 downto 0) <= mch_data & mch_addr(15 downto 0) & conf_wr_1541 & conf_wr_core & conf_valid & conf_write & '0' & mode_1541 & mch_taken & mch_valid & mch_read & mch_read & mch_addr(1 downto 0);
+
+  -- I/O
+
+  u_JoyPS2 : entity work.Replay_JoyPS2
+  port map (
+    i_Clk                 => clk_ctl,
+    i_Tick_1us            => tick_ctl_1us,
+    i_Tick_100us          => tick_ctl_100us,
+    i_Rst                 => rst_ctl,
+    --
+    -- IO Joysticks
+    --
+    i_Joy_A               => i_Joy_A,
+    i_Joy_B               => i_Joy_B,
+
+    -- IO PS2
+    i_PS2A_Clk            => b_PS2A_Clk,
+    i_PS2A_Data           => b_PS2A_Data,
+-- TODO
+    o_PS2A_Drive_Clk_Low  => ps2a_drive_clk_low,
+    o_PS2A_Drive_Data_Low => ps2a_drive_data_low,
+--
+    i_PS2B_Clk            => b_PS2B_Clk,
+    i_PS2B_Data           => b_PS2B_Data,
+    o_PS2B_Drive_Clk_Low  => ps2b_drive_clk_low,
+    o_PS2B_Drive_Data_Low => ps2b_drive_data_low,
+    --
+    -- to core
+    --
+    i_Kb_PS2_Leds         => kb_led,
+    o_Kb_PS2_We           => kb_we,
+    o_Kb_PS2_Data         => kb_ps2,
+    --
+    o_Ms_We               => ms_we,
+    o_Ms_PosX             => ms_posx,
+    o_Ms_PosY             => ms_posy,
+    o_Ms_Butn             => ms_butn
+    );
+
+  b_PS2A_Clk  <= '0' when (ps2a_drive_clk_low  = '1') else 'Z';
+  b_PS2A_Data <= '0' when (ps2a_drive_data_low = '1') else 'Z';
+  b_PS2B_Clk  <= '0' when (ps2b_drive_clk_low  = '1') else 'Z';
+  b_PS2B_Data <= '0' when (ps2b_drive_data_low = '1') else 'Z';
+
+  b_PULLUP : block
+  begin
+    -- input's have pulls in UCF file
+    ps2a_pu_clk  : PULLUP port map (o => b_PS2A_Clk);
+    ps2a_pu_data : PULLUP port map (o => b_PS2A_Data);
+    ps2b_pu_clk  : PULLUP port map (o => b_PS2B_Clk);
+    ps2b_pu_data : PULLUP port map (o => b_PS2B_Data);
+
+    io : for i in 0 to 54 generate
+      io_pu  : PULLUP port map (o   => b_IO(i));
+    end generate;
+
+    aux : for i in 12 to 39 generate
+      auxio_pu  : PULLUP port map (o   => b_Aux_IO(i));
+    end generate;
+
+    aux2 : for i in 0 to 3 generate
+      auxio_pu  : PULLUP port map (o   => b_Aux_IO(i));
+    end generate;
+
+    aux_pu  : PULLUP port map (o => b_Clk_Aux);
+    io_1_pu : PULLUP port map (o => b_2V5_IO_1);
+    io_0_pu : PULLUP port map (o => b_2V5_IO_0);
+
+  end block;
+
+  --
+  -- DRAM is 64MB x 8bit or 16MB x 32bit
+  --
+  -- (byte) address is 0x03FF FFFF downto 0x0000 0000
+  --
+  -- we use the first 32MB (x8) for memory on the VIC-20          --> 0x01FF FFFF downto 0x0000 0000
+  -- we use the second 32MB (x8) as memory for the 1541 d64 files --> 0x03FF FFFF downto 0x0200 0000
+
+--  mch_ddr_valid <= mch_valid when (mch_addr(31) = '0') else '0';  -- first addresses from 0x00000000 on are DRAM, from 0x80000000 on is for other memory
+
+  u_DDRCtrl : entity work.Replay_DDRCtrl_top
+  port map (
+    i_Clk_Ram         => clk_ram,
+    i_Clk_Ram_90      => clk_ram_90,
+    i_Rst_Ram         => rst_ram,
+    --
+    i_Clk_Capture     => clk_capture,
+    i_Rst_Capture     => rst_capture,
+    --
+    i_Clk_Sys         => clk_sys,
+    i_Ena_Sys         => ena_sys_ddr,
+    i_Ena_Sys_C1      => ena_sys_C1,
+    i_Rst_Sys         => rst_sys,
+
+    -- DDR Signals
+    o_RAM_BA          => o_Mem_Addr(14 downto 13),
+    o_RAM_Addr        => o_Mem_Addr(12 downto  0),
+    --
+    o_RAM_CS_L        => o_Mem_CS,
+    o_RAM_WE_L        => o_Mem_WE,
+    o_RAM_RAS_L       => o_Mem_RAS,
+    o_RAM_CAS_L       => o_Mem_CAS,
+    --
+    o_RAM_DM_L(1)     => o_Mem_UDM,
+    o_RAM_DM_L(0)     => o_Mem_LDM,
+    b_RAM_DQS(1)      => b_Mem_UDQS,
+    b_RAM_DQS(0)      => b_Mem_LDQS,
+    b_RAM_DQ          => b_Mem_DQ,
+    --
+    o_RAM_CKE         => o_Mem_CKE,
+    o_RAM_CK_P        => o_Mem_Clk_P,
+    o_RAM_CK_N        => o_Mem_Clk_N,
+    --
+    i_Cfg_Cal_Sel     => cfg_cal_sel,
+
+    -- High Priority - 32 bit i/f
+    i_HP_Valid        => hp_ddr_valid,
+    o_HP_Taken        => hp_ddr_taken,
+    i_HP_Addr         => hp_ddr_addr(25 downto 2),
+    i_HP_RW_l         => hp_wl,
+    i_HP_W_BE         => hp_wbe,
+    i_HP_W_Data       => hp_wdata,
+    --
+    o_HP_R_Data       => hp_rdata,
+    o_HP_R_We         => hp_ddr_we,
+
+    -- Low Priority - 8 bit i/f
+    i_LP_Valid        => mch_valid,
+    o_LP_Taken        => mch_ddr_taken,
+    i_LP_Addr         => mch_addr(25 downto 0),
+    i_LP_RW_l         => mch_read,
+    i_LP_W_Data       => mch_data,
+    --
+    o_LP_R_Data       => mch_ddr_rd_data,
+    o_LP_R_We         => mch_ddr_rd_we
+    );
+
+  -- handling media access when d64 is load via
+  -- ARM to DDR (on low-prio channel) 
+  media_access : process (clk_sys, rst_sys) is
+  begin
+    if rst_sys='1' then
+      init_diskinsert_s <= '0';
+      diskid_s <= x"0000";
+      inscnt_s <= (others => '0');
+      writeprotn_s <= '0';
+    elsif rising_edge(clk_sys) then
+      -- handle disk change and fetch disk id
+      if mch_read='0' and mch_valid='1' and mch_ddr_taken='0' then
+        if mch_addr=x"02000000" then
+          init_diskinsert_s <= '0';
+          writeprotn_s <= '1';
+        elsif mch_addr=x"020165A2" then
+          diskid_s(15 downto 8) <= mch_data;
+        elsif mch_addr=x"020165A3" then
+          diskid_s(7 downto 0)  <= mch_data;
+        elsif mch_addr=x"0202AAFF" then
+          inscnt_s <= (others => '1');
+        end if;
+      end if;
+      if ena_sub1='1' then
+        if inscnt_s/=0 then
+          inscnt_s<=inscnt_s-1;
+          if inscnt_s=1 then
+            init_diskinsert_s <= '1';
+            writeprotn_s <= '0';
+          end if;
+        end if;
+      end if;
+    end if;
+  end process;
+
+  ----------------------------------------------------------
+  -- RAM/ROM load process
+  ----------------------------------------------------------
+
+  conf_valid <= mch_valid when (mch_addr(31 downto 20) = x"000") else '0';
+  conf_write <= conf_valid and ena_sys and not mch_read;   -- 0x000?xxxx --> configuration upload (ROM or PRG)
+  mode_1541 <= mch_addr(18);                   -- 0x0004xxxx --> 1541 configuration upload
+  mode_key  <= mch_addr(17);                   -- 0x0002xxxx --> keymapping configuration upload
+
+  -- we pass all input also to the core memories in parallel to the DDR ram
+  conf_wr_core <= conf_write and mch_valid and (not mode_1541) and (not mode_key);
+  conf_wr_1541 <= conf_write and mch_valid and mode_1541;
+  conf_wr_key  <= conf_write and mch_valid and mode_key;
+
+  --
+  -- System control / On Screen Display
+  --
+  u_Syscon : entity work.Replay_Syscon
+  generic map (
+    -- defaults
+    g_Cfg_Static          => x"00000000",
+    g_Cfg_Dynamic         => x"00000000",
+    g_Cfg_FileIO          => "00000000",   --  7..4 HD MASK 2..0 #FD
+    g_Cfg_Ctrl            => x"0080",
+    --
+    g_Version             => x"0001" -- top bit DRAM disabled
+    )
+  port map (
+    i_Clk_Vid             => clk_vid,
+    i_Ena_Vid             => ena_vid,
+    i_Rst_Vid             => rst_vid,
+    --
+    i_Clk_Ctl             => clk_ctl,
+    i_Rst_Ctl             => rst_ctl,
+    i_Rst_Ctl_Hard        => rst_ctl_hard,
+    --
+    o_Rst_Soft            => rst_soft,
+    o_Halt                => halt_soft,
+    --
+    i_SPI_CS_l            => spi_syscon_cs_l,
+    i_SPI_Clk             => clk_spi,
+    i_SPI_D               => b_FPGA_SPI_MOSI,
+    o_SPI_D               => spi_syscon_miso,
+    --
+    o_VBL                 => o_SSC_RD,
+     -- Config
+    i_cfg_fileio_mask     => cfg_fileio, -- tells the system what the core supports.
+    i_cfg_status          => x"0000",
+    --
+    o_cfg_Static          => cfg_static,
+    o_cfg_Dynamic         => cfg_dynamic,
+    o_Cfg_FileIO          => cfg_fileio_i,
+    o_Cfg_Ctrl            => cfg_ctrl,
+    --
+    i_Kb_PS2_We           => kb_we,
+    i_Kb_PS2_Data         => kb_ps2,
+    o_Kb_Inhibit          => kb_inhibit, -- core should use to ignore keypresses when OSD active
+    --
+    i_Vid_RGB             => core_vid_rgb,
+    i_Vid_Sync            => core_vid_sync,
+    --
+    o_Vid_RGB             => syscon_vid_rgb,
+    o_Vid_Sync            => syscon_vid_sync
+    --
+    );
+
+  cfg_fileio  <= cfg_fileio_i and "00000000"; -- 0 HD, 0 FD
+  cfg_phase   <= cfg_ctrl(7 downto 0);  -- 25 ps per tick
+  cfg_cal_sel <= cfg_ctrl(9 downto 8);
+-- When the transfer is in direct mode from SD card, we need
+-- to swap over the in and out pins on the SPI interface (we are now a slave).
+-- We cannot drive the output in this case unless the ARM is not.
+
+  spi_fileio_cs_l <= i_FPGA_Ctrl0;
+  spi_syscon_cs_l <= i_FPGA_Ctrl1;
+
+  b_FPGA_SPI_MOSI <= 'Z';
+  b_FPGA_SPI_MISO <= spi_fileio_miso when (spi_fileio_cs_l = '0') else 'Z';
+  b_FPGA_SPI_MISO <= spi_syscon_miso when (spi_syscon_cs_l = '0') else 'Z';
+
+  u_FileIO : entity work.Replay_FileIO
+  port map (
+  -- handles all disk/tape/HDD/ROM transfers to the SD card/ARM
+    i_Clk_Ctl             => clk_ctl,
+    i_Rst_Ctl             => rst_ctl,
+    --
+    i_Ena_Sys             => ena_sys_ddr,
+    --
+    i_SPI_CS_l            => spi_fileio_cs_l,
+    i_SPI_Clk             => clk_spi,
+    i_SPI_D               => b_FPGA_SPI_MOSI,
+    o_SPI_D               => spi_fileio_miso,
+    --
+    -- FD
+    --
+    o_fch_to_core         => open,
+    i_fch_fm_core         => z_FCh_fm_core, -- tie off
+    --
+    -- HD
+    --
+    o_hch_to_core         => open,
+    i_hch_fm_core         => z_HCh_fm_core, -- tie off
+    --
+    -- Memory interface
+    --
+    o_MCh_Addr            => mch_addr,
+    o_Mch_Read            => mch_read,
+    o_MCh_Data            => mch_data,
+    o_MCh_Flush           => open,
+    o_MCh_Valid           => mch_valid,
+    i_MCh_Taken           => mch_taken,
+    --
+    i_MCh_Data            => mch_rd_data,
+    i_MCh_We              => mch_rd_we
+  );
+
+  -- mch read combine
+  mch_taken   <= --conf_taken or
+                 mch_ddr_taken;
+
+  mch_rd_data <= mch_ddr_rd_data(7 downto 0);
+
+  mch_rd_we   <= mch_ddr_rd_we;
+
+  --
+  -- VIDEO
+  --
+  u_Video : entity work.Replay_Video
+  port map (
+    i_Clk_Vid             => clk_vid,
+    i_Clk_Vid_90          => clk_vid_90,
+    i_Ena_Vid             => ena_vid,
+    i_Rst_Vid_Hard        => rst_vid_hard,
+    --
+    i_Clk_Ctl             => clk_ctl, -- used for i2c bridge
+    i_Rst_Ctl             => rst_ctl,
+    --
+    -- Input video must come from a register clocked with Clk_Video
+    i_Vid_RGB             => syscon_vid_rgb,
+    i_Vid_Sync            => syscon_vid_sync,
+    -- cpu i2c pins
+    i_SCL                 => b_SCL,
+    i_SDA                 => b_SDA,
+    o_Drive_SCL_Low       => drive_scl_low,
+    o_Drive_SDA_Low       => drive_sda_low,
+    -- video i2c pins
+    i_SPC                 => b_Video_SPC,
+    i_SPD                 => b_Video_SPD,
+    o_Drive_SPC_Low       => drive_spc_low,
+    o_Drive_SPD_Low       => drive_spd_low,
+    --
+    o_Video_Clk_P         => o_Video_Clk_P,
+    o_Video_Clk_N         => o_Video_Clk_N,
+    o_Video_Rst_L         => o_Video_Rst_L,
+    i_Video_Int           => i_Video_Int,
+    o_Video_DE            => o_Video_DE,
+    o_Video_V             => o_Video_V,
+    o_Video_H             => o_Video_H,
+    o_Video_Data          => o_Video_Data,
+    b_Video_DDC_Clk       => b_Video_DDC_Clk,
+    b_Video_DDC_Data      => b_Video_DDC_Data,
+    --
+    o_Video_HSync         => o_Video_HSync,
+    o_Video_VSync         => o_Video_VSync
+    );
+  --
+  b_SCL       <= '0' when (drive_scl_low = '1') else 'Z';
+  b_SDA       <= '0' when (drive_sda_low = '1') else 'Z';
+  b_Video_SPC <= '0' when (drive_spc_low = '1') else 'Z';
+  b_Video_SPD <= '0' when (drive_spd_low = '1') else 'Z';
+  --
+  -- AUDIO PHY
+  --
+  u_Audio : entity work.Replay_Audio
+  port map (
+    i_Clk                 => clk_aud, --sys,
+    i_Ena                 => '1',     --ena_sys,
+    i_Rst                 => rst_aud, --rst_sys,
+    --
+    i_Sample_L            => core_audio_l,
+    i_Sample_R            => core_audio_r,
+    o_Sample_Taken        => phy_audio_taken,
+    --
+    o_Audio_LRCIN         => o_Audio_LRCIN,
+    o_Audio_MCLK          => o_Audio_MCLK,
+    o_Audio_BCKIN         => o_Audio_BCKIN,
+    o_Audio_DIN           => o_Audio_DIN
+    );
+  --
+
+  -- memory debugging
+
+  dbg : block is
+    --{{{  cs
+    component icon
+      PORT (
+        CONTROL0 : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0)
+        );
+    end component;
+
+    component ila_1024_63
+      PORT (
+        CONTROL : INOUT STD_LOGIC_VECTOR(35 DOWNTO 0);
+        CLK     : IN STD_LOGIC;
+        TRIG0   : IN STD_LOGIC_VECTOR(62 DOWNTO 0)
+        );
+    end component;
+
+    signal cs_control0   : std_logic_vector(35 downto 0);
+    signal cs_clk        : std_logic;
+    signal cs_trig       : std_logic_vector(62 downto 0);
+    --}}}
+  begin
+    local_mem_dla : if dla_mem_enable=true generate
+      i_icon : icon
+        port map (
+          CONTROL0 => cs_control0
+      );
+
+      i_ila : ila_1024_63
+        port map (
+          CONTROL => cs_control0,
+          CLK     => cs_clk,
+          TRIG0   => cs_trig);
+
+      cs_clk       <= clk_ctl;
+
+      cs_trig(62) <= '0';
+      cs_trig(61 downto 52) <= "0000000000";
+
+      cs_trig(51 downto 20) <= mch_addr;
+      cs_trig(19 downto 12) <= mch_data;
+
+      cs_trig(11) <= hp_ddr_taken;
+      cs_trig(10) <= mch_ddr_rd_we;
+      cs_trig(9)  <= mch_valid;
+      cs_trig(8)  <= mch_ddr_taken;
+
+      cs_trig(7)  <= ena_sys;
+      cs_trig(6)  <= conf_valid;
+      cs_trig(5)  <= conf_write;
+      cs_trig(4)  <= conf_taken;
+
+      cs_trig(3)  <= mch_valid;
+      cs_trig(2)  <= mch_read;
+      cs_trig(1)  <= mch_rd_we;
+      cs_trig(0)  <= mch_taken;
+
+    end generate local_mem_dla;
+  end block dbg;
+end RTL;
Index: unmerged/changes_de1_to_mcc_summary
===================================================================
--- unmerged/changes_de1_to_mcc_summary	(nonexistent)
+++ unmerged/changes_de1_to_mcc_summary	(revision 1)
@@ -0,0 +1,41 @@
+diff -ur atari800core_20140301_de1/address_decoder.vhdl atari800core_v1_20140121_mcc216/address_decoder.vhdl
+diff -ur atari800core_20140301_de1/atari800core.qsf atari800core_v1_20140121_mcc216/atari800core.qsf
+diff -ur atari800core_20140301_de1/atari800core.qsf~ atari800core_v1_20140121_mcc216/atari800core.qsf~
+Only in atari800core_v1_20140121_mcc216: atari800core.qsf.bak
+Binary files atari800core_20140301_de1/atari800core.qws and atari800core_v1_20140121_mcc216/atari800core.qws differ
+diff -ur atari800core_20140301_de1/atari800core.sdc atari800core_v1_20140121_mcc216/atari800core.sdc
+Only in atari800core_20140301_de1: atari800core.sdc~
+Only in atari800core_v1_20140121_mcc216: atari800core.sdc.bak
+diff -ur atari800core_20140301_de1/atari800core.vhd atari800core_v1_20140121_mcc216/atari800core.vhd
+Only in atari800core_v1_20140121_mcc216: hq_dac.v
+Only in atari800core_v1_20140121_mcc216: internalromram.vhd
+Only in atari800core_v1_20140121_mcc216: internalromram.vhd.bak
+Only in atari800core_v1_20140121_mcc216: pll.bsf
+diff -ur atari800core_20140301_de1/pll.cmp atari800core_v1_20140121_mcc216/pll.cmp
+Only in atari800core_v1_20140121_mcc216: PLLJ_PLLSPE_INFO.txt
+diff -ur atari800core_20140301_de1/pll.ppf atari800core_v1_20140121_mcc216/pll.ppf
+diff -ur atari800core_20140301_de1/pll.qip atari800core_v1_20140121_mcc216/pll.qip
+diff -ur atari800core_20140301_de1/pll.vhd atari800core_v1_20140121_mcc216/pll.vhd
+Only in atari800core_v1_20140121_mcc216: pll.vhd.bak
+diff -ur atari800core_20140301_de1/pokey_ps2_decoder.vhdl atari800core_v1_20140121_mcc216/pokey_ps2_decoder.vhdl
+Only in atari800core_v1_20140121_mcc216: pokey_ps2_decoder.vhdl.bak
+Only in atari800core_v1_20140121_mcc216: ramint.bsf
+Only in atari800core_v1_20140121_mcc216: ramint.cmp
+Only in atari800core_v1_20140121_mcc216: ramint.qip
+Only in atari800core_v1_20140121_mcc216: ramint.vhd
+Only in atari800core_v1_20140121_mcc216: romhi.bsf
+Only in atari800core_v1_20140121_mcc216: romhi.cmp
+Only in atari800core_v1_20140121_mcc216: romhi.qip
+Only in atari800core_v1_20140121_mcc216: romhi.vhd
+Only in atari800core_v1_20140121_mcc216: romlo.bsf
+Only in atari800core_v1_20140121_mcc216: romlo.cmp
+Only in atari800core_v1_20140121_mcc216: romlo.qip
+Only in atari800core_v1_20140121_mcc216: romlo.vhd
+Only in atari800core_v1_20140121_mcc216: sdram_ctrl_4_ports.v
+Only in atari800core_v1_20140121_mcc216: sdram_ctrl_4_ports.v.bak
+Only in atari800core_v1_20140121_mcc216: sdram_statemachine_mcc.vhdl
+Only in atari800core_v1_20140121_mcc216: sdram_statemachine_mcc.vhdl.bak
+diff -ur atari800core_20140301_de1/sdram_statemachine.vhdl atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl
+Only in atari800core_v1_20140121_mcc216: sdram_statemachine.vhdl.bak
+diff -ur atari800core_20140301_de1/zpu/HelloTinyROM_ROM.mif atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif
+diff -ur atari800core_20140301_de1/zpu_config_regs.vhdl atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl
Index: unmerged/core/de1/COPYRIGHT_NOTICE
===================================================================
--- unmerged/core/de1/COPYRIGHT_NOTICE	(nonexistent)
+++ unmerged/core/de1/COPYRIGHT_NOTICE	(revision 1)
@@ -0,0 +1,129 @@
+(c) 2013 Mark Watson
+I am happy for anyone to use these for non-commercial use.
+If my vhdl files are used commercially or sold please contact me for explicit permission at scrameta@gmail.com.
+This applies for source and binary form and derived works.
+
+pokey.vhdl
+pokey_noise_filter.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_ps2_decoder.vhdl
+pokey_mixer.vhdl
+poly_4.vhdl
+poly_5.vhdl
+poly_17_9.vhdl
+
+gtia.vhdl
+gtia_priority.vhdl
+gtia_palette.vhdl // Palette data itself from laoo and Altirra
+gtia_player.vhdl
+
+antic.vhdl
+antic_dma_clock.vhdl
+antic_counter.vhdl
+
+pia.vhdl
+
+cpu.vhd
+shared_enable.vhdl
+irq_glue.vhdl
+
+ps2_keyboard.vhdl
+
+scandoubler.vhdl
+scandouble_ram_infer.vhdl
+
+zpu_glue.vhdl
+zpu_config_regs.vhdl
+
+// utils
+synchronizer.vhdl
+delay_line.vhdl
+wide_delay_line.vhdl
+reg_file.vhdl
+enable_divider.vhdl
+syncreset_enable_divider.vhd
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+simple_counter.vhdl
+
+// semi de1 specific
+sram.vhdl
+flashrom.vhdl
+sdram_statemachine.vhdl
+address_decoder.vhdl
+
+// de1 specific
+atari800core.vhd // top level for DE1
+i2sslave.vhdl
+hexdecoder.vhd
+gpio.vhd
+ledsw.vhd
+
+// altera megafunctions
+pll.vhd 
+zpu_ram.vhd
+zpu_rom.vhd
+
+-----------------------------------------------------------------------------------
+(c) Mike Stirling (from Spectrum core)
+See header for Mike's copyright note
+Parameters modified for my use case
+
+i2c_loader.vhd
+i2s_intf.vhd
+
+-----------------------------------------------------------------------------------
+(c) Peter Wendrich
+Please contact Peter if you wish to use them. I have permission for use as part of the Atari800 core.
+
+cpu_6510.vhd
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+
+-----------------------------------------------------------------------------------
+---- Copyright (c) 2008 Ãvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+ZPU implementation. See headers for more details
+I made a few fixes to make it work for my use case.
+
+zpu_core.vhd
+zpupkg.vhd
+
+-----------------------------------------------------------------------------------
+(c) Scott Larson
+See file header
+
+spi_master.vhd
+
+-----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+zpu/*.[ch]
+SD card/OSD
+-----------------------------------------------------------------------------------
+(c) Mark Watson
+Also some portions taken from SDrive, so (c) Bob and Raster
+
+I am happy for these to be used freely for commercial and non-commercial use.
+
+debug.h  led.h   pause.h  regs.h  types.h  uart.h
+bootdump.c  debug.c  led.c  main.c  regs.c  test.c  uart.c
+
+zpuromgen.c
+
+----------------------------------------------------------------------------------
+(c) Pascal Stang + Bob and Raster
+spi.c
+spi.h
+mmc.c  
+mmc.h
+mmcconf.h 
+
+-----------------------------------------------------------------------------------
+(c) ChaN
+Petit File System
+
+integer.h  
+diskio.h  
+pff.h
+pff.c  
Index: unmerged/core/de1/antic_dma_clock.vhdl
===================================================================
--- unmerged/core/de1/antic_dma_clock.vhdl	(nonexistent)
+++ unmerged/core/de1/antic_dma_clock.vhdl	(revision 1)
@@ -0,0 +1,74 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic_dma_clock IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	enable_dma : IN STD_LOGIC;
+	
+	playfield_start : in std_logic;
+	playfield_end : in std_logic;
+	vblank : in std_logic;
+	
+	slow_dma : in std_logic;
+	medium_dma : in std_logic;
+	fast_dma : in std_logic;
+	
+	dma_clock_out_0 : out std_logic;
+	dma_clock_out_1 : out std_logic;
+	dma_clock_out_2 : out std_logic;
+	dma_clock_out_3 : out std_logic
+);
+END antic_dma_clock;
+
+ARCHITECTURE vhdl OF antic_dma_clock IS
+	signal dma_shiftreg_next : std_logic_vector(7 downto 0);
+	signal dma_shiftreg_reg : std_logic_vector(7 downto 0);
+	
+	signal tick : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			dma_shiftreg_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			dma_shiftreg_reg <= dma_shiftreg_next;
+		end if;
+	end process;
+
+	-- next state
+	tick <=(dma_shiftreg_reg(0) and slow_dma) or (dma_shiftreg_reg(4) and medium_dma) or (dma_shiftreg_reg(6) and fast_dma);
+	process(enable_dma, dma_shiftreg_reg, playfield_start, playfield_end, vblank, slow_dma, medium_dma, fast_dma, tick)
+	begin
+		dma_shiftreg_next <= dma_shiftreg_reg;
+
+		if (enable_dma = '1') then			
+			dma_shiftreg_next <= 
+				not((playfield_start nor tick)
+				or playfield_end or vblank)				
+				&dma_shiftreg_reg(7 downto 1);
+		end if;
+		
+		if (playfield_start = '1') then
+			dma_shiftreg_next(7) <= not((playfield_start nor tick) or playfield_end or vblank);
+		end if;
+	end process;
+	
+	-- output
+	dma_clock_out_0 <= dma_shiftreg_reg(6) and enable_dma;
+	dma_clock_out_1 <= dma_shiftreg_reg(5) and enable_dma;
+	dma_clock_out_2 <= dma_shiftreg_reg(4) and enable_dma;
+	dma_clock_out_3 <= dma_shiftreg_reg(3) and enable_dma;
+	
+END vhdl;
Index: unmerged/core/de1/atari800core.qsf~
===================================================================
--- unmerged/core/de1/atari800core.qsf~	(nonexistent)
+++ unmerged/core/de1/atari800core.qsf~	(revision 1)
@@ -0,0 +1,586 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_V20 -to SD_CLK
+set_location_assignment PIN_Y20 -to SD_CMD
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_W20 -to SD_DATA
+set_location_assignment PIN_U20 -to SD_THREE
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name VHDL_FILE ledsw.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE dumprom.vhdl
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE nmigen.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE tvsync.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE flashrom.vhdl
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: unmerged/core/de1/atari800core.vhd
===================================================================
--- unmerged/core/de1/atari800core.vhd	(nonexistent)
+++ unmerged/core/de1/atari800core.vhd	(revision 1)
@@ -0,0 +1,1461 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLOCK_50 :  IN  STD_LOGIC;
+		AUD_BCLK :  IN  STD_LOGIC;
+		AUD_DACLRCK :  IN  STD_LOGIC;
+		PS2_CLK :  IN  STD_LOGIC;
+		PS2_DAT :  IN  STD_LOGIC;
+		UART_RXD :  IN  STD_LOGIC;
+		SD_DATA :  IN  STD_LOGIC;
+		I2C_SCLK :  INOUT  STD_LOGIC;
+		I2C_SDAT :  INOUT  STD_LOGIC;
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		AUD_XCK :  OUT  STD_LOGIC;
+		AUD_DACDAT :  OUT  STD_LOGIC;
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		FL_OE_N :  OUT  STD_LOGIC;
+		FL_WE_N :  OUT  STD_LOGIC;
+		FL_RST_N :  OUT  STD_LOGIC;
+		SRAM_CE_N :  OUT  STD_LOGIC;
+		SRAM_OE_N :  OUT  STD_LOGIC;
+		SRAM_WE_N :  OUT  STD_LOGIC;
+		SRAM_LB_N :  OUT  STD_LOGIC;
+		SRAM_UB_N :  OUT  STD_LOGIC;
+		UART_TXD :  OUT  STD_LOGIC;
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_THREE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT hexdecoder
+	PORT(CLK : IN STD_LOGIC;
+		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sram
+	PORT(WREN : IN STD_LOGIC;
+		 clk : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 request : IN STD_LOGIC;
+		 width_16bit : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_CE_N : OUT STD_LOGIC;
+		 SRAM_OE_N : OUT STD_LOGIC;
+		 SRAM_WE_N : OUT STD_LOGIC;
+		 SRAM_LB_N : OUT STD_LOGIC;
+		 SRAM_UB_N : OUT STD_LOGIC;
+		 complete : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT gpio
+	PORT(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+	);
+END COMPONENT;
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REPLY : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 REPLY : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT i2c_loader
+GENERIC (device_address : INTEGER;
+			log2_divider : INTEGER;
+			num_retries : INTEGER
+			);
+	PORT(CLK : IN STD_LOGIC;
+		 nRESET : IN STD_LOGIC;
+		 I2C_SCL : INOUT STD_LOGIC;
+		 I2C_SDA : INOUT STD_LOGIC;
+		 IS_DONE : OUT STD_LOGIC;
+		 IS_ERROR : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT flashrom
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_CE_N : OUT STD_LOGIC;
+		 FLASH_OE_N : OUT STD_LOGIC;
+		 FLASH_WE_N : OUT STD_LOGIC;
+		 FLASH_RESET_N : OUT STD_LOGIC;
+		 COMPLETE : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT i2sslave
+	PORT(CLK : IN STD_LOGIC;
+		 BCLK : IN STD_LOGIC;
+		 DACLRC : IN STD_LOGIC;
+		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 MCLK_2 : OUT STD_LOGIC;
+		 DACDAT : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+SIGNAL	CART_CCTL_N :  STD_LOGIC;
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+
+BEGIN 
+
+
+
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+
+b2v_hex0_inst : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(3 DOWNTO 0),
+		 DIGIT => HEX0);
+
+
+b2v_hex0_inst2 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(7 DOWNTO 4),
+		 DIGIT => HEX1);
+
+
+b2v_hex0_inst3 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(11 DOWNTO 8),
+		 DIGIT => HEX2);
+
+
+b2v_hex0_inst4 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(15 DOWNTO 12),
+		 DIGIT => HEX3);
+
+
+b2v_inst : sram
+PORT MAP(WREN => RAM_WRITE_ENABLE,
+		 clk => CLK,
+		 reset_n => RESET_N,
+		 request => RAM_REQUEST,
+		 width_16bit => WIDTH_16BIT_ACCESS,
+		 ADDRESS => RAM_ADDR,
+		 DIN => WRITE_DATA(15 DOWNTO 0),
+		 SRAM_DQ => SRAM_DQ,
+		 SRAM_CE_N => SRAM_CE_N,
+		 SRAM_OE_N => SRAM_OE_N,
+		 SRAM_WE_N => SRAM_WE_N,
+		 SRAM_LB_N => SRAM_LB_N,
+		 SRAM_UB_N => SRAM_UB_N,
+		 complete => RAM_REQUEST_COMPLETE,
+		 DOUT => RAM_DO,
+		 SRAM_ADDR => SRAM_ADDR);
+
+
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+
+b2v_inst10 : ledsw
+PORT MAP(CLK => CLK,
+		 KEY => KEY,
+		 SW => SW,
+		 SYNC_KEYS => SYNC_KEYS,
+		 SYNC_SWITCHES => SYNC_SWITCHES);
+
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2_CLK,
+		 PS2_DAT => PS2_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+b2v_inst18 : pokey_ps2_decoder
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_CODE => SYNTHESIZED_WIRE_11,
+		 KEY_HELD => KEY_HELD,
+		 SHIFT_PRESSED => SHIFT_PRESSED,
+		 BREAK_PRESSED => BREAK_PRESSED,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+		 KBCODE => KBCODE,
+		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
+
+gpio0_gen:
+   for I in 0 to 35 generate
+		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+   end generate gpio0_gen;
+
+gpio1_gen:
+   for I in 0 to 35 generate
+		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+   end generate gpio1_gen;
+	
+b2v_inst19 : gpio
+PORT MAP(clk => CLK,
+		 gpio_enable => GPIO_ENABLE,
+		 pot_reset => POT_RESET,
+		 virtual_keyheld => KEY_HELD,
+		 virtual_shift_pressed => SHIFT_PRESSED,
+		 virtual_control_pressed => KBCODE(7),
+		 virtual_break_pressed => BREAK_PRESSED,
+		 pbi_write_enable => PBI_WRITE_ENABLE,
+		 cart_request => CART_REQUEST,
+		 s4_n => CART_S4_n,
+		 s5_n => CART_S5_N,
+		 cctl_n => CART_CCTL_N,
+		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+		 GPIO_0_IN => GPIO_0,
+		 GPIO_0_OUT => GPIO_0_OUT,
+		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+		 GPIO_1_IN => GPIO_1,
+		 GPIO_1_OUT => GPIO_1_OUT,
+		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN,
+		 pbi_addr_out => PBI_ADDR,
+		 porta_out => PORTA_OUT,
+		 porta_output => PORTA_DIR_OUT,
+		 virtual_keycode => KBCODE(5 DOWNTO 0),
+		 virtual_stick_in => VIRTUAL_STICKS,
+		 virtual_trig_in => VIRTUAL_TRIGGERS,
+		 lightpen => LIGHTPEN,
+		 cart_complete => CART_REQUEST_COMPLETE,
+		 rd4 => CART_RD4,
+		 rd5 => CART_RD5,
+		 cart_data_read => CART_ROM_DO,
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 porta_in => GPIO_PORTA_IN,
+		 pot_in => POT_IN,
+		 trig_in => TRIGGERS,
+		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_OUT => CA2_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_OUT => CB2_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 SIO_IN => GPIO_SIO_IN,
+		 SIO_OUT => GPIO_SIO_OUT
+		 );
+
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REPLY => SDRAM_REPLY,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT,
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT,
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA);
+
+
+b2v_inst20 : sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => DRAM_DQ,
+		 REPLY => SDRAM_REPLY,
+		 SDRAM_BA0 => DRAM_BA_0,
+		 SDRAM_BA1 => DRAM_BA_1,
+		 SDRAM_CKE => DRAM_CKE,
+		 SDRAM_CS_N => DRAM_CS_N,
+		 SDRAM_RAS_N => DRAM_RAS_N,
+		 SDRAM_CAS_N => DRAM_CAS_N,
+		 SDRAM_WE_N => DRAM_WE_N,
+		 SDRAM_ldqm => DRAM_LDQM,
+		 SDRAM_udqm => DRAM_UDQM,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => DRAM_ADDR);
+
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DATA,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_THREE,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG,
+		 LEDR => LEDR,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX);
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst3 : i2c_loader
+GENERIC MAP(device_address => 26,
+			log2_divider => 6,
+			num_retries => 0
+			)
+PORT MAP(CLK => CLK,
+		 nRESET => RESET_N,
+		 I2C_SCL => I2C_SCLK,
+		 I2C_SDA => I2C_SDAT);
+
+
+b2v_inst4 : flashrom
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 REQUEST => ROM_REQUEST,
+		 ADDRESS => ROM_ADDR,
+		 FLASH_D => FL_DQ,
+		 FLASH_OE_N => FL_OE_N,
+		 FLASH_WE_N => FL_WE_N,
+		 FLASH_RESET_N => FL_RST_N,
+		 COMPLETE => ROM_REQUEST_COMPLETE,
+		 DOUT => ROM_DO,
+		 FLASH_ADDRESS => FL_ADDR);
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => CLOCK_50,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+
+
+b2v_inst6 : i2sslave
+PORT MAP(CLK => CLK,
+		 BCLK => AUD_BCLK,
+		 DACLRC => AUD_DACLRCK,
+		 LEFT_IN => AUDIO_LEFT,
+		 RIGHT_IN => AUDIO_RIGHT,
+		 MCLK_2 => AUD_XCK,
+		 DACDAT => AUD_DACDAT);
+
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => UART_RXD,
+		 SIO_IN2 => GPIO_SIO_IN,
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => TRIGGERS(0),
+		 TRIG1 => TRIGGERS(1),
+		 TRIG2 => TRIGGERS(2),
+		 TRIG3 => TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+END bdf_type;
\ No newline at end of file
Index: unmerged/core/de1/cpu_6510.vhd
===================================================================
--- unmerged/core/de1/cpu_6510.vhd	(nonexistent)
+++ unmerged/core/de1/cpu_6510.vhd	(revision 1)
@@ -0,0 +1,201 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- 6510 wrapper for 65xx core
+-- Adds 8 bit I/O port mapped at addresses $0000 to $0001
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_6510 is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean;
+		emulate_bitfade : boolean
+	);
+	port (
+		clk : in std_logic;
+		ena_1khz : in std_logic := '0';
+		enable : in std_logic;
+		halt : in std_logic;
+		reset : in std_logic;
+		nmi_n : in std_logic;
+		irq_n : in std_logic;
+
+		we : out std_logic;
+		a : out unsigned(15 downto 0);
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+
+		diIO : in unsigned(7 downto 0);
+		doIO : out unsigned(7 downto 0);
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0);
+		debug_io : out unsigned(7 downto 0)
+	);
+end cpu_6510;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_6510 is
+	signal localA : unsigned(15 downto 0);
+	signal localD : unsigned(7 downto 0);
+	signal localQ : unsigned(7 downto 0);
+	signal localWe : std_logic;
+
+	signal currentIO : unsigned(7 downto 0);
+	signal ioDir : unsigned(7 downto 0);
+	signal ioData : unsigned(7 downto 0);
+	
+	signal accessIO : std_logic;
+	signal ioFade : unsigned(7 downto 0) := (others => '0');
+begin
+	cpuInstance: entity work.cpu_65xx
+		generic map (
+			pipelineOpcode => pipelineOpcode,
+			pipelineAluMux => pipelineAluMux,
+			pipelineAluOut => pipelineAluOut
+		)
+		port map (
+			clk => clk,
+			enable => enable,
+			halt => halt,
+			reset => reset,
+			nmi_n => nmi_n,
+			irq_n => irq_n,
+
+			d => localD,
+			q => localQ,
+			addr => localA,
+			we => localWe,
+
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugY,
+			debugS => debugS,
+			debug_flags => debug_flags
+		);
+	
+	MyBitfade: if emulate_bitfade generate
+		bitfade7 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(7),
+				d => ioData(7),
+				q => ioFade(7)
+			);
+		bitfade6 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(6),
+				d => ioData(6),
+				q => ioFade(6)
+			);
+		bitfade3 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(3),
+				d => ioData(3),
+				q => ioFade(3)
+			);
+	end generate;
+	
+	process(localA)
+	begin
+		accessIO <= '0';
+		if localA(15 downto 1) = 0 then
+			accessIO <= '1';
+		end if;
+	end process;
+	
+	process(d, localA, ioDir, currentIO, accessIO)
+	begin
+		localD <= d;
+		if accessIO = '1' then
+			if localA(0) = '0' then
+				localD <= ioDir;
+			else
+				localD <= currentIO;
+			end if;
+		end if;
+	end process;
+	
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if accessIO = '1' then
+				if localWe = '1'
+				and enable = '1' then
+					if localA(0) = '0' then
+						ioDir <= localQ;
+					else
+						ioData <= localQ;
+					end if;
+				end if;
+			end if;
+			if reset = '1' then
+				ioDir <= (others => '0');
+			end if;
+		end if;
+	end process;
+	
+	process(ioDir, ioData, diIO)
+	begin
+		for i in 0 to 7 loop
+			if ioDir(i) = '0' then
+				currentIO(i) <= diIO(i);
+			else
+				currentIO(i) <= ioData(i);
+			end if;
+		end loop;
+		if emulate_bitfade then
+			currentIO(7) <= ioFade(7);
+			currentIO(6) <= ioFade(6);
+			currentIO(3) <= ioFade(3);
+		end if;
+	end process;
+	
+	-- Cunnect zee wires
+	a <= localA;
+	q <= localQ;
+	we <= localWe;
+	doIO <= currentIO;
+	debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
+end architecture;
Index: unmerged/core/de1/enable_divider.vhdl
===================================================================
--- unmerged/core/de1/enable_divider.vhdl	(nonexistent)
+++ unmerged/core/de1/enable_divider.vhdl	(revision 1)
@@ -0,0 +1,76 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY enable_divider IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END enable_divider;
+
+ARCHITECTURE vhdl OF enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: unmerged/core/de1/gtia_palette.vhdl
===================================================================
--- unmerged/core/de1/gtia_palette.vhdl	(nonexistent)
+++ unmerged/core/de1/gtia_palette.vhdl	(revision 1)
@@ -0,0 +1,2092 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_palette IS
+PORT 
+( 
+	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+);
+END gtia_palette;
+
+ARCHITECTURE altirra OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+				when X"00" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"01" =>
+					R_next <= X"11";
+					G_next <= X"11";
+					B_next <= X"11";
+				when X"02" =>
+					R_next <= X"22";
+					G_next <= X"22";
+					B_next <= X"22";
+				when X"03" =>
+					R_next <= X"33";
+					G_next <= X"33";
+					B_next <= X"33";
+				when X"04" =>
+					R_next <= X"44";
+					G_next <= X"44";
+					B_next <= X"44";
+				when X"05" =>
+					R_next <= X"55";
+					G_next <= X"55";
+					B_next <= X"55";
+				when X"06" =>
+					R_next <= X"66";
+					G_next <= X"66";
+					B_next <= X"66";
+				when X"07" =>
+					R_next <= X"77";
+					G_next <= X"77";
+					B_next <= X"77";
+				when X"08" =>
+					R_next <= X"88";
+					G_next <= X"88";
+					B_next <= X"88";
+				when X"09" =>
+					R_next <= X"99";
+					G_next <= X"99";
+					B_next <= X"99";
+				when X"0a" =>
+					R_next <= X"aa";
+					G_next <= X"aa";
+					B_next <= X"aa";
+				when X"0b" =>
+					R_next <= X"bb";
+					G_next <= X"bb";
+					B_next <= X"bb";
+				when X"0c" =>
+					R_next <= X"cc";
+					G_next <= X"cc";
+					B_next <= X"cc";
+				when X"0d" =>
+					R_next <= X"dd";
+					G_next <= X"dd";
+					B_next <= X"dd";
+				when X"0e" =>
+					R_next <= X"ee";
+					G_next <= X"ee";
+					B_next <= X"ee";
+				when X"0f" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"10" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"11" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"12" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"13" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"14" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"15" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"16" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"17" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"18" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"19" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"1a" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"1b" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"1c" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"1d" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"1e" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"1f" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+				when X"20" =>
+					R_next <= X"50";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"21" =>
+					R_next <= X"61";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"22" =>
+					R_next <= X"72";
+					G_next <= X"03";
+					B_next <= X"00";
+				when X"23" =>
+					R_next <= X"83";
+					G_next <= X"14";
+					B_next <= X"03";
+				when X"24" =>
+					R_next <= X"94";
+					G_next <= X"25";
+					B_next <= X"14";
+				when X"25" =>
+					R_next <= X"a5";
+					G_next <= X"36";
+					B_next <= X"25";
+				when X"26" =>
+					R_next <= X"b6";
+					G_next <= X"47";
+					B_next <= X"36";
+				when X"27" =>
+					R_next <= X"c7";
+					G_next <= X"58";
+					B_next <= X"47";
+				when X"28" =>
+					R_next <= X"d8";
+					G_next <= X"69";
+					B_next <= X"58";
+				when X"29" =>
+					R_next <= X"e9";
+					G_next <= X"7a";
+					B_next <= X"69";
+				when X"2a" =>
+					R_next <= X"fa";
+					G_next <= X"8b";
+					B_next <= X"7a";
+				when X"2b" =>
+					R_next <= X"ff";
+					G_next <= X"9c";
+					B_next <= X"8b";
+				when X"2c" =>
+					R_next <= X"ff";
+					G_next <= X"ad";
+					B_next <= X"9c";
+				when X"2d" =>
+					R_next <= X"ff";
+					G_next <= X"be";
+					B_next <= X"ad";
+				when X"2e" =>
+					R_next <= X"ff";
+					G_next <= X"cf";
+					B_next <= X"be";
+				when X"2f" =>
+					R_next <= X"ff";
+					G_next <= X"e0";
+					B_next <= X"cf";
+				when X"30" =>
+					R_next <= X"54";
+					G_next <= X"00";
+					B_next <= X"03";
+				when X"31" =>
+					R_next <= X"65";
+					G_next <= X"00";
+					B_next <= X"14";
+				when X"32" =>
+					R_next <= X"76";
+					G_next <= X"00";
+					B_next <= X"25";
+				when X"33" =>
+					R_next <= X"87";
+					G_next <= X"08";
+					B_next <= X"36";
+				when X"34" =>
+					R_next <= X"98";
+					G_next <= X"19";
+					B_next <= X"47";
+				when X"35" =>
+					R_next <= X"a9";
+					G_next <= X"2a";
+					B_next <= X"58";
+				when X"36" =>
+					R_next <= X"ba";
+					G_next <= X"3b";
+					B_next <= X"69";
+				when X"37" =>
+					R_next <= X"cb";
+					G_next <= X"4c";
+					B_next <= X"7a";
+				when X"38" =>
+					R_next <= X"dc";
+					G_next <= X"5d";
+					B_next <= X"8b";
+				when X"39" =>
+					R_next <= X"ed";
+					G_next <= X"6e";
+					B_next <= X"9c";
+				when X"3a" =>
+					R_next <= X"fe";
+					G_next <= X"7f";
+					B_next <= X"ad";
+				when X"3b" =>
+					R_next <= X"ff";
+					G_next <= X"90";
+					B_next <= X"be";
+				when X"3c" =>
+					R_next <= X"ff";
+					G_next <= X"a1";
+					B_next <= X"cf";
+				when X"3d" =>
+					R_next <= X"ff";
+					G_next <= X"b2";
+					B_next <= X"e0";
+				when X"3e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"f1";
+				when X"3f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"40" =>
+					R_next <= X"4f";
+					G_next <= X"00";
+					B_next <= X"35";
+				when X"41" =>
+					R_next <= X"60";
+					G_next <= X"00";
+					B_next <= X"46";
+				when X"42" =>
+					R_next <= X"71";
+					G_next <= X"00";
+					B_next <= X"57";
+				when X"43" =>
+					R_next <= X"82";
+					G_next <= X"01";
+					B_next <= X"68";
+				when X"44" =>
+					R_next <= X"93";
+					G_next <= X"12";
+					B_next <= X"79";
+				when X"45" =>
+					R_next <= X"a4";
+					G_next <= X"23";
+					B_next <= X"8a";
+				when X"46" =>
+					R_next <= X"b5";
+					G_next <= X"34";
+					B_next <= X"9b";
+				when X"47" =>
+					R_next <= X"c6";
+					G_next <= X"45";
+					B_next <= X"ac";
+				when X"48" =>
+					R_next <= X"d7";
+					G_next <= X"56";
+					B_next <= X"bd";
+				when X"49" =>
+					R_next <= X"e8";
+					G_next <= X"67";
+					B_next <= X"ce";
+				when X"4a" =>
+					R_next <= X"f9";
+					G_next <= X"78";
+					B_next <= X"df";
+				when X"4b" =>
+					R_next <= X"ff";
+					G_next <= X"89";
+					B_next <= X"f0";
+				when X"4c" =>
+					R_next <= X"ff";
+					G_next <= X"9a";
+					B_next <= X"ff";
+				when X"4d" =>
+					R_next <= X"ff";
+					G_next <= X"ab";
+					B_next <= X"ff";
+				when X"4e" =>
+					R_next <= X"ff";
+					G_next <= X"bc";
+					B_next <= X"ff";
+				when X"4f" =>
+					R_next <= X"ff";
+					G_next <= X"cd";
+					B_next <= X"ff";
+				when X"50" =>
+					R_next <= X"3d";
+					G_next <= X"00";
+					B_next <= X"68";
+				when X"51" =>
+					R_next <= X"4e";
+					G_next <= X"00";
+					B_next <= X"79";
+				when X"52" =>
+					R_next <= X"5f";
+					G_next <= X"00";
+					B_next <= X"8a";
+				when X"53" =>
+					R_next <= X"70";
+					G_next <= X"00";
+					B_next <= X"9b";
+				when X"54" =>
+					R_next <= X"81";
+					G_next <= X"11";
+					B_next <= X"ac";
+				when X"55" =>
+					R_next <= X"92";
+					G_next <= X"22";
+					B_next <= X"bd";
+				when X"56" =>
+					R_next <= X"a3";
+					G_next <= X"33";
+					B_next <= X"ce";
+				when X"57" =>
+					R_next <= X"b4";
+					G_next <= X"44";
+					B_next <= X"df";
+				when X"58" =>
+					R_next <= X"c5";
+					G_next <= X"55";
+					B_next <= X"f0";
+				when X"59" =>
+					R_next <= X"d6";
+					G_next <= X"66";
+					B_next <= X"ff";
+				when X"5a" =>
+					R_next <= X"e7";
+					G_next <= X"77";
+					B_next <= X"ff";
+				when X"5b" =>
+					R_next <= X"f8";
+					G_next <= X"88";
+					B_next <= X"ff";
+				when X"5c" =>
+					R_next <= X"ff";
+					G_next <= X"99";
+					B_next <= X"ff";
+				when X"5d" =>
+					R_next <= X"ff";
+					G_next <= X"aa";
+					B_next <= X"ff";
+				when X"5e" =>
+					R_next <= X"ff";
+					G_next <= X"bb";
+					B_next <= X"ff";
+				when X"5f" =>
+					R_next <= X"ff";
+					G_next <= X"cc";
+					B_next <= X"ff";
+				when X"60" =>
+					R_next <= X"20";
+					G_next <= X"00";
+					B_next <= X"8b";
+				when X"61" =>
+					R_next <= X"31";
+					G_next <= X"00";
+					B_next <= X"9c";
+				when X"62" =>
+					R_next <= X"42";
+					G_next <= X"00";
+					B_next <= X"ad";
+				when X"63" =>
+					R_next <= X"53";
+					G_next <= X"08";
+					B_next <= X"be";
+				when X"64" =>
+					R_next <= X"64";
+					G_next <= X"19";
+					B_next <= X"cf";
+				when X"65" =>
+					R_next <= X"75";
+					G_next <= X"2a";
+					B_next <= X"e0";
+				when X"66" =>
+					R_next <= X"86";
+					G_next <= X"3b";
+					B_next <= X"f1";
+				when X"67" =>
+					R_next <= X"97";
+					G_next <= X"4c";
+					B_next <= X"ff";
+				when X"68" =>
+					R_next <= X"a8";
+					G_next <= X"5d";
+					B_next <= X"ff";
+				when X"69" =>
+					R_next <= X"b9";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"6a" =>
+					R_next <= X"ca";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"6b" =>
+					R_next <= X"db";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"6c" =>
+					R_next <= X"ec";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"6d" =>
+					R_next <= X"fd";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"6e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"6f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"70" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"89";
+				when X"71" =>
+					R_next <= X"00";
+					G_next <= X"08";
+					B_next <= X"9a";
+				when X"72" =>
+					R_next <= X"00";
+					G_next <= X"19";
+					B_next <= X"ab";
+				when X"73" =>
+					R_next <= X"10";
+					G_next <= X"2a";
+					B_next <= X"bc";
+				when X"74" =>
+					R_next <= X"21";
+					G_next <= X"3b";
+					B_next <= X"cd";
+				when X"75" =>
+					R_next <= X"32";
+					G_next <= X"4c";
+					B_next <= X"de";
+				when X"76" =>
+					R_next <= X"43";
+					G_next <= X"5d";
+					B_next <= X"ef";
+				when X"77" =>
+					R_next <= X"54";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"78" =>
+					R_next <= X"65";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"79" =>
+					R_next <= X"76";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"7a" =>
+					R_next <= X"87";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"7b" =>
+					R_next <= X"98";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"7c" =>
+					R_next <= X"a9";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"7d" =>
+					R_next <= X"ba";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"7e" =>
+					R_next <= X"cb";
+					G_next <= X"e5";
+					B_next <= X"ff";
+				when X"7f" =>
+					R_next <= X"dc";
+					G_next <= X"f6";
+					B_next <= X"ff";
+				when X"80" =>
+					R_next <= X"00";
+					G_next <= X"0c";
+					B_next <= X"65";
+				when X"81" =>
+					R_next <= X"00";
+					G_next <= X"1d";
+					B_next <= X"76";
+				when X"82" =>
+					R_next <= X"00";
+					G_next <= X"2e";
+					B_next <= X"87";
+				when X"83" =>
+					R_next <= X"00";
+					G_next <= X"3f";
+					B_next <= X"98";
+				when X"84" =>
+					R_next <= X"05";
+					G_next <= X"50";
+					B_next <= X"a9";
+				when X"85" =>
+					R_next <= X"16";
+					G_next <= X"61";
+					B_next <= X"ba";
+				when X"86" =>
+					R_next <= X"27";
+					G_next <= X"72";
+					B_next <= X"cb";
+				when X"87" =>
+					R_next <= X"38";
+					G_next <= X"83";
+					B_next <= X"dc";
+				when X"88" =>
+					R_next <= X"49";
+					G_next <= X"94";
+					B_next <= X"ed";
+				when X"89" =>
+					R_next <= X"5a";
+					G_next <= X"a5";
+					B_next <= X"fe";
+				when X"8a" =>
+					R_next <= X"6b";
+					G_next <= X"b6";
+					B_next <= X"ff";
+				when X"8b" =>
+					R_next <= X"7c";
+					G_next <= X"c7";
+					B_next <= X"ff";
+				when X"8c" =>
+					R_next <= X"8d";
+					G_next <= X"d8";
+					B_next <= X"ff";
+				when X"8d" =>
+					R_next <= X"9e";
+					G_next <= X"e9";
+					B_next <= X"ff";
+				when X"8e" =>
+					R_next <= X"af";
+					G_next <= X"fa";
+					B_next <= X"ff";
+				when X"8f" =>
+					R_next <= X"c0";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"90" =>
+					R_next <= X"00";
+					G_next <= X"1f";
+					B_next <= X"30";
+				when X"91" =>
+					R_next <= X"00";
+					G_next <= X"30";
+					B_next <= X"41";
+				when X"92" =>
+					R_next <= X"00";
+					G_next <= X"41";
+					B_next <= X"52";
+				when X"93" =>
+					R_next <= X"00";
+					G_next <= X"52";
+					B_next <= X"63";
+				when X"94" =>
+					R_next <= X"00";
+					G_next <= X"63";
+					B_next <= X"74";
+				when X"95" =>
+					R_next <= X"05";
+					G_next <= X"74";
+					B_next <= X"85";
+				when X"96" =>
+					R_next <= X"16";
+					G_next <= X"85";
+					B_next <= X"96";
+				when X"97" =>
+					R_next <= X"27";
+					G_next <= X"96";
+					B_next <= X"a7";
+				when X"98" =>
+					R_next <= X"38";
+					G_next <= X"a7";
+					B_next <= X"b8";
+				when X"99" =>
+					R_next <= X"49";
+					G_next <= X"b8";
+					B_next <= X"c9";
+				when X"9a" =>
+					R_next <= X"5a";
+					G_next <= X"c9";
+					B_next <= X"da";
+				when X"9b" =>
+					R_next <= X"6b";
+					G_next <= X"da";
+					B_next <= X"eb";
+				when X"9c" =>
+					R_next <= X"7c";
+					G_next <= X"eb";
+					B_next <= X"fc";
+				when X"9d" =>
+					R_next <= X"8d";
+					G_next <= X"fc";
+					B_next <= X"ff";
+				when X"9e" =>
+					R_next <= X"9e";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"9f" =>
+					R_next <= X"af";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"a0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"a1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"0e";
+				when X"a2" =>
+					R_next <= X"00";
+					G_next <= X"4d";
+					B_next <= X"1f";
+				when X"a3" =>
+					R_next <= X"00";
+					G_next <= X"5e";
+					B_next <= X"30";
+				when X"a4" =>
+					R_next <= X"00";
+					G_next <= X"6f";
+					B_next <= X"41";
+				when X"a5" =>
+					R_next <= X"01";
+					G_next <= X"80";
+					B_next <= X"52";
+				when X"a6" =>
+					R_next <= X"12";
+					G_next <= X"91";
+					B_next <= X"63";
+				when X"a7" =>
+					R_next <= X"23";
+					G_next <= X"a2";
+					B_next <= X"74";
+				when X"a8" =>
+					R_next <= X"34";
+					G_next <= X"b3";
+					B_next <= X"85";
+				when X"a9" =>
+					R_next <= X"45";
+					G_next <= X"c4";
+					B_next <= X"96";
+				when X"aa" =>
+					R_next <= X"56";
+					G_next <= X"d5";
+					B_next <= X"a7";
+				when X"ab" =>
+					R_next <= X"67";
+					G_next <= X"e6";
+					B_next <= X"b8";
+				when X"ac" =>
+					R_next <= X"78";
+					G_next <= X"f7";
+					B_next <= X"c9";
+				when X"ad" =>
+					R_next <= X"89";
+					G_next <= X"ff";
+					B_next <= X"da";
+				when X"ae" =>
+					R_next <= X"9a";
+					G_next <= X"ff";
+					B_next <= X"eb";
+				when X"af" =>
+					R_next <= X"ab";
+					G_next <= X"ff";
+					B_next <= X"fc";
+				when X"b0" =>
+					R_next <= X"00";
+					G_next <= X"33";
+					B_next <= X"00";
+				when X"b1" =>
+					R_next <= X"00";
+					G_next <= X"44";
+					B_next <= X"00";
+				when X"b2" =>
+					R_next <= X"00";
+					G_next <= X"55";
+					B_next <= X"00";
+				when X"b3" =>
+					R_next <= X"00";
+					G_next <= X"66";
+					B_next <= X"00";
+				when X"b4" =>
+					R_next <= X"07";
+					G_next <= X"77";
+					B_next <= X"00";
+				when X"b5" =>
+					R_next <= X"18";
+					G_next <= X"88";
+					B_next <= X"00";
+				when X"b6" =>
+					R_next <= X"29";
+					G_next <= X"99";
+					B_next <= X"00";
+				when X"b7" =>
+					R_next <= X"3a";
+					G_next <= X"aa";
+					B_next <= X"0f";
+				when X"b8" =>
+					R_next <= X"4b";
+					G_next <= X"bb";
+					B_next <= X"20";
+				when X"b9" =>
+					R_next <= X"5c";
+					G_next <= X"cc";
+					B_next <= X"31";
+				when X"ba" =>
+					R_next <= X"6d";
+					G_next <= X"dd";
+					B_next <= X"42";
+				when X"bb" =>
+					R_next <= X"7e";
+					G_next <= X"ee";
+					B_next <= X"53";
+				when X"bc" =>
+					R_next <= X"8f";
+					G_next <= X"ff";
+					B_next <= X"64";
+				when X"bd" =>
+					R_next <= X"a0";
+					G_next <= X"ff";
+					B_next <= X"75";
+				when X"be" =>
+					R_next <= X"b1";
+					G_next <= X"ff";
+					B_next <= X"86";
+				when X"bf" =>
+					R_next <= X"c2";
+					G_next <= X"ff";
+					B_next <= X"97";
+				when X"c0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"c1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"c2" =>
+					R_next <= X"02";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"c3" =>
+					R_next <= X"13";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"c4" =>
+					R_next <= X"24";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"c5" =>
+					R_next <= X"35";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"c6" =>
+					R_next <= X"46";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"c7" =>
+					R_next <= X"57";
+					G_next <= X"a2";
+					B_next <= X"00";
+				when X"c8" =>
+					R_next <= X"68";
+					G_next <= X"b3";
+					B_next <= X"00";
+				when X"c9" =>
+					R_next <= X"79";
+					G_next <= X"c4";
+					B_next <= X"0e";
+				when X"ca" =>
+					R_next <= X"8a";
+					G_next <= X"d5";
+					B_next <= X"1f";
+				when X"cb" =>
+					R_next <= X"9b";
+					G_next <= X"e6";
+					B_next <= X"30";
+				when X"cc" =>
+					R_next <= X"ac";
+					G_next <= X"f7";
+					B_next <= X"41";
+				when X"cd" =>
+					R_next <= X"bd";
+					G_next <= X"ff";
+					B_next <= X"52";
+				when X"ce" =>
+					R_next <= X"ce";
+					G_next <= X"ff";
+					B_next <= X"63";
+				when X"cf" =>
+					R_next <= X"df";
+					G_next <= X"ff";
+					B_next <= X"74";
+				when X"d0" =>
+					R_next <= X"01";
+					G_next <= X"1c";
+					B_next <= X"00";
+				when X"d1" =>
+					R_next <= X"12";
+					G_next <= X"2d";
+					B_next <= X"00";
+				when X"d2" =>
+					R_next <= X"23";
+					G_next <= X"3e";
+					B_next <= X"00";
+				when X"d3" =>
+					R_next <= X"34";
+					G_next <= X"4f";
+					B_next <= X"00";
+				when X"d4" =>
+					R_next <= X"45";
+					G_next <= X"60";
+					B_next <= X"00";
+				when X"d5" =>
+					R_next <= X"56";
+					G_next <= X"71";
+					B_next <= X"00";
+				when X"d6" =>
+					R_next <= X"67";
+					G_next <= X"82";
+					B_next <= X"00";
+				when X"d7" =>
+					R_next <= X"78";
+					G_next <= X"93";
+					B_next <= X"00";
+				when X"d8" =>
+					R_next <= X"89";
+					G_next <= X"a4";
+					B_next <= X"00";
+				when X"d9" =>
+					R_next <= X"9a";
+					G_next <= X"b5";
+					B_next <= X"03";
+				when X"da" =>
+					R_next <= X"ab";
+					G_next <= X"c6";
+					B_next <= X"14";
+				when X"db" =>
+					R_next <= X"bc";
+					G_next <= X"d7";
+					B_next <= X"25";
+				when X"dc" =>
+					R_next <= X"cd";
+					G_next <= X"e8";
+					B_next <= X"36";
+				when X"dd" =>
+					R_next <= X"de";
+					G_next <= X"f9";
+					B_next <= X"47";
+				when X"de" =>
+					R_next <= X"ef";
+					G_next <= X"ff";
+					B_next <= X"58";
+				when X"df" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"69";
+				when X"e0" =>
+					R_next <= X"23";
+					G_next <= X"09";
+					B_next <= X"00";
+				when X"e1" =>
+					R_next <= X"34";
+					G_next <= X"1a";
+					B_next <= X"00";
+				when X"e2" =>
+					R_next <= X"45";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"e3" =>
+					R_next <= X"56";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"e4" =>
+					R_next <= X"67";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"e5" =>
+					R_next <= X"78";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"e6" =>
+					R_next <= X"89";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"e7" =>
+					R_next <= X"9a";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"e8" =>
+					R_next <= X"ab";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"e9" =>
+					R_next <= X"bc";
+					G_next <= X"a2";
+					B_next <= X"10";
+				when X"ea" =>
+					R_next <= X"cd";
+					G_next <= X"b3";
+					B_next <= X"21";
+				when X"eb" =>
+					R_next <= X"de";
+					G_next <= X"c4";
+					B_next <= X"32";
+				when X"ec" =>
+					R_next <= X"ef";
+					G_next <= X"d5";
+					B_next <= X"43";
+				when X"ed" =>
+					R_next <= X"ff";
+					G_next <= X"e6";
+					B_next <= X"54";
+				when X"ee" =>
+					R_next <= X"ff";
+					G_next <= X"f7";
+					B_next <= X"65";
+				when X"ef" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"76";
+				when X"f0" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"f1" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"f2" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"f3" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"f4" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"f5" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"f6" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"f7" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"f8" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"f9" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"fa" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"fb" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"fc" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"fd" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"fe" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"ff" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+			end case;
+			
+		end process;
+		
+end altirra;
+
+
+ARCHITECTURE laoo OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+					when X"00" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"01" =>
+						R_next <= X"0e";
+						G_next <= X"0d";
+						B_next <= X"0e";
+					when X"02" =>
+						R_next <= X"1d";
+						G_next <= X"1d";
+						B_next <= X"1d";
+					when X"03" =>
+						R_next <= X"2e";
+						G_next <= X"2d";
+						B_next <= X"2e";
+					when X"04" =>
+						R_next <= X"3e";
+						G_next <= X"3d";
+						B_next <= X"3e";
+					when X"05" =>
+						R_next <= X"4f";
+						G_next <= X"4e";
+						B_next <= X"4f";
+					when X"06" =>
+						R_next <= X"5f";
+						G_next <= X"5e";
+						B_next <= X"5f";
+					when X"07" =>
+						R_next <= X"70";
+						G_next <= X"6f";
+						B_next <= X"6f";
+					when X"08" =>
+						R_next <= X"7a";
+						G_next <= X"7a";
+						B_next <= X"79";
+					when X"09" =>
+						R_next <= X"8b";
+						G_next <= X"8a";
+						B_next <= X"8b";
+					when X"0a" =>
+						R_next <= X"9c";
+						G_next <= X"9b";
+						B_next <= X"9b";
+					when X"0b" =>
+						R_next <= X"ad";
+						G_next <= X"ac";
+						B_next <= X"ac";
+					when X"0c" =>
+						R_next <= X"bc";
+						G_next <= X"bb";
+						B_next <= X"bb";
+					when X"0d" =>
+						R_next <= X"cd";
+						G_next <= X"cc";
+						B_next <= X"cd";
+					when X"0e" =>
+						R_next <= X"dc";
+						G_next <= X"db";
+						B_next <= X"dc";
+					when X"0f" =>
+						R_next <= X"ec";
+						G_next <= X"ec";
+						B_next <= X"ec";
+					when X"10" =>
+						R_next <= X"35";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"11" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"12" =>
+						R_next <= X"4f";
+						G_next <= X"14";
+						B_next <= X"00";
+					when X"13" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"14" =>
+						R_next <= X"6e";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"15" =>
+						R_next <= X"7f";
+						G_next <= X"45";
+						B_next <= X"03";
+					when X"16" =>
+						R_next <= X"8e";
+						G_next <= X"55";
+						B_next <= X"13";
+					when X"17" =>
+						R_next <= X"9f";
+						G_next <= X"66";
+						B_next <= X"23";
+					when X"18" =>
+						R_next <= X"a9";
+						G_next <= X"71";
+						B_next <= X"2d";
+					when X"19" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"1a" =>
+						R_next <= X"ca";
+						G_next <= X"92";
+						B_next <= X"50";
+					when X"1b" =>
+						R_next <= X"db";
+						G_next <= X"a3";
+						B_next <= X"61";
+					when X"1c" =>
+						R_next <= X"ea";
+						G_next <= X"b2";
+						B_next <= X"70";
+					when X"1d" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"1e" =>
+						R_next <= X"fe";
+						G_next <= X"d2";
+						B_next <= X"91";
+					when X"1f" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+					when X"20" =>
+						R_next <= X"3f";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"21" =>
+						R_next <= X"4b";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"22" =>
+						R_next <= X"59";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"23" =>
+						R_next <= X"69";
+						G_next <= X"19";
+						B_next <= X"03";
+					when X"24" =>
+						R_next <= X"78";
+						G_next <= X"29";
+						B_next <= X"12";
+					when X"25" =>
+						R_next <= X"88";
+						G_next <= X"3a";
+						B_next <= X"23";
+					when X"26" =>
+						R_next <= X"98";
+						G_next <= X"4a";
+						B_next <= X"34";
+					when X"27" =>
+						R_next <= X"a9";
+						G_next <= X"5b";
+						B_next <= X"45";
+					when X"28" =>
+						R_next <= X"b3";
+						G_next <= X"65";
+						B_next <= X"4f";
+					when X"29" =>
+						R_next <= X"c4";
+						G_next <= X"76";
+						B_next <= X"61";
+					when X"2a" =>
+						R_next <= X"d4";
+						G_next <= X"87";
+						B_next <= X"72";
+					when X"2b" =>
+						R_next <= X"e5";
+						G_next <= X"98";
+						B_next <= X"83";
+					when X"2c" =>
+						R_next <= X"f4";
+						G_next <= X"a7";
+						B_next <= X"92";
+					when X"2d" =>
+						R_next <= X"fd";
+						G_next <= X"b8";
+						B_next <= X"a3";
+					when X"2e" =>
+						R_next <= X"ff";
+						G_next <= X"c7";
+						B_next <= X"b3";
+					when X"2f" =>
+						R_next <= X"ff";
+						G_next <= X"d7";
+						B_next <= X"c2";
+					when X"30" =>
+						R_next <= X"3d";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"31" =>
+						R_next <= X"49";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"32" =>
+						R_next <= X"57";
+						G_next <= X"05";
+						B_next <= X"0b";
+					when X"33" =>
+						R_next <= X"68";
+						G_next <= X"15";
+						B_next <= X"1b";
+					when X"34" =>
+						R_next <= X"77";
+						G_next <= X"25";
+						B_next <= X"2a";
+					when X"35" =>
+						R_next <= X"88";
+						G_next <= X"36";
+						B_next <= X"3c";
+					when X"36" =>
+						R_next <= X"98";
+						G_next <= X"46";
+						B_next <= X"4c";
+					when X"37" =>
+						R_next <= X"a8";
+						G_next <= X"57";
+						B_next <= X"5d";
+					when X"38" =>
+						R_next <= X"b2";
+						G_next <= X"61";
+						B_next <= X"67";
+					when X"39" =>
+						R_next <= X"c3";
+						G_next <= X"72";
+						B_next <= X"79";
+					when X"3a" =>
+						R_next <= X"d3";
+						G_next <= X"83";
+						B_next <= X"89";
+					when X"3b" =>
+						R_next <= X"e4";
+						G_next <= X"94";
+						B_next <= X"9a";
+					when X"3c" =>
+						R_next <= X"f3";
+						G_next <= X"a3";
+						B_next <= X"a9";
+					when X"3d" =>
+						R_next <= X"fd";
+						G_next <= X"b4";
+						B_next <= X"ba";
+					when X"3e" =>
+						R_next <= X"ff";
+						G_next <= X"c4";
+						B_next <= X"ca";
+					when X"3f" =>
+						R_next <= X"ff";
+						G_next <= X"d4";
+						B_next <= X"d9";
+					when X"40" =>
+						R_next <= X"38";
+						G_next <= X"00";
+						B_next <= X"27";
+					when X"41" =>
+						R_next <= X"42";
+						G_next <= X"00";
+						B_next <= X"32";
+					when X"42" =>
+						R_next <= X"51";
+						G_next <= X"01";
+						B_next <= X"40";
+					when X"43" =>
+						R_next <= X"61";
+						G_next <= X"0e";
+						B_next <= X"50";
+					when X"44" =>
+						R_next <= X"70";
+						G_next <= X"1e";
+						B_next <= X"5f";
+					when X"45" =>
+						R_next <= X"81";
+						G_next <= X"2f";
+						B_next <= X"70";
+					when X"46" =>
+						R_next <= X"90";
+						G_next <= X"3f";
+						B_next <= X"81";
+					when X"47" =>
+						R_next <= X"a0";
+						G_next <= X"51";
+						B_next <= X"90";
+					when X"48" =>
+						R_next <= X"ab";
+						G_next <= X"5b";
+						B_next <= X"9a";
+					when X"49" =>
+						R_next <= X"bc";
+						G_next <= X"6c";
+						B_next <= X"ac";
+					when X"4a" =>
+						R_next <= X"cc";
+						G_next <= X"7c";
+						B_next <= X"bc";
+					when X"4b" =>
+						R_next <= X"dc";
+						G_next <= X"8d";
+						B_next <= X"cd";
+					when X"4c" =>
+						R_next <= X"ec";
+						G_next <= X"9d";
+						B_next <= X"dc";
+					when X"4d" =>
+						R_next <= X"fa";
+						G_next <= X"ae";
+						B_next <= X"ed";
+					when X"4e" =>
+						R_next <= X"fe";
+						G_next <= X"bd";
+						B_next <= X"fa";
+					when X"4f" =>
+						R_next <= X"ff";
+						G_next <= X"cd";
+						B_next <= X"fe";
+					when X"50" =>
+						R_next <= X"2c";
+						G_next <= X"00";
+						B_next <= X"46";
+					when X"51" =>
+						R_next <= X"37";
+						G_next <= X"00";
+						B_next <= X"50";
+					when X"52" =>
+						R_next <= X"46";
+						G_next <= X"01";
+						B_next <= X"5f";
+					when X"53" =>
+						R_next <= X"55";
+						G_next <= X"0e";
+						B_next <= X"6e";
+					when X"54" =>
+						R_next <= X"65";
+						G_next <= X"1e";
+						B_next <= X"7d";
+					when X"55" =>
+						R_next <= X"75";
+						G_next <= X"2f";
+						B_next <= X"8e";
+					when X"56" =>
+						R_next <= X"85";
+						G_next <= X"3f";
+						B_next <= X"9f";
+					when X"57" =>
+						R_next <= X"95";
+						G_next <= X"50";
+						B_next <= X"ae";
+					when X"58" =>
+						R_next <= X"a0";
+						G_next <= X"5b";
+						B_next <= X"b8";
+					when X"59" =>
+						R_next <= X"b1";
+						G_next <= X"6c";
+						B_next <= X"ca";
+					when X"5a" =>
+						R_next <= X"c1";
+						G_next <= X"7c";
+						B_next <= X"da";
+					when X"5b" =>
+						R_next <= X"d2";
+						G_next <= X"8d";
+						B_next <= X"eb";
+					when X"5c" =>
+						R_next <= X"e1";
+						G_next <= X"9d";
+						B_next <= X"f8";
+					when X"5d" =>
+						R_next <= X"f2";
+						G_next <= X"ae";
+						B_next <= X"fe";
+					when X"5e" =>
+						R_next <= X"fc";
+						G_next <= X"bd";
+						B_next <= X"ff";
+					when X"5f" =>
+						R_next <= X"fe";
+						G_next <= X"cd";
+						B_next <= X"ff";
+					when X"60" =>
+						R_next <= X"19";
+						G_next <= X"00";
+						B_next <= X"5e";
+					when X"61" =>
+						R_next <= X"24";
+						G_next <= X"00";
+						B_next <= X"67";
+					when X"62" =>
+						R_next <= X"34";
+						G_next <= X"03";
+						B_next <= X"76";
+					when X"63" =>
+						R_next <= X"44";
+						G_next <= X"13";
+						B_next <= X"85";
+					when X"64" =>
+						R_next <= X"53";
+						G_next <= X"22";
+						B_next <= X"94";
+					when X"65" =>
+						R_next <= X"64";
+						G_next <= X"33";
+						B_next <= X"a5";
+					when X"66" =>
+						R_next <= X"74";
+						G_next <= X"43";
+						B_next <= X"b5";
+					when X"67" =>
+						R_next <= X"85";
+						G_next <= X"55";
+						B_next <= X"c4";
+					when X"68" =>
+						R_next <= X"8f";
+						G_next <= X"5f";
+						B_next <= X"ce";
+					when X"69" =>
+						R_next <= X"a0";
+						G_next <= X"70";
+						B_next <= X"e0";
+					when X"6a" =>
+						R_next <= X"b0";
+						G_next <= X"81";
+						B_next <= X"f0";
+					when X"6b" =>
+						R_next <= X"c1";
+						G_next <= X"92";
+						B_next <= X"fc";
+					when X"6c" =>
+						R_next <= X"d0";
+						G_next <= X"a1";
+						B_next <= X"fe";
+					when X"6d" =>
+						R_next <= X"e1";
+						G_next <= X"b2";
+						B_next <= X"ff";
+					when X"6e" =>
+						R_next <= X"f0";
+						G_next <= X"c2";
+						B_next <= X"ff";
+					when X"6f" =>
+						R_next <= X"fc";
+						G_next <= X"d2";
+						B_next <= X"ff";
+					when X"70" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"5c";
+					when X"71" =>
+						R_next <= X"00";
+						G_next <= X"09";
+						B_next <= X"66";
+					when X"72" =>
+						R_next <= X"09";
+						G_next <= X"18";
+						B_next <= X"75";
+					when X"73" =>
+						R_next <= X"1a";
+						G_next <= X"29";
+						B_next <= X"84";
+					when X"74" =>
+						R_next <= X"29";
+						G_next <= X"38";
+						B_next <= X"93";
+					when X"75" =>
+						R_next <= X"3a";
+						G_next <= X"49";
+						B_next <= X"a4";
+					when X"76" =>
+						R_next <= X"4a";
+						G_next <= X"59";
+						B_next <= X"b4";
+					when X"77" =>
+						R_next <= X"5c";
+						G_next <= X"6a";
+						B_next <= X"c3";
+					when X"78" =>
+						R_next <= X"66";
+						G_next <= X"74";
+						B_next <= X"cd";
+					when X"79" =>
+						R_next <= X"77";
+						G_next <= X"85";
+						B_next <= X"df";
+					when X"7a" =>
+						R_next <= X"87";
+						G_next <= X"96";
+						B_next <= X"ef";
+					when X"7b" =>
+						R_next <= X"98";
+						G_next <= X"a7";
+						B_next <= X"fc";
+					when X"7c" =>
+						R_next <= X"a8";
+						G_next <= X"b6";
+						B_next <= X"fe";
+					when X"7d" =>
+						R_next <= X"b9";
+						G_next <= X"c7";
+						B_next <= X"ff";
+					when X"7e" =>
+						R_next <= X"c8";
+						G_next <= X"d6";
+						B_next <= X"ff";
+					when X"7f" =>
+						R_next <= X"d8";
+						G_next <= X"e7";
+						B_next <= X"ff";
+					when X"80" =>
+						R_next <= X"00";
+						G_next <= X"0b";
+						B_next <= X"45";
+					when X"81" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"4f";
+					when X"82" =>
+						R_next <= X"00";
+						G_next <= X"25";
+						B_next <= X"5d";
+					when X"83" =>
+						R_next <= X"09";
+						G_next <= X"36";
+						B_next <= X"6d";
+					when X"84" =>
+						R_next <= X"18";
+						G_next <= X"45";
+						B_next <= X"7c";
+					when X"85" =>
+						R_next <= X"29";
+						G_next <= X"56";
+						B_next <= X"8d";
+					when X"86" =>
+						R_next <= X"39";
+						G_next <= X"66";
+						B_next <= X"9d";
+					when X"87" =>
+						R_next <= X"4b";
+						G_next <= X"77";
+						B_next <= X"ac";
+					when X"88" =>
+						R_next <= X"56";
+						G_next <= X"81";
+						B_next <= X"b6";
+					when X"89" =>
+						R_next <= X"67";
+						G_next <= X"92";
+						B_next <= X"c8";
+					when X"8a" =>
+						R_next <= X"77";
+						G_next <= X"a2";
+						B_next <= X"d9";
+					when X"8b" =>
+						R_next <= X"88";
+						G_next <= X"b3";
+						B_next <= X"e9";
+					when X"8c" =>
+						R_next <= X"98";
+						G_next <= X"c3";
+						B_next <= X"f7";
+					when X"8d" =>
+						R_next <= X"a9";
+						G_next <= X"d3";
+						B_next <= X"fe";
+					when X"8e" =>
+						R_next <= X"b8";
+						G_next <= X"e3";
+						B_next <= X"ff";
+					when X"8f" =>
+						R_next <= X"c8";
+						G_next <= X"f3";
+						B_next <= X"ff";
+					when X"90" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"25";
+					when X"91" =>
+						R_next <= X"00";
+						G_next <= X"22";
+						B_next <= X"30";
+					when X"92" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"3f";
+					when X"93" =>
+						R_next <= X"01";
+						G_next <= X"42";
+						B_next <= X"4f";
+					when X"94" =>
+						R_next <= X"0c";
+						G_next <= X"51";
+						B_next <= X"5e";
+					when X"95" =>
+						R_next <= X"1e";
+						G_next <= X"62";
+						B_next <= X"6f";
+					when X"96" =>
+						R_next <= X"2e";
+						G_next <= X"72";
+						B_next <= X"80";
+					when X"97" =>
+						R_next <= X"40";
+						G_next <= X"82";
+						B_next <= X"8f";
+					when X"98" =>
+						R_next <= X"4a";
+						G_next <= X"8d";
+						B_next <= X"99";
+					when X"99" =>
+						R_next <= X"5c";
+						G_next <= X"9d";
+						B_next <= X"ab";
+					when X"9a" =>
+						R_next <= X"6c";
+						G_next <= X"ae";
+						B_next <= X"bc";
+					when X"9b" =>
+						R_next <= X"7e";
+						G_next <= X"be";
+						B_next <= X"cc";
+					when X"9c" =>
+						R_next <= X"8d";
+						G_next <= X"ce";
+						B_next <= X"db";
+					when X"9d" =>
+						R_next <= X"9e";
+						G_next <= X"de";
+						B_next <= X"ed";
+					when X"9e" =>
+						R_next <= X"ad";
+						G_next <= X"ee";
+						B_next <= X"fa";
+					when X"9f" =>
+						R_next <= X"bd";
+						G_next <= X"fc";
+						B_next <= X"fe";
+					when X"a0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"a1" =>
+						R_next <= X"00";
+						G_next <= X"2f";
+						B_next <= X"00";
+					when X"a2" =>
+						R_next <= X"00";
+						G_next <= X"3e";
+						B_next <= X"0a";
+					when X"a3" =>
+						R_next <= X"00";
+						G_next <= X"4f";
+						B_next <= X"1a";
+					when X"a4" =>
+						R_next <= X"08";
+						G_next <= X"5e";
+						B_next <= X"29";
+					when X"a5" =>
+						R_next <= X"18";
+						G_next <= X"6f";
+						B_next <= X"3b";
+					when X"a6" =>
+						R_next <= X"28";
+						G_next <= X"7f";
+						B_next <= X"4b";
+					when X"a7" =>
+						R_next <= X"3a";
+						G_next <= X"8f";
+						B_next <= X"5c";
+					when X"a8" =>
+						R_next <= X"44";
+						G_next <= X"9a";
+						B_next <= X"65";
+					when X"a9" =>
+						R_next <= X"55";
+						G_next <= X"ab";
+						B_next <= X"78";
+					when X"aa" =>
+						R_next <= X"65";
+						G_next <= X"bb";
+						B_next <= X"88";
+					when X"ab" =>
+						R_next <= X"77";
+						G_next <= X"cc";
+						B_next <= X"99";
+					when X"ac" =>
+						R_next <= X"86";
+						G_next <= X"db";
+						B_next <= X"a8";
+					when X"ad" =>
+						R_next <= X"97";
+						G_next <= X"ec";
+						B_next <= X"ba";
+					when X"ae" =>
+						R_next <= X"a6";
+						G_next <= X"fa";
+						B_next <= X"c9";
+					when X"af" =>
+						R_next <= X"b7";
+						G_next <= X"fe";
+						B_next <= X"d9";
+					when X"b0" =>
+						R_next <= X"00";
+						G_next <= X"2a";
+						B_next <= X"00";
+					when X"b1" =>
+						R_next <= X"00";
+						G_next <= X"37";
+						B_next <= X"00";
+					when X"b2" =>
+						R_next <= X"00";
+						G_next <= X"46";
+						B_next <= X"00";
+					when X"b3" =>
+						R_next <= X"01";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"b4" =>
+						R_next <= X"0f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"b5" =>
+						R_next <= X"20";
+						G_next <= X"76";
+						B_next <= X"03";
+					when X"b6" =>
+						R_next <= X"31";
+						G_next <= X"85";
+						B_next <= X"13";
+					when X"b7" =>
+						R_next <= X"42";
+						G_next <= X"96";
+						B_next <= X"24";
+					when X"b8" =>
+						R_next <= X"4c";
+						G_next <= X"a1";
+						B_next <= X"2d";
+					when X"b9" =>
+						R_next <= X"5d";
+						G_next <= X"b1";
+						B_next <= X"40";
+					when X"ba" =>
+						R_next <= X"6d";
+						G_next <= X"c1";
+						B_next <= X"51";
+					when X"bb" =>
+						R_next <= X"7f";
+						G_next <= X"d2";
+						B_next <= X"62";
+					when X"bc" =>
+						R_next <= X"8e";
+						G_next <= X"e2";
+						B_next <= X"71";
+					when X"bd" =>
+						R_next <= X"9f";
+						G_next <= X"f2";
+						B_next <= X"82";
+					when X"be" =>
+						R_next <= X"af";
+						G_next <= X"fd";
+						B_next <= X"92";
+					when X"bf" =>
+						R_next <= X"bf";
+						G_next <= X"ff";
+						B_next <= X"a1";
+					when X"c0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"c1" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"00";
+					when X"c2" =>
+						R_next <= X"05";
+						G_next <= X"40";
+						B_next <= X"00";
+					when X"c3" =>
+						R_next <= X"16";
+						G_next <= X"50";
+						B_next <= X"00";
+					when X"c4" =>
+						R_next <= X"26";
+						G_next <= X"5f";
+						B_next <= X"00";
+					when X"c5" =>
+						R_next <= X"36";
+						G_next <= X"70";
+						B_next <= X"00";
+					when X"c6" =>
+						R_next <= X"47";
+						G_next <= X"80";
+						B_next <= X"00";
+					when X"c7" =>
+						R_next <= X"58";
+						G_next <= X"90";
+						B_next <= X"08";
+					when X"c8" =>
+						R_next <= X"62";
+						G_next <= X"9b";
+						B_next <= X"12";
+					when X"c9" =>
+						R_next <= X"73";
+						G_next <= X"ac";
+						B_next <= X"24";
+					when X"ca" =>
+						R_next <= X"84";
+						G_next <= X"bc";
+						B_next <= X"35";
+					when X"cb" =>
+						R_next <= X"95";
+						G_next <= X"cd";
+						B_next <= X"46";
+					when X"cc" =>
+						R_next <= X"a4";
+						G_next <= X"dc";
+						B_next <= X"55";
+					when X"cd" =>
+						R_next <= X"b5";
+						G_next <= X"ed";
+						B_next <= X"67";
+					when X"ce" =>
+						R_next <= X"c5";
+						G_next <= X"fb";
+						B_next <= X"77";
+					when X"cf" =>
+						R_next <= X"d5";
+						G_next <= X"ff";
+						B_next <= X"86";
+					when X"d0" =>
+						R_next <= X"02";
+						G_next <= X"18";
+						B_next <= X"00";
+					when X"d1" =>
+						R_next <= X"0f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"d2" =>
+						R_next <= X"1f";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"d3" =>
+						R_next <= X"2f";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"d4" =>
+						R_next <= X"3f";
+						G_next <= X"54";
+						B_next <= X"00";
+					when X"d5" =>
+						R_next <= X"4f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"d6" =>
+						R_next <= X"60";
+						G_next <= X"75";
+						B_next <= X"00";
+					when X"d7" =>
+						R_next <= X"70";
+						G_next <= X"86";
+						B_next <= X"01";
+					when X"d8" =>
+						R_next <= X"7b";
+						G_next <= X"90";
+						B_next <= X"0a";
+					when X"d9" =>
+						R_next <= X"8c";
+						G_next <= X"a1";
+						B_next <= X"1c";
+					when X"da" =>
+						R_next <= X"9c";
+						G_next <= X"b1";
+						B_next <= X"2c";
+					when X"db" =>
+						R_next <= X"ad";
+						G_next <= X"c2";
+						B_next <= X"3e";
+					when X"dc" =>
+						R_next <= X"bd";
+						G_next <= X"d1";
+						B_next <= X"4d";
+					when X"dd" =>
+						R_next <= X"cd";
+						G_next <= X"e2";
+						B_next <= X"5e";
+					when X"de" =>
+						R_next <= X"dd";
+						G_next <= X"f1";
+						B_next <= X"6e";
+					when X"df" =>
+						R_next <= X"ed";
+						G_next <= X"fd";
+						B_next <= X"7e";
+					when X"e0" =>
+						R_next <= X"1e";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"e1" =>
+						R_next <= X"2a";
+						G_next <= X"16";
+						B_next <= X"00";
+					when X"e2" =>
+						R_next <= X"39";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"e3" =>
+						R_next <= X"49";
+						G_next <= X"36";
+						B_next <= X"00";
+					when X"e4" =>
+						R_next <= X"58";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"e5" =>
+						R_next <= X"69";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"e6" =>
+						R_next <= X"79";
+						G_next <= X"66";
+						B_next <= X"00";
+					when X"e7" =>
+						R_next <= X"8a";
+						G_next <= X"77";
+						B_next <= X"08";
+					when X"e8" =>
+						R_next <= X"94";
+						G_next <= X"81";
+						B_next <= X"12";
+					when X"e9" =>
+						R_next <= X"a5";
+						G_next <= X"92";
+						B_next <= X"24";
+					when X"ea" =>
+						R_next <= X"b5";
+						G_next <= X"a3";
+						B_next <= X"35";
+					when X"eb" =>
+						R_next <= X"c6";
+						G_next <= X"b3";
+						B_next <= X"46";
+					when X"ec" =>
+						R_next <= X"d6";
+						G_next <= X"c3";
+						B_next <= X"55";
+					when X"ed" =>
+						R_next <= X"e6";
+						G_next <= X"d4";
+						B_next <= X"66";
+					when X"ee" =>
+						R_next <= X"f6";
+						G_next <= X"e3";
+						B_next <= X"76";
+					when X"ef" =>
+						R_next <= X"fe";
+						G_next <= X"f3";
+						B_next <= X"86";
+					when X"f0" =>
+						R_next <= X"34";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"f1" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"f2" =>
+						R_next <= X"4f";
+						G_next <= X"15";
+						B_next <= X"00";
+					when X"f3" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"f4" =>
+						R_next <= X"6e";
+						G_next <= X"35";
+						B_next <= X"00";
+					when X"f5" =>
+						R_next <= X"7f";
+						G_next <= X"46";
+						B_next <= X"03";
+					when X"f6" =>
+						R_next <= X"8f";
+						G_next <= X"56";
+						B_next <= X"13";
+					when X"f7" =>
+						R_next <= X"9f";
+						G_next <= X"67";
+						B_next <= X"23";
+					when X"f8" =>
+						R_next <= X"aa";
+						G_next <= X"71";
+						B_next <= X"2e";
+					when X"f9" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"fa" =>
+						R_next <= X"cb";
+						G_next <= X"92";
+						B_next <= X"51";
+					when X"fb" =>
+						R_next <= X"dc";
+						G_next <= X"a3";
+						B_next <= X"62";
+					when X"fc" =>
+						R_next <= X"eb";
+						G_next <= X"b3";
+						B_next <= X"71";
+					when X"fd" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"fe" =>
+						R_next <= X"fe";
+						G_next <= X"d3";
+						B_next <= X"92";
+					when X"ff" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+			end case;
+			
+		end process;
+		
+end laoo;
Index: unmerged/core/de1/i2c_loader.vhd
===================================================================
--- unmerged/core/de1/i2c_loader.vhd	(nonexistent)
+++ unmerged/core/de1/i2c_loader.vhd	(revision 1)
@@ -0,0 +1,302 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
+use IEEE.NUMERIC_STD.ALL;
+
+entity i2c_loader is
+generic (
+	-- Address of slave to be loaded
+	device_address : integer := 16#1a#;
+	-- Number of retries to allow before stopping
+	num_retries : integer := 0;
+	-- Length of clock divider in bits.  Resulting bus frequency is
+	-- CLK/2^(log2_divider + 2)
+	log2_divider : integer := 7
+);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	I2C_SCL		:	inout	std_logic;
+	I2C_SDA		:	inout	std_logic;
+	
+	IS_DONE		:	out std_logic;
+	IS_ERROR	:	out	std_logic
+	);
+end i2c_loader;
+
+architecture i2c_loader_arch of i2c_loader is
+type regs is array(0 to 19) of std_logic_vector(7 downto 0);
+constant init_regs : regs := (
+	-- Left line in, 0dB, mute
+	X"00", X"97",
+	-- Right line in, 0dB, mute
+	X"02", X"97",
+	-- Left headphone out, -29dB, zero cross disabled
+	--X"04", X"58",
+	X"04", X"78",
+	-- Right headphone out, -29dB, zero cross disabled
+	--X"06", X"58",
+	X"06", X"78",
+	-- Audio path, DAC enabled, Line in, Bypass off, mic muted
+	X"08", X"12",
+	-- Digital path, Unmute, HP filter enabled
+	X"0A", X"00",
+	-- Power down mic, clkout and xtal osc, line in and adc
+	X"0C", X"67",
+	-- Format 16-bit I2S, no bit inversion or phase changes, MASTER
+	X"0E", X"42",
+	-- Sampling control, Normal mode, mclk/2 used, We should provide 12.288MHz but will provide 12.25MHz - making 96KHz notional, 97.656KHz actual 
+	X"10", X"DC",
+	-- Activate
+	X"12", X"01"
+	);
+-- Number of bursts (i.e. total number of registers)
+constant burst_length : positive := 2;
+-- Number of bytes to transfer per burst
+constant num_bursts : positive := (init_regs'length / burst_length);
+	
+type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
+signal state : state_t;
+signal phase : std_logic_vector(1 downto 0);
+subtype nbit_t is integer range 0 to 7;
+signal nbit : nbit_t;
+subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
+signal nbyte : nbyte_t;
+subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
+signal thisbyte : thisbyte_t;
+subtype retries_t is integer range 0 to num_retries;
+signal retries : retries_t;
+
+signal clken : std_logic;
+signal divider : std_logic_vector(log2_divider-1 downto 0);
+signal shiftreg : std_logic_vector(7 downto 0);
+signal scl_out : std_logic;
+signal sda_out : std_logic;
+signal nak : std_logic;
+begin
+	-- Create open-drain outputs for I2C bus
+	I2C_SCL <= '0' when scl_out = '0' else 'Z';
+	I2C_SDA <= '0' when sda_out = '0' else 'Z';
+	-- Status outputs are driven both ways
+	IS_DONE <= '1' when state = Done else '0';
+	IS_ERROR <= nak;
+	
+	-- Generate clock enable for desired bus speed
+	clken <= AND_REDUCE(divider);
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			divider <= (others => '0');
+		elsif falling_edge(CLK) then
+			divider <= divider + '1';
+		end if;
+	end process;
+
+	-- The I2C loader process
+	process(nRESET,CLK,clken)
+	begin
+		if nRESET = '0' then
+			scl_out <= '1';
+			sda_out <= '1';
+			state <= Idle;
+			phase <= "00";
+			nbit <= 0;
+			nbyte <= 0;
+			thisbyte <= 0;
+			shiftreg <= (others => '0');
+			nak <= '0'; -- No error
+			retries <= num_retries;
+		elsif rising_edge(CLK) and clken = '1' then
+  			-- Next phase by default
+			phase <= phase + 1;
+
+			-- STATE: IDLE
+			if state = Idle then
+				-- Start loading the device registers straight away
+				-- A 'GO' bit could be polled here if required
+				state <= Start;
+				phase <= "00";
+				scl_out <= '1';
+				sda_out <= '1';
+				
+			-- STATE: START
+			elsif state = Start then
+				-- Generate START condition
+				case phase is
+				when "00" =>
+					-- Drop SDA first
+					sda_out <= '0';
+				when "10" =>
+					-- Then drop SCL
+					scl_out <= '0';
+				when "11" =>
+					-- Advance to next state
+					-- Shift register loaded with device slave address
+					state <= Data;
+					nbit <= 7;
+					shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
+					nbyte <= burst_length;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: DATA
+			elsif state = Data then
+				-- Generate data
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Output data and shift (MSb first)
+					sda_out <= shiftreg(7);
+					shiftreg <= shiftreg(6 downto 0) & '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Next bit or advance to next state when done
+					if nbit = 0 then
+						state <= Ack;
+					else
+						nbit <= nbit - 1;
+					end if;
+				when others =>
+				  null;
+				end case;
+				
+			-- STATE: ACK
+			elsif state = Ack then
+				-- Generate ACK clock and check for error condition
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Float data
+					sda_out <= '1';
+				when "10" =>
+					-- Sample ack bit
+					nak <= I2C_SDA;
+					if I2C_SDA = '1' then
+						-- Error
+						nbyte <= 0; -- Close this burst and skip remaining registers
+						thisbyte <= init_regs'length;
+					else
+						-- Hold ACK to avoid spurious stops - this seems to fix a
+						-- problem with the Wolfson codec which releases the ACK
+						-- right on the falling edge of the clock pulse.  It looks like
+						-- the device interprets this is a STOP condition and then fails
+						-- to acknowledge the next byte.  We can avoid this by holding the
+						-- ACK condition for a little longer.
+						sda_out <= '0';
+					end if;
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Advance to next state
+					if nbyte = 0 then
+						-- No more bytes in this burst - generate a STOP
+						state <= Stop;
+					else
+						-- Generate next byte
+						state <= Data;
+						nbit <= 7;
+						shiftreg <= init_regs(thisbyte);
+						nbyte <= nbyte - 1;
+						thisbyte <= thisbyte + 1;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: STOP
+			elsif state = Stop then
+				-- Generate STOP condition
+				case phase is
+				when "00" =>
+					-- Drop SCL first
+					scl_out <= '0';
+				when "01" =>
+					-- Drop SDA
+					sda_out <= '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					if thisbyte = init_regs'length then
+						-- All registers done, advance to finished state.  This will
+						-- bring SDA high while SCL is still high, completing the STOP
+						-- condition
+						state <= Done;
+					else
+						-- Load the next register after a short delay
+						state <= Pause;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: PAUSE
+			elsif state = Pause then
+				-- Delay for one cycle of 'phase' then start the next burst
+				scl_out <= '1';
+				sda_out <= '1';
+				if phase = "11" then
+					state <= Start;
+				end if;
+				
+			-- STATE: DONE
+			else
+				-- Finished
+				scl_out <= '1';
+				sda_out <= '1';
+				
+				if nak = '1' and retries > 0 then
+					-- We can retry in the event of a NAK in case the
+					-- slave got out of sync for some reason
+					retries <= retries - 1;
+					state <= Idle;
+				end if;
+			end if;
+		end if;
+	end process;
+end i2c_loader_arch;
+
Index: unmerged/changes_de1_to_mcc
===================================================================
--- unmerged/changes_de1_to_mcc	(nonexistent)
+++ unmerged/changes_de1_to_mcc	(revision 1)
@@ -0,0 +1,10631 @@
+diff -ur atari800core_20140301_de1/address_decoder.vhdl atari800core_v1_20140121_mcc216/address_decoder.vhdl
+--- atari800core_20140301_de1/address_decoder.vhdl	2014-01-20 20:46:50.000000000 +0000
++++ atari800core_v1_20140121_mcc216/address_decoder.vhdl	2014-01-30 21:32:16.000000000 +0000
+@@ -10,6 +10,7 @@
+ use ieee.numeric_std.all;
+ use IEEE.STD_LOGIC_MISC.all;
+ 
++
+ ENTITY address_decoder IS
+ PORT 
+ ( 
+@@ -110,10 +111,12 @@
+ 	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+ 	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+ 	SDRAM_WRITE_EN : out std_logic;
+-	SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
++	--SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
++	SDRAM_REQUEST : out std_logic; -- Usual pattern
+ 	SDRAM_REFRESH : out std_logic;
+ 
+-	SDRAM_REPLY : in std_logic; -- This matches the request once complete
++	--SDRAM_REPLY : in std_logic; -- This matches the request once complete
++	SDRAM_REQUEST_COMPLETE : in std_logic;
+ 	SDRAM_DATA : in std_logic_vector(31 downto 0);
+ 	
+ 	WRITE_DATA : out std_logic_vector(31 downto 0)
+@@ -161,12 +164,15 @@
+ 	signal ram_chip_select : std_logic;
+ 	signal sdram_chip_select : std_logic;
+ 	
+-	signal sdram_request_next : std_logic;
+-	signal sdram_request_reg : std_logic;
+-	signal SDRAM_REQUEST_COMPLETE	: std_logic;
++--	signal sdram_request_next : std_logic;
++--	signal sdram_request_reg : std_logic;
++--	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+ 	
+ 	signal fetch_priority : std_logic_vector(2 downto 0);
+ 	
++	signal fetch_wait_next : std_logic_vector(8 downto 0);
++	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
++	
+ BEGIN
+ 		-- register
+ 	process(clk,reset_n)
+@@ -179,7 +185,8 @@
+ 			width_32bit_reg <= '0';
+ 			write_enable_reg <= '0';
+ 			data_write_reg <= (others=> '0');
+-			sdram_request_reg <= '0';
++			--sdram_request_reg <= '0';
++			fetch_wait_reg <= (others=>'0');
+ 		elsif (clk'event and clk='1') then
+ 			addr_reg <= addr_next;
+ 			state_reg <= state_next;
+@@ -188,7 +195,8 @@
+ 			width_32bit_reg <= width_32bit_next;
+ 			write_enable_reg <= write_enable_next;
+ 			data_write_reg <= data_WRITE_next;
+-			sdram_request_reg <= sdram_request_next;
++			--sdram_request_reg <= sdram_request_next;
++			fetch_wait_reg <= fetch_wait_next;
+ 		end if;
+ 	end process;
+ 	
+@@ -211,13 +219,14 @@
+ 	
+ 	-- state machine impl
+ 	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+-	process(state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
++	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
+ 	begin
+ 		start_request <= '0';
+ 		notify_antic <= '0';
+ 		notify_cpu <= '0';
+ 		notify_zpu <= '0';
+ 		state_next <= state_reg;
++		fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1);
+ 
+ 		addr_next <= addr_reg;
+ 		data_WRITE_next <= data_WRITE_reg;
+@@ -228,6 +237,7 @@
+ 		
+ 		case state_reg is
+ 			when state_idle =>
++				fetch_wait_next <= (others=>'0');
+ 				write_enable_next <= '0';
+ 				width_8bit_next <= '0';
+ 				width_16bit_next <= '0';
+@@ -300,8 +310,9 @@
+ 	
+ 	RAM_REQUEST <= ram_chip_select;
+ 		
+-	SDRAM_REQUEST <= sdram_request_next;
+-	SDRAM_REFRESH <= '0'; -- TODO, BROKEN! antic_refresh;
++	SDRAM_REQUEST <= sdram_chip_select;
++	--SDRAM_REQUEST <= sdram_request_next;
++	SDRAM_REFRESH <= fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+ 	SDRAM_READ_EN <= not(write_enable_next);
+ 	SDRAM_WRITE_EN <= write_enable_next;
+ 	
+@@ -312,8 +323,8 @@
+ 	WRITE_DATA <= DATA_WRITE_next;
+ 
+ 	-- a little sdram glue - move to sdram wrapper? TODO
+-	SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+-	sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
++	--SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
++	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+ 	
+ 	-- Calculate which memory area to use
+ 	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+@@ -466,19 +477,31 @@
+ 					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+ 									
+ 					if (portb(7) = '0' and portb(0) = '1') then
+-						request_complete <= ROM_REQUEST_COMPLETE;
+-						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+-						rom_request <= start_request;					
++						--request_complete <= ROM_REQUEST_COMPLETE;
++						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
++						--rom_request <= start_request;					
++						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						
++						if (write_enable_next = '1') then
++							request_complete <= '1';
++						else
++							request_complete <= sdram_request_COMPLETE;							
++							sdram_chip_select <= start_request;							
++						end if;
+ 						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+ 						case rom_select is
+ 							when "00" =>
+ 								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
++						    SDRAM_ADDR <="0010000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+ 							when "01" =>
+ 								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
++							 SDRAM_ADDR <="0010000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k								
+ 							when "10" =>
+ 								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
++							 SDRAM_ADDR <="0010000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k							
+ 							when "11" =>
+ 								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
++							SDRAM_ADDR <= "0010001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)								
+ 						end case;														
+ 					else				
+ 						if (use_sdram = '1') then
+@@ -540,10 +563,19 @@
+ 						request_complete <= CART_REQUEST_COMPLETE;
+ 					else
+ 						if (portb(1) = '0') then
+-							request_complete <= ROM_REQUEST_COMPLETE;
+-							MEMORY_DATA(7 downto 0) <= ROM_DATA;
+-							rom_request <= start_request;
++							--request_complete <= ROM_REQUEST_COMPLETE;
++							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
++							--rom_request <= start_request;					
++							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++							if (write_enable_next = '1') then
++								request_complete <= '1';
++							else
++								request_complete <= sdram_request_COMPLETE;							
++								sdram_chip_select <= start_request;								
++							end if;
++						
+ 							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
++						 SDRAM_ADDR <="0010000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k							
+ 						else
+ 							if (use_sdram = '1') then
+ 								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+@@ -566,18 +598,30 @@
+ 					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+ 					
+ 					if (portb(0) = '1') then
+-						request_complete <= ROM_REQUEST_COMPLETE;
+-						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+-						rom_request <= start_request;
++						--request_complete <= ROM_REQUEST_COMPLETE;
++						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
++						--rom_request <= start_request;					
++						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						if (write_enable_next = '1') then
++							request_complete <= '1';
++						else
++							request_complete <= sdram_request_COMPLETE;							
++							sdram_chip_select <= start_request;							
++						end if;																			
++
+ 						case rom_select is
+ 							when "00" =>
+ 								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
++							SDRAM_ADDR <= "0010000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+ 							when "01" =>
+ 								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
++							SDRAM_ADDR <= "0010000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+ 							when "10" =>
+ 								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
++							SDRAM_ADDR <= "0010000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+ 							when "11" =>
+ 								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
++							SDRAM_ADDR <= "0010001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+ 						end case;
+ 								
+ 					else
+diff -ur atari800core_20140301_de1/atari800core.qsf atari800core_v1_20140121_mcc216/atari800core.qsf
+--- atari800core_20140301_de1/atari800core.qsf	2014-03-01 12:49:08.000000000 +0000
++++ atari800core_v1_20140121_mcc216/atari800core.qsf	2014-02-03 19:39:52.000000000 +0000
+@@ -36,8 +36,8 @@
+ # -------------------------------------------------------------------------- #
+ 
+ 
+-set_global_assignment -name FAMILY "Cyclone II"
+-set_global_assignment -name DEVICE EP2C20F484C7
++set_global_assignment -name FAMILY "Cyclone III"
++set_global_assignment -name DEVICE EP3C16E144C8
+ set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+@@ -47,504 +47,35 @@
+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+-set_location_assignment PIN_A15 -to GPIO_0[4]
+-set_location_assignment PIN_B15 -to GPIO_0[5]
+-set_location_assignment PIN_A16 -to GPIO_0[6]
+-set_location_assignment PIN_B16 -to GPIO_0[7]
+-set_location_assignment PIN_A17 -to GPIO_0[8]
+-set_location_assignment PIN_B17 -to GPIO_0[9]
+-set_location_assignment PIN_A18 -to GPIO_0[10]
+-set_location_assignment PIN_B18 -to GPIO_0[11]
+-set_location_assignment PIN_A19 -to GPIO_0[12]
+-set_location_assignment PIN_B19 -to GPIO_0[13]
+-set_location_assignment PIN_A20 -to GPIO_0[14]
+-set_location_assignment PIN_B20 -to GPIO_0[15]
+-set_location_assignment PIN_C21 -to GPIO_0[16]
+-set_location_assignment PIN_C22 -to GPIO_0[17]
+-set_location_assignment PIN_D21 -to GPIO_0[18]
+-set_location_assignment PIN_D22 -to GPIO_0[19]
+-set_location_assignment PIN_E21 -to GPIO_0[20]
+-set_location_assignment PIN_E22 -to GPIO_0[21]
+-set_location_assignment PIN_F21 -to GPIO_0[22]
+-set_location_assignment PIN_F22 -to GPIO_0[23]
+-set_location_assignment PIN_G21 -to GPIO_0[24]
+-set_location_assignment PIN_G22 -to GPIO_0[25]
+-set_location_assignment PIN_J21 -to GPIO_0[26]
+-set_location_assignment PIN_J22 -to GPIO_0[27]
+-set_location_assignment PIN_K21 -to GPIO_0[28]
+-set_location_assignment PIN_K22 -to GPIO_0[29]
+-set_location_assignment PIN_J19 -to GPIO_0[30]
+-set_location_assignment PIN_J20 -to GPIO_0[31]
+-set_location_assignment PIN_J18 -to GPIO_0[32]
+-set_location_assignment PIN_K20 -to GPIO_0[33]
+-set_location_assignment PIN_L19 -to GPIO_0[34]
+-set_location_assignment PIN_L18 -to GPIO_0[35]
+-set_location_assignment PIN_H12 -to GPIO_1[0]
+-set_location_assignment PIN_H13 -to GPIO_1[1]
+-set_location_assignment PIN_H14 -to GPIO_1[2]
+-set_location_assignment PIN_G15 -to GPIO_1[3]
+-set_location_assignment PIN_E14 -to GPIO_1[4]
+-set_location_assignment PIN_E15 -to GPIO_1[5]
+-set_location_assignment PIN_F15 -to GPIO_1[6]
+-set_location_assignment PIN_G16 -to GPIO_1[7]
+-set_location_assignment PIN_F12 -to GPIO_1[8]
+-set_location_assignment PIN_F13 -to GPIO_1[9]
+-set_location_assignment PIN_C14 -to GPIO_1[10]
+-set_location_assignment PIN_D14 -to GPIO_1[11]
+-set_location_assignment PIN_D15 -to GPIO_1[12]
+-set_location_assignment PIN_D16 -to GPIO_1[13]
+-set_location_assignment PIN_C17 -to GPIO_1[14]
+-set_location_assignment PIN_C18 -to GPIO_1[15]
+-set_location_assignment PIN_C19 -to GPIO_1[16]
+-set_location_assignment PIN_C20 -to GPIO_1[17]
+-set_location_assignment PIN_D19 -to GPIO_1[18]
+-set_location_assignment PIN_D20 -to GPIO_1[19]
+-set_location_assignment PIN_E20 -to GPIO_1[20]
+-set_location_assignment PIN_F20 -to GPIO_1[21]
+-set_location_assignment PIN_E19 -to GPIO_1[22]
+-set_location_assignment PIN_E18 -to GPIO_1[23]
+-set_location_assignment PIN_G20 -to GPIO_1[24]
+-set_location_assignment PIN_G18 -to GPIO_1[25]
+-set_location_assignment PIN_G17 -to GPIO_1[26]
+-set_location_assignment PIN_H17 -to GPIO_1[27]
+-set_location_assignment PIN_J15 -to GPIO_1[28]
+-set_location_assignment PIN_H18 -to GPIO_1[29]
+-set_location_assignment PIN_N22 -to GPIO_1[30]
+-set_location_assignment PIN_N21 -to GPIO_1[31]
+-set_location_assignment PIN_P15 -to GPIO_1[32]
+-set_location_assignment PIN_N15 -to GPIO_1[33]
+-set_location_assignment PIN_P17 -to GPIO_1[34]
+-set_location_assignment PIN_P18 -to GPIO_1[35]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+-set_location_assignment PIN_L22 -to SW[0]
+-set_location_assignment PIN_L21 -to SW[1]
+-set_location_assignment PIN_M22 -to SW[2]
+-set_location_assignment PIN_V12 -to SW[3]
+-set_location_assignment PIN_W12 -to SW[4]
+-set_location_assignment PIN_U12 -to SW[5]
+-set_location_assignment PIN_U11 -to SW[6]
+-set_location_assignment PIN_M2 -to SW[7]
+-set_location_assignment PIN_M1 -to SW[8]
+-set_location_assignment PIN_L2 -to SW[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+-set_location_assignment PIN_J2 -to HEX0[0]
+-set_location_assignment PIN_J1 -to HEX0[1]
+-set_location_assignment PIN_H2 -to HEX0[2]
+-set_location_assignment PIN_H1 -to HEX0[3]
+-set_location_assignment PIN_F2 -to HEX0[4]
+-set_location_assignment PIN_F1 -to HEX0[5]
+-set_location_assignment PIN_E2 -to HEX0[6]
+-set_location_assignment PIN_E1 -to HEX1[0]
+-set_location_assignment PIN_H6 -to HEX1[1]
+-set_location_assignment PIN_H5 -to HEX1[2]
+-set_location_assignment PIN_H4 -to HEX1[3]
+-set_location_assignment PIN_G3 -to HEX1[4]
+-set_location_assignment PIN_D2 -to HEX1[5]
+-set_location_assignment PIN_D1 -to HEX1[6]
+-set_location_assignment PIN_G5 -to HEX2[0]
+-set_location_assignment PIN_G6 -to HEX2[1]
+-set_location_assignment PIN_C2 -to HEX2[2]
+-set_location_assignment PIN_C1 -to HEX2[3]
+-set_location_assignment PIN_E3 -to HEX2[4]
+-set_location_assignment PIN_E4 -to HEX2[5]
+-set_location_assignment PIN_D3 -to HEX2[6]
+-set_location_assignment PIN_F4 -to HEX3[0]
+-set_location_assignment PIN_D5 -to HEX3[1]
+-set_location_assignment PIN_D6 -to HEX3[2]
+-set_location_assignment PIN_J4 -to HEX3[3]
+-set_location_assignment PIN_L8 -to HEX3[4]
+-set_location_assignment PIN_F3 -to HEX3[5]
+-set_location_assignment PIN_D4 -to HEX3[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+-set_location_assignment PIN_R22 -to KEY[0]
+-set_location_assignment PIN_R21 -to KEY[1]
+-set_location_assignment PIN_T22 -to KEY[2]
+-set_location_assignment PIN_T21 -to KEY[3]
+-set_location_assignment PIN_R20 -to LEDR[0]
+-set_location_assignment PIN_R19 -to LEDR[1]
+-set_location_assignment PIN_U19 -to LEDR[2]
+-set_location_assignment PIN_Y19 -to LEDR[3]
+-set_location_assignment PIN_T18 -to LEDR[4]
+-set_location_assignment PIN_V19 -to LEDR[5]
+-set_location_assignment PIN_Y18 -to LEDR[6]
+-set_location_assignment PIN_U18 -to LEDR[7]
+-set_location_assignment PIN_R18 -to LEDR[8]
+-set_location_assignment PIN_R17 -to LEDR[9]
+-set_location_assignment PIN_U22 -to LEDG[0]
+-set_location_assignment PIN_U21 -to LEDG[1]
+-set_location_assignment PIN_V22 -to LEDG[2]
+-set_location_assignment PIN_V21 -to LEDG[3]
+-set_location_assignment PIN_W22 -to LEDG[4]
+-set_location_assignment PIN_W21 -to LEDG[5]
+-set_location_assignment PIN_Y22 -to LEDG[6]
+-set_location_assignment PIN_Y21 -to LEDG[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+-set_location_assignment PIN_D12 -to CLOCK_27[0]
+-set_location_assignment PIN_E12 -to CLOCK_27[1]
+-set_location_assignment PIN_B12 -to CLOCK_24[0]
+-set_location_assignment PIN_A12 -to CLOCK_24[1]
+-set_location_assignment PIN_L1 -to CLOCK_50
+-set_location_assignment PIN_M21 -to EXT_CLOCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+-set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+-set_location_assignment PIN_H15 -to PS2_CLK
+-set_location_assignment PIN_J14 -to PS2_DAT
+-set_location_assignment PIN_F14 -to UART_RXD
+-set_location_assignment PIN_G12 -to UART_TXD
+-set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+-set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+-set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+-set_location_assignment PIN_E8 -to TDI
+-set_location_assignment PIN_D8 -to TCS
+-set_location_assignment PIN_C7 -to TCK
+-set_location_assignment PIN_D7 -to TDO
+-set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+-set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+-set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+-set_location_assignment PIN_D9 -to VGA_R[0]
+-set_location_assignment PIN_C9 -to VGA_R[1]
+-set_location_assignment PIN_A7 -to VGA_R[2]
+-set_location_assignment PIN_B7 -to VGA_R[3]
+-set_location_assignment PIN_B8 -to VGA_G[0]
+-set_location_assignment PIN_C10 -to VGA_G[1]
+-set_location_assignment PIN_B9 -to VGA_G[2]
+-set_location_assignment PIN_A8 -to VGA_G[3]
+-set_location_assignment PIN_A9 -to VGA_B[0]
+-set_location_assignment PIN_D11 -to VGA_B[1]
+-set_location_assignment PIN_A10 -to VGA_B[2]
+-set_location_assignment PIN_B10 -to VGA_B[3]
+-set_location_assignment PIN_A11 -to VGA_HS
+-set_location_assignment PIN_B11 -to VGA_VS
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+-set_location_assignment PIN_A3 -to I2C_SCLK
+-set_location_assignment PIN_B3 -to I2C_SDAT
+-set_location_assignment PIN_A6 -to AUD_ADCLRCK
+-set_location_assignment PIN_B6 -to AUD_ADCDAT
+-set_location_assignment PIN_A5 -to AUD_DACLRCK
+-set_location_assignment PIN_B5 -to AUD_DACDAT
+-set_location_assignment PIN_B4 -to AUD_XCK
+-set_location_assignment PIN_A4 -to AUD_BCLK
+-set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+-set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+-set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+-set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+-set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+-set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+-set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+-set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+-set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+-set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+-set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+-set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+-set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+-set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+-set_location_assignment PIN_U3 -to DRAM_BA_0
+-set_location_assignment PIN_V4 -to DRAM_BA_1
+-set_location_assignment PIN_T3 -to DRAM_CAS_N
+-set_location_assignment PIN_N3 -to DRAM_CKE
+-set_location_assignment PIN_U4 -to DRAM_CLK
+-set_location_assignment PIN_T6 -to DRAM_CS_N
+-set_location_assignment PIN_U1 -to DRAM_DQ[0]
+-set_location_assignment PIN_U2 -to DRAM_DQ[1]
+-set_location_assignment PIN_V1 -to DRAM_DQ[2]
+-set_location_assignment PIN_V2 -to DRAM_DQ[3]
+-set_location_assignment PIN_W1 -to DRAM_DQ[4]
+-set_location_assignment PIN_W2 -to DRAM_DQ[5]
+-set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+-set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+-set_location_assignment PIN_N1 -to DRAM_DQ[8]
+-set_location_assignment PIN_N2 -to DRAM_DQ[9]
+-set_location_assignment PIN_P1 -to DRAM_DQ[10]
+-set_location_assignment PIN_P2 -to DRAM_DQ[11]
+-set_location_assignment PIN_R1 -to DRAM_DQ[12]
+-set_location_assignment PIN_R2 -to DRAM_DQ[13]
+-set_location_assignment PIN_T1 -to DRAM_DQ[14]
+-set_location_assignment PIN_T2 -to DRAM_DQ[15]
+-set_location_assignment PIN_R7 -to DRAM_LDQM
+-set_location_assignment PIN_T5 -to DRAM_RAS_N
+-set_location_assignment PIN_M5 -to DRAM_UDQM
+-set_location_assignment PIN_R8 -to DRAM_WE_N
+-set_location_assignment PIN_AB20 -to FL_ADDR[0]
+-set_location_assignment PIN_AA14 -to FL_ADDR[1]
+-set_location_assignment PIN_Y16 -to FL_ADDR[2]
+-set_location_assignment PIN_R15 -to FL_ADDR[3]
+-set_location_assignment PIN_T15 -to FL_ADDR[4]
+-set_location_assignment PIN_U15 -to FL_ADDR[5]
+-set_location_assignment PIN_V15 -to FL_ADDR[6]
+-set_location_assignment PIN_W15 -to FL_ADDR[7]
+-set_location_assignment PIN_R14 -to FL_ADDR[8]
+-set_location_assignment PIN_Y13 -to FL_ADDR[9]
+-set_location_assignment PIN_R12 -to FL_ADDR[10]
+-set_location_assignment PIN_T12 -to FL_ADDR[11]
+-set_location_assignment PIN_AB14 -to FL_ADDR[12]
+-set_location_assignment PIN_AA13 -to FL_ADDR[13]
+-set_location_assignment PIN_AB13 -to FL_ADDR[14]
+-set_location_assignment PIN_AA12 -to FL_ADDR[15]
+-set_location_assignment PIN_AB12 -to FL_ADDR[16]
+-set_location_assignment PIN_AA20 -to FL_ADDR[17]
+-set_location_assignment PIN_U14 -to FL_ADDR[18]
+-set_location_assignment PIN_V14 -to FL_ADDR[19]
+-set_location_assignment PIN_U13 -to FL_ADDR[20]
+-set_location_assignment PIN_R13 -to FL_ADDR[21]
+-set_location_assignment PIN_AB16 -to FL_DQ[0]
+-set_location_assignment PIN_AA16 -to FL_DQ[1]
+-set_location_assignment PIN_AB17 -to FL_DQ[2]
+-set_location_assignment PIN_AA17 -to FL_DQ[3]
+-set_location_assignment PIN_AB18 -to FL_DQ[4]
+-set_location_assignment PIN_AA18 -to FL_DQ[5]
+-set_location_assignment PIN_AB19 -to FL_DQ[6]
+-set_location_assignment PIN_AA19 -to FL_DQ[7]
+-set_location_assignment PIN_AA15 -to FL_OE_N
+-set_location_assignment PIN_W14 -to FL_RST_N
+-set_location_assignment PIN_Y14 -to FL_WE_N
+-set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+-set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+-set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+-set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+-set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+-set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+-set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+-set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+-set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+-set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+-set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+-set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+-set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+-set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+-set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+-set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+-set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+-set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+-set_location_assignment PIN_AB5 -to SRAM_CE_N
+-set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+-set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+-set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+-set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+-set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+-set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+-set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+-set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+-set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+-set_location_assignment PIN_W9 -to SRAM_DQ[9]
+-set_location_assignment PIN_V9 -to SRAM_DQ[10]
+-set_location_assignment PIN_U9 -to SRAM_DQ[11]
+-set_location_assignment PIN_R9 -to SRAM_DQ[12]
+-set_location_assignment PIN_W8 -to SRAM_DQ[13]
+-set_location_assignment PIN_V8 -to SRAM_DQ[14]
+-set_location_assignment PIN_U8 -to SRAM_DQ[15]
+-set_location_assignment PIN_Y7 -to SRAM_LB_N
+-set_location_assignment PIN_T8 -to SRAM_OE_N
+-set_location_assignment PIN_W7 -to SRAM_UB_N
+-set_location_assignment PIN_AA10 -to SRAM_WE_N
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_CE_N
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_LB_N
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_OE_N
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_UB_N
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_WE_N
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[0]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[1]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[2]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[3]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[4]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[5]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[6]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[7]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[8]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[9]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[10]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[11]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[12]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[13]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[14]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[15]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[16]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[17]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[0]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[1]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[2]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[3]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[4]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[5]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[6]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[7]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[8]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[9]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[10]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[11]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[12]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[13]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[14]
+-set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[15]
+-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
++set_location_assignment PIN_135 -to VGA_R[0]
++set_location_assignment PIN_134 -to VGA_R[1]
++set_location_assignment PIN_133 -to VGA_R[2]
++set_location_assignment PIN_132 -to VGA_R[3]
++set_location_assignment PIN_141 -to VGA_G[0]
++set_location_assignment PIN_142 -to VGA_G[1]
++set_location_assignment PIN_143 -to VGA_G[2]
++set_location_assignment PIN_144 -to VGA_G[3]
++set_location_assignment PIN_4 -to VGA_B[0]
++set_location_assignment PIN_7 -to VGA_B[1]
++set_location_assignment PIN_10 -to VGA_B[2]
++set_location_assignment PIN_11 -to VGA_B[3]
++set_location_assignment PIN_136 -to VGA_HS
++set_location_assignment PIN_137 -to VGA_VS
+ set_global_assignment -name ENABLE_SIGNALTAP ON
+-set_location_assignment PIN_V20 -to SD_CLK
+-set_location_assignment PIN_Y20 -to SD_CMD
+-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
++set_location_assignment PIN_44 -to SD_CLK
++set_location_assignment PIN_46 -to SD_CMD
+ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+ set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+ set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+-set_location_assignment PIN_W20 -to SD_DATA
+-set_location_assignment PIN_U20 -to SD_THREE
+-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name SMART_RECOMPILE ON
+ set_global_assignment -name ENABLE_DRC_SETTINGS ON
+ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+@@ -555,6 +86,215 @@
+ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+ set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+ set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
++
++set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
++set_location_assignment PIN_28 -to AUDIO_L
++set_location_assignment PIN_30 -to AUDIO_R
++set_location_assignment PIN_53 -to CPU_RESET_n
++set_location_assignment PIN_55 -to FPGA_CLK
++set_location_assignment PIN_127 -to JOY1_n[0]
++set_location_assignment PIN_91 -to JOY1_n[1]
++set_location_assignment PIN_90 -to JOY1_n[2]
++set_location_assignment PIN_88 -to JOY1_n[3]
++set_location_assignment PIN_89 -to JOY1_n[4]
++set_location_assignment PIN_126 -to JOY1_n[5]
++set_location_assignment PIN_128 -to JOY2_n[0]
++set_location_assignment PIN_25 -to JOY2_n[1]
++set_location_assignment PIN_24 -to JOY2_n[2]
++set_location_assignment PIN_22 -to JOY2_n[3]
++set_location_assignment PIN_23 -to JOY2_n[4]
++set_location_assignment PIN_129 -to JOY2_n[5]
++set_location_assignment PIN_33 -to PS2K_DAT
++set_location_assignment PIN_39 -to PS2K_CLK
++set_location_assignment PIN_32 -to PS2M_DAT
++set_location_assignment PIN_31 -to PS2M_CLK
++set_location_assignment PIN_52 -to SD_DAT0
++set_location_assignment PIN_49 -to SD_DAT3
++set_location_assignment PIN_42 -to USB_P
++set_location_assignment PIN_43 -to USB_N
++set_location_assignment PIN_50 -to USB2_P
++set_location_assignment PIN_51 -to USB2_N
++set_location_assignment PIN_112 -to SDRAM_CLK
++set_location_assignment PIN_61 -to SDRAM_A[0]
++set_location_assignment PIN_60 -to SDRAM_A[1]
++set_location_assignment PIN_59 -to SDRAM_A[2]
++set_location_assignment PIN_58 -to SDRAM_A[3]
++set_location_assignment PIN_125 -to SDRAM_A[4]
++set_location_assignment PIN_121 -to SDRAM_A[5]
++set_location_assignment PIN_120 -to SDRAM_A[6]
++set_location_assignment PIN_119 -to SDRAM_A[7]
++set_location_assignment PIN_115 -to SDRAM_A[8]
++set_location_assignment PIN_114 -to SDRAM_A[9]
++set_location_assignment PIN_64 -to SDRAM_A[10]
++set_location_assignment PIN_113 -to SDRAM_A[11]
++set_location_assignment PIN_111 -to SDRAM_A[12]
++set_location_assignment PIN_66 -to SDRAM_BA[0]
++set_location_assignment PIN_65 -to SDRAM_BA[1]
++set_location_assignment PIN_87 -to SDRAM_DQ[0]
++set_location_assignment PIN_86 -to SDRAM_DQ[1]
++set_location_assignment PIN_85 -to SDRAM_DQ[2]
++set_location_assignment PIN_83 -to SDRAM_DQ[3]
++set_location_assignment PIN_80 -to SDRAM_DQ[4]
++set_location_assignment PIN_79 -to SDRAM_DQ[5]
++set_location_assignment PIN_77 -to SDRAM_DQ[6]
++set_location_assignment PIN_76 -to SDRAM_DQ[7]
++set_location_assignment PIN_106 -to SDRAM_DQ[8]
++set_location_assignment PIN_105 -to SDRAM_DQ[9]
++set_location_assignment PIN_104 -to SDRAM_DQ[10]
++set_location_assignment PIN_103 -to SDRAM_DQ[11]
++set_location_assignment PIN_101 -to SDRAM_DQ[12]
++set_location_assignment PIN_100 -to SDRAM_DQ[13]
++set_location_assignment PIN_99 -to SDRAM_DQ[14]
++set_location_assignment PIN_98 -to SDRAM_DQ[15]
++set_location_assignment PIN_67 -to SDRAM_CS_n
++set_location_assignment PIN_68 -to SDRAM_RAS_n
++set_location_assignment PIN_69 -to SDRAM_CAS_n
++set_location_assignment PIN_71 -to SDRAM_WE_n
++set_location_assignment PIN_6 -to CFG_DOUT
++set_location_assignment PIN_8 -to CFG_CS_n
++set_location_assignment PIN_12 -to CFG_CLK
++set_location_assignment PIN_13 -to CFG_DIN
++set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
++set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
++set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
++set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
++set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
++set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
++set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN
++set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
++set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
++set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
++
++
++set_global_assignment -name VERILOG_FILE hq_dac.v
++set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
++set_global_assignment -name VHDL_FILE romlo.vhd
++set_global_assignment -name VHDL_FILE romhi.vhd
++set_global_assignment -name VHDL_FILE ramint.vhd
+ set_global_assignment -name VHDL_FILE atari800core.vhd
+ set_global_assignment -name VHDL_FILE spi_master.vhd
+ set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+@@ -565,19 +305,12 @@
+ set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+ set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+ set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+-set_global_assignment -name VHDL_FILE i2s_intf.vhd
+-set_global_assignment -name VHDL_FILE i2c_loader.vhd
+ set_global_assignment -name VHDL_FILE cpu.vhd
+-set_global_assignment -name VHDL_FILE ledsw.vhd
+-set_global_assignment -name VHDL_FILE hexdecoder.vhd
+ set_global_assignment -name QIP_FILE pll.qip
+ set_global_assignment -name SDC_FILE atari800core.sdc
+-set_global_assignment -name VHDL_FILE dumprom.vhdl
+ set_global_assignment -name VHDL_FILE reg_file.vhdl
+ set_global_assignment -name VHDL_FILE address_decoder.vhdl
+-set_global_assignment -name VHDL_FILE i2sslave.vhdl
+ set_global_assignment -name VHDL_FILE pokey.vhdl
+-set_global_assignment -name VHDL_FILE nmigen.vhdl
+ set_global_assignment -name VHDL_FILE enable_divider.vhdl
+ set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+ set_global_assignment -name VHDL_FILE poly_5.vhdl
+@@ -587,11 +320,8 @@
+ set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+ set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+ set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+-set_global_assignment -name VHDL_FILE tvsync.vhdl
+ set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+ set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+-set_global_assignment -name VHDL_FILE flashrom.vhdl
+-set_global_assignment -name VHDL_FILE sram.vhdl
+ set_global_assignment -name VHDL_FILE antic.vhdl
+ set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+ set_global_assignment -name VHDL_FILE antic_counter.vhdl
+@@ -608,19 +338,11 @@
+ set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+ set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+ set_global_assignment -name VHDL_FILE irq_glue.vhdl
+-set_global_assignment -name VHDL_FILE gpio.vhd
+ set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+ set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+ set_global_assignment -name QIP_FILE zpu_ram.qip
+ set_global_assignment -name QIP_FILE zpu_rom.qip
+-set_location_assignment PIN_A13 -to GPIO_0[0]
+-set_location_assignment PIN_B13 -to GPIO_0[1]
+-set_location_assignment PIN_A14 -to GPIO_0[2]
+-set_location_assignment PIN_B14 -to GPIO_0[3]
+-
+-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+ set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+-
+-
+-
++set_global_assignment -name VHDL_FILE internalromram.vhd
++set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
+diff -ur atari800core_20140301_de1/atari800core.qsf~ atari800core_v1_20140121_mcc216/atari800core.qsf~
+--- atari800core_20140301_de1/atari800core.qsf~	2014-03-01 12:42:20.000000000 +0000
++++ atari800core_v1_20140121_mcc216/atari800core.qsf~	2014-01-26 10:34:19.000000000 +0000
+@@ -36,8 +36,8 @@
+ # -------------------------------------------------------------------------- #
+ 
+ 
+-set_global_assignment -name FAMILY "Cyclone II"
+-set_global_assignment -name DEVICE EP2C20F484C7
++set_global_assignment -name FAMILY "Cyclone III"
++set_global_assignment -name DEVICE EP3C16E144C8
+ set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+@@ -47,465 +47,36 @@
+ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+ set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+-set_location_assignment PIN_A15 -to GPIO_0[4]
+-set_location_assignment PIN_B15 -to GPIO_0[5]
+-set_location_assignment PIN_A16 -to GPIO_0[6]
+-set_location_assignment PIN_B16 -to GPIO_0[7]
+-set_location_assignment PIN_A17 -to GPIO_0[8]
+-set_location_assignment PIN_B17 -to GPIO_0[9]
+-set_location_assignment PIN_A18 -to GPIO_0[10]
+-set_location_assignment PIN_B18 -to GPIO_0[11]
+-set_location_assignment PIN_A19 -to GPIO_0[12]
+-set_location_assignment PIN_B19 -to GPIO_0[13]
+-set_location_assignment PIN_A20 -to GPIO_0[14]
+-set_location_assignment PIN_B20 -to GPIO_0[15]
+-set_location_assignment PIN_C21 -to GPIO_0[16]
+-set_location_assignment PIN_C22 -to GPIO_0[17]
+-set_location_assignment PIN_D21 -to GPIO_0[18]
+-set_location_assignment PIN_D22 -to GPIO_0[19]
+-set_location_assignment PIN_E21 -to GPIO_0[20]
+-set_location_assignment PIN_E22 -to GPIO_0[21]
+-set_location_assignment PIN_F21 -to GPIO_0[22]
+-set_location_assignment PIN_F22 -to GPIO_0[23]
+-set_location_assignment PIN_G21 -to GPIO_0[24]
+-set_location_assignment PIN_G22 -to GPIO_0[25]
+-set_location_assignment PIN_J21 -to GPIO_0[26]
+-set_location_assignment PIN_J22 -to GPIO_0[27]
+-set_location_assignment PIN_K21 -to GPIO_0[28]
+-set_location_assignment PIN_K22 -to GPIO_0[29]
+-set_location_assignment PIN_J19 -to GPIO_0[30]
+-set_location_assignment PIN_J20 -to GPIO_0[31]
+-set_location_assignment PIN_J18 -to GPIO_0[32]
+-set_location_assignment PIN_K20 -to GPIO_0[33]
+-set_location_assignment PIN_L19 -to GPIO_0[34]
+-set_location_assignment PIN_L18 -to GPIO_0[35]
+-set_location_assignment PIN_H12 -to GPIO_1[0]
+-set_location_assignment PIN_H13 -to GPIO_1[1]
+-set_location_assignment PIN_H14 -to GPIO_1[2]
+-set_location_assignment PIN_G15 -to GPIO_1[3]
+-set_location_assignment PIN_E14 -to GPIO_1[4]
+-set_location_assignment PIN_E15 -to GPIO_1[5]
+-set_location_assignment PIN_F15 -to GPIO_1[6]
+-set_location_assignment PIN_G16 -to GPIO_1[7]
+-set_location_assignment PIN_F12 -to GPIO_1[8]
+-set_location_assignment PIN_F13 -to GPIO_1[9]
+-set_location_assignment PIN_C14 -to GPIO_1[10]
+-set_location_assignment PIN_D14 -to GPIO_1[11]
+-set_location_assignment PIN_D15 -to GPIO_1[12]
+-set_location_assignment PIN_D16 -to GPIO_1[13]
+-set_location_assignment PIN_C17 -to GPIO_1[14]
+-set_location_assignment PIN_C18 -to GPIO_1[15]
+-set_location_assignment PIN_C19 -to GPIO_1[16]
+-set_location_assignment PIN_C20 -to GPIO_1[17]
+-set_location_assignment PIN_D19 -to GPIO_1[18]
+-set_location_assignment PIN_D20 -to GPIO_1[19]
+-set_location_assignment PIN_E20 -to GPIO_1[20]
+-set_location_assignment PIN_F20 -to GPIO_1[21]
+-set_location_assignment PIN_E19 -to GPIO_1[22]
+-set_location_assignment PIN_E18 -to GPIO_1[23]
+-set_location_assignment PIN_G20 -to GPIO_1[24]
+-set_location_assignment PIN_G18 -to GPIO_1[25]
+-set_location_assignment PIN_G17 -to GPIO_1[26]
+-set_location_assignment PIN_H17 -to GPIO_1[27]
+-set_location_assignment PIN_J15 -to GPIO_1[28]
+-set_location_assignment PIN_H18 -to GPIO_1[29]
+-set_location_assignment PIN_N22 -to GPIO_1[30]
+-set_location_assignment PIN_N21 -to GPIO_1[31]
+-set_location_assignment PIN_P15 -to GPIO_1[32]
+-set_location_assignment PIN_N15 -to GPIO_1[33]
+-set_location_assignment PIN_P17 -to GPIO_1[34]
+-set_location_assignment PIN_P18 -to GPIO_1[35]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+-set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+-set_location_assignment PIN_L22 -to SW[0]
+-set_location_assignment PIN_L21 -to SW[1]
+-set_location_assignment PIN_M22 -to SW[2]
+-set_location_assignment PIN_V12 -to SW[3]
+-set_location_assignment PIN_W12 -to SW[4]
+-set_location_assignment PIN_U12 -to SW[5]
+-set_location_assignment PIN_U11 -to SW[6]
+-set_location_assignment PIN_M2 -to SW[7]
+-set_location_assignment PIN_M1 -to SW[8]
+-set_location_assignment PIN_L2 -to SW[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+-set_location_assignment PIN_J2 -to HEX0[0]
+-set_location_assignment PIN_J1 -to HEX0[1]
+-set_location_assignment PIN_H2 -to HEX0[2]
+-set_location_assignment PIN_H1 -to HEX0[3]
+-set_location_assignment PIN_F2 -to HEX0[4]
+-set_location_assignment PIN_F1 -to HEX0[5]
+-set_location_assignment PIN_E2 -to HEX0[6]
+-set_location_assignment PIN_E1 -to HEX1[0]
+-set_location_assignment PIN_H6 -to HEX1[1]
+-set_location_assignment PIN_H5 -to HEX1[2]
+-set_location_assignment PIN_H4 -to HEX1[3]
+-set_location_assignment PIN_G3 -to HEX1[4]
+-set_location_assignment PIN_D2 -to HEX1[5]
+-set_location_assignment PIN_D1 -to HEX1[6]
+-set_location_assignment PIN_G5 -to HEX2[0]
+-set_location_assignment PIN_G6 -to HEX2[1]
+-set_location_assignment PIN_C2 -to HEX2[2]
+-set_location_assignment PIN_C1 -to HEX2[3]
+-set_location_assignment PIN_E3 -to HEX2[4]
+-set_location_assignment PIN_E4 -to HEX2[5]
+-set_location_assignment PIN_D3 -to HEX2[6]
+-set_location_assignment PIN_F4 -to HEX3[0]
+-set_location_assignment PIN_D5 -to HEX3[1]
+-set_location_assignment PIN_D6 -to HEX3[2]
+-set_location_assignment PIN_J4 -to HEX3[3]
+-set_location_assignment PIN_L8 -to HEX3[4]
+-set_location_assignment PIN_F3 -to HEX3[5]
+-set_location_assignment PIN_D4 -to HEX3[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+-set_location_assignment PIN_R22 -to KEY[0]
+-set_location_assignment PIN_R21 -to KEY[1]
+-set_location_assignment PIN_T22 -to KEY[2]
+-set_location_assignment PIN_T21 -to KEY[3]
+-set_location_assignment PIN_R20 -to LEDR[0]
+-set_location_assignment PIN_R19 -to LEDR[1]
+-set_location_assignment PIN_U19 -to LEDR[2]
+-set_location_assignment PIN_Y19 -to LEDR[3]
+-set_location_assignment PIN_T18 -to LEDR[4]
+-set_location_assignment PIN_V19 -to LEDR[5]
+-set_location_assignment PIN_Y18 -to LEDR[6]
+-set_location_assignment PIN_U18 -to LEDR[7]
+-set_location_assignment PIN_R18 -to LEDR[8]
+-set_location_assignment PIN_R17 -to LEDR[9]
+-set_location_assignment PIN_U22 -to LEDG[0]
+-set_location_assignment PIN_U21 -to LEDG[1]
+-set_location_assignment PIN_V22 -to LEDG[2]
+-set_location_assignment PIN_V21 -to LEDG[3]
+-set_location_assignment PIN_W22 -to LEDG[4]
+-set_location_assignment PIN_W21 -to LEDG[5]
+-set_location_assignment PIN_Y22 -to LEDG[6]
+-set_location_assignment PIN_Y21 -to LEDG[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+-set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+-set_location_assignment PIN_D12 -to CLOCK_27[0]
+-set_location_assignment PIN_E12 -to CLOCK_27[1]
+-set_location_assignment PIN_B12 -to CLOCK_24[0]
+-set_location_assignment PIN_A12 -to CLOCK_24[1]
+-set_location_assignment PIN_L1 -to CLOCK_50
+-set_location_assignment PIN_M21 -to EXT_CLOCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+-set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+-set_location_assignment PIN_H15 -to PS2_CLK
+-set_location_assignment PIN_J14 -to PS2_DAT
+-set_location_assignment PIN_F14 -to UART_RXD
+-set_location_assignment PIN_G12 -to UART_TXD
+-set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+-set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+-set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+-set_location_assignment PIN_E8 -to TDI
+-set_location_assignment PIN_D8 -to TCS
+-set_location_assignment PIN_C7 -to TCK
+-set_location_assignment PIN_D7 -to TDO
+-set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+-set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+-set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+-set_location_assignment PIN_D9 -to VGA_R[0]
+-set_location_assignment PIN_C9 -to VGA_R[1]
+-set_location_assignment PIN_A7 -to VGA_R[2]
+-set_location_assignment PIN_B7 -to VGA_R[3]
+-set_location_assignment PIN_B8 -to VGA_G[0]
+-set_location_assignment PIN_C10 -to VGA_G[1]
+-set_location_assignment PIN_B9 -to VGA_G[2]
+-set_location_assignment PIN_A8 -to VGA_G[3]
+-set_location_assignment PIN_A9 -to VGA_B[0]
+-set_location_assignment PIN_D11 -to VGA_B[1]
+-set_location_assignment PIN_A10 -to VGA_B[2]
+-set_location_assignment PIN_B10 -to VGA_B[3]
+-set_location_assignment PIN_A11 -to VGA_HS
+-set_location_assignment PIN_B11 -to VGA_VS
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+-set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+-set_location_assignment PIN_A3 -to I2C_SCLK
+-set_location_assignment PIN_B3 -to I2C_SDAT
+-set_location_assignment PIN_A6 -to AUD_ADCLRCK
+-set_location_assignment PIN_B6 -to AUD_ADCDAT
+-set_location_assignment PIN_A5 -to AUD_DACLRCK
+-set_location_assignment PIN_B5 -to AUD_DACDAT
+-set_location_assignment PIN_B4 -to AUD_XCK
+-set_location_assignment PIN_A4 -to AUD_BCLK
+-set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+-set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+-set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+-set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+-set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+-set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+-set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+-set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+-set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+-set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+-set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+-set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+-set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+-set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+-set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+-set_location_assignment PIN_U3 -to DRAM_BA_0
+-set_location_assignment PIN_V4 -to DRAM_BA_1
+-set_location_assignment PIN_T3 -to DRAM_CAS_N
+-set_location_assignment PIN_N3 -to DRAM_CKE
+-set_location_assignment PIN_U4 -to DRAM_CLK
+-set_location_assignment PIN_T6 -to DRAM_CS_N
+-set_location_assignment PIN_U1 -to DRAM_DQ[0]
+-set_location_assignment PIN_U2 -to DRAM_DQ[1]
+-set_location_assignment PIN_V1 -to DRAM_DQ[2]
+-set_location_assignment PIN_V2 -to DRAM_DQ[3]
+-set_location_assignment PIN_W1 -to DRAM_DQ[4]
+-set_location_assignment PIN_W2 -to DRAM_DQ[5]
+-set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+-set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+-set_location_assignment PIN_N1 -to DRAM_DQ[8]
+-set_location_assignment PIN_N2 -to DRAM_DQ[9]
+-set_location_assignment PIN_P1 -to DRAM_DQ[10]
+-set_location_assignment PIN_P2 -to DRAM_DQ[11]
+-set_location_assignment PIN_R1 -to DRAM_DQ[12]
+-set_location_assignment PIN_R2 -to DRAM_DQ[13]
+-set_location_assignment PIN_T1 -to DRAM_DQ[14]
+-set_location_assignment PIN_T2 -to DRAM_DQ[15]
+-set_location_assignment PIN_R7 -to DRAM_LDQM
+-set_location_assignment PIN_T5 -to DRAM_RAS_N
+-set_location_assignment PIN_M5 -to DRAM_UDQM
+-set_location_assignment PIN_R8 -to DRAM_WE_N
+-set_location_assignment PIN_AB20 -to FL_ADDR[0]
+-set_location_assignment PIN_AA14 -to FL_ADDR[1]
+-set_location_assignment PIN_Y16 -to FL_ADDR[2]
+-set_location_assignment PIN_R15 -to FL_ADDR[3]
+-set_location_assignment PIN_T15 -to FL_ADDR[4]
+-set_location_assignment PIN_U15 -to FL_ADDR[5]
+-set_location_assignment PIN_V15 -to FL_ADDR[6]
+-set_location_assignment PIN_W15 -to FL_ADDR[7]
+-set_location_assignment PIN_R14 -to FL_ADDR[8]
+-set_location_assignment PIN_Y13 -to FL_ADDR[9]
+-set_location_assignment PIN_R12 -to FL_ADDR[10]
+-set_location_assignment PIN_T12 -to FL_ADDR[11]
+-set_location_assignment PIN_AB14 -to FL_ADDR[12]
+-set_location_assignment PIN_AA13 -to FL_ADDR[13]
+-set_location_assignment PIN_AB13 -to FL_ADDR[14]
+-set_location_assignment PIN_AA12 -to FL_ADDR[15]
+-set_location_assignment PIN_AB12 -to FL_ADDR[16]
+-set_location_assignment PIN_AA20 -to FL_ADDR[17]
+-set_location_assignment PIN_U14 -to FL_ADDR[18]
+-set_location_assignment PIN_V14 -to FL_ADDR[19]
+-set_location_assignment PIN_U13 -to FL_ADDR[20]
+-set_location_assignment PIN_R13 -to FL_ADDR[21]
+-set_location_assignment PIN_AB16 -to FL_DQ[0]
+-set_location_assignment PIN_AA16 -to FL_DQ[1]
+-set_location_assignment PIN_AB17 -to FL_DQ[2]
+-set_location_assignment PIN_AA17 -to FL_DQ[3]
+-set_location_assignment PIN_AB18 -to FL_DQ[4]
+-set_location_assignment PIN_AA18 -to FL_DQ[5]
+-set_location_assignment PIN_AB19 -to FL_DQ[6]
+-set_location_assignment PIN_AA19 -to FL_DQ[7]
+-set_location_assignment PIN_AA15 -to FL_OE_N
+-set_location_assignment PIN_W14 -to FL_RST_N
+-set_location_assignment PIN_Y14 -to FL_WE_N
+-set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+-set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+-set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+-set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+-set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+-set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+-set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+-set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+-set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+-set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+-set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+-set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+-set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+-set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+-set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+-set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+-set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+-set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+-set_location_assignment PIN_AB5 -to SRAM_CE_N
+-set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+-set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+-set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+-set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+-set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+-set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+-set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+-set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+-set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+-set_location_assignment PIN_W9 -to SRAM_DQ[9]
+-set_location_assignment PIN_V9 -to SRAM_DQ[10]
+-set_location_assignment PIN_U9 -to SRAM_DQ[11]
+-set_location_assignment PIN_R9 -to SRAM_DQ[12]
+-set_location_assignment PIN_W8 -to SRAM_DQ[13]
+-set_location_assignment PIN_V8 -to SRAM_DQ[14]
+-set_location_assignment PIN_U8 -to SRAM_DQ[15]
+-set_location_assignment PIN_Y7 -to SRAM_LB_N
+-set_location_assignment PIN_T8 -to SRAM_OE_N
+-set_location_assignment PIN_W7 -to SRAM_UB_N
+-set_location_assignment PIN_AA10 -to SRAM_WE_N
+-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
++set_location_assignment PIN_135 -to VGA_R[0]
++set_location_assignment PIN_134 -to VGA_R[1]
++set_location_assignment PIN_133 -to VGA_R[2]
++set_location_assignment PIN_132 -to VGA_R[3]
++set_location_assignment PIN_141 -to VGA_G[0]
++set_location_assignment PIN_142 -to VGA_G[1]
++set_location_assignment PIN_143 -to VGA_G[2]
++set_location_assignment PIN_144 -to VGA_G[3]
++set_location_assignment PIN_4 -to VGA_B[0]
++set_location_assignment PIN_7 -to VGA_B[1]
++set_location_assignment PIN_10 -to VGA_B[2]
++set_location_assignment PIN_11 -to VGA_B[3]
++set_location_assignment PIN_136 -to VGA_HS
++set_location_assignment PIN_137 -to VGA_VS
+ set_global_assignment -name ENABLE_SIGNALTAP ON
+-set_location_assignment PIN_V20 -to SD_CLK
+-set_location_assignment PIN_Y20 -to SD_CMD
+-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
++set_location_assignment PIN_44 -to SD_CLK
++set_location_assignment PIN_46 -to SD_CMD
+ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+ set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+ set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+ set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+ set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+-set_location_assignment PIN_W20 -to SD_DATA
+-set_location_assignment PIN_U20 -to SD_THREE
+ set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name SMART_RECOMPILE ON
+ set_global_assignment -name ENABLE_DRC_SETTINGS ON
+ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+@@ -516,6 +87,104 @@
+ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+ set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+ set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
++
++set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
++set_location_assignment PIN_28 -to AUDIO_L
++set_location_assignment PIN_30 -to AUDIO_R
++set_location_assignment PIN_53 -to CPU_RESET_n
++set_location_assignment PIN_55 -to FPGA_CLK
++set_location_assignment PIN_127 -to JOY1_n[0]
++set_location_assignment PIN_91 -to JOY1_n[1]
++set_location_assignment PIN_90 -to JOY1_n[2]
++set_location_assignment PIN_88 -to JOY1_n[3]
++set_location_assignment PIN_89 -to JOY1_n[4]
++set_location_assignment PIN_126 -to JOY1_n[5]
++set_location_assignment PIN_128 -to JOY2_n[0]
++set_location_assignment PIN_25 -to JOY2_n[1]
++set_location_assignment PIN_24 -to JOY2_n[2]
++set_location_assignment PIN_22 -to JOY2_n[3]
++set_location_assignment PIN_23 -to JOY2_n[4]
++set_location_assignment PIN_129 -to JOY2_n[5]
++set_location_assignment PIN_33 -to PS2K_DAT
++set_location_assignment PIN_39 -to PS2K_CLK
++set_location_assignment PIN_32 -to PS2M_DAT
++set_location_assignment PIN_31 -to PS2M_CLK
++set_location_assignment PIN_52 -to SD_DAT0
++set_location_assignment PIN_49 -to SD_DAT3
++set_location_assignment PIN_42 -to USB_P
++set_location_assignment PIN_43 -to USB_N
++set_location_assignment PIN_50 -to USB2_P
++set_location_assignment PIN_51 -to USB2_N
++set_location_assignment PIN_112 -to SDRAM_CLK
++set_location_assignment PIN_61 -to SDRAM_A[0]
++set_location_assignment PIN_60 -to SDRAM_A[1]
++set_location_assignment PIN_59 -to SDRAM_A[2]
++set_location_assignment PIN_58 -to SDRAM_A[3]
++set_location_assignment PIN_125 -to SDRAM_A[4]
++set_location_assignment PIN_121 -to SDRAM_A[5]
++set_location_assignment PIN_120 -to SDRAM_A[6]
++set_location_assignment PIN_119 -to SDRAM_A[7]
++set_location_assignment PIN_115 -to SDRAM_A[8]
++set_location_assignment PIN_114 -to SDRAM_A[9]
++set_location_assignment PIN_64 -to SDRAM_A[10]
++set_location_assignment PIN_113 -to SDRAM_A[11]
++set_location_assignment PIN_111 -to SDRAM_A[12]
++set_location_assignment PIN_66 -to SDRAM_BA[0]
++set_location_assignment PIN_65 -to SDRAM_BA[1]
++set_location_assignment PIN_87 -to SDRAM_DQ[0]
++set_location_assignment PIN_86 -to SDRAM_DQ[1]
++set_location_assignment PIN_85 -to SDRAM_DQ[2]
++set_location_assignment PIN_83 -to SDRAM_DQ[3]
++set_location_assignment PIN_80 -to SDRAM_DQ[4]
++set_location_assignment PIN_79 -to SDRAM_DQ[5]
++set_location_assignment PIN_77 -to SDRAM_DQ[6]
++set_location_assignment PIN_76 -to SDRAM_DQ[7]
++set_location_assignment PIN_106 -to SDRAM_DQ[8]
++set_location_assignment PIN_105 -to SDRAM_DQ[9]
++set_location_assignment PIN_104 -to SDRAM_DQ[10]
++set_location_assignment PIN_103 -to SDRAM_DQ[11]
++set_location_assignment PIN_101 -to SDRAM_DQ[12]
++set_location_assignment PIN_100 -to SDRAM_DQ[13]
++set_location_assignment PIN_99 -to SDRAM_DQ[14]
++set_location_assignment PIN_98 -to SDRAM_DQ[15]
++set_location_assignment PIN_67 -to SDRAM_CS_n
++set_location_assignment PIN_68 -to SDRAM_RAS_n
++set_location_assignment PIN_69 -to SDRAM_CAS_n
++set_location_assignment PIN_71 -to SDRAM_WE_n
++set_location_assignment PIN_6 -to CFG_DOUT
++set_location_assignment PIN_8 -to CFG_CS_n
++set_location_assignment PIN_12 -to CFG_CLK
++set_location_assignment PIN_13 -to CFG_DIN
++set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
++set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
++set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
++set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
++set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
++set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
++set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
++set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
++set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
++set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
++set_global_assignment -name VHDL_FILE romlo.vhd
++set_global_assignment -name VHDL_FILE romhi.vhd
++set_global_assignment -name VHDL_FILE ramint.vhd
+ set_global_assignment -name VHDL_FILE atari800core.vhd
+ set_global_assignment -name VHDL_FILE spi_master.vhd
+ set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+@@ -526,19 +195,12 @@
+ set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+ set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+ set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+-set_global_assignment -name VHDL_FILE i2s_intf.vhd
+-set_global_assignment -name VHDL_FILE i2c_loader.vhd
+ set_global_assignment -name VHDL_FILE cpu.vhd
+-set_global_assignment -name VHDL_FILE ledsw.vhd
+-set_global_assignment -name VHDL_FILE hexdecoder.vhd
+ set_global_assignment -name QIP_FILE pll.qip
+ set_global_assignment -name SDC_FILE atari800core.sdc
+-set_global_assignment -name VHDL_FILE dumprom.vhdl
+ set_global_assignment -name VHDL_FILE reg_file.vhdl
+ set_global_assignment -name VHDL_FILE address_decoder.vhdl
+-set_global_assignment -name VHDL_FILE i2sslave.vhdl
+ set_global_assignment -name VHDL_FILE pokey.vhdl
+-set_global_assignment -name VHDL_FILE nmigen.vhdl
+ set_global_assignment -name VHDL_FILE enable_divider.vhdl
+ set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+ set_global_assignment -name VHDL_FILE poly_5.vhdl
+@@ -548,11 +210,8 @@
+ set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+ set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+ set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+-set_global_assignment -name VHDL_FILE tvsync.vhdl
+ set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+ set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+-set_global_assignment -name VHDL_FILE flashrom.vhdl
+-set_global_assignment -name VHDL_FILE sram.vhdl
+ set_global_assignment -name VHDL_FILE antic.vhdl
+ set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+ set_global_assignment -name VHDL_FILE antic_counter.vhdl
+@@ -569,18 +228,461 @@
+ set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+ set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+ set_global_assignment -name VHDL_FILE irq_glue.vhdl
+-set_global_assignment -name VHDL_FILE gpio.vhd
+ set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+ set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+ set_global_assignment -name QIP_FILE zpu_ram.qip
+ set_global_assignment -name QIP_FILE zpu_rom.qip
+-set_location_assignment PIN_A13 -to GPIO_0[0]
+-set_location_assignment PIN_B13 -to GPIO_0[1]
+-set_location_assignment PIN_A14 -to GPIO_0[2]
+-set_location_assignment PIN_B14 -to GPIO_0[3]
+-
+-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+ set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
++set_global_assignment -name VHDL_FILE internalromram.vhd
++set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "sdram_statemachine_mcc:b2v_inst20|CLK_SDRAM" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=221" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=221" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=686" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=45961" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=45082" -section_id auto_signaltap_0
+ 
+-
+-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
++set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+Only in atari800core_v1_20140121_mcc216: atari800core.qsf.bak
+Binary files atari800core_20140301_de1/atari800core.qws and atari800core_v1_20140121_mcc216/atari800core.qws differ
+diff -ur atari800core_20140301_de1/atari800core.sdc atari800core_v1_20140121_mcc216/atari800core.sdc
+--- atari800core_20140301_de1/atari800core.sdc	2014-03-01 12:29:51.000000000 +0000
++++ atari800core_v1_20140121_mcc216/atari800core.sdc	2014-01-21 19:27:45.000000000 +0000
+@@ -1,6 +1,3 @@
+-create_clock -period 50MHz [get_ports CLOCK_50]
+-derive_pll_clocks
+-
+-set_input_delay -max -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+-set_input_delay -min -clock CLOCK_50 -1.5 [get_ports SRAM_DQ*]
+-
++create_clock -period 5MHz [get_ports FPGA_CLK]
++derive_pll_clocks
++derive_clock_uncertainty
+\ No newline at end of file
+Only in atari800core_20140301_de1: atari800core.sdc~
+Only in atari800core_v1_20140121_mcc216: atari800core.sdc.bak
+diff -ur atari800core_20140301_de1/atari800core.vhd atari800core_v1_20140121_mcc216/atari800core.vhd
+--- atari800core_20140301_de1/atari800core.vhd	2014-01-20 20:13:33.000000000 +0000
++++ atari800core_v1_20140121_mcc216/atari800core.vhd	2014-01-28 20:47:59.000000000 +0000
+@@ -24,60 +24,39 @@
+ ENTITY atari800core IS 
+ 	PORT
+ 	(
+-		CLOCK_50 :  IN  STD_LOGIC;
+-		AUD_BCLK :  IN  STD_LOGIC;
+-		AUD_DACLRCK :  IN  STD_LOGIC;
+-		PS2_CLK :  IN  STD_LOGIC;
+-		PS2_DAT :  IN  STD_LOGIC;
+-		UART_RXD :  IN  STD_LOGIC;
+-		SD_DATA :  IN  STD_LOGIC;
+-		I2C_SCLK :  INOUT  STD_LOGIC;
+-		I2C_SDAT :  INOUT  STD_LOGIC;
+-		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+-		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+-		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		AUD_XCK :  OUT  STD_LOGIC;
+-		AUD_DACDAT :  OUT  STD_LOGIC;
++		FPGA_CLK :  IN  STD_LOGIC;
++		PS2K_CLK :  IN  STD_LOGIC;
++		PS2K_DAT :  IN  STD_LOGIC;
++		PS2M_CLK :  IN  STD_LOGIC;
++		PS2M_DAT :  IN  STD_LOGIC;		
++
+ 		VGA_VS :  OUT  STD_LOGIC;
+ 		VGA_HS :  OUT  STD_LOGIC;
+-		FL_OE_N :  OUT  STD_LOGIC;
+-		FL_WE_N :  OUT  STD_LOGIC;
+-		FL_RST_N :  OUT  STD_LOGIC;
+-		SRAM_CE_N :  OUT  STD_LOGIC;
+-		SRAM_OE_N :  OUT  STD_LOGIC;
+-		SRAM_WE_N :  OUT  STD_LOGIC;
+-		SRAM_LB_N :  OUT  STD_LOGIC;
+-		SRAM_UB_N :  OUT  STD_LOGIC;
+-		UART_TXD :  OUT  STD_LOGIC;
+-		DRAM_BA_0 :  OUT  STD_LOGIC;
+-		DRAM_BA_1 :  OUT  STD_LOGIC;
+-		DRAM_CS_N :  OUT  STD_LOGIC;
+-		DRAM_RAS_N :  OUT  STD_LOGIC;
+-		DRAM_CAS_N :  OUT  STD_LOGIC;
+-		DRAM_WE_N :  OUT  STD_LOGIC;
+-		DRAM_LDQM :  OUT  STD_LOGIC;
+-		DRAM_UDQM :  OUT  STD_LOGIC;
+-		DRAM_CLK :  OUT  STD_LOGIC;
+-		DRAM_CKE :  OUT  STD_LOGIC;
+-		SD_CLK :  OUT  STD_LOGIC;
+-		SD_CMD :  OUT  STD_LOGIC;
+-		SD_THREE :  OUT  STD_LOGIC;
+-		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+-		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+-		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+-		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+-		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+-		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+-		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+ 		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
++		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
++		
++		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		
++		AUDIO_L : OUT std_logic;
++		AUDIO_R : OUT std_logic;
++
++		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
++		SDRAM_CS_N :  OUT  STD_LOGIC;
++		SDRAM_RAS_N :  OUT  STD_LOGIC;
++		SDRAM_CAS_N :  OUT  STD_LOGIC;
++		SDRAM_WE_N :  OUT  STD_LOGIC;
++		SDRAM_DQM_n :  OUT  STD_LOGIC_vector(1 downto 0);
++		SDRAM_CLK :  OUT  STD_LOGIC;
++		--SDRAM_CKE :  OUT  STD_LOGIC;
++		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
++		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
++
++		SD_DAT0 :  IN  STD_LOGIC;
++		SD_CLK :  OUT  STD_LOGIC;
++		SD_CMD :  OUT  STD_LOGIC;
++		SD_DAT3 :  OUT  STD_LOGIC
+ 	);
+ END atari800core;
+ 
+@@ -100,32 +79,35 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT hexdecoder
+-	PORT(CLK : IN STD_LOGIC;
+-		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+-	);
+-END COMPONENT;
++component hq_dac
++port (
++  reset :in std_logic;
++  clk :in std_logic;
++  clk_ena : in std_logic;
++  pcm_in : in std_logic_vector(19 downto 0);
++  dac_out : out std_logic
++);
++end component;
+ 
+-COMPONENT sram
+-	PORT(WREN : IN STD_LOGIC;
+-		 clk : IN STD_LOGIC;
+-		 reset_n : IN STD_LOGIC;
+-		 request : IN STD_LOGIC;
+-		 width_16bit : IN STD_LOGIC;
+-		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+-		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 SRAM_CE_N : OUT STD_LOGIC;
+-		 SRAM_OE_N : OUT STD_LOGIC;
+-		 SRAM_WE_N : OUT STD_LOGIC;
+-		 SRAM_LB_N : OUT STD_LOGIC;
+-		 SRAM_UB_N : OUT STD_LOGIC;
+-		 complete : OUT STD_LOGIC;
+-		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
++component internalromram IS
++  PORT(
++    clock   : IN     STD_LOGIC;                             --system clock
++    reset_n : IN     STD_LOGIC;                             --asynchronous reset
++
++	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
++	ROM_REQUEST_COMPLETE : out STD_LOGIC;
++	ROM_REQUEST : in std_logic;
++	ROM_DATA : out std_logic_vector(7 downto 0);
++	
++	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
++	RAM_WR_ENABLE : in std_logic;
++	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
++	RAM_REQUEST_COMPLETE : out STD_LOGIC;
++	RAM_REQUEST : in std_logic;
++	RAM_DATA : out std_logic_vector(7 downto 0)
+ 	);
+-END COMPONENT;
++	
++END component;
+ 
+ COMPONENT antic
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -306,72 +288,11 @@
+ 		 SYSTEM_RESET : OUT STD_LOGIC;
+ 		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
++		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
++		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT gpio
+-	PORT(
+-	clk : in std_logic;
+-	
+-	gpio_enable : in std_logic;
+-
+-	-- pia
+-	porta_in : out std_logic_vector(7 downto 0);
+-	virtual_stick_in : in std_logic_vector(7 downto 0);
+-	porta_out : in std_logic_vector(7 downto 0);
+-	porta_output : in std_logic_vector(7 downto 0);
+-	CA2_DIR_OUT : IN std_logic;
+-	CA2_OUT : IN std_logic;
+-	CA2_IN : OUT STD_LOGIC;
+-	CB2_DIR_OUT : IN std_logic;
+-	CB2_OUT : IN std_logic;
+-	CB2_IN : OUT STD_LOGIC;
+-	
+-	-- gtia
+-	virtual_trig_in : in std_logic_vector(3 downto 0);
+-	trig_in : out std_logic_vector(3 downto 0);
+-	
+-	-- antic
+-	lightpen : out std_logic;
+-	
+-	-- pokey
+-	pot_reset : in std_logic;
+-	pot_in : out std_logic_vector(7 downto 0);
+-	keyboard_scan : in std_logic_vector(5 downto 0);
+-	keyboard_response : out std_logic_vector(1 downto 0);
+-	virtual_keycode : in std_logic_vector(5 downto 0);
+-	virtual_keyheld : in std_logic;
+-	virtual_shift_pressed : in std_logic;
+-	virtual_control_pressed : in std_logic;
+-	virtual_break_pressed : in std_logic;
+-	SIO_IN : OUT STD_LOGIC;
+-	SIO_OUT : IN STD_LOGIC;
+-	
+-	-- cartridge
+-	pbi_addr_out : in std_logic_vector(15 downto 0);
+-	pbi_write_enable : in std_logic;
+-	cart_data_read : out std_logic_vector(7 downto 0);
+-	cart_request : in std_logic;
+-	cart_complete : out std_logic;
+-	cart_data_write : in std_logic_vector(7 downto 0);
+-	rd4 : out std_logic;
+-	rd5 : out std_logic;
+-	s4_n : in std_logic;
+-	s5_n : in std_logic;
+-	cctl_n : in std_logic;
+-	
+-	monitor : in std_logic;
+-	
+-	-- gpio connections
+-	GPIO_0_IN : in std_logic_vector(35 downto 0);
+-	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+-	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+-	GPIO_1_IN : in std_logic_vector(35 downto 0);
+-	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+-	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+-	);
+-END COMPONENT;
+ 
+ COMPONENT address_decoder
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -391,7 +312,7 @@
+ 		 CART_RD4 : IN STD_LOGIC;
+ 		 CART_RD5 : IN STD_LOGIC;
+ 		 use_sdram : IN STD_LOGIC;
+-		 SDRAM_REPLY : IN STD_LOGIC;
++		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+ 		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ 		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+@@ -480,6 +401,50 @@
+ 	);
+ END COMPONENT;
+ 
++component sdram_statemachine_mcc IS
++generic
++(
++	ADDRESS_WIDTH : natural := 22;
++	ROW_WIDTH : natural := 12;
++	AP_BIT : natural := 10;
++	COLUMN_WIDTH : natural := 8
++);
++PORT 
++( 
++	CLK_SYSTEM : IN STD_LOGIC;
++	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
++	RESET_N : in STD_LOGIC;
++	
++	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
++	DATA_IN : in std_logic_vector(31 downto 0);
++	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
++	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
++	WRITE_EN : in std_logic;
++	REQUEST : in std_logic; -- Toggle this to issue a new request
++	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
++	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
++	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
++	REFRESH : in std_logic;
++
++	REPLY : out std_logic; -- This matches the request once complete
++	DATA_OUT : out std_logic_vector(31 downto 0);
++
++	-- sdram itself
++	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
++	SDRAM_DQ : inout std_logic_vector(15 downto 0);
++	SDRAM_BA0 : out std_logic;
++	SDRAM_BA1 : out std_logic;
++	
++	SDRAM_CS_N : out std_logic;
++	SDRAM_RAS_N : out std_logic;
++	SDRAM_CAS_N : out std_logic;
++	SDRAM_WE_N : out std_logic;
++	
++	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
++	SDRAM_udqm : out std_logic
++);
++END component;
++
+ COMPONENT zpu_rom
+ 	PORT(clock : IN STD_LOGIC;
+ 		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+@@ -551,36 +516,6 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT i2c_loader
+-GENERIC (device_address : INTEGER;
+-			log2_divider : INTEGER;
+-			num_retries : INTEGER
+-			);
+-	PORT(CLK : IN STD_LOGIC;
+-		 nRESET : IN STD_LOGIC;
+-		 I2C_SCL : INOUT STD_LOGIC;
+-		 I2C_SDA : INOUT STD_LOGIC;
+-		 IS_DONE : OUT STD_LOGIC;
+-		 IS_ERROR : OUT STD_LOGIC
+-	);
+-END COMPONENT;
+-
+-COMPONENT flashrom
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 REQUEST : IN STD_LOGIC;
+-		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+-		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 FLASH_CE_N : OUT STD_LOGIC;
+-		 FLASH_OE_N : OUT STD_LOGIC;
+-		 FLASH_WE_N : OUT STD_LOGIC;
+-		 FLASH_RESET_N : OUT STD_LOGIC;
+-		 COMPLETE : OUT STD_LOGIC;
+-		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+ COMPONENT pll
+ 	PORT(inclk0 : IN STD_LOGIC;
+ 		 c0 : OUT STD_LOGIC;
+@@ -590,17 +525,6 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT i2sslave
+-	PORT(CLK : IN STD_LOGIC;
+-		 BCLK : IN STD_LOGIC;
+-		 DACLRC : IN STD_LOGIC;
+-		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 MCLK_2 : OUT STD_LOGIC;
+-		 DACDAT : OUT STD_LOGIC
+-	);
+-END COMPONENT;
+-
+ COMPONENT gtia
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 WR_EN : IN STD_LOGIC;
+@@ -657,6 +581,7 @@
+ );
+ END component;
+ 
++
+ SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+@@ -672,7 +597,7 @@
+ SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+-SIGNAL	CART_CCTL_N :  STD_LOGIC;
++
+ SIGNAL	CART_RD4 :  STD_LOGIC;
+ SIGNAL	CART_RD5 :  STD_LOGIC;
+ SIGNAL	CART_REQUEST :  STD_LOGIC;
+@@ -680,6 +605,7 @@
+ SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	CART_S4_n :  STD_LOGIC;
+ SIGNAL	CART_S5_N :  STD_LOGIC;
++signal CART_CCTL_N : std_logic;
+ SIGNAL	CA2_OUT :  STD_LOGIC;
+ SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+ SIGNAL	CB2_OUT :  STD_LOGIC;
+@@ -770,7 +696,8 @@
+ SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+-SIGNAL	SDRAM_REPLY :  STD_LOGIC;
++--SIGNAL	SDRAM_REPLY :  STD_LOGIC;
++SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+ SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+ SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+@@ -786,6 +713,7 @@
+ SIGNAL	VGA :  STD_LOGIC;
+ SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
++SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+ SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+ SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+@@ -822,6 +750,9 @@
+ SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+ SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 
++SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
++SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
++signal UART_TXD_dummy : std_logic;
+ 
+ BEGIN 
+ 
+@@ -842,50 +773,7 @@
+ 		 A => CPU_ADDR,
+ 		 DO => CPU_DO);
+ 
+-
+-b2v_hex0_inst : hexdecoder
+-PORT MAP(CLK => CLK,
+-		 NUMBER => ZPU_HEX(3 DOWNTO 0),
+-		 DIGIT => HEX0);
+-
+-
+-b2v_hex0_inst2 : hexdecoder
+-PORT MAP(CLK => CLK,
+-		 NUMBER => ZPU_HEX(7 DOWNTO 4),
+-		 DIGIT => HEX1);
+-
+-
+-b2v_hex0_inst3 : hexdecoder
+-PORT MAP(CLK => CLK,
+-		 NUMBER => ZPU_HEX(11 DOWNTO 8),
+-		 DIGIT => HEX2);
+-
+-
+-b2v_hex0_inst4 : hexdecoder
+-PORT MAP(CLK => CLK,
+-		 NUMBER => ZPU_HEX(15 DOWNTO 12),
+-		 DIGIT => HEX3);
+-
+-
+-b2v_inst : sram
+-PORT MAP(WREN => RAM_WRITE_ENABLE,
+-		 clk => CLK,
+-		 reset_n => RESET_N,
+-		 request => RAM_REQUEST,
+-		 width_16bit => WIDTH_16BIT_ACCESS,
+-		 ADDRESS => RAM_ADDR,
+-		 DIN => WRITE_DATA(15 DOWNTO 0),
+-		 SRAM_DQ => SRAM_DQ,
+-		 SRAM_CE_N => SRAM_CE_N,
+-		 SRAM_OE_N => SRAM_OE_N,
+-		 SRAM_WE_N => SRAM_WE_N,
+-		 SRAM_LB_N => SRAM_LB_N,
+-		 SRAM_UB_N => SRAM_UB_N,
+-		 complete => RAM_REQUEST_COMPLETE,
+-		 DOUT => RAM_DO,
+-		 SRAM_ADDR => SRAM_ADDR);
+-
+-
++LIGHTPEN <= '1';
+ b2v_inst1 : antic
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => ANTIC_WRITE_ENABLE,
+@@ -909,15 +797,6 @@
+ 		 DATA_OUT => ANTIC_DO,
+ 		 dma_address_out => ANTIC_ADDR);
+ 
+-
+-b2v_inst10 : ledsw
+-PORT MAP(CLK => CLK,
+-		 KEY => KEY,
+-		 SW => SW,
+-		 SYNC_KEYS => SYNC_KEYS,
+-		 SYNC_SWITCHES => SYNC_SWITCHES);
+-
+-
+ b2v_inst11 : pokey_mixer
+ PORT MAP(CLK => CLK,
+ 		 GTIA_SOUND => GTIA_SOUND,
+@@ -927,13 +806,33 @@
+ 		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+ 		 CHANNEL_ENABLE => "1111",
+ 		 VOLUME_OUT => AUDIO_LEFT);
++		 
++dac_left : hq_dac
++port map
++(
++  reset => not(reset_n),
++  clk => clk,
++  clk_ena => '1',
++  pcm_in => audio_left&"0000",
++  dac_out => audio_l
++);
++
++dac_right : hq_dac
++port map
++(
++  reset => not(reset_n),
++  clk => clk,
++  clk_ena => '1',
++  pcm_in => audio_right&"0000",
++  dac_out => audio_r
++);
+ 
+ 
+ b2v_inst12 : ps2_keyboard
+ PORT MAP(CLK => CLK,
+ 		 RESET_N => RESET_N,
+-		 PS2_CLK => PS2_CLK,
+-		 PS2_DAT => PS2_DAT,
++		 PS2_CLK => PS2K_CLK,
++		 PS2_DAT => PS2K_DAT,
+ 		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+ 		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+ 		 KEY_UP => SYNTHESIZED_WIRE_10,
+@@ -1001,6 +900,9 @@
+ SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+ -- TODO - sioto gpio!
+ GPIO_PORTB_IN <= PORTB_OUT;
++GPIO_CA2_IN <= CA2_OUT;
++GPIO_CB2_IN <= CB2_OUT;
++GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
+ 
+ b2v_inst16 : pia
+ PORT MAP(CLK => CLK,
+@@ -1058,65 +960,14 @@
+ 		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+ 		 KBCODE => KBCODE,
+ 		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+-		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
+-
+-gpio0_gen:
+-   for I in 0 to 35 generate
+-		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+-   end generate gpio0_gen;
+-
+-gpio1_gen:
+-   for I in 0 to 35 generate
+-		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+-   end generate gpio1_gen;
+-	
+-b2v_inst19 : gpio
+-PORT MAP(clk => CLK,
+-		 gpio_enable => GPIO_ENABLE,
+-		 pot_reset => POT_RESET,
+-		 virtual_keyheld => KEY_HELD,
+-		 virtual_shift_pressed => SHIFT_PRESSED,
+-		 virtual_control_pressed => KBCODE(7),
+-		 virtual_break_pressed => BREAK_PRESSED,
+-		 pbi_write_enable => PBI_WRITE_ENABLE,
+-		 cart_request => CART_REQUEST,
+-		 s4_n => CART_S4_n,
+-		 s5_n => CART_S5_N,
+-		 cctl_n => CART_CCTL_N,
+-		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+-		 GPIO_0_IN => GPIO_0,
+-		 GPIO_0_OUT => GPIO_0_OUT,
+-		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+-		 GPIO_1_IN => GPIO_1,
+-		 GPIO_1_OUT => GPIO_1_OUT,
+-		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+-		 keyboard_scan => KEYBOARD_SCAN,
+-		 pbi_addr_out => PBI_ADDR,
+-		 porta_out => PORTA_OUT,
+-		 porta_output => PORTA_DIR_OUT,
+-		 virtual_keycode => KBCODE(5 DOWNTO 0),
+-		 virtual_stick_in => VIRTUAL_STICKS,
+-		 virtual_trig_in => VIRTUAL_TRIGGERS,
+-		 lightpen => LIGHTPEN,
+-		 cart_complete => CART_REQUEST_COMPLETE,
+-		 rd4 => CART_RD4,
+-		 rd5 => CART_RD5,
+-		 cart_data_read => CART_ROM_DO,
+-		 keyboard_response => KEYBOARD_RESPONSE,
+-		 porta_in => GPIO_PORTA_IN,
+-		 pot_in => POT_IN,
+-		 trig_in => TRIGGERS,
+-		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+-		 CA2_DIR_OUT => CA2_DIR_OUT,
+-		 CA2_OUT => CA2_OUT,
+-		 CA2_IN => GPIO_CA2_IN,
+-		 CB2_DIR_OUT => CB2_DIR_OUT,
+-		 CB2_OUT => CB2_OUT,
+-		 CB2_IN => GPIO_CB2_IN,
+-		 SIO_IN => GPIO_SIO_IN,
+-		 SIO_OUT => GPIO_SIO_OUT
+-		 );
++		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
++		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+ 
++-- no cart!
++CART_RD4 <= '0';
++CART_RD5 <= '0';
++CART_REQUEST_COMPLETE <= '0';
++CART_ROM_DO <= (others=>'0');
+ 
+ b2v_inst2 : address_decoder
+ PORT MAP(CLK => CLK,
+@@ -1136,7 +987,7 @@
+ 		 CART_RD4 => CART_RD4,
+ 		 CART_RD5 => CART_RD5,
+ 		 use_sdram => USE_SDRAM,
+-		 SDRAM_REPLY => SDRAM_REPLY,
++		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+ 		 ANTIC_ADDR => ANTIC_ADDR,
+ 		 ANTIC_DATA => ANTIC_DO,
+ 		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+@@ -1189,40 +1040,6 @@
+ 		 SDRAM_ADDR => SDRAM_ADDR,
+ 		 WRITE_DATA => WRITE_DATA);
+ 
+-
+-b2v_inst20 : sdram_statemachine
+-GENERIC MAP(ADDRESS_WIDTH => 22,
+-			AP_BIT => 10,
+-			COLUMN_WIDTH => 8,
+-			ROW_WIDTH => 12
+-			)
+-PORT MAP(CLK_SYSTEM => CLK,
+-		 CLK_SDRAM => CLK_SDRAM,
+-		 RESET_N => RESET_N,
+-		 READ_EN => SDRAM_READ_ENABLE,
+-		 WRITE_EN => SDRAM_WRITE_ENABLE,
+-		 REQUEST => SDRAM_REQUEST,
+-		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+-		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+-		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+-		 REFRESH => SDRAM_REFRESH,
+-		 ADDRESS_IN => SDRAM_ADDR,
+-		 DATA_IN => WRITE_DATA,
+-		 SDRAM_DQ => DRAM_DQ,
+-		 REPLY => SDRAM_REPLY,
+-		 SDRAM_BA0 => DRAM_BA_0,
+-		 SDRAM_BA1 => DRAM_BA_1,
+-		 SDRAM_CKE => DRAM_CKE,
+-		 SDRAM_CS_N => DRAM_CS_N,
+-		 SDRAM_RAS_N => DRAM_RAS_N,
+-		 SDRAM_CAS_N => DRAM_CAS_N,
+-		 SDRAM_WE_N => DRAM_WE_N,
+-		 SDRAM_ldqm => DRAM_LDQM,
+-		 SDRAM_udqm => DRAM_UDQM,
+-		 DATA_OUT => SDRAM_DO,
+-		 SDRAM_ADDR => DRAM_ADDR);
+-
+-
+ b2v_inst21 : zpu_rom
+ PORT MAP(clock => CLK,
+ 		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+@@ -1253,23 +1070,24 @@
+ 		 data => ZPU_DO(23 DOWNTO 16),
+ 		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+ 
+-
++SYNC_KEYS <= (others=> '0');
++SYNC_SWITCHES <= (others=> '1');
+ b2v_inst24 : zpu_config_regs
+ PORT MAP(CLK => CLK,
+ 		 ENABLE_179 => POKEY_ENABLE_179,
+ 		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+-		 SDCARD_DAT => SD_DATA,
++		 SDCARD_DAT => SD_DAT0,
+ 		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+ 		 SIO_DATA_OUT => SIO_DATA_OUT,
+ 		 PLL_LOCKED => PLL_LOCKED,
+ 		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+ 		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+ 		 CPU_DATA_IN => ZPU_DO,
+-		 KEY => SYNC_KEYS,
++		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+ 		 SWITCH => SYNC_SWITCHES,
+ 		 SDCARD_CLK => SD_CLK,
+ 		 SDCARD_CMD => SD_CMD,
+-		 SDCARD_DAT3 => SD_THREE,
++		 SDCARD_DAT3 => SD_DAT3,
+ 		 SIO_DATA_IN => SIO_DATA_IN,
+ 		 PAUSE_ZPU => ZPU_PAUSE,
+ 		 PAL => PAL,
+@@ -1282,8 +1100,8 @@
+ 		 RESET_N => RESET_N,
+ 		 PAUSE_6502 => PAUSE_6502,
+ 		 DATA_OUT => ZPU_CONFIG_DO,
+-		 LEDG => LEDG,
+-		 LEDR => LEDR,
++		 LEDG => LEDG_dummy,
++		 LEDR => LEDR_dummy,
+ 		 RAM_SELECT => RAM_SELECT,
+ 		 ROM_SELECT => ROM_SELECT,
+ 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+@@ -1314,64 +1132,28 @@
+ 		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+ 
+ 
+-b2v_inst3 : i2c_loader
+-GENERIC MAP(device_address => 26,
+-			log2_divider => 6,
+-			num_retries => 0
+-			)
+-PORT MAP(CLK => CLK,
+-		 nRESET => RESET_N,
+-		 I2C_SCL => I2C_SCLK,
+-		 I2C_SDA => I2C_SDAT);
+-
+-
+-b2v_inst4 : flashrom
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 REQUEST => ROM_REQUEST,
+-		 ADDRESS => ROM_ADDR,
+-		 FLASH_D => FL_DQ,
+-		 FLASH_OE_N => FL_OE_N,
+-		 FLASH_WE_N => FL_WE_N,
+-		 FLASH_RESET_N => FL_RST_N,
+-		 COMPLETE => ROM_REQUEST_COMPLETE,
+-		 DOUT => ROM_DO,
+-		 FLASH_ADDRESS => FL_ADDR);
+-
+-
+ b2v_inst5 : pll
+-PORT MAP(inclk0 => CLOCK_50,
++PORT MAP(inclk0 => FPGA_CLK,
+ 		 c0 => CLK_SDRAM,
+ 		 c1 => CLK,
+-		 c2 => DRAM_CLK,
++		 c2 => SDRAM_CLK,
+ 		 locked => PLL_LOCKED);
+ 
+-
+-b2v_inst6 : i2sslave
+-PORT MAP(CLK => CLK,
+-		 BCLK => AUD_BCLK,
+-		 DACLRC => AUD_DACLRCK,
+-		 LEFT_IN => AUDIO_LEFT,
+-		 RIGHT_IN => AUDIO_RIGHT,
+-		 MCLK_2 => AUD_XCK,
+-		 DACDAT => AUD_DACDAT);
+-
+-
+ b2v_inst7 : pokey
+ PORT MAP(CLK => CLK,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+ 		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+ 		 WR_EN => POKEY_WRITE_ENABLE,
+ 		 RESET_N => RESET_N,
+-		 SIO_IN1 => UART_RXD,
+-		 SIO_IN2 => GPIO_SIO_IN,
++		 SIO_IN1 => '1',
++		 SIO_IN2 => '1',
+ 		 SIO_IN3 => SIO_DATA_IN,
+ 		 ADDR => PBI_ADDR(3 DOWNTO 0),
+ 		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+ 		 keyboard_response => KEYBOARD_RESPONSE,
+ 		 POT_IN => POT_IN,
+ 		 IRQ_N_OUT => POKEY_IRQ,
+-		 SIO_OUT1 => UART_TXD,
++		 SIO_OUT1 => UART_TXD_dummy,
+ 		 SIO_OUT2 => GPIO_SIO_OUT,
+ 		 SIO_OUT3 => SIO_DATA_OUT,
+ 		 POT_RESET => POT_RESET,
+@@ -1382,6 +1164,27 @@
+ 		 DATA_OUT => POKEY_DO,
+ 		 keyboard_scan => KEYBOARD_SCAN);
+ 
++	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
++	begin	
++		keyboard_response <= (others=>'1');
++		
++		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
++			keyboard_response(0) <= '0';
++		end if;
++		
++		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++		
++		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++
++		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++	end process;		 
++		 	 
+ b2v_inst8 : gtia
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => GTIA_WRITE_ENABLE,
+@@ -1397,10 +1200,12 @@
+ 		 CONSOL_START => CONSOL_START,
+ 		 CONSOL_SELECT => CONSOL_SELECT,
+ 		 CONSOL_OPTION => CONSOL_OPTION,
+-		 TRIG0 => TRIGGERS(0),
+-		 TRIG1 => TRIGGERS(1),
+-		 TRIG2 => TRIGGERS(2),
+-		 TRIG3 => TRIGGERS(3),
++		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
++		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
++		 --TRIG0 => VIRTUAL_TRIGGERS(0),
++		 --TRIG1 => VIRTUAL_TRIGGERS(1),
++		 TRIG2 => VIRTUAL_TRIGGERS(2),
++		 TRIG3 => VIRTUAL_TRIGGERS(3),
+ 		 ADDR => PBI_ADDR(4 DOWNTO 0),
+ 		 AN => ANTIC_AN,
+ 		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+@@ -1458,4 +1263,87 @@
+ 	DATA_OUT => CACHE_ANTIC_DO
+ );	
+ 
++irr : internalromram
++  PORT map(
++    clock => clk,
++    reset_n => reset_n,
++
++	ROM_ADDR =>rom_addr,
++	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
++	ROM_REQUEST => rom_REQUEST,
++	ROM_DATA => rom_DO,
++	
++	RAM_ADDR => ram_addr,
++	RAM_WR_ENABLE => ram_WRITE_ENABLE,
++	RAM_DATA_IN => wriTE_DATA(7 downto 0),
++	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
++	RAM_REQUEST => ram_REQUEST,
++	RAM_DATA => ram_do(7 downto 0)
++	);
++
++--b2v_inst20 : sdram_statemachine
++--GENERIC MAP(ADDRESS_WIDTH => 22,
++--			AP_BIT => 10,
++--			COLUMN_WIDTH => 8,
++--			ROW_WIDTH => 12
++--			)
++--PORT MAP(CLK_SYSTEM => CLK,
++--		 CLK_SDRAM => CLK_SDRAM,
++--		 RESET_N => RESET_N,
++--		 READ_EN => SDRAM_READ_ENABLE,
++--		 WRITE_EN => SDRAM_WRITE_ENABLE,
++--		 REQUEST => SDRAM_REQUEST,
++--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
++--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
++--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
++--		 REFRESH => SDRAM_REFRESH,
++--		 ADDRESS_IN => SDRAM_ADDR,
++--		 DATA_IN => WRITE_DATA,
++--		 SDRAM_DQ => SDRAM_DQ,
++--		 REPLY => SDRAM_REPLY,
++--		 SDRAM_BA0 => SDRAM_BA(0),
++--		 SDRAM_BA1 => SDRAM_BA(1),
++--		 SDRAM_CKE => SDRAM_A(12),
++--		 SDRAM_CS_N => SDRAM_CS_N,
++--		 SDRAM_RAS_N => SDRAM_RAS_N,
++--		 SDRAM_CAS_N => SDRAM_CAS_N,
++--		 SDRAM_WE_N => SDRAM_WE_N,
++--		 SDRAM_ldqm => SDRAM_DQM_n(0),
++--		 SDRAM_udqm => SDRAM_DQM_n(1),
++--		 DATA_OUT => SDRAM_DO,
++--		 SDRAM_ADDR => SDRAM_A(11 downto 0));
++
++b2v_inst20 : sdram_statemachine_mcc
++GENERIC MAP(ADDRESS_WIDTH => 22,
++			AP_BIT => 10,
++			COLUMN_WIDTH => 8,
++			ROW_WIDTH => 12
++			)
++PORT MAP(CLK_SYSTEM => CLK,
++		 CLK_SDRAM => CLK_SDRAM,
++		 RESET_N => RESET_N,
++		 READ_EN => SDRAM_READ_ENABLE,
++		 WRITE_EN => SDRAM_WRITE_ENABLE,
++		 REQUEST => SDRAM_REQUEST,
++		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
++		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
++		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
++		 REFRESH => SDRAM_REFRESH,
++		 ADDRESS_IN => SDRAM_ADDR,
++		 DATA_IN => WRITE_DATA,
++		 SDRAM_DQ => SDRAM_DQ,
++		 REPLY => SDRAM_REQUEST_COMPLETE,
++		 SDRAM_BA0 => SDRAM_BA(0),
++		 SDRAM_BA1 => SDRAM_BA(1),
++		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
++		 SDRAM_CS_N => SDRAM_CS_N,
++		 SDRAM_RAS_N => SDRAM_RAS_N,
++		 SDRAM_CAS_N => SDRAM_CAS_N,
++		 SDRAM_WE_N => SDRAM_WE_N,
++		 SDRAM_ldqm => SDRAM_DQM_n(0),
++		 SDRAM_udqm => SDRAM_DQM_n(1),
++		 DATA_OUT => SDRAM_DO,
++		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
++
++		
+ END bdf_type;
+\ No newline at end of file
+Only in atari800core_v1_20140121_mcc216: hq_dac.v
+Only in atari800core_v1_20140121_mcc216: internalromram.vhd
+Only in atari800core_v1_20140121_mcc216: internalromram.vhd.bak
+Only in atari800core_v1_20140121_mcc216: pll.bsf
+diff -ur atari800core_20140301_de1/pll.cmp atari800core_v1_20140121_mcc216/pll.cmp
+--- atari800core_20140301_de1/pll.cmp	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140121_mcc216/pll.cmp	2014-01-26 09:19:13.000000000 +0000
+@@ -1,25 +1,25 @@
+---Copyright (C) 1991-2012 Altera Corporation
+---Your use of Altera Corporation's design tools, logic functions 
+---and other software and tools, and its AMPP partner logic 
+---functions, and any output files from any of the foregoing 
+---(including device programming or simulation files), and any 
+---associated documentation or information are expressly subject 
+---to the terms and conditions of the Altera Program License 
+---Subscription Agreement, Altera MegaCore Function License 
+---Agreement, or other applicable license agreement, including, 
+---without limitation, that your use is for the sole purpose of 
+---programming logic devices manufactured by Altera and sold by 
+---Altera or its authorized distributors.  Please refer to the 
+---applicable agreement for further details.
+-
+-
+-component pll
+-	PORT
+-	(
+-		inclk0		: IN STD_LOGIC  := '0';
+-		c0		: OUT STD_LOGIC ;
+-		c1		: OUT STD_LOGIC ;
+-		c2		: OUT STD_LOGIC ;
+-		locked		: OUT STD_LOGIC 
+-	);
+-end component;
++--Copyright (C) 1991-2012 Altera Corporation
++--Your use of Altera Corporation's design tools, logic functions 
++--and other software and tools, and its AMPP partner logic 
++--functions, and any output files from any of the foregoing 
++--(including device programming or simulation files), and any 
++--associated documentation or information are expressly subject 
++--to the terms and conditions of the Altera Program License 
++--Subscription Agreement, Altera MegaCore Function License 
++--Agreement, or other applicable license agreement, including, 
++--without limitation, that your use is for the sole purpose of 
++--programming logic devices manufactured by Altera and sold by 
++--Altera or its authorized distributors.  Please refer to the 
++--applicable agreement for further details.
++
++
++component pll
++	PORT
++	(
++		inclk0		: IN STD_LOGIC  := '0';
++		c0		: OUT STD_LOGIC ;
++		c1		: OUT STD_LOGIC ;
++		c2		: OUT STD_LOGIC ;
++		locked		: OUT STD_LOGIC 
++	);
++end component;
+Only in atari800core_v1_20140121_mcc216: PLLJ_PLLSPE_INFO.txt
+diff -ur atari800core_20140301_de1/pll.ppf atari800core_v1_20140121_mcc216/pll.ppf
+--- atari800core_20140301_de1/pll.ppf	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140121_mcc216/pll.ppf	2014-01-26 09:19:13.000000000 +0000
+@@ -1,12 +1,12 @@
+-<?xml version="1.0" encoding="UTF-8" ?>
+-<!DOCTYPE pinplan>
+-<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+-<global>
+-<pin name="inclk0" direction="input" scope="external" source="clock"  />
+-<pin name="c0" direction="output" scope="external" source="clock"  />
+-<pin name="c1" direction="output" scope="external" source="clock"  />
+-<pin name="c2" direction="output" scope="external" source="clock"  />
+-<pin name="locked" direction="output" scope="external"  />
+-
+-</global>
+-</pinplan>
++<?xml version="1.0" encoding="UTF-8" ?>
++<!DOCTYPE pinplan>
++<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
++<global>
++<pin name="inclk0" direction="input" scope="external" source="clock"  />
++<pin name="c0" direction="output" scope="external" source="clock"  />
++<pin name="c1" direction="output" scope="external" source="clock"  />
++<pin name="c2" direction="output" scope="external" source="clock"  />
++<pin name="locked" direction="output" scope="external"  />
++
++</global>
++</pinplan>
+diff -ur atari800core_20140301_de1/pll.qip atari800core_v1_20140121_mcc216/pll.qip
+--- atari800core_20140301_de1/pll.qip	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140121_mcc216/pll.qip	2014-01-26 09:19:14.000000000 +0000
+@@ -1,6 +1,6 @@
+-set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+-set_global_assignment -name IP_TOOL_VERSION "12.1"
+-set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
++set_global_assignment -name IP_TOOL_NAME "ALTPLL"
++set_global_assignment -name IP_TOOL_VERSION "12.1"
++set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
++set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
++set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
++set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
+diff -ur atari800core_20140301_de1/pll.vhd atari800core_v1_20140121_mcc216/pll.vhd
+--- atari800core_20140301_de1/pll.vhd	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140121_mcc216/pll.vhd	2014-01-26 09:19:13.000000000 +0000
+@@ -1,427 +1,424 @@
+--- megafunction wizard: %ALTPLL%
+--- GENERATION: STANDARD
+--- VERSION: WM1.0
+--- MODULE: altpll 
+-
+--- ============================================================
+--- File Name: pll.vhd
+--- Megafunction Name(s):
+--- 			altpll
+---
+--- Simulation Library Files(s):
+--- 			altera_mf
+--- ============================================================
+--- ************************************************************
+--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+---
+--- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+--- ************************************************************
+-
+-
+---Copyright (C) 1991-2012 Altera Corporation
+---Your use of Altera Corporation's design tools, logic functions 
+---and other software and tools, and its AMPP partner logic 
+---functions, and any output files from any of the foregoing 
+---(including device programming or simulation files), and any 
+---associated documentation or information are expressly subject 
+---to the terms and conditions of the Altera Program License 
+---Subscription Agreement, Altera MegaCore Function License 
+---Agreement, or other applicable license agreement, including, 
+---without limitation, that your use is for the sole purpose of 
+---programming logic devices manufactured by Altera and sold by 
+---Altera or its authorized distributors.  Please refer to the 
+---applicable agreement for further details.
+-
+-
+-LIBRARY ieee;
+-USE ieee.std_logic_1164.all;
+-
+-LIBRARY altera_mf;
+-USE altera_mf.all;
+-
+-ENTITY pll IS
+-	PORT
+-	(
+-		inclk0		: IN STD_LOGIC  := '0';
+-		c0		: OUT STD_LOGIC ;
+-		c1		: OUT STD_LOGIC ;
+-		c2		: OUT STD_LOGIC ;
+-		locked		: OUT STD_LOGIC 
+-	);
+-END pll;
+-
+-
+-ARCHITECTURE SYN OF pll IS
+-
+-	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+-	SIGNAL sub_wire1	: STD_LOGIC ;
+-	SIGNAL sub_wire2	: STD_LOGIC ;
+-	SIGNAL sub_wire3	: STD_LOGIC ;
+-	SIGNAL sub_wire4	: STD_LOGIC ;
+-	SIGNAL sub_wire5	: STD_LOGIC ;
+-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+-
+-
+-
+-	COMPONENT altpll
+-	GENERIC (
+-		clk0_divide_by		: NATURAL;
+-		clk0_duty_cycle		: NATURAL;
+-		clk0_multiply_by		: NATURAL;
+-		clk0_phase_shift		: STRING;
+-		clk1_divide_by		: NATURAL;
+-		clk1_duty_cycle		: NATURAL;
+-		clk1_multiply_by		: NATURAL;
+-		clk1_phase_shift		: STRING;
+-		clk2_divide_by		: NATURAL;
+-		clk2_duty_cycle		: NATURAL;
+-		clk2_multiply_by		: NATURAL;
+-		clk2_phase_shift		: STRING;
+-		compensate_clock		: STRING;
+-		gate_lock_counter		: NATURAL;
+-		gate_lock_signal		: STRING;
+-		inclk0_input_frequency		: NATURAL;
+-		intended_device_family		: STRING;
+-		invalid_lock_multiplier		: NATURAL;
+-		lpm_hint		: STRING;
+-		lpm_type		: STRING;
+-		operation_mode		: STRING;
+-		port_activeclock		: STRING;
+-		port_areset		: STRING;
+-		port_clkbad0		: STRING;
+-		port_clkbad1		: STRING;
+-		port_clkloss		: STRING;
+-		port_clkswitch		: STRING;
+-		port_configupdate		: STRING;
+-		port_fbin		: STRING;
+-		port_inclk0		: STRING;
+-		port_inclk1		: STRING;
+-		port_locked		: STRING;
+-		port_pfdena		: STRING;
+-		port_phasecounterselect		: STRING;
+-		port_phasedone		: STRING;
+-		port_phasestep		: STRING;
+-		port_phaseupdown		: STRING;
+-		port_pllena		: STRING;
+-		port_scanaclr		: STRING;
+-		port_scanclk		: STRING;
+-		port_scanclkena		: STRING;
+-		port_scandata		: STRING;
+-		port_scandataout		: STRING;
+-		port_scandone		: STRING;
+-		port_scanread		: STRING;
+-		port_scanwrite		: STRING;
+-		port_clk0		: STRING;
+-		port_clk1		: STRING;
+-		port_clk2		: STRING;
+-		port_clk3		: STRING;
+-		port_clk4		: STRING;
+-		port_clk5		: STRING;
+-		port_clkena0		: STRING;
+-		port_clkena1		: STRING;
+-		port_clkena2		: STRING;
+-		port_clkena3		: STRING;
+-		port_clkena4		: STRING;
+-		port_clkena5		: STRING;
+-		port_extclk0		: STRING;
+-		port_extclk1		: STRING;
+-		port_extclk2		: STRING;
+-		port_extclk3		: STRING;
+-		valid_lock_multiplier		: NATURAL
+-	);
+-	PORT (
+-			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+-			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+-			locked	: OUT STD_LOGIC 
+-	);
+-	END COMPONENT;
+-
+-BEGIN
+-	sub_wire7_bv(0 DOWNTO 0) <= "0";
+-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+-	sub_wire4    <= sub_wire0(2);
+-	sub_wire3    <= sub_wire0(0);
+-	sub_wire1    <= sub_wire0(1);
+-	c1    <= sub_wire1;
+-	locked    <= sub_wire2;
+-	c0    <= sub_wire3;
+-	c2    <= sub_wire4;
+-	sub_wire5    <= inclk0;
+-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+-
+-	altpll_component : altpll
+-	GENERIC MAP (
+-		clk0_divide_by => 10,
+-		clk0_duty_cycle => 50,
+-		clk0_multiply_by => 23,
+-		clk0_phase_shift => "0",
+-		clk1_divide_by => 20,
+-		clk1_duty_cycle => 50,
+-		clk1_multiply_by => 23,
+-		clk1_phase_shift => "0",
+-		clk2_divide_by => 10,
+-		clk2_duty_cycle => 50,
+-		clk2_multiply_by => 23,
+-		clk2_phase_shift => "-1280",
+-		compensate_clock => "CLK0",
+-		gate_lock_counter => 1048575,
+-		gate_lock_signal => "YES",
+-		inclk0_input_frequency => 20000,
+-		intended_device_family => "Cyclone II",
+-		invalid_lock_multiplier => 5,
+-		lpm_hint => "CBX_MODULE_PREFIX=pll",
+-		lpm_type => "altpll",
+-		operation_mode => "NORMAL",
+-		port_activeclock => "PORT_UNUSED",
+-		port_areset => "PORT_UNUSED",
+-		port_clkbad0 => "PORT_UNUSED",
+-		port_clkbad1 => "PORT_UNUSED",
+-		port_clkloss => "PORT_UNUSED",
+-		port_clkswitch => "PORT_UNUSED",
+-		port_configupdate => "PORT_UNUSED",
+-		port_fbin => "PORT_UNUSED",
+-		port_inclk0 => "PORT_USED",
+-		port_inclk1 => "PORT_UNUSED",
+-		port_locked => "PORT_USED",
+-		port_pfdena => "PORT_UNUSED",
+-		port_phasecounterselect => "PORT_UNUSED",
+-		port_phasedone => "PORT_UNUSED",
+-		port_phasestep => "PORT_UNUSED",
+-		port_phaseupdown => "PORT_UNUSED",
+-		port_pllena => "PORT_UNUSED",
+-		port_scanaclr => "PORT_UNUSED",
+-		port_scanclk => "PORT_UNUSED",
+-		port_scanclkena => "PORT_UNUSED",
+-		port_scandata => "PORT_UNUSED",
+-		port_scandataout => "PORT_UNUSED",
+-		port_scandone => "PORT_UNUSED",
+-		port_scanread => "PORT_UNUSED",
+-		port_scanwrite => "PORT_UNUSED",
+-		port_clk0 => "PORT_USED",
+-		port_clk1 => "PORT_USED",
+-		port_clk2 => "PORT_USED",
+-		port_clk3 => "PORT_UNUSED",
+-		port_clk4 => "PORT_UNUSED",
+-		port_clk5 => "PORT_UNUSED",
+-		port_clkena0 => "PORT_UNUSED",
+-		port_clkena1 => "PORT_UNUSED",
+-		port_clkena2 => "PORT_UNUSED",
+-		port_clkena3 => "PORT_UNUSED",
+-		port_clkena4 => "PORT_UNUSED",
+-		port_clkena5 => "PORT_UNUSED",
+-		port_extclk0 => "PORT_UNUSED",
+-		port_extclk1 => "PORT_UNUSED",
+-		port_extclk2 => "PORT_UNUSED",
+-		port_extclk3 => "PORT_UNUSED",
+-		valid_lock_multiplier => 1
+-	)
+-	PORT MAP (
+-		inclk => sub_wire6,
+-		clk => sub_wire0,
+-		locked => sub_wire2
+-	);
+-
+-
+-
+-END SYN;
+-
+--- ============================================================
+--- CNX file retrieval info
+--- ============================================================
+--- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+--- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+--- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+--- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+--- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+--- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+--- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+--- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+--- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+--- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+--- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+--- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+--- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+--- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+--- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+--- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+--- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+--- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+--- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+--- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+--- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+--- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+--- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+--- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+--- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+--- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+--- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+--- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+--- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+--- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+--- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+--- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+--- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "23"
+--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "23"
+--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23"
+--- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+--- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+--- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+--- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+--- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+--- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+--- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+--- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+--- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+--- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+--- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+--- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+--- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+--- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+--- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+--- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+--- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+--- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+--- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+--- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+--- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+--- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+--- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+--- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+--- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+--- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+--- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+--- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+--- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+--- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
+--- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+--- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20"
+--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
+--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+--- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+--- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+--- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+--- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+--- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+--- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+--- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+--- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+--- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+--- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+--- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+--- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+--- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+--- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+--- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+--- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+--- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+--- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+--- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+--- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+--- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+--- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+--- Retrieval info: LIB_FILE: altera_mf
+--- Retrieval info: CBX_MODULE_PREFIX: ON
++-- megafunction wizard: %ALTPLL%
++-- GENERATION: STANDARD
++-- VERSION: WM1.0
++-- MODULE: altpll 
++
++-- ============================================================
++-- File Name: pll.vhd
++-- Megafunction Name(s):
++-- 			altpll
++--
++-- Simulation Library Files(s):
++-- 			altera_mf
++-- ============================================================
++-- ************************************************************
++-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
++--
++-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
++-- ************************************************************
++
++
++--Copyright (C) 1991-2012 Altera Corporation
++--Your use of Altera Corporation's design tools, logic functions 
++--and other software and tools, and its AMPP partner logic 
++--functions, and any output files from any of the foregoing 
++--(including device programming or simulation files), and any 
++--associated documentation or information are expressly subject 
++--to the terms and conditions of the Altera Program License 
++--Subscription Agreement, Altera MegaCore Function License 
++--Agreement, or other applicable license agreement, including, 
++--without limitation, that your use is for the sole purpose of 
++--programming logic devices manufactured by Altera and sold by 
++--Altera or its authorized distributors.  Please refer to the 
++--applicable agreement for further details.
++
++
++LIBRARY ieee;
++USE ieee.std_logic_1164.all;
++
++LIBRARY altera_mf;
++USE altera_mf.all;
++
++ENTITY pll IS
++	PORT
++	(
++		inclk0		: IN STD_LOGIC  := '0';
++		c0		: OUT STD_LOGIC ;
++		c1		: OUT STD_LOGIC ;
++		c2		: OUT STD_LOGIC ;
++		locked		: OUT STD_LOGIC 
++	);
++END pll;
++
++
++ARCHITECTURE SYN OF pll IS
++
++	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
++	SIGNAL sub_wire1	: STD_LOGIC ;
++	SIGNAL sub_wire2	: STD_LOGIC ;
++	SIGNAL sub_wire3	: STD_LOGIC ;
++	SIGNAL sub_wire4	: STD_LOGIC ;
++	SIGNAL sub_wire5	: STD_LOGIC ;
++	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
++	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
++	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
++
++
++
++	COMPONENT altpll
++	GENERIC (
++		bandwidth_type		: STRING;
++		clk0_divide_by		: NATURAL;
++		clk0_duty_cycle		: NATURAL;
++		clk0_multiply_by		: NATURAL;
++		clk0_phase_shift		: STRING;
++		clk1_divide_by		: NATURAL;
++		clk1_duty_cycle		: NATURAL;
++		clk1_multiply_by		: NATURAL;
++		clk1_phase_shift		: STRING;
++		clk2_divide_by		: NATURAL;
++		clk2_duty_cycle		: NATURAL;
++		clk2_multiply_by		: NATURAL;
++		clk2_phase_shift		: STRING;
++		compensate_clock		: STRING;
++		inclk0_input_frequency		: NATURAL;
++		intended_device_family		: STRING;
++		lpm_hint		: STRING;
++		lpm_type		: STRING;
++		operation_mode		: STRING;
++		pll_type		: STRING;
++		port_activeclock		: STRING;
++		port_areset		: STRING;
++		port_clkbad0		: STRING;
++		port_clkbad1		: STRING;
++		port_clkloss		: STRING;
++		port_clkswitch		: STRING;
++		port_configupdate		: STRING;
++		port_fbin		: STRING;
++		port_inclk0		: STRING;
++		port_inclk1		: STRING;
++		port_locked		: STRING;
++		port_pfdena		: STRING;
++		port_phasecounterselect		: STRING;
++		port_phasedone		: STRING;
++		port_phasestep		: STRING;
++		port_phaseupdown		: STRING;
++		port_pllena		: STRING;
++		port_scanaclr		: STRING;
++		port_scanclk		: STRING;
++		port_scanclkena		: STRING;
++		port_scandata		: STRING;
++		port_scandataout		: STRING;
++		port_scandone		: STRING;
++		port_scanread		: STRING;
++		port_scanwrite		: STRING;
++		port_clk0		: STRING;
++		port_clk1		: STRING;
++		port_clk2		: STRING;
++		port_clk3		: STRING;
++		port_clk4		: STRING;
++		port_clk5		: STRING;
++		port_clkena0		: STRING;
++		port_clkena1		: STRING;
++		port_clkena2		: STRING;
++		port_clkena3		: STRING;
++		port_clkena4		: STRING;
++		port_clkena5		: STRING;
++		port_extclk0		: STRING;
++		port_extclk1		: STRING;
++		port_extclk2		: STRING;
++		port_extclk3		: STRING;
++		self_reset_on_loss_lock		: STRING;
++		width_clock		: NATURAL
++	);
++	PORT (
++			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
++			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
++			locked	: OUT STD_LOGIC 
++	);
++	END COMPONENT;
++
++BEGIN
++	sub_wire7_bv(0 DOWNTO 0) <= "0";
++	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
++	sub_wire4    <= sub_wire0(2);
++	sub_wire3    <= sub_wire0(0);
++	sub_wire1    <= sub_wire0(1);
++	c1    <= sub_wire1;
++	locked    <= sub_wire2;
++	c0    <= sub_wire3;
++	c2    <= sub_wire4;
++	sub_wire5    <= inclk0;
++	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
++
++	altpll_component : altpll
++	GENERIC MAP (
++		bandwidth_type => "AUTO",
++		clk0_divide_by => 2,
++		clk0_duty_cycle => 50,
++		clk0_multiply_by => 23,
++		clk0_phase_shift => "0",
++		clk1_divide_by => 2,
++		clk1_duty_cycle => 50,
++		clk1_multiply_by => 23,
++		clk1_phase_shift => "0",
++		clk2_divide_by => 2,
++		clk2_duty_cycle => 50,
++		clk2_multiply_by => 23,
++		clk2_phase_shift => "0",
++		compensate_clock => "CLK0",
++		inclk0_input_frequency => 200000,
++		intended_device_family => "Cyclone III",
++		lpm_hint => "CBX_MODULE_PREFIX=pll",
++		lpm_type => "altpll",
++		operation_mode => "NORMAL",
++		pll_type => "AUTO",
++		port_activeclock => "PORT_UNUSED",
++		port_areset => "PORT_UNUSED",
++		port_clkbad0 => "PORT_UNUSED",
++		port_clkbad1 => "PORT_UNUSED",
++		port_clkloss => "PORT_UNUSED",
++		port_clkswitch => "PORT_UNUSED",
++		port_configupdate => "PORT_UNUSED",
++		port_fbin => "PORT_UNUSED",
++		port_inclk0 => "PORT_USED",
++		port_inclk1 => "PORT_UNUSED",
++		port_locked => "PORT_USED",
++		port_pfdena => "PORT_UNUSED",
++		port_phasecounterselect => "PORT_UNUSED",
++		port_phasedone => "PORT_UNUSED",
++		port_phasestep => "PORT_UNUSED",
++		port_phaseupdown => "PORT_UNUSED",
++		port_pllena => "PORT_UNUSED",
++		port_scanaclr => "PORT_UNUSED",
++		port_scanclk => "PORT_UNUSED",
++		port_scanclkena => "PORT_UNUSED",
++		port_scandata => "PORT_UNUSED",
++		port_scandataout => "PORT_UNUSED",
++		port_scandone => "PORT_UNUSED",
++		port_scanread => "PORT_UNUSED",
++		port_scanwrite => "PORT_UNUSED",
++		port_clk0 => "PORT_USED",
++		port_clk1 => "PORT_USED",
++		port_clk2 => "PORT_USED",
++		port_clk3 => "PORT_UNUSED",
++		port_clk4 => "PORT_UNUSED",
++		port_clk5 => "PORT_UNUSED",
++		port_clkena0 => "PORT_UNUSED",
++		port_clkena1 => "PORT_UNUSED",
++		port_clkena2 => "PORT_UNUSED",
++		port_clkena3 => "PORT_UNUSED",
++		port_clkena4 => "PORT_UNUSED",
++		port_clkena5 => "PORT_UNUSED",
++		port_extclk0 => "PORT_UNUSED",
++		port_extclk1 => "PORT_UNUSED",
++		port_extclk2 => "PORT_UNUSED",
++		port_extclk3 => "PORT_UNUSED",
++		self_reset_on_loss_lock => "OFF",
++		width_clock => 5
++	)
++	PORT MAP (
++		inclk => sub_wire6,
++		clk => sub_wire0,
++		locked => sub_wire2
++	);
++
++
++
++END SYN;
++
++-- ============================================================
++-- CNX file retrieval info
++-- ============================================================
++-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
++-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
++-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
++-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
++-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
++-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
++-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
++-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
++-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
++-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
++-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
++-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
++-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
++-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
++-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
++-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
++-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
++-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
++-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
++-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
++-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
++-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
++-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000"
++-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
++-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000"
++-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
++-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
++-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
++-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
++-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
++-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
++-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
++-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
++-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
++-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
++-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
++-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
++-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
++-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
++-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
++-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
++-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
++-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
++-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
++-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
++-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
++-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
++-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
++-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
++-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
++-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
++-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
++-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
++-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
++-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
++-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
++-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
++-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
++-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
++-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
++-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
++-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
++-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
++-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
++-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
++-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
++-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
++-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
++-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
++-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
++-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
++-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
++-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
++-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
++-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
++-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
++-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
++-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
++-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
++-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
++-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
++-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
++-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
++-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
++-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
++-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
++-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
++-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
++-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
++-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
++-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
++-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
++-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
++-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
++-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
++-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
++-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
++-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
++-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
++-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
++-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
++-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
++-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
++-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
++-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
++-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
++-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
++-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
++-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
++-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
++-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
++-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
++-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
++-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
++-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
++-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
++-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
++-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
++-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
++-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
++-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
++-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
++-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
++-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
++-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
++-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
++-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
++-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
++-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
++-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
++-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
++-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
++-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
++-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
++-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
++-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
++-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
++-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
++-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
++-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
++-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
++-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
++-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
++-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
++-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
++-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
++-- Retrieval info: LIB_FILE: altera_mf
++-- Retrieval info: CBX_MODULE_PREFIX: ON
+Only in atari800core_v1_20140121_mcc216: pll.vhd.bak
+diff -ur atari800core_20140301_de1/pokey_ps2_decoder.vhdl atari800core_v1_20140121_mcc216/pokey_ps2_decoder.vhdl
+--- atari800core_20140301_de1/pokey_ps2_decoder.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140121_mcc216/pokey_ps2_decoder.vhdl	2014-01-26 19:29:53.000000000 +0000
+@@ -37,7 +37,9 @@
+ 	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+ 	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+ 	
+-	SYSTEM_RESET : out std_logic
++	SYSTEM_RESET : out std_logic;
++	
++	VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+ );
+ END pokey_ps2_decoder;
+ 
+@@ -84,6 +86,9 @@
+ 	
+ 	signal system_reset_next : std_logic;
+ 	signal system_reset_reg : std_logic;	
++
++	signal virtual_keys_next : std_logic_vector(3 downto 0);
++	signal virtual_keys_reg : std_logic_vector(3 downto 0);	
+ 	
+ 	signal no_kbcode_update : std_logic;
+ BEGIN
+@@ -116,6 +121,8 @@
+ 			virtual_stick_pressed_reg <= '0';
+ 			
+ 			system_reset_reg <= '0';
++			
++			virtual_keys_reg <= (others=>'0');
+ 		elsif (clk'event and clk='1') then
+ 			left_shift_pressed_reg <= left_shift_pressed_next;
+ 			right_shift_pressed_reg <= right_shift_pressed_next;
+@@ -142,11 +149,12 @@
+ 			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+ 			
+ 			system_reset_reg <= system_reset_next;
++			virtual_keys_reg <= virtual_keys_next;
+ 		end if;
+ 	end process;
+ 	
+ 	-- update key pressed
+-	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg)
++	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg, virtual_keys_reg)
+ 	begin
+ 		left_shift_pressed_next <= left_shift_pressed_reg;
+ 		right_shift_pressed_next <= right_shift_pressed_reg;
+@@ -170,6 +178,7 @@
+ 		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+ 		
+ 		system_reset_next <= system_reset_reg;
++		virtual_keys_next <= virtual_keys_reg;
+ 		
+ 		key_held_next <= key_held_reg;
+ 		
+@@ -377,7 +386,31 @@
+ 					no_kbcode_update <= '1';
+ 					virtual_stick_pressed_next <= not(key_UP);
+ 					interrupt_next <= '0';	
+-					key_held_next <= '0';					
++					key_held_next <= '0';	
++					
++				when '0'&X"0a" => -- f8 => system reset
++					no_kbcode_update <= '1';
++					virtual_keys_next(0) <= not(key_UP);
++					interrupt_next <= '0';	
++					key_held_next <= '0';	
++					
++				when '0'&X"01" => -- f9 => system reset
++					no_kbcode_update <= '1';
++					virtual_keys_next(1) <= not(key_UP);
++					interrupt_next <= '0';	
++					key_held_next <= '0';						
++					
++				when '0'&X"09" => -- f10 => system reset
++					no_kbcode_update <= '1';
++					virtual_keys_next(2) <= not(key_UP);
++					interrupt_next <= '0';	
++					key_held_next <= '0';						
++					
++				when '0'&X"78" => -- f11 => system reset
++					no_kbcode_update <= '1';
++					virtual_keys_next(3) <= not(key_UP);
++					interrupt_next <= '0';	
++					key_held_next <= '0';	
+ 					
+ 				when '0'&X"07" => -- f12 => system reset
+ 					no_kbcode_update <= '1';
+@@ -430,5 +463,6 @@
+ 	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+ 	
+ 	system_reset <= system_reset_reg;
++	virtual_keys <= virtual_keys_reg;
+ 		
+ END vhdl;
+\ No newline at end of file
+Only in atari800core_v1_20140121_mcc216: pokey_ps2_decoder.vhdl.bak
+Only in atari800core_v1_20140121_mcc216: ramint.bsf
+Only in atari800core_v1_20140121_mcc216: ramint.cmp
+Only in atari800core_v1_20140121_mcc216: ramint.qip
+Only in atari800core_v1_20140121_mcc216: ramint.vhd
+Only in atari800core_v1_20140121_mcc216: romhi.bsf
+Only in atari800core_v1_20140121_mcc216: romhi.cmp
+Only in atari800core_v1_20140121_mcc216: romhi.qip
+Only in atari800core_v1_20140121_mcc216: romhi.vhd
+Only in atari800core_v1_20140121_mcc216: romlo.bsf
+Only in atari800core_v1_20140121_mcc216: romlo.cmp
+Only in atari800core_v1_20140121_mcc216: romlo.qip
+Only in atari800core_v1_20140121_mcc216: romlo.vhd
+Only in atari800core_v1_20140121_mcc216: sdram_ctrl_4_ports.v
+Only in atari800core_v1_20140121_mcc216: sdram_ctrl_4_ports.v.bak
+Only in atari800core_v1_20140121_mcc216: sdram_statemachine_mcc.vhdl
+Only in atari800core_v1_20140121_mcc216: sdram_statemachine_mcc.vhdl.bak
+diff -ur atari800core_20140301_de1/sdram_statemachine.vhdl atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl
+--- atari800core_20140301_de1/sdram_statemachine.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl	2014-01-22 21:37:54.000000000 +0000
+@@ -204,8 +204,8 @@
+ 			ras_n_reg <= '0';
+ 			cas_n_reg <= '0';
+ 			we_n_reg <= '0';
+-			ldqm_reg <= '1';
+-			udqm_reg <= '1';
++			ldqm_reg <= '0';
++			udqm_reg <= '0';
+ 			cke_reg <= '0';
+ 			
+ 			--bank_row_reg <= (others=>(others=>'0'));
+Only in atari800core_v1_20140121_mcc216: sdram_statemachine.vhdl.bak
+diff -ur atari800core_20140301_de1/zpu/HelloTinyROM_ROM.mif atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif
+--- atari800core_20140301_de1/zpu/HelloTinyROM_ROM.mif	2014-01-20 21:22:00.000000000 +0000
++++ atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif	2014-01-31 21:09:40.000000000 +0000
+@@ -170,7 +170,7 @@
+ 009f : 00000000;
+ 00a0 : 71fc0608;
+ 00a1 : 0b0b80f5;
+-00a2 : 98738306;
++00a2 : d0738306;
+ 00a3 : 10100508;
+ 00a4 : 060b0b0b;
+ 00a5 : 88a20400;
+@@ -216,8 +216,8 @@
+ 00cd : 00000000;
+ 00ce : 00000000;
+ 00cf : 00000000;
+-00d0 : 810b80fa;
+-00d1 : ec0c5104;
++00d0 : 810b80fb;
++00d1 : ac0c5104;
+ 00d2 : 00000000;
+ 00d3 : 00000000;
+ 00d4 : 00000000;
+@@ -290,7 +290,7 @@
+ 0117 : 83e08408;
+ 0118 : 83e08808;
+ 0119 : 757580ef;
+-011a : c72d5050;
++011a : fe2d5050;
+ 011b : 83e08008;
+ 011c : 5683e088;
+ 011d : 0c83e084;
+@@ -299,7 +299,7 @@
+ 0120 : e0800883;
+ 0121 : e0840883;
+ 0122 : e0880875;
+-0123 : 7580eddb;
++0123 : 7580ee92;
+ 0124 : 2d505083;
+ 0125 : e0800856;
+ 0126 : 83e0880c;
+@@ -308,11 +308,11 @@
+ 0129 : 51040000;
+ 012a : 800489aa;
+ 012b : 0489aa0b;
+-012c : 80c0b404;
++012c : 80c1a404;
+ 012d : fd3d0d75;
+ 012e : b9297681;
+ 012f : 2a0580fd;
+-0130 : bc085473;
++0130 : fc085473;
+ 0131 : 0c853d0d;
+ 0132 : 04803d0d;
+ 0133 : 81ff5180;
+@@ -321,10 +321,10 @@
+ 0136 : 5170f438;
+ 0137 : 823d0d04;
+ 0138 : fa3d0d78;
+-0139 : 0b0b80f5;
+-013a : f05383e2;
++0139 : 0b0b80f6;
++013a : a85383e2;
+ 013b : f4525680;
+-013c : cd9a3f80;
++013c : cdd13f80;
+ 013d : 5383e080;
+ 013e : 08732e8a;
+ 013f : 387283e0;
+@@ -332,7 +332,7 @@
+ 0141 : 0d0483e0;
+ 0142 : 945283e2;
+ 0143 : f45180ce;
+-0144 : 8e3f83e0;
++0144 : c53f83e0;
+ 0145 : 800880d5;
+ 0146 : 3883e09d;
+ 0147 : 33537280;
+@@ -362,9 +362,9 @@
+ 015f : e0800c88;
+ 0160 : 3d0d04fd;
+ 0161 : 3d0d800b;
+-0162 : 80fdac08;
++0162 : 80fdec08;
+ 0163 : 5353ff72;
+-0164 : 0c80fdb0;
++0164 : 0c80fdf0;
+ 0165 : 0873710c;
+ 0166 : 5284d851;
+ 0167 : fe963f88;
+@@ -373,10 +373,10 @@
+ 016a : 553472a8;
+ 016b : 800a2e09;
+ 016c : 8106f038;
+-016d : 80fdac08;
++016d : 80fdec08;
+ 016e : 5485aad5;
+ 016f : aad5740c;
+-0170 : 80fdb008;
++0170 : 80fdf008;
+ 0171 : 5285aad5;
+ 0172 : aad5720c;
+ 0173 : 82800a53;
+@@ -390,10 +390,10 @@
+ 017b : 3f853d0d;
+ 017c : 04fd3d0d;
+ 017d : 800b80fd;
+-017e : ac085353;
++017e : ec085353;
+ 017f : ff87c3e1;
+ 0180 : f0720c80;
+-0181 : fdb00873;
++0181 : fdf00873;
+ 0182 : 710c528c;
+ 0183 : 9ac051fd;
+ 0184 : a33f8880;
+@@ -402,10 +402,10 @@
+ 0187 : 34728184;
+ 0188 : 80802e09;
+ 0189 : 8106ef38;
+-018a : 80fdac08;
++018a : 80fdec08;
+ 018b : 5485aad5;
+ 018c : aad5740c;
+-018d : 80fdb008;
++018d : 80fdf008;
+ 018e : 5285aad5;
+ 018f : aad5720c;
+ 0190 : 82800a53;
+@@ -419,8 +419,8 @@
+ 0198 : 8c9ac051;
+ 0199 : fcce3f85;
+ 019a : 3d0d04ff;
+-019b : 3d0d80fd;
+-019c : c0087008;
++019b : 3d0d80fe;
++019c : 80087008;
+ 019d : 52527381;
+ 019e : 2e8b3870;
+ 019f : 81800772;
+@@ -428,8 +428,8 @@
+ 01a1 : 0470feff;
+ 01a2 : 06720c83;
+ 01a3 : 3d0d04ff;
+-01a4 : 3d0d80fd;
+-01a5 : c0087008;
++01a4 : 3d0d80fe;
++01a5 : 80087008;
+ 01a6 : 5252738b;
+ 01a7 : 3870ffbf;
+ 01a8 : 06720c83;
+@@ -438,10 +438,10 @@
+ 01ab : 0c833d0d;
+ 01ac : 04ff0b83;
+ 01ad : e0b00c80;
+-01ae : ceac3f80;
+-01af : d1b03f83;
++01ae : cee33f80;
++01af : d1e73f83;
+ 01b0 : e08008f3;
+-01b1 : 3880d3f5;
++01b1 : 3880d4ac;
+ 01b2 : 3f800b83;
+ 01b3 : e0800c04;
+ 01b4 : 803d0d70;
+@@ -476,22 +476,22 @@
+ 01d1 : 3d238070;
+ 01d2 : 7183e2e4;
+ 01d3 : 0c0b0b80;
+-01d4 : f5f45357;
+-01d5 : 5880da88;
++01d4 : f6ac5357;
++01d5 : 5880dabf;
+ 01d6 : 3f765180;
+-01d7 : da823f0b;
+-01d8 : 0b80fab4;
+-01d9 : 5180d9f8;
++01d7 : dab93f0b;
++01d8 : 0b80faf4;
++01d9 : 5180daaf;
+ 01da : 3f765180;
+-01db : c2ba3f83;
++01db : c2f13f83;
+ 01dc : e0800878;
+ 01dd : 2e8f380b;
+-01de : 0b80f680;
+-01df : 5180d9e0;
++01de : 0b80f6b8;
++01df : 5180da97;
+ 01e0 : 3f8a3d0d;
+ 01e1 : 040b0b80;
+-01e2 : f6885180;
+-01e3 : d9d23f75;
++01e2 : f6c05180;
++01e3 : da893f75;
+ 01e4 : 17703355;
+ 01e5 : 5573802e;
+ 01e6 : 80fd3873;
+@@ -530,12 +530,12 @@
+ 0207 : 8a3dfc05;
+ 0208 : 53905283;
+ 0209 : e2e85180;
+-020a : c2be3f89;
++020a : c2f53f89;
+ 020b : 3d225574;
+ 020c : 902e8e38;
+ 020d : 0b0b80f6;
+-020e : 8c5180d8;
+-020f : a33ffec1;
++020e : c45180d8;
++020f : da3ffec1;
+ 0210 : 3983e2e8;
+ 0211 : 51fd953f;
+ 0212 : 83e2ea51;
+@@ -552,11 +552,11 @@
+ 021d : 2e82ce38;
+ 021e : 7385962e;
+ 021f : 8e380b0b;
+-0220 : 80f6a451;
+-0221 : 80d7d93f;
++0220 : 80f6dc51;
++0221 : 80d8903f;
+ 0222 : fdf7390b;
+-0223 : 0b80f6b8;
+-0224 : 5180d7cc;
++0223 : 0b80f6f0;
++0224 : 5180d883;
+ 0225 : 3f7483e3;
+ 0226 : 900c83e2;
+ 0227 : ec3383e2;
+@@ -568,20 +568,20 @@
+ 022d : 81387381;
+ 022e : ff2681b8;
+ 022f : 380b0b80;
+-0230 : f6c05180;
+-0231 : d79a3f83;
++0230 : f6f85180;
++0231 : d7d13f83;
+ 0232 : e2ea3383;
+ 0233 : e2eb3371;
+ 0234 : 882b0752;
+-0235 : 5680d897;
++0235 : 5680d8ce;
+ 0236 : 3f0b0b80;
+-0237 : f6c45180;
+-0238 : d6fe3f81;
++0237 : f6fc5180;
++0238 : d7b53f81;
+ 0239 : 0b83e2e4;
+ 023a : 0c8a3d0d;
+ 023b : 040b0b80;
+-023c : f6c85180;
+-023d : d6ea3f80;
++023c : f7805180;
++023d : d7a13f80;
+ 023e : 0b83e390;
+ 023f : 0c820b83;
+ 0240 : e2e834ff;
+@@ -613,29 +613,29 @@
+ 025a : ec34ff80;
+ 025b : 0b83e2ed;
+ 025c : 34fea739;
+-025d : 0b0b80f6;
+-025e : d05180d5;
+-025f : e33ffc81;
++025d : 0b0b80f7;
++025e : 885180d6;
++025f : 9a3ffc81;
+ 0260 : 3983e2ea;
+ 0261 : 3383e2eb;
+ 0262 : 3371882b;
+ 0263 : 075558ad;
+ 0264 : 80742781;
+ 0265 : f2380b0b;
+-0266 : 80f6e051;
+-0267 : 80d5c13f;
++0266 : 80f79851;
++0267 : 80d5f83f;
+ 0268 : 83e2ea33;
+ 0269 : 83e2eb33;
+ 026a : 71882b07;
+ 026b : 525680d6;
+-026c : be3f0b0b;
+-026d : 80f6c451;
+-026e : 80d5a53f;
++026c : f53f0b0b;
++026d : 80f6fc51;
++026e : 80d5dc3f;
+ 026f : 810b83e2;
+ 0270 : e40cfea5;
+ 0271 : 390b0b80;
+-0272 : f6e45180;
+-0273 : d5923ffe;
++0272 : f79c5180;
++0273 : d5c93ffe;
+ 0274 : 800b83e3;
+ 0275 : 900c810b;
+ 0276 : 83e3880c;
+@@ -682,43 +682,43 @@
+ 029f : 800b83e2;
+ 02a0 : ed348055;
+ 02a1 : ffa5390b;
+-02a2 : 0b80f6ec;
+-02a3 : 5180d3d0;
++02a2 : 0b80f7a4;
++02a3 : 5180d487;
+ 02a4 : 3f83e2ea;
+ 02a5 : 3383e2eb;
+ 02a6 : 3371882b;
+ 02a7 : 07525680;
+-02a8 : d4cd3f0b;
+-02a9 : 0b80f6c4;
+-02aa : 5180d3b4;
++02a8 : d5843f0b;
++02a9 : 0b80f6fc;
++02aa : 5180d3eb;
+ 02ab : 3f810b83;
+ 02ac : e2e40cfc;
+ 02ad : b4390b0b;
+-02ae : 80f6f051;
+-02af : 80d3a13f;
++02ae : 80f7a851;
++02af : 80d3d83f;
+ 02b0 : 83e2ea33;
+ 02b1 : 83e2eb33;
+ 02b2 : 71882b07;
+ 02b3 : 525680d4;
+-02b4 : 9e3f0b0b;
+-02b5 : 80f6c451;
+-02b6 : 80d3853f;
++02b4 : d53f0b0b;
++02b5 : 80f6fc51;
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+ 02bb : c051f3c4;
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+ 02be : 54800b86;
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++02c6 : aa3f83e0;
+ 02c7 : 800883db;
+ 02c8 : 38807083;
+ 02c9 : e3a80855;
+@@ -728,8 +728,8 @@
+ 02cd : 80732482;
+ 02ce : ff3883e0;
+ 02cf : 945283e2;
+-02d0 : f45180c1;
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++02d1 : 913f83e0;
+ 02d2 : 800880db;
+ 02d3 : 3883e09d;
+ 02d4 : 33537280;
+@@ -751,17 +751,17 @@
+ 02e4 : 175783e0;
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+ 02e6 : f45180c1;
+-02e7 : 823f83e0;
++02e7 : b93f83e0;
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++02ed : cfcb3f80;
+ 02ee : 0b83e0b4;
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++02f0 : fb3f80fd;
++02f1 : 80087033;
+ 02f2 : 7081ff06;
+ 02f3 : 70812a81;
+ 02f4 : 32708106;
+@@ -777,17 +777,17 @@
+ 02fe : 822a8132;
+ 02ff : 70810651;
+ 0300 : 537282a3;
+-0301 : 3880fcb8;
++0301 : 3880fcf8;
+ 0302 : 08703370;
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++030a : 733480fd;
++030b : 80087033;
+ 030c : 7081ff06;
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+ 030e : 32708106;
+@@ -798,8 +798,8 @@
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+ 0315 : 51f0dd3f;
+-0316 : 805780cd;
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++0316 : 805780ce;
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+@@ -816,8 +816,8 @@
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+@@ -825,22 +825,22 @@
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++033f : 0b80f7b4;
++0340 : 5180cf93;
+ 0341 : 3fff3973;
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+@@ -864,7 +864,7 @@
+ 0355 : f18051fd;
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+ 0357 : 0d800b80;
+-0358 : fdb40870;
++0358 : fdf40870;
+ 0359 : 08708106;
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+@@ -880,13 +880,13 @@
+ 0365 : 8051f1d3;
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+ 0367 : ce3f80fd;
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+@@ -894,60 +894,60 @@
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++03ab : da3f84df;
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+@@ -961,7 +961,7 @@
+ 03b6 : 88802e09;
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+-03b9 : 819c8080;
++03b9 : 84dc8080;
+ 03ba : 18888080;
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+@@ -971,7 +971,7 @@
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+@@ -981,7 +981,7 @@
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+-03cd : 819c8080;
++03cd : 84dc8080;
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+@@ -990,59 +990,59 @@
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+@@ -1054,25 +1054,25 @@
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+@@ -1080,17 +1080,17 @@
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+@@ -1098,49 +1098,49 @@
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+@@ -1149,24 +1149,24 @@
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+@@ -1179,10 +1179,10 @@
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+@@ -1190,13 +1190,13 @@
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+@@ -1204,7 +1204,7 @@
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+@@ -1212,7 +1212,7 @@
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+@@ -1220,57 +1220,57 @@
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+@@ -1278,16 +1278,16 @@
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++0e02 : 3d0d800b;
++0e03 : 83e08c08;
++0e04 : fc050c83;
++0e05 : e08c0888;
++0e06 : 05088025;
++0e07 : 993883e0;
++0e08 : 8c088805;
++0e09 : 083083e0;
++0e0a : 8c088805;
++0e0b : 0c810b83;
++0e0c : e08c08fc;
++0e0d : 050c83e0;
++0e0e : 8c088c05;
++0e0f : 08802590;
++0e10 : 3883e08c;
++0e11 : 088c0508;
++0e12 : 3083e08c;
++0e13 : 088c050c;
++0e14 : 815383e0;
++0e15 : 8c088c05;
++0e16 : 085283e0;
++0e17 : 8c088805;
++0e18 : 0851bd3f;
++0e19 : 83e08008;
++0e1a : 7083e08c;
++0e1b : 08f8050c;
++0e1c : 5483e08c;
++0e1d : 08fc0508;
++0e1e : 802e9038;
++0e1f : 83e08c08;
++0e20 : f8050830;
++0e21 : 83e08c08;
++0e22 : f8050c83;
++0e23 : e08c08f8;
++0e24 : 05087083;
++0e25 : e0800c54;
++0e26 : 873d0d83;
++0e27 : e08c0c04;
++0e28 : 83e08c08;
++0e29 : 0283e08c;
++0e2a : 0cfd3d0d;
++0e2b : 810b83e0;
++0e2c : 8c08fc05;
++0e2d : 0c800b83;
++0e2e : e08c08f8;
+ 0e2f : 050c83e0;
+-0e30 : 8c08fc05;
+-0e31 : 081083e0;
+-0e32 : 8c08fc05;
+-0e33 : 0cffb839;
+-0e34 : 83e08c08;
+-0e35 : fc050880;
+-0e36 : 2e80e138;
++0e30 : 8c088c05;
++0e31 : 0883e08c;
++0e32 : 08880508;
++0e33 : 27b93883;
++0e34 : e08c08fc;
++0e35 : 0508802e;
++0e36 : ae38800b;
+ 0e37 : 83e08c08;
+-0e38 : 8c050883;
+-0e39 : e08c0888;
+-0e3a : 050826ad;
+-0e3b : 3883e08c;
+-0e3c : 08880508;
+-0e3d : 83e08c08;
+-0e3e : 8c050831;
+-0e3f : 83e08c08;
+-0e40 : 88050c83;
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+-0e42 : 050883e0;
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+-0e44 : 080783e0;
+-0e45 : 8c08f805;
+-0e46 : 0c83e08c;
+-0e47 : 08fc0508;
+-0e48 : 812a83e0;
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+-0e4a : 0c83e08c;
+-0e4b : 088c0508;
+-0e4c : 812a83e0;
+-0e4d : 8c088c05;
+-0e4e : 0cff9539;
+-0e4f : 83e08c08;
+-0e50 : 90050880;
+-0e51 : 2e933883;
+-0e52 : e08c0888;
+-0e53 : 05087083;
+-0e54 : e08c08f4;
+-0e55 : 050c5191;
+-0e56 : 3983e08c;
+-0e57 : 08f80508;
+-0e58 : 7083e08c;
+-0e59 : 08f4050c;
+-0e5a : 5183e08c;
+-0e5b : 08f40508;
+-0e5c : 83e0800c;
+-0e5d : 853d0d83;
+-0e5e : e08c0c04;
+-0e5f : 83e08c08;
+-0e60 : 0283e08c;
+-0e61 : 0cff3d0d;
+-0e62 : 800b83e0;
+-0e63 : 8c08fc05;
+-0e64 : 0c83e08c;
+-0e65 : 08880508;
+-0e66 : 8106ff11;
+-0e67 : 70097083;
+-0e68 : e08c088c;
+-0e69 : 05080683;
+-0e6a : e08c08fc;
+-0e6b : 05081183;
+-0e6c : e08c08fc;
+-0e6d : 050c83e0;
+-0e6e : 8c088805;
+-0e6f : 08812a83;
+-0e70 : e08c0888;
+-0e71 : 050c83e0;
+-0e72 : 8c088c05;
+-0e73 : 081083e0;
+-0e74 : 8c088c05;
+-0e75 : 0c515151;
+-0e76 : 5183e08c;
+-0e77 : 08880508;
+-0e78 : 802e8438;
+-0e79 : ffab3983;
+-0e7a : e08c08fc;
+-0e7b : 05087083;
+-0e7c : e0800c51;
+-0e7d : 833d0d83;
+-0e7e : e08c0c04;
+-0e7f : fc3d0d76;
+-0e80 : 70797b55;
+-0e81 : 5555558f;
+-0e82 : 72278c38;
+-0e83 : 72750783;
+-0e84 : 06517080;
+-0e85 : 2ea938ff;
+-0e86 : 125271ff;
+-0e87 : 2e983872;
+-0e88 : 70810554;
+-0e89 : 33747081;
+-0e8a : 055634ff;
+-0e8b : 125271ff;
+-0e8c : 2e098106;
+-0e8d : ea387483;
+-0e8e : e0800c86;
+-0e8f : 3d0d0474;
+-0e90 : 51727084;
+-0e91 : 05540871;
+-0e92 : 70840553;
+-0e93 : 0c727084;
+-0e94 : 05540871;
+-0e95 : 70840553;
+-0e96 : 0c727084;
+-0e97 : 05540871;
+-0e98 : 70840553;
+-0e99 : 0c727084;
+-0e9a : 05540871;
+-0e9b : 70840553;
+-0e9c : 0cf01252;
+-0e9d : 718f26c9;
+-0e9e : 38837227;
+-0e9f : 95387270;
+-0ea0 : 84055408;
+-0ea1 : 71708405;
+-0ea2 : 530cfc12;
+-0ea3 : 52718326;
+-0ea4 : ed387054;
+-0ea5 : ff813900;
+-0ea6 : 00ffffff;
+-0ea7 : ff00ffff;
+-0ea8 : ffff00ff;
+-0ea9 : ffffff00;
+-0eaa : 70707042;
+-0eab : 409c0202;
+-0eac : 02020202;
+-0ead : 02020202;
+-0eae : 02020202;
+-0eaf : 02020202;
+-0eb0 : 02020202;
+-0eb1 : 02704100;
+-0eb2 : 06000000;
+-0eb3 : 70707042;
+-0eb4 : 409c0202;
+-0eb5 : 02020202;
+-0eb6 : 02020202;
+-0eb7 : 02020202;
+-0eb8 : 02020202;
+-0eb9 : 02020202;
+-0eba : 02704100;
+-0ebb : 9c000000;
+-0ebc : 2f000000;
+-0ebd : 4f70656e;
+-0ebe : 696e673a;
+-0ebf : 00000000;
+-0ec0 : 6661696c;
+-0ec1 : 0a000000;
+-0ec2 : 6f6b0a00;
+-0ec3 : 436f756c;
+-0ec4 : 64206e6f;
+-0ec5 : 74207265;
+-0ec6 : 61642068;
+-0ec7 : 65616465;
+-0ec8 : 720a0000;
+-0ec9 : 556e6b6e;
+-0eca : 6f776e20;
+-0ecb : 66696c65;
+-0ecc : 20747970;
+-0ecd : 65000000;
+-0ece : 41545220;
+-0ecf : 00000000;
+-0ed0 : 58442000;
+-0ed1 : 300a0000;
+-0ed2 : 58464420;
+-0ed3 : 00000000;
+-0ed4 : 42414420;
+-0ed5 : 73656374;
+-0ed6 : 6f722073;
+-0ed7 : 697a6500;
+-0ed8 : 4d442000;
+-0ed9 : 58455820;
+-0eda : 00000000;
+-0edb : 53442000;
+-0edc : 44442000;
+-0edd : 44495220;
+-0ede : 00000000;
+-0edf : 6f70656e;
+-0ee0 : 64697220;
+-0ee1 : 6661696c;
+-0ee2 : 65640a00;
+-0ee3 : 426f6f74;
+-0ee4 : 696e672e;
+-0ee5 : 2e2e0000;
+-0ee6 : 53797374;
+-0ee7 : 656d2073;
+-0ee8 : 65747469;
+-0ee9 : 6e67730a;
+-0eea : 00000000;
+-0eeb : 2d2d2d2d;
+-0eec : 2d2d2d2d;
+-0eed : 2d2d2d2d;
+-0eee : 2d2d2d0a;
+-0eef : 00000000;
+-0ef0 : 4d656d6f;
+-0ef1 : 72793a00;
+-0ef2 : 556e6b6e;
+-0ef3 : 6f776e00;
+-0ef4 : 524f4d20;
+-0ef5 : 62616e6b;
+-0ef6 : 3a000000;
+-0ef7 : 53706565;
+-0ef8 : 643a0000;
+-0ef9 : 204b487a;
+-0efa : 0a44313a;
+-0efb : 00000000;
+-0efc : 0a44323a;
++0e38 : 8c050824;
++0e39 : a23883e0;
++0e3a : 8c088c05;
++0e3b : 081083e0;
++0e3c : 8c088c05;
++0e3d : 0c83e08c;
++0e3e : 08fc0508;
++0e3f : 1083e08c;
++0e40 : 08fc050c;
++0e41 : ffb83983;
++0e42 : e08c08fc;
++0e43 : 0508802e;
++0e44 : 80e13883;
++0e45 : e08c088c;
++0e46 : 050883e0;
++0e47 : 8c088805;
++0e48 : 0826ad38;
++0e49 : 83e08c08;
++0e4a : 88050883;
++0e4b : e08c088c;
++0e4c : 05083183;
++0e4d : e08c0888;
++0e4e : 050c83e0;
++0e4f : 8c08f805;
++0e50 : 0883e08c;
++0e51 : 08fc0508;
++0e52 : 0783e08c;
++0e53 : 08f8050c;
++0e54 : 83e08c08;
++0e55 : fc050881;
++0e56 : 2a83e08c;
++0e57 : 08fc050c;
++0e58 : 83e08c08;
++0e59 : 8c050881;
++0e5a : 2a83e08c;
++0e5b : 088c050c;
++0e5c : ff953983;
++0e5d : e08c0890;
++0e5e : 0508802e;
++0e5f : 933883e0;
++0e60 : 8c088805;
++0e61 : 087083e0;
++0e62 : 8c08f405;
++0e63 : 0c519139;
++0e64 : 83e08c08;
++0e65 : f8050870;
++0e66 : 83e08c08;
++0e67 : f4050c51;
++0e68 : 83e08c08;
++0e69 : f4050883;
++0e6a : e0800c85;
++0e6b : 3d0d83e0;
++0e6c : 8c0c0483;
++0e6d : e08c0802;
++0e6e : 83e08c0c;
++0e6f : ff3d0d80;
++0e70 : 0b83e08c;
++0e71 : 08fc050c;
++0e72 : 83e08c08;
++0e73 : 88050881;
++0e74 : 06ff1170;
++0e75 : 097083e0;
++0e76 : 8c088c05;
++0e77 : 080683e0;
++0e78 : 8c08fc05;
++0e79 : 081183e0;
++0e7a : 8c08fc05;
++0e7b : 0c83e08c;
++0e7c : 08880508;
++0e7d : 812a83e0;
++0e7e : 8c088805;
++0e7f : 0c83e08c;
++0e80 : 088c0508;
++0e81 : 1083e08c;
++0e82 : 088c050c;
++0e83 : 51515151;
++0e84 : 83e08c08;
++0e85 : 88050880;
++0e86 : 2e8438ff;
++0e87 : ab3983e0;
++0e88 : 8c08fc05;
++0e89 : 087083e0;
++0e8a : 800c5183;
++0e8b : 3d0d83e0;
++0e8c : 8c0c04fc;
++0e8d : 3d0d7670;
++0e8e : 797b5555;
++0e8f : 55558f72;
++0e90 : 278c3872;
++0e91 : 75078306;
++0e92 : 5170802e;
++0e93 : a938ff12;
++0e94 : 5271ff2e;
++0e95 : 98387270;
++0e96 : 81055433;
++0e97 : 74708105;
++0e98 : 5634ff12;
++0e99 : 5271ff2e;
++0e9a : 098106ea;
++0e9b : 387483e0;
++0e9c : 800c863d;
++0e9d : 0d047451;
++0e9e : 72708405;
++0e9f : 54087170;
++0ea0 : 8405530c;
++0ea1 : 72708405;
++0ea2 : 54087170;
++0ea3 : 8405530c;
++0ea4 : 72708405;
++0ea5 : 54087170;
++0ea6 : 8405530c;
++0ea7 : 72708405;
++0ea8 : 54087170;
++0ea9 : 8405530c;
++0eaa : f0125271;
++0eab : 8f26c938;
++0eac : 83722795;
++0ead : 38727084;
++0eae : 05540871;
++0eaf : 70840553;
++0eb0 : 0cfc1252;
++0eb1 : 718326ed;
++0eb2 : 387054ff;
++0eb3 : 81390000;
++0eb4 : 00ffffff;
++0eb5 : ff00ffff;
++0eb6 : ffff00ff;
++0eb7 : ffffff00;
++0eb8 : 70707042;
++0eb9 : 409c0202;
++0eba : 02020202;
++0ebb : 02020202;
++0ebc : 02020202;
++0ebd : 02020202;
++0ebe : 02020202;
++0ebf : 02704100;
++0ec0 : 06000000;
++0ec1 : 70707042;
++0ec2 : 409c0202;
++0ec3 : 02020202;
++0ec4 : 02020202;
++0ec5 : 02020202;
++0ec6 : 02020202;
++0ec7 : 02020202;
++0ec8 : 02704100;
++0ec9 : 9c000000;
++0eca : 2f000000;
++0ecb : 4f70656e;
++0ecc : 696e673a;
++0ecd : 00000000;
++0ece : 6661696c;
++0ecf : 0a000000;
++0ed0 : 6f6b0a00;
++0ed1 : 436f756c;
++0ed2 : 64206e6f;
++0ed3 : 74207265;
++0ed4 : 61642068;
++0ed5 : 65616465;
++0ed6 : 720a0000;
++0ed7 : 556e6b6e;
++0ed8 : 6f776e20;
++0ed9 : 66696c65;
++0eda : 20747970;
++0edb : 65000000;
++0edc : 41545220;
++0edd : 00000000;
++0ede : 58442000;
++0edf : 300a0000;
++0ee0 : 58464420;
++0ee1 : 00000000;
++0ee2 : 42414420;
++0ee3 : 73656374;
++0ee4 : 6f722073;
++0ee5 : 697a6500;
++0ee6 : 4d442000;
++0ee7 : 58455820;
++0ee8 : 00000000;
++0ee9 : 53442000;
++0eea : 44442000;
++0eeb : 44495220;
++0eec : 00000000;
++0eed : 6f70656e;
++0eee : 64697220;
++0eef : 6661696c;
++0ef0 : 65640a00;
++0ef1 : 426f6f74;
++0ef2 : 696e672e;
++0ef3 : 2e2e0000;
++0ef4 : 53797374;
++0ef5 : 656d2073;
++0ef6 : 65747469;
++0ef7 : 6e67730a;
++0ef8 : 00000000;
++0ef9 : 2d2d2d2d;
++0efa : 2d2d2d2d;
++0efb : 2d2d2d2d;
++0efc : 2d2d2d0a;
+ 0efd : 00000000;
+-0efe : 0a44333a;
+-0eff : 00000000;
+-0f00 : 0a44343a;
+-0f01 : 00000000;
+-0f02 : 0a526562;
+-0f03 : 6f6f7400;
+-0f04 : 0a457869;
+-0f05 : 74000000;
+-0f06 : 3332304b;
+-0f07 : 69422052;
+-0f08 : 616d626f;
++0efe : 4d656d6f;
++0eff : 72793a00;
++0f00 : 556e6b6e;
++0f01 : 6f776e00;
++0f02 : 524f4d20;
++0f03 : 62616e6b;
++0f04 : 3a000000;
++0f05 : 53706565;
++0f06 : 643a0000;
++0f07 : 204b487a;
++0f08 : 0a44313a;
+ 0f09 : 00000000;
+-0f0a : 30202864;
+-0f0b : 65666175;
+-0f0c : 6c743a58;
+-0f0d : 4c290000;
+-0f0e : 31202864;
+-0f0f : 65666175;
+-0f10 : 6c743a58;
+-0f11 : 4c202b20;
+-0f12 : 68692073;
+-0f13 : 70656564;
+-0f14 : 29000000;
+-0f15 : 3332304b;
+-0f16 : 69422043;
+-0f17 : 6f6d7079;
+-0f18 : 2053686f;
+-0f19 : 70000000;
+-0f1a : 36344b69;
+-0f1b : 42000000;
+-0f1c : 3132384b;
+-0f1d : 69420000;
+-0f1e : 32202864;
+-0f1f : 65666175;
+-0f20 : 6c743a55;
+-0f21 : 6c74696d;
+-0f22 : 6f6e2900;
+-0f23 : 33202864;
+-0f24 : 65666175;
+-0f25 : 6c743a4f;
+-0f26 : 53204220;
+-0f27 : 2b206869;
+-0f28 : 20737065;
+-0f29 : 65642900;
+-0f2a : 636d643a;
+-0f2b : 00000000;
+-0f2c : 45525220;
+-0f2d : 00000000;
+-0f2e : 53504453;
+-0f2f : 00000000;
+-0f30 : 53504446;
+-0f31 : 00000000;
+-0f32 : 2873656e;
+-0f33 : 643a0000;
+-0f34 : 3a63686b;
+-0f35 : 3a000000;
+-0f36 : 73646361;
+-0f37 : 72640a00;
+-0f38 : 6469736b;
+-0f39 : 5f696e69;
+-0f3a : 743a0000;
+-0f3b : 6d6f756e;
+-0f3c : 743a0000;
+-0f3d : 6f70656e;
+-0f3e : 6469723a;
++0f0a : 0a44323a;
++0f0b : 00000000;
++0f0c : 0a44333a;
++0f0d : 00000000;
++0f0e : 0a44343a;
++0f0f : 00000000;
++0f10 : 0a526562;
++0f11 : 6f6f7400;
++0f12 : 0a457869;
++0f13 : 74000000;
++0f14 : 3332304b;
++0f15 : 69422052;
++0f16 : 616d626f;
++0f17 : 00000000;
++0f18 : 30202864;
++0f19 : 65666175;
++0f1a : 6c743a58;
++0f1b : 4c290000;
++0f1c : 31202864;
++0f1d : 65666175;
++0f1e : 6c743a58;
++0f1f : 4c202b20;
++0f20 : 68692073;
++0f21 : 70656564;
++0f22 : 29000000;
++0f23 : 3332304b;
++0f24 : 69422043;
++0f25 : 6f6d7079;
++0f26 : 2053686f;
++0f27 : 70000000;
++0f28 : 36344b69;
++0f29 : 42000000;
++0f2a : 3132384b;
++0f2b : 69420000;
++0f2c : 32202864;
++0f2d : 65666175;
++0f2e : 6c743a55;
++0f2f : 6c74696d;
++0f30 : 6f6e2900;
++0f31 : 33202864;
++0f32 : 65666175;
++0f33 : 6c743a4f;
++0f34 : 53204220;
++0f35 : 2b206869;
++0f36 : 20737065;
++0f37 : 65642900;
++0f38 : 636d643a;
++0f39 : 00000000;
++0f3a : 45525220;
++0f3b : 00000000;
++0f3c : 53504453;
++0f3d : 00000000;
++0f3e : 53504446;
+ 0f3f : 00000000;
+-0f40 : 424f4f54;
+-0f41 : 2e415452;
+-0f42 : 00000000;
+-0f43 : 50617573;
+-0f44 : 65640a00;
+-0f45 : 53746174;
+-0f46 : 3a000000;
+-0f47 : 3a646f6e;
+-0f48 : 650a0000;
+-0f49 : 53656374;
+-0f4a : 6f723a00;
+-0f4b : 20726563;
+-0f4c : 65697665;
+-0f4d : 3a000000;
+-0f4e : 2073656e;
+-0f4f : 64696e67;
+-0f50 : 0a000000;
+-0f51 : 64617461;
+-0f52 : 20000000;
+-0f53 : 6e616d65;
+-0f54 : 20000000;
+-0f55 : 6e756d74;
+-0f56 : 6f627566;
+-0f57 : 66657220;
+-0f58 : 00000000;
+-0f59 : 626f6f74;
+-0f5a : 20000000;
+-0f5b : 00000000;
+-0f5c : 00000000;
+-0f5d : 72025f07;
+-0f5e : f807a900;
+-0f5f : 8d04038d;
+-0f60 : 4402a907;
+-0f61 : 8d0503a9;
+-0f62 : 708d0a03;
+-0f63 : a9018d0b;
+-0f64 : 03850960;
+-0f65 : 7d8a4820;
+-0f66 : 53e488d0;
+-0f67 : fa68aa8c;
+-0f68 : 8e07ad7d;
+-0f69 : 07ee8e07;
+-0f6a : 60a9938d;
+-0f6b : e202a907;
+-0f6c : 8de302a2;
+-0f6d : 0220da07;
+-0f6e : 954320da;
+-0f6f : 07954435;
+-0f70 : 43c9fff0;
+-0f71 : f0caca10;
+-0f72 : ec3006e6;
+-0f73 : 45d002e6;
+-0f74 : 4620da07;
+-0f75 : a2018144;
+-0f76 : b545d543;
+-0f77 : d0edca10;
+-0f78 : f720d207;
+-0f79 : 4c9407a9;
+-0f7a : 038d0fd2;
+-0f7b : 6ce202ad;
+-0f7c : 8e07cd7f;
+-0f7d : 07d0abee;
+-0f7e : 0a03d003;
+-0f7f : ee0b03ad;
+-0f80 : 7d070d7e;
+-0f81 : 07d08e20;
+-0f82 : d2076ce0;
+-0f83 : 0220da07;
+-0f84 : 8de00220;
+-0f85 : da078de1;
+-0f86 : 022de002;
+-0f87 : c9fff0ed;
+-0f88 : a9008d8e;
+-0f89 : 07f08200;
+-0f8a : 0001d20f;
+-0f8b : 0001d400;
+-0f8c : 0001d401;
+-0f8d : 0001d409;
+-0f8e : 0001d010;
+-0f8f : 0001d301;
+-0f90 : 0001d300;
+-0f91 : 0001d20a;
+-0f92 : 0001d01b;
+-0f93 : 0001d018;
+-0f94 : 0001d017;
+-0f95 : 0001d01a;
+-0f96 : 0001d403;
+-0f97 : 0001d402;
+-0f98 : 0001d40e;
+-0f99 : 0004007c;
+-0f9a : 00040078;
+-0f9b : 00040074;
+-0f9c : 00040068;
+-0f9d : 00040060;
+-0f9e : 0004005c;
+-0f9f : 00040058;
+-0fa0 : 00040054;
+-0fa1 : 00040050;
+-0fa2 : 0004004c;
+-0fa3 : 00040048;
+-0fa4 : 00040044;
+-0fa5 : 00040040;
+-0fa6 : 00040028;
+-0fa7 : 00040024;
+-0fa8 : 00040020;
+-0fa9 : 0004001c;
+-0faa : 00040018;
+-0fab : 00040014;
+-0fac : 00040010;
+-0fad : 0004000c;
+-0fae : 00040008;
+-0faf : 00040004;
+-0fb0 : 00040000;
++0f40 : 2873656e;
++0f41 : 643a0000;
++0f42 : 3a63686b;
++0f43 : 3a000000;
++0f44 : 73646361;
++0f45 : 72640a00;
++0f46 : 6469736b;
++0f47 : 5f696e69;
++0f48 : 743a0000;
++0f49 : 6d6f756e;
++0f4a : 743a0000;
++0f4b : 6f70656e;
++0f4c : 6469723a;
++0f4d : 00000000;
++0f4e : 424f4f54;
++0f4f : 2e415452;
++0f50 : 00000000;
++0f51 : 61746172;
++0f52 : 69726f6d;
++0f53 : 2e62696e;
++0f54 : 00000000;
++0f55 : 53746174;
++0f56 : 3a000000;
++0f57 : 3a646f6e;
++0f58 : 650a0000;
++0f59 : 53656374;
++0f5a : 6f723a00;
++0f5b : 20726563;
++0f5c : 65697665;
++0f5d : 3a000000;
++0f5e : 2073656e;
++0f5f : 64696e67;
++0f60 : 0a000000;
++0f61 : 64617461;
++0f62 : 20000000;
++0f63 : 626f6f74;
++0f64 : 20000000;
++0f65 : 6e616d65;
++0f66 : 20000000;
++0f67 : 6e756d74;
++0f68 : 6f627566;
++0f69 : 66657220;
++0f6a : 00000000;
++0f6b : 00000000;
++0f6c : 00000000;
++0f6d : 72025f07;
++0f6e : f807a900;
++0f6f : 8d04038d;
++0f70 : 4402a907;
++0f71 : 8d0503a9;
++0f72 : 708d0a03;
++0f73 : a9018d0b;
++0f74 : 03850960;
++0f75 : 7d8a4820;
++0f76 : 53e488d0;
++0f77 : fa68aa8c;
++0f78 : 8e07ad7d;
++0f79 : 07ee8e07;
++0f7a : 60a9938d;
++0f7b : e202a907;
++0f7c : 8de302a2;
++0f7d : 0220da07;
++0f7e : 954320da;
++0f7f : 07954435;
++0f80 : 43c9fff0;
++0f81 : f0caca10;
++0f82 : ec3006e6;
++0f83 : 45d002e6;
++0f84 : 4620da07;
++0f85 : a2018144;
++0f86 : b545d543;
++0f87 : d0edca10;
++0f88 : f720d207;
++0f89 : 4c9407a9;
++0f8a : 038d0fd2;
++0f8b : 6ce202ad;
++0f8c : 8e07cd7f;
++0f8d : 07d0abee;
++0f8e : 0a03d003;
++0f8f : ee0b03ad;
++0f90 : 7d070d7e;
++0f91 : 07d08e20;
++0f92 : d2076ce0;
++0f93 : 0220da07;
++0f94 : 8de00220;
++0f95 : da078de1;
++0f96 : 022de002;
++0f97 : c9fff0ed;
++0f98 : a9008d8e;
++0f99 : 07f08200;
++0f9a : 0001d20f;
++0f9b : 0001d400;
++0f9c : 0001d401;
++0f9d : 0001d409;
++0f9e : 0001d010;
++0f9f : 0001d301;
++0fa0 : 0001d300;
++0fa1 : 0001d20a;
++0fa2 : 0001d01b;
++0fa3 : 0001d018;
++0fa4 : 0001d017;
++0fa5 : 0001d01a;
++0fa6 : 0001d403;
++0fa7 : 0001d402;
++0fa8 : 0001d40e;
++0fa9 : 0004007c;
++0faa : 00040078;
++0fab : 00040074;
++0fac : 00040068;
++0fad : 00040060;
++0fae : 0004005c;
++0faf : 00040058;
++0fb0 : 00040054;
++0fb1 : 00040050;
++0fb2 : 0004004c;
++0fb3 : 00040048;
++0fb4 : 00040044;
++0fb5 : 00040040;
++0fb6 : 00040028;
++0fb7 : 00040024;
++0fb8 : 00040020;
++0fb9 : 0004001c;
++0fba : 00040018;
++0fbb : 00040014;
++0fbc : 00040010;
++0fbd : 0004000c;
++0fbe : 00040008;
++0fbf : 00040004;
++0fc0 : 00040000;
+ END; 
+diff -ur atari800core_20140301_de1/zpu_config_regs.vhdl atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl
+--- atari800core_20140301_de1/zpu_config_regs.vhdl	2014-01-18 20:59:03.000000000 +0000
++++ atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl	2014-02-02 19:12:56.000000000 +0000
+@@ -413,11 +413,11 @@
+ 			end if;
+ 			
+ 			if (addr_decoded(2) = '1') then
+-				data_out(9 downto 0) <= SWITCH;
++				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+ 			end if;		
+ 			
+ 			if (addr_decoded(3) = '1') then
+-				data_out(3 downto 0) <= KEY;
++				data_out(3 downto 0) <= key;
+ 			end if;		
+ 			
+ 			if (addr_decoded(4) = '1') then
+@@ -441,11 +441,11 @@
+ 			end if;	
+ 			
+ 			if (addr_decoded(9) = '1') then
+-				data_out <= X"00000000"; -- DE1!
++				--data_out <= X"00000000"; -- DE1!
+ 				--data_out <= X"00000001"; -- DE2!
+ 				--data_out <= X"00000002"; -- SOCKIT!
+ 				--data_out <= X"00000003"; -- REPLAY!
+-				--data_out <= X"00000004"; -- MMC!		
++				data_out <= X"00000004"; -- MMC!		
+ 			end if;
+ 			
+ 			if (addr_decoded(10) = '1') then
+@@ -479,12 +479,12 @@
+ 	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+ 	SDCARD_DAT3 <= spi_chip_select(0);
+ 	
+-	PAL <= switch(6);
+-	USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings...
++	PAL <= '1'; -- TODO
++	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+ 	RAM_SELECT <= ram_select_reg;
+-	VGA <= switch(9);
+-	COMPOSITE_ON_HSYNC <= switch(8);
+-	GPIO_ENABLE <= gpio_enable_reg; -- enable gpio - FIXME - esp carts!
++	VGA <= '1';
++	COMPOSITE_ON_HSYNC <= '0';
++	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
+ 	ROM_SELECT <= rom_select_reg;
+ 	
+ 	reset_n <= reset_n_reg; -- system reset or pll not locked
Index: unmerged/core/de1/CHANGELOG
===================================================================
--- unmerged/core/de1/CHANGELOG	(nonexistent)
+++ unmerged/core/de1/CHANGELOG	(revision 1)
@@ -0,0 +1,3 @@
+Version 1
+---------
+Initial source release
Index: unmerged/core/de1/antic_counter.vhdl
===================================================================
--- unmerged/core/de1/antic_counter.vhdl	(nonexistent)
+++ unmerged/core/de1/antic_counter.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY antic_counter IS
+generic
+(
+	STORE_WIDTH : natural := 1;
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+);
+END antic_counter;
+
+ARCHITECTURE vhdl OF antic_counter IS
+	signal value_next : std_logic_vector(STORE_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(STORE_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= value_reg(STORE_WIDTH-1 downto COUNT_WIDTH)&std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: unmerged/core/de1/atari800core.qsf
===================================================================
--- unmerged/core/de1/atari800core.qsf	(nonexistent)
+++ unmerged/core/de1/atari800core.qsf	(revision 1)
@@ -0,0 +1,626 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_CE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_LB_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_OE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_UB_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_WE_N
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[0]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[1]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[2]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[3]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[4]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[5]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[6]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[7]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[8]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[9]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[10]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[11]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[12]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[13]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[14]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[15]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[16]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_ADDR[17]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[0]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[1]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[2]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[3]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[4]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[5]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[6]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[7]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[8]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[9]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[10]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[11]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[12]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[13]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[14]
+set_instance_assignment -name CYCLONEII_TERMINATION "SERIES 25 OHMS" -to SRAM_DQ[15]
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_V20 -to SD_CLK
+set_location_assignment PIN_Y20 -to SD_CMD
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_W20 -to SD_DATA
+set_location_assignment PIN_U20 -to SD_THREE
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name VHDL_FILE ledsw.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE dumprom.vhdl
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE nmigen.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE tvsync.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE flashrom.vhdl
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: unmerged/core/de1/atari800core.sdc~
===================================================================
--- unmerged/core/de1/atari800core.sdc~	(nonexistent)
+++ unmerged/core/de1/atari800core.sdc~	(revision 1)
@@ -0,0 +1,2 @@
+create_clock -period 50MHz [get_ports CLOCK_50]
+derive_pll_clocks
\ No newline at end of file
Index: unmerged/core/de1/cpu.vhd
===================================================================
--- unmerged/core/de1/cpu.vhd	(nonexistent)
+++ unmerged/core/de1/cpu.vhd	(revision 1)
@@ -0,0 +1,142 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+ENTITY cpu IS
+PORT 
+(
+	CLK,RESET,ENABLE : IN STD_logic;
+	DI : IN std_logic_vector(7 downto 0);
+	IRQ_n   : in  std_logic;
+	NMI_n   : in  std_logic;
+	MEMORY_READY : in std_logic;
+	THROTTLE : in std_logic;
+	RDY : in std_logic;
+	DO : OUT std_logic_vector(7 downto 0);
+	A : OUT std_logic_vector(15 downto 0);
+	R_W_n : OUT std_logic;
+	CPU_FETCH : out std_logic
+);
+END cpu;
+
+architecture vhdl of cpu is
+component cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end component;
+
+	signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle
+		
+	-- Support for Peter's core (NMI patch applied)
+	signal debugOpcode : unsigned(7 downto 0);
+	signal debugPc : unsigned(15 downto 0);
+	signal debugA : unsigned(7 downto 0);
+	signal debugX : unsigned(7 downto 0);
+	signal debugY : unsigned(7 downto 0);
+	signal debugS : unsigned(7 downto 0);
+	signal di_unsigned : unsigned(7 downto 0);
+   signal do_unsigned : unsigned(7 downto 0);
+	signal addr_unsigned : unsigned(15 downto 0);
+	signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line
+	signal WE : std_logic;
+	signal nmi_pending_next : std_logic; -- NMI during RDY
+	signal nmi_pending_reg : std_logic;
+	signal nmi_n_adjusted : std_logic;
+	signal nmi_n_reg : std_logic;
+	signal nmi_edge : std_logic;
+	
+	signal CPU_ENABLE_RESET : std_logic;
+	signal not_rdy : std_logic;	
+	
+BEGIN
+	CPU_ENABLE <= ENABLE and memory_ready and THROTTLE;
+	
+	-- CPU designed by Peter W - as used in Chameleon
+	di_unsigned <= unsigned(di);
+	cpu_6502_peter:cpu_65xx
+		generic map
+		(
+			pipelineOpcode => false,
+			pipelineAluMux => false,
+			pipelineAluOut => false
+		)
+		port map (
+			clk => clk,
+			enable => CPU_ENABLE_RDY,
+			halt => '0',
+			reset=>reset,
+			nmi_n=>nmi_n_adjusted,
+			irq_n=>irq_n,
+			d=>di_unsigned,
+			q=>do_unsigned,
+			addr=>addr_unsigned,
+			WE=>WE,
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugOpcode,
+			debugS => debugS
+		);
+		CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
+		
+		CPU_ENABLE_RESET <= CPU_ENABLE or reset;
+		not_rdy <= not(rdy);
+		
+		nmi_edge <= not(nmi_n) and nmi_n_reg;
+		nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable));
+		nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n;
+		
+	-- register
+	process(clk,reset)
+	begin
+		if (RESET = '1') then
+			nmi_pending_reg <= '0';
+			nmi_n_reg <= '1';
+		elsif (clk'event and clk='1') then						
+			nmi_pending_reg <= nmi_pending_next;		
+			nmi_n_reg <= nmi_n;
+		end if;
+	end process;	
+
+	-- outputs
+	r_w_n <= not(we);
+	do <= std_logic_vector(do_unsigned);
+	a <= std_logic_vector(addr_unsigned);
+		
+	CPU_FETCH <= ENABLE and THROTTLE;
+
+END vhdl;
Index: unmerged/core/de1/delay_line.vhdl
===================================================================
--- unmerged/core/de1/delay_line.vhdl	(nonexistent)
+++ unmerged/core/de1/delay_line.vhdl	(revision 1)
@@ -0,0 +1,57 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY delay_line IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC
+);
+END delay_line;
+
+ARCHITECTURE vhdl OF delay_line IS
+	signal shift_reg : std_logic_vector(COUNT-1 downto 0);
+	signal shift_next : std_logic_vector(COUNT-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>'0');
+		end if;		
+	end process;
+	
+	-- output
+	data_out <= shift_reg(0) and enable;
+		
+END vhdl;
Index: unmerged/core/de1/gtia.vhdl
===================================================================
--- unmerged/core/de1/gtia.vhdl	(nonexistent)
+++ unmerged/core/de1/gtia.vhdl	(revision 1)
@@ -0,0 +1,1556 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	CPU_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_FETCH : IN STD_LOGIC;
+	
+	CPU_ENABLE_ORIGINAL : in std_logic;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	PAL : IN STD_LOGIC;
+	
+	-- ANTIC interface
+	COLOUR_CLOCK_ORIGINAL : in std_logic;
+	COLOUR_CLOCK : in std_logic;
+	COLOUR_CLOCK_HIGHRES : in std_logic;
+	AN : IN STD_LOGIC_VECTOR(2 downto 0);
+	
+	-- keyboard interface
+	CONSOL_START : IN STD_LOGIC;
+	CONSOL_SELECT : IN STD_LOGIC;
+	CONSOL_OPTION : IN STD_LOGIC;
+	
+	-- keyboard interface
+	TRIG0 : IN STD_LOGIC;
+	TRIG1 : IN STD_LOGIC;
+	TRIG2 : IN STD_LOGIC;
+	TRIG3 : IN STD_LOGIC;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	-- TO scandoubler...
+	COLOUR_out : out std_logic_vector(7 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic;
+	
+	-- To speaker
+	sound : out std_logic
+);
+END gtia;
+
+ARCHITECTURE vhdl OF gtia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component gtia_player IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : in std_logic;
+		
+		COLOUR_ENABLE : IN STD_LOGIC;
+		LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+		PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+		SIZE : in std_logic_vector(1 downto 0);
+		bitmap : in std_logic_vector(7 downto 0);
+		
+		output : out std_logic
+	);
+	END component;
+	
+	component gtia_priority IS
+	PORT 
+	( 
+		CLK : in std_logic;
+		colour_enable : in std_logic;
+		PRIOR : in std_logic_vector(7 downto 0);
+		P0 : in std_logic;
+		P1 : in std_logic;
+		P2	: in std_logic;
+		P3 : in std_logic;
+		PF0 : in std_logic;
+		PF1 : in std_logic;
+		PF2 : in std_logic;
+		PF3 : in std_logic;
+		BK : in std_logic;
+		
+		P0_OUT : out std_logic;
+		P1_OUT : out std_logic;
+		P2_OUT : out std_logic;
+		P3_OUT : out std_logic;
+		PF0_OUT : out std_logic;
+		PF1_OUT : out std_logic;
+		PF2_OUT : out std_logic;
+		PF3_OUT : out std_logic;
+		BK_OUT : out std_logic
+	);
+	END component;	
+	
+	signal addr_decoded : std_logic_vector(31 downto 0);
+	
+	signal hposp0_raw_next : std_logic_vector(7 downto 0);
+	signal hposp0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp1_raw_next : std_logic_vector(7 downto 0);
+	signal hposp1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp2_raw_next : std_logic_vector(7 downto 0);
+	signal hposp2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp3_raw_next : std_logic_vector(7 downto 0);
+	signal hposp3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp3_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal hposm0_raw_next : std_logic_vector(7 downto 0);
+	signal hposm0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm1_raw_next : std_logic_vector(7 downto 0);
+	signal hposm1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm2_raw_next : std_logic_vector(7 downto 0);
+	signal hposm2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm3_raw_next : std_logic_vector(7 downto 0);
+	signal hposm3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm3_delayed_reg : std_logic_vector(7 downto 0);	
+	
+	signal sizep0_raw_next : std_logic_vector(1 downto 0);
+	signal sizep0_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep1_raw_next : std_logic_vector(1 downto 0);
+	signal sizep1_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep2_raw_next : std_logic_vector(1 downto 0);
+	signal sizep2_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep3_raw_next : std_logic_vector(1 downto 0);
+	signal sizep3_raw_reg : std_logic_vector(1 downto 0);
+
+	signal sizem_raw_next : std_logic_vector(7 downto 0);
+	signal sizem_raw_reg : std_logic_vector(7 downto 0);
+
+	signal sizep0_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep1_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep2_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep3_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizem_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal grafp0_next : std_logic_vector(7 downto 0);
+	signal grafp0_reg : std_logic_vector(7 downto 0);
+	signal grafp1_next : std_logic_vector(7 downto 0);
+	signal grafp1_reg : std_logic_vector(7 downto 0);
+	signal grafp2_next : std_logic_vector(7 downto 0);
+	signal grafp2_reg : std_logic_vector(7 downto 0);
+	signal grafp3_next : std_logic_vector(7 downto 0);
+	signal grafp3_reg : std_logic_vector(7 downto 0);
+	
+	signal grafm_next : std_logic_vector(7 downto 0);
+	signal grafm_reg : std_logic_vector(7 downto 0);
+
+	signal colpm0_raw_next : std_logic_vector(7 downto 1);
+	signal colpm0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm1_raw_next : std_logic_vector(7 downto 1);
+	signal colpm1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm2_raw_next : std_logic_vector(7 downto 1);
+	signal colpm2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm3_raw_next : std_logic_vector(7 downto 1);
+	signal colpm3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colpf0_raw_next : std_logic_vector(7 downto 1);
+	signal colpf0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf1_raw_next : std_logic_vector(7 downto 1);
+	signal colpf1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf2_raw_next : std_logic_vector(7 downto 1);
+	signal colpf2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf3_raw_next : std_logic_vector(7 downto 1);
+	signal colpf3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colbk_raw_next : std_logic_vector(7 downto 1);
+	signal colbk_raw_reg : std_logic_vector(7 downto 1);
+	signal colbk_delayed_reg : std_logic_vector(7 downto 1);	
+	
+	signal prior_raw_next : std_logic_vector(7 downto 0);
+	signal prior_raw_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed2_reg : std_logic_vector(7 downto 6);
+	
+	signal vdelay_next : std_logic_vector(7 downto 0);
+	signal vdelay_reg : std_logic_vector(7 downto 0);
+
+	signal gractl_next : std_logic_vector(2 downto 0);
+	signal gractl_reg : std_logic_vector(2 downto 0);
+	
+	signal consol_output_next : std_logic_vector(3 downto 0);
+	signal consol_output_reg : std_logic_vector(3 downto 0);
+	
+	signal trig0_next : std_logic;
+	signal trig0_reg : std_logic;
+	signal trig1_next : std_logic;
+	signal trig1_reg : std_logic;
+	signal trig2_next : std_logic;
+	signal trig2_reg : std_logic;
+	signal trig3_next : std_logic;
+	signal trig3_reg : std_logic;
+	
+	-- collisions
+	signal hitclr_write : std_logic;
+	
+	signal m0pf_next : std_logic_vector(3 downto 0);
+	signal m0pf_reg : std_logic_vector(3 downto 0);
+	signal m1pf_next : std_logic_vector(3 downto 0);
+	signal m1pf_reg : std_logic_vector(3 downto 0);
+	signal m2pf_next : std_logic_vector(3 downto 0);
+	signal m2pf_reg : std_logic_vector(3 downto 0);
+	signal m3pf_next : std_logic_vector(3 downto 0);
+	signal m3pf_reg : std_logic_vector(3 downto 0);
+
+	signal m0pl_next : std_logic_vector(3 downto 0);
+	signal m0pl_reg : std_logic_vector(3 downto 0);
+	signal m1pl_next : std_logic_vector(3 downto 0);
+	signal m1pl_reg : std_logic_vector(3 downto 0);
+	signal m2pl_next : std_logic_vector(3 downto 0);
+	signal m2pl_reg : std_logic_vector(3 downto 0);
+	signal m3pl_next : std_logic_vector(3 downto 0);
+	signal m3pl_reg : std_logic_vector(3 downto 0);
+	
+	signal p0pf_next : std_logic_vector(3 downto 0);
+	signal p0pf_reg : std_logic_vector(3 downto 0);
+	signal p1pf_next : std_logic_vector(3 downto 0);
+	signal p1pf_reg : std_logic_vector(3 downto 0);
+	signal p2pf_next : std_logic_vector(3 downto 0);
+	signal p2pf_reg : std_logic_vector(3 downto 0);
+	signal p3pf_next : std_logic_vector(3 downto 0);
+	signal p3pf_reg : std_logic_vector(3 downto 0);	
+	
+	signal p0pl_next : std_logic_vector(3 downto 0);
+	signal p0pl_reg : std_logic_vector(3 downto 0);
+	signal p1pl_next : std_logic_vector(3 downto 0);
+	signal p1pl_reg : std_logic_vector(3 downto 0);
+	signal p2pl_next : std_logic_vector(3 downto 0);
+	signal p2pl_reg : std_logic_vector(3 downto 0);
+	signal p3pl_next : std_logic_vector(3 downto 0);
+	signal p3pl_reg : std_logic_vector(3 downto 0);		
+	
+	-- priority
+	signal set_p0 : std_logic;
+	signal set_p1 : std_logic;
+	signal set_p2 : std_logic;
+	signal set_p3 : std_logic;
+	signal set_pf0 : std_logic;
+	signal set_pf1 : std_logic;
+	signal set_pf2 : std_logic;
+	signal set_pf3 : std_logic;
+	signal set_bk : std_logic;	
+	
+	-- ouput/sync
+	signal COLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal COLOUR_REG : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_REG : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+	
+	signal hsync_start : std_logic;
+	signal hsync_end : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	-- visible region (no collision detection outside this)
+	signal visible_live : std_logic;
+	
+	-- antic input decode
+	signal an_prev3_next : std_logic_vector(2 downto 0);
+	signal an_prev3_reg : std_logic_vector(2 downto 0);	
+	signal an_prev2_next : std_logic_vector(2 downto 0);
+	signal an_prev2_reg : std_logic_vector(2 downto 0);	
+	signal an_prev_next : std_logic_vector(2 downto 0);
+	signal an_prev_reg : std_logic_vector(2 downto 0);
+	
+	signal active_bk_modify_next : std_logic_vector(7 downto 0);
+	signal active_bk_modify_reg : std_logic_vector(7 downto 0);
+	signal active_bk_valid_next : std_logic_vector(7 downto 0);
+	signal active_bk_valid_reg : std_logic_vector(7 downto 0);
+	signal active_bk_live : std_logic;
+	signal active_pf0_live : std_logic;
+	signal active_pf1_live : std_logic;
+	signal active_pf2_live : std_logic;
+	signal active_pf2_collision_live : std_logic;
+	signal active_pf3_live : std_logic;
+	signal active_pf3_collision_live : std_logic;
+	signal active_pm0_live : std_logic;
+	signal active_pm1_live : std_logic;
+	signal active_pm2_live : std_logic;
+	signal active_pm3_live : std_logic;
+	
+	signal active_p0_live : std_logic;
+	signal active_p1_live : std_logic;
+	signal active_p2_live : std_logic;
+	signal active_p3_live : std_logic;
+	signal active_m0_live : std_logic;
+	signal active_m1_live : std_logic;
+	signal active_m2_live : std_logic;
+	signal active_m3_live : std_logic;
+	
+	signal active_hr_next : std_logic_vector(1 downto 0);
+	signal active_hr_reg : std_logic_vector(1 downto 0);
+	signal highres_next : std_logic;
+	signal highres_reg : std_logic;
+	
+	-- horizontal position counter
+	signal hpos_reg : std_logic_vector(7 downto 0);
+	signal reset_counter : std_logic;
+	signal counter_load_value : std_logic_vector(7 downto 0);
+	
+	-- sub colour clock highres mode	
+	signal trigger_secondhalf : std_logic;
+	
+	-- pmg dma
+	signal grafm_dma_load : std_logic;
+	signal grafm_dma_next : std_logic_vector(7 downto 0);
+	signal grafp0_dma_load : std_logic;
+	signal grafp0_dma_next : std_logic_vector(7 downto 0);
+	signal grafp1_dma_load : std_logic;
+	signal grafp1_dma_next : std_logic_vector(7 downto 0);
+	signal grafp2_dma_load : std_logic;
+	signal grafp2_dma_next : std_logic_vector(7 downto 0);
+	signal grafp3_dma_load : std_logic;
+	signal grafp3_dma_next : std_logic_vector(7 downto 0);
+	signal odd_scanline_next : std_logic;
+	signal odd_scanline_reg : std_logic;
+	
+	signal pmg_dma_state_next : std_logic_vector(2 downto 0);
+	signal pmg_dma_state_reg : std_logic_vector(2 downto 0);
+	constant pmg_dma_missile : std_logic_vector(2 downto 0) := "000";
+	constant pmg_dma_player0 : std_logic_vector(2 downto 0) := "001";
+	constant pmg_dma_player1 : std_logic_vector(2 downto 0) := "010";
+	constant pmg_dma_player2 : std_logic_vector(2 downto 0) := "011";
+	constant pmg_dma_player3 : std_logic_vector(2 downto 0) := "100";
+	constant pmg_dma_done    : std_logic_vector(2 downto 0) := "101";	
+	constant pmg_dma_instruction : std_logic_vector(2 downto 0) := "110";	
+	
+	signal memory_ready : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			hposp0_raw_reg <= (others=>'0');
+			hposp1_raw_reg <= (others=>'0');
+			hposp2_raw_reg <= (others=>'0');
+			hposp3_raw_reg <= (others=>'0');
+
+			hposm0_raw_reg <= (others=>'0');
+			hposm1_raw_reg <= (others=>'0');
+			hposm2_raw_reg <= (others=>'0');
+			hposm3_raw_reg <= (others=>'0');			
+
+			sizep0_raw_reg <= (others=>'0');
+			sizep1_raw_reg <= (others=>'0');
+			sizep2_raw_reg <= (others=>'0');
+			sizep3_raw_reg <= (others=>'0');
+
+			sizem_raw_reg <= (others=>'0');
+			
+			grafp0_reg <= (others=>'0');
+			grafp1_reg <= (others=>'0');
+			grafp2_reg <= (others=>'0');
+			grafp3_reg <= (others=>'0');
+
+			grafm_reg <= (others=>'0');
+			
+			colpm0_raw_reg <= (others=>'0');
+			colpm1_raw_reg <= (others=>'0');
+			colpm2_raw_reg <= (others=>'0');
+			colpm3_raw_reg <= (others=>'0');
+
+			colpf0_raw_reg <= (others=>'0');
+			colpf1_raw_reg <= (others=>'0');
+			colpf2_raw_reg <= (others=>'0');
+			colpf3_raw_reg <= (others=>'0');
+			
+			colbk_raw_reg <= (others=>'0');
+			
+			prior_raw_reg <= (others=>'0');
+			
+			vdelay_reg <= (others=>'0');
+			
+			gractl_reg <= (others=>'0');
+			
+			consol_output_reg <= (others=>'1');
+			
+			COLOUR_REG <= (OTHERS=>'0');
+			HRCOLOUR_REG <= (OTHERS=>'0');
+			
+			vsync_reg <= '0';
+			hsync_reg <= '0';
+			hblank_reg <= '0';
+			
+			an_prev_reg <= (others=>'0');
+			an_prev2_reg <= (others=>'0');
+			an_prev3_reg <= (others=>'0');
+			
+			highres_reg <= '0';
+			active_hr_reg <= (others=>'0');
+			
+			trig0_reg <= '0';
+			trig1_reg <= '0';
+			trig2_reg <= '0';
+			trig3_reg <= '0';
+			
+			odd_scanline_reg <= '0';
+			
+			pmg_dma_state_reg <= pmg_dma_done;
+			
+			m0pf_reg <= (others=>'0');
+			m1pf_reg <= (others=>'0');
+			m2pf_reg <= (others=>'0');
+			m3pf_reg <= (others=>'0');
+			m0pl_reg <= (others=>'0');
+			m1pl_reg <= (others=>'0');
+			m2pl_reg <= (others=>'0');
+			m3pl_reg <= (others=>'0');
+			
+			p0pf_reg <= (others=>'0');
+			p1pf_reg <= (others=>'0');
+			p2pf_reg <= (others=>'0');
+			p3pf_reg <= (others=>'0');
+			p0pl_reg <= (others=>'0');
+			p1pl_reg <= (others=>'0');
+			p2pl_reg <= (others=>'0');
+			p3pl_reg <= (others=>'0');	
+			
+			active_bk_modify_reg <= (others=>'0');
+			active_bk_valid_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then										
+			hposp0_raw_reg <= hposp0_raw_next;
+			hposp1_raw_reg <= hposp1_raw_next;
+			hposp2_raw_reg <= hposp2_raw_next;
+			hposp3_raw_reg <= hposp3_raw_next;
+
+			hposm0_raw_reg <= hposm0_raw_next;
+			hposm1_raw_reg <= hposm1_raw_next;
+			hposm2_raw_reg <= hposm2_raw_next;
+			hposm3_raw_reg <= hposm3_raw_next;			
+
+			sizep0_raw_reg <= sizep0_raw_next;
+			sizep1_raw_reg <= sizep1_raw_next;
+			sizep2_raw_reg <= sizep2_raw_next;
+			sizep3_raw_reg <= sizep3_raw_next;
+
+			sizem_raw_reg <= sizem_raw_next;
+			
+			grafp0_reg <= grafp0_next;
+			grafp1_reg <= grafp1_next;
+			grafp2_reg <= grafp2_next;
+			grafp3_reg <= grafp3_next;
+
+			grafm_reg <= grafm_next;
+			
+			colpm0_raw_reg <= colpm0_raw_next;
+			colpm1_raw_reg <= colpm1_raw_next;
+			colpm2_raw_reg <= colpm2_raw_next;
+			colpm3_raw_reg <= colpm3_raw_next;
+
+			colpf0_raw_reg <= colpf0_raw_next;
+			colpf1_raw_reg <= colpf1_raw_next;
+			colpf2_raw_reg <= colpf2_raw_next;
+			colpf3_raw_reg <= colpf3_raw_next;
+			
+			colbk_raw_reg <= colbk_raw_next;
+			
+			prior_raw_reg <= prior_raw_next;
+			
+			vdelay_reg <= vdelay_next;
+			
+			gractl_reg <= gractl_next;
+			
+			consol_output_reg <= consol_output_next;		
+
+			COLOUR_REG <= colour_next;
+			HRCOLOUR_REG <= hrcolour_next;
+			
+			vsync_reg <= vsync_next;
+			hsync_reg <= hsync_next;
+			hblank_reg <= hblank_next;
+			
+			an_prev_reg <= an_prev_next;
+			an_prev2_reg <= an_prev2_next;
+			an_prev3_reg <= an_prev3_next;
+	
+			highres_reg <= highres_next;
+			active_hr_reg <= active_hr_next;
+			
+			trig0_reg <= trig0_next;
+			trig1_reg <= trig1_next;
+			trig2_reg <= trig2_next;
+			trig3_reg <= trig3_next;
+			
+			odd_scanline_reg <= odd_scanline_next;
+			
+			pmg_dma_state_reg <= pmg_dma_state_next;
+			
+			m0pf_reg <= m0pf_next;
+			m1pf_reg <= m1pf_next;
+			m2pf_reg <= m2pf_next;
+			m3pf_reg <= m3pf_next;
+			m0pl_reg <= m0pl_next;
+			m1pl_reg <= m1pl_next;
+			m2pl_reg <= m2pl_next;
+			m3pl_reg <= m3pl_next;
+			
+			p0pf_reg <= p0pf_next;
+			p1pf_reg <= p1pf_next;
+			p2pf_reg <= p2pf_next;
+			p3pf_reg <= p3pf_next;
+			p0pl_reg <= p0pl_next;
+			p1pl_reg <= p1pl_next;
+			p2pl_reg <= p2pl_next;
+			p3pl_reg <= p3pl_next;
+			
+			active_bk_modify_reg <= active_bk_modify_next;
+			active_bk_valid_reg <= active_bk_valid_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>5)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+		
+	-- decode antic input
+	process (AN, COLOUR_CLOCK, COLOUR_CLOCK_ORIGINAL, an_prev_reg, an_prev2_reg, an_prev3_reg, hblank_reg, vsync_reg, highres_reg, odd_scanline_reg, prior_delayed_reg, prior_delayed2_reg, hpos_reg, active_p0_live, active_p1_live, active_p2_live, active_p3_live, active_m0_live, active_m1_live, active_m2_live, active_m3_live, active_pf3_collision_live, active_bk_modify_reg, active_bk_modify_next, active_bk_valid_reg, active_hr_reg, visible_live)
+	begin	
+		hblank_next <= hblank_reg;
+		reset_counter <= '0';
+		counter_load_value <= (others=>'0');
+		vsync_next <= vsync_reg;
+		
+		odd_scanline_next <= odd_scanline_reg;
+			
+		-- NB high res mode gives pf2 - which is or of the two pixels
+		highres_next <= highres_reg;
+		
+		-- for gtia modes
+		an_prev_next <= an_prev_reg;
+		an_prev2_next <= an_prev2_reg;
+		an_prev3_next <= an_prev3_reg;
+		
+		-- decoded AN
+		visible_live <= '0';
+		
+		active_hr_next <= active_hr_reg;
+		
+		active_bk_modify_next <= active_bk_modify_reg;
+		active_bk_valid_next <= active_bk_valid_reg;
+		active_bk_live <= '0';
+		active_pf0_live <= '0';
+		active_pf1_live <= '0';
+		active_pf2_live <= '0';
+		active_pf2_collision_live <= '0';
+		active_pf3_live <= '0';
+		active_pf3_collision_live <= '0';
+		active_pm0_live <= '0';
+		active_pm1_live <= '0';
+		active_pm2_live <= '0';
+		active_pm3_live <= '0';
+		
+		if (COLOUR_CLOCK = '1') then	
+			visible_live <= '1';
+			vsync_next <= '0';
+			hblank_next <= '0';
+			an_prev_next <= an;
+			an_prev2_next <= an_prev_reg;
+			an_prev3_next <= an_prev2_reg;
+			
+			active_pm0_live <= active_p0_live or (active_m0_live and not(prior_delayed_reg(4)));
+			active_pm1_live <= active_p1_live or (active_m1_live and not(prior_delayed_reg(4)));
+			active_pm2_live <= active_p2_live or (active_m2_live and not(prior_delayed_reg(4)));
+			active_pm3_live <= active_p3_live or (active_m3_live and not(prior_delayed_reg(4)));			
+			
+			active_bk_modify_next <= (others=>'0');
+			active_bk_valid_next <= (others=>'1');
+			
+			active_hr_next <= (others=>'0');
+		
+			-- 000 background colour
+			-- 001 vsync
+			-- 01X hsync (low bit is high res mode - i.e. 2 pixels per colour clock)
+			-- 1XX colour 0 to colour 3
+			
+			-- in gtia modes then we listen for 2 colour clocks to get one pixels
+			-- 1ZY (giving signal ZYXV for 4 bit colour reg/luminance - unfortunately we only have 9 colour regs!)
+			-- 1XV
+			
+			if (highres_reg = '1') then
+				if (an(2) = '1') then
+					active_hr_next <= AN(1 downto 0);				
+				end if;
+				
+				active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= an(2);
+				active_pf2_collision_live <= an(2) and (an(1) or an(0));
+				active_pf3_collision_live <= '0';				
+			else								
+				-- gtia modes										
+				case prior_delayed_reg(7 downto 6) is
+					when "00" => 
+						-- normal mode
+						active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+						active_pf0_live <= an(2) and not(an(1)) and not(an(0));
+						active_pf1_live <= an(2) and not(an(1)) and an(0);
+						active_pf2_live <= an(2) and      an(1) and not(an(0));
+						active_pf2_collision_live <= an(2) and      an(1) and not(an(0));
+						active_pf3_collision_live <= an(2) and      an(1) and an(0);
+					when "01" =>
+						-- 1 colour/16 luminance
+						-- no playfield collisions
+						-- 5th player gets my luminance
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';						
+						active_bk_live <= '1';
+						
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(3 downto 0) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(3 downto 0) <= active_bk_modify_reg(3 downto 0);
+						end if;
+					when "10" => 
+						-- 9 colour
+						-- playfield collisions
+						-- no missile/player collisions from 'playfield' data though		
+						-- offset by 1 colour clock...
+						if (hpos_reg(0) = '1') then
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev_reg(1 downto 0)&an(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an(2);
+									active_pf2_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;
+						else
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev2_reg(1 downto 0)&an_prev_reg(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an_prev_reg(2);
+									active_pf2_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;									
+						end if;
+						
+					when "11" =>
+						-- 16 colour/1 luminance
+						-- no playfield collisions
+						-- 5th player gets our luminance
+						active_bk_live <= '1';
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';	
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(7 downto 4) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(7 downto 4) <= active_bk_modify_reg(7 downto 4);
+						end if;
+						
+						if (active_bk_modify_next(7 downto 4) = "0000") then
+							active_bk_valid_next(3 downto 0) <= "0000";
+						end if;
+				end case;
+			end if;
+			
+			if (prior_delayed_reg(4) = '1') then
+				active_pf3_live <= active_pf3_collision_live or active_m0_live or active_m1_live or active_m2_live or active_m3_live;
+			else
+				active_pf3_live <= active_pf3_collision_live;
+			end if;
+			
+			if (not (prior_delayed2_reg(7 downto 6) = "00")) then
+				-- force off flip flop when in gtia mode
+				highres_next <= '0';
+			end if;
+			
+			-- hblank
+			if (an_prev_reg(2 downto 1) = "01") then
+				hblank_next <= '1';
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				highres_next <= an_prev_reg(0);
+			
+				if (COLOUR_CLOCK_ORIGINAL='1') then				
+					if (hblank_reg = '0' and vsync_reg = '0') then
+						reset_counter <= '1';
+						counter_load_value <= X"E0"; -- 2 lower than antic
+						odd_scanline_next <= not(odd_scanline_reg);
+					end if;
+				end if;
+			end if;
+			if (an(2 downto 1) = "01") then
+				visible_live <= '0';
+			end if;			
+	
+			-- vsync
+			if (an_prev_reg = "001") then
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				
+				vsync_next <= '1';
+
+				odd_scanline_next <= '0';
+				
+				visible_live <= '0';
+			end if;
+			
+			-- during vblank we reset our own counter - since Antic does not clear hblank_reg
+			if (hpos_reg = X"E3" and COLOUR_CLOCK_ORIGINAL='1') then
+				reset_counter <= '1';
+				counter_load_value <= X"00";
+			end if;
+
+		end if;
+	end process;
+	
+	-- hpos
+	counter_hpos : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>COLOUR_CLOCK_ORIGINAL, load=>reset_counter, load_value=>counter_load_value, current_value=>hpos_reg);
+	
+	-- visible region
+--	process(hpos_reg,vpos_reg)
+--	begin		
+--		visible_live <= '1';
+--		
+----		if (unsigned(vpos_reg) < to_unsigned(8,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(vpos_reg) > to_unsigned(247,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) <= to_unsigned(34,8)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) > to_unsigned(221,8)) then
+----			visible_live <= '0';
+----		end if;		
+--	end process;
+	
+	-- generate hsync
+	process(hpos_reg, hsync_reg, hsync_end, vsync_reg, vsync_next)
+	begin
+		hsync_start <= '0';
+		hsync_next <= hsync_reg;
+
+		if (unsigned(hpos_reg) = X"D4" and vsync_reg = '1') then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+	
+		if (unsigned(hpos_reg) = X"0" and vsync_reg = '0' ) then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+			
+		if (hsync_end = '1') then
+			hsync_next <= '0';
+		end if;
+		
+		if (vsync_next = '0' and vsync_reg = '1') then
+			hsync_next <= '0';
+		end if;
+	end process;
+
+	hsync_delay : delay_line
+		generic map (COUNT=>15)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hsync_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hsync_end);	
+
+	-- pmg dma
+	MEMORY_READY <= CPU_MEMORY_READY or ANTIC_MEMORY_READY; -- TODO, REVIEW timing vs CPU/ANTIC - simpler may be possible now
+	process(antic_fetch,CPU_ENABLE_ORIGINAL,memory_ready,memory_data_in,hsync_start,pmg_dma_state_reg,gractl_reg,odd_scanline_reg,vdelay_reg,grafm_reg, visible_live,hpos_reg, hblank_reg)
+	begin
+		pmg_dma_state_next <= pmg_dma_state_reg;
+		grafm_dma_load <= '0';
+		grafm_dma_next <= grafm_reg;		
+		grafp0_dma_load <= '0';
+		grafp0_dma_next <= (others=>'0');
+		grafp1_dma_load <= '0';
+		grafp1_dma_next <= (others=>'0');
+		grafp2_dma_load <= '0';
+		grafp2_dma_next <= (others=>'0');
+		grafp3_dma_load <= '0';
+		grafp3_dma_next <= (others=>'0');
+	
+		-- pull pmg data from bus
+		if (hpos_reg = X"E1") then
+			pmg_dma_state_next <= pmg_dma_missile;
+		end if;
+		
+		-- we start from the first antic refresh cycle
+		-- TODO - CPU enable does not identify next 'antic' cycle in turbo mode...
+		case pmg_dma_state_reg is
+			when pmg_dma_missile =>
+				if (antic_fetch = '1' and memory_ready = '1' and hblank_reg = '1' and visible_live = '0' and hpos_reg(7 downto 4) = "0000") then
+					-- here we have the missile0					
+					grafm_dma_load <= gractl_reg(0);
+				
+					if ((odd_scanline_reg or not(vdelay_reg(0))) = '1') then
+						grafm_dma_next(1 downto 0) <= memory_data_in(1 downto 0);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(1))) = '1') then
+						grafm_dma_next(3 downto 2) <= memory_data_in(3 downto 2);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(2))) = '1') then
+						grafm_dma_next(5 downto 4) <= memory_data_in(5 downto 4);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(3))) = '1') then
+						grafm_dma_next(7 downto 6) <= memory_data_in(7 downto 6);
+					end if;
+					
+					pmg_dma_state_next <= pmg_dma_instruction;
+				end if;
+			when pmg_dma_instruction =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					pmg_dma_state_next <= pmg_dma_player0;
+				end if;			
+			when pmg_dma_player0 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player0
+					grafp0_dma_next <= memory_data_in;				
+					grafp0_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(4)));
+					pmg_dma_state_next <= pmg_dma_player1;
+				end if;
+			when pmg_dma_player1 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp1_dma_next <= memory_data_in;
+					grafp1_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(5)));
+					pmg_dma_state_next <= pmg_dma_player2;
+				end if;
+			when pmg_dma_player2 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp2_dma_next <= memory_data_in;
+					grafp2_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(6)));
+					pmg_dma_state_next <= pmg_dma_player3;
+				end if;				
+			when pmg_dma_player3 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp3_dma_next <= memory_data_in;				
+					grafp3_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(7)));
+					pmg_dma_state_next <= pmg_dma_done;
+				end if;
+			when others =>
+				-- nop
+		end case;
+	end process;
+		
+	-- pmg display - same for all pmgs
+	-- TODO: priority
+	player0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp0_delayed_reg,size=>sizep0_delayed_reg(1 downto 0),bitmap=>grafp0_reg, output=>active_p0_live);	
+	player1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp1_delayed_reg,size=>sizep1_delayed_reg(1 downto 0),bitmap=>grafp1_reg, output=>active_p1_live);	
+	player2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp2_delayed_reg,size=>sizep2_delayed_reg(1 downto 0),bitmap=>grafp2_reg, output=>active_p2_live);	
+	player3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);				
+
+	missile0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg(1 downto 0)&"000000", output=>active_m0_live);
+	missile1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg(3 downto 2)&"000000", output=>active_m1_live);
+	missile2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg(5 downto 4)&"000000", output=>active_m2_live);
+	missile3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg(7 downto 6)&"000000", output=>active_m3_live);
+		
+	-- calculate atari colour
+	priority_rules : gtia_priority
+		port map(clk=>clk, colour_enable=>colour_clock, prior=>prior_delayed_reg,p0=>active_pm0_live,p1=>active_pm1_live,p2=>active_pm2_live,p3=>active_pm3_live,pf0=>active_pf0_live,pf1=>active_pf1_live,pf2=>active_pf2_live,pf3=>active_pf3_live,bk=>active_bk_live,p0_out=>set_p0,p1_out=>set_p1,p2_out=>set_p2,p3_out=>set_p3,pf0_out=>set_pf0,pf1_out=>set_pf1,pf2_out=>set_pf2,pf3_out=>set_pf3,bk_out=>set_bk);	
+
+	trigger_secondhalf <= colour_clock_HIGHRES and not colour_clock;
+	process(set_p0,set_p1,set_p2,set_p3,set_pf0,set_pf1,set_pf2,set_pf3,set_bk,highres_reg, active_hr_reg, colbk_delayed_reg, colpf0_delayed_reg, colpf1_delayed_reg, colpf2_delayed_reg, colpf3_delayed_reg, colpm0_delayed_reg, colpm1_delayed_reg, colpm2_delayed_reg, colpm3_delayed_reg, trigger_secondhalf, colour_clock, COLOUR_REG, hrcolour_reg, visible_live, active_bk_modify_next, active_bk_valid_next)
+	begin
+		colour_next <= colour_reg;
+		hrcolour_next <= hrcolour_reg;
+		
+		if (trigger_secondhalf = '1') then
+			if (highres_reg = '1') then
+				colour_next <= hrcolour_reg;
+			end if;
+		end if;		
+		
+		if (colour_clock = '1') then 
+			colour_next <= 
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+			hrcolour_next <= -- SAME FIXME
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+						
+			-- finally high-res mode overrides the luma
+			if (set_bk = '0' and highres_reg = '1') then
+			
+				if (active_hr_reg(1) = '1') then
+					colour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';						
+				end if;
+				
+				if (active_hr_reg(0) = '1') then						
+					hrcolour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
+				end if;
+			end if;				
+			
+			if (visible_live = '0') then
+				colour_next <= X"00";
+				hrcolour_next <= X"00";
+			end if;			
+		end if;
+	end process;
+
+	-- collision detection
+	process (colour_clock, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg,hitclr_write,active_pf0_live,active_pf1_live,active_pf2_collision_live,active_pf3_collision_live,active_p0_live,active_p1_live,active_p2_live,active_p3_live,active_m0_live,active_m1_live,active_m2_live,active_m3_live, visible_live)
+	begin
+		m0pf_next <= m0pf_reg;
+		m1pf_next <= m1pf_reg;
+		m2pf_next <= m2pf_reg;
+		m3pf_next <= m3pf_reg;
+		m0pl_next <= m0pl_reg;
+		m1pl_next <= m1pl_reg;
+		m2pl_next <= m2pl_reg;
+		m3pl_next <= m3pl_reg;
+		
+		p0pf_next <= p0pf_reg;
+		p1pf_next <= p1pf_reg;
+		p2pf_next <= p2pf_reg;
+		p3pf_next <= p3pf_reg;
+		p0pl_next <= p0pl_reg;
+		p1pl_next <= p1pl_reg;
+		p2pl_next <= p2pl_reg;
+		p3pl_next <= p3pl_reg;	
+		
+		if (hitclr_write = '1') then
+			m0pf_next <= (others=>'0');
+			m1pf_next <= (others=>'0');
+			m2pf_next <= (others=>'0');
+			m3pf_next <= (others=>'0');
+			m0pl_next <= (others=>'0');
+			m1pl_next <= (others=>'0');
+			m2pl_next <= (others=>'0');
+			m3pl_next <= (others=>'0');
+			
+			p0pf_next <= (others=>'0');
+			p1pf_next <= (others=>'0');
+			p2pf_next <= (others=>'0');
+			p3pf_next <= (others=>'0');
+			p0pl_next <= (others=>'0');
+			p1pl_next <= (others=>'0');
+			p2pl_next <= (others=>'0');
+			p3pl_next <= (others=>'0');
+		else
+			if (visible_live = '1' and colour_clock = '1') then
+				m0pl_next <= m0pl_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m1pl_next <= m1pl_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m2pl_next <= m2pl_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m3pl_next <= m3pl_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+
+				m0pf_next <= m0pf_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m1pf_next <= m1pf_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m2pf_next <= m2pf_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m3pf_next <= m3pf_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				
+				p0pl_next <= p0pl_reg or (active_p0_live&active_p0_live&active_p0_live&'0'        and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p1pl_next <= p1pl_reg or (active_p1_live&active_p1_live&'0'       &active_p1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p2pl_next <= p2pl_reg or (active_p2_live&'0'       &active_p2_live&active_p2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p3pl_next <= p3pl_reg or ('0'       &active_p3_live&active_p3_live&active_p3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);	
+				
+				p0pf_next <= p0pf_reg or (active_p0_live&active_p0_live&active_p0_live&active_p0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p1pf_next <= p1pf_reg or (active_p1_live&active_p1_live&active_p1_live&active_p1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p2pf_next <= p2pf_reg or (active_p2_live&active_p2_live&active_p2_live&active_p2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p3pf_next <= p3pf_reg or (active_p3_live&active_p3_live&active_p3_live&active_p3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);			
+			end if;
+		end if;
+		
+	end process;
+
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,hposp0_raw_reg,hposp1_raw_reg,hposp2_raw_reg,hposp3_raw_reg,hposm0_raw_reg,hposm1_raw_reg,hposm2_raw_reg,hposm3_raw_reg,sizep0_raw_reg,sizep1_raw_reg,sizep2_raw_reg,sizep3_raw_reg,sizem_raw_reg,grafp0_reg,grafp1_reg,grafp2_reg,grafp3_reg, grafm_reg, colpm0_raw_reg, colpm1_raw_reg, colpm2_raw_reg, colpm3_raw_reg, colpf0_raw_reg, colpf1_raw_reg,colpf2_raw_reg, colpf3_raw_reg, colbk_raw_reg, prior_raw_reg, vdelay_reg, gractl_reg, consol_output_reg, grafm_dma_load, grafm_dma_next, grafp0_dma_load, grafp0_dma_next, grafp1_dma_load, grafp1_dma_next, grafp2_dma_load, grafp2_dma_next, grafp3_dma_load, grafp3_dma_next)
+	begin
+		hposp0_raw_next <= hposp0_raw_reg;
+		hposp1_raw_next <= hposp1_raw_reg;
+		hposp2_raw_next <= hposp2_raw_reg;
+		hposp3_raw_next <= hposp3_raw_reg;
+
+		hposm0_raw_next <= hposm0_raw_reg;
+		hposm1_raw_next <= hposm1_raw_reg;
+		hposm2_raw_next <= hposm2_raw_reg;
+		hposm3_raw_next <= hposm3_raw_reg;			
+
+		sizep0_raw_next <= sizep0_raw_reg;
+		sizep1_raw_next <= sizep1_raw_reg;
+		sizep2_raw_next <= sizep2_raw_reg;
+		sizep3_raw_next <= sizep3_raw_reg;
+
+		sizem_raw_next <= sizem_raw_reg;
+		
+		grafp0_next <= grafp0_reg;
+		grafp1_next <= grafp1_reg;
+		grafp2_next <= grafp2_reg;
+		grafp3_next <= grafp3_reg;
+
+		grafm_next <= grafm_reg;
+		
+		colpm0_raw_next <= colpm0_raw_reg;
+		colpm1_raw_next <= colpm1_raw_reg;
+		colpm2_raw_next <= colpm2_raw_reg;
+		colpm3_raw_next <= colpm3_raw_reg;
+
+		colpf0_raw_next <= colpf0_raw_reg;
+		colpf1_raw_next <= colpf1_raw_reg;
+		colpf2_raw_next <= colpf2_raw_reg;
+		colpf3_raw_next <= colpf3_raw_reg;
+		
+		colbk_raw_next <= colbk_raw_reg;
+		
+		prior_raw_next <= prior_raw_reg;
+		
+		vdelay_next <= vdelay_reg;
+		
+		gractl_next <= gractl_reg;
+		
+		consol_output_next <= consol_output_reg;	
+		
+		hitclr_write <= '0';
+		
+		if (grafm_dma_load = '1') then
+			grafm_next <= grafm_dma_next;
+		end if;
+
+		if (grafp0_dma_load = '1') then
+			grafp0_next <= grafp0_dma_next;
+		end if;
+
+		if (grafp1_dma_load = '1') then
+			grafp1_next <= grafp1_dma_next;
+		end if;
+
+		if (grafp2_dma_load = '1') then
+			grafp2_next <= grafp2_dma_next;
+		end if;
+
+		if (grafp3_dma_load = '1') then
+			grafp3_next <= grafp3_dma_next;
+		end if;
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				hposp0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				hposp1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(2) = '1') then
+				hposp2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				hposp3_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(4) = '1') then
+				hposm0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				hposm1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(6) = '1') then
+				hposm2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(7) = '1') then
+				hposm3_raw_next <= cpu_data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				sizep0_raw_next <= cpu_data_in(1 downto 0);
+			end if;	
+
+			if(addr_decoded(9) = '1') then
+				sizep1_raw_next <= cpu_data_in(1 downto 0);
+			end if;		
+			
+			if(addr_decoded(10) = '1') then
+				sizep2_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+
+			if(addr_decoded(11) = '1') then
+				sizep3_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+			
+			if(addr_decoded(12) = '1') then
+				sizem_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(13) = '1') then
+				grafp0_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(14) = '1') then
+				grafp1_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(15) = '1') then
+				grafp2_next <= cpu_data_in;
+			end if;			
+			
+			if(addr_decoded(16) = '1') then
+				grafp3_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(17) = '1') then
+				grafm_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(18) = '1') then
+				colpm0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(19) = '1') then
+				colpm1_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(20) = '1') then
+				colpm2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(21) = '1') then
+				colpm3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(22) = '1') then
+				colpf0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(23) = '1') then
+				colpf1_raw_next <= cpu_data_in(7 downto 1);
+			end if;									
+
+			if(addr_decoded(24) = '1') then
+				colpf2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(25) = '1') then
+				colpf3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(26) = '1') then
+				colbk_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(27) = '1') then
+				prior_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(28) = '1') then
+				vdelay_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(29) = '1') then
+				gractl_next <= cpu_data_in(2 downto 0);
+			end if;		
+			
+			if(addr_decoded(30) = '1') then
+				-- clear the collision regs
+				hitclr_write <= '1';
+			end if;
+
+			if(addr_decoded(31) = '1') then
+				consol_output_next <= cpu_data_in(3 downto 0);
+			end if;				
+			
+		end if;
+	end process;
+	
+	-- delays...
+		-- TODO - needs more attention ... 
+		-- The prior behaviour here in real hardware is all over the place...
+		-- THESE CAN TAKE MUCH LESS SPACE - only need to store per CPU cycle, not per colour clock original
+	prior_short_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>6)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(5 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(5 downto 0));
+
+	prior_long_delay : wide_delay_line
+		generic map (COUNT=>3, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(7 downto 6));
+
+	prior_longer_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed2_reg(7 downto 6));		
+		
+	colbk_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colbk_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colbk_delayed_reg(7 downto 1));	
+
+	colpm0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm0_delayed_reg(7 downto 1));		
+	colpm1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm1_delayed_reg(7 downto 1));		
+	colpm2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm2_delayed_reg(7 downto 1));		
+	colpm3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm3_delayed_reg(7 downto 1));		
+
+	colpf0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf0_delayed_reg(7 downto 1));		
+	colpf1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf1_delayed_reg(7 downto 1));		
+	colpf2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf2_delayed_reg(7 downto 1));		
+	colpf3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf3_delayed_reg(7 downto 1));				
+
+	hposp0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp0_delayed_reg(7 downto 0));		
+	hposp1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp1_delayed_reg(7 downto 0));		
+	hposp2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp2_delayed_reg(7 downto 0));		
+	hposp3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp3_delayed_reg(7 downto 0));				
+
+	hposm0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm0_delayed_reg(7 downto 0));		
+	hposm1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm1_delayed_reg(7 downto 0));		
+	hposm2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm2_delayed_reg(7 downto 0));		
+	hposm3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm3_delayed_reg(7 downto 0));				
+		
+	sizep0_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep0_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep0_delayed_reg(1 downto 0));		
+	sizep1_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep1_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep1_delayed_reg(1 downto 0));		
+	sizep2_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep2_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep2_delayed_reg(1 downto 0));		
+	sizep3_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep3_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep3_delayed_reg(1 downto 0));		
+	sizem_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizem_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizem_delayed_reg(7 downto 0));				
+		
+	-- joystick
+	process(trig0_reg, trig1_reg, trig2_reg, trig3_reg, trig0, trig1, trig2, trig3, gractl_reg)
+	begin	
+		trig0_next <= trig0;
+		trig1_next <= trig1;
+		trig2_next <= trig2;
+		trig3_next <= trig3;
+		
+		if (gractl_reg(2) = '1') then
+			trig0_next <= trig0_reg and trig0;
+			trig1_next <= trig1_reg and trig1;
+			trig2_next <= trig2_reg and trig2;
+			trig3_next <= trig3_reg and trig3;
+		end if;
+	end process;
+	
+	-- Read from registers		
+	process(addr_decoded, CONSOL_OPTION, CONSOL_SELECT, CONSOL_START, consol_output_reg, trig0_reg, trig1_reg, trig2_reg, trig3_reg, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg, pal)
+	begin
+		data_out <= X"0F";
+
+		if (addr_decoded(0) = '1') then
+			data_out <= "0000"&m0pf_reg;
+		end if;
+
+		if (addr_decoded(1) = '1') then
+			data_out <= "0000"&m1pf_reg;
+		end if;
+		
+		if (addr_decoded(2) = '1') then
+			data_out <= "0000"&m2pf_reg;
+		end if;
+
+		if (addr_decoded(3) = '1') then
+			data_out <= "0000"&m3pf_reg;
+		end if;
+
+		if (addr_decoded(4) = '1') then
+			data_out <= "0000"&p0pf_reg;
+		end if;
+
+		if (addr_decoded(5) = '1') then
+			data_out <= "0000"&p1pf_reg;
+		end if;
+		
+		if (addr_decoded(6) = '1') then
+			data_out <= "0000"&p2pf_reg;
+		end if;
+
+		if (addr_decoded(7) = '1') then
+			data_out <= "0000"&p3pf_reg;
+		end if;
+		
+		if (addr_decoded(8) = '1') then
+			data_out <= "0000"&m0pl_reg;
+		end if;
+
+		if (addr_decoded(9) = '1') then
+			data_out <= "0000"&m1pl_reg;
+		end if;
+		
+		if (addr_decoded(10) = '1') then
+			data_out <= "0000"&m2pl_reg;
+		end if;
+
+		if (addr_decoded(11) = '1') then
+			data_out <= "0000"&m3pl_reg;
+		end if;		
+
+		if (addr_decoded(12) = '1') then
+			data_out <= "0000"&p0pl_reg;
+		end if;
+
+		if (addr_decoded(13) = '1') then
+			data_out <= "0000"&p1pl_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then
+			data_out <= "0000"&p2pl_reg;
+		end if;
+
+		if (addr_decoded(15) = '1') then
+			data_out <= "0000"&p3pl_reg;
+		end if;		
+		
+		if (addr_decoded(16) = '1') then
+			data_out <= "0000000"&trig0_reg;
+		end if;
+
+		if (addr_decoded(17) = '1') then
+			data_out <= "0000000"&trig1_reg;
+		end if;
+
+		if (addr_decoded(18) = '1') then
+			data_out <= "0000000"&trig2_reg;
+		end if;
+		
+		if (addr_decoded(19) = '1') then
+			data_out <= "0000000"&trig3_reg;
+		end if;
+		
+		if (addr_decoded(20) = '1') then
+			data_out <= "00000"&not(pal&pal&pal);
+		end if;
+
+		if (addr_decoded(31) = '1') then
+			data_out <= "0000"&('0'&not(CONSOL_OPTION)&not(CONSOL_SELECT)&not(CONSOL_START) and (not consol_output_reg));
+		end if;
+		
+	end process;
+	
+	-- output	
+	colour_out <= colour_reg;
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+	
+	sound <= consol_output_reg(3);
+
+end vhdl;
+
+
Index: unmerged/core/de1/hexdecoder.vhd
===================================================================
--- unmerged/core/de1/hexdecoder.vhd	(nonexistent)
+++ unmerged/core/de1/hexdecoder.vhd	(revision 1)
@@ -0,0 +1,75 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY hexdecoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+);
+END hexdecoder;
+
+ARCHITECTURE vhdl OF hexdecoder IS
+	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
+	signal digit_next : std_logic_vector(6 downto 0);
+	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
+BEGIN
+	--numinv <= not(NUMBER);
+	numinv <= NUMBER;
+	process(numinv)
+	begin
+		case numinv is
+			when "0000" =>
+				digit_next <= "1111111";
+			when "0001" =>
+				digit_next <= "1111001";
+			when "0010" =>
+				digit_next <= "0100100";
+			when "0011" =>
+				digit_next <= "0110000";
+			when "0100" =>
+				digit_next <= "0011001";
+			when "0101" =>
+				digit_next <= "0010010";
+			when "0110" =>
+				digit_next <= "0000010";
+			when "0111" =>
+				digit_next <= "1111000";
+			when "1000" =>
+				digit_next <= "0000000";
+			when "1001" =>
+				digit_next <= "0011000";
+			when "1010" =>
+				digit_next <= "0001000";
+			when "1011" =>
+				digit_next <= "0000011";
+			when "1100" =>
+				digit_next <= "1000110";
+			when "1101" =>
+				digit_next <= "0100001";
+			when "1110" =>
+				digit_next <= "0000110";
+			when "1111" =>
+				digit_next <= "0001110";
+			when others =>
+				digit_next <= "1111111";
+		end case;
+	end process;
+	
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	digit<=digit_reg;
+END vhdl;
\ No newline at end of file
Index: unmerged/core/de1/ledsw.vhd
===================================================================
--- unmerged/core/de1/ledsw.vhd	(nonexistent)
+++ unmerged/core/de1/ledsw.vhd	(revision 1)
@@ -0,0 +1,70 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+-- Simple module that connects the SW switches to the LEDR lights
+ENTITY ledsw IS
+PORT ( 
+	CLK : IN STD_LOGIC;
+
+	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	SYNC_KEYS : out std_logic_vector(3 downto 0);
+	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
+); 
+END ledsw;
+
+ARCHITECTURE Behavior OF ledsw IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+		
+	signal sw_reg : std_logic_vector(9 downto 0);
+	signal key_reg : std_logic_vector(3 downto 0);
+	
+BEGIN
+	sw9_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
+	sw8_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
+	sw7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
+	sw6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
+	sw5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
+	sw4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
+	sw3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
+	sw2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
+	sw1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
+	sw0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
+
+	key3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
+	key2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
+	key1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
+	key0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
+	
+	-- outputs
+	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
+	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
+END Behavior;
Index: unmerged/core/de1/pll.qip
===================================================================
--- unmerged/core/de1/pll.qip	(nonexistent)
+++ unmerged/core/de1/pll.qip	(revision 1)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: unmerged/core/de1/gtia_priority.vhdl
===================================================================
--- unmerged/core/de1/gtia_priority.vhdl	(nonexistent)
+++ unmerged/core/de1/gtia_priority.vhdl	(revision 1)
@@ -0,0 +1,175 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_priority IS
+PORT 
+( 
+	CLK : in std_logic;
+	colour_enable : in std_logic;
+
+	PRIOR : in std_logic_vector(7 downto 0);
+	P0 : in std_logic;
+	P1 : in std_logic;
+	P2	: in std_logic;
+	P3 : in std_logic;
+	PF0 : in std_logic;
+	PF1 : in std_logic;
+	PF2 : in std_logic;
+	PF3 : in std_logic;
+	BK : in std_logic;
+	
+	P0_OUT : out std_logic;
+	P1_OUT : out std_logic;
+	P2_OUT : out std_logic;
+	P3_OUT : out std_logic;
+	PF0_OUT : out std_logic;
+	PF1_OUT : out std_logic;
+	PF2_OUT : out std_logic;
+	PF3_OUT : out std_logic;
+	BK_OUT : out std_logic
+);
+END gtia_priority;
+
+ARCHITECTURE vhdl OF gtia_priority IS
+	signal P01 : std_logic;
+	signal P23 : std_logic;
+	
+	signal PF01 : std_logic;
+	signal PF23 : std_logic;
+	
+	signal PRI01 : std_logic;
+	signal PRI12 : std_logic;
+	signal PRI23 : std_logic;
+	signal PRI03 : std_logic;
+	
+	signal PRI0 : std_logic;
+	signal PRI1 : std_logic;
+	signal PRI2 : std_logic;
+	signal PRI3 : std_logic;
+	signal MULTI : std_logic;
+	
+	signal SP0 : std_logic;
+	signal SP1 : std_logic;
+	signal SP2 : std_logic;
+	signal SP3 : std_logic;	
+	signal SF0 : std_logic;
+	signal SF1 : std_logic;
+	signal SF2 : std_logic;
+	signal SF3 : std_logic;	
+	signal SB : std_logic;
+	
+	signal SP0_next : std_logic;
+	signal SP1_next : std_logic;
+	signal SP2_next : std_logic;
+	signal SP3_next : std_logic;	
+	signal SF0_next : std_logic;
+	signal SF1_next : std_logic;
+	signal SF2_next : std_logic;
+	signal SF3_next : std_logic;	
+	signal SB_next : std_logic;
+
+	signal SP0_reg : std_logic;
+	signal SP1_reg : std_logic;
+	signal SP2_reg : std_logic;
+	signal SP3_reg : std_logic;	
+	signal SF0_reg : std_logic;
+	signal SF1_reg : std_logic;
+	signal SF2_reg : std_logic;
+	signal SF3_reg : std_logic;	
+	signal SB_reg : std_logic;
+begin
+	-- Use actual GTIA logic...
+	P01 <= P0 or P1;
+	P23 <= P2 or P3;
+
+	PF01 <= PF0 or PF1;
+	PF23 <= PF2 or PF3;
+	
+	PRI0 <= prior(0);
+	PRI1 <= prior(1);
+	PRI2 <= prior(2);
+	PRI3 <= prior(3);
+	MULTI <= prior(5);
+	
+	PRI01 <= PRI0  or  PRI1;
+	PRI12 <= PRI1  or  PRI2;
+	PRI23 <= PRI2  or  PRI3;
+	PRI03 <= PRI0  or  PRI3;
+	
+	SP0 <= P0  and   not (PF01 and PRI23)  and   not (PRI2 and PF23);
+	SP1 <= P1  and   not (PF01 and PRI23)  and   not (PRI2 and PF23)  and  ( not P0  or  MULTI);
+	SP2 <= P2  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0);
+	SP3 <= P3  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0)  and  ( not P2  or  MULTI);
+	SF0 <= PF0  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF1 <= PF1  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF2 <= PF2  and   not (P23 and PRI03)  and   not (P01 and  not PRI2)  and   not SF3;
+	SF3 <= PF3  and   not (P23 and PRI03)  and   not (P01 and  not PRI2);
+	SB <=  not P01  and   not P23  and   not PF01  and   not PF23;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+		SP0_reg <= SP0_next;
+		SP1_reg <= SP1_next;
+		SP2_reg <= SP2_next;
+		SP3_reg <= SP3_next;
+		
+		SF0_reg <= SF0_next;
+		SF1_reg <= SF1_next;
+		SF2_reg <= SF2_next;
+		SF3_reg <= SF3_next;
+		
+		SB_reg <= SB_next;
+		end if;
+	end process;
+	
+	-- need to register this to get same position as GTIA modes - i.e. two colour clocks after AN data received
+	process(colour_enable,SP0_reg,SP1_reg,SP2_reg,SP3_reg,SF0_reg,SF1_reg,SF2_reg,SF3_reg,SB_reg,SP0,SP1,SP2,SP3,SF0,SF1,SF2,SF3,SB)
+	begin
+		SP0_next <= SP0_reg;
+		SP1_next <= SP1_reg;
+		SP2_next <= SP2_reg;
+		SP3_next <= SP3_reg;
+		
+		SF0_next <= SF0_reg;
+		SF1_next <= SF1_reg;
+		SF2_next <= SF2_reg;
+		SF3_next <= SF3_reg;
+		
+		SB_next <= SB_reg;
+		
+		if (colour_enable = '1') then	
+			SP0_next <= SP0;
+			SP1_next <= SP1;
+			SP2_next <= SP2;
+			SP3_next <= SP3;
+			
+			SF0_next <= SF0;
+			SF1_next <= SF1;
+			SF2_next <= SF2;
+			SF3_next <= SF3;
+			
+			SB_next <= SB;	
+		end if;
+	end process;
+		
+	-- output
+	P0_OUT <= SP0_reg;
+	P1_OUT <= SP1_reg;
+	P2_OUT <= SP2_reg;
+	P3_OUT <= SP3_reg;
+	PF0_OUT <= SF0_reg;
+	PF1_OUT <= SF1_reg;
+	PF2_OUT <= SF2_reg;
+	PF3_OUT <= SF3_reg;
+	BK_OUT <= SB_reg;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/de1/i2sslave.vhdl
===================================================================
--- unmerged/core/de1/i2sslave.vhdl	(nonexistent)
+++ unmerged/core/de1/i2sslave.vhdl	(revision 1)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY i2sslave IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	BCLK : IN STD_LOGIC;
+	DACLRC : IN STD_LOGIC;
+	
+	LEFT_IN : in std_logic_vector(15 downto 0);
+	RIGHT_IN : in std_logic_vector(15 downto 0);
+	
+	MCLK_2 : OUT STD_LOGIC;
+	DACDAT : OUT STD_LOGIC
+);
+END i2sslave;
+
+ARCHITECTURE vhdl OF i2sslave IS
+	signal bclk_reg : std_logic;
+	signal bclk_last_reg : std_logic;
+	signal daclrc_reg : std_logic;
+	signal daclrc_last_reg : std_logic;
+	
+	signal shiftreg_reg : std_logic_vector(15 downto 0);
+	signal shiftreg_next : std_logic_vector(15 downto 0);
+	
+	signal CLK_FAKE : std_logic;
+BEGIN
+	MCLK_2 <= CLK_FAKE; -- bad practice, but pll out of...
+	
+	-- Data read on bclk low->high transition
+	-- daclrc is set on bclk high->low transition
+	
+	-- register inputs
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			CLK_FAKE <= not(CLK_FAKE);
+		end if;
+	end process;
+	
+	process(CLK_FAKE)
+	begin	
+		if (CLK_FAKE'event and CLK_FAKE='1') then
+			bclk_reg <= bclk;
+			bclk_last_reg <= bclk_reg;
+			daclrc_reg <= daclrc;
+			daclrc_last_reg <= daclrc_reg;
+			shiftreg_reg <= shiftreg_next;
+		end if;
+	end process;
+	
+	-- sample on change to daclrc, shift out bit if required
+	process(daclrc_reg,daclrc_last_reg,bclk_reg,shiftreg_reg,left_in,right_in,bclk_last_reg)
+		variable reload : std_logic;
+	begin
+		reload := '0';
+		shiftreg_next <= shiftreg_reg;
+		
+		if (daclrc_reg = '1' and daclrc_last_reg = '0') then
+			shiftreg_next <= right_in;
+			reload := '1';
+		end if;
+		
+		if (daclrc_reg = '0' and daclrc_last_reg = '1') then
+			shiftreg_next <= left_in;
+			reload := '1';
+		end if;
+		
+		if (bclk_reg = '0' and bclk_last_reg = '1' and reload='0') then
+				shiftreg_next <= shiftreg_reg(14 downto 0)&'0';
+		end if;
+			
+	end process;
+	
+	DACDAT <= shiftreg_reg(15);
+END vhdl;
\ No newline at end of file
Index: unmerged/core/de1/irq_glue.vhdl
===================================================================
--- unmerged/core/de1/irq_glue.vhdl	(nonexistent)
+++ unmerged/core/de1/irq_glue.vhdl	(revision 1)
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY irq_glue IS
+PORT 
+( 
+	pokey_irq : in std_logic;
+	pia_irqa : in std_logic;
+	pia_irqb : in std_logic;
+	
+	combined_irq : out std_logic
+);
+end irq_glue;
+
+architecture vhdl of irq_glue is
+begin
+	combined_irq <= pokey_irq and pia_irqa and pia_irqb;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/de1/pll.ppf
===================================================================
--- unmerged/core/de1/pll.ppf	(nonexistent)
+++ unmerged/core/de1/pll.ppf	(revision 1)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone II" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: unmerged/core/de1/pll.cmp
===================================================================
--- unmerged/core/de1/pll.cmp	(nonexistent)
+++ unmerged/core/de1/pll.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: unmerged/core/de1/pokey_mixer.vhdl
===================================================================
--- unmerged/core/de1/pokey_mixer.vhdl	(nonexistent)
+++ unmerged/core/de1/pokey_mixer.vhdl	(revision 1)
@@ -0,0 +1,231 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_mixer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
+		
+	CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	GTIA_SOUND : IN STD_LOGIC;
+	
+	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+);
+END pokey_mixer;
+
+ARCHITECTURE vhdl OF pokey_mixer IS
+	signal volume_reg : std_logic_vector(15 downto 0);
+	signal volume_next : std_logic_vector(15 downto 0);
+	
+	signal volume_sum : std_logic_vector(5 downto 0);
+	
+	signal channel_0_en : std_logic_vector(3 downto 0);
+	signal channel_1_en : std_logic_vector(3 downto 0);
+	signal channel_2_en : std_logic_vector(3 downto 0);
+	signal channel_3_en : std_logic_vector(3 downto 0);
+	
+	signal gtia_en : std_logic_vector(5 downto 0);
+BEGIN
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			volume_reg <= volume_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(channel_enable,channel_0,channel_1,channel_2,channel_3)
+	begin
+		channel_0_en <= channel_0;
+		channel_1_en <= channel_1;
+		channel_2_en <= channel_2;
+		channel_3_en <= channel_3;
+	
+--		if (channel_enable(3)='0') then
+--			channel_0_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(2)='0') then
+--			channel_1_en <= X"0";
+--		end if;
+--
+--		if (channel_enable(1)='0') then
+--			channel_2_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(0)='0') then
+--			channel_3_en <= X"0";
+--		end if;
+	end process;
+	
+	gtia_en <= "0000"&gtia_sound&gtia_sound;  -- only room for 3 more! TODO, regenerate...
+	
+	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
+	begin
+		volume_sum <= 
+			std_logic_vector
+			(
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_0_en)
+						+ unsigned('0'&CHANNEL_1_en)
+					)) 
+					+ 
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_2_en) + 
+						unsigned('0'&CHANNEL_3_en)
+					))
+					+ 
+					unsigned(gtia_en)
+			);
+	end process;
+	
+	process (volume_sum)
+	begin
+		case volume_sum is 
+			when "000000" =>
+				volume_next <= X"0000";
+			when "000001" =>
+				volume_next <= X"05e4";
+			when "000010" =>
+				volume_next <= X"0b90";
+			when "000011" =>
+				volume_next <= X"1107";
+			when "000100" =>
+				volume_next <= X"1649";
+			when "000101" =>
+				volume_next <= X"1b57";
+			when "000110" =>
+				volume_next <= X"2032";
+			when "000111" =>
+				volume_next <= X"24db";
+			when "001000" =>
+				volume_next <= X"2954";
+			when "001001" =>
+				volume_next <= X"2d9d";
+			when "001010" =>
+				volume_next <= X"31b8";
+			when "001011" =>
+				volume_next <= X"35a6";
+			when "001100" =>
+				volume_next <= X"3968";
+			when "001101" =>
+				volume_next <= X"3cff";
+			when "001110" =>
+				volume_next <= X"406b";
+			when "001111" =>
+				volume_next <= X"43af";
+			when "010000" =>
+				volume_next <= X"46cc";
+			when "010001" =>
+				volume_next <= X"49c2";
+			when "010010" =>
+				volume_next <= X"4c92";
+			when "010011" =>
+				volume_next <= X"4f3e";
+			when "010100" =>
+				volume_next <= X"51c7";
+			when "010101" =>
+				volume_next <= X"542d";
+			when "010110" =>
+				volume_next <= X"5673";
+			when "010111" =>
+				volume_next <= X"5898";
+			when "011000" =>
+				volume_next <= X"5a9f";
+			when "011001" =>
+				volume_next <= X"5c88";
+			when "011010" =>
+				volume_next <= X"5e55";
+			when "011011" =>
+				volume_next <= X"6006";
+			when "011100" =>
+				volume_next <= X"619d";
+			when "011101" =>
+				volume_next <= X"631a";
+			when "011110" =>
+				volume_next <= X"647f";
+			when "011111" =>
+				volume_next <= X"65ce";
+			when "100000" =>
+				volume_next <= X"6706";
+			when "100001" =>
+				volume_next <= X"682a";
+			when "100010" =>
+				volume_next <= X"6939";
+			when "100011" =>
+				volume_next <= X"6a37";
+			when "100100" =>
+				volume_next <= X"6b22";
+			when "100101" =>
+				volume_next <= X"6bfe";
+			when "100110" =>
+				volume_next <= X"6cca";
+			when "100111" =>
+				volume_next <= X"6d88";
+			when "101000" =>
+				volume_next <= X"6e38";
+			when "101001" =>
+				volume_next <= X"6edd";
+			when "101010" =>
+				volume_next <= X"6f77";
+			when "101011" =>
+				volume_next <= X"7008";
+			when "101100" =>
+				volume_next <= X"708f";
+			when "101101" =>
+				volume_next <= X"710f";
+			when "101110" =>
+				volume_next <= X"7189";
+			when "101111" =>
+				volume_next <= X"71fe";
+			when "110000" =>
+				volume_next <= X"726e";
+			when "110001" =>
+				volume_next <= X"72db";
+			when "110010" =>
+				volume_next <= X"7347";
+			when "110011" =>
+				volume_next <= X"73b1";
+			when "110100" =>
+				volume_next <= X"741c";
+			when "110101" =>
+				volume_next <= X"7488";
+			when "110110" =>
+				volume_next <= X"74f6";
+			when "110111" =>
+				volume_next <= X"7568";
+			when "111000" =>
+				volume_next <= X"75df";
+			when "111001" =>
+				volume_next <= X"765c";
+			when "111010" =>
+				volume_next <= X"76df";
+			when "111011" =>
+				volume_next <= X"776b";
+			when "111100" =>
+				volume_next <= X"7800";				
+			when others =>
+				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+		end case;
+		
+	end process;
+			
+	-- output
+	volume_out <= volume_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/de1/poly_4.vhdl
===================================================================
--- unmerged/core/de1/poly_4.vhdl	(nonexistent)
+++ unmerged/core/de1/poly_4.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_4 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;	
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_4;
+
+ARCHITECTURE vhdl OF poly_4 IS
+	signal shift_reg: std_logic_vector(3 downto 0);
+	signal shift_next: std_logic_vector(3 downto 0);
+BEGIN
+	-- register
+	process(clk, reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "1010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: unmerged/core/de1/pokey_keyboard_scanner.vhdl
===================================================================
--- unmerged/core/de1/pokey_keyboard_scanner.vhdl	(nonexistent)
+++ unmerged/core/de1/pokey_keyboard_scanner.vhdl	(revision 1)
@@ -0,0 +1,179 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pokey_keyboard_scanner is
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	enable : in std_logic; -- typically hsync or equiv timing
+	keyboard_response : in std_logic_vector(1 downto 0);
+	debounce_disable : in std_logic;
+	scan_enable : in std_logic;
+	
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	
+	shift_pressed : out std_logic;
+	control_pressed : out std_logic;
+	break_pressed : out std_logic;
+	key_held : out std_logic;
+	keycode : out std_logic_vector(5 downto 0);
+	other_key_irq : out std_logic
+);
+end pokey_keyboard_scanner;
+
+architecture vhdl of pokey_keyboard_scanner is
+	signal bincnt_next : std_logic_vector(5 downto 0);
+	signal bincnt_reg : std_logic_vector(5 downto 0);
+
+	signal break_pressed_next : std_logic;
+	signal break_pressed_reg : std_logic;
+
+	signal shift_pressed_next : std_logic;
+	signal shift_pressed_reg : std_logic;
+	
+	signal control_pressed_next : std_logic;
+	signal control_pressed_reg : std_logic;	
+	
+	signal compare_latch_next : std_logic_vector(5 downto 0);
+	signal compare_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal keycode_latch_next : std_logic_vector(5 downto 0);
+	signal keycode_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal irq_next : std_logic;
+	signal irq_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal my_key : std_logic;
+	
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_wait_key : std_logic_vector(1 downto 0) := "00";
+	constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
+	constant state_valid_key : std_logic_vector(1 downto 0) := "10";
+	constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
+begin
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			bincnt_reg <= (others=>'0');
+			break_pressed_reg <= '0';
+			shift_pressed_reg <= '0';
+			control_pressed_reg <= '0';
+			compare_latch_reg <= (others=>'0');
+			keycode_latch_reg <= (others=>'1');
+			key_held_reg <= '0';
+			state_reg <= state_wait_key;
+			irq_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			bincnt_reg <= bincnt_next;
+			state_reg <= state_next;
+			break_pressed_reg <= break_pressed_next;
+			shift_pressed_reg <= shift_pressed_next;
+			control_pressed_reg <= control_pressed_next;
+			compare_latch_reg <= compare_latch_next;
+			keycode_latch_reg <= keycode_latch_next;
+			key_held_reg <= key_held_next;
+			state_reg <= state_next;
+			irq_reg <= irq_next;
+		end if;
+	end process;
+
+	process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_reg, shift_pressed_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
+	begin
+		bincnt_next <= bincnt_reg;
+		state_next <= state_reg;
+		compare_latch_next <= compare_latch_reg;
+		irq_next <= '0';
+		break_pressed_next <= break_pressed_reg;
+		shift_pressed_next <= shift_pressed_reg;
+		control_pressed_next <= control_pressed_reg;
+		keycode_latch_next <= keycode_latch_reg;
+		key_held_next <= key_held_reg;
+		
+		my_key <= '0';
+		if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
+			my_key <= '1';
+		end if;
+		
+		if (enable = '1' and scan_enable='1') then			
+			bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
+		
+			key_held_next<= '0';
+		
+			case state_reg is
+			when state_wait_key =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					state_next <= state_key_bounce;
+					compare_latch_next <= bincnt_reg;
+				end if;
+				
+			when state_key_bounce =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					if (my_key = '1') then -- same key
+						keycode_latch_next <= compare_latch_reg;
+						irq_next <= '1';
+						key_held_next<= '1';
+						state_next <= state_valid_key;
+					else -- different key (multiple keys pressed)
+						state_next <= state_wait_key;
+					end if;
+				else -- key not pressed
+					if (my_key = '1') then -- same key, no longer pressed
+						state_next <= state_wait_key;
+					end if;
+				end if;
+			
+			when state_valid_key =>
+				key_held_next<= '1';
+				if (my_key = '1') then -- only response to my key
+					if (keyboard_response(0) = '1') then -- no longer pressed
+						state_next <= state_key_debounce;
+					end if;					
+				end if;
+				
+			when state_key_debounce =>
+				if (my_key = '1') then
+					state_next <= state_wait_key;
+				end if;
+			end case;
+
+			if (bincnt_reg(3 downto 0)  = "0000") then
+				case bincnt_reg(5 downto 4) is
+				when "11" =>
+					break_pressed_next <= not(keyboard_response(1)); --0x30
+				when "01" =>
+					shift_pressed_next <= not(keyboard_response(1)); --0x10
+				when "00" =>
+					control_pressed_next <= not(keyboard_response(1)); -- 0x00
+				when others =>
+					--
+				end case;
+			end if;
+		end if;
+	end process;
+	
+	-- outputs
+	keyboard_scan <= not(bincnt_reg);
+	
+	key_held <= key_held_reg;	
+	keycode <= keycode_latch_reg;
+	break_pressed <= break_pressed_reg;
+	shift_pressed <= shift_pressed_reg;
+	control_pressed <= control_pressed_reg;
+	other_key_irq <= irq_reg;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/de1/pokey.vhdl
===================================================================
--- unmerged/core/de1/pokey.vhdl	(nonexistent)
+++ unmerged/core/de1/pokey.vhdl	(revision 1)
@@ -0,0 +1,1229 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Problem - UART on the DE1 does not have all pins connected. Need to use...
+
+ENTITY pokey IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	--ENABLE_179 :in std_logic;
+	CPU_MEMORY_READY :in std_logic;
+	ANTIC_MEMORY_READY :in std_logic;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	-- keyboard interface
+--	KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
+--	KEY_HELD : IN STD_LOGIC;
+--	SHIFT_PRESSED : IN STD_LOGIC;
+--	BREAK_PRESSED : IN STD_LOGIC;
+--	KEY_INTERRUPT : IN STD_LOGIC;
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	keyboard_response : in std_logic_vector(1 downto 0);
+	
+	-- pots - go high as capacitor charges
+	POT_IN : in std_logic_vector(7 downto 0);
+	
+	-- sio interface
+	SIO_IN1 : IN std_logic;
+	SIO_IN2 : IN std_logic;
+	SIO_IN3 : IN std_logic;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	
+	IRQ_N_OUT : OUT std_logic;
+	
+	SIO_OUT1 : OUT std_logic;
+	SIO_OUT2 : OUT std_logic;
+	SIO_OUT3 : OUT std_logic;
+	
+	SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+	
+	POT_RESET : out std_logic
+);
+END pokey;
+
+ARCHITECTURE vhdl OF pokey IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+
+	component syncreset_enable_divider IS
+	generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		syncreset : in std_logic;
+		reset_n : in std_logic;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_17_9 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC;
+		
+		RAND_OUT : OUT std_logic_vector(7 downto 0)
+	);
+	END component;
+	
+	component poly_5 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_4 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_countdown_timer IS
+	generic(UNDERFLOW_DELAY : natural := 3);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		ENABLE_UNDERFLOW : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		WR_EN : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_noise_filter IS
+	PORT 
+	( 
+		NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+			
+		PULSE_IN : IN STD_LOGIC;
+
+		NOISE_4 : IN STD_LOGIC;
+		NOISE_5 : IN STD_LOGIC;
+		NOISE_LARGE : IN STD_LOGIC;
+		
+		PULSE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_keyboard_scanner is
+	port
+	(
+		clk : in std_logic;
+		reset_n : in std_logic;
+		
+		enable : in std_logic; -- typically hsync or equiv timing
+		keyboard_response : in std_logic_vector(1 downto 0);
+		debounce_disable : in std_logic;
+		scan_enable : in std_logic;
+		
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		
+		shift_pressed : out std_logic;
+		control_pressed : out std_logic;
+		break_pressed : out std_logic;
+		key_held : out std_logic;
+		keycode : out std_logic_vector(5 downto 0);
+		other_key_irq : out std_logic
+	);
+	end component;
+	
+	--signal enable_179 : std_logic;
+	signal enable_64 : std_logic;
+	signal enable_15 : std_logic;
+
+	signal audf0_reg : std_logic_vector(7 downto 0);
+	signal audc0_reg : std_logic_vector(7 downto 0);
+	signal audf1_reg : std_logic_vector(7 downto 0);
+	signal audc1_reg : std_logic_vector(7 downto 0);
+	signal audf2_reg : std_logic_vector(7 downto 0);
+	signal audc2_reg : std_logic_vector(7 downto 0);
+	signal audf3_reg : std_logic_vector(7 downto 0);
+	signal audc3_reg : std_logic_vector(7 downto 0);
+	signal audctl_reg : std_logic_vector(7 downto 0);	
+	signal audf0_next : std_logic_vector(7 downto 0);
+	signal audc0_next : std_logic_vector(7 downto 0);
+	signal audf1_next : std_logic_vector(7 downto 0);
+	signal audc1_next : std_logic_vector(7 downto 0);
+	signal audf2_next : std_logic_vector(7 downto 0);
+	signal audc2_next : std_logic_vector(7 downto 0);
+	signal audf3_next : std_logic_vector(7 downto 0);
+	signal audc3_next : std_logic_vector(7 downto 0);
+	signal audctl_next : std_logic_vector(7 downto 0);
+
+	signal audf0_pulse : std_logic;
+	signal audf1_pulse : std_logic;
+	signal audf2_pulse : std_logic;
+	signal audf3_pulse : std_logic;
+	
+	signal audf0_reload : std_logic;
+	signal audf1_reload : std_logic;
+	signal audf2_reload : std_logic;
+	signal audf3_reload : std_logic;
+	
+	signal stimer_write : std_logic;
+	signal stimer_write_delayed : std_logic;
+	
+	signal audf0_pulse_noise : std_logic;
+	signal audf1_pulse_noise : std_logic;
+	signal audf2_pulse_noise : std_logic;
+	signal audf3_pulse_noise : std_logic;
+	
+	signal audf0_enable : std_logic;
+	signal audf1_enable : std_logic;
+	signal audf2_enable : std_logic;
+	signal audf3_enable : std_logic;
+	
+	signal chan0_output_next : std_logic;
+	signal chan1_output_next : std_logic;
+	signal chan2_output_next : std_logic;
+	signal chan3_output_next : std_logic;
+	signal chan0_output_reg : std_logic;
+	signal chan1_output_reg : std_logic;
+	signal chan2_output_reg : std_logic;
+	signal chan3_output_reg : std_logic;
+	
+	signal highpass0_next : std_logic;
+	signal highpass1_next : std_logic;	
+	signal highpass0_reg : std_logic;
+	signal highpass1_reg : std_logic;
+	
+	signal volume_channel_0_next : std_logic_vector(3 downto 0);
+	signal volume_channel_1_next : std_logic_vector(3 downto 0);
+	signal volume_channel_2_next : std_logic_vector(3 downto 0);
+	signal volume_channel_3_next : std_logic_vector(3 downto 0);
+	signal volume_channel_0_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_1_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_2_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_3_reg : std_logic_vector(3 downto 0);
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal noise_4 : std_logic;
+	signal noise_5 : std_logic;
+	signal noise_large : std_logic;
+	signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
+	
+	signal initmode : std_logic;
+	
+	signal irqen_next : std_logic_vector(7 downto 0);
+	signal irqen_reg : std_logic_vector(7 downto 0);
+
+	signal irqst_next : std_logic_vector(7 downto 0);
+	signal irqst_reg : std_logic_vector(7 downto 0);
+	
+	signal irq_n_next : std_logic;
+	signal irq_n_reg : std_logic; -- for output
+	
+	-- serial ports!
+	signal serial_ip_ready_interrupt : std_logic;
+	signal serial_ip_framing_next : std_logic;
+	signal serial_ip_framing_reg : std_logic;
+	signal serial_ip_overrun_next : std_logic;
+	signal serial_ip_overrun_reg : std_logic;
+	signal serial_op_needed_interrupt : std_logic;
+	
+	signal skctl_next : std_logic_vector(7 downto 0);
+	signal skctl_reg : std_logic_vector(7 downto 0);
+	
+	signal serin_shift_next : std_logic_vector(9 downto 0);
+	signal serin_shift_reg : std_logic_vector(9 downto 0);
+	signal serin_next : std_logic_vector(7 downto 0);
+	signal serin_reg : std_logic_vector(7 downto 0);
+	signal serin_bitcount_next : std_logic_vector(3 downto 0);
+	signal serin_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal sio_in1_reg : std_logic;
+	signal sio_in2_reg : std_logic;
+	signal sio_in3_reg : std_logic;
+	signal sio_in_next : std_logic;
+	signal sio_in_reg : std_logic;
+	
+	signal sio_out_next : std_logic;
+	signal sio_out_reg : std_logic;
+	signal serial_out_next : std_logic;
+	signal serial_out_reg : std_logic;
+	
+	signal serout_shift_next : std_logic_vector(9 downto 0);
+	signal serout_shift_reg : std_logic_vector(9 downto 0);
+	
+	signal serout_holding_full_next : std_logic;
+	signal serout_holding_full_reg : std_logic;
+	signal serout_holding_next : std_logic_vector(7 downto 0);
+	signal serout_holding_reg : std_logic_vector(7 downto 0);
+	signal serout_holding_load : std_logic;
+
+	signal serout_bitcount_next : std_logic_vector(3 downto 0);
+	signal serout_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal serout_active_next : std_logic;
+	signal serout_active_reg : std_logic;
+	
+	signal serial_reset : std_logic;
+	signal skrest_write : std_logic;
+	
+	signal serout_enable : std_logic;
+	signal serout_enable_delayed : std_logic;
+	signal serin_enable : std_logic;
+	
+	signal async_serial_reset : std_logic;
+	signal waiting_for_start_bit : std_logic;
+	
+	signal serin_clock_next : std_logic;
+	signal serin_clock_reg : std_logic;
+	signal serin_clock_last_next : std_logic;
+	signal serin_clock_last_reg : std_logic;
+
+	signal serout_clock_next : std_logic;
+	signal serout_clock_reg : std_logic;
+	signal serout_clock_last_next : std_logic;
+	signal serout_clock_last_reg : std_logic;
+	
+	signal twotone_reset : std_logic;
+	signal twotone_next : std_logic;
+	signal twotone_reg : std_logic;
+	
+	signal clock_next : std_logic;
+	signal clock_reg : std_logic;
+	signal clock_sync_next : std_logic;
+	signal clock_sync_reg : std_logic;
+	signal clock_input : std_logic;
+	
+	-- keyboard
+	signal keyboard_overrun_next : std_logic;
+	signal keyboard_overrun_reg : std_logic;
+	
+	signal shift_pressed : std_logic;
+	signal control_pressed : std_logic;
+	signal break_pressed : std_logic;
+	signal key_held : std_logic;
+	signal other_key_irq : std_logic;
+	
+	signal kbcode : std_logic_vector(5 downto 0);
+	
+	-- pots
+	signal pot0_next : std_logic_vector(7 downto 0);
+	signal pot0_reg : std_logic_vector(7 downto 0);
+	signal pot1_next : std_logic_vector(7 downto 0);
+	signal pot1_reg : std_logic_vector(7 downto 0);
+	signal pot2_next : std_logic_vector(7 downto 0);
+	signal pot2_reg : std_logic_vector(7 downto 0);
+	signal pot3_next : std_logic_vector(7 downto 0);
+	signal pot3_reg : std_logic_vector(7 downto 0);
+	signal pot4_next : std_logic_vector(7 downto 0);
+	signal pot4_reg : std_logic_vector(7 downto 0);
+	signal pot5_next : std_logic_vector(7 downto 0);
+	signal pot5_reg : std_logic_vector(7 downto 0);	
+	signal pot6_next : std_logic_vector(7 downto 0);
+	signal pot6_reg : std_logic_vector(7 downto 0);
+	signal pot7_next : std_logic_vector(7 downto 0);
+	signal pot7_reg : std_logic_vector(7 downto 0);	
+	
+	signal pot_counter_next : std_logic_vector(7 downto 0);
+	signal pot_counter_reg : std_logic_vector(7 downto 0);
+	
+	signal potgo_write : std_logic;
+	
+	signal pot_reset_next : std_logic;
+	signal pot_reset_reg : std_logic;
+	
+	signal enable_179 : std_logic;
+BEGIN
+	--HACK FIXME TODO
+	enable_179 <= cpu_MEMORY_READY or antIC_MEMORY_READY;
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
+			audf0_reg <= X"00";
+			audc0_reg <= X"00";
+			audf1_reg <= X"00";
+			audc1_reg <= X"00";
+			audf2_reg <= X"00";
+			audc2_reg <= X"00";
+			audf3_reg <= X"00";
+			audc3_reg <= X"00";
+			audctl_reg <= X"00";
+			
+			irqen_reg <= X"00";
+			irqst_reg <= X"FF";
+			irq_n_reg <= '1';
+			
+			skctl_reg <= X"00";
+			
+			highpass0_reg <= '0';
+			highpass1_reg <= '0';
+			
+			chan0_output_reg <= '0';
+			chan1_output_reg <= '0';
+			chan2_output_reg <= '0';
+			chan3_output_reg <= '0';
+			
+			volume_channel_0_reg <= (others=>'0');
+			volume_channel_1_reg <= (others=>'0');
+			volume_channel_2_reg <= (others=>'0');
+			volume_channel_3_reg <= (others=>'0');
+			
+			serin_reg <= (others=>'0');
+			serin_shift_reg <= (others=>'0');
+			serin_bitcount_reg <= (others=>'0');
+			serout_shift_reg <= (others=>'0');
+			serout_holding_reg <= (others=>'0');
+			serout_holding_full_reg <= '0';
+			serout_active_reg <= '0';		
+			sio_out_reg <= '1';
+			serial_out_reg <= '1';
+			
+			serial_ip_framing_reg <= '0';
+			serial_ip_overrun_reg <= '0';
+			
+			clock_reg <= '0';
+			clock_sync_reg <= '0';
+	
+			keyboard_overrun_reg <= '0';
+			
+			serin_clock_reg <= '0';
+			serin_clock_last_reg <= '0';
+			serout_clock_reg <= '0';
+			serout_clock_last_reg <= '0';
+			
+			twotone_reg <= '0';
+			
+			sio_in_reg <= '0';
+			
+			pot0_reg <= (others=>'0');
+			pot1_reg <= (others=>'0');
+			pot2_reg <= (others=>'0');
+			pot3_reg <= (others=>'0');
+			pot4_reg <= (others=>'0');
+			pot5_reg <= (others=>'0');
+			pot6_reg <= (others=>'0');
+			pot7_reg <= (others=>'0');
+			
+			pot_counter_reg <= (others=>'0');
+			
+			pot_reset_reg <= '1';
+			
+		elsif (clk'event and clk='1') then			
+			audf0_reg <= audf0_next;
+			audc0_reg <= audc0_next;
+			audf1_reg <= audf1_next;
+			audc1_reg <= audc1_next;
+			audf2_reg <= audf2_next;
+			audc2_reg <= audc2_next;
+			audf3_reg <= audf3_next;
+			audc3_reg <= audc3_next;
+			audctl_reg <= audctl_next;
+			
+			irqen_reg <= irqen_next;
+			irqst_reg <= irqst_next;
+			irq_n_reg <= irq_n_next;
+			
+			skctl_reg <= skctl_next;
+			
+			highpass0_reg <= highpass0_next;
+			highpass1_reg <= highpass1_next;
+			
+			chan0_output_reg <= chan0_output_next;
+			chan1_output_reg <= chan1_output_next;
+			chan2_output_reg <= chan2_output_next;
+			chan3_output_reg <= chan3_output_next;
+			
+			volume_channel_0_reg<= volume_channel_0_next;
+			volume_channel_1_reg<= volume_channel_1_next;
+			volume_channel_2_reg<= volume_channel_2_next;
+			volume_channel_3_reg<= volume_channel_3_next;
+			
+			serin_reg <= serin_next;
+			serin_shift_reg <= serin_shift_next;
+			serin_bitcount_reg <= serin_bitcount_next;
+			serout_shift_reg <= serout_shift_next;
+			serout_bitcount_reg <= serout_bitcount_next;
+			
+			serout_holding_reg<=serout_holding_next;
+			serout_holding_full_reg<=serout_holding_full_next;
+			serout_active_reg <= serout_active_next;
+			
+			sio_out_reg <= sio_out_next;
+			serial_out_reg <= serial_out_next;
+			
+			serial_ip_framing_reg <= serial_ip_framing_next;
+			serial_ip_overrun_reg <= serial_ip_overrun_next;
+			
+			clock_reg <= clock_next;
+			clock_sync_reg <= clock_sync_next;
+			
+			keyboard_overrun_reg <= keyboard_overrun_next;
+			
+			serin_clock_reg <= serin_clock_next;
+			serin_clock_last_reg <= serin_clock_last_next;
+			serout_clock_reg <= serout_clock_next;
+			serout_clock_last_reg <= serout_clock_last_next;
+			
+			twotone_reg <= twotone_next;
+			
+			sio_in_reg <= sio_in_next;
+			
+			pot0_reg <= pot0_next;
+			pot1_reg <= pot1_next;
+			pot2_reg <= pot2_next;
+			pot3_reg <= pot3_next;
+			pot4_reg <= pot4_next;
+			pot5_reg <= pot5_next;
+			pot6_reg <= pot6_next;
+			pot7_reg <= pot7_next;
+			
+			pot_counter_reg <= pot_counter_next;
+			
+			pot_reset_reg <= pot_reset_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+	
+	-- clock selection
+	process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
+	begin
+		audf0_enable <= enable_64;
+		audf1_enable <= enable_64;
+		audf2_enable <= enable_64;
+		audf3_enable <= enable_64;		
+		
+		if (audctl_reg(0) = '1') then
+			audf0_enable <= enable_15;
+			audf1_enable <= enable_15;
+			audf2_enable <= enable_15;
+			audf3_enable <= enable_15;
+		end if;
+
+		if (audctl_reg(6) = '1') then
+			audf0_enable <= enable_179;
+		end if;
+		
+		if (audctl_reg(5) = '1') then
+			audf2_enable <= enable_179;
+		end if;
+		
+		if(audctl_reg(4) = '1') then
+			audf1_enable <= audf0_pulse;
+		end if;
+		
+		if(audctl_reg(3) = '1') then
+			audf3_enable <= audf2_pulse;
+		end if;
+	end process;
+	
+	-- Instantiate timers
+	timer0 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
+	timer1 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
+	timer2 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
+	timer3 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);		
+		
+	-- Timer reloading
+	process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
+	begin
+		audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
+		audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
+		audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
+		audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
+	end process;
+	
+	-- Writes to registers
+	process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
+	begin
+		audf0_next <= audf0_reg;
+		audc0_next <= audc0_reg;
+		audf1_next <= audf1_reg;
+		audc1_next <= audc1_reg;
+		audf2_next <= audf2_reg;
+		audc2_next <= audc2_reg;
+		audf3_next <= audf3_reg;
+		audc3_next <= audc3_reg;
+		audctl_next <= audctl_reg;		
+		
+		irqen_next <= irqen_reg;
+		skctl_next <= skctl_reg;
+		
+		stimer_write <= '0';
+		
+		serout_holding_load <= '0';
+		serout_holding_next <= serout_holding_reg;
+		
+		serial_reset <= '0';
+		skrest_write <= '0';
+		potgo_write <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				audf0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(1) = '1') then
+				audc0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(2) = '1') then
+				audf1_next <= data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				audc1_next <= data_in;
+			end if;
+			
+			if(addr_decoded(4) = '1') then
+				audf2_next <= data_in;
+			end if;
+
+			if(addr_decoded(5) = '1') then
+				audc2_next <= data_in;
+			end if;
+			
+			if(addr_decoded(6) = '1') then
+				audf3_next <= data_in;
+			end if;		
+
+			if(addr_decoded(7) = '1') then
+				audc3_next <= data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				audctl_next <= data_in;
+			end if;
+			
+			if (addr_decoded(9) = '1') then --STIMER
+				stimer_write <= '1';
+			end if;
+			
+			if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
+				skrest_write <= '1';
+			end if;
+
+			if (addr_decoded(11) = '1') then -- POTGO - start POT scan
+				potgo_write <= '1';
+			end if;
+			
+			if (addr_decoded(13) = '1') then --SEROUT								
+				serout_holding_next <= data_in;
+				serout_holding_load <= '1';
+			end if;
+			
+			if (addr_decoded(14) = '1') then --IRQEN
+				irqen_next <= data_in;
+			end if;
+
+			if (addr_decoded(15) = '1') then --SKCTL
+				skctl_next <= data_in;
+				
+				if (data_in(6 downto 4)="000") then
+					serial_reset <= '1';
+				end if;
+			end if;	
+	
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin
+		data_out <= X"FF";
+
+		if(addr_decoded(0) = '1') then --POT0
+			data_out <= pot0_reg;
+		end if;
+
+		if(addr_decoded(1) = '1') then --POT1
+			data_out <= pot1_reg;
+		end if;
+
+		if(addr_decoded(2) = '1') then --POT2
+			data_out <= pot2_reg;
+		end if;
+
+		if(addr_decoded(3) = '1') then --POT3
+			data_out <= pot3_reg;
+		end if;
+		
+		if(addr_decoded(4) = '1') then --POT4
+			data_out <= pot4_reg;
+		end if;
+
+		if(addr_decoded(5) = '1') then --POT5
+			data_out <= pot5_reg;
+		end if;
+
+		if(addr_decoded(6) = '1') then --POT6
+			data_out <= pot6_reg;
+		end if;
+
+		if(addr_decoded(7) = '1') then --POT7
+			data_out <= pot7_reg;
+		end if;
+
+		if(addr_decoded(8) = '1') then --ALLPOT
+			data_out <= not(pot_in);
+		end if;
+		
+		if(addr_decoded(9) = '1') then --KBCODE
+			data_out <= control_pressed&shift_pressed&kbcode;
+		end if;
+		
+		if(addr_decoded(10) = '1') then -- RANDOM
+			data_out <= RAND_OUT;
+		end if;
+
+		if (addr_decoded(13) = '1') then --SERIN			
+			data_out <= serin_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
+			data_out <= IRQST_REG;
+			--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
+		end if;		
+
+		if (addr_decoded(15) = '1') then --SKSTAT
+			data_out <= not(serial_ip_framing_reg)&not(serial_ip_overrun_reg)&not(keyboard_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
+		end if;		
+		
+	end process;
+	
+	-- Fire interrupts
+	process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
+	begin
+		-- clear interrupts
+		irqst_next <= irqst_reg or not(irqen_reg);
+				
+		irq_n_next <= '0';
+
+		if ((irqst_reg or "0000"&not(irqen_reg(3))&"000") = X"FF") then
+			irq_n_next <= '1';
+		end if;
+	
+		-- set interrupts
+		if (audf0_pulse = '1') then
+			irqst_next(0) <= not(irqen_reg(0));
+		end if;
+
+		if (audf1_pulse = '1') then
+			irqst_next(1) <= not(irqen_reg(1));
+		end if;
+
+		if (audf3_pulse = '1') then
+			irqst_next(2) <= not(irqen_reg(2));
+		end if;
+		
+		if (other_key_irq = '1') then
+			irqst_next(6) <= not(irqen_reg(6));			
+		end if;
+		
+		if (break_pressed = '1') then
+			irqst_next(7) <= not(irqen_reg(7));			
+		end if;		
+	
+		if (serial_ip_ready_interrupt = '1') then
+			irqst_next(5) <= not(irqen_reg(5));
+		end if;
+		
+		irqst_next(3) <= serout_active_reg;
+		
+		if (serial_op_needed_interrupt = '1') then
+			irqst_next(4) <= not(irqen_reg(4));
+		end if;
+		
+	end process;
+	
+	-- Instantiate delay for stimer reload_request
+	stimer_delay : delay_line
+		generic map (count=>3)
+		port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
+		
+	--stimer_write_delayed <= stimer_write;
+	
+	-- Instantiate audio noise filters
+	pokey_noise_filter0 : pokey_noise_filter
+		port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter1 : pokey_noise_filter
+		port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter2 : pokey_noise_filter
+		port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter3 : pokey_noise_filter
+		port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	
+	-- Audio output stage
+	process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
+	begin
+		chan0_output_next <= chan0_output_reg;
+		chan1_output_next <= chan1_output_reg;
+		chan2_output_next <= chan2_output_reg;
+		chan3_output_next <= chan3_output_reg;
+		
+		if (audf0_pulse_noise = '1') then
+			chan0_output_next <= not(chan0_output_reg);
+		end if;
+		
+		if (audf1_pulse_noise = '1') then
+			chan1_output_next <= not(chan1_output_reg);
+		end if;
+		
+		if (audf2_pulse_noise = '1') then
+			chan2_output_next <= not(chan2_output_reg);
+		end if;
+		
+		if (audf3_pulse_noise = '1') then
+			chan3_output_next <= not(chan3_output_reg);
+		end if;
+	end process;
+	
+	-- High pass filters
+	process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
+	begin
+		highpass0_next <= highpass0_reg;
+		highpass1_next <= highpass1_reg;
+		
+		if (audctl_reg(2) = '1') then
+			if (audf2_pulse = '1') then
+				highpass0_next <= chan0_output_reg;
+			end if;
+		else
+			highpass0_next <= '1';
+		end if;
+		
+		if (audctl_reg(1) = '1') then
+			if (audf3_pulse = '1') then
+				highpass1_next <= chan1_output_reg;
+			end if;
+		else
+			highpass1_next <= '1';
+		end if;
+		
+	end process;
+	
+	-- Instantiate key pokey clocks
+	-- ~1.79MHz - from 25MHz/14
+	-- ~64KHz - from 1.79MHz/28
+	-- ~15KHz - from 1.79MHz/114
+	--enable_179_div : enable_divider
+	--	generic map (COUNT=>14)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);		
+		
+	-- resetcount 6/33
+	enable_64_div : syncreset_enable_divider
+		generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
+		
+	enable_15_div : syncreset_enable_divider
+		generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
+		
+	-- Instantiate pokey noise circuits (lfsr)
+	initmode <= skctl_next(1) nor skctl_next(0);
+	poly_17_19_lfsr : poly_17_9
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
+		
+	poly_5_lfsr : poly_5
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
+		
+	poly_4_lfsr : poly_4
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
+	
+	--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
+	process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
+	begin
+		volume_channel_0_next <= "0000";
+		volume_channel_1_next <= "0000";
+		volume_channel_2_next <= "0000";
+		volume_channel_3_next <= "0000";
+			
+		if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
+			volume_channel_0_next <= audc0_reg(3 downto 0);
+		end if;
+		
+		if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
+			volume_channel_1_next <= audc1_reg(3 downto 0);
+		end if;
+		
+		if ((chan2_output_reg or audc2_reg(4)) = '1') then
+			volume_channel_2_next <= audc2_reg(3 downto 0);
+		end if;
+		
+		if ((chan3_output_reg or audc3_reg(4)) = '1') then
+			volume_channel_3_next <= audc3_reg(3 downto 0);
+		end if;
+		
+	end process;
+	
+	-- serial port output	
+	-- urghhh
+	serout_clock_delay : delay_line
+		generic map (count=>2)
+		port map (clk=>clk, sync_reset=>serial_reset or stimer_write_delayed,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+		
+	
+	process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
+	begin
+		serout_clock_next <= serout_clock_reg;
+		serout_clock_last_next <= serout_clock_reg;
+	
+		serout_shift_next <= serout_shift_reg;
+		serout_bitcount_next <= serout_bitcount_reg;
+		serout_holding_full_next <= serout_holding_full_reg;
+		serout_active_next <= serout_active_reg;
+		
+		serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
+		sio_out_next <= serial_out_reg;		
+	
+		-- two tone output
+		twotone_next <= twotone_reg;
+		twotone_reset <= '0';
+		
+		if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
+			twotone_next <= not(twotone_reg);
+			twotone_reset <= skctl_reg(3);
+		end if;
+		
+		if (skctl_reg(3) = '1') then
+			sio_out_next <= twotone_reg;
+		end if;
+	
+		-- force break
+		if (skctl_reg(7) = '1') then
+			sio_out_next <= '0';
+		end if;
+		
+		serial_op_needed_interrupt <= '0';		
+		
+		-- generate clock from enable signals
+		if (serout_enable_delayed = '1') then
+			serout_clock_next <= not(serout_clock_reg);
+		end if;
+		
+		-- output bits over sio
+		if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then			
+			serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
+			serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
+				
+			-- reload			
+			if (serout_bitcount_reg = X"0") then
+				if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
+					serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
+					serout_shift_next <= '1'&serout_holding_reg&'0';
+					serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
+					serout_holding_full_next <= '0';					
+					serial_op_needed_interrupt <= '1'; -- more data please!
+					serout_active_next <= '1';
+				else
+					serout_active_next <= '0';
+					serial_out_next <= '1'; -- remove blip! 
+				end if;
+			else
+				serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
+			end if;
+		end if;
+		
+		-- register to load has been written too, update our state to reflect that it is full
+		if (serout_holding_load = '1') then
+			serout_holding_full_next <= '1';
+		end if;
+		
+		if (serial_reset = '1') then
+			twotone_next <= '0';
+			serout_bitcount_next <= (others=>'0');
+			serout_shift_next <= (others=>'0');
+			serout_holding_full_next <= '0';
+			serout_clock_next <= '0';
+			serout_clock_last_next <= '0';
+			serout_active_next <= '0';
+		end if;
+	end process;
+	
+	-- serial port input
+	sio_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);	
+	sio_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);	
+	sio_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);	
+	sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
+		
+	waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
+	process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
+	begin
+		serin_clock_next <= serin_clock_reg;
+		serin_clock_last_next <= serin_clock_reg;
+	
+		serin_shift_next <= serin_shift_reg;
+		serin_bitcount_next <= serin_bitcount_reg;
+		serin_next <= serin_reg;
+		
+		serial_ip_overrun_next <= serial_ip_overrun_reg;
+		serial_ip_framing_next <= serial_ip_framing_reg;
+		serial_ip_ready_interrupt <= '0';
+		
+		async_serial_reset <= '0';
+		
+		-- generate clock from enable signals
+		if (serin_enable = '1') then
+			serin_clock_next <= not(serin_clock_reg);
+		end if;
+		
+		-- resync clock on receipt of start bit
+		if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
+			async_serial_reset <= '1';
+			serin_clock_next <= '1';
+		end if;
+		
+		-- receive bits into shift reg		
+		if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge					
+			if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then				
+				serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
+			
+				if (serin_bitcount_reg = X"0") then -- full byte
+					serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
+					
+					serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
+					
+					-- irq to alert new data avilable
+					serial_ip_ready_interrupt <= '1';
+					
+					-- flag up overrun
+					if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
+						serial_ip_overrun_next <= '1';
+					end if;				
+					
+					-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
+					if (sio_in_reg='0') then
+						serial_ip_framing_next <= '1';
+					end if;
+				else			
+					serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
+				end if;
+			end if;
+		end if;
+		
+		if (skrest_write = '1') then
+			serial_ip_overrun_next <= '0';
+			serial_ip_framing_next <= '0';
+		end if;
+		
+		if (serial_reset = '1') then
+			serin_clock_next <= '0';
+			serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
+			serin_shift_next <= (others=>'0');			
+		end if;		
+	end process;
+	
+	-- serial clocks
+	process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
+	begin
+		clock_next <= sio_clock;
+		clock_sync_next <= clock_reg;
+	
+		serout_enable <= '0';
+		serin_enable <= '0';
+		clock_input <= '1'; -- when output, outputs channel 4
+		
+		case skctl_reg(6 downto 4) is
+			when "000" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "001" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "010" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+				clock_input <= '0';
+			when "011" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "100" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= audf3_pulse;
+			when "101" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "110" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+				clock_input <= '0';
+			when "111" =>			
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+		end case;
+	end process;
+	
+	-- keyboard overrun (i.e. second key pressed before interrupt cleared)
+	process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
+	begin
+		keyboard_overrun_next <= keyboard_overrun_reg;
+		
+		if (other_key_irq='1' and irqst_reg(6)='0') then
+			keyboard_overrun_next <= '1';
+		end if;
+		
+		if (skrest_write = '1') then
+			keyboard_overrun_next <= '0';
+		end if;
+	end process;
+	
+	-- keyboard scan
+	pokey_keyboard_scanner1 : pokey_keyboard_scanner
+		port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);	
+	
+	-- POT scan
+	process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin	
+		pot0_next <= pot0_reg;
+		pot1_next <= pot1_reg;
+		pot2_next <= pot2_reg;
+		pot3_next <= pot3_reg;
+		pot4_next <= pot4_reg;
+		pot5_next <= pot5_reg;
+		pot6_next <= pot6_reg;
+		pot7_next <= pot7_reg;
+		
+		pot_reset_next <= pot_reset_reg;
+		
+		pot_counter_next <= pot_counter_reg;
+		
+		if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
+			pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
+			if (pot_counter_reg = X"E4") then
+				pot_reset_next <= '1'; -- turn on pot dump transistors
+			end if;
+			
+			if (pot_reset_reg = '0') then
+				if (pot_in(0) = '0') then -- pot now high, latch
+					pot0_next <= pot_counter_reg;
+				end if;
+				if (pot_in(1) = '0') then -- pot now high, latch
+					pot1_next <= pot_counter_reg;
+				end if;				
+				if (pot_in(2) = '0') then -- pot now high, latch
+					pot2_next <= pot_counter_reg;
+				end if;
+				if (pot_in(3) = '0') then -- pot now high, latch
+					pot3_next <= pot_counter_reg;
+				end if;
+				if (pot_in(4) = '0') then -- pot now high, latch
+					pot4_next <= pot_counter_reg;
+				end if;
+				if (pot_in(5) = '0') then -- pot now high, latch
+					pot5_next <= pot_counter_reg;
+				end if;
+				if (pot_in(6) = '0') then -- pot now high, latch
+					pot6_next <= pot_counter_reg;
+				end if;
+				if (pot_in(7) = '0') then -- pot now high, latch
+					pot7_next <= pot_counter_reg;
+				end if;
+			end if;			
+		end if;
+			
+		if (potgo_write = '1') then
+			pot_counter_next <= (others=>'0');
+			pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
+		end if;		
+	end process;
+	
+	-- Outputs
+	irq_n_out <= irq_n_reg;	
+	
+	CHANNEL_0_OUT <= volume_channel_0_reg;
+	CHANNEL_1_OUT <= volume_channel_1_reg;
+	CHANNEL_2_OUT <= volume_channel_2_reg;
+	CHANNEL_3_OUT <= volume_channel_3_reg;
+	
+	sio_out1 <= sio_out_reg;	
+	sio_out2 <= sio_out_reg;	
+	sio_out3 <= sio_out_reg;	
+	
+	sio_clock <= audf3_pulse when clock_input='0' else 'Z';
+	
+	pot_reset <= pot_reset_reg;
+		
+END vhdl;
+
+
Index: unmerged/core/de1/pokey_ps2_decoder.vhdl
===================================================================
--- unmerged/core/de1/pokey_ps2_decoder.vhdl	(nonexistent)
+++ unmerged/core/de1/pokey_ps2_decoder.vhdl	(revision 1)
@@ -0,0 +1,434 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_ps2_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : std_logic;
+	-- ENABLE : IN STD_LOGIC; TODO Pokey debounce and scanning can be disabled
+	
+	-- ps2 keyboard input
+	KEY_EVENT : IN STD_LOGIC;
+	KEY_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
+	KEY_EXTENDED : IN STD_LOGIC;
+	KEY_UP : IN STD_LOGIC;
+	
+	-- pokey output
+	KBCODE : OUT STD_LOGIC_VECTOR(7 downto 0);
+	KEY_HELD : OUT STD_LOGIC;
+	SHIFT_PRESSED : OUT STD_LOGIC;
+	BREAK_PRESSED : OUT STD_LOGIC;
+	KEY_INTERRUPT : OUT STD_LOGIC;
+	
+	-- other output
+	CONSOL_START : OUT STD_LOGIC;
+	CONSOL_SELECT : OUT STD_LOGIC;
+	CONSOL_OPTION : OUT STD_LOGIC;
+	
+	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+	
+	SYSTEM_RESET : out std_logic
+);
+END pokey_ps2_decoder;
+
+ARCHITECTURE vhdl OF pokey_ps2_decoder IS
+	signal left_shift_pressed_reg : std_logic;
+	signal left_shift_pressed_next : std_logic;
+	signal right_shift_pressed_reg : std_logic;
+	signal right_shift_pressed_next : std_logic;	
+	
+	signal left_control_pressed_reg : std_logic;
+	signal left_control_pressed_next : std_logic;	
+	signal right_control_pressed_reg : std_logic;
+	signal right_control_pressed_next : std_logic;	
+	
+	signal kbcode_next : std_logic_vector(7 downto 0);
+	signal kbcode_reg : std_logic_vector(7 downto 0); -- XXX remove unused upper bits
+	
+	signal interrupt_next : std_logic;
+	signal interrupt_reg : std_logic;
+	
+	signal break_next : std_logic;
+	signal break_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal start_next : std_logic;
+	signal start_reg : std_logic;
+	signal select_next : std_logic;
+	signal select_reg : std_logic;	
+	signal option_next : std_logic;
+	signal option_reg : std_logic;
+	
+	signal virtual_up_next : std_logic;
+	signal virtual_up_reg : std_logic;
+	signal virtual_down_next : std_logic;
+	signal virtual_down_reg : std_logic;
+	signal virtual_left_next : std_logic;
+	signal virtual_left_reg : std_logic;
+	signal virtual_right_next : std_logic;
+	signal virtual_right_reg : std_logic;
+	signal virtual_stick_pressed_next : std_logic;
+	signal virtual_stick_pressed_reg : std_logic;
+	
+	signal system_reset_next : std_logic;
+	signal system_reset_reg : std_logic;	
+	
+	signal no_kbcode_update : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			left_shift_pressed_reg <= '0';
+			right_shift_pressed_reg <= '0';
+			
+			left_control_pressed_reg <= '0';
+			right_control_pressed_reg <= '0';
+			
+			kbcode_reg <= X"3F";
+			
+			interrupt_reg <= '0';
+			
+			break_reg <= '0';
+			
+			key_held_reg <= '0';
+			
+			start_reg <= '0';
+			select_reg <= '0';
+			option_reg <= '0';
+			
+			virtual_up_reg <= '0';
+			virtual_down_reg <= '0';
+			virtual_left_reg <= '0';
+			virtual_right_reg <= '0';
+			virtual_stick_pressed_reg <= '0';
+			
+			system_reset_reg <= '0';
+		elsif (clk'event and clk='1') then
+			left_shift_pressed_reg <= left_shift_pressed_next;
+			right_shift_pressed_reg <= right_shift_pressed_next;
+			
+			left_control_pressed_reg <= left_control_pressed_next;
+			right_control_pressed_reg <= right_control_pressed_next;			
+			
+			kbcode_reg <= kbcode_next;
+			
+			interrupt_reg <= interrupt_next;
+			
+			break_reg <= break_next;
+			
+			key_held_reg <= key_held_next;
+			
+			start_reg <= start_next;
+			select_reg <= select_next;
+			option_reg <= option_next;
+			
+			virtual_up_reg <= virtual_up_next;
+			virtual_down_reg <= virtual_down_next;
+			virtual_left_reg <= virtual_left_next;
+			virtual_right_reg <= virtual_right_next;
+			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+			
+			system_reset_reg <= system_reset_next;
+		end if;
+	end process;
+	
+	-- update key pressed
+	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg)
+	begin
+		left_shift_pressed_next <= left_shift_pressed_reg;
+		right_shift_pressed_next <= right_shift_pressed_reg;
+		
+		left_control_pressed_next <= left_control_pressed_reg;
+		right_control_pressed_next <= right_control_pressed_reg;		
+	
+		kbcode_next <= kbcode_reg;
+		interrupt_next <= '0';
+		
+		break_next <= break_reg;
+	
+		start_next <= start_reg;
+		select_next <= select_reg;
+		option_next <= option_reg;
+		
+		virtual_up_next <= virtual_up_reg;
+		virtual_down_next <= virtual_down_reg;
+		virtual_left_next <= virtual_left_reg;
+		virtual_right_next <= virtual_right_reg;				
+		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+		
+		system_reset_next <= system_reset_reg;
+		
+		key_held_next <= key_held_reg;
+		
+		no_kbcode_update <= '0';
+	
+		-- Core functionality exactly as the Atari layout
+		if (key_event = '1') then
+			interrupt_next <= not(key_up);			
+			key_held_next <= not(key_up);
+			
+			case key_extended&key_code is 
+			
+				-- Basic mapping - should allow all keys on Atari, just fiddly
+				when 
+					'0'&X"AA"|'1'&X"AA"|  -- BAT SUCCESSFUL
+					'0'&X"FC"|'1'&X"FC"   -- BAT FAIL
+					=>
+					no_kbcode_update <= '1';
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"4B" => --L
+					kbcode_next <= X"00";
+				when '0'&X"3B" => --J
+					kbcode_next <= X"01";					
+				when '0'&X"4C" => --;
+					kbcode_next <= X"02";										
+				when '0'&X"42" => --K
+					kbcode_next <= X"05";				
+				when '0'&X"79" => --+
+					kbcode_next <= X"06";
+				when '0'&X"7C" => --*
+					kbcode_next <= X"07";
+				when '0'&X"44" => --O
+					kbcode_next <= X"08";
+				when '0'&X"4D" => --P
+					kbcode_next <= X"0A";
+				when '0'&X"3C" => --U
+					kbcode_next <= X"0B";
+				when '0'&X"5A" => --Enter
+					kbcode_next <= X"0C";
+				when '0'&X"43" => --I
+					kbcode_next <= X"0D";
+				when '0'&X"4E" => -- -
+					kbcode_next <= X"0E";
+				when '0'&X"55" => -- =
+					kbcode_next <= X"0F";
+
+				when '0'&X"2A" => --V
+					kbcode_next <= X"10";
+				when '0'&X"05" => --Help (Using F1)
+					kbcode_next <= X"11";					
+				when '0'&X"21" => --C
+					kbcode_next <= X"12";										
+				when '0'&X"32" => --B
+					kbcode_next <= X"15";				
+				when '0'&X"22" => --X
+					kbcode_next <= X"16";
+				when '0'&X"1A" => --Z
+					kbcode_next <= X"17";
+				when '0'&X"25" => --4
+					kbcode_next <= X"18";
+				when '0'&X"26" => --3
+					kbcode_next <= X"1A";
+				when '0'&X"36" => --6
+					kbcode_next <= X"1B";
+				when '0'&X"76" => --Esc
+					kbcode_next <= X"1C";
+				when '0'&X"2E" => --5
+					kbcode_next <= X"1D";
+				when '0'&X"1E" => --2
+					kbcode_next <= X"1E";
+				when '0'&X"16" => --1
+					kbcode_next <= X"1F";
+
+				when '0'&X"41" => --,
+					kbcode_next <= X"20";
+				when '0'&X"29" => --Spc
+					kbcode_next <= X"21";					
+				when '0'&X"49" => --.
+					kbcode_next <= X"22";										
+				when '0'&X"31" => --N
+					kbcode_next <= X"23";
+				when '0'&X"3A" => --M
+					kbcode_next <= X"25";				
+				when '0'&X"4A" => --/
+					kbcode_next <= X"26";
+				when '1'&X"11" => --Inv
+					kbcode_next <= X"27";
+				when '0'&X"2D" => --R
+					kbcode_next <= X"28";
+				when '0'&X"24" => --E
+					kbcode_next <= X"2A";
+				when '0'&X"35" => --Y
+					kbcode_next <= X"2B";
+				when '0'&X"0D" => --Tab
+					kbcode_next <= X"2C";
+				when '0'&X"2C" => --T
+					kbcode_next <= X"2D";
+				when '0'&X"1D" => --W
+					kbcode_next <= X"2E";
+				when '0'&X"15" => --Q
+					kbcode_next <= X"2F";					
+					
+				when '0'&X"46" => --9
+					kbcode_next <= X"30";				
+				when '0'&X"45" => --0
+					kbcode_next <= X"32";										
+				when '0'&X"3D" => --7
+					kbcode_next <= X"33";
+				when '0'&X"66" => --Backspace
+					kbcode_next <= X"34";						
+				when '0'&X"3E" => --8
+					kbcode_next <= X"35";				
+				when '0'&X"54" => --< (using [)
+					kbcode_next <= X"36";
+				when '0'&X"5B" => --> (using ])
+					kbcode_next <= X"37";
+				when '0'&X"2B" => --F
+					kbcode_next <= X"38";
+				when '0'&X"33" => --H
+					kbcode_next <= X"39";					
+				when '0'&X"23" => --D
+					kbcode_next <= X"3A";
+				when '0'&X"58" => --Caps
+					kbcode_next <= X"3C";
+				when '0'&X"34" => --G
+					kbcode_next <= X"3D";
+				when '0'&X"1B" => --S
+					kbcode_next <= X"3E";
+				when '0'&X"1C" => --A
+					kbcode_next <= X"3F";
+
+				when '0'&X"77" => --Break - XXX BUG, also presses 14, since E1 ext code...
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+				when '1'&X"77" => --Break
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+					
+				-- XXX BUGS
+				-- i) press shift when already holding key - does not update kbcode
+				-- ii) press key, then press another, then release second key. Should go back to first...
+				when '0'&X"12" => --Left shift
+					no_kbcode_update <= '1';
+					left_shift_pressed_next <= not(key_UP);					
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"59" => --Right shift
+					no_kbcode_update <= '1';
+					right_shift_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+					
+				when '0'&X"14" => --Left control
+					no_kbcode_update <= '1';
+					left_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '1'&X"14" => --Right control
+					no_kbcode_update <= '1';
+					right_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';			
+					key_held_next <= '0';
+					
+				when '0'&X"06" => --Start (F2)
+					no_kbcode_update <= '1';
+					start_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"04" => --Select (F3)
+					no_kbcode_update <= '1';
+					select_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"0C" => --Option (F4)
+					no_kbcode_update <= '1';
+					option_next <= not(key_UP);
+					interrupt_next <= '0';					
+					key_held_next <= '0';
+
+				-- TODO will also be useful to cursor control...
+				when '1'&X"75" => -- up
+					no_kbcode_update <= '1';
+					virtual_up_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"72" => -- down
+					no_kbcode_update <= '1';
+					virtual_down_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"6b" => -- left
+					no_kbcode_update <= '1';
+					virtual_left_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"74" => -- right
+					no_kbcode_update <= '1';
+					virtual_right_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';
+				when '1'&X"27" => -- right windows key -> fire button
+					no_kbcode_update <= '1';
+					virtual_stick_pressed_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';					
+					
+				when '0'&X"07" => -- f12 => system reset
+					no_kbcode_update <= '1';
+					system_reset_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';										
+					
+				when others =>
+					no_kbcode_update <= '1';
+					-- nop
+				-- Idea: Use Windows key and Alt for atari shift/control. Then use keyboard ones for 'nice' mapping as displayed on keyboard?
+			end case;
+			
+			if (key_up = '1' or no_kbcode_update = '1') then
+				kbcode_next <= kbcode_reg;				
+			else
+				kbcode_next(7 downto 6) <= (left_control_pressed_reg or right_control_pressed_reg)&(left_shift_pressed_reg or right_shift_pressed_reg);
+			end if;
+		end if;
+		
+		-- Then override a few for convenience
+		-- e.g. if we press '#' on the keyboard we want to see '#' on the atari, even though on the atari its shift a different key.
+
+--http://atariwiki.de/wiki/Wiki.jsp?page=KBCODE
+-- 			$00	$01	$02	$03	$04	$05	$06	$07	$08	$09	$0A	$0B	$0C	$0D	$0E	$0F
+--		$00	L		J		;		F1		F2		K		+		*		O	 			P		U		CR		I		-		=
+--		$10	V		Help	C		F3		F4		B		X		Z		4	 			3		6		Esc	5		2		1
+--		$20	,		Spc	.		N	 			M		/		Inv	R	 			E		Y		Tab	T		W		Q
+--		$30	9	 			0		7		BS		8		<		>		F		H		D	 			Caps	G		S		A
+--together with Shift Key: add +$40
+--together with Control key: add +$80
+
+-- Would be great to have option of using real Atari keyboard, but probably not worthwhile yet.
+
+	end process;
+			
+	-- output
+	kbcode <= kbcode_reg;
+	KEY_HELD <= key_held_reg;
+	shift_pressed <= left_shift_pressed_reg or right_shift_pressed_reg;
+	break_pressed <= break_reg;
+	
+	key_interrupt <= interrupt_reg;
+	
+	consol_start <= start_reg;
+	consol_select <= select_reg;
+	consol_option <= option_reg;
+	
+	VIRTUAL_STICKS <= not(virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg&virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg);
+	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+	
+	system_reset <= system_reset_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/de1/ps2_keyboard.vhdl
===================================================================
--- unmerged/core/de1/ps2_keyboard.vhdl	(nonexistent)
+++ unmerged/core/de1/ps2_keyboard.vhdl	(revision 1)
@@ -0,0 +1,266 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+--	KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code
+	
+--	KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed
+--	SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held
+--	CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held
+--	BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers)
+
+ENTITY ps2_keyboard IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	PS2_CLK : IN STD_LOGIC;
+	PS2_DAT : IN STD_LOGIC;
+	
+	KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released
+	KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code
+	KEY_EXTENDED : OUT STD_LOGIC;           -- valid on event, if scan code extended
+	KEY_UP : OUT STD_LOGIC                 -- value on event, if key released
+);
+END ps2_keyboard;
+
+ARCHITECTURE vhdl OF ps2_keyboard IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	-- PS2 keyboard sends on its own clock high->low transition
+	-- start, 8 data bits, parity, stop
+	
+	-- Codes are either 1 bytes or 2 bytes (extended) on press
+	-- XX
+	-- EX YY
+	-- Codes are eighter 2 bytes or 3 bytes (extended) on release
+	-- F0 XX
+	-- EX F0 YY
+	
+	-- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77
+	
+	-- LSB first
+	-- Start bit 0
+	-- Stop bit 1
+	-- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7))
+	-- e.g. 
+	-- '0 1100 0010 0 1'
+	-- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0
+	
+
+	-- Receive raw data from ps2 serial interface
+	signal ps2_shiftreg_next : std_logic_vector(10 downto 0);
+	signal ps2_shiftreg_reg : std_logic_vector(10 downto 0);
+	
+	signal idle_next : std_logic_vector(3 downto 0);
+	signal idle_reg : std_logic_vector(3 downto 0);	
+
+	signal bitcount_next : std_logic_vector(3 downto 0);
+	signal bitcount_reg : std_logic_vector(3 downto 0);	
+	
+	signal enable_ps2 : std_logic;
+	
+	signal last_ps2_clk_next : std_logic;
+	signal last_ps2_clk_reg : std_logic;
+	
+	signal ps2_clk_reg : std_logic;
+	signal ps2_dat_reg : std_logic;
+	
+	signal parity : std_logic;
+	
+	-- Once we have whole parity checked bytes
+	signal byte_next : std_logic_vector(7 downto 0);
+	signal byte_reg : std_logic_vector(7 downto 0);
+	
+	signal byte_received_next : std_logic;
+	signal byte_received_reg : std_logic;	
+	
+	-- Decode if they are press(or repeat)/release or extended
+	signal pending_extended_next : std_logic;
+	signal pending_extended_reg : std_logic;
+	
+	signal pending_keyup_next : std_logic;
+	signal pending_keyup_reg : std_logic;
+	
+	-- To eventually get the code itself
+	signal key_event_next : std_logic;
+	signal key_event_reg : std_logic;
+	
+	signal key_value_next : std_logic_vector(9 downto 0);
+	signal key_value_reg : std_logic_vector(9 downto 0);
+	
+	-- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard
+	signal key_value_last_next : std_logic_vector(9 downto 0);
+	signal key_value_last_reg : std_logic_vector(9 downto 0);
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			ps2_clk_reg <= '0';
+			ps2_dat_reg <= '0';
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= '0';
+			
+			ps2_shiftreg_reg<= (others=>'0');		
+			idle_reg <= (others=>'0');
+			bitcount_reg <= (others=>'0');
+			
+			byte_received_reg <= '0';
+			byte_reg <= (others=>'0');
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= '0';
+			pending_keyup_reg <= '0';			
+
+			-- Output registers
+			key_event_reg <= '0';
+			key_value_reg <= (others=>'0');
+			
+			key_value_last_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			-- Raw interface
+			-- async - do we need some form of synchronizer?
+			ps2_clk_reg <= ps2_clk;
+			ps2_dat_reg <= ps2_dat;
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= last_ps2_clk_next;
+			
+			ps2_shiftreg_reg<= ps2_shiftreg_next;		
+			idle_reg <= idle_next;
+			bitcount_reg <= bitcount_next;
+			
+			byte_received_reg <= byte_received_next;
+			byte_reg <= byte_next;
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= pending_extended_next;
+			pending_keyup_reg <= pending_keyup_next;			
+
+			-- Output registers
+			key_event_reg <= key_event_next;
+			key_value_reg <= key_value_next;
+			
+			key_value_last_reg <= key_value_last_next;
+			
+		end if;
+	end process;
+
+	-- Divide clock by 256 to get approx 4*ps2 clock
+	enable_div : enable_divider
+		generic map (COUNT=>256)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2);
+	
+	-- capture bytes from ps2
+	parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor  ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1));
+	process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity)
+	begin	
+		ps2_shiftreg_next <= ps2_shiftreg_reg;
+		last_ps2_clk_next <= last_ps2_clk_reg;
+		
+		bitcount_next <= bitcount_reg;
+		
+		idle_next <= idle_reg;
+		
+		byte_received_next <= '0';
+		byte_next <= (others=>'0');
+		
+		if (enable_ps2 = '1') then		
+			last_ps2_clk_next <= ps2_clk_reg;
+			
+			-- sample on falling edge
+			if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then
+				ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1);
+				bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1);
+			end if;
+			
+			-- output to next stage when done
+			if (bitcount_reg = X"B") then
+				byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10);
+				byte_next <= ps2_shiftreg_reg(8 downto 1);
+				bitcount_next <= (others=>'0');
+			end if;
+			
+			-- reset if both high for a time period
+			idle_next <= std_logic_vector(unsigned(idle_reg) +1);
+			if (idle_reg = X"F") then
+				ps2_shiftreg_next <= (others=>'0');
+				bitcount_next <= (others=>'0');
+			end if;
+			if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then
+				idle_next <= X"0";
+			end if;		
+		end if;
+	end process;
+	
+	-- process bytes
+	process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg)
+	begin
+		pending_extended_next <=  pending_extended_reg;
+		pending_keyup_next <=  pending_keyup_reg;
+		
+		key_event_next <= '0';
+		key_value_next <= (others =>'0');
+		
+		key_value_last_next <= key_value_last_reg;
+		
+		if (byte_received_reg = '1') then		
+			case byte_reg is 
+				when X"E0" =>
+					pending_extended_next <= '1';					
+				when X"E1" =>
+					pending_extended_next <= '1';
+				when X"F0" =>
+					pending_keyup_next <= '1';
+				when others => 
+					pending_extended_next <= '0';
+					pending_keyup_next <= '0';	
+					
+					if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then
+						key_event_next <= '1';
+						key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+						
+						key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+					end if;
+			end case;
+		end if;
+	end process;
+			
+	-- Output
+	key_event <= key_event_reg;
+	key_value <= key_value_reg(7 downto 0);
+	key_extended <= key_value_reg(8);
+	key_up <= key_value_reg(9);
+		
+END vhdl;
Index: unmerged/core/de1/sdram_statemachine.vhdl
===================================================================
--- unmerged/core/de1/sdram_statemachine.vhdl	(nonexistent)
+++ unmerged/core/de1/sdram_statemachine.vhdl	(revision 1)
@@ -0,0 +1,515 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CKE : out std_logic;
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine;
+
+ARCHITECTURE vhdl OF sdram_statemachine IS
+	function repeat(N: natural; B: std_logic) 
+	return std_logic_vector
+	is
+	variable result: std_logic_vector(1 to N);
+	begin
+	for i in 1 to N loop
+	result(i) := B;
+	end loop;
+	return result;
+	end;
+
+	-- bits are: CS_n, RAS_n, CAS_n,WE_n
+	constant sdram_command_inhibit                  : std_logic_vector(3 downto 0) := "1000";
+	constant sdram_command_no_operation             : std_logic_vector(3 downto 0) := "0111";
+	constant sdram_command_device_burst_stop        : std_logic_vector(3 downto 0) := "0110";
+	constant sdram_command_read                     : std_logic_vector(3 downto 0) := "0101";
+	constant sdram_command_write                    : std_logic_vector(3 downto 0) := "0100";
+	constant sdram_command_bank_activate            : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
+	constant sdram_command_precharge                : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
+	constant sdram_command_mode_register            : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
+	constant sdram_command_refresh                  : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
+	
+	signal command_next : std_logic_vector(3 downto 0);
+	
+--	constant bank_state_idle                 : std_logic_vector(3 downto 0) := "0000";
+--	constant bank_state_row_active           : std_logic_vector(3 downto 0) := "0001";
+--	constant bank_state_read                 : std_logic_vector(3 downto 0) := "0010";
+--	constant bank_state_write                : std_logic_vector(3 downto 0) := "0011";
+--	constant bank_state_read_pre             : std_logic_vector(3 downto 0) := "0100";
+--	constant bank_state_write_pre            : std_logic_vector(3 downto 0) := "0101";
+--	constant bank_state_precharging          : std_logic_vector(3 downto 0) := "0111";
+--	constant bank_state_row_activating       : std_logic_vector(3 downto 0) := "1000";
+--	constant bank_state_write_recovering     : std_logic_vector(3 downto 0) := "1001";
+--	constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
+--	constant bank_state_refresh              : std_logic_vector(3 downto 0) := "1011";
+--	constant bank_state_mode_access          : std_logic_vector(3 downto 0) := "1100"; 
+--	constant bank_state_init                 : std_logic_vector(3 downto 0) := "1101"; 
+-- Banks each have their own state, but since read/write lines are shared they are not truly independent
+-- Also for auto-refresh all banks must be in idle state
+
+	constant sdram_state_powerup        : std_logic_vector(2 downto 0) := "000"; -- requires standard init
+	constant sdram_state_init           : std_logic_vector(2 downto 0) := "001"; -- requires standard init
+	constant sdram_state_idle           : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
+	constant sdram_state_refresh        : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
+	constant sdram_state_read           : std_logic_vector(2 downto 0) := "100"; -- processing a read request
+	constant sdram_state_write          : std_logic_vector(2 downto 0) := "101"; -- processing a write request
+	constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
+	
+	signal sdram_state_next : std_logic_vector(2 downto 0);
+	signal sdram_state_reg : std_logic_vector(2 downto 0);
+	
+	signal delay_next : std_logic_vector(13 downto 0);
+	signal delay_reg : std_logic_vector(13 downto 0);
+	
+	signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
+	signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
+	
+	signal refresh_pending_next : std_logic_vector(11 downto 0);
+	signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
+	
+	signal suggest_refresh : std_logic; -- i.e. do we have any pending?
+	signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
+	signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time	
+	signal refreshing_now : std_logic;
+	
+	signal idle_priority : std_logic_vector(3 downto 0);
+
+	signal data_out_next : std_logic_vector(31 downto 0);
+	signal data_out_reg : std_logic_vector(31 downto 0);
+	
+	signal reply_next : std_logic;
+	signal reply_reg : std_logic;
+	
+	-- track the active bank
+	-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
+	-- CAS,NOP,NOP,DATA
+	-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
+	--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	
+	-- capture inputs
+	signal DATA_IN_snext      : std_logic_vector(31 downto 0);
+	signal DATA_IN_sreg       : std_logic_vector(31 downto 0);
+	signal ADDRESS_IN_snext   : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal ADDRESS_IN_sreg    : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal READ_EN_snext      : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal READ_EN_sreg       : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal WRITE_EN_snext     : std_logic;
+	signal WRITE_EN_sreg      : std_logic;	
+	signal dqm_mask_snext     : std_logic_vector(3 downto 0);
+	signal dqm_mask_sreg      : std_logic_vector(3 downto 0);
+	signal request_snext      : std_logic;
+	signal request_sreg       : std_logic;
+	signal refresh_snext      : std_logic;
+	signal refresh_sreg       : std_logic;
+	
+	-- slow clock output regs
+	signal DATA_OUT_snext     : std_logic_vector(31 downto 0);
+	signal DATA_OUT_sreg      : std_logic_vector(31 downto 0);
+	
+	signal reply_snext : std_logic;
+	signal reply_sreg  : std_logic;
+	
+	-- sdram output registers 
+	signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_next : std_logic_vector(15 downto 0);
+	signal dq_output_next : std_logic;
+	signal dq_in_next  : std_logic_vector(15 downto 0);	
+	signal ba_next : std_logic_vector(1 downto 0);
+	signal cs_n_next : std_logic;
+	signal ras_n_next : std_logic;
+	signal cas_n_next : std_logic;
+	signal we_n_next : std_logic;
+	signal ldqm_next : std_logic;
+	signal udqm_next : std_logic;
+	signal cke_next : std_logic;
+	
+	signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_reg : std_logic_vector(15 downto 0);
+	signal dq_output_reg : std_logic;
+	signal ba_reg : std_logic_vector(1 downto 0);
+	signal cs_n_reg : std_logic;
+	signal ras_n_reg : std_logic;
+	signal cas_n_reg : std_logic;
+	signal we_n_reg : std_logic;
+	signal ldqm_reg : std_logic;
+	signal udqm_reg : std_logic;
+	signal cke_reg : std_logic;
+	
+BEGIN
+	-- register
+	process(CLK_SDRAM,reset_n)
+	begin
+		if (reset_N = '0') then
+			sdram_state_reg <= sdram_state_init;
+			delay_reg <= (others=>'0');
+			refresh_pending_reg <= (others=>'0');
+			cycles_since_refresh_reg <= (others=>'0');
+			data_out_reg <= (others=>'0');
+			reply_reg <= '0';
+			
+			addr_reg <= (others => '0');
+			dq_out_reg <= (others=> '0');
+			dq_output_reg <= '0';
+			ba_reg <= (others=>'0');
+			cs_n_reg <= '0';
+			ras_n_reg <= '0';
+			cas_n_reg <= '0';
+			we_n_reg <= '0';
+			ldqm_reg <= '1';
+			udqm_reg <= '1';
+			cke_reg <= '0';
+			
+			--bank_row_reg <= (others=>(others=>'0'));
+		elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
+			sdram_state_reg <= sdram_state_next;
+			delay_reg <= delay_next;
+			refresh_pending_reg <= refresh_pending_next;
+			cycles_since_refresh_reg <= cycles_since_refresh_next;
+			data_out_reg <= data_out_next;
+			reply_reg <= reply_next;
+			
+			addr_reg <= addr_next;
+			dq_out_reg <= dq_out_next;
+			dq_output_reg <= dq_output_next;
+			ba_reg <= ba_next;
+			cs_n_reg <= cs_n_next;
+			ras_n_reg <= ras_n_next;
+			cas_n_reg <= cas_n_next;
+			we_n_reg <= we_n_next;
+			ldqm_reg <=ldqm_next;
+			udqm_reg <= udqm_next;
+			cke_reg <= cke_next;
+			
+			--bank_row_reg <= bank_row_next;
+		end if;
+	end process;
+
+	-- register request	
+	process(CLK_SYSTEM,reset_n)
+	begin
+		if (reset_N = '0') then
+			data_in_sreg <= (others=>'0');
+			address_in_sreg <= (others=>'0');
+			read_en_sreg <= '0';
+			write_en_sreg <= '0';
+			request_sreg <= '0';
+			dqm_mask_sreg <= (others=>'1');
+			refresh_sreg <= '0';
+			
+			data_out_sreg <= (others=>'0');
+			reply_sreg <= '0';
+		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+			data_in_sreg <= data_in_snext;
+			address_in_sreg <= address_in_snext;
+			read_en_sreg <= read_en_snext;
+			write_en_sreg <= write_en_snext;
+			request_sreg <= request_snext;
+			dqm_mask_sreg <= dqm_mask_snext;
+			refresh_sreg <= refresh_snext;
+			
+			data_out_sreg <= data_out_snext;
+			reply_sreg <= reply_snext;
+		end if;
+	end process;
+
+	-- Inputs - NB, clocked at a smaller multiple
+	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, request, byte_access, word_access, longword_access, refresh)
+	begin
+		data_in_snext <= data_in_sreg;
+		address_in_snext <= address_in_sreg;
+		read_en_snext <= read_en_sreg;
+		write_en_snext <= write_en_sreg;
+		request_snext <= request_sreg;
+		dqm_mask_snext <= dqm_mask_sreg;
+		
+		refresh_snext <= refresh; -- independent of memory requests
+	
+		-- only snap inputs on new request
+		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+		if ((request xor request_sreg) = '1') then
+			data_in_snext <= data_in;
+			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+			read_en_snext <= read_en;
+			write_en_snext <= write_en;
+			request_snext <= request;
+			
+			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+			dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
+			dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
+		end if;
+	end process;
+	
+	-- refresh counters
+	process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
+	begin
+		cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
+		refresh_pending_next <= refresh_pending_reg;
+		suggest_refresh <= '0';
+		force_refresh <= '0';
+		
+		if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
+			suggest_refresh <= '1';
+		end if;
+		
+		if (refresh_pending_reg = X"FFF") then
+			force_refresh <= '1';
+		end if;
+		
+		require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
+		
+		if (refreshing_now = '1') then
+			-- refreshing right now
+			cycles_since_refresh_next <= (others=>'0');
+			
+			-- This is one of our pending refreshes (if we have any)			
+			if (suggest_refresh = '1') then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
+			end if;
+		else
+			if (cycles_since_refresh_reg = "11111111111") then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
+				cycles_since_refresh_next <= (others=>'0');
+			end if;
+		end if;
+
+	end process;
+	
+	--
+	process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
+	begin
+		idle_priority <= (others=>'0');
+		refreshing_now <= '0';
+	
+		sdram_state_next <= sdram_state_reg;
+		
+		command_next <= sdram_command_no_operation;
+		
+		delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
+		
+		data_out_next <= data_out_reg;
+		reply_next <= reply_reg;
+		
+		-- Set some default for when we're sending NOP
+		dq_out_next <= (others=>'0');
+		dq_output_next <= '0';
+		cke_next <= '1';
+		ldqm_next <= '1';
+		udqm_next <= '1';
+		ba_next <= (others=>'0');
+		addr_next <= (others=>'1');
+
+		-- TODO - use bank states!!
+		-- TODO - MUCH MORE SMART STUFF!
+		-- Lets do them once we have Hello World running...
+		case sdram_state_reg is
+		when sdram_state_powerup =>			
+			-- wait 100us (min)
+			if (delay_reg(13) = '1') then
+				sdram_state_next <= sdram_state_init_precharge;
+				delay_next <= (others=>'0');
+			end if;			
+		when sdram_state_init =>			
+			case delay_reg(5 downto 3)&delay_reg(0) is
+			when "0001" =>
+				command_next <= sdram_command_precharge;
+				addr_next(AP_BIT) <= '1'; --all banks
+			when "0010" =>
+				command_next <= sdram_command_refresh;				
+				-- cke still high, so auto refresh
+			when "0100" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+			when "1000" =>
+				command_next <= sdram_command_mode_register;
+				--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
+				addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
+				addr_next(3) <= '0'; -- sequential
+				addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
+				addr_next(8 downto 7) <= "00"; -- standard operation
+				addr_next(9) <= '0'; -- programmed burst access - of single cycle!
+				addr_next(11 downto 10) <= "00"; -- reserved
+			when "1010" =>
+				sdram_state_next <= sdram_state_idle;
+				delay_next <= (others=>'0');
+			when others =>
+				-- nop
+			end case;
+		when sdram_state_idle =>
+			delay_next <= (others=>'0');						
+			
+			idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
+			case idle_priority is -- priority encoder...
+			when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
+				sdram_state_next <= sdram_state_refresh;
+			when "1010"|"1011" =>				
+				sdram_state_next <= sdram_state_write;
+			when "1001" =>
+				sdram_state_next <= sdram_state_read;
+			when others =>
+				-- stay here
+			end case;
+		when sdram_state_read =>
+			-- TODO - if same bank we can save some time... ?
+			-- Only do precharge on switching bank?
+				
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_read;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+			when X"4" =>  -- command actually sent now
+				ldqm_next <= dqm_mask_sreg(0);  -- for first read
+				udqm_next <= dqm_mask_sreg(1);
+			
+			when X"5" =>  -- dqm for 1st read is sent
+				ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
+				udqm_next <= dqm_mask_sreg(3);				
+			when X"7" => 
+				data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				data_out_next(15 downto 8) <= dq_in_next(15 downto 8);				
+			when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
+				data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
+				data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
+				
+				reply_next <= request_sreg;
+				sdram_state_next <= sdram_state_idle;
+				-- after 3 cycles we can do the next ACT (21 ns psc)
+				-- TODO - directly switch to next action so as not to waste a cycle
+			when others =>
+			end case;				
+		when sdram_state_write =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_write; 
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
+				dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
+				ldqm_next <= dqm_mask_sreg(0);
+				udqm_next <= dqm_mask_sreg(1);
+			when X"4" =>
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
+				ldqm_next <= dqm_mask_sreg(2);
+				udqm_next <= dqm_mask_sreg(3);
+
+				reply_next <= request_sreg;				
+			when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
+				sdram_state_next <= sdram_state_idle;		
+				-- TODO - directly switch to next action to match read
+			when others =>
+			end case;				
+		when sdram_state_refresh =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+				refreshing_now <= '1';
+			when X"8" =>
+				sdram_state_next <= sdram_state_idle;
+			when others =>
+			end case;
+		when others =>
+			sdram_state_next <= sdram_state_init;			
+		end case;
+	end process;
+	
+	-- command_next directly translates to lines to send
+	-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
+	process(command_next)
+	begin
+		cs_n_next <= command_next(3);
+		ras_n_next <= command_next(2);
+		cas_n_next <= command_next(1);
+		we_n_next <= command_next(0);
+	end process;
+	
+	-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
+	SDRAM_ADDR <= addr_reg;
+	SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
+	SDRAM_BA0 <= ba_reg(0);
+	SDRAM_BA1 <= ba_reg(1);
+	SDRAM_CS_N <= cs_n_reg;
+	SDRAM_RAS_N <= ras_n_reg;
+	SDRAM_CAS_N <= cas_n_reg;
+	SDRAM_WE_N <= we_n_reg;
+	SDRAM_ldqm <= ldqm_reg;
+	SDRAM_udqm <= udqm_reg;
+	SDRAM_CKE <= cke_reg;
+	
+	-- inputs from SDRAM
+	dq_in_next <= SDRAM_DQ;
+	
+	-- back to slower clock
+	reply_snext <= reply_reg;
+	data_out_snext <= data_out_reg;
+	
+	-- outputs to rest of system
+	REPLY <= reply_sreg;
+	DATA_OUT <= DATA_OUT_sreg;
+		
+END vhdl;
Index: unmerged/core/de1/sram.vhdl
===================================================================
--- unmerged/core/de1/sram.vhdl	(nonexistent)
+++ unmerged/core/de1/sram.vhdl	(revision 1)
@@ -0,0 +1,143 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY sram IS
+PORT 
+( 
+	ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+	DIN : IN STD_LOGIC_vector(15 downto 0);
+	WREN : IN STD_LOGIC;
+	
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	request : in std_logic;
+	
+	width_16bit : in std_logic;
+	
+	-- SRAM interface
+	SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
+	SRAM_CE_N: OUT STD_LOGIC;
+	SRAM_OE_N: OUT STD_LOGIC;
+	SRAM_WE_N: OUT STD_LOGIC;
+
+	SRAM_LB_N: OUT STD_LOGIC;
+	SRAM_UB_N: OUT STD_LOGIC;
+	
+	SRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
+	complete : out std_logic
+);
+
+END sram;
+
+-- TODO, implement 32-bit accesses in two cycles
+
+-- first cycle, capture inputs
+-- second cycle, sram access
+ARCHITECTURE slow OF sram IS
+	signal oe_n_next : std_logic;
+	signal oe_n_reg : std_logic;
+	
+	signal we_n_next : std_logic;
+	signal we_n_reg : std_logic;	
+	
+	signal data_next : std_logic_vector(15 downto 0);
+	signal data_reg : std_logic_vector(15 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+	signal low_byte : std_logic_vector(7 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			oe_n_reg <= '1';
+			we_n_reg <= '1';
+			data_reg <= (others=>'0');
+			request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			oe_n_reg <= oe_n_next;
+			we_n_reg <= we_n_next;
+			data_reg <= data_next;
+			request_reg <= request_next;
+		end if;
+	end process;
+
+	-- next state
+	process(din,wren,request,request_reg,width_16bit)
+	begin		
+		data_next <= din;
+		request_next <= '0';
+		
+		oe_n_next <= '0';
+		we_n_next <= '1';
+		
+		if (width_16bit = '0') then
+			data_next <= din(7 downto 0)&din(7 downto 0);
+		end if;
+		
+		if (request = '1') then
+			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
+			oe_n_next <= wren;
+			we_n_next <= not(wren);		
+			request_next <= '1';
+		end if;
+	end process;
+	
+	LOW_BYTE <= SRAM_DQ(7 downto 0) when address(0)='0' else SRAM_DQ(15 downto 8);
+	
+	-- output
+	SRAM_ADDR <= address(18 downto 1);
+	SRAM_CE_N <= '0';
+	SRAM_OE_N <= oe_n_reg;
+	SRAM_WE_N <= we_n_reg;
+	SRAM_LB_N <= not(width_16bit) and address(0);
+	SRAM_UB_N <= not(width_16bit) and NOT(address(0));
+	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+
+	DOUT <= SRAM_DQ(15 downto 8)&LOW_BYTE;
+			
+	complete <= request_reg;		
+		
+	--GPIO <= (others=>'0');
+END slow;
+
+--ARCHITECTURE fast OF sram IS
+--	signal we_n : std_logic;
+--	signal dq : std_logic_vector(7 downto 0);
+--	
+--BEGIN
+--	we_n <= not(clk) nand WREN;
+--	dq <= SRAM_DQ(7 downto 0) when address(0)='0' else
+--		SRAM_DQ(15 downto 8);
+--		
+--	-- output
+--	SRAM_ADDR <= ADDRESS(18 downto 1);
+--	--SRAM_ADDR <= ADDRESS(17 downto 0);
+--	SRAM_CE_N <= '0';
+--	SRAM_OE_N <= WREN;
+--	SRAM_WE_N <= we_n;
+--	
+--	SRAM_LB_N <= ADDRESS(0);
+--	SRAM_UB_N <= NOT(ADDRESS(0));
+--	--SRAM_LB_N <= '0';
+--	--SRAM_UB_N <= '0';
+--		
+--	DOUT <= dq;		
+--	SRAM_DQ <= DIN&DIN when wren='1' else (others=>'Z');
+--	
+--	-- immediate completion
+--	complete <= request;
+--END fast;
\ No newline at end of file
Index: unmerged/core/de1/poly_17_9.vhdl
===================================================================
--- unmerged/core/de1/poly_17_9.vhdl	(nonexistent)
+++ unmerged/core/de1/poly_17_9.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_17_9 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC;
+	
+	RAND_OUT : OUT std_logic_vector(7 downto 0)
+);
+END poly_17_9;
+
+ARCHITECTURE vhdl OF poly_17_9 IS
+	signal shift_reg: std_logic_vector(16 downto 0);
+	signal shift_next: std_logic_vector(16 downto 0);
+	
+	signal feedback : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010101010101010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state (as pokey decap)
+	feedback <= shift_reg(13) xnor shift_reg(8);
+	process(enable,shift_reg,feedback,select_9_17,init)
+	begin
+		shift_next <= shift_reg;
+		
+		if (enable = '1') then	
+			shift_next(15 downto 8) <= shift_reg(16 downto 9);	
+			shift_next(7) <= feedback;
+			shift_next(6 downto 0) <= shift_reg(7 downto 1);
+
+			shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
+		end if;
+	end process;
+	
+		-- output
+	bit_out <= shift_reg(9);
+	RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
+		
+END vhdl;
Index: unmerged/core/de1/reg_file.vhdl
===================================================================
--- unmerged/core/de1/reg_file.vhdl	(nonexistent)
+++ unmerged/core/de1/reg_file.vhdl	(revision 1)
@@ -0,0 +1,85 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END reg_file;
+
+ARCHITECTURE vhdl OF reg_file IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+
+	type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
+
+	signal digit_next : reg_file_type;
+	signal digit_reg : reg_file_type;
+	
+	signal addr_decoded : std_logic_vector(2**width-1 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => WIDTH)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(digit_reg,addr_decoded,data_in,WR_EN)
+	begin
+		digit_next <= digit_reg;
+		
+		if (WR_EN = '1') then		
+			comp_gen:
+			for i in 0 to (BYTES-1) loop
+				if (addr_decoded(i) = '1') then				
+					digit_next(i) <= data_in;
+				end if;
+			end loop;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	-- output
+	process(addr_decoded,digit_reg)
+	begin
+		data_out <= X"FF";
+		comp_gen:
+		for i in 0 to (BYTES-1) loop
+			if (addr_decoded(i) = '1') then				
+				data_out <= digit_reg(i);
+			end if;
+		end loop;	
+	end process;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/de1/shared_enable.vhdl
===================================================================
--- unmerged/core/de1/shared_enable.vhdl	(nonexistent)
+++ unmerged/core/de1/shared_enable.vhdl	(revision 1)
@@ -0,0 +1,163 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY shared_enable IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;	
+	RESET_N : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	MEMORY_READY_ANTIC : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	PAUSE_6502 : in std_logic;
+	THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
+
+	POKEY_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same
+	ANTIC_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same - 1 cycle early
+	oldcpu_enable : OUT STD_LOGIC;     -- always about 1.79MHz to keep sound the same - expanded to next ready
+	CPU_ENABLE_OUT : OUT STD_LOGIC;    -- for compatibility run at 1.79MHz, for speed run as fast as we can
+	
+	SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC; -- double antic's rate - due to high-res mode
+	SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC -- four times antic's rate - due to high-res mode
+	
+	-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by 31 cycles vs CPU_ENABLE (when in 1.79MHz mode)
+	-- XXX watch out on clock speed change from 56MHz!
+);
+END shared_enable;
+
+ARCHITECTURE vhdl OF shared_enable IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;		
+	
+	signal enable_179 : std_logic;
+	signal enable_179_early : std_logic;
+	signal enable_179_late : std_logic;
+	signal cpu_enable : std_logic;
+	
+	signal cpu_extra_enable_next : std_logic;
+	signal cpu_extra_enable_reg : std_logic;
+	
+	signal turbo_next : std_logic;
+	signal turbo_reg : std_logic;	
+
+	signal throttle_count_next : std_logic_vector(5 downto 0);
+	signal throttle_count_reg : std_logic_vector(5 downto 0);	
+	
+	-- TODO - clean up
+	signal oldcpu_extra_enable_next : std_logic;
+	signal oldcpu_extra_enable_reg : std_logic;
+	signal enable_179_expanded : std_logic;
+	
+	signal memory_ready : std_logic;
+begin
+	-- instantiate some clock calcs
+	SCANDOUBLER_ENABLE_HIGH <= '1';
+		
+	sl_enable_colour_clock_div : enable_divider
+		generic map (COUNT=>2)
+		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
+
+	enable_179_clock_div : enable_divider
+		--generic map (COUNT=>16)
+		generic map (COUNT=>32)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
+		
+	process(THROTTLE_COUNT_6502, throttle_count_reg, enable_179)
+	begin
+		turbo_next <= '0';
+		throttle_count_next <= std_logic_vector(unsigned(throttle_count_reg) + 1);
+
+		--011111/31/1f = run every 32 cycles
+		
+		if (throttle_count_reg = THROTTLE_COUNT_6502) then
+			throttle_count_next <= (others=>'0');
+			turbo_next <= '1';
+		end if;
+		
+		if (enable_179 = '1') then -- synchronize
+			throttle_count_next <= "000001";
+		end if;
+		--0000000000111111111122222222223333
+		--0123456789012345678901234567890123
+		--X-------------------------------X
+		--
+		--000000000011111111112222222222333
+		--R12345678901234567890123456789012
+		---------------------------------NT
+		
+		--000000000011111100000000001111111
+		--R12345678901234501234567890123456
+		-----------------NT--------------NT
+	end process;
+
+	delay_line_phase : delay_line
+		--generic map (COUNT=>15)
+		generic map (COUNT=>31)
+		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+
+	delay_line_phase2 : delay_line
+		--generic map (COUNT=>15)
+		generic map (COUNT=>16)
+		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+	
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			cpu_extra_enable_reg <= '0';
+			oldcpu_extra_enable_reg <= '0';
+			turbo_reg <= '0';
+			throttle_count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then										
+			cpu_extra_enable_reg <= cpu_extra_enable_next;
+			oldcpu_extra_enable_reg <= oldcpu_extra_enable_next;
+			turbo_reg <= turbo_next;
+			throttle_count_reg <= throttle_count_next;
+		end if;
+	end process;
+	
+	-- next state
+	memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
+	cpu_enable <= (turbo_reg or cpu_extra_enable_reg or enable_179) and not(pause_6502);
+	cpu_extra_enable_next <= cpu_enable and not(memory_ready);
+	
+	oldcpu_extra_enable_next <= enable_179_expanded and not(memory_ready);
+	enable_179_expanded <= oldcpu_extra_enable_reg or enable_179;
+	
+	-- output
+	POKEY_ENABLE_179 <= enable_179_late; -- aka enable_179_late!  TODO!!!
+	oldcpu_enable <= enable_179_expanded;
+	ANTIC_ENABLE_179 <= enable_179_early;
+	
+	CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
+
+end vhdl;
Index: unmerged/core/de1/synchronizer.vhdl
===================================================================
--- unmerged/core/de1/synchronizer.vhdl	(nonexistent)
+++ unmerged/core/de1/synchronizer.vhdl	(revision 1)
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END synchronizer;
+
+ARCHITECTURE vhdl OF synchronizer IS
+	signal ff_next : std_logic_vector(2 downto 0);
+	signal ff_reg : std_logic_vector(2 downto 0);
+begin
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then						
+			ff_reg <= ff_next;	
+		end if;
+	end process;
+	
+	ff_next <= RAW&ff_reg(2 downto 1);
+	
+	SYNC <= ff_reg(0);
+
+end vhdl;
+
+
Index: replay/sdcard/atari800.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/atari800.bin
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: replay/sdcard/osborig.rom
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/osborig.rom
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: replay/sdcard/xlorig.rom
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: replay/sdcard/xlorig.rom
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: replay/tb/Replay_tb.vhd
===================================================================
--- replay/tb/Replay_tb.vhd	(nonexistent)
+++ replay/tb/Replay_tb.vhd	(revision 1)
@@ -0,0 +1,1109 @@
+library ieee;
+  use ieee.std_logic_1164.all;
+  use ieee.std_logic_unsigned.all;
+  use ieee.numeric_std.all;
+  use ieee.std_logic_textio.all;
+
+library std_developerskit ; -- used for to_string
+--  use std_developerskit.std_iopak.all;
+
+  use work.Replay_Pack.all;
+
+entity Replay_tb is
+end;
+
+architecture rtl of Replay_tb is
+
+  -- SYSCLK=4436250Hz, Nsys=1183, Msys=300, Psys=1 ... VIDCLK=27035651Hz, Nvid=2275, Mvid=284, Pvid=8
+  constant CLK_A_PERIOD : time := 1 us / (4*4*7.11631);
+  constant CLK_B_PERIOD : time := 1 us / 49.152 ;
+  constant CLK_C_PERIOD : time := 1 us / 27.010289;
+
+  constant PS2BITTIME : time := 60 uS;
+  constant SPIBITTIME : time := 40.00 ns;
+  --constant PS2BITTIME : time := 10 uS;
+
+  signal rs232_rxd            : bit1;
+  signal rs232_txd            : bit1;
+  signal rs232_cts            : bit1;
+  signal rs232_rts            : bit1;
+
+  signal joy_a                : word( 5 downto 0);
+  signal joy_b                : word( 5 downto 0);
+  signal io                   : word(54 downto 0);
+  signal aux_io               : word(39 downto 0);
+  signal aux_ip               : word(22 downto 0);
+
+  signal mem_addr             : word(14 downto 0);
+  signal mem_dq               : word(15 downto 0);
+  signal mem_dqs              : word(1 downto 0);
+  signal mem_dm               : word(1 downto 0);
+--  signal mem_udqs             : bit1; -- Ctrl8
+--  signal mem_ldqs             : bit1; -- Ctrl7
+--  signal mem_udm              : bit1; -- Ctrl6
+--  signal mem_ldm              : bit1; -- Ctrl5
+  signal mem_cs               : bit1; -- Ctrl4
+  signal mem_ras              : bit1; -- Ctrl3
+  signal mem_cas              : bit1; -- Ctrl2
+  signal mem_we               : bit1; -- Ctrl1
+  signal mem_cke              : bit1; -- Ctrl0
+  signal mem_clk_p            : bit1;
+  signal mem_clk_n            : bit1;
+
+  signal disk_led             : bit1;
+  signal pwr_led              : bit1;
+
+  signal Ext_Rst_L            : bit1;
+  signal b2v5_io_1            : bit1;
+  signal b2v5_io_0            : bit1;
+
+  signal video_clk_p          : bit1;
+  signal video_clk_n          : bit1;
+  signal video_rst_l          : bit1;
+  signal video_int            : bit1;
+  signal video_de             : bit1;
+  signal video_v              : bit1;
+  signal video_h              : bit1;
+  signal video_data           : word(11 downto 0);  --Video11..0
+  signal video_ddc_clk        : bit1;
+  signal video_ddc_data       : bit1;
+  signal video_hsync          : bit1;
+  signal video_vsync          : bit1;
+  signal video_spc            : bit1;
+  signal video_spd            : bit1;
+
+  signal audio_lrcin          : bit1;
+  signal audio_mclk           : bit1;
+  signal audio_bckin          : bit1;
+  signal audio_din            : bit1;
+
+  signal ps2_clk              : word(1 downto 0);
+  signal ps2_data             : word(1 downto 0);
+
+  signal scl                  : bit1;
+  signal sda                  : bit1;
+
+  signal fpga_ctrl            : word(1 downto 0);
+  signal fpga_spi_clk         : bit1;
+  signal fpga_spi_mosi        : bit1;
+  signal fpga_spi_miso        : bit1;
+
+  --signal ssc_tf               : bit1;
+  --signal ssc_td               : bit1;
+  --signal ssc_rk               : bit1;
+  --signal ssc_rd               : bit1;
+
+  signal clk_68k              : bit1;
+  signal clk_aux              : bit1;
+
+  signal clk_a                : bit1;
+  signal clk_b                : bit1;
+  signal clk_c                : bit1;
+  --
+  signal por                  : bit1;
+  signal por_l                : bit1;
+
+  signal ps2_clk_drive_tx     : word(1 downto 0) := "11";
+  signal ps2_data_drive_tx    : word(1 downto 0) := "11";
+  signal ps2_clk_drive_rx     : word(1 downto 0) := "11";
+  signal ps2_data_drive_rx    : word(1 downto 0) := "11";
+  signal ps2_send_active      : word(1 downto 0) := "00";
+  signal ps2_slave_rx         : bit1;
+  signal ps2_slave_data       : word(8 downto 0);
+  --{{{
+  component ddr
+  port (
+    DQ    : inout std_logic_vector(15 downto 0);
+    DQS   : inout std_logic_vector( 1 downto 0);
+    ADDR  : in    std_logic_vector(12 downto 0);
+    BA    : in    std_logic_vector( 1 downto 0);
+    CLK   : in    std_logic;
+    CLK_N : in    std_logic;
+    CKE   : in    std_logic;
+    CS_N  : in    std_logic;
+    RAS_N : in    std_logic;
+    CAS_N : in    std_logic;
+    WE_N  : in    std_logic;
+    DM    : in    std_logic_vector( 1 downto 0)
+  );
+  end component;
+  --}}}
+
+begin
+  p_clk_gen_a : process
+  begin
+  clk_a <= '1';
+  wait for CLK_A_PERIOD/2;
+  clk_a <= '0';
+  wait for CLK_A_PERIOD - (CLK_A_PERIOD/2 );
+  end process;
+
+  p_clk_gen_b : process
+  begin
+  clk_b <= '1';
+  wait for CLK_B_PERIOD/2;
+  clk_b <= '0';
+  wait for CLK_B_PERIOD - (CLK_B_PERIOD/2 );
+  end process;
+
+  p_clk_gen_c : process
+  begin
+  clk_c <= '1';
+  wait for CLK_C_PERIOD/2;
+  clk_c <= '0';
+  wait for CLK_C_PERIOD - (CLK_C_PERIOD/2 );
+  end process;
+
+  p_rst                  : process
+  begin
+  por <= '1'; por_l <= '0';
+  wait until rising_edge(clk_c);
+  wait until rising_edge(clk_c);
+  wait until rising_edge(clk_c);
+  wait until rising_edge(clk_c);
+  por <= '0'; por_l <= '1';
+  wait;
+  end process;
+
+  Ext_Rst_L  <= por_l;
+
+  -- core
+  u_Replay : entity work.Replay_Top
+  port map (
+    -- RS232 debug port
+    i_RS232_RXD           => rs232_rxd,
+    o_RS232_TXD           => rs232_txd,
+    i_RS232_CTS           => rs232_cts,
+    o_RS232_RTS           => rs232_rts,
+    -- Joysticks
+    i_Joy_A               => joy_a,
+    i_Joy_B               => joy_b,
+    -- IO
+    b_IO                  => io,
+    b_Aux_IO              => aux_io,
+    i_Aux_IP              => aux_ip,
+    -- DRAM
+    o_Mem_Addr            => mem_addr,
+    b_Mem_DQ              => mem_dq,
+    b_Mem_UDQS            => mem_dqs(1), --mem_udqs,
+    b_Mem_LDQS            => mem_dqs(0), --mem_ldqs,
+    o_Mem_UDM             => mem_dm(1), --mem_udm,
+    o_Mem_LDM             => mem_dm(0), --mem_ldm,
+    o_Mem_CS              => mem_cs,
+    o_Mem_RAS             => mem_ras,
+    o_Mem_CAS             => mem_cas,
+    o_Mem_WE              => mem_we,
+    o_Mem_CKE             => mem_cke,
+    o_Mem_Clk_P           => mem_clk_p,
+    o_Mem_Clk_N           => mem_clk_n,
+    --
+    o_Disk_Led            => disk_led,
+    o_Pwr_Led             => pwr_led,
+    --
+    i_Ext_Rst_L           => Ext_Rst_L,
+    b_2V5_IO_1            => b2v5_io_1,
+    b_2V5_IO_0            => b2v5_io_0,
+    -- Video
+    o_Video_Clk_P         => video_clk_p,
+    o_Video_Clk_N         => video_clk_n,
+    o_Video_Rst_L         => video_rst_l,
+    i_Video_Int           => video_int,
+    o_Video_DE            => video_de,
+    o_Video_V             => video_v,
+    o_Video_H             => video_h,
+    o_Video_Data          => video_data,
+    b_Video_DDC_Clk       => video_ddc_clk,
+    b_Video_DDC_Data      => video_ddc_data,
+    o_Video_HSync         => video_hsync,
+    o_Video_VSync         => video_vsync,
+    b_Video_SPC           => video_spc,
+    b_Video_SPD           => video_spd,
+    -- Audio
+    o_Audio_LRCIN         => audio_lrcin,
+    o_Audio_MCLK          => audio_mclk,
+    o_Audio_BCKIN         => audio_bckin,
+    o_Audio_DIN           => audio_din,
+    --
+    b_PS2A_Clk            => ps2_clk(0),
+    b_PS2A_Data           => ps2_data(0),
+    b_PS2B_Clk            => ps2_clk(1),
+    b_PS2B_Data           => ps2_data(1),
+
+    b_SCL                 => scl,
+    b_SDA                 => sda,
+
+    -- System control
+    i_FPGA_Ctrl0          => fpga_ctrl(0),
+    i_FPGA_Ctrl1          => fpga_ctrl(1),
+    i_FPGA_SPI_Clk        => fpga_spi_clk,
+    b_FPGA_SPI_MOSI       => fpga_spi_mosi,
+    b_FPGA_SPI_MISO       => fpga_spi_miso,
+
+    -- SSC & config pins
+    --i_SSC_TF              => ssc_tf,
+    --i_SSC_TD              => ssc_td,
+    --o_SSC_RK              => ssc_rk,
+    --o_SSC_RD              => ssc_rd,
+    o_SSC_RD              => open,
+
+    -- Clocks
+    o_Clk_68K             => clk_68k,
+    b_Clk_Aux             => clk_aux,
+    ClK_A                 => clk_a,
+    ClK_B                 => clk_b,
+    ClK_C                 => clk_c
+    );
+
+  rs232_rxd <= '0';
+  rs232_cts <= '0';
+
+  joy_a <= "000000";
+  joy_b <= "000000";
+  io    <= (others => 'Z');
+
+  aux_io <= (others => 'Z');
+  aux_ip <= (others => '0');
+  mem_dq <= (others => 'Z');
+
+  mem_dqs <= "ZZ";
+--  mem_udqs <= 'Z';
+--  mem_ldqs <= 'Z';
+
+  b2v5_io_1 <= 'Z';
+  b2v5_io_0 <= 'Z';
+
+  video_int <= '0';
+  video_ddc_clk <= '0';
+  video_ddc_data <= '0';
+
+  clk_aux <= 'Z';
+
+  p_i2c_test : process
+  -- chrontel
+  -- EC write  1110110x
+  -- ED read
+  constant I2CBITTIME : time := 2.5 uS;
+
+  procedure I2CStart is
+  begin
+    scl <= 'H';
+    sda <= 'H';
+    -- start bit
+    wait for I2CBITTIME/4;
+    sda <= '0';
+    wait for I2CBITTIME/4;
+  end procedure;
+
+  procedure I2CReStart is
+  begin
+    scl <= '0';
+    sda <= 'H';
+    wait for I2CBITTIME/2;
+    scl <= 'H';
+    wait for I2CBITTIME/4;
+    sda <= '0';
+    wait for I2CBITTIME/4;
+    scl <= '0';
+  end procedure;
+
+  procedure I2CStop is
+  begin
+    sda <= '0';
+    scl <= '0';
+    wait for I2CBITTIME/2;
+    scl <= 'H';
+    wait for I2CBITTIME/2;
+    sda <= 'H';
+    wait for I2CBITTIME/2;
+
+  end procedure;
+
+  procedure I2CWaitAck is
+  begin
+    sda <= 'H';
+    scl <= '0';
+    wait for I2CBITTIME/2;
+    scl <= 'H';
+    wait for I2CBITTIME/2;
+  end procedure;
+
+  procedure I2CNAck is
+  begin
+    sda <= 'H';
+    scl <= '0';
+    wait for I2CBITTIME/2;
+    scl <= 'H';
+    wait for I2CBITTIME/2;
+  end procedure;
+
+  procedure I2CWrite (data:word(7 downto 0)) is
+  begin
+    for i in 7 downto 0 loop
+    scl <= '0';
+    wait for I2CBITTIME/4;
+    if (data(i) = '1') then sda <= 'H'; else sda <= '0'; end if;
+    wait for I2CBITTIME/4;
+    scl <= 'H';
+    wait for I2CBITTIME/2;
+    end loop;
+  end procedure;
+
+  procedure I2CRead is
+    variable read_data : word(7 downto 0);
+  begin
+    for i in 7 downto 0 loop
+    scl <= '0';
+    wait for I2CBITTIME/4;
+    read_data(i) := sda;
+    sda <= 'H';
+    wait for I2CBITTIME/4;
+    scl <= 'H';
+    wait for I2CBITTIME/2;
+    end loop;
+
+    assert false report
+    "I2C Read : " ; --& to_string(to_bitvector(read_data), "%2x");
+
+  end procedure;
+
+  begin
+  scl       <= 'H';
+  sda       <= 'H';
+
+  video_spc <= 'H';
+  video_spd <= 'H';
+  wait for 5 us;
+  -- write
+  I2CStart;
+  I2CWrite(x"EC"); -- addr
+  I2CWaitAck;
+  I2CWrite(x"81"); -- sub addr
+  I2CWaitAck;
+  I2CWrite(x"12"); -- data
+  I2CWaitAck;
+  I2CStop;
+  wait for 5 us;
+  -- read
+  I2CStart;
+  I2CWrite(x"EC"); -- addr
+  I2CWaitAck;
+  I2CWrite(x"81"); -- sub addr
+  I2CWaitAck;
+  I2CReStart; -- restart
+  I2CWrite(x"ED"); -- addr
+  I2CWaitAck;
+  I2CRead;
+  I2CNAck;
+  I2CStop;
+
+  wait;
+  end process;
+  --
+  -- dummy i2c slave
+  u_slave : entity work.Replay_I2C_CH7301
+  port map (
+    i_Rst    => por,
+    b_SPC    => video_spc,
+    b_SPD    => video_spd
+    );
+  --
+  --
+  p_spi_test : process
+  procedure SPI (data:word(7 downto 0)) is
+    variable read_data : word(7 downto 0);
+  begin
+    wait for SPIBITTIME/4;
+
+    for i in 7 downto 0 loop
+    fpga_spi_clk <= '1';
+    wait for SPIBITTIME/4;
+    if (data(i) = '1') then fpga_spi_mosi <= '1'; else fpga_spi_mosi <= '0'; end if;
+    wait for SPIBITTIME/4;
+    fpga_spi_clk <= '0';
+    wait for SPIBITTIME/2;
+    fpga_spi_clk <= '1';
+    read_data(i) := fpga_spi_miso;
+    end loop;
+    fpga_spi_clk <= '1';
+    wait for SPIBITTIME;
+
+    assert false report
+    "SPI Read : "; -- & to_string(to_bitvector(read_data), "%2x");
+    --wait for 1 us;
+  end procedure;
+
+  procedure Ena(sel:integer) is
+  begin
+    case sel is
+    --when 0 => fpga_ctrl <= "00";
+
+    when 1 => fpga_ctrl <= "10";
+    when 2 => fpga_ctrl <= "01";
+
+    when others => null;
+    end case;
+  end procedure;
+
+  procedure Dis is
+  begin
+    fpga_ctrl <= "11";
+  end procedure;
+
+  begin
+  -- SAM7S CPOL = 1, NCPHA = 0
+  -- clock normally high, data change on leading edge of clock, captured on following
+  fpga_spi_clk  <= '1';
+  fpga_spi_mosi <= '0';
+
+  Dis;
+
+  wait for 1 us;
+  Ena(2);
+  SPI(x"23"); -- set phase
+  SPI(x"68");
+  SPI(x"02");
+  Dis;
+  wait for 5 us;
+
+  -- RESET ----------------------------------------------------------
+
+  Ena(2);
+  SPI(x"11"); -- soft reset
+  Dis;
+  wait for 5 us;
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"10");
+  SPI(x"00");
+  SPI(x"01");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"80"); -- set up for read
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"80"); -- command
+  SPI(x"10"); -- command
+  SPI(x"00"); -- command
+  SPI(x"01"); -- command
+  SPI(x"00"); -- command
+  Dis;
+
+  wait for 1 us;
+  Ena(1);
+  SPI(x"84"); -- command
+  SPI(x"0F"); -- do read (word len -1)
+  SPI(x"00"); -- do read (word len -1)
+  Dis;
+  wait for 5 us;
+
+  Ena(1);
+  SPI(x"A0"); -- command
+  for i in 0 to 15 loop
+    SPI(x"00"); -- command
+  end loop;
+  Dis;
+
+  -- RESET ----------------------------------------------------------
+
+  wait for 10 us;
+  Ena(2);
+  SPI(x"11"); -- command: soft reset active
+  Dis;
+  wait for 20 us;
+  Ena(2);
+  SPI(x"10"); -- command: soft reset off
+  Dis;
+
+  -- we check how loading a PRG file works out...
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"00");
+  SPI(x"00");
+  SPI(x"08");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"00"); -- ADDR L
+  SPI(x"A0"); -- ADDR H
+  SPI(x"09"); -- data 00
+  SPI(x"A0"); -- data 01
+  SPI(x"77"); -- data 02
+  SPI(x"A0"); -- data 03
+  SPI(x"41"); -- data 04
+  SPI(x"30"); -- data 05
+  SPI(x"C3"); -- data 06
+  SPI(x"C2"); -- data 07
+  SPI(x"CD"); -- data 08
+  SPI(x"A0"); -- data LDY #$80
+  SPI(x"80"); -- data
+  SPI(x"99"); -- data STA $4000,Y
+  SPI(x"00"); -- data
+  SPI(x"40"); -- data
+  SPI(x"C8"); -- data INY
+  SPI(x"D0"); -- data BNE to STA
+  SPI(x"FA"); -- data
+  SPI(x"A0"); -- data LDY #$80
+  SPI(x"80"); -- data
+  SPI(x"B9"); -- data LDA $4000,Y
+  SPI(x"00"); -- data
+  SPI(x"40"); -- data
+  SPI(x"C8"); -- data INY
+  SPI(x"D0"); -- data BNE to LDA
+  SPI(x"FA"); -- data
+  SPI(x"4C"); -- data
+  SPI(x"2F"); -- data
+  SPI(x"FD"); -- data
+  Dis;
+  wait for 30 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"80"); -- set up for read
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"80"); -- addr
+  SPI(x"00"); --
+  SPI(x"A0"); --
+  SPI(x"00"); --
+  SPI(x"00"); --
+  Dis;
+
+  wait for 1 us;
+  Ena(1);
+  SPI(x"84"); -- command
+  SPI(x"0F"); -- do read (word len -1)
+  SPI(x"00"); -- do read (word len -1)
+  Dis;
+  wait for 5 us;
+
+  Ena(1);
+  SPI(x"A0"); -- command
+  for i in 0 to 15 loop
+    SPI(x"00"); -- command
+  end loop;
+  Dis;
+
+  -- RESET ----------------------------------------------------------
+
+  wait for 10 us;
+  Ena(2);
+  SPI(x"11"); -- command: soft reset active
+  Dis;
+  wait for 20 us;
+  Ena(2);
+  SPI(x"10"); -- command: soft reset off
+  Dis;
+
+  -- we check how loading a BIN file works out... (1541)
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"00");
+  SPI(x"80");
+  SPI(x"04");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"00"); -- data
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  -- we check how loading a BIN file works out... (VIC-20)
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"00");
+  SPI(x"80");
+  SPI(x"00");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"00"); -- data
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 30 us;
+
+  -- RESET ----------------------------------------------------------
+
+  wait for 10 us;
+  Ena(2);
+  SPI(x"11"); -- command: soft reset active
+  Dis;
+  wait for 20 us;
+  Ena(2);
+  SPI(x"10"); -- command: soft reset off
+  Dis;
+
+  -- we check how loading a d64 file works out...
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"00");
+  SPI(x"00");
+  SPI(x"00");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"A0");
+  SPI(x"65");
+  SPI(x"01");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"f0");
+  SPI(x"AA");
+  SPI(x"02");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  -- do again, check how reload works
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"00");
+  SPI(x"00");
+  SPI(x"00");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"A0");
+  SPI(x"65");
+  SPI(x"01");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"01"); -- data
+  SPI(x"02"); -- data
+  SPI(x"03"); -- data
+  SPI(x"04"); -- data
+  SPI(x"05"); -- data
+  SPI(x"06"); -- data
+  SPI(x"07"); -- data
+  SPI(x"08"); -- data
+  SPI(x"09"); -- data
+  SPI(x"0A"); -- data
+  SPI(x"0B"); -- data
+  SPI(x"0C"); -- data
+  SPI(x"0D"); -- data
+  SPI(x"0E"); -- data
+  SPI(x"0F"); -- data
+  SPI(x"10"); -- data
+  Dis;
+  wait for 10 us;
+
+  Ena(1);
+  SPI(x"80"); -- command set addr
+  SPI(x"00");
+  SPI(x"26");
+  SPI(x"01");
+  SPI(x"00");
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"81"); -- command
+  SPI(x"00"); -- do write
+  Dis;
+  wait for 1 us;
+
+  Ena(1);
+  SPI(x"B0"); -- command
+  SPI(x"A1"); -- data
+  SPI(x"A2"); -- data
+  SPI(x"A3"); -- data
+  SPI(x"A4"); -- data
+  SPI(x"A5"); -- data
+  SPI(x"A6"); -- data
+  SPI(x"A7"); -- data
+  SPI(x"A8"); -- data
+  SPI(x"A9"); -- data
+  SPI(x"AA"); -- data
+  SPI(x"AB"); -- data
+  SPI(x"AC"); -- data
+  SPI(x"AD"); -- data
+  SPI(x"AE"); -- data
+  SPI(x"AF"); -- data
+  SPI(x"B0"); -- data
+  Dis;
+  wait for 10 us;
+
+  wait;
+  end process;
+
+  p_ps2 : process
+
+  procedure PS2Write (dst : integer; data:word(7 downto 0)) is
+    variable parity : bit1;
+  begin
+    -- wait for high clock
+    while (ps2_clk(dst) = '0') loop
+    wait for PS2BITTIME;
+    end loop;
+    ps2_send_active(dst) <= '1';
+    -- start
+    ps2_data_drive_tx(dst) <= '0';
+    wait for PS2BITTIME/4;
+    ps2_clk_drive_tx(dst) <= '0';
+    wait for PS2BITTIME/2;
+    ps2_clk_drive_tx(dst) <= '1';
+
+    parity := '0';
+    for i in 0 to 7 loop
+    wait for PS2BITTIME/4;
+    if (data(i) = '1') then ps2_data_drive_tx(dst) <= '1'; else ps2_data_drive_tx(dst) <= '0'; end if;
+    parity := parity xor data(i);
+    wait for PS2BITTIME/4;
+    ps2_clk_drive_tx(dst) <= '0';
+    wait for PS2BITTIME/2;
+    ps2_clk_drive_tx(dst) <= '1';
+
+    if (i=3) then
+      wait;
+    end if;
+    end loop;
+    -- parity
+    --parity := not parity;
+    wait for PS2BITTIME/4;
+    if (parity = '0') then ps2_data_drive_tx(dst) <= '1'; else ps2_data_drive_tx(dst) <= '0'; end if;
+    wait for PS2BITTIME/4;
+    ps2_clk_drive_tx(dst) <= '0';
+    wait for PS2BITTIME/2;
+    ps2_clk_drive_tx(dst) <= '1';
+    -- stop
+    wait for PS2BITTIME/4;
+    ps2_clk_drive_tx(dst) <= '1';
+    wait for PS2BITTIME/4;
+    ps2_clk_drive_tx(dst) <= '0';
+    wait for PS2BITTIME/2;
+    ps2_clk_drive_tx(dst) <= '1';
+    ps2_send_active(dst)  <= '0';
+
+  end procedure;
+
+  begin
+  ps2_clk_drive_tx(0)  <= '1';
+  ps2_data_drive_tx(0) <= '1';
+  ps2_clk_drive_tx(1)  <= '1';
+  ps2_data_drive_tx(1) <= '1';
+
+  wait for 300 us;
+
+  wait until ps2_slave_rx = '1';
+
+  wait for 100 us;
+  PS2Write(0, x"FA");
+  wait for 100 us;
+  PS2Write(0, x"AA");
+  wait for 100 us;
+  PS2Write(0, x"00");
+  wait for 100 us;
+  --PS2Write(0, x"27");
+
+  wait for 1 ms;
+  PS2Write(0, x"23");
+  wait for 300 us;
+  PS2Write(0, x"F0");
+  wait for 100 us;
+  PS2Write(0, x"23");
+  wait for 100 us;
+  wait;
+  end process;
+
+  ps2_clk_drive_rx(1)  <= '1';
+  ps2_data_drive_rx(1) <= '1';
+
+  p_ps2_slave : process
+  begin
+  wait until falling_edge(ps2_data(0)) and (ps2_send_active(0) = '0');
+
+  ps2_slave_rx <= '0';
+----
+----  wait;
+----
+  ps2_clk_drive_rx(0)  <= '1';
+  ps2_data_drive_rx(0) <= '1';
+
+  if (ps2_clk(0) = '0') then
+    wait for 1 us;
+    -- wait for clock to go high
+    while (ps2_clk(0) = '0') loop
+    wait for PS2BITTIME/2;
+    end loop;
+    wait for PS2BITTIME/2;
+
+    ps2_clk_drive_rx(0)  <= '0';
+    wait for PS2BITTIME/2;
+
+    for i in 0 to 8 loop
+    ps2_clk_drive_rx(0)  <= '1';
+    wait for PS2BITTIME/2;
+    if (ps2_data(0) = '0') then
+      ps2_slave_data <= '0' & ps2_slave_data(7 downto 0);
+    else
+      ps2_slave_data <= '1' & ps2_slave_data(7 downto 0);
+    end if;
+
+    ps2_clk_drive_rx(0)  <= '0';
+    wait for PS2BITTIME/2;
+    end loop;
+    ps2_clk_drive_rx(0)  <= '1';
+    ps2_data_drive_rx(0) <= '0';
+    wait for PS2BITTIME/2;
+    ps2_clk_drive_rx(0)  <= '0';
+
+    wait for PS2BITTIME/2;
+    ps2_data_drive_rx(0) <= '1';
+    ps2_clk_drive_rx(0)  <= '1';
+    ps2_slave_rx <= '1';
+  end if;
+  end process;
+
+
+  ps2_clk(0)   <= '0' when (ps2_clk_drive_rx(0) = '0')  or (ps2_clk_drive_tx(0)  = '0') else 'H';
+  ps2_data(0)  <= '0' when (ps2_data_drive_rx(0) = '0') or (ps2_data_drive_tx(0) = '0') else 'H';
+  ps2_clk(1)   <= '0' when (ps2_clk_drive_rx(1) = '0')  or (ps2_clk_drive_tx(1)  = '0') else 'H';
+  ps2_data(1)  <= '0' when (ps2_data_drive_rx(1) = '0') or (ps2_data_drive_tx(1) = '0') else 'H';
+
+  u_ram : ddr
+  port map (
+    DQ     => mem_dq,
+    DQS    => mem_dqs,
+--    DQS(1) => mem_udqs,
+--    DQS(0) => mem_ldqs,
+    ADDR   => mem_addr(12 downto  0),
+    BA     => mem_addr(14 downto 13),
+    CLK    => mem_clk_p,
+    CLK_N  => mem_clk_n,
+    CKE    => mem_cke,
+    CS_N   => mem_cs,
+    RAS_N  => mem_ras,
+    CAS_N  => mem_cas,
+    WE_N   => mem_we,
+    DM     => mem_dm
+--    DM(1)  => mem_udm,
+--    DM(0)  => mem_ldm
+  );
+
+end;
Index: unmerged/core/de1/scandouble_ram_infer.vhdl
===================================================================
--- unmerged/core/de1/scandouble_ram_infer.vhdl	(nonexistent)
+++ unmerged/core/de1/scandouble_ram_infer.vhdl	(revision 1)
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+END scandouble_ram_infer;
+
+ARCHITECTURE rtl OF scandouble_ram_infer IS
+   TYPE mem IS ARRAY(0 TO 1824) OF std_logic_vector(7 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(address) <= data;
+         END IF;
+         q <= ram_block(address);
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: unmerged/core/de1/simple_counter.vhdl
===================================================================
--- unmerged/core/de1/simple_counter.vhdl	(nonexistent)
+++ unmerged/core/de1/simple_counter.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY simple_counter IS
+generic
+(
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+);
+END simple_counter;
+
+ARCHITECTURE vhdl OF simple_counter IS
+	signal value_next : std_logic_vector(COUNT_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(COUNT_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: unmerged/core/de1/syncreset_enable_divider.vhd
===================================================================
--- unmerged/core/de1/syncreset_enable_divider.vhd	(nonexistent)
+++ unmerged/core/de1/syncreset_enable_divider.vhd	(revision 1)
@@ -0,0 +1,81 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY syncreset_enable_divider IS
+generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNCRESET : in std_logic;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END syncreset_enable_divider;
+
+ARCHITECTURE vhdl OF syncreset_enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg,syncreset)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+		
+		if (syncreset='1') then
+			count_next <= std_logic_vector(to_unsigned(resetcount,width));
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: unmerged/core/de1/zpu/bootdump.c
===================================================================
--- unmerged/core/de1/zpu/bootdump.c	(nonexistent)
+++ unmerged/core/de1/zpu/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/core/de1/zpu/Makefile
===================================================================
--- unmerged/core/de1/zpu/Makefile	(nonexistent)
+++ unmerged/core/de1/zpu/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c mmc.c    spi.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/core/de1/zpu/diskio.h
===================================================================
--- unmerged/core/de1/zpu/diskio.h	(nonexistent)
+++ unmerged/core/de1/zpu/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/core/de1/zpu/integer.h
===================================================================
--- unmerged/core/de1/zpu/integer.h	(nonexistent)
+++ unmerged/core/de1/zpu/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/core/de1/zpu/mmc.c
===================================================================
--- unmerged/core/de1/zpu/mmc.c	(nonexistent)
+++ unmerged/core/de1/zpu/mmc.c	(revision 1)
@@ -0,0 +1,269 @@
+/*! \file mmc.c \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.c'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+//----- Include Files ---------------------------------------------------------
+#include "spi.h"		// include spi bus support
+
+
+//#define spiTransferTwoFF()	{ spiTransferFF(); spiTransferFF(); }
+
+
+#include "mmc.h"
+
+// include project-specific hardware configuration
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+	// initialize SPI interface
+	spiInit();
+	// release chip select
+	mmcChipSelect(0);
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(1);
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+	u08 retry=0xff;	//255x
+	//
+
+	spiTransferFF();
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+	//
+	spiTransferByte(arg>>24);
+	spiTransferByte(arg>>16);
+	spiTransferByte(arg>>8);
+	spiTransferByte(arg);
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+		retry--;
+	}
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
Index: unmerged/changes_mcc_to_mist
===================================================================
--- unmerged/changes_mcc_to_mist	(nonexistent)
+++ unmerged/changes_mcc_to_mist	(revision 1)
@@ -0,0 +1,10594 @@
+diff -ur atari800core_v1_20140121_mcc216/address_decoder.vhdl atari800core_v1_20140312_mist/address_decoder.vhdl
+--- atari800core_v1_20140121_mcc216/address_decoder.vhdl	2014-01-30 21:32:16.000000000 +0000
++++ atari800core_v1_20140312_mist/address_decoder.vhdl	2014-03-09 20:12:21.000000000 +0000
+@@ -59,9 +59,11 @@
+ 	
+ 	reset_n : in std_logic;
+ 	
+-	rom_select : in std_logic_vector(1 downto 0);
++	rom_select : in std_logic_vector(5 downto 0);
++	cart_select : in std_logic_vector(6 downto 0);
++	cart_activate : in std_logic;
+ 	
+-	ram_select : in std_logic_vector(1 downto 0);
++	ram_select : in std_logic_vector(2 downto 0);
+ 	
+ 	CART_RD4 : in std_logic;
+ 	CART_RD5 : in std_logic;
+@@ -88,7 +90,8 @@
+ 	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+ 	RAM_WR_ENABLE : OUT STD_LOGIC;	
+ 	PBI_WR_ENABLE : OUT STD_LOGIC;
+-	
++	D6_WR_ENABLE : OUT STD_LOGIC;
++ 	
+ 	-- ROM and RAM have extended address busses to allow for bank switching etc.
+ 	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+ 	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+@@ -147,12 +150,16 @@
+ 	signal notify_cpu : std_logic;
+ 	signal start_request : std_logic;
+ 	
++	signal extended_access_addr : std_logic;
+ 	signal extended_access_cpu_or_antic : std_logic;
+ 	signal extended_access_antic : std_logic;
+ 	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+ 	
+ 	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+ 
++	signal extended_self_test : std_logic;
++	signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
++	
+ 	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+ 	signal state_next : std_logic_vector(1 downto 0);
+ 	signal state_reg : std_logic_vector(1 downto 0);
+@@ -173,6 +180,19 @@
+ 	signal fetch_wait_next : std_logic_vector(8 downto 0);
+ 	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
+ 	
++	signal rom_in_ram : std_logic;
++	
++	signal antic_fetch_real_next : std_logic;
++	signal antic_fetch_real_reg : std_logic;
++	signal cpu_fetch_real_next : std_logic;
++	signal cpu_fetch_real_reg : std_logic;
++
++	signal SDRAM_CART_ADDR   : std_logic_vector(22 downto 0);
++	signal SDRAM_BASIC_ROM_ADDR  : std_logic_vector(22 downto 0);
++	signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
++	
++	signal sdram_only_bank : std_logic;
++	
+ BEGIN
+ 		-- register
+ 	process(clk,reset_n)
+@@ -187,7 +207,10 @@
+ 			data_write_reg <= (others=> '0');
+ 			--sdram_request_reg <= '0';
+ 			fetch_wait_reg <= (others=>'0');
+-		elsif (clk'event and clk='1') then
++
++			cpu_fetch_real_reg <= '0';
++			antic_fetch_real_reg <= '0';	
++	elsif (clk'event and clk='1') then
+ 			addr_reg <= addr_next;
+ 			state_reg <= state_next;
+ 			width_8bit_reg <= width_8bit_next;
+@@ -197,6 +220,9 @@
+ 			data_write_reg <= data_WRITE_next;
+ 			--sdram_request_reg <= sdram_request_next;
+ 			fetch_wait_reg <= fetch_wait_next;
++			
++			cpu_fetch_real_reg <= cpu_fetch_real_next;
++			antic_fetch_real_reg <= antic_fetch_real_next;
+ 		end if;
+ 	end process;
+ 	
+@@ -219,7 +245,7 @@
+ 	
+ 	-- state machine impl
+ 	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+-	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
++	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
+ 	begin
+ 		start_request <= '0';
+ 		notify_antic <= '0';
+@@ -235,6 +261,9 @@
+ 		width_32bit_next <= width_32bit_reg;		
+ 		write_enable_next <= write_enable_reg;
+ 		
++		antic_fetch_real_next <= antic_fetch_real_reg;
++		cpu_fetch_real_next <= cpu_fetch_real_reg;
++		
+ 		case state_reg is
+ 			when state_idle =>
+ 				fetch_wait_next <= (others=>'0');
+@@ -255,6 +284,7 @@
+ 					else
+ 						state_next <= state_waiting_antic;
+ 					end if;
++					antic_fetch_real_next <= '1';
+ 				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+ 					start_request <= '1';
+ 					addr_next <= zpu_ADDR;
+@@ -282,6 +312,7 @@
+ 					else
+ 						state_next <= state_waiting_cpu;
+ 					end if;
++					cpu_fetch_real_next <= '1';
+ 				when "000" =>
+ 					-- no requests
+ 				end case;
+@@ -312,7 +343,7 @@
+ 		
+ 	SDRAM_REQUEST <= sdram_chip_select;
+ 	--SDRAM_REQUEST <= sdram_request_next;
+-	SDRAM_REFRESH <= fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
++	SDRAM_REFRESH <= '0'; --fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+ 	SDRAM_READ_EN <= not(write_enable_next);
+ 	SDRAM_WRITE_EN <= write_enable_next;
+ 	
+@@ -327,11 +358,78 @@
+ 	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+ 	
+ 	-- Calculate which memory area to use
++	extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
+ 	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+-	extended_access_antic <= (antic_fetch and not(portb(5)));
+-	extended_access_cpu <= not(antic_fetch) and not(portb(4));
++	extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
++	extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
++	extended_access_either <= extended_access_addr and not(portb(4));
++	sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
++	
++	process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
++	begin	
++		extended_bank <= "0000000"&addr_next(15 downto 14);
++		extended_self_test <= '1';
++		
++		case ram_select is
++			when "000" => -- 64k
++				-- default
++			when "001" => -- 128k			
++				if (extended_access_cpu_or_antic='1') then
++					extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
++				end if;
++			when "010" => -- 320k compy shop
++				if (extended_access_cpu_or_antic='1') then
++					extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
++					extended_self_test <= '0';
++				end if;
++			when "011" => -- 320k rambo
++				if (extended_access_either='1')then
++					extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
++				end if;
++			when "100" => -- 576k compy shop
++				if (extended_access_cpu_or_antic='1') then
++					extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
++					extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
++					extended_self_test <= '0';
++				end if;
++			when "101" => -- 576k rambo
++				if (extended_access_either='1') then
++					extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
++					extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
++				end if;
++			when "110" => -- 1088k rambo
++				if (extended_access_either='1') then
++					extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
++					extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
++					extended_self_test <= '0';
++				end if;
++			when "111" => -- 4MB!	
++				if (extended_access_addr='1') then
++					extended_bank(7 downto 0) <= portb(7 downto 0);				
++					extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
++					extended_self_test <= and_reduce(portb(6 downto 4));	 -- which means self-test is in the middle of half the banks - euuugh, oh well!						
++				end if;
++			when others =>
++				-- TODO - portc!
++		end case;
++	end process;
++
+ 	
+-	extended_access_either <= not(portb(4));
++	-- SRAM memory map (512k)
++	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
++	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP)
++	-- SDRAM memory map (8MB)
++	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
++	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP) 
++	-- to 4MB RAM    - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
++	-- +64k          - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
++	-- SCRATCH       - 4MB+64k-5MB
++	-- CARTS         -              "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
++	SDRAM_CART_ADDR      <= "101"&cart_select& "0000000000000";
++	-- BASIC/OS ROM  -              "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K				
++	SDRAM_BASIC_ROM_ADDR <= "111"&"000000"   &"00000000000000";
++	SDRAM_OS_ROM_ADDR    <= "111"&rom_select &"00000000000000";
++	-- SYSTEM        -              "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
+ 	
+   	process(
+ 		-- address and writing absolutely points us at a device
+@@ -341,7 +439,7 @@
+ 		portb, 
+ 		antic_fetch,
+ 		rom_select,
+-		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
++		ram_select,cart_rd4,cart_rd5,
+ 		use_sdram,
+ 		
+ 		-- input data from n sources
+@@ -353,7 +451,14 @@
+ 		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+ 		
+ 		-- on new access this is set - we must select the appropriate device - for this cycle only
+-		start_request
++		start_request,
++		
++		rom_in_ram,
++		
++		-- SDRAM base addresses
++		extended_self_test,extended_bank,sdram_only_bank,
++		SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
++		
+ 	)
+ 	begin
+ 		MEMORY_DATA <= (others => '1');
+@@ -373,6 +478,7 @@
+ 		PIA_WR_ENABLE <= '0';
+ 		PIA_RD_ENABLE <= '0';
+ 		PBI_WR_ENABLE <= '0';
++		D6_WR_ENABLE <= '0';
+ 
+ 		RAM_WR_ENABLE <= write_enable_next;
+ 		SDRAM_WRITE_EN <= write_enable_next;		
+@@ -386,13 +492,27 @@
+ 		
+ 		ram_chip_select <= '0';
+ 		sdram_chip_select <= '0';
++		
++		rom_in_ram <= '1';
+ 
+ 	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+ 		if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+ 
+-		RAM_ADDR(18 downto 16) <= "000";	
+-		SDRAM_ADDR(22 downto 16) <= "0000000";
+-	
++		SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
++		SDRAM_ADDR(22 downto 14) <= extended_bank;
++		RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
++		RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
++					
++		if ((use_sdram or sdram_only_bank)='1') then
++			MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++			sdram_chip_select <= start_request;
++			request_complete <= sdram_request_COMPLETE;														
++		else
++			MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
++			ram_chip_select <= start_request;
++			request_complete <= ram_request_COMPLETE;									
++		end if;
++		
+ 		case addr_next(15 downto 8) is 
+ 				-- GTIA
+ 				when X"D0" =>
+@@ -400,6 +520,8 @@
+ 					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+ 					MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';
+ 			
+ 				-- POKEY
+ 				when X"D2" =>				
+@@ -413,6 +535,8 @@
+ 						MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
+ 					end if;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';					
+ 
+ 				-- PIA
+ 				when X"D3" =>
+@@ -420,6 +544,8 @@
+ 					PIA_RD_ENABLE <= '1';
+ 					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';					
+ 					
+ 				-- ANTIC
+ 				when X"D4" =>
+@@ -427,9 +553,13 @@
+ 					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+ 					MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';					
+ 					
+ 				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+ 				when X"D5" =>
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';				
+ 					if ((CART_RD4 or CART_RD5) = '1') then
+ 						PBI_WR_ENABLE <= write_enable_next;
+ 						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+@@ -441,92 +571,39 @@
+ 						request_complete <= '1';
+ 					end if;
+ 					
+-				-- XE RAM
+-				when 
+-					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+-					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+-					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+-					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+-					
+-					if (use_sdram = '1') then
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-						sdram_chip_select <= start_request;
+-						request_complete <= sdram_request_COMPLETE;														
+-					else
+-						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-						ram_chip_select <= start_request;
+-						request_complete <= ram_request_COMPLETE;									
+-					end if;
+-					
+-					case ram_select is
+-						when "00" => -- 64k
+-							-- default
+-						when "01" => -- 128k					
+-							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+-							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+-						when "10" => -- 320k compy shop
+-							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-						when "11" => -- 320k rambo
+-							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-					end case;
+-					
++				when X"D6" =>
++					D6_WR_ENABLE <= write_enable_next;
++					-- TODO - should this still have RAM with covox here?
++										
+ 				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+ 				when 
+ 					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+ 									
+-					if (portb(7) = '0' and portb(0) = '1') then
+-						--request_complete <= ROM_REQUEST_COMPLETE;
+-						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+-						--rom_request <= start_request;					
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++					if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';	
++						
++						if (rom_in_ram = '1') then
++							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						else
++							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
++						end if;
+ 						
+ 						if (write_enable_next = '1') then
+ 							request_complete <= '1';
+ 						else
+-							request_complete <= sdram_request_COMPLETE;							
+-							sdram_chip_select <= start_request;							
++							if (rom_in_ram = '1') then
++								request_complete <= sdram_request_COMPLETE;							
++								sdram_chip_select <= start_request;							
++							else
++								request_complete <= rom_request_COMPLETE;							
++								rom_request <= start_request;															
++							end if;
+ 						end if;
+ 						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+-						case rom_select is
+-							when "00" =>
+-								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+-						    SDRAM_ADDR <="0010000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+-							when "01" =>
+-								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+-							 SDRAM_ADDR <="0010000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k								
+-							when "10" =>
+-								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+-							 SDRAM_ADDR <="0010000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k							
+-							when "11" =>
+-								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+-							SDRAM_ADDR <= "0010001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)								
+-						end case;														
+-					else				
+-						if (use_sdram = '1') then
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-							sdram_chip_select <= start_request;
+-							request_complete <= sdram_request_COMPLETE;														
+-						else
+-							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-							ram_chip_select <= start_request;
+-							request_complete <= ram_request_COMPLETE;									
+-						end if;
+-						
+-						case ram_select is
+-							when "00" => -- 64k
+-								-- default
+-							when "01" => -- 128k					
+-								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+-								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+-							when "10" => -- 320k compy shop
+-								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-							when "11" => -- 320k rambo
+-								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-						end case;
++						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
++						SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
++						ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k						
+ 					end if;
+ 				
+ 				-- 0x80 cart
+@@ -539,16 +616,8 @@
+ 						rom_request <= start_request;
+ 						CART_S4_n <= '0';
+ 						request_complete <= CART_REQUEST_COMPLETE;
+-					else
+-						if (use_sdram = '1') then
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-							sdram_chip_select <= start_request;
+-							request_complete <= sdram_request_COMPLETE;														
+-						else
+-							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-							ram_chip_select <= start_request;
+-							request_complete <= ram_request_COMPLETE;									
+-						end if;
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';							
+ 					end if;	
+ 			
+ 				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+@@ -561,31 +630,35 @@
+ 						cart_request <= start_request;
+ 						CART_S5_n <= '0';
+ 						request_complete <= CART_REQUEST_COMPLETE;
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';													
+ 					else
+ 						if (portb(1) = '0') then
++							sdram_chip_select <= '0';
++							ram_chip_select <= '0';							
+ 							--request_complete <= ROM_REQUEST_COMPLETE;
+ 							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+ 							--rom_request <= start_request;					
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++							if (rom_in_ram = '1') then
++								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++							else
++								MEMORY_DATA(7 downto 0) <= ROM_DATA;						
++							end if;
+ 							if (write_enable_next = '1') then
+ 								request_complete <= '1';
+ 							else
+-								request_complete <= sdram_request_COMPLETE;							
+-								sdram_chip_select <= start_request;								
++								if (rom_in_ram = '1') then
++									request_complete <= sdram_request_COMPLETE;							
++									sdram_chip_select <= start_request;							
++								else
++									request_complete <= rom_request_COMPLETE;							
++									rom_request <= start_request;															
++								end if;
+ 							end if;
+ 						
+ 							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+-						 SDRAM_ADDR <="0010000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k							
+-						else
+-							if (use_sdram = '1') then
+-								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-								sdram_chip_select <= start_request;
+-								request_complete <= sdram_request_COMPLETE;														
+-							else
+-								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-								ram_chip_select <= start_request;
+-								request_complete <= ram_request_COMPLETE;									
+-							end if;
++						 SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
++						 SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k							
+ 						end if;
+ 					end if;
+ 					
+@@ -598,56 +671,38 @@
+ 					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+ 					
+ 					if (portb(0) = '1') then
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';																		
+ 						--request_complete <= ROM_REQUEST_COMPLETE;
+ 						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+ 						--rom_request <= start_request;					
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						if (rom_in_ram = '1') then
++							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						else
++							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
++						end if;
+ 						if (write_enable_next = '1') then
+ 							request_complete <= '1';
+ 						else
+-							request_complete <= sdram_request_COMPLETE;							
+-							sdram_chip_select <= start_request;							
++								if (rom_in_ram = '1') then
++									request_complete <= sdram_request_COMPLETE;							
++									sdram_chip_select <= start_request;							
++								else
++									request_complete <= rom_request_COMPLETE;							
++									rom_request <= start_request;															
++								end if;						
+ 						end if;																			
+ 
+-						case rom_select is
+-							when "00" =>
+-								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+-							SDRAM_ADDR <= "0010000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+-							when "01" =>
+-								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+-							SDRAM_ADDR <= "0010000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+-							when "10" =>
+-								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+-							SDRAM_ADDR <= "0010000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+-							when "11" =>
+-								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+-							SDRAM_ADDR <= "0010001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+-						end case;
+-								
+-					else
+-						if (use_sdram = '1') then
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-							sdram_chip_select <= start_request;
+-							request_complete <= sdram_request_COMPLETE;														
+-						else
+-							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-							ram_chip_select <= start_request;
+-							request_complete <= ram_request_COMPLETE;									
+-						end if;
++						ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
++						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
++						SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
+ 					end if;
+ 					
+ 				when others =>
+-					if (use_sdram = '1') then
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-						sdram_chip_select <= start_request;
+-						request_complete <= sdram_request_COMPLETE;														
+-					else
+-						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-						ram_chip_select <= start_request;
+-						request_complete <= ram_request_COMPLETE;									
+-					end if;
+ 			end case;				
+ 		else		
++			sdram_chip_select <= '0';
++			ram_chip_select <= '0';													
+ 			case addr_next(23 downto 21) is			
+ 				when "000" =>				
+ 					-- internal area for zpu, never happens!
+Only in atari800core_v1_20140312_mist/: atari800core_assignment_defaults.qdf
+diff -ur atari800core_v1_20140121_mcc216/atari800core.jdi atari800core_v1_20140312_mist/atari800core.jdi
+--- atari800core_v1_20140121_mcc216/atari800core.jdi	2014-02-03 19:43:36.000000000 +0000
++++ atari800core_v1_20140312_mist/atari800core.jdi	2014-03-12 05:05:06.000000000 +0000
+@@ -1,6 +1,62 @@
+ <sld_project_info>
+   <project>
+-    <hash md5_digest_80b="00000000000000000000"/>
++    <hash md5_digest_80b="7d0f11bf891bc55d775e"/>
+   </project>
+   <file_info/>
++  <hub_info ir_width="8" node_count="1"/>
++  <node_info>
++    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
++      <parameters>
++        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
++        <parameter name="sld_node_info" type="unknown" value="805334528"/>
++        <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
++        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
++        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
++        <parameter name="sld_data_bits" type="unknown" value="119"/>
++        <parameter name="sld_trigger_bits" type="unknown" value="119"/>
++        <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
++        <parameter name="sld_node_crc_hiword" type="unknown" value="37736"/>
++        <parameter name="sld_node_crc_loword" type="unknown" value="25945"/>
++        <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
++        <parameter name="sld_sample_depth" type="unknown" value="2048"/>
++        <parameter name="sld_segment_size" type="unknown" value="2048"/>
++        <parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
++        <parameter name="sld_state_bits" type="unknown" value="11"/>
++        <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
++        <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
++        <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
++        <parameter name="sld_trigger_level" type="unknown" value="1"/>
++        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
++        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
++        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
++        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
++        <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
++        <parameter name="sld_inversion_mask_length" type="unknown" value="382"/>
++        <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
++        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
++        <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
++        <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
++        <parameter name="sld_current_resource_width" type="unknown" value="1"/>
++        <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
++        <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
++        <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
++        <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
++        <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
++        <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
++        <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
++        <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
++      </parameters>
++      <inputs/>
++      <outputs/>
++    </node>
++  </node_info>
+ </sld_project_info>
+diff -ur atari800core_v1_20140121_mcc216/atari800core.qsf atari800core_v1_20140312_mist/atari800core.qsf
+--- atari800core_v1_20140121_mcc216/atari800core.qsf	2014-02-03 19:39:52.000000000 +0000
++++ atari800core_v1_20140312_mist/atari800core.qsf	2014-03-12 05:08:27.000000000 +0000
+@@ -1,6 +1,4 @@
+-# -------------------------------------------------------------------------- #
+-#
+-# Copyright (C) 1991-2012 Altera Corporation
++# Copyright (C) 1991-2007 Altera Corporation
+ # Your use of Altera Corporation's design tools, logic functions 
+ # and other software and tools, and its AMPP partner logic 
+ # functions, and any output files from any of the foregoing 
+@@ -13,287 +11,308 @@
+ # programming logic devices manufactured by Altera and sold by 
+ # Altera or its authorized distributors.  Please refer to the 
+ # applicable agreement for further details.
+-#
+-# -------------------------------------------------------------------------- #
+-#
+-# Quartus II 64-Bit
+-# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+-# Date created = 13:58:39  April 11, 2013
+-#
+-# -------------------------------------------------------------------------- #
+-#
+-# Notes:
+-#
+-# 1) The default values for assignments are stored in the file:
+-#		atari800core_assignment_defaults.qdf
+-#    If this file doesn't exist, see file:
++
++
++# The default values for assignments are stored in the file
++#		minimig_de1_assignment_defaults.qdf
++# If this file doesn't exist, and for assignments not listed, see file
+ #		assignment_defaults.qdf
+-#
+-# 2) Altera recommends that you do not modify this file. This
+-#    file is updated automatically by the Quartus II software
+-#    and any changes you make may be lost or overwritten.
+-#
+-# -------------------------------------------------------------------------- #
++
++# Altera recommends that you do not modify this file. This
++# file is updated automatically by the Quartus II software
++# and any changes you make may be lost or overwritten.
+ 
+ 
+ set_global_assignment -name FAMILY "Cyclone III"
+-set_global_assignment -name DEVICE EP3C16E144C8
++set_global_assignment -name DEVICE EP3C25E144C8
+ set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+-set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+-set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
++set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
++set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
+ set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+-set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+-set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+-set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+-set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
++set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
++set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
++set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
++set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
++set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
++set_global_assignment -name FITTER_EFFORT "AUTO FIT"
++set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
++set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
++set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
++set_global_assignment -name GENERATE_RBF_FILE ON
++set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
++
++set_location_assignment PIN_7 -to LED
++set_location_assignment PIN_22 -to CLOCK_50[0]
++set_location_assignment PIN_23 -to CLOCK_50[1]
++set_location_assignment PIN_128 -to CLOCK_32[0]
++set_location_assignment PIN_129 -to CLOCK_32[1]
++set_location_assignment PIN_54 -to CLOCK_27[0]
++set_location_assignment PIN_55 -to CLOCK_27[1]
++set_location_assignment PIN_144 -to VGA_R[5]
++set_location_assignment PIN_143 -to VGA_R[4]
++set_location_assignment PIN_142 -to VGA_R[3]
++set_location_assignment PIN_141 -to VGA_R[2]
++set_location_assignment PIN_137 -to VGA_R[1]
+ set_location_assignment PIN_135 -to VGA_R[0]
+-set_location_assignment PIN_134 -to VGA_R[1]
+-set_location_assignment PIN_133 -to VGA_R[2]
+-set_location_assignment PIN_132 -to VGA_R[3]
+-set_location_assignment PIN_141 -to VGA_G[0]
+-set_location_assignment PIN_142 -to VGA_G[1]
+-set_location_assignment PIN_143 -to VGA_G[2]
+-set_location_assignment PIN_144 -to VGA_G[3]
+-set_location_assignment PIN_4 -to VGA_B[0]
+-set_location_assignment PIN_7 -to VGA_B[1]
+-set_location_assignment PIN_10 -to VGA_B[2]
+-set_location_assignment PIN_11 -to VGA_B[3]
+-set_location_assignment PIN_136 -to VGA_HS
+-set_location_assignment PIN_137 -to VGA_VS
++set_location_assignment PIN_133 -to VGA_B[5]
++set_location_assignment PIN_132 -to VGA_B[4]
++set_location_assignment PIN_125 -to VGA_B[3]
++set_location_assignment PIN_121 -to VGA_B[2]
++set_location_assignment PIN_120 -to VGA_B[1]
++set_location_assignment PIN_115 -to VGA_B[0]
++set_location_assignment PIN_114 -to VGA_G[5]
++set_location_assignment PIN_113 -to VGA_G[4]
++set_location_assignment PIN_112 -to VGA_G[3]
++set_location_assignment PIN_111 -to VGA_G[2]
++set_location_assignment PIN_110 -to VGA_G[1]
++set_location_assignment PIN_106 -to VGA_G[0]
++set_location_assignment PIN_136 -to VGA_VS
++set_location_assignment PIN_119 -to VGA_HS
++set_location_assignment PIN_65 -to AUDIO_L
++set_location_assignment PIN_80 -to AUDIO_R
++set_location_assignment PIN_46 -to UART_TX
++set_location_assignment PIN_31 -to UART_RX
++set_location_assignment PIN_105 -to SPI_DO
++set_location_assignment PIN_88 -to SPI_DI
++set_location_assignment PIN_126 -to SPI_SCK
++set_location_assignment PIN_127 -to SPI_SS2
++set_location_assignment PIN_91 -to SPI_SS3
++set_location_assignment PIN_90 -to SPI_SS4
++set_location_assignment PIN_13 -to CONF_DATA0
++
++set_location_assignment PIN_49 -to SDRAM_A[0]
++set_location_assignment PIN_44 -to SDRAM_A[1]
++set_location_assignment PIN_42 -to SDRAM_A[2]
++set_location_assignment PIN_39 -to SDRAM_A[3]
++set_location_assignment PIN_4 -to SDRAM_A[4]
++set_location_assignment PIN_6 -to SDRAM_A[5]
++set_location_assignment PIN_8 -to SDRAM_A[6]
++set_location_assignment PIN_10 -to SDRAM_A[7]
++set_location_assignment PIN_11 -to SDRAM_A[8]
++set_location_assignment PIN_28 -to SDRAM_A[9]
++set_location_assignment PIN_50 -to SDRAM_A[10]
++set_location_assignment PIN_30 -to SDRAM_A[11]
++set_location_assignment PIN_32 -to SDRAM_A[12]
++set_location_assignment PIN_83 -to SDRAM_DQ[0]
++set_location_assignment PIN_79 -to SDRAM_DQ[1]
++set_location_assignment PIN_77 -to SDRAM_DQ[2]
++set_location_assignment PIN_76 -to SDRAM_DQ[3]
++set_location_assignment PIN_72 -to SDRAM_DQ[4]
++set_location_assignment PIN_71 -to SDRAM_DQ[5]
++set_location_assignment PIN_69 -to SDRAM_DQ[6]
++set_location_assignment PIN_68 -to SDRAM_DQ[7]
++set_location_assignment PIN_86 -to SDRAM_DQ[8]
++set_location_assignment PIN_87 -to SDRAM_DQ[9]
++set_location_assignment PIN_98 -to SDRAM_DQ[10]
++set_location_assignment PIN_99 -to SDRAM_DQ[11]
++set_location_assignment PIN_100 -to SDRAM_DQ[12]
++set_location_assignment PIN_101 -to SDRAM_DQ[13]
++set_location_assignment PIN_103 -to SDRAM_DQ[14]
++set_location_assignment PIN_104 -to SDRAM_DQ[15]
++set_location_assignment PIN_58 -to SDRAM_BA[0]
++set_location_assignment PIN_51 -to SDRAM_BA[1]
++set_location_assignment PIN_85 -to SDRAM_DQMH
++set_location_assignment PIN_67 -to SDRAM_DQML
++set_location_assignment PIN_60 -to SDRAM_nRAS
++set_location_assignment PIN_64 -to SDRAM_nCAS
++set_location_assignment PIN_66 -to SDRAM_nWE
++set_location_assignment PIN_59 -to SDRAM_nCS
++set_location_assignment PIN_33 -to SDRAM_CKE
++set_location_assignment PIN_43 -to SDRAM_CLK
++
++set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
++set_global_assignment -name SMART_RECOMPILE ON
+ set_global_assignment -name ENABLE_SIGNALTAP ON
+-set_location_assignment PIN_44 -to SD_CLK
+-set_location_assignment PIN_46 -to SD_CMD
++set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
++set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
++set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
++set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
++set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
++set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
++set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
++set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+ set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+-set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
++set_global_assignment -name TPD_REQUIREMENT "2 ns"
++set_global_assignment -name TSU_REQUIREMENT "2 ns"
++set_global_assignment -name TCO_REQUIREMENT "2 ns"
++set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+-set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+-set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+-set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+-set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+-set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
++set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
++set_global_assignment -name AUTO_RAM_RECOGNITION ON
++set_global_assignment -name AUTO_ROM_RECOGNITION ON
++set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
++set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
++set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
++set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
++set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
++set_global_assignment -name MISC_FILE atari800core.dpf
++set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
++
++set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
++set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
++set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
++
++set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
++set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
++set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
++set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
++
++#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
++#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
++
++set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+ set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+ set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+-set_global_assignment -name SMART_RECOMPILE ON
+-set_global_assignment -name ENABLE_DRC_SETTINGS ON
+-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+-set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+-set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+-set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+-set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+-set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+-set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
++set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
++set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
++set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
++set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+ 
+-set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+-set_location_assignment PIN_28 -to AUDIO_L
+-set_location_assignment PIN_30 -to AUDIO_R
+-set_location_assignment PIN_53 -to CPU_RESET_n
+-set_location_assignment PIN_55 -to FPGA_CLK
+-set_location_assignment PIN_127 -to JOY1_n[0]
+-set_location_assignment PIN_91 -to JOY1_n[1]
+-set_location_assignment PIN_90 -to JOY1_n[2]
+-set_location_assignment PIN_88 -to JOY1_n[3]
+-set_location_assignment PIN_89 -to JOY1_n[4]
+-set_location_assignment PIN_126 -to JOY1_n[5]
+-set_location_assignment PIN_128 -to JOY2_n[0]
+-set_location_assignment PIN_25 -to JOY2_n[1]
+-set_location_assignment PIN_24 -to JOY2_n[2]
+-set_location_assignment PIN_22 -to JOY2_n[3]
+-set_location_assignment PIN_23 -to JOY2_n[4]
+-set_location_assignment PIN_129 -to JOY2_n[5]
+-set_location_assignment PIN_33 -to PS2K_DAT
+-set_location_assignment PIN_39 -to PS2K_CLK
+-set_location_assignment PIN_32 -to PS2M_DAT
+-set_location_assignment PIN_31 -to PS2M_CLK
+-set_location_assignment PIN_52 -to SD_DAT0
+-set_location_assignment PIN_49 -to SD_DAT3
+-set_location_assignment PIN_42 -to USB_P
+-set_location_assignment PIN_43 -to USB_N
+-set_location_assignment PIN_50 -to USB2_P
+-set_location_assignment PIN_51 -to USB2_N
+-set_location_assignment PIN_112 -to SDRAM_CLK
+-set_location_assignment PIN_61 -to SDRAM_A[0]
+-set_location_assignment PIN_60 -to SDRAM_A[1]
+-set_location_assignment PIN_59 -to SDRAM_A[2]
+-set_location_assignment PIN_58 -to SDRAM_A[3]
+-set_location_assignment PIN_125 -to SDRAM_A[4]
+-set_location_assignment PIN_121 -to SDRAM_A[5]
+-set_location_assignment PIN_120 -to SDRAM_A[6]
+-set_location_assignment PIN_119 -to SDRAM_A[7]
+-set_location_assignment PIN_115 -to SDRAM_A[8]
+-set_location_assignment PIN_114 -to SDRAM_A[9]
+-set_location_assignment PIN_64 -to SDRAM_A[10]
+-set_location_assignment PIN_113 -to SDRAM_A[11]
+-set_location_assignment PIN_111 -to SDRAM_A[12]
+-set_location_assignment PIN_66 -to SDRAM_BA[0]
+-set_location_assignment PIN_65 -to SDRAM_BA[1]
+-set_location_assignment PIN_87 -to SDRAM_DQ[0]
+-set_location_assignment PIN_86 -to SDRAM_DQ[1]
+-set_location_assignment PIN_85 -to SDRAM_DQ[2]
+-set_location_assignment PIN_83 -to SDRAM_DQ[3]
+-set_location_assignment PIN_80 -to SDRAM_DQ[4]
+-set_location_assignment PIN_79 -to SDRAM_DQ[5]
+-set_location_assignment PIN_77 -to SDRAM_DQ[6]
+-set_location_assignment PIN_76 -to SDRAM_DQ[7]
+-set_location_assignment PIN_106 -to SDRAM_DQ[8]
+-set_location_assignment PIN_105 -to SDRAM_DQ[9]
+-set_location_assignment PIN_104 -to SDRAM_DQ[10]
+-set_location_assignment PIN_103 -to SDRAM_DQ[11]
+-set_location_assignment PIN_101 -to SDRAM_DQ[12]
+-set_location_assignment PIN_100 -to SDRAM_DQ[13]
+-set_location_assignment PIN_99 -to SDRAM_DQ[14]
+-set_location_assignment PIN_98 -to SDRAM_DQ[15]
+-set_location_assignment PIN_67 -to SDRAM_CS_n
+-set_location_assignment PIN_68 -to SDRAM_RAS_n
+-set_location_assignment PIN_69 -to SDRAM_CAS_n
+-set_location_assignment PIN_71 -to SDRAM_WE_n
+-set_location_assignment PIN_6 -to CFG_DOUT
+-set_location_assignment PIN_8 -to CFG_CS_n
+-set_location_assignment PIN_12 -to CFG_CLK
+-set_location_assignment PIN_13 -to CFG_DIN
+-set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+-set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+-set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+-set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+-set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+-set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
+-set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n
+-set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN
+-set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+-set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
+-set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
+-set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
+-set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
+-set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
+ 
+ 
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
++set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
++
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
++set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
++
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
++set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
++
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
++
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
++
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
++
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
++set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
++
++
++set_global_assignment -name VHDL_FILE data_io.vhdl
++set_global_assignment -name QIP_FILE basic.qip
++set_global_assignment -name VERILOG_FILE user_io.v
+ set_global_assignment -name VERILOG_FILE hq_dac.v
+ set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+-set_global_assignment -name VHDL_FILE romlo.vhd
+-set_global_assignment -name VHDL_FILE romhi.vhd
+ set_global_assignment -name VHDL_FILE ramint.vhd
+ set_global_assignment -name VHDL_FILE atari800core.vhd
+ set_global_assignment -name VHDL_FILE spi_master.vhd
+@@ -307,7 +326,6 @@
+ set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+ set_global_assignment -name VHDL_FILE cpu.vhd
+ set_global_assignment -name QIP_FILE pll.qip
+-set_global_assignment -name SDC_FILE atari800core.sdc
+ set_global_assignment -name VHDL_FILE reg_file.vhdl
+ set_global_assignment -name VHDL_FILE address_decoder.vhdl
+ set_global_assignment -name VHDL_FILE pokey.vhdl
+@@ -345,4 +363,272 @@
+ set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+ set_global_assignment -name VHDL_FILE internalromram.vhd
+ set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
++set_global_assignment -name SIGNALTAP_FILE stp1.stp
++set_global_assignment -name SDC_FILE atari800core.sdc
++set_global_assignment -name QIP_FILE rom16.qip
++set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
++set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SPI_DI -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SPI_DO -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SPI_SS2 -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "data_io:mist_spi_interface|SPI_CLK" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
++set_global_assignment -name QIP_FILE mist_sector_buffer.qip
++set_global_assignment -name VHDL_FILE covox.vhd
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SPI_DI -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SPI_DO -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SPI_SS2 -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
++set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=119" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=119" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=382" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=25945" -section_id auto_signaltap_0
++set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=37736" -section_id auto_signaltap_0
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+\ No newline at end of file
+Binary files atari800core_v1_20140121_mcc216/atari800core.qws and atari800core_v1_20140312_mist/atari800core.qws differ
+diff -ur atari800core_v1_20140121_mcc216/atari800core.sdc atari800core_v1_20140312_mist/atari800core.sdc
+--- atari800core_v1_20140121_mcc216/atari800core.sdc	2014-01-21 19:27:45.000000000 +0000
++++ atari800core_v1_20140312_mist/atari800core.sdc	2014-02-16 08:53:36.000000000 +0000
+@@ -1,3 +1,3 @@
+-create_clock -period 5MHz [get_ports FPGA_CLK]
++create_clock -period 27MHz [get_ports CLOCK_27[0]]
+ derive_pll_clocks
+ derive_clock_uncertainty
+\ No newline at end of file
+diff -ur atari800core_v1_20140121_mcc216/atari800core.vhd atari800core_v1_20140312_mist/atari800core.vhd
+--- atari800core_v1_20140121_mcc216/atari800core.vhd	2014-01-28 20:47:59.000000000 +0000
++++ atari800core_v1_20140312_mist/atari800core.vhd	2014-03-12 05:00:20.000000000 +0000
+@@ -18,49 +18,155 @@
+ 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all; 
++use ieee.numeric_std.all;
+ 
+ LIBRARY work;
+ 
+ ENTITY atari800core IS 
+ 	PORT
+ 	(
+-		FPGA_CLK :  IN  STD_LOGIC;
+-		PS2K_CLK :  IN  STD_LOGIC;
+-		PS2K_DAT :  IN  STD_LOGIC;
+-		PS2M_CLK :  IN  STD_LOGIC;
+-		PS2M_DAT :  IN  STD_LOGIC;		
++		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
++--		PS2K_CLK :  IN  STD_LOGIC;
++--		PS2K_DAT :  IN  STD_LOGIC;
++--		PS2M_CLK :  IN  STD_LOGIC;
++--		PS2M_DAT :  IN  STD_LOGIC;		
+ 
+ 		VGA_VS :  OUT  STD_LOGIC;
+ 		VGA_HS :  OUT  STD_LOGIC;
+-		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
++		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+ 		
+-		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++--		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++--		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+ 		
+ 		AUDIO_L : OUT std_logic;
+ 		AUDIO_R : OUT std_logic;
+ 
+ 		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+-		SDRAM_CS_N :  OUT  STD_LOGIC;
+-		SDRAM_RAS_N :  OUT  STD_LOGIC;
+-		SDRAM_CAS_N :  OUT  STD_LOGIC;
+-		SDRAM_WE_N :  OUT  STD_LOGIC;
+-		SDRAM_DQM_n :  OUT  STD_LOGIC_vector(1 downto 0);
++		SDRAM_nCS :  OUT  STD_LOGIC;
++		SDRAM_nRAS :  OUT  STD_LOGIC;
++		SDRAM_nCAS :  OUT  STD_LOGIC;
++		SDRAM_nWE :  OUT  STD_LOGIC;
++		SDRAM_DQMH :  OUT  STD_LOGIC;
++		SDRAM_DQML :  OUT  STD_LOGIC;
+ 		SDRAM_CLK :  OUT  STD_LOGIC;
+-		--SDRAM_CKE :  OUT  STD_LOGIC;
++		SDRAM_CKE :  OUT  STD_LOGIC;
+ 		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+ 		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ 
+-		SD_DAT0 :  IN  STD_LOGIC;
+-		SD_CLK :  OUT  STD_LOGIC;
+-		SD_CMD :  OUT  STD_LOGIC;
+-		SD_DAT3 :  OUT  STD_LOGIC
++--		SD_DAT0 :  IN  STD_LOGIC;
++--		SD_CLK :  OUT  STD_LOGIC;
++--		SD_CMD :  OUT  STD_LOGIC;
++--		SD_DAT3 :  OUT  STD_LOGIC
++
++		LED : OUT std_logic;
++		
++		UART_TX :  OUT  STD_LOGIC;
++		UART_RX :  IN  STD_LOGIC;
++		
++		SPI_DO :  INOUT  STD_LOGIC;
++		SPI_DI :  IN  STD_LOGIC;
++		SPI_SCK :  IN  STD_LOGIC;
++		SPI_SS2 :  IN  STD_LOGIC;		
++		SPI_SS3 :  IN  STD_LOGIC;		
++		SPI_SS4 :  IN  STD_LOGIC;
++		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
+ 	);
+ END atari800core;
+ 
+ ARCHITECTURE bdf_type OF atari800core IS 
++--
++--component generic_ram_infer IS
++--	generic
++--	(
++--		ADDRESS_WIDTH : natural := 9;
++--		SPACE : natural := 512;
++--		DATA_WIDTH : natural := 8
++--	);
++--   PORT
++--   (
++--      clock: IN   std_logic;
++--      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
++--      address:  IN   std_logic_vector(address_width-1 downto 0);
++--      we:    IN   std_logic;
++--      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
++--   );
++--END component;
++
++component mist_sector_buffer IS
++	PORT
++	(
++		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
++		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
++		clock_a		: IN STD_LOGIC  := '1';
++		clock_b		: IN STD_LOGIC ;
++		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
++		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
++		wren_a		: IN STD_LOGIC  := '0';
++		wren_b		: IN STD_LOGIC  := '0';
++		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
++		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
++	);
++END component;
++
++component synchronizer IS
++PORT 
++( 
++	CLK : IN STD_LOGIC;
++	RAW : IN STD_LOGIC;
++	SYNC : OUT STD_LOGIC
++);
++END component;
++
++component data_io IS 
++	PORT
++	(
++		CLK : in std_logic;
++		RESET_n : in std_logic;
++		
++		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
++	   SPI_CLK : in std_logic;
++	   SPI_SS_IO : in std_logic;
++	   SPI_MISO: out std_logic;
++	   SPI_MOSI : in std_logic;
++		
++		-- Sector access request
++		request : in std_logic;
++		sector : in std_logic_vector(23 downto 0);
++		ready : out std_logic;
++		
++		-- DMA to RAM
++		ADDR: out std_logic_vector(8 downto 0);
++		DATA_OUT : out std_logic_vector(7 downto 0);
++		DATA_IN : in std_logic_vector(7 downto 0);
++		WR_EN : out std_logic
++	 );
++end component;
++
++component user_io
++	PORT(
++	   SPI_CLK : in std_logic;
++	   SPI_SS_IO : in std_logic;
++	   SPI_MISO : out std_logic;
++	   SPI_MOSI : in std_logic;
++	   CORE_TYPE : in std_logic_vector(7 downto 0);
++		JOY0 : out std_logic_vector(5 downto 0);
++		JOY1 : out std_logic_vector(5 downto 0);
++		KEYBOARD : out std_logic_vector(127 downto 0);
++		BUTTONS : out std_logic_vector(1 downto 0);
++		SWITCHES : out std_logic_vector(1 downto 0)
++	  );
++end component;
++
++COMPONENT complete_address_decoder IS
++generic (width : natural := 1);
++PORT 
++( 
++	addr_in : in std_logic_vector(width-1 downto 0);			
++	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
++);
++END component;
+ 
+ COMPONENT cpu
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -151,6 +257,8 @@
+ 		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
++		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
++		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+ 		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ 	);
+@@ -177,6 +285,7 @@
+ 		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
++		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 MEMORY_FETCH : OUT STD_LOGIC;
+ 		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+ 		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+@@ -328,9 +437,11 @@
+ 		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
++		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ 		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
++		 rom_select : in std_logic_vector(5 downto 0);
++		 cart_select : in std_logic_vector(6 downto 0);
++		 cart_activate : in std_logic;
+ 		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+ 		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+@@ -363,7 +474,8 @@
+ 		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+ 		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+ 		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+-		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
++		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
++		 D6_WR_ENABLE : out std_logic
+ 	);
+ END COMPONENT;
+ 
+@@ -386,7 +498,7 @@
+ 		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+ 		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 REPLY : OUT STD_LOGIC;
++		 COMPLETE : OUT STD_LOGIC;
+ 		 SDRAM_BA0 : OUT STD_LOGIC;
+ 		 SDRAM_BA1 : OUT STD_LOGIC;
+ 		 SDRAM_CKE : OUT STD_LOGIC;
+@@ -509,10 +621,13 @@
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+-		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
++		 RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
++		 ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+-		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
++		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
++		 sector : out std_logic_vector(31 downto 0);
++		 sector_request : out std_logic;
++		 sector_ready : in std_logic
+ 	);
+ END COMPONENT;
+ 
+@@ -581,6 +696,20 @@
+ );
+ END component;
+ 
++component covox IS
++PORT 
++( 
++	CLK : IN STD_LOGIC;
++	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
++	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
++	WR_EN : IN STD_LOGIC;
++	
++	covox_channel0 : out std_logic_vector(7 downto 0);
++	covox_channel1 : out std_logic_vector(7 downto 0);
++	covox_channel2 : out std_logic_vector(7 downto 0);
++	covox_channel3 : out std_logic_vector(7 downto 0)
++);
++END component;
+ 
+ SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+@@ -642,7 +771,7 @@
+ SIGNAL	GTIA_SOUND :  STD_LOGIC;
+ SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	IRQ_n :  STD_LOGIC;
+-SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
++SIGNAL	KBCODE_DUMMY :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	KEY_HELD :  STD_LOGIC;
+ SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+ SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+@@ -682,14 +811,14 @@
+ SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	RAM_REQUEST :  STD_LOGIC;
+ SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
++SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	RESET_N :  STD_LOGIC;
+ SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+ SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	ROM_REQUEST :  STD_LOGIC;
+ SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
++SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+ SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+ SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+@@ -733,6 +862,7 @@
+ SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	ZPU_RESET :  STD_LOGIC;
+ SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
++SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+ SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+@@ -754,10 +884,344 @@
+ SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ signal UART_TXD_dummy : std_logic;
+ 
++-- STUB OUT FOR NOW
++SIGNAL		PS2K_CLK :  STD_LOGIC;
++SIGNAL		PS2K_DAT :  STD_LOGIC;
++signal		JOY1_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
++signal		JOY2_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
++signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
++signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
++
++
++SIGNAL		SD_DAT0 :  STD_LOGIC;
++SIGNAL		SD_CLK :  STD_LOGIC;
++SIGNAL		SD_CMD :  STD_LOGIC;
++SIGNAL		SD_DAT3 :  STD_LOGIC;
++
++signal mist_buttons : std_logic_vector(1 downto 0);
++signal mist_switches : std_logic_vector(1 downto 0);
++
++signal keyboard : std_logic_vector(127 downto 0);
++signal atari_keyboard : std_logic_vector(63 downto 0);
++
++SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
++SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
++SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
++
++SIGNAL	CONSOL_OPTION_DUMMY :  STD_LOGIC;
++SIGNAL	CONSOL_SELECT_DUMMY :  STD_LOGIC;
++SIGNAL	CONSOL_START_DUMMY :  STD_LOGIC;
++
++signal capslock_pressed : std_logic;
++signal capsheld_next : std_logic;
++signal capsheld_reg : std_logic;
++
++signal mist_sector_ready : std_logic;
++signal mist_sector_ready_sync : std_logic;
++signal mist_sector_request : std_logic;
++signal mist_sector_request_sync : std_logic;
++signal mist_sector : std_logic_vector(31 downto 0);
++signal mist_sector_sync : std_logic_vector(31 downto 0);
++
++		
++signal mist_addr : std_logic_vector(8 downto 0);
++signal mist_do : std_logic_vector(7 downto 0);
++signal mist_di : std_logic_vector(7 downto 0);
++signal mist_wren : std_logic;
++
++signal spi_miso_data : std_logic;
++signal spi_miso_io : std_logic;
++
++signal covox_write_enable : std_logic;
++signal covox_channel0 : std_logic_vector(7 downto 0);
++signal covox_channel1 : std_logic_vector(7 downto 0);
++signal covox_channel2 : std_logic_vector(7 downto 0);
++signal covox_channel3 : std_logic_vector(7 downto 0);
++
+ BEGIN 
+ 
++	
++-- mist spi io
++mist_spi_interface : data_io 
++	PORT map
++	(
++		CLK =>spi_sck,
++		RESET_n =>reset_n,
++		
++		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
++		SPI_CLK =>spi_sck,
++		SPI_SS_IO => spi_ss2,
++		SPI_MISO => spi_miso_data,
++		SPI_MOSI => spi_di,
++		
++		-- Sector access request
++		request => mist_sector_request_sync,
++		sector => mist_sector_sync(23 downto 0),
++		ready => mist_sector_ready,
++		
++		-- DMA to RAM
++		ADDR => mist_addr,
++		DATA_OUT => mist_do,
++		DATA_IN => mist_di,
++		WR_EN => mist_wren
++	 );
++ 
++	select_sync : synchronizer
++	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
++
++	select_sync2 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
++
++	sector_sync0 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
++
++	sector_sync1 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
++
++	sector_sync2 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
++
++	sector_sync3 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
++
++	sector_sync4 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
++
++	sector_sync5 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
++
++	sector_sync6 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
++
++	sector_sync7 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
++
++	sector_sync8 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
++
++	sector_sync9 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
++
++	sector_sync10 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
++
++	sector_sync11 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
++
++	sector_sync12 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
++
++	sector_sync13 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
++
++	sector_sync14 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
++
++	sector_sync15 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
++
++	sector_sync16 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
++
++	sector_sync17 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
+ 
++	sector_sync18 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
++
++	sector_sync19 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
++
++	sector_sync20 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
++
++	sector_sync21 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
++
++	sector_sync22 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
++
++	sector_sync23 : synchronizer
++	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
++	
++	
++	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
++
++	-- TODO, dual port, dual clock! 
++--	mist_sector_buffer : generic_ram_infer
++--	generic map
++--	(
++--		ADDRESS_WIDTH => 9,
++--		SPACE => 512,
++--		DATA_WIDTH => 8
++--	)
++--   PORT map
++--   (
++--      clock => spi_sck,
++--      data => mist_do,
++--      address => mist_addr,
++--      we => mist_wren,
++--      q => mist_di
++--   );
++
++mist_sector_buffer1 : mist_sector_buffer
++	PORT map
++	(
++		address_a		=> mist_addr,
++		address_b		=> ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
++		clock_a		=> spi_sck,
++		clock_b		=> clk,
++		data_a		=> mist_do,
++		data_b		=> zpu_do,
++		wren_a		=> mist_wren,
++		wren_b		=> '0',
++		q_a		=> mist_di,
++		q_b		=> zpu_sector_data
++	);
++	
++my_user_io : user_io
++	PORT map(
++	   SPI_CLK => SPI_SCK,
++	   SPI_SS_IO => CONF_DATA0,
++	   SPI_MISO => SPI_miso_io,
++	   SPI_MOSI => SPI_DI,
++	   CORE_TYPE => x"A4",
++		JOY0 => joy1,
++		JOY1 => joy2,
++		KEYBOARD => keyboard,
++		BUTTONS => mist_buttons,
++		SWITCHES => mist_switches
++	  );
++	  
++	 joy1_n <= not(joy1);
++	 joy2_n <= not(joy2);
++	 
++	process(clk,reset_n)
++	begin
++		if (reset_n='0') then
++			capsheld_reg <= '0';
++		elsif (clk'event and clk='1') then
++			capsheld_reg <= capsheld_next;
++		end if;
++	end process;
++
++	process(keyboard,capsheld_reg)
++	begin
++		capsheld_next <= capsheld_reg;
++		capslock_pressed <= '0';
++		
++		if ((keyboard(58) xor capsheld_reg)='1') then
++			capsheld_next <= keyboard(58);
++			
++			-- assert something for 10 frames
++			capslock_pressed <= '1';
++		end if;
++	end process;
++	
++atari_keyboard(63) <= keyboard(30);
++atari_keyboard(62) <= keyboard(31);
++atari_keyboard(61) <= keyboard(34);
++atari_keyboard(60) <= '0';
++atari_keyboard(58) <= keyboard(32);
++atari_keyboard(57) <= keyboard(35);
++atari_keyboard(56) <= keyboard(33);
++atari_keyboard(55) <= keyboard(13);
++atari_keyboard(54) <= keyboard(12);
++atari_keyboard(53) <= keyboard(9);
++atari_keyboard(52) <= keyboard(14);
++atari_keyboard(51) <= keyboard(8);
++atari_keyboard(50) <= keyboard(11);
++atari_keyboard(48) <= keyboard(10);
++atari_keyboard(47) <= keyboard(16);
++atari_keyboard(46) <= keyboard(17);
++atari_keyboard(45) <= keyboard(20);
++atari_keyboard(44) <= keyboard(15);
++atari_keyboard(43) <= keyboard(21);
++atari_keyboard(42) <= keyboard(18);
++atari_keyboard(40) <= keyboard(19);
++atari_keyboard(39) <= keyboard(56);
++atari_keyboard(38) <= keyboard(53);
++atari_keyboard(37) <= keyboard(50);
++atari_keyboard(35) <= keyboard(49);
++atari_keyboard(34) <= keyboard(52);
++atari_keyboard(33) <= keyboard(57);
++atari_keyboard(32) <= keyboard(51);
++atari_keyboard(31) <= keyboard(2);
++atari_keyboard(30) <= keyboard(3);
++atari_keyboard(29) <= keyboard(6);
++atari_keyboard(28) <= keyboard(1);
++atari_keyboard(27) <= keyboard(7);
++atari_keyboard(26) <= keyboard(4);
++atari_keyboard(24) <= keyboard(5);
++atari_keyboard(23) <= keyboard(44);
++atari_keyboard(22) <= keyboard(45);
++atari_keyboard(21) <= keyboard(48);
++atari_keyboard(18) <= keyboard(46);
++atari_keyboard(17) <= keyboard(59);
++atari_keyboard(16) <= keyboard(47);
++atari_keyboard(15) <= keyboard(27);
++atari_keyboard(14) <= keyboard(26);
++atari_keyboard(13) <= keyboard(23);
++atari_keyboard(12) <= keyboard(28);
++atari_keyboard(11) <= keyboard(22);
++atari_keyboard(10) <= keyboard(25);
++atari_keyboard(8) <= keyboard(24);
++atari_keyboard(7) <= keyboard(41);
++atari_keyboard(6) <= keyboard(40);
++atari_keyboard(5) <= keyboard(37);
++atari_keyboard(2) <= keyboard(39);
++atari_keyboard(1) <= keyboard(36);
++atari_keyboard(0) <= keyboard(38);
++
++	  
++shift_pressed <= keyboard(54) or keyboard(42);
++control_pressed <= keyboard(29);
++break_pressed <= keyboard(96); -- TODO - not on st keyboard
++
++consol_start <= keyboard(60); --F2
++consol_select <= keyboard(61); --F3
++consol_option <= keyboard(62); -- F4
++		
++--f5 <= keyboard(63);
++--f6 <= keyboard(64);
++--f7 <= keyboard(65);
++--f8 <= keyboard(66);
++--f9 <= keyboard(67);
++--f10 <= keyboard(68);
++
++virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
++SYSTEM_RESET_REQUEST <= keyboard(63);
++
++process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
++	begin	
++		keyboard_response <= (others=>'1');		
++		
++		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
++			keyboard_response(0) <= '0';
++		end if;
++		
++--		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
++--			keyboard_response(0) <= '0';
++--		end if;
++		
++		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++		
++		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
++			keyboard_response(1) <= '0';
++		end if;
+ 
++		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++end process;		 
++		  
++	-- decode address
++--decode_addr1 : complete_address_decoder
++--	generic map(width=>6)
++--	port map (addr_in=>keyboard_scan, addr_decoded=>keyboard_scan_decoded);
++	  
+ b2v_a_6502 : cpu
+ PORT MAP(CLK => CLK,
+ 		 RESET => CPU_6502_RESET,
+@@ -804,6 +1268,8 @@
+ 		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+ 		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+ 		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
++		 COVOX_CHANNEL_0 => covox_channel0,
++		 COVOX_CHANNEL_1 => covox_channel1,
+ 		 CHANNEL_ENABLE => "1111",
+ 		 VOLUME_OUT => AUDIO_LEFT);
+ 		 
+@@ -848,6 +1314,7 @@
+ 		 ZPU_DI => MEMORY_DATA,
+ 		 ZPU_RAM_DI => ZPU_RAM_DATA,
+ 		 ZPU_ROM_DI => ZPU_ROM_DATA,
++		 ZPU_SECTOR_DI => zpu_sector_data,
+ 		 MEMORY_FETCH => ZPU_FETCH,
+ 		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+ 		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+@@ -867,6 +1334,8 @@
+ 		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+ 		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+ 		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
++		 COVOX_CHANNEL_0 => covox_channel2,
++		 COVOX_CHANNEL_1 => covox_channel3, 
+ 		 CHANNEL_ENABLE => "1111",
+ 		 VOLUME_OUT => AUDIO_RIGHT);
+ 
+@@ -944,24 +1413,26 @@
+ 		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+ 
+ 
+-b2v_inst18 : pokey_ps2_decoder
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+-		 KEY_UP => SYNTHESIZED_WIRE_10,
+-		 KEY_CODE => SYNTHESIZED_WIRE_11,
+-		 KEY_HELD => KEY_HELD,
+-		 SHIFT_PRESSED => SHIFT_PRESSED,
+-		 BREAK_PRESSED => BREAK_PRESSED,
+-		 CONSOL_START => CONSOL_START,
+-		 CONSOL_SELECT => CONSOL_SELECT,
+-		 CONSOL_OPTION => CONSOL_OPTION,
+-		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+-		 KBCODE => KBCODE,
+-		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+-		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+-		 VIRTUAL_KEYS => VIRTUAL_KEYS);
++virtual_sticks <= (others=>'1');
++virtual_triggers <= "0011";
++--b2v_inst18 : pokey_ps2_decoder
++--PORT MAP(CLK => CLK,
++--		 RESET_N => RESET_N,
++--		 KEY_EVENT => SYNTHESIZED_WIRE_8,
++--		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
++--		 KEY_UP => SYNTHESIZED_WIRE_10,
++--		 KEY_CODE => SYNTHESIZED_WIRE_11,
++--		 KEY_HELD => KEY_HELD,
++--		 SHIFT_PRESSED => SHIFT_PRESSED_DUMMY,
++--		 BREAK_PRESSED => BREAK_PRESSED_DUMMY,
++--		 CONSOL_START => CONSOL_START_DUMMY,
++--		 CONSOL_SELECT => CONSOL_SELECT_DUMMY,
++--		 CONSOL_OPTION => CONSOL_OPTION_DUMMY,
++--		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
++--		 KBCODE => KBCODE_dummy,
++--		 VIRTUAL_STICKS => VIRTUAL_STICKS,
++--		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
++--		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+ 
+ -- no cart!
+ CART_RD4 <= '0';
+@@ -1003,9 +1474,9 @@
+ 		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+ 		 PORTB => PORTB_OUT,
+ 		 RAM_DATA => RAM_DO,
+-		 ram_select => RAM_SELECT,
++		 ram_select => RAM_SELECT(2 downto 0),
+ 		 ROM_DATA => ROM_DO,
+-		 rom_select => ROM_SELECT,
++		 rom_select => "00"&ROM_SELECT, -- TODO
+ 		 SDRAM_DATA => SDRAM_DO,
+ 		 ZPU_ADDR => ZPU_ADDR_FETCH,
+ 		 ZPU_WRITE_DATA => ZPU_DO,
+@@ -1038,7 +1509,10 @@
+ 		 RAM_ADDR => RAM_ADDR,
+ 		 ROM_ADDR => ROM_ADDR,
+ 		 SDRAM_ADDR => SDRAM_ADDR,
+-		 WRITE_DATA => WRITE_DATA);
++		 WRITE_DATA => WRITE_DATA,
++		 d6_wr_enable => covox_write_enable,
++		 cart_select => "0000000",
++		 cart_activate => '0');
+ 
+ b2v_inst21 : zpu_rom
+ PORT MAP(clock => CLK,
+@@ -1058,10 +1532,9 @@
+ 		 colour_in => SYNTHESIZED_WIRE_14,
+ 		 VSYNC => VGA_VS,
+ 		 HSYNC => VGA_HS,
+-		 B => VGA_B,
+-		 G => VGA_G,
+-		 R => VGA_R);
+-
++		 B => VGA_B(5 downto 2),
++		 G => VGA_G(5 downto 2),
++		 R => VGA_R(5 downto 2));
+ 
+ b2v_inst23 : zpu_ram
+ PORT MAP(wren => ZPU_STACK_WRITE(2),
+@@ -1105,7 +1578,11 @@
+ 		 RAM_SELECT => RAM_SELECT,
+ 		 ROM_SELECT => ROM_SELECT,
+ 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+-		 ZPU_HEX => ZPU_HEX);
++		 ZPU_HEX => ZPU_HEX,
++		 sector_request => mist_sector_request,
++		 sector => mist_sector,
++		 sector_ready => mist_sector_ready_sync
++		 );
+ 
+ 
+ b2v_inst25 : zpu_ram
+@@ -1133,7 +1610,7 @@
+ 
+ 
+ b2v_inst5 : pll
+-PORT MAP(inclk0 => FPGA_CLK,
++PORT MAP(inclk0 => CLOCK_27(0),
+ 		 c0 => CLK_SDRAM,
+ 		 c1 => CLK,
+ 		 c2 => SDRAM_CLK,
+@@ -1164,27 +1641,27 @@
+ 		 DATA_OUT => POKEY_DO,
+ 		 keyboard_scan => KEYBOARD_SCAN);
+ 
+-	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+-	begin	
+-		keyboard_response <= (others=>'1');
+-		
+-		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+-			keyboard_response(0) <= '0';
+-		end if;
+-		
+-		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+-			keyboard_response(1) <= '0';
+-		end if;
+-		
+-		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+-			keyboard_response(1) <= '0';
+-		end if;
+-
+-		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
+-			keyboard_response(1) <= '0';
+-		end if;
+-	end process;		 
+-		 	 
++--	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
++--	begin	
++--		keyboard_response <= (others=>'1');
++--		
++--		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
++--			keyboard_response(0) <= '0';
++--		end if;
++--		
++--		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
++--			keyboard_response(1) <= '0';
++--		end if;
++--		
++--		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
++--			keyboard_response(1) <= '0';
++--		end if;
++--
++--		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
++--			keyboard_response(1) <= '0';
++--		end if;
++--	end process;		 
++--		 	 
+ b2v_inst8 : gtia
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => GTIA_WRITE_ENABLE,
+@@ -1281,39 +1758,7 @@
+ 	RAM_DATA => ram_do(7 downto 0)
+ 	);
+ 
+---b2v_inst20 : sdram_statemachine
+---GENERIC MAP(ADDRESS_WIDTH => 22,
+---			AP_BIT => 10,
+---			COLUMN_WIDTH => 8,
+---			ROW_WIDTH => 12
+---			)
+---PORT MAP(CLK_SYSTEM => CLK,
+---		 CLK_SDRAM => CLK_SDRAM,
+---		 RESET_N => RESET_N,
+---		 READ_EN => SDRAM_READ_ENABLE,
+---		 WRITE_EN => SDRAM_WRITE_ENABLE,
+---		 REQUEST => SDRAM_REQUEST,
+---		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+---		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+---		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+---		 REFRESH => SDRAM_REFRESH,
+---		 ADDRESS_IN => SDRAM_ADDR,
+---		 DATA_IN => WRITE_DATA,
+---		 SDRAM_DQ => SDRAM_DQ,
+---		 REPLY => SDRAM_REPLY,
+---		 SDRAM_BA0 => SDRAM_BA(0),
+---		 SDRAM_BA1 => SDRAM_BA(1),
+---		 SDRAM_CKE => SDRAM_A(12),
+---		 SDRAM_CS_N => SDRAM_CS_N,
+---		 SDRAM_RAS_N => SDRAM_RAS_N,
+---		 SDRAM_CAS_N => SDRAM_CAS_N,
+---		 SDRAM_WE_N => SDRAM_WE_N,
+---		 SDRAM_ldqm => SDRAM_DQM_n(0),
+---		 SDRAM_udqm => SDRAM_DQM_n(1),
+---		 DATA_OUT => SDRAM_DO,
+---		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+-
+-b2v_inst20 : sdram_statemachine_mcc
++b2v_inst20 : sdram_statemachine
+ GENERIC MAP(ADDRESS_WIDTH => 22,
+ 			AP_BIT => 10,
+ 			COLUMN_WIDTH => 8,
+@@ -1332,18 +1777,70 @@
+ 		 ADDRESS_IN => SDRAM_ADDR,
+ 		 DATA_IN => WRITE_DATA,
+ 		 SDRAM_DQ => SDRAM_DQ,
+-		 REPLY => SDRAM_REQUEST_COMPLETE,
++		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+ 		 SDRAM_BA0 => SDRAM_BA(0),
+ 		 SDRAM_BA1 => SDRAM_BA(1),
+-		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+-		 SDRAM_CS_N => SDRAM_CS_N,
+-		 SDRAM_RAS_N => SDRAM_RAS_N,
+-		 SDRAM_CAS_N => SDRAM_CAS_N,
+-		 SDRAM_WE_N => SDRAM_WE_N,
+-		 SDRAM_ldqm => SDRAM_DQM_n(0),
+-		 SDRAM_udqm => SDRAM_DQM_n(1),
++		 SDRAM_CKE => SDRAM_CKE,
++		 SDRAM_CS_N => SDRAM_nCS,
++		 SDRAM_RAS_N => SDRAM_nRAS,
++		 SDRAM_CAS_N => SDRAM_nCAS,
++		 SDRAM_WE_N => SDRAM_nWE,
++		 SDRAM_ldqm => SDRAM_DQML,
++		 SDRAM_udqm => SDRAM_DQMH,
+ 		 DATA_OUT => SDRAM_DO,
+-		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
++		 SDRAM_ADDR => SDRAM_A(11 downto 0));
++		 
++SDRAM_A(12) <= '0';
++
++--b2v_inst20 : sdram_statemachine_mcc
++--GENERIC MAP(ADDRESS_WIDTH => 22,
++--			AP_BIT => 10,
++--			COLUMN_WIDTH => 8,
++--			ROW_WIDTH => 12
++--			)
++--PORT MAP(CLK_SYSTEM => CLK,
++--		 CLK_SDRAM => CLK_SDRAM,
++--		 RESET_N => RESET_N,
++--		 READ_EN => SDRAM_READ_ENABLE,
++--		 WRITE_EN => SDRAM_WRITE_ENABLE,
++--		 REQUEST => SDRAM_REQUEST,
++--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
++--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
++--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
++--		 REFRESH => SDRAM_REFRESH,
++--		 ADDRESS_IN => SDRAM_ADDR,
++--		 DATA_IN => WRITE_DATA,
++--		 SDRAM_DQ => SDRAM_DQ,
++--		 REPLY => SDRAM_REQUEST_COMPLETE,
++--		 SDRAM_BA0 => SDRAM_BA(0),
++--		 SDRAM_BA1 => SDRAM_BA(1),
++--		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
++--		 SDRAM_CS_N => SDRAM_nCS,
++--		 SDRAM_RAS_N => SDRAM_nRAS,
++--		 SDRAM_CAS_N => SDRAM_nCAS,
++--		 SDRAM_WE_N => SDRAM_nWE,
++--		 SDRAM_ldqm => SDRAM_DQML,
++--		 SDRAM_udqm => SDRAM_DQMH,
++--		 DATA_OUT => SDRAM_DO,
++--		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
+ 
++--SDRAM_CKE <= '1';		 
++LED <= '0';
++VGA_R(1 downto 0) <= "00";
++VGA_G(1 downto 0) <= "00";
++VGA_B(1 downto 0) <= "00";
++
++covox1 : covox
++	PORT map
++	( 
++		clk => clk,
++		addr => pbi_addr(1 downto 0),
++		data_in => WRITE_DATA(7 DOWNTO 0),
++		wr_en => covox_write_enable,
++		covox_channel0 => covox_channel0,
++		covox_channel1 => covox_channel1,
++		covox_channel2 => covox_channel2,
++		covox_channel3 => covox_channel3
++	);
+ 		
+ END bdf_type;
+\ No newline at end of file
+Only in atari800core_v1_20140312_mist/: ataribas.mif
+Only in atari800core_v1_20140312_mist/: basic.cmp
+Only in atari800core_v1_20140312_mist/: basic.qip
+Only in atari800core_v1_20140312_mist/: basic.vhd
+Only in atari800core_v1_20140312_mist/: covox.vhd
+Only in atari800core_v1_20140312_mist/: covox.vhd.bak
+Only in atari800core_v1_20140312_mist/: custom_io.vhd
+Only in atari800core_v1_20140312_mist/: data_io.v~
+Only in atari800core_v1_20140312_mist/: data_io.vhdl
+Only in atari800core_v1_20140312_mist/: data_io.vhdl.bak
+Only in atari800core_v1_20140312_mist/: generic_ram_infer.vhdl
+Only in atari800core_v1_20140312_mist/: generic_ram_infer.vhdl.bak
+diff -ur atari800core_v1_20140121_mcc216/internalromram.vhd atari800core_v1_20140312_mist/internalromram.vhd
+--- atari800core_v1_20140121_mcc216/internalromram.vhd	2014-01-21 20:44:04.000000000 +0000
++++ atari800core_v1_20140312_mist/internalromram.vhd	2014-03-08 17:35:06.000000000 +0000
+@@ -34,16 +34,16 @@
+ 	);
+ END component;
+ 
+-component romlo IS
++component rom16 IS
+ 	PORT
+ 	(
+-		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
++		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ 		clock		: IN STD_LOGIC  := '1';
+ 		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ 	);
+ END component;
+ 
+-component romhi IS
++component basic IS
+ 	PORT
+ 	(
+ 		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+@@ -55,8 +55,8 @@
+ 	signal rom_request_reg : std_logic;
+ 	signal ram_request_reg : std_logic;
+ 	
+-	signal ROMLO_DATA : std_logic_vector(7 downto 0);
+-	signal ROMHI_DATA : std_logic_vector(7 downto 0);
++	signal ROM16_DATA : std_logic_vector(7 downto 0);
++	signal BASIC_DATA : std_logic_vector(7 downto 0);	
+ 	
+ 	signal RAM_WR_ENABLE_REAL : std_logic;
+ 	signal IRAM_DATA : std_logic_vector(7 downto 0);
+@@ -74,26 +74,42 @@
+ 	end process;
+ 
+ 	rom_request_complete <= rom_request_reg;
+-	ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
+-	romlo1 : romlo
+-	PORT MAP(clock => clock,
+-			 address => rom_addr(10 downto 0),
+-			 q => ROMLO_data
+-			 );	
+-	romhi1 : romhi
+-	PORT MAP(clock => clock,
+-			 address => rom_addr(12 downto 0),
+-			 q => ROMHI_data
+-			 );
+-	
+-	ramint1 : ramint
+-	PORT MAP(clock => clock,
+-			 address => ram_addr(12 downto 0),
+-			 data => ram_data_in(7 downto 0),
+-			 wren => RAM_WR_ENABLE_REAL,
+-			 q => iram_data
+-			 );	
++	--C000 = basic. 
++	--0000-07FF = low
++	--0800-27ff high
++	
++	process(rom16_data,basic_data, rom_addr(15 downto 0))
++	begin
++		ROM_DATA <= ROM16_DATA;
++		if (rom_addr(15)='1') then
++			ROM_DATA <= BASIC_DATA;
++		end if;
++	end process;
++	
++	
++	--ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
++	--ROM_DATA <= ROMHI_DATA;
++--	basic1 : basic
++--	PORT MAP(clock => clock,
++--			 address => rom_addr(12 downto 0),
++--			 q => BASIC_data
++--			 );			 
++--			 
++--	rom16a : rom16
++--	PORT MAP(clock => clock,
++--			 address => rom_addr(13 downto 0),
++--			 q => ROM16_data
++--			 );
++--	
++--	ramint1 : ramint
++--	PORT MAP(clock => clock,
++--			 address => ram_addr(12 downto 0),
++--			 data => ram_data_in(7 downto 0),
++--			 wren => RAM_WR_ENABLE_REAL,
++--			 q => iram_data
++--			 );	
+ 	ram_request_complete <= ram_request_reg;
++	
+ 	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
+ 	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
+ end vhdl;
+\ No newline at end of file
+Only in atari800core_v1_20140312_mist/: mist_sector_buffer.cmp
+Only in atari800core_v1_20140312_mist/: mist_sector_buffer.qip
+Only in atari800core_v1_20140312_mist/: mist_sector_buffer.vhd
+Only in atari800core_v1_20140312_mist/: os16.mif
+Only in atari800core_v1_20140312_mist/: output_file.rbf
+diff -ur atari800core_v1_20140121_mcc216/pll.bsf atari800core_v1_20140312_mist/pll.bsf
+--- atari800core_v1_20140121_mcc216/pll.bsf	2014-01-26 09:19:13.000000000 +0000
++++ atari800core_v1_20140312_mist/pll.bsf	2014-03-01 09:10:29.000000000 +0000
+@@ -20,8 +20,8 @@
+ */
+ (header "symbol" (version "1.2"))
+ (symbol
+-	(rect 0 0 248 184)
+-	(text "pll" (rect 118 0 133 16)(font "Arial" (font_size 10)))
++	(rect 0 0 256 184)
++	(text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
+ 	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+ 	(port
+ 		(pt 0 64)
+@@ -31,70 +31,70 @@
+ 		(line (pt 0 64)(pt 40 64))
+ 	)
+ 	(port
+-		(pt 248 64)
++		(pt 256 64)
+ 		(output)
+ 		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+-		(text "c0" (rect 232 50 242 63)(font "Arial" (font_size 8)))
++		(text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8)))
+ 	)
+ 	(port
+-		(pt 248 80)
++		(pt 256 80)
+ 		(output)
+ 		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+-		(text "c1" (rect 232 66 240 79)(font "Arial" (font_size 8)))
++		(text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8)))
+ 	)
+ 	(port
+-		(pt 248 96)
++		(pt 256 96)
+ 		(output)
+ 		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+-		(text "c2" (rect 232 82 242 95)(font "Arial" (font_size 8)))
++		(text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8)))
+ 	)
+ 	(port
+-		(pt 248 112)
++		(pt 256 112)
+ 		(output)
+ 		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+-		(text "locked" (rect 213 98 242 111)(font "Arial" (font_size 8)))
++		(text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8)))
+ 	)
+ 	(drawing
+-		(text "Cyclone III" (rect 186 168 417 347)(font "Arial" ))
+-		(text "inclk0 frequency: 5.000 MHz" (rect 50 59 218 129)(font "Arial" ))
++		(text "Cyclone III" (rect 194 168 433 347)(font "Arial" ))
++		(text "inclk0 frequency: 27.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+ 		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+ 		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+ 		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+-		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+-		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
++		(text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
++		(text "DC (%)" (rect 133 93 296 197)(font "Arial" ))
+ 		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+-		(text "23/2" (rect 74 107 164 225)(font "Arial" ))
+-		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+-		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
++		(text "69/16" (rect 72 107 165 225)(font "Arial" ))
++		(text "0.00" (rect 105 107 226 225)(font "Arial" ))
++		(text "50.00" (rect 137 107 295 225)(font "Arial" ))
+ 		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+-		(text "23/2" (rect 74 121 164 253)(font "Arial" ))
+-		(text "0.00" (rect 104 121 224 253)(font "Arial" ))
+-		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
++		(text "69/32" (rect 72 121 165 253)(font "Arial" ))
++		(text "0.00" (rect 105 121 226 253)(font "Arial" ))
++		(text "50.00" (rect 137 121 295 253)(font "Arial" ))
+ 		(text "c2" (rect 54 135 116 281)(font "Arial" ))
+-		(text "23/2" (rect 74 135 164 281)(font "Arial" ))
+-		(text "0.00" (rect 104 135 224 281)(font "Arial" ))
+-		(text "50.00" (rect 136 135 293 281)(font "Arial" ))
+-		(line (pt 0 0)(pt 249 0))
+-		(line (pt 249 0)(pt 249 185))
+-		(line (pt 0 185)(pt 249 185))
++		(text "69/16" (rect 72 135 165 281)(font "Arial" ))
++		(text "-67.06" (rect 101 135 226 281)(font "Arial" ))
++		(text "50.00" (rect 137 135 295 281)(font "Arial" ))
++		(line (pt 0 0)(pt 257 0))
++		(line (pt 257 0)(pt 257 185))
++		(line (pt 0 185)(pt 257 185))
+ 		(line (pt 0 0)(pt 0 185))
+-		(line (pt 48 91)(pt 164 91))
+-		(line (pt 48 104)(pt 164 104))
+-		(line (pt 48 118)(pt 164 118))
+-		(line (pt 48 132)(pt 164 132))
+-		(line (pt 48 146)(pt 164 146))
++		(line (pt 48 91)(pt 165 91))
++		(line (pt 48 104)(pt 165 104))
++		(line (pt 48 118)(pt 165 118))
++		(line (pt 48 132)(pt 165 132))
++		(line (pt 48 146)(pt 165 146))
+ 		(line (pt 48 91)(pt 48 146))
+ 		(line (pt 69 91)(pt 69 146)(line_width 3))
+-		(line (pt 95 91)(pt 95 146)(line_width 3))
+-		(line (pt 129 91)(pt 129 146)(line_width 3))
+-		(line (pt 163 91)(pt 163 146))
+-		(line (pt 40 48)(pt 199 48))
+-		(line (pt 199 48)(pt 199 167))
+-		(line (pt 40 167)(pt 199 167))
++		(line (pt 96 91)(pt 96 146)(line_width 3))
++		(line (pt 130 91)(pt 130 146)(line_width 3))
++		(line (pt 164 91)(pt 164 146))
++		(line (pt 40 48)(pt 207 48))
++		(line (pt 207 48)(pt 207 167))
++		(line (pt 40 167)(pt 207 167))
+ 		(line (pt 40 48)(pt 40 167))
+-		(line (pt 247 64)(pt 199 64))
+-		(line (pt 247 80)(pt 199 80))
+-		(line (pt 247 96)(pt 199 96))
+-		(line (pt 247 112)(pt 199 112))
++		(line (pt 255 64)(pt 207 64))
++		(line (pt 255 80)(pt 207 80))
++		(line (pt 255 96)(pt 207 96))
++		(line (pt 255 112)(pt 207 112))
+ 	)
+ )
+diff -ur atari800core_v1_20140121_mcc216/PLLJ_PLLSPE_INFO.txt atari800core_v1_20140312_mist/PLLJ_PLLSPE_INFO.txt
+--- atari800core_v1_20140121_mcc216/PLLJ_PLLSPE_INFO.txt	2014-02-03 19:43:41.000000000 +0000
++++ atari800core_v1_20140312_mist/PLLJ_PLLSPE_INFO.txt	2014-03-12 05:05:11.000000000 +0000
+@@ -1,5 +1,5 @@
+ PLL_Name	pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
+-PLLJITTER	NA
++PLLJITTER	26
+ PLLSPEmax	84
+ PLLSPEmin	-53
+ 
+diff -ur atari800core_v1_20140121_mcc216/pll.vhd atari800core_v1_20140312_mist/pll.vhd
+--- atari800core_v1_20140121_mcc216/pll.vhd	2014-01-26 09:19:13.000000000 +0000
++++ atari800core_v1_20140312_mist/pll.vhd	2014-03-01 09:10:29.000000000 +0000
+@@ -154,20 +154,20 @@
+ 	altpll_component : altpll
+ 	GENERIC MAP (
+ 		bandwidth_type => "AUTO",
+-		clk0_divide_by => 2,
++		clk0_divide_by => 16,
+ 		clk0_duty_cycle => 50,
+-		clk0_multiply_by => 23,
++		clk0_multiply_by => 69,
+ 		clk0_phase_shift => "0",
+-		clk1_divide_by => 2,
++		clk1_divide_by => 32,
+ 		clk1_duty_cycle => 50,
+-		clk1_multiply_by => 23,
++		clk1_multiply_by => 69,
+ 		clk1_phase_shift => "0",
+-		clk2_divide_by => 2,
++		clk2_divide_by => 16,
+ 		clk2_duty_cycle => 50,
+-		clk2_multiply_by => 23,
+-		clk2_phase_shift => "0",
++		clk2_multiply_by => 69,
++		clk2_phase_shift => "-1600",
+ 		compensate_clock => "CLK0",
+-		inclk0_input_frequency => 200000,
++		inclk0_input_frequency => 37037,
+ 		intended_device_family => "Cyclone III",
+ 		lpm_hint => "CBX_MODULE_PREFIX=pll",
+ 		lpm_type => "altpll",
+@@ -246,15 +246,15 @@
+ -- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+ -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+ -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+--- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
+--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
++-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
++-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
++-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
+ -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+ -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+ -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000"
+--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000"
++-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
++-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
++-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
+ -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+ -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+ -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+@@ -262,7 +262,7 @@
+ -- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+ -- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+ -- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+--- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
++-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+ -- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+ -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+ -- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+@@ -281,13 +281,13 @@
+ -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+ -- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+ -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+--- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
+--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
+--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
++-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
++-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
++-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
+ -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
++-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
+ -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+ -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+ -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+@@ -298,7 +298,7 @@
+ -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+ -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+ -- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
++-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.60000000"
+ -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+ -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+ -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+@@ -340,20 +340,20 @@
+ -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+ -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+ -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+--- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
++-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
+ -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
++-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
+ -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
++-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
+ -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
++-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
+ -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
++-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
+ -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
++-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
++-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1600"
+ -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+--- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
++-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+ -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+ -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+ -- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+diff -ur atari800core_v1_20140121_mcc216/pokey_mixer.vhdl atari800core_v1_20140312_mist/pokey_mixer.vhdl
+--- atari800core_v1_20140121_mcc216/pokey_mixer.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ atari800core_v1_20140312_mist/pokey_mixer.vhdl	2014-03-09 17:25:18.000000000 +0000
+@@ -22,6 +22,9 @@
+ 	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+ 	
+ 	GTIA_SOUND : IN STD_LOGIC;
++
++	COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
++	COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+ 	
+ 	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+ );
+@@ -30,6 +33,7 @@
+ ARCHITECTURE vhdl OF pokey_mixer IS
+ 	signal volume_reg : std_logic_vector(15 downto 0);
+ 	signal volume_next : std_logic_vector(15 downto 0);
++	signal volume_next_real : std_logic_vector(15 downto 0);	
+ 	
+ 	signal volume_sum : std_logic_vector(5 downto 0);
+ 	
+@@ -38,13 +42,13 @@
+ 	signal channel_2_en : std_logic_vector(3 downto 0);
+ 	signal channel_3_en : std_logic_vector(3 downto 0);
+ 	
+-	signal gtia_en : std_logic_vector(5 downto 0);
++	signal gtia_en : std_logic_vector(15 downto 0);
+ BEGIN
+ 	-- register
+ 	process(clk)
+ 	begin
+ 		if (clk'event and clk='1') then
+-			volume_reg <= volume_next;
++			volume_reg <= volume_next_real;
+ 		end if;
+ 	end process;
+ 	
+@@ -73,9 +77,7 @@
+ --		end if;
+ 	end process;
+ 	
+-	gtia_en <= "0000"&gtia_sound&gtia_sound;  -- only room for 3 more! TODO, regenerate...
+-	
+-	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
++	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_en)
+ 	begin
+ 		volume_sum <= 
+ 			std_logic_vector
+@@ -89,12 +91,13 @@
+ 						unsigned('0'&CHANNEL_2_en) + 
+ 						unsigned('0'&CHANNEL_3_en)
+ 					))
+-					+ 
+-					unsigned(gtia_en)
+ 			);
+ 	end process;
+ 	
+-	process (volume_sum)
++	gtia_en(15 downto 13) <= (others=>'0');
++	gtia_en(12) <= gtia_sound;
++	gtia_en(11 downto 0) <= (others=>'0');
++ 	process (volume_sum, volume_next, gtia_en, covOX_CHANNEL_0,covOX_CHANNEL_1)
+ 	begin
+ 		case volume_sum is 
+ 			when "000000" =>
+@@ -223,9 +226,24 @@
+ 				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+ 		end case;
+ 		
++--		volume_next_real <= std_LOGIC_vector(
++--			(unsigned('0'&volume_next(15 downto 1)) 
++--			+ unsigned(gtia_en)) 
++--			+ (unsigned("00"&covox_CHANNEL_0) 
++--			+ unsigned("00"&covox_CHANNEL_1)));
++		
++		--volume_next_real <= '0'&volume_next(15 downto 1);
++		
++		volume_next_real <= std_LOGIC_vector(
++			(unsigned("00"&volume_next(15 downto 2)) 
++			+ unsigned(gtia_en)) 		
++			+ (unsigned("000"&covox_CHANNEL_0&"00000") 
++			+ unsigned("000"&covox_CHANNEL_1&"00000")));
++		
+ 	end process;
+ 			
+ 	-- output
++	-- TODO
+ 	volume_out <= volume_reg;
+ 		
+ END vhdl;
+\ No newline at end of file
+Only in atari800core_v1_20140312_mist/: pokey_mixer.vhdl.bak
+Only in atari800core_v1_20140312_mist/: rom16.cmp
+Only in atari800core_v1_20140312_mist/: rom16.qip
+Only in atari800core_v1_20140312_mist/: rom16.vhd
+diff -ur atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl atari800core_v1_20140312_mist/sdram_statemachine.vhdl
+--- atari800core_v1_20140121_mcc216/sdram_statemachine.vhdl	2014-01-22 21:37:54.000000000 +0000
++++ atari800core_v1_20140312_mist/sdram_statemachine.vhdl	2014-02-16 20:26:57.000000000 +0000
+@@ -28,13 +28,13 @@
+ 	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+ 	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+ 	WRITE_EN : in std_logic;
+-	REQUEST : in std_logic; -- Toggle this to issue a new request
++	REQUEST : in std_logic; -- set true to request
+ 	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+ 	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+ 	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+ 	REFRESH : in std_logic;
+ 
+-	REPLY : out std_logic; -- This matches the request once complete
++	COMPLETE : out std_logic;
+ 	DATA_OUT : out std_logic_vector(31 downto 0);
+ 
+ 	-- sdram itself
+@@ -184,6 +184,9 @@
+ 	signal udqm_reg : std_logic;
+ 	signal cke_reg : std_logic;
+ 	
++	signal sdram_request_reg : std_logic;
++	signal sdram_request_next : std_logic;
++	
+ BEGIN
+ 	-- register
+ 	process(CLK_SDRAM,reset_n)
+@@ -247,6 +250,8 @@
+ 			
+ 			data_out_sreg <= (others=>'0');
+ 			reply_sreg <= '0';
++			
++			sdram_request_reg <= '0';
+ 		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+ 			data_in_sreg <= data_in_snext;
+ 			address_in_sreg <= address_in_snext;
+@@ -258,11 +263,13 @@
+ 			
+ 			data_out_sreg <= data_out_snext;
+ 			reply_sreg <= reply_snext;
++			
++			sdram_request_reg <= sdram_request_next;
+ 		end if;
+ 	end process;
+ 
+ 	-- Inputs - NB, clocked at a smaller multiple
+-	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, request, byte_access, word_access, longword_access, refresh)
++	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, sdram_request_next, byte_access, word_access, longword_access, refresh)
+ 	begin
+ 		data_in_snext <= data_in_sreg;
+ 		address_in_snext <= address_in_sreg;
+@@ -275,12 +282,12 @@
+ 	
+ 		-- only snap inputs on new request
+ 		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+-		if ((request xor request_sreg) = '1') then
++		if ((sdram_request_next xor request_sreg) = '1') then
+ 			data_in_snext <= data_in;
+ 			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+ 			read_en_snext <= read_en;
+ 			write_en_snext <= write_en;
+-			request_snext <= request;
++			request_snext <= sdram_request_next;
+ 			
+ 			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+ 			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+@@ -509,7 +516,11 @@
+ 	data_out_snext <= data_out_reg;
+ 	
+ 	-- outputs to rest of system
+-	REPLY <= reply_sreg;
++	--REPLY <= reply_sreg;
+ 	DATA_OUT <= DATA_OUT_sreg;
+-		
++
++	-- a little sdram glue - move to sdram wrapper?
++	COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
++	sdram_request_next <= sdram_request_reg xor request;
++	
+ END vhdl;
+Only in atari800core_v1_20140312_mist/: stp1.stp
+Only in atari800core_v1_20140312_mist/: user_io.v
+Only in atari800core_v1_20140312_mist/: user_io.v.bak
+diff -ur atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif atari800core_v1_20140312_mist/zpu/HelloTinyROM_ROM.mif
+--- atari800core_v1_20140121_mcc216/zpu/HelloTinyROM_ROM.mif	2014-01-31 21:09:40.000000000 +0000
++++ atari800core_v1_20140312_mist/zpu/HelloTinyROM_ROM.mif	2014-03-09 18:12:34.000000000 +0000
+@@ -169,8 +169,8 @@
+ 009e : 00000000;
+ 009f : 00000000;
+ 00a0 : 71fc0608;
+-00a1 : 0b0b80f5;
+-00a2 : d0738306;
++00a1 : 0b0b80ef;
++00a2 : 98738306;
+ 00a3 : 10100508;
+ 00a4 : 060b0b0b;
+ 00a5 : 88a20400;
+@@ -216,7 +216,7 @@
+ 00cd : 00000000;
+ 00ce : 00000000;
+ 00cf : 00000000;
+-00d0 : 810b80fb;
++00d0 : 810b80f5;
+ 00d1 : ac0c5104;
+ 00d2 : 00000000;
+ 00d3 : 00000000;
+@@ -289,8 +289,8 @@
+ 0116 : 83e08008;
+ 0117 : 83e08408;
+ 0118 : 83e08808;
+-0119 : 757580ef;
+-011a : fe2d5050;
++0119 : 757580e9;
++011a : c62d5050;
+ 011b : 83e08008;
+ 011c : 5683e088;
+ 011d : 0c83e084;
+@@ -299,7 +299,7 @@
+ 0120 : e0800883;
+ 0121 : e0840883;
+ 0122 : e0880875;
+-0123 : 7580ee92;
++0123 : 7580e7da;
+ 0124 : 2d505083;
+ 0125 : e0800856;
+ 0126 : 83e0880c;
+@@ -308,31 +308,31 @@
+ 0129 : 51040000;
+ 012a : 800489aa;
+ 012b : 0489aa0b;
+-012c : 80c1a404;
++012c : 80c1eb04;
+ 012d : fd3d0d75;
+ 012e : b9297681;
+-012f : 2a0580fd;
+-0130 : fc085473;
++012f : 2a0580f8;
++0130 : 80085473;
+ 0131 : 0c853d0d;
+ 0132 : 04803d0d;
+ 0133 : 81ff5180;
+-0134 : 0b83e0c8;
++0134 : 0b83e0cc;
+ 0135 : 1234ff11;
+ 0136 : 5170f438;
+ 0137 : 823d0d04;
+ 0138 : fa3d0d78;
+-0139 : 0b0b80f6;
+-013a : a85383e2;
+-013b : f4525680;
+-013c : cdd13f80;
++0139 : 0b0b80ef;
++013a : ec5383e2;
++013b : f8525680;
++013c : ce9b3f80;
+ 013d : 5383e080;
+ 013e : 08732e8a;
+ 013f : 387283e0;
+ 0140 : 800c883d;
+ 0141 : 0d0483e0;
+ 0142 : 945283e2;
+-0143 : f45180ce;
+-0144 : c53f83e0;
++0143 : f85180cf;
++0144 : 8f3f83e0;
+ 0145 : 800880d5;
+ 0146 : 3883e09d;
+ 0147 : 33537280;
+@@ -360,3685 +360,3494 @@
+ 015d : 3d0d0483;
+ 015e : e0940883;
+ 015f : e0800c88;
+-0160 : 3d0d04fd;
+-0161 : 3d0d800b;
+-0162 : 80fdec08;
+-0163 : 5353ff72;
+-0164 : 0c80fdf0;
+-0165 : 0873710c;
+-0166 : 5284d851;
+-0167 : fe963f88;
+-0168 : 800a5380;
+-0169 : 73708105;
+-016a : 553472a8;
+-016b : 800a2e09;
+-016c : 8106f038;
+-016d : 80fdec08;
+-016e : 5485aad5;
+-016f : aad5740c;
+-0170 : 80fdf008;
+-0171 : 5285aad5;
+-0172 : aad5720c;
+-0173 : 82800a53;
+-0174 : 80737084;
+-0175 : 05550c72;
+-0176 : 81800a2e;
+-0177 : 098106f0;
+-0178 : 3880740c;
+-0179 : ff720c84;
+-017a : d851fdc8;
+-017b : 3f853d0d;
+-017c : 04fd3d0d;
+-017d : 800b80fd;
+-017e : ec085353;
+-017f : ff87c3e1;
+-0180 : f0720c80;
+-0181 : fdf00873;
+-0182 : 710c528c;
+-0183 : 9ac051fd;
+-0184 : a33f8880;
+-0185 : 0a538073;
+-0186 : 70810555;
+-0187 : 34728184;
+-0188 : 80802e09;
+-0189 : 8106ef38;
+-018a : 80fdec08;
+-018b : 5485aad5;
+-018c : aad5740c;
+-018d : 80fdf008;
+-018e : 5285aad5;
+-018f : aad5720c;
+-0190 : 82800a53;
+-0191 : 80737084;
+-0192 : 05550c72;
+-0193 : 84848080;
+-0194 : 2e098106;
+-0195 : ef388074;
+-0196 : 0cff87c3;
+-0197 : e1f0720c;
+-0198 : 8c9ac051;
+-0199 : fcce3f85;
+-019a : 3d0d04ff;
+-019b : 3d0d80fe;
+-019c : 80087008;
+-019d : 52527381;
+-019e : 2e8b3870;
+-019f : 81800772;
+-01a0 : 0c833d0d;
+-01a1 : 0470feff;
+-01a2 : 06720c83;
+-01a3 : 3d0d04ff;
+-01a4 : 3d0d80fe;
+-01a5 : 80087008;
+-01a6 : 5252738b;
+-01a7 : 3870ffbf;
+-01a8 : 06720c83;
+-01a9 : 3d0d0470;
+-01aa : 80c00772;
+-01ab : 0c833d0d;
+-01ac : 04ff0b83;
+-01ad : e0b00c80;
+-01ae : cee33f80;
+-01af : d1e73f83;
+-01b0 : e08008f3;
+-01b1 : 3880d4ac;
+-01b2 : 3f800b83;
+-01b3 : e0800c04;
+-01b4 : 803d0d70;
+-01b5 : 83e0800c;
+-01b6 : 823d0d04;
+-01b7 : ff3d0d73;
+-01b8 : 70335351;
+-01b9 : 81113371;
+-01ba : 34718112;
+-01bb : 34833d0d;
+-01bc : 04fb3d0d;
+-01bd : 77028405;
+-01be : a2052256;
+-01bf : 56807071;
+-01c0 : 55555271;
+-01c1 : 7527ac38;
+-01c2 : 75137033;
+-01c3 : 70147081;
+-01c4 : ff065551;
+-01c5 : 51517174;
+-01c6 : 27893881;
+-01c7 : 127081ff;
+-01c8 : 06535171;
+-01c9 : 81147083;
+-01ca : ffff0655;
+-01cb : 52547473;
+-01cc : 26d63871;
+-01cd : 83e0800c;
+-01ce : 873d0d04;
+-01cf : f83d0d7a;
+-01d0 : 57800b8a;
+-01d1 : 3d238070;
+-01d2 : 7183e2e4;
+-01d3 : 0c0b0b80;
+-01d4 : f6ac5357;
+-01d5 : 5880dabf;
+-01d6 : 3f765180;
+-01d7 : dab93f0b;
+-01d8 : 0b80faf4;
+-01d9 : 5180daaf;
+-01da : 3f765180;
+-01db : c2f13f83;
+-01dc : e0800878;
+-01dd : 2e8f380b;
+-01de : 0b80f6b8;
+-01df : 5180da97;
+-01e0 : 3f8a3d0d;
+-01e1 : 040b0b80;
+-01e2 : f6c05180;
+-01e3 : da893f75;
+-01e4 : 17703355;
+-01e5 : 5573802e;
+-01e6 : 80fd3873;
+-01e7 : ae2e8638;
+-01e8 : 811656eb;
+-01e9 : 39800b81;
+-01ea : 16335556;
+-01eb : 7380d82e;
+-01ec : 09810683;
+-01ed : 38815673;
+-01ee : 80f83270;
+-01ef : 30708025;
+-01f0 : 78075151;
+-01f1 : 5473802e;
+-01f2 : 80cd3880;
+-01f3 : 0b821633;
+-01f4 : 55567380;
+-01f5 : c62e0981;
+-01f6 : 06833881;
+-01f7 : 567380e6;
+-01f8 : 32703070;
+-01f9 : 80257807;
+-01fa : 51515473;
+-01fb : 802ea838;
+-01fc : 800b8316;
+-01fd : 33555673;
+-01fe : 80c42e09;
+-01ff : 81068338;
+-0200 : 81567380;
+-0201 : e4327030;
+-0202 : 70802578;
+-0203 : 07515154;
+-0204 : 73802e83;
+-0205 : 38815880;
+-0206 : 0b8a3d23;
+-0207 : 8a3dfc05;
+-0208 : 53905283;
+-0209 : e2e85180;
+-020a : c2f53f89;
+-020b : 3d225574;
+-020c : 902e8e38;
+-020d : 0b0b80f6;
+-020e : c45180d8;
+-020f : da3ffec1;
+-0210 : 3983e2e8;
+-0211 : 51fd953f;
+-0212 : 83e2ea51;
+-0213 : fd8e3f83;
+-0214 : e2ec51fd;
+-0215 : 873f800b;
+-0216 : 83e3880c;
+-0217 : 77812e81;
+-0218 : 8c3883e2;
+-0219 : e83383e2;
+-021a : e9337188;
+-021b : 2b075556;
+-021c : 7383ffff;
+-021d : 2e82ce38;
+-021e : 7385962e;
+-021f : 8e380b0b;
+-0220 : 80f6dc51;
+-0221 : 80d8903f;
+-0222 : fdf7390b;
+-0223 : 0b80f6f0;
+-0224 : 5180d883;
+-0225 : 3f7483e3;
+-0226 : 900c83e2;
+-0227 : ec3383e2;
+-0228 : ed337188;
+-0229 : 2b075555;
+-022a : 7381802e;
+-022b : 81d33873;
+-022c : 82802e84;
+-022d : 81387381;
+-022e : ff2681b8;
+-022f : 380b0b80;
+-0230 : f6f85180;
+-0231 : d7d13f83;
+-0232 : e2ea3383;
+-0233 : e2eb3371;
+-0234 : 882b0752;
+-0235 : 5680d8ce;
+-0236 : 3f0b0b80;
+-0237 : f6fc5180;
+-0238 : d7b53f81;
+-0239 : 0b83e2e4;
+-023a : 0c8a3d0d;
+-023b : 040b0b80;
+-023c : f7805180;
+-023d : d7a13f80;
+-023e : 0b83e390;
+-023f : 0c820b83;
+-0240 : e2e834ff;
+-0241 : 960b83e2;
+-0242 : e9347651;
+-0243 : f7d23f83;
+-0244 : e0800854;
+-0245 : 800b83e0;
+-0246 : 800824a9;
+-0247 : 3873842c;
+-0248 : 7083ffff;
+-0249 : 0670882a;
+-024a : 57515474;
+-024b : 83e2ea34;
+-024c : 7383e2eb;
+-024d : 34800b83;
+-024e : e2ec34ff;
+-024f : 800b83e2;
+-0250 : ed34fed6;
+-0251 : 3983e080;
+-0252 : 088f0570;
+-0253 : 842c7083;
+-0254 : ffff0670;
+-0255 : 882a5851;
+-0256 : 51547483;
+-0257 : e2ea3473;
+-0258 : 83e2eb34;
+-0259 : 800b83e2;
+-025a : ec34ff80;
+-025b : 0b83e2ed;
+-025c : 34fea739;
+-025d : 0b0b80f7;
+-025e : 885180d6;
+-025f : 9a3ffc81;
+-0260 : 3983e2ea;
+-0261 : 3383e2eb;
+-0262 : 3371882b;
+-0263 : 075558ad;
+-0264 : 80742781;
+-0265 : f2380b0b;
+-0266 : 80f79851;
+-0267 : 80d5f83f;
+-0268 : 83e2ea33;
+-0269 : 83e2eb33;
+-026a : 71882b07;
+-026b : 525680d6;
+-026c : f53f0b0b;
+-026d : 80f6fc51;
+-026e : 80d5dc3f;
+-026f : 810b83e2;
+-0270 : e40cfea5;
+-0271 : 390b0b80;
+-0272 : f79c5180;
+-0273 : d5c93ffe;
+-0274 : 800b83e3;
+-0275 : 900c810b;
+-0276 : 83e3880c;
+-0277 : ff0b83e2;
+-0278 : e834ff0b;
+-0279 : 83e2e934;
+-027a : 7651f5f4;
+-027b : 3f83e080;
+-027c : 0883e394;
+-027d : 0c83e080;
+-027e : 0854800b;
+-027f : 83e08008;
+-0280 : 2480d338;
+-0281 : 73842c70;
+-0282 : 83ffff06;
+-0283 : 70882a57;
+-0284 : 51547483;
+-0285 : e2ea3473;
+-0286 : 83e2eb34;
+-0287 : 800b83e2;
+-0288 : ec34ff80;
+-0289 : 0b83e2ed;
+-028a : 34805574;
+-028b : 17547333;
+-028c : 83e2d816;
+-028d : 34811555;
+-028e : 748c2efc;
+-028f : dd387417;
+-0290 : 54733383;
+-0291 : e2d81634;
+-0292 : 81155574;
+-0293 : 8c2e0981;
+-0294 : 06d938fc;
+-0295 : c53983e0;
+-0296 : 80088f05;
+-0297 : 70842c70;
+-0298 : 83ffff06;
+-0299 : 70882a58;
+-029a : 51515474;
+-029b : 83e2ea34;
+-029c : 7383e2eb;
+-029d : 34800b83;
+-029e : e2ec34ff;
+-029f : 800b83e2;
+-02a0 : ed348055;
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+-02a2 : 0b80f7a4;
+-02a3 : 5180d487;
+-02a4 : 3f83e2ea;
+-02a5 : 3383e2eb;
+-02a6 : 3371882b;
+-02a7 : 07525680;
+-02a8 : d5843f0b;
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+-02aa : 5180d3eb;
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+-02b5 : 80f6fc51;
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+-02b9 : 39f73d0d;
+-02ba : 7b5a8c9a;
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+-02bc : 3f805780;
+-02bd : d0f83f76;
+-02be : 54800b86;
+-02bf : b8c01534;
+-02c0 : 81145473;
+-02c1 : 87c02e09;
+-02c2 : 8106ee38;
+-02c3 : 0b0b80f6;
+-02c4 : a85283e2;
+-02c5 : f45180c1;
+-02c6 : aa3f83e0;
+-02c7 : 800883db;
+-02c8 : 38807083;
+-02c9 : e3a80855;
+-02ca : 59599473;
+-02cb : 258638ec;
+-02cc : 13fe0658;
+-02cd : 80732482;
+-02ce : ff3883e0;
+-02cf : 945283e2;
+-02d0 : f45180c2;
+-02d1 : 913f83e0;
+-02d2 : 800880db;
+-02d3 : 3883e09d;
+-02d4 : 33537280;
+-02d5 : 2e80d038;
+-02d6 : 83e09c33;
+-02d7 : 70822a70;
+-02d8 : 81065154;
+-02d9 : 5472d338;
+-02da : 73812a81;
+-02db : 065574ca;
+-02dc : 3873842a;
+-02dd : 70810651;
+-02de : 537282a3;
+-02df : 3883e3a8;
+-02e0 : 08772e81;
+-02e1 : de38ff18;
+-02e2 : 58807824;
+-02e3 : 82b23881;
+-02e4 : 175783e0;
+-02e5 : 945283e2;
+-02e6 : f45180c1;
+-02e7 : b93f83e0;
+-02e8 : 8008802e;
+-02e9 : ffa7380b;
+-02ea : 0b80fb80;
+-02eb : 5180d1e7;
+-02ec : 3f955180;
+-02ed : cfcb3f80;
+-02ee : 0b83e0b4;
+-02ef : 0c7951f6;
+-02f0 : fb3f80fd;
+-02f1 : 80087033;
+-02f2 : 7081ff06;
+-02f3 : 70812a81;
+-02f4 : 32708106;
+-02f5 : 51525651;
+-02f6 : 537280eb;
+-02f7 : 38738132;
+-02f8 : 70810651;
+-02f9 : 537282e1;
+-02fa : 3873832a;
+-02fb : 81327081;
+-02fc : 06515372;
+-02fd : 82c23873;
+-02fe : 822a8132;
+-02ff : 70810651;
+-0300 : 537282a3;
+-0301 : 3880fcf8;
+-0302 : 08703370;
+-0303 : 81ff0651;
+-0304 : 54547280;
+-0305 : 2e81f038;
+-0306 : 80ced33f;
+-0307 : 80fd8408;
+-0308 : 80fd9408;
+-0309 : 54547333;
+-030a : 733480fd;
++0160 : 3d0d04fe;
++0161 : 3d0d7453;
++0162 : 7283e0b4;
++0163 : 082e9838;
++0164 : 80f7d808;
++0165 : 73710c52;
++0166 : 71087081;
++0167 : 06515170;
++0168 : f7387283;
++0169 : e0b40c84;
++016a : 3d0d04fd;
++016b : 3d0d800b;
++016c : 80f7f008;
++016d : 5353ff72;
++016e : 0c80f7f4;
++016f : 0873710c;
++0170 : 5284d851;
++0171 : fdee3f88;
++0172 : 800a5380;
++0173 : 73708105;
++0174 : 553472a8;
++0175 : 800a2e09;
++0176 : 8106f038;
++0177 : 80f7f008;
++0178 : 5485aad5;
++0179 : aad5740c;
++017a : 80f7f408;
++017b : 5285aad5;
++017c : aad5720c;
++017d : 82800a53;
++017e : 80737084;
++017f : 05550c72;
++0180 : 81800a2e;
++0181 : 098106f0;
++0182 : 3880740c;
++0183 : ff720c84;
++0184 : d851fda0;
++0185 : 3f853d0d;
++0186 : 04fd3d0d;
++0187 : 800b80f7;
++0188 : f0085353;
++0189 : ff87c3e1;
++018a : f0720c80;
++018b : f7f40873;
++018c : 710c528c;
++018d : 9ac051fc;
++018e : fb3f8880;
++018f : 0a538073;
++0190 : 70810555;
++0191 : 34728184;
++0192 : 80802e09;
++0193 : 8106ef38;
++0194 : 80f7f008;
++0195 : 5485aad5;
++0196 : aad5740c;
++0197 : 80f7f408;
++0198 : 5285aad5;
++0199 : aad5720c;
++019a : 82800a53;
++019b : 80737084;
++019c : 05550c72;
++019d : 84848080;
++019e : 2e098106;
++019f : ef388074;
++01a0 : 0cff87c3;
++01a1 : e1f0720c;
++01a2 : 8c9ac051;
++01a3 : fca63f85;
++01a4 : 3d0d04ff;
++01a5 : 3d0d80f8;
++01a6 : 84087008;
++01a7 : 52527381;
++01a8 : 2e8b3870;
++01a9 : 81800772;
++01aa : 0c833d0d;
++01ab : 0470feff;
++01ac : 06720c83;
++01ad : 3d0d04ff;
++01ae : 3d0d80f8;
++01af : 84087008;
++01b0 : 5252738b;
++01b1 : 3870ffbf;
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++0c91 : 51fef53f;
++0c92 : 800b83e3;
++0c93 : f00c843d;
++0c94 : 0d04fb3d;
++0c95 : 0d777956;
++0c96 : 56fcb73f;
++0c97 : 80752580;
++0c98 : fb387570;
++0c99 : 81055733;
++0c9a : 705254fc;
++0c9b : e63f83e3;
++0c9c : f8085383;
++0c9d : e3ec0852;
++0c9e : 83e08008;
++0c9f : 81ff0651;
++0ca0 : fbdf3f73;
++0ca1 : 842a51fd;
++0ca2 : a03f83e3;
++0ca3 : f8085383;
++0ca4 : e3ec0810;
++0ca5 : 94055283;
++0ca6 : e0800881;
++0ca7 : ff0651fb;
++0ca8 : c03f738f;
++0ca9 : 0651fd81;
++0caa : 3f83e3f8;
++0cab : 085383e3;
++0cac : ec081095;
++0cad : 055283e0;
++0cae : 800881ff;
++0caf : 0651fba1;
++0cb0 : 3f83e3ec;
++0cb1 : 08810583;
++0cb2 : e3ec0c83;
++0cb3 : e3ec088a;
++0cb4 : 2e9138ff;
++0cb5 : 15557480;
++0cb6 : 24ff8738;
++0cb7 : fbb43f87;
++0cb8 : 3d0d04fb;
++0cb9 : ad3fff15;
++0cba : 55ec39fb;
++0cbb : 3d0d7779;
++0cbc : 83e3ec08;
++0cbd : 83fffe06;
++0cbe : 83e3ec0c;
++0cbf : 56568075;
++0cc0 : 2580e538;
++0cc1 : 75708105;
++0cc2 : 57337084;
++0cc3 : 2a5254fc;
++0cc4 : 983f83e3;
++0cc5 : f8085383;
++0cc6 : e3ec0852;
++0cc7 : 83e3ec08;
++0cc8 : 810583e3;
++0cc9 : ec0c83e0;
++0cca : 800881ff;
++0ccb : 0651fab1;
++0ccc : 3f738f06;
++0ccd : 51fbf23f;
++0cce : 83e3f808;
++0ccf : 5383e3ec;
++0cd0 : 085283e3;
++0cd1 : ec088105;
++0cd2 : 83e3ec0c;
++0cd3 : 83e08008;
++0cd4 : 81ff0651;
++0cd5 : fa8b3f83;
++0cd6 : e3ec08a8;
++0cd7 : 2e8e38ff;
++0cd8 : 15557480;
++0cd9 : 24ff9d38;
++0cda : 873d0d04;
++0cdb : faa43fff;
++0cdc : 1555ef39;
++0cdd : 83e08c08;
++0cde : 0283e08c;
++0cdf : 0cfd3d0d;
++0ce0 : 805383e0;
++0ce1 : 8c088c05;
++0ce2 : 085283e0;
++0ce3 : 8c088805;
++0ce4 : 085183d4;
++0ce5 : 3f83e080;
++0ce6 : 087083e0;
++0ce7 : 800c5485;
++0ce8 : 3d0d83e0;
++0ce9 : 8c0c0483;
++0cea : e08c0802;
++0ceb : 83e08c0c;
++0cec : fd3d0d81;
++0ced : 5383e08c;
++0cee : 088c0508;
++0cef : 5283e08c;
++0cf0 : 08880508;
++0cf1 : 5183a13f;
++0cf2 : 83e08008;
++0cf3 : 7083e080;
++0cf4 : 0c54853d;
++0cf5 : 0d83e08c;
++0cf6 : 0c0483e0;
++0cf7 : 8c080283;
++0cf8 : e08c0cf9;
++0cf9 : 3d0d800b;
++0cfa : 83e08c08;
++0cfb : fc050c83;
++0cfc : e08c0888;
++0cfd : 05088025;
++0cfe : b93883e0;
++0cff : 8c088805;
++0d00 : 083083e0;
++0d01 : 8c088805;
++0d02 : 0c800b83;
++0d03 : e08c08f4;
++0d04 : 050c83e0;
++0d05 : 8c08fc05;
++0d06 : 088a3881;
++0d07 : 0b83e08c;
++0d08 : 08f4050c;
++0d09 : 83e08c08;
++0d0a : f4050883;
++0d0b : e08c08fc;
++0d0c : 050c83e0;
++0d0d : 8c088c05;
++0d0e : 088025b9;
++0d0f : 3883e08c;
++0d10 : 088c0508;
++0d11 : 3083e08c;
++0d12 : 088c050c;
++0d13 : 800b83e0;
++0d14 : 8c08f005;
++0d15 : 0c83e08c;
++0d16 : 08fc0508;
++0d17 : 8a38810b;
++0d18 : 83e08c08;
++0d19 : f0050c83;
++0d1a : e08c08f0;
++0d1b : 050883e0;
++0d1c : 8c08fc05;
++0d1d : 0c805383;
++0d1e : e08c088c;
++0d1f : 05085283;
++0d20 : e08c0888;
++0d21 : 05085181;
++0d22 : df3f83e0;
++0d23 : 80087083;
++0d24 : e08c08f8;
++0d25 : 050c5483;
++0d26 : e08c08fc;
++0d27 : 0508802e;
++0d28 : 903883e0;
++0d29 : 8c08f805;
++0d2a : 083083e0;
++0d2b : 8c08f805;
++0d2c : 0c83e08c;
++0d2d : 08f80508;
++0d2e : 7083e080;
++0d2f : 0c54893d;
++0d30 : 0d83e08c;
++0d31 : 0c0483e0;
++0d32 : 8c080283;
++0d33 : e08c0cfb;
++0d34 : 3d0d800b;
++0d35 : 83e08c08;
++0d36 : fc050c83;
++0d37 : e08c0888;
++0d38 : 05088025;
++0d39 : 993883e0;
++0d3a : 8c088805;
++0d3b : 083083e0;
++0d3c : 8c088805;
++0d3d : 0c810b83;
++0d3e : e08c08fc;
++0d3f : 050c83e0;
++0d40 : 8c088c05;
++0d41 : 08802590;
++0d42 : 3883e08c;
++0d43 : 088c0508;
++0d44 : 3083e08c;
++0d45 : 088c050c;
++0d46 : 815383e0;
++0d47 : 8c088c05;
++0d48 : 085283e0;
++0d49 : 8c088805;
++0d4a : 0851bd3f;
++0d4b : 83e08008;
++0d4c : 7083e08c;
++0d4d : 08f8050c;
++0d4e : 5483e08c;
++0d4f : 08fc0508;
++0d50 : 802e9038;
++0d51 : 83e08c08;
++0d52 : f8050830;
++0d53 : 83e08c08;
++0d54 : f8050c83;
++0d55 : e08c08f8;
++0d56 : 05087083;
++0d57 : e0800c54;
++0d58 : 873d0d83;
++0d59 : e08c0c04;
++0d5a : 83e08c08;
++0d5b : 0283e08c;
++0d5c : 0cfd3d0d;
++0d5d : 810b83e0;
++0d5e : 8c08fc05;
++0d5f : 0c800b83;
++0d60 : e08c08f8;
++0d61 : 050c83e0;
++0d62 : 8c088c05;
++0d63 : 0883e08c;
++0d64 : 08880508;
++0d65 : 27b93883;
++0d66 : e08c08fc;
++0d67 : 0508802e;
++0d68 : ae38800b;
++0d69 : 83e08c08;
++0d6a : 8c050824;
++0d6b : a23883e0;
++0d6c : 8c088c05;
++0d6d : 081083e0;
++0d6e : 8c088c05;
++0d6f : 0c83e08c;
++0d70 : 08fc0508;
++0d71 : 1083e08c;
++0d72 : 08fc050c;
++0d73 : ffb83983;
++0d74 : e08c08fc;
++0d75 : 0508802e;
++0d76 : 80e13883;
++0d77 : e08c088c;
++0d78 : 050883e0;
++0d79 : 8c088805;
++0d7a : 0826ad38;
++0d7b : 83e08c08;
++0d7c : 88050883;
++0d7d : e08c088c;
++0d7e : 05083183;
++0d7f : e08c0888;
++0d80 : 050c83e0;
++0d81 : 8c08f805;
++0d82 : 0883e08c;
++0d83 : 08fc0508;
++0d84 : 0783e08c;
++0d85 : 08f8050c;
++0d86 : 83e08c08;
++0d87 : fc050881;
++0d88 : 2a83e08c;
++0d89 : 08fc050c;
++0d8a : 83e08c08;
++0d8b : 8c050881;
++0d8c : 2a83e08c;
++0d8d : 088c050c;
++0d8e : ff953983;
++0d8f : e08c0890;
++0d90 : 0508802e;
++0d91 : 933883e0;
++0d92 : 8c088805;
++0d93 : 087083e0;
++0d94 : 8c08f405;
++0d95 : 0c519139;
++0d96 : 83e08c08;
++0d97 : f8050870;
++0d98 : 83e08c08;
++0d99 : f4050c51;
++0d9a : 83e08c08;
++0d9b : f4050883;
++0d9c : e0800c85;
++0d9d : 3d0d83e0;
++0d9e : 8c0c0483;
++0d9f : e08c0802;
++0da0 : 83e08c0c;
++0da1 : ff3d0d80;
++0da2 : 0b83e08c;
++0da3 : 08fc050c;
++0da4 : 83e08c08;
++0da5 : 88050881;
++0da6 : 06ff1170;
++0da7 : 097083e0;
++0da8 : 8c088c05;
++0da9 : 080683e0;
++0daa : 8c08fc05;
++0dab : 081183e0;
++0dac : 8c08fc05;
++0dad : 0c83e08c;
++0dae : 08880508;
++0daf : 812a83e0;
++0db0 : 8c088805;
++0db1 : 0c83e08c;
++0db2 : 088c0508;
++0db3 : 1083e08c;
++0db4 : 088c050c;
++0db5 : 51515151;
++0db6 : 83e08c08;
++0db7 : 88050880;
++0db8 : 2e8438ff;
++0db9 : ab3983e0;
++0dba : 8c08fc05;
++0dbb : 087083e0;
++0dbc : 800c5183;
++0dbd : 3d0d83e0;
++0dbe : 8c0c04fc;
++0dbf : 3d0d7670;
++0dc0 : 797b5555;
++0dc1 : 55558f72;
++0dc2 : 278c3872;
++0dc3 : 75078306;
++0dc4 : 5170802e;
++0dc5 : a938ff12;
++0dc6 : 5271ff2e;
++0dc7 : 98387270;
++0dc8 : 81055433;
++0dc9 : 74708105;
++0dca : 5634ff12;
++0dcb : 5271ff2e;
++0dcc : 098106ea;
++0dcd : 387483e0;
++0dce : 800c863d;
++0dcf : 0d047451;
++0dd0 : 72708405;
++0dd1 : 54087170;
++0dd2 : 8405530c;
++0dd3 : 72708405;
++0dd4 : 54087170;
++0dd5 : 8405530c;
++0dd6 : 72708405;
++0dd7 : 54087170;
++0dd8 : 8405530c;
++0dd9 : 72708405;
++0dda : 54087170;
++0ddb : 8405530c;
++0ddc : f0125271;
++0ddd : 8f26c938;
++0dde : 83722795;
++0ddf : 38727084;
++0de0 : 05540871;
++0de1 : 70840553;
++0de2 : 0cfc1252;
++0de3 : 718326ed;
++0de4 : 387054ff;
++0de5 : 81390000;
++0de6 : 00ffffff;
++0de7 : ff00ffff;
++0de8 : ffff00ff;
++0de9 : ffffff00;
++0dea : 70707042;
++0deb : 409c0202;
++0dec : 02020202;
++0ded : 02020202;
++0dee : 02020202;
++0def : 02020202;
++0df0 : 02020202;
++0df1 : 02704100;
++0df2 : 9c000000;
++0df3 : 0000175d;
++0df4 : 00001754;
++0df5 : 0000174b;
++0df6 : 00001742;
++0df7 : 00001739;
++0df8 : 00001730;
++0df9 : 00001727;
++0dfa : 000011b0;
++0dfb : 2f000000;
++0dfc : 4f70656e;
++0dfd : 696e673a;
++0dfe : 00000000;
++0dff : 6661696c;
++0e00 : 0a000000;
++0e01 : 6f6b0a00;
++0e02 : 436f756c;
++0e03 : 64206e6f;
++0e04 : 74207265;
++0e05 : 61642068;
++0e06 : 65616465;
++0e07 : 720a0000;
++0e08 : 556e6b6e;
++0e09 : 6f776e20;
++0e0a : 66696c65;
++0e0b : 20747970;
++0e0c : 65000000;
++0e0d : 41545220;
++0e0e : 00000000;
++0e0f : 58442000;
++0e10 : 300a0000;
++0e11 : 58464420;
++0e12 : 00000000;
++0e13 : 42414420;
++0e14 : 73656374;
++0e15 : 6f722073;
++0e16 : 697a6500;
++0e17 : 4d442000;
++0e18 : 58455820;
++0e19 : 00000000;
++0e1a : 53442000;
++0e1b : 44442000;
++0e1c : 44495220;
++0e1d : 00000000;
++0e1e : 6f70656e;
++0e1f : 64697220;
++0e20 : 6661696c;
++0e21 : 65640a00;
++0e22 : 426f6f74;
++0e23 : 696e672e;
++0e24 : 2e2e0000;
++0e25 : 53797374;
++0e26 : 656d2073;
++0e27 : 65747469;
++0e28 : 6e67730a;
++0e29 : 00000000;
++0e2a : 2d2d2d2d;
++0e2b : 2d2d2d2d;
++0e2c : 2d2d2d2d;
++0e2d : 2d2d2d0a;
++0e2e : 00000000;
++0e2f : 4d656d6f;
++0e30 : 72793a00;
++0e31 : 344d4221;
++0e32 : 00000000;
++0e33 : 524f4d20;
++0e34 : 62616e6b;
++0e35 : 3a000000;
++0e36 : 556e6b6e;
++0e37 : 6f776e00;
++0e38 : 53706565;
++0e39 : 643a0000;
++0e3a : 204b487a;
++0e3b : 0a44313a;
++0e3c : 00000000;
++0e3d : 0a44323a;
++0e3e : 00000000;
++0e3f : 0a44333a;
++0e40 : 00000000;
++0e41 : 0a44343a;
++0e42 : 00000000;
++0e43 : 0a526562;
++0e44 : 6f6f7400;
++0e45 : 0a457869;
++0e46 : 74000000;
++0e47 : 34202864;
++0e48 : 65666175;
++0e49 : 6c743a4f;
++0e4a : 53204220;
++0e4b : 2b206869;
++0e4c : 20737065;
++0e4d : 65642900;
++0e4e : 32202864;
++0e4f : 65666175;
++0e50 : 6c743a58;
++0e51 : 4c202b20;
++0e52 : 68692073;
++0e53 : 70656564;
++0e54 : 29000000;
++0e55 : 31202864;
++0e56 : 65666175;
++0e57 : 6c743a58;
++0e58 : 4c290000;
++0e59 : 33202864;
++0e5a : 65666175;
++0e5b : 6c743a55;
++0e5c : 6c74696d;
++0e5d : 6f6e2900;
++0e5e : 31303838;
++0e5f : 4b694220;
++0e60 : 52616d62;
++0e61 : 6f000000;
++0e62 : 3537364b;
++0e63 : 69422052;
++0e64 : 616d626f;
++0e65 : 00000000;
++0e66 : 3537364b;
++0e67 : 69422043;
++0e68 : 6f6d7079;
++0e69 : 2053686f;
++0e6a : 70000000;
++0e6b : 3332304b;
++0e6c : 69422052;
++0e6d : 616d626f;
++0e6e : 00000000;
++0e6f : 3332304b;
++0e70 : 69422043;
++0e71 : 6f6d7079;
++0e72 : 2053686f;
++0e73 : 70000000;
++0e74 : 3132384b;
++0e75 : 69420000;
++0e76 : 36344b69;
++0e77 : 42000000;
++0e78 : 636d643a;
++0e79 : 00000000;
++0e7a : 45525220;
++0e7b : 00000000;
++0e7c : 53504453;
++0e7d : 00000000;
++0e7e : 53504446;
++0e7f : 00000000;
++0e80 : 2873656e;
++0e81 : 643a0000;
++0e82 : 3a63686b;
++0e83 : 3a000000;
++0e84 : 73646361;
++0e85 : 72640a00;
++0e86 : 6469736b;
++0e87 : 5f696e69;
++0e88 : 743a0000;
++0e89 : 6d6f756e;
++0e8a : 743a0000;
++0e8b : 6f70656e;
++0e8c : 6469723a;
++0e8d : 00000000;
++0e8e : 424f4f54;
++0e8f : 2e415452;
++0e90 : 00000000;
++0e91 : 61746172;
++0e92 : 69726f6d;
++0e93 : 2e62696e;
++0e94 : 00000000;
++0e95 : 53746174;
++0e96 : 3a000000;
++0e97 : 3a646f6e;
++0e98 : 650a0000;
++0e99 : 53656374;
++0e9a : 6f723a00;
++0e9b : 20726563;
++0e9c : 65697665;
++0e9d : 3a000000;
++0e9e : 2073656e;
++0e9f : 64696e67;
++0ea0 : 0a000000;
++0ea1 : 64617461;
++0ea2 : 20000000;
++0ea3 : 626f6f74;
++0ea4 : 20000000;
++0ea5 : 6e616d65;
++0ea6 : 20000000;
++0ea7 : 6e756d74;
++0ea8 : 6f627566;
++0ea9 : 66657220;
++0eaa : 00000000;
++0eab : 00000000;
++0eac : 00000000;
++0ead : 72025f07;
++0eae : f807a900;
++0eaf : 8d04038d;
++0eb0 : 4402a907;
++0eb1 : 8d0503a9;
++0eb2 : 708d0a03;
++0eb3 : a9018d0b;
++0eb4 : 03850960;
++0eb5 : 7d8a4820;
++0eb6 : 53e488d0;
++0eb7 : fa68aa8c;
++0eb8 : 8e07ad7d;
++0eb9 : 07ee8e07;
++0eba : 60a9938d;
++0ebb : e202a907;
++0ebc : 8de302a2;
++0ebd : 0220da07;
++0ebe : 954320da;
++0ebf : 07954435;
++0ec0 : 43c9fff0;
++0ec1 : f0caca10;
++0ec2 : ec3006e6;
++0ec3 : 45d002e6;
++0ec4 : 4620da07;
++0ec5 : a2018144;
++0ec6 : b545d543;
++0ec7 : d0edca10;
++0ec8 : f720d207;
++0ec9 : 4c9407a9;
++0eca : 038d0fd2;
++0ecb : 6ce202ad;
++0ecc : 8e07cd7f;
++0ecd : 07d0abee;
++0ece : 0a03d003;
++0ecf : ee0b03ad;
++0ed0 : 7d070d7e;
++0ed1 : 07d08e20;
++0ed2 : d2076ce0;
++0ed3 : 0220da07;
++0ed4 : 8de00220;
++0ed5 : da078de1;
++0ed6 : 022de002;
++0ed7 : c9fff0ed;
++0ed8 : a9008d8e;
++0ed9 : 07f08200;
++0eda : 0001d20f;
++0edb : 0001d400;
++0edc : 0001d401;
++0edd : 0001d409;
++0ede : 0001d010;
++0edf : 0001d301;
++0ee0 : 0001d300;
++0ee1 : 0001d20a;
++0ee2 : 0001d01b;
++0ee3 : 0001d018;
++0ee4 : 0001d017;
++0ee5 : 0001d01a;
++0ee6 : 0001d403;
++0ee7 : 0001d402;
++0ee8 : 0001d40e;
++0ee9 : 0004007c;
++0eea : 00040078;
++0eeb : 00040074;
++0eec : 00040068;
++0eed : 00040060;
++0eee : 0004005c;
++0eef : 00040058;
++0ef0 : 00040054;
++0ef1 : 00040050;
++0ef2 : 0004004c;
++0ef3 : 00040048;
++0ef4 : 00040044;
++0ef5 : 00040040;
++0ef6 : 0004002c;
++0ef7 : 00040028;
++0ef8 : 00040024;
++0ef9 : 00040020;
++0efa : 0004001c;
++0efb : 00040018;
++0efc : 00040014;
++0efd : 00040010;
++0efe : 0004000c;
++0eff : 00040008;
++0f00 : 00040004;
++0f01 : 00040000;
+ END; 
+diff -ur atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl atari800core_v1_20140312_mist/zpu_config_regs.vhdl
+--- atari800core_v1_20140121_mcc216/zpu_config_regs.vhdl	2014-02-02 19:12:56.000000000 +0000
++++ atari800core_v1_20140312_mist/zpu_config_regs.vhdl	2014-03-09 18:09:38.000000000 +0000
+@@ -46,11 +46,16 @@
+ 	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+ 	PAL : OUT STD_LOGIC;
+ 	USE_SDRAM : OUT STD_LOGIC;
+-	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
++	RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);
+ 	VGA : OUT STD_LOGIC;
+ 	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+ 	GPIO_ENABLE : OUT STD_LOGIC;
+-	ROM_SELECT : out stD_logic_vector(1 downto 0);
++	ROM_SELECT : out stD_logic_vector(3 downto 0);
++	
++	-- sector buffer
++	sector : out std_logic_vector(31 downto 0);
++	sector_request : out std_logic;
++	sector_ready : in std_logic;
+ 
+ 	-- system reset/halt
+ 	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+@@ -161,10 +166,10 @@
+ 	
+ 	signal config_6502_next : std_logic_vector(7 downto 0);
+ 	signal config_6502_reg : std_logic_vector(7 downto 0);
+-	signal ram_select_next : std_logic_vector(1 downto 0);
+-	signal ram_select_reg : std_logic_vector(1 downto 0);
+-	signal rom_select_next : std_logic_vector(1 downto 0);
+-	signal rom_select_reg : std_logic_vector(1 downto 0);
++	signal ram_select_next : std_logic_vector(3 downto 0);
++	signal ram_select_reg : std_logic_vector(3 downto 0);
++	signal rom_select_next : std_logic_vector(3 downto 0);
++	signal rom_select_reg : std_logic_vector(3 downto 0);
+ 	signal gpio_enable_next : std_logic;
+ 	signal gpio_enable_reg : std_logic;
+ 	
+@@ -207,6 +212,12 @@
+ 	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+ 	
+ 	signal pokey_data_out : std_logic_vector(7 downto 0);
++	
++	signal sector_next : std_logic_vector(31 downto 0);
++	signal sector_reg : std_logic_vector(31 downto 0);
++	signal sector_request_next : std_logic;
++	signal sector_request_reg : std_logic; -- cleared when ready asserted
++	
+ begin
+ 	-- register
+ 	process(clk,pll_locked)
+@@ -214,8 +225,8 @@
+ 		if (clk'event and clk='1') then	
+ 			if (pll_locked = '0') then
+ 				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+-				rom_select_reg <= "01";
+-				ram_select_reg <= "10";
++				rom_select_reg <= "0010";
++				ram_select_reg <= "0010";
+ 				gpio_enable_reg <= '0';
+ 				pause_reg <= (others=>'0');
+ 				paused_reg <= '0';
+@@ -230,6 +241,9 @@
+ 				reset_n_reg <= '0';			
+ 				reset_zpu_reg <= '1';
+ 				reset_6502_cpu_reg <= '1';											
++				
++				sector_reg <= (others=>'0');
++				sector_request_reg <= '0';
+ 			else
+ 				config_6502_reg <= config_6502_next;
+ 				rom_select_reg <= rom_select_next;
+@@ -248,6 +262,9 @@
+ 				reset_n_reg <= reset_n_next;			
+ 				reset_zpu_reg <= reset_zpu_next;
+ 				reset_6502_cpu_reg <= reset_6502_cpu_next;							
++				
++				sector_reg <= sector_next;
++				sector_request_reg <= sector_request_next;				
+ 			end if;
+ 		end if;
+ 	end process;
+@@ -328,12 +345,15 @@
+ 	--    R(32 bits) 0=DE1
+ 	-- HEX digits
+ 	--    W(16 bits)
++	-- SECTOR
++	--   W(32 bits) - write here initiates a request_reset_zpu
++	--   R: 0=request_active
+ 	
+ 	-- TODO, ROM select, RAM select etc etc
+ 	-- TODO firmware with OSD!
+ 				
+ 	-- Writes to registers
+-	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
++	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
+ 	begin
+ 		config_6502_next <= config_6502_reg;
+ 		rom_select_next <= rom_select_reg;
+@@ -350,6 +370,9 @@
+ 		
+ 		zpu_hex_next <= zpu_hex_reg;
+ 		
++		sector_next <= sector_reg;
++		sector_request_next <= sector_request_reg and not(sector_ready);
++		
+ 		paused_next <= '0';
+ 		if (not(pause_reg = X"00000000")) then
+ 			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+@@ -359,8 +382,8 @@
+ 		if (wr_en = '1' and addr(4) = '0') then
+ 			if(addr_decoded(0) = '1') then
+ 				config_6502_next <= cpu_data_in(7 downto 0);
+-				ram_select_next <= cpu_DATA_IN(9 downto 8);
+-				rom_select_next <= cpu_DATA_IN(13 downto 12);
++				ram_select_next <= cpu_DATA_IN(11 downto 8);
++				rom_select_next <= cpu_DATA_IN(15 downto 12);
+ 				gpio_enable_next <= cpu_DATA_IN(16);
+ 			end if;	
+ 			
+@@ -396,19 +419,24 @@
+ 				zpu_hex_next <= cpu_data_in(15 downto 0);
+ 			end if;	
+ 			
++			if(addr_decoded(11) = '1') then
++				sector_next <= cpu_data_in;
++				sector_request_next <= '1';
++			end if;
++			
+ 		end if;
+ 	end process;
+ 	
+ 	-- Read from registers
+-	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
++	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
+ 	begin
+ 		data_out <= (others=>'0');
+ 
+ 		if (addr(4) = '0') then
+ 			if (addr_decoded(0) = '1') then
+ 				data_out(7 downto 0) <= config_6502_reg;
+-				data_out(9 downto 8) <= ram_select_reg;
+-				data_out(13 downto 12) <= rom_select_reg;
++				data_out(11 downto 8) <= ram_select_reg;
++				data_out(15 downto 12) <= rom_select_reg;
+ 				data_out(16) <= gpio_enable_reg;
+ 			end if;
+ 			
+@@ -451,6 +479,11 @@
+ 			if (addr_decoded(10) = '1') then
+ 				data_out(15 downto 0) <= zpu_hex_reg;
+ 			end if;			
++			
++			if (addr_decoded(11) = '1') then
++				data_out(0) <= sector_request_reg;
++			end if;			
++			
+ 		else
+ 			data_out(7 downto 0) <= pokey_data_out;
+ 		end if;
+@@ -480,6 +513,7 @@
+ 	SDCARD_DAT3 <= spi_chip_select(0);
+ 	
+ 	PAL <= '1'; -- TODO
++	--USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+ 	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+ 	RAM_SELECT <= ram_select_reg;
+ 	VGA <= '1';
+@@ -496,6 +530,9 @@
+ 	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+ 	
+ 	zpu_hex <= zpu_hex_reg;
++	
++	sector <= sector_reg;
++	sector_request <= sector_request_reg;
+ end vhdl;
+ 
+ 
+diff -ur atari800core_v1_20140121_mcc216/zpu_glue.vhdl atari800core_v1_20140312_mist/zpu_glue.vhdl
+--- atari800core_v1_20140121_mcc216/zpu_glue.vhdl	2014-01-20 20:41:50.000000000 +0000
++++ atari800core_v1_20140312_mist/zpu_glue.vhdl	2014-03-06 06:02:49.000000000 +0000
+@@ -24,6 +24,7 @@
+ 	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+ 	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+ 	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
++	ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+ 	
+ 	ZPU_DO : out std_logic_vector(31 downto 0);
+@@ -43,7 +44,7 @@
+ 	
+ 	-- stack request
+ 	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+-	
++
+ 	-- response
+ 	MEMORY_READY : in std_logic
+ );
+@@ -114,22 +115,27 @@
+ 	signal config_mem : std_logic;
+ 	signal special_mem : std_logic;
+ 	
+-	signal result_next : std_logic_vector(3 downto 0);
+-	signal result_reg : std_logic_vector(3 downto 0);
+-	constant result_external : std_logic_vector(3 downto 0) := "0000";
+-	constant result_ram : std_logic_vector(3 downto 0) := "0001";
+-	constant result_ram_8bit_0 : std_logic_vector(3 downto 0) := "0010";
+-	constant result_ram_8bit_1 : std_logic_vector(3 downto 0) := "0011";
+-	constant result_ram_8bit_2 : std_logic_vector(3 downto 0) := "0100";
+-	constant result_ram_8bit_3 : std_logic_vector(3 downto 0) := "0101";
+-	constant result_rom : std_logic_vector(3 downto 0) := "0110";
+-	constant result_rom_8bit_0 : std_logic_vector(3 downto 0) := "0111";
+-	constant result_rom_8bit_1 : std_logic_vector(3 downto 0) := "1000";
+-	constant result_rom_8bit_2 : std_logic_vector(3 downto 0) := "1001";
+-	constant result_rom_8bit_3 : std_logic_vector(3 downto 0) := "1010";	
+-	constant result_config : std_logic_vector(3 downto 0) := "1011";	
+-	constant result_external_special : std_logic_vector(3 downto 0) := "1100";
+-
++	signal result_next : std_logic_vector(4 downto 0);
++	signal result_reg : std_logic_vector(4 downto 0);
++	constant result_external   : std_logic_vector(4 downto 0) := "00000";
++	constant result_ram        : std_logic_vector(4 downto 0) := "00001";
++	constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
++	constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
++	constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
++	constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
++	constant result_rom        : std_logic_vector(4 downto 0) := "00110";
++	constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
++	constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
++	constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
++	constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";	
++	constant result_config     : std_logic_vector(4 downto 0) := "01011";	
++	constant result_external_special : std_logic_vector(4 downto 0) := "01100";
++	constant result_sec        : std_logic_vector(4 downto 0) := "01101";
++	constant result_sec_8bit_0 : std_logic_vector(4 downto 0) := "01110";
++	constant result_sec_8bit_1 : std_logic_vector(4 downto 0) := "01111";
++	constant result_sec_8bit_2 : std_logic_vector(4 downto 0) := "10000";
++	constant result_sec_8bit_3 : std_logic_vector(4 downto 0) := "10001";
++	
+ 	signal request_type : std_logic_vector(4 downto 0);
+ 	
+ 	signal zpu_di_use : std_logic_vector(31 downto 0);
+@@ -196,7 +202,8 @@
+ 	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+ 	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+ 	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+-			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp
++			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
++			  special_mem
+ 			  )
+ 	begin
+ 		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+@@ -234,19 +241,37 @@
+ 				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+ 				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+ 			when "01010" =>
+-				if (zpu_8bit_read_enable_temp='1') then
+-					case (zpu_addr_unsigned(1 downto 0)) is
+-					when "00" =>
+-						result_next <= result_rom_8bit_3;										
+-					when "01" =>
+-						result_next <= result_rom_8bit_2;
+-					when "10" =>
+-						result_next <= result_rom_8bit_1;										
+-					when "11" =>
+-						result_next <= result_rom_8bit_0;
+-					end case;
++				-- TODO - addr(14) should just feed 1 bit in result reg!
++				if (zpu_addr_unsigned(14) = '1') then
++					if (zpu_8bit_read_enable_temp='1') then
++						case (zpu_addr_unsigned(1 downto 0)) is
++						when "00" =>
++							result_next <= result_sec_8bit_0;										
++						when "01" =>
++							result_next <= result_sec_8bit_1;
++						when "10" =>
++							result_next <= result_sec_8bit_2;										
++						when "11" =>
++							result_next <= result_sec_8bit_3;
++						end case;
++					else
++						result_next <= result_sec;
++					end if;					
+ 				else
+-					result_next <= result_rom;
++					if (zpu_8bit_read_enable_temp='1') then
++						case (zpu_addr_unsigned(1 downto 0)) is
++						when "00" =>
++							result_next <= result_rom_8bit_3;										
++						when "01" =>
++							result_next <= result_rom_8bit_2;
++						when "10" =>
++							result_next <= result_rom_8bit_1;										
++						when "11" =>
++							result_next <= result_rom_8bit_0;
++						end case;
++					else
++						result_next <= result_rom;
++					end if;
+ 				end if;
+ 				ZPU_MEM_BUSY <= '1';
+ 				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+@@ -287,7 +312,7 @@
+ 	end process;
+ 
+ 	zpu_di_next <= zpu_di;
+-	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
++	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di, zpu_sector_di)
+ 	begin
+ 		zpu_di_use <= (others=>'0');
+ 		case result_reg is 
+@@ -315,6 +340,16 @@
+ 				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+ 			when result_ram_8bit_3 =>
+ 				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
++			when result_sec =>
++				zpu_di_use <= zpu_sector_DI;
++			when result_sec_8bit_0 =>
++				zpu_di_use(7 downto 0) <= zpu_sector_DI(7 downto 0);
++			when result_sec_8bit_1 =>
++				zpu_di_use(7 downto 0) <= zpu_sector_DI(15 downto 8);
++			when result_sec_8bit_2 =>
++				zpu_di_use(7 downto 0) <= zpu_sector_DI(23 downto 16);
++			when result_sec_8bit_3 =>
++				zpu_di_use(7 downto 0) <= zpu_sector_DI(31 downto 24);								
+ 			when result_config =>
+ 				zpu_di_use <= zpu_config_di;
+ 			when others =>
Index: unmerged/core/de1/address_decoder.vhdl
===================================================================
--- unmerged/core/de1/address_decoder.vhdl	(nonexistent)
+++ unmerged/core/de1/address_decoder.vhdl	(revision 1)
@@ -0,0 +1,667 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+ENTITY address_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	-- bus masters - either CPU or antic
+	-- antic has priority and is slected when ANTIC_FETCH high
+	CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	CPU_FETCH : in std_logic;
+	CPU_WRITE_N : IN STD_LOGIC;
+	CPU_WRITE_DATA : in std_logic_vector(7 downto 0);	
+	
+	ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	ANTIC_FETCH : IN STD_LOGIC;
+	antic_refresh : in std_logic; -- use for sdram refresh (sdram needs more, but this is a start)
+
+	ZPU_ADDR : in std_logic_vector(23 downto 0);	
+	ZPU_FETCH : in std_logic;
+	ZPU_READ_ENABLE : in std_logic;
+	ZPU_32BIT_WRITE_ENABLE : in std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : in std_logic; -- for sram
+	ZPU_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs	
+	ZPU_WRITE_DATA : in std_logic_vector(31 downto 0);
+	
+	-- sources of data
+	ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	-- flash rom
+	GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
+	CART_ROM_DATA : in std_logic_Vector(7 downto 0);
+	
+	-- completion flags
+	RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+	ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+	CART_REQUEST_COMPLETE : IN STD_LOGIC;
+	
+	-- configuration options	
+	PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	reset_n : in std_logic;
+	
+	rom_select : in std_logic_vector(1 downto 0);
+	
+	ram_select : in std_logic_vector(1 downto 0);
+	
+	CART_RD4 : in std_logic;
+	CART_RD5 : in std_logic;
+	
+	use_sdram : in std_logic;
+		
+	-- Memory read mux output
+	MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
+	
+	-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
+	-- Allow us to say we're not ready for a cycle
+	MEMORY_READY_ANTIC : OUT STD_LOGIC;
+	MEMORY_READY_ZPU : OUT STD_LOGIC;
+	MEMORY_READY_CPU : out std_logic;	
+	
+	-- Each chip does not have whole address bus, so several are addressed at once
+	-- For reads not an issue, but for writes we need to only write to a single place!
+		-- these all take 1 cycle, so fine to leave device selected in general
+	GTIA_WR_ENABLE : OUT STD_LOGIC;
+	POKEY_WR_ENABLE : OUT STD_LOGIC;
+	POKEY2_WR_ENABLE : OUT STD_LOGIC;
+	ANTIC_WR_ENABLE : OUT STD_LOGIC;
+	PIA_WR_ENABLE : OUT STD_LOGIC;
+	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+	RAM_WR_ENABLE : OUT STD_LOGIC;	
+	PBI_WR_ENABLE : OUT STD_LOGIC;
+	
+	-- ROM and RAM have extended address busses to allow for bank switching etc.
+	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+	PBI_ADDR : out  std_logic_vector(15 downto 0);
+	
+	RAM_REQUEST : out std_logic;
+	ROM_REQUEST : out std_logic;
+	CART_REQUEST : out std_logic;
+	
+	CART_S4_n : out std_logic;
+	CART_S5_n : out std_logic;
+	CART_CCTL_n : out std_logic;
+	
+	-- width of access
+	WIDTH_8bit_ACCESS : out std_logic;
+	WIDTH_16bit_ACCESS : out std_logic;
+	WIDTH_32bit_ACCESS : out std_logic;
+	
+		-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+	SDRAM_WRITE_EN : out std_logic;
+	SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+	SDRAM_REFRESH : out std_logic;
+
+	SDRAM_REPLY : in std_logic; -- This matches the request once complete
+	SDRAM_DATA : in std_logic_vector(31 downto 0);
+	
+	WRITE_DATA : out std_logic_vector(31 downto 0)
+);
+
+END address_decoder;
+
+ARCHITECTURE vhdl OF address_decoder IS
+	signal ADDR_next : std_logic_vector(23 downto 0);
+	signal ADDR_reg : std_logic_vector(23 downto 0);
+
+	signal DATA_WRITE_next : std_logic_vector(31 downto 0);
+	signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
+	
+	signal width_8bit_next : std_logic;
+	signal width_16bit_next : std_logic;
+	signal width_32bit_next : std_logic;
+	signal write_enable_next : std_logic;
+
+	signal width_8bit_reg : std_logic;
+	signal width_16bit_reg : std_logic;
+	signal width_32bit_reg : std_logic;
+	signal write_enable_reg : std_logic;
+	
+	signal request_complete : std_logic;
+	signal notify_antic : std_logic;
+	signal notify_zpu : std_logic;
+	signal notify_cpu : std_logic;
+	signal start_request : std_logic;
+	
+	signal extended_access_cpu_or_antic : std_logic;
+	signal extended_access_antic : std_logic;
+	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+	
+	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+
+	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_idle : std_logic_vector(1 downto 0) := "00";
+	constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
+	constant state_waiting_zpu : std_logic_vector(1 downto 0) := "10";
+	constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
+		
+	signal ram_chip_select : std_logic;
+	signal sdram_chip_select : std_logic;
+	
+	signal sdram_request_next : std_logic;
+	signal sdram_request_reg : std_logic;
+	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+	
+	signal fetch_priority : std_logic_vector(2 downto 0);
+	
+BEGIN
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			addr_reg <= (others=>'0');
+			state_reg <= state_idle;
+			width_8bit_reg <= '0';
+			width_16bit_reg <= '0';
+			width_32bit_reg <= '0';
+			write_enable_reg <= '0';
+			data_write_reg <= (others=> '0');
+			sdram_request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			addr_reg <= addr_next;
+			state_reg <= state_next;
+			width_8bit_reg <= width_8bit_next;
+			width_16bit_reg <= width_16bit_next;
+			width_32bit_reg <= width_32bit_next;
+			write_enable_reg <= write_enable_next;
+			data_write_reg <= data_WRITE_next;
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+	
+	-- ANTIC FETCH
+	
+	-- concept
+	-- bus master sends request - antic or cpu
+	-- antic has priority
+	-- cpu may be idle
+	-- once request complete MEMORY_READY is set
+	-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
+	
+	-- so
+	-- memory_ready <= device_ready;
+	
+	-- problem
+	-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
+	
+	-- state machine
+	
+	-- state machine impl
+	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+	process(state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
+	begin
+		start_request <= '0';
+		notify_antic <= '0';
+		notify_cpu <= '0';
+		notify_zpu <= '0';
+		state_next <= state_reg;
+
+		addr_next <= addr_reg;
+		data_WRITE_next <= data_WRITE_reg;
+		width_8bit_next <= width_8bit_reg;		
+		width_16bit_next <= width_16bit_reg;		
+		width_32bit_next <= width_32bit_reg;		
+		write_enable_next <= write_enable_reg;
+		
+		case state_reg is
+			when state_idle =>
+				write_enable_next <= '0';
+				width_8bit_next <= '0';
+				width_16bit_next <= '0';
+				width_32bit_next <= '0';	
+				data_WRITE_next <= (others => '0');
+				addr_next <= zpu_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);				
+				
+				case fetch_priority is
+				when "100"|"101"|"110"|"111" => -- antic wins
+					start_request <= '1';
+					addr_next <= "00000000"&antic_ADDR;
+					width_8bit_next <= '1';					
+					if (request_complete = '1') then
+						notify_antic <= '1';
+					else
+						state_next <= state_waiting_antic;
+					end if;
+				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+					start_request <= '1';
+					addr_next <= zpu_ADDR;
+					data_WRITE_next <= zpu_wRITE_DATA;
+
+					width_8bit_next <= zpu_8BIT_WRITE_ENABLE or (zpu_READ_ENABLE and (zpu_addr(0) or zpu_addr(1)));
+					width_16bit_next <= zpu_16BIT_WRITE_ENABLE;
+					width_32bit_next <= zpu_32BIT_WRITE_ENABLE or (zpu_READ_ENABLE and not(zpu_addr(0) or zpu_addr(1))); -- narrower devices just return 8 bits on read
+					
+					write_enable_next <= not(zpu_READ_ENABLE);
+					
+					if (request_complete = '1') then
+						notify_zpu <= '1';
+					else
+						state_next <= state_waiting_zpu;
+					end if;					
+				when "001" => -- 6502 wins
+					start_request <= '1';
+					addr_next <= "00000000"&cpu_ADDR;
+					data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
+					width_8bit_next <= '1';
+					write_enable_next <= not(cpu_WRITE_N);
+					if (request_complete = '1') then
+						notify_cpu <= '1';
+					else
+						state_next <= state_waiting_cpu;
+					end if;
+				when "000" =>
+					-- no requests
+				end case;
+			when state_waiting_antic =>
+				if (request_complete = '1') then
+					notify_antic <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_zpu =>
+				if (request_complete = '1') then
+					notify_zpu <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_cpu =>
+				if (request_complete = '1') then
+					notify_cpu <= '1';
+					state_next <= state_idle;
+				end if;				
+		end case;
+	end process;
+	
+	-- output
+	MEMORY_READY_ANTIC <= notify_antic;
+	MEMORY_READY_ZPU <= notify_zpu;
+	MEMORY_READY_CPU <= notify_cpu;
+	
+	RAM_REQUEST <= ram_chip_select;
+		
+	SDRAM_REQUEST <= sdram_request_next;
+	SDRAM_REFRESH <= '0'; -- TODO, BROKEN! antic_refresh;
+	SDRAM_READ_EN <= not(write_enable_next);
+	SDRAM_WRITE_EN <= write_enable_next;
+	
+	WIDTH_8bit_ACCESS <= width_8bit_next;
+	WIDTH_16bit_ACCESS <= width_16bit_next;
+	WIDTH_32bit_ACCESS <= width_32bit_next;	
+	
+	WRITE_DATA <= DATA_WRITE_next;
+
+	-- a little sdram glue - move to sdram wrapper? TODO
+	SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+	sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+	
+	-- Calculate which memory area to use
+	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+	extended_access_antic <= (antic_fetch and not(portb(5)));
+	extended_access_cpu <= not(antic_fetch) and not(portb(4));
+	
+	extended_access_either <= not(portb(4));
+	
+  	process(
+		-- address and writing absolutely points us at a device
+		ADDR_next,WRITE_enable_next, 
+	
+		-- except for these additional special address bits	
+		portb, 
+		antic_fetch,
+		rom_select,
+		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
+		use_sdram,
+		
+		-- input data from n sources
+		GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
+		CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_POKEY2_DATA,CACHE_ANTIC_DATA,
+		
+		-- input data from n sources complete?
+		-- hardware regs take 1 cycle, so always complete		
+		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+		
+		-- on new access this is set - we must select the appropriate device - for this cycle only
+		start_request
+	)
+	begin
+		MEMORY_DATA <= (others => '1');
+		
+		ROM_ADDR <= (others=>'0');
+		RAM_ADDR <= addr_next(18 downto 0);
+		SDRAM_ADDR <= addr_next(22 downto 0);
+		
+		PBI_ADDR <= ADDR_next(15 downto 0);
+		
+		request_complete <= '0';
+		
+		GTIA_WR_ENABLE <= '0';
+		POKEY_WR_ENABLE <= '0';
+		POKEY2_WR_ENABLE <= '0';
+		ANTIC_WR_ENABLE <= '0';
+		PIA_WR_ENABLE <= '0';
+		PIA_RD_ENABLE <= '0';
+		PBI_WR_ENABLE <= '0';
+
+		RAM_WR_ENABLE <= write_enable_next;
+		SDRAM_WRITE_EN <= write_enable_next;		
+		
+		CART_S4_n <= '1';
+		CART_S5_n <= '1';
+		CART_CCTL_n <= '1';
+		
+		rom_request <= '0';
+		cart_request <= '0';
+		
+		ram_chip_select <= '0';
+		sdram_chip_select <= '0';
+
+	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+		if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+
+		RAM_ADDR(18 downto 16) <= "000";	
+		SDRAM_ADDR(22 downto 16) <= "0000000";
+	
+		case addr_next(15 downto 8) is 
+				-- GTIA
+				when X"D0" =>
+					GTIA_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
+					request_complete <= '1';
+			
+				-- POKEY
+				when X"D2" =>				
+					if (addr_next(4) = '0') then
+						POKEY_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY_DATA;
+					else
+						POKEY2_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
+					end if;
+					request_complete <= '1';
+
+				-- PIA
+				when X"D3" =>
+					PIA_WR_ENABLE <= write_enable_next;
+					PIA_RD_ENABLE <= '1';
+					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+					request_complete <= '1';
+					
+				-- ANTIC
+				when X"D4" =>
+					ANTIC_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
+					request_complete <= '1';
+					
+				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+				when X"D5" =>
+					if ((CART_RD4 or CART_RD5) = '1') then
+						PBI_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_CCTL_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						MEMORY_DATA(7 downto 0) <= X"FF";
+						request_complete <= '1';
+					end if;
+					
+				-- XE RAM
+				when 
+					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+					
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+					
+					case ram_select is
+						when "00" => -- 64k
+							-- default
+						when "01" => -- 128k					
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+						when "10" => -- 320k compy shop
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+						when "11" => -- 320k rambo
+							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+					end case;
+					
+				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+				when 
+					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+									
+					if (portb(7) = '0' and portb(0) = '1') then
+						request_complete <= ROM_REQUEST_COMPLETE;
+						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						rom_request <= start_request;					
+						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+						end case;														
+					else				
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+						
+						case ram_select is
+							when "00" => -- 64k
+								-- default
+							when "01" => -- 128k					
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+							when "10" => -- 320k compy shop
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							when "11" => -- 320k rambo
+								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+						end case;
+					end if;
+				
+				-- 0x80 cart
+				when
+					X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
+					|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
+		
+					if (cart_rd4 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						rom_request <= start_request;
+						CART_S4_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;	
+			
+				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+				when 
+					X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
+					|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
+					
+					if (cart_rd5 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_S5_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (portb(1) = '0') then
+							request_complete <= ROM_REQUEST_COMPLETE;
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;
+							rom_request <= start_request;
+							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+						else
+							if (use_sdram = '1') then
+								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+								sdram_chip_select <= start_request;
+								request_complete <= sdram_request_COMPLETE;														
+							else
+								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+								ram_chip_select <= start_request;
+								request_complete <= ram_request_COMPLETE;									
+							end if;
+						end if;
+					end if;
+					
+				-- OS ROM 0xc00->0xcff				
+				-- OS ROM d800->0xfff
+				when 
+					X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
+					|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
+					|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
+					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+					
+					if (portb(0) = '1') then
+						request_complete <= ROM_REQUEST_COMPLETE;
+						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						rom_request <= start_request;
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+						end case;
+								
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;
+					
+				when others =>
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+			end case;				
+		else		
+			case addr_next(23 downto 21) is			
+				when "000" =>				
+					-- internal area for zpu, never happens!
+				when "001" => -- sram, 512K
+					MEMORY_DATA(15 downto 0) <= RAM_DATA;
+					ram_chip_select <= start_request;
+					request_complete <= ram_request_COMPLETE;									
+					RAM_ADDR <= addr_next(18 downto 0);
+
+				when "010"|"011" => -- flash rom, 4MB
+					request_complete <= ROM_REQUEST_COMPLETE;
+					MEMORY_DATA(7 downto 0) <= ROM_DATA;
+					rom_request <= start_request;
+					ROM_ADDR <= addr_next(21 downto 0);
+					
+				when "100"|"101"|"110"|"111" => -- sdram, 8MB
+					MEMORY_DATA <= SDRAM_DATA;
+					sdram_chip_select <= start_request;
+					request_complete <= sdram_request_COMPLETE;	
+					SDRAM_ADDR <= addr_next(22 downto 0);				
+			end case;
+		end if;
+		
+--		case addr_next(15 downto 0) is
+--			when X"FFFC" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"FFFD" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0600" => --JSR 0610
+--				MEMORY_DATA(7 downto 0) <= X"20";
+--			when X"0601" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0602" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0603" => --JMP
+--				MEMORY_DATA(7 downto 0) <= X"4C";
+--			when X"0604" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"0605" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
+--				MEMORY_DATA(7 downto 0) <= X"AD";
+--			when X"0611" =>
+--				MEMORY_DATA(7 downto 0) <= X"0A";
+--			when X"0612" =>
+--				MEMORY_DATA(7 downto 0) <= X"D2";
+--			when X"0613" =>
+--				MEMORY_DATA(7 downto 0) <= X"85";
+--			when X"0614" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0615" =>
+--				MEMORY_DATA(7 downto 0) <= X"44";
+--			when X"0616" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0617" =>
+--				MEMORY_DATA(7 downto 0) <= X"60";
+--			when others =>
+--		end case;
+			
+	end process;
+END vhdl;
Index: unmerged/core/de1/atari800core.jdi
===================================================================
--- unmerged/core/de1/atari800core.jdi	(nonexistent)
+++ unmerged/core/de1/atari800core.jdi	(revision 1)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: unmerged/core/de1/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/core/de1/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/core/de1/complete_address_decoder.vhdl
===================================================================
--- unmerged/core/de1/complete_address_decoder.vhdl	(nonexistent)
+++ unmerged/core/de1/complete_address_decoder.vhdl	(revision 1)
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);	
+	
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END complete_address_decoder;
+
+--ARCHITECTURE vhdl OF complete_address_decoder IS
+--BEGIN
+--	comp_gen:
+--	for i in 0 to ((2**width)-1) generate
+--		addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
+--	end generate;
+--end vhdl;
+
+architecture tree of complete_address_decoder is
+	constant STAGE : natural:=width;
+	type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
+	signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
+	signal a: std_logic_vector(width-1 downto 0) ;
+begin
+	a<=addr_in;
+	process(a,p)
+	begin
+		p(stage,0) <= '1';
+		
+		for s in stage downto 1 loop
+			for r in 0 to (2**(stage-s)-1) loop
+				p(s-1,2*r) <= (not a(s-1)) and p(s,r);
+				p(s-1,2*r+1) <= a(s-1) and p(s,r);
+			end loop;
+		end loop;
+		
+		for i in  0 to (2**stage-1) loop
+			addr_decoded(i) <= p(0,i);
+		end loop;
+	end process;
+end tree;
\ No newline at end of file
Index: unmerged/core/de1/cpu_65xx_a.vhd
===================================================================
--- unmerged/core/de1/cpu_65xx_a.vhd	(nonexistent)
+++ unmerged/core/de1/cpu_65xx_a.vhd	(revision 1)
@@ -0,0 +1,1599 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processNmi : std_logic := '0';
+	signal processIrq : std_logic := '0';
+	signal processInt : std_logic := '0';
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal so_reg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAX  & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal Creg: std_logic; -- Carry
+	signal Zreg: std_logic; -- Zero flag
+	signal Ireg: std_logic; -- Interrupt flag
+	signal Dreg: std_logic; -- Decimal mode
+	signal Vreg: std_logic; -- Overflow
+	signal Nreg: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := Creg & aluInput;
+		when aluModeP =>
+			rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
+		when aluModeInc =>
+			rmwBits := Creg & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := Creg & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & Creg;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := Creg & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if Dreg = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if Dreg = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if Dreg = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if Dreg = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then -- and (halt = '0') then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+					
+					if theCpuCycle = cycleStack4 -- MWW
+					or reset = '1' then
+						nmiReg <= '1';
+					end if;					
+				if halt = '0' then
+					if theCpuCycle /= cycleBranchTaken then
+						-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+						-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+						processNmi <= not (nmiReg or opcInfo(opcIRQ));
+						processIrq <= not (irqReg or opcInfo(opcIRQ));
+					end if;
+				end if;
+			end if;
+			processInt <= processNmi or (processIrq and (not Ireg));
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, d, reset, processInt)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := d;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processInt = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processInt = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, halt, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if (enable = '1') and (halt = '0') then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= d;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= d;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= d;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					Creg <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Zreg <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					Ireg <= aluInput(2);
+				end if;
+			end if;
+			-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
+			if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
+				if (theOpcode = X"58") then
+					Ireg <= '0';
+				end if;
+				if (theOpcode = X"78") then
+					Ireg <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					Dreg <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					Vreg <= aluV;
+				end if;
+			end if;
+			if so_reg = '1' and so_n = '0' then
+				Vreg <= '1';
+			end if;
+			so_reg <= so_n;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					Nreg <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if (enable = '1') and (halt = '0') then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					q <= T; -- Read-modify-write write old value first.
+					doReg <= d; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	q <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+				if reset = '1' then
+					theWe <= '0';
+				end if;
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else
+							PC <= myAddr;
+						end if;
+					end if;
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when opcodeFetch =>
+			if processInt = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else
+				nextAddr <= nextAddrAbsIndexed;
+			end if;
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then
+				halt_dly <= halt;
+			end if;
+			if (enable = '1') and (halt = '0') then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
+--				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= d & T;
+				when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & d;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+			if (enable = '1') and (halt_dly = '0') then
+				case nextAddr is
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
+					else myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
+
+end architecture;
+
+
Index: unmerged/core/de1/flashrom.vhdl
===================================================================
--- unmerged/core/de1/flashrom.vhdl	(nonexistent)
+++ unmerged/core/de1/flashrom.vhdl	(revision 1)
@@ -0,0 +1,63 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY flashrom IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+
+	ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+	
+	REQUEST : IN STD_LOGIC;
+
+	-- takes 90+ns, wait states handled here
+	
+	-- Flash interface
+	FLASH_D : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	FLASH_CE_N : OUT STD_LOGIC;
+	FLASH_OE_N : OUT STD_LOGIC;
+	FLASH_WE_N : OUT STD_LOGIC;
+	FLASH_RESET_N : OUT STD_LOGIC;
+	FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	COMPLETE : OUT STD_LOGIC
+);
+
+END flashrom;
+
+ARCHITECTURE vhdl OF flashrom IS
+	signal complete_next : std_logic_vector(4 downto 0); --56MHZ, 17ns per cycle.
+	signal complete_reg : std_logic_vector(4 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			complete_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			complete_reg <= complete_next;
+		end if;
+	end process;
+	
+	complete_next <= request&complete_reg(complete_reg'left downto 1);
+
+	FLASH_CE_N <= '0';
+	FLASH_OE_N <= '0';
+	FLASH_WE_N <= '1';
+	FLASH_RESET_N <= RESET_N;
+	FLASH_ADDRESS <= ADDRESS;
+	
+	DOUT <= FLASH_D;
+	COMPLETE <= complete_reg(0);
+END vhdl;
\ No newline at end of file
Index: unmerged/core/de1/gtia_player.vhdl
===================================================================
--- unmerged/core/de1/gtia_player.vhdl	(nonexistent)
+++ unmerged/core/de1/gtia_player.vhdl	(revision 1)
@@ -0,0 +1,108 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_player IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : in std_logic;
+	
+	COLOUR_ENABLE : IN STD_LOGIC;
+	LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+	PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+	SIZE : in std_logic_vector(1 downto 0);
+	bitmap : in std_logic_vector(7 downto 0);
+	
+	output : out std_logic
+);
+END gtia_player;
+
+ARCHITECTURE vhdl OF gtia_player IS
+
+	-- pmgs
+	signal shift_next : std_logic_vector(7 downto 0);
+	signal shift_reg : std_logic_vector(7 downto 0);
+	signal count_next : std_logic_vector(1 downto 0);
+	signal count_reg : std_logic_vector(1 downto 0);
+begin
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= (others=>'0');
+			count_reg <= (others=>'0');		
+		elsif (clk'event and clk='1') then										
+			shift_reg <= shift_next;
+			count_reg <= count_next;
+		end if;
+	end process;
+	
+	
+	process(shift_next,COLOUR_ENABLE, live_position, player_position, size, bitmap, shift_reg, count_reg)
+	begin
+		-- size is 2 bits (00 normal, 01 twice, 10 normal(bugged), 11 four times)
+		-- grafp0 is 8 bits of data (2 bits for missiles)
+		-- hposp0_reg is position - 0x30 is left side of normal playfield, 0xd0 is right size of normal playfield
+		
+		-- 'or' into shift register, so if not empty we get extra pixels
+		
+		-- counter before we shift	
+		
+		shift_next <= shift_reg;
+		count_next <= count_reg;
+		
+		output <= shift_next(7);
+		
+		if (COLOUR_ENABLE = '1') then								
+			case size is 
+				when "00" => -- normal size
+					count_next <= "00";
+					shift_next <= shift_reg(6 downto 0) &'0';
+				when "10" => -- normal size (with bug)
+					case count_reg is
+						when "00"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "01"|"10" =>
+							count_next <= "10";						
+					end case;					
+				when "01" =>					
+					case count_reg is
+						when "01"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "00"|"10" =>
+							count_next <= "01";							
+					end case;					
+
+				when "11" =>
+					case count_reg is
+						when "00" =>
+							count_next <= "01";
+						when "01" =>
+							count_next <= "10";						
+						when "10" =>
+							count_next <= "11";
+						when "11" =>
+							shift_next <= shift_reg(6 downto 0) &'0';
+							count_next <= "00";
+					end case;
+			end case;	
+
+			if (live_position = player_position) then
+				shift_next <= shift_reg(6 downto 0) &'0' or bitmap;
+				count_next <= (others=>'0');
+			end if;			
+		end if;
+		
+	end process;
+	
+end vhdl;
\ No newline at end of file
Index: unmerged/core/de1/i2s_intf.vhd
===================================================================
--- unmerged/core/de1/i2s_intf.vhd	(nonexistent)
+++ unmerged/core/de1/i2s_intf.vhd	(revision 1)
@@ -0,0 +1,183 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+-- Modified by Mark Watson for the Atari800
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity i2s_intf is
+generic(
+   inclk_rate : positive := 25000000;
+	sample_rate : positive := 8000;
+	preamble : positive := 1; -- I2S
+	word_length : positive := 16
+	);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	-- Parallel IO
+	PCM_INL		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_INR		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTL	:	in	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTR	:	in	std_logic_vector(word_length - 1 downto 0);
+	
+	-- Codec interface (right justified mode)
+	-- LRCLK is equal to the sample rate and is synchronous to
+	-- MCLK.  It must be related to MCLK by the oversampling ratio
+	-- given in the codec datasheet.
+	I2S_LRCLK	:	out	std_logic;
+	
+	-- Data is shifted out on the falling edge of BCLK, sampled
+	-- on the rising edge.  The bit rate is determined such that
+	-- it is fast enough to fit preamble + word_length bits into
+	-- each LRCLK half cycle.  The last cycle of each word may be 
+	-- stretched to fit to LRCLK.  This is OK at least for the 
+	-- WM8731 codec.
+	-- The first falling edge of each timeslot is always synchronised
+	-- with the LRCLK edge.
+	I2S_BCLK	:	out	std_logic;
+	-- Output bitstream
+	I2S_DOUT	:	out	std_logic;
+	-- Input bitstream
+	I2S_DIN		:	in	std_logic
+	);
+end i2s_intf;
+
+architecture i2s_intf_arch of i2s_intf is
+constant ratio_mclk_fs : positive := (inclk_rate / sample_rate);
+constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
+constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
+constant nbits : positive := preamble + word_length;
+
+subtype lrdivider_t is integer range 0 to lrdivider_top;
+subtype bdivider_t is integer range 0 to bdivider_top;
+subtype bitcount_t is integer range 0 to nbits;
+
+signal lrdivider : lrdivider_t; 
+signal bdivider : bdivider_t;
+signal bitcount : bitcount_t;
+
+signal lrclk_r : std_logic;
+signal bclk_r : std_logic;
+
+-- Shift register is long enough for the number of data bits
+-- plus the preamble, plus an extra bit on the right to register
+-- the incoming data
+signal shiftreg : std_logic_vector(nbits downto 0);
+begin
+	I2S_LRCLK <= lrclk_r;
+	I2S_BCLK <= bclk_r;
+	I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
+
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			PCM_INL <= (others => '0');
+			PCM_INR <= (others => '0');
+						
+			-- Preload down-counters for clock generation
+			lrdivider <= lrdivider_top;
+			bdivider <= bdivider_top;
+			bitcount <= nbits;
+			
+			lrclk_r <= '0';
+			bclk_r <= '0';
+			shiftreg <= (others => '0');
+		elsif rising_edge(CLK) then		
+			-- Generate LRCLK at rate specified by codec configuration
+			if lrdivider = 0 then
+				-- LRCLK divider has reached 0 - start again from the top
+				lrdivider <= lrdivider_top;
+				
+				-- Generate LRCLK edge and sync the BCLK counter
+				lrclk_r <= not lrclk_r;
+				bclk_r <= '0';
+				bitcount <= nbits; -- 1 extra required for setup
+				bdivider <= bdivider_top;
+				
+				-- Load shift register with output data padding preamble
+				-- with 0s.  Load output buses with input word from the 
+				-- previous timeslot.
+				shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
+				if lrclk_r = '0' then
+					-- Previous channel input is LEFT.  This is available in the
+					-- shift register at the end of a cycle, right justified
+					PCM_INL <= shiftreg(word_length - 1 downto 0);
+					-- Next channel to output is RIGHT.  Load this into the
+					-- shift register at the start of a cycle, left justified
+					shiftreg(word_length downto 1) <= PCM_OUTR;
+				else
+					-- Previous channel input is RIGHT
+					PCM_INR <= shiftreg(word_length - 1 downto 0);
+					-- Next channel is LEFT
+					shiftreg(word_length downto 1) <= PCM_OUTL;
+				end if;
+			else
+				-- Decrement the LRCLK counter
+				lrdivider <= lrdivider - 1;
+				
+				-- Generate BCLK at a suitable rate to fit the required number
+				-- of bits into each timeslot.  Data is changed on the falling edge,
+				-- sampled on the rising edge
+				if bdivider = 0 then
+					-- If all bits have been output for this phase then
+					-- stop and wait to sync back up with LRCLK
+					if bitcount > 0 then
+						-- Reset
+						bdivider <= bdivider_top;
+						
+						-- Toggle BCLK
+						bclk_r <= not bclk_r;
+						if bclk_r = '0' then
+							-- Rising edge - shift in current bit and decrement bit counter
+							bitcount <= bitcount - 1;
+							shiftreg(0) <= I2S_DIN;
+						else
+							-- Falling edge - shift out next bit
+							shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
+						end if;
+					end if;
+				else
+					-- Decrement the BCLK counter
+					bdivider <= bdivider - 1;
+				end if;
+			end if;
+			
+		end if;
+	end process;
+end i2s_intf_arch;
+
Index: unmerged/core/de1/pia.vhdl
===================================================================
--- unmerged/core/de1/pia.vhdl	(nonexistent)
+++ unmerged/core/de1/pia.vhdl	(revision 1)
@@ -0,0 +1,402 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;	
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- pull up - i.e. 0 driven only
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC
+);
+END pia;
+
+ARCHITECTURE vhdl OF pia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	signal addr_decoded : std_logic_vector(3 downto 0);
+	
+	signal porta_output_next : std_logic_vector(7 downto 0);
+	signal porta_output_reg : std_logic_vector(7 downto 0);
+	signal porta_input_reg : std_logic_vector(7 downto 0);
+	signal porta_input_next : std_logic_vector(7 downto 0);
+
+	signal porta_direction_next : std_logic_vector(7 downto 0);
+	signal porta_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal porta_control_next : std_logic_vector(5 downto 0);
+	signal porta_control_reg : std_logic_vector(5 downto 0);
+	
+	signal portb_output_next : std_logic_vector(7 downto 0);
+	signal portb_output_reg : std_logic_vector(7 downto 0);
+	signal portb_input_reg : std_logic_vector(7 downto 0);
+	signal portb_input_next : std_logic_vector(7 downto 0);	
+
+	signal portb_direction_next : std_logic_vector(7 downto 0);
+	signal portb_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal portb_control_next : std_logic_vector(5 downto 0);
+	signal portb_control_reg : std_logic_vector(5 downto 0);
+	
+	signal irqa_next : std_logic_vector(1 downto 0);
+	signal irqa_reg : std_logic_vector(1 downto 0);
+	signal irqb_next : std_logic_vector(1 downto 0);
+	signal irqb_reg : std_logic_vector(1 downto 0);
+	
+	signal CA1_reg : std_logic;
+	signal CA2_reg : std_logic;
+	signal CB1_reg : std_logic;
+	signal CB2_reg : std_logic;
+
+	signal CA2_output_next : std_logic;
+	signal CA2_output_reg : std_logic;
+	signal CB2_output_next : std_logic;
+	signal CB2_output_reg : std_logic;
+	
+	signal read_ora : std_logic;
+	signal read_orb : std_logic;
+	
+	signal write_ora : std_logic;
+	signal write_orb : std_logic;
+
+	signal ca1_edge_next : std_logic;
+	signal ca1_edge_reg : std_logic;	
+	signal ca2_edge_next : std_logic;
+	signal ca2_edge_reg : std_logic;
+	
+	signal cb1_edge_next : std_logic;
+	signal cb1_edge_reg : std_logic;	
+	signal cb2_edge_next : std_logic;
+	signal cb2_edge_reg : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			porta_output_reg <= (others=>'0');
+			porta_input_reg <= (others=>'0');
+			porta_direction_reg <= (others=>'0'); -- default to input
+			porta_control_reg <= (others=>'0');
+			
+			portb_output_reg <= X"FF"; -- all high to ensure we have OS Rom enabled
+			portb_input_reg <= (others=>'0');
+			portb_direction_reg <= (others=>'1'); -- default to ouput
+			portb_control_reg <= (others=>'0');
+			
+			irqa_reg <= (others=>'0');
+			irqb_reg <= (others=>'0');
+			
+			CA1_reg	<= '0';
+			CA2_reg	<= '0';
+			CB1_reg	<= '0';
+			CB2_reg	<= '0';
+			
+			CA2_output_reg <= '0';
+			CB2_output_reg <= '0';
+			
+			ca1_edge_reg <= '0';
+			ca2_edge_reg <= '0';
+			
+			cb1_edge_reg <= '0';
+			cb2_edge_reg <= '0';
+			
+		elsif (clk'event and clk='1') then						
+			porta_output_reg <= porta_output_next;
+			porta_input_reg <= porta_input_next;
+			porta_direction_reg <= porta_direction_next;
+			porta_control_reg <= porta_control_next;
+			
+			portb_output_reg <= portb_output_next;
+			portb_input_reg <= PORTB_input_next;
+			portb_direction_reg <= portb_direction_next;
+			portb_control_reg <= portb_control_next;	
+	
+			irqa_reg <= irqa_next;
+			irqb_reg <= irqb_next;
+	
+			CA1_reg	<= CA1;
+			CA2_reg	<= CA2_in;
+			CB1_reg	<= CB1;
+			CB2_reg	<= CB2_in;
+			
+			CA2_output_reg <= CA2_output_next;
+			CB2_output_reg <= CB2_output_next;
+
+			ca1_edge_reg <= ca1_edge_next;			
+			ca2_edge_reg <= ca2_edge_next;
+			
+			cb1_edge_reg <= cb1_edge_next;			
+			cb2_edge_reg <= cb2_edge_next;			
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>2)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded, porta_output_reg, portb_output_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg)
+	begin
+		porta_output_next <= porta_output_reg;
+		portb_output_next <= portb_output_reg;
+		porta_direction_next <= porta_direction_reg;
+		portb_direction_next <= portb_direction_reg;
+		porta_control_next(5 downto 0) <= porta_control_reg(5 downto 0);
+		portb_control_next(5 downto 0) <= portb_control_reg(5 downto 0);
+		
+		write_ora <= '0';
+		write_orb <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					porta_output_next <= cpu_data_in;
+					write_ora <= '1';
+				else
+					porta_direction_next <= cpu_data_in;
+				end if;
+			end if;	
+
+			if(addr_decoded(1) = '1') then				
+				if (portb_control_reg(2) = '1') then
+					portb_output_next <= cpu_data_in;
+					write_orb <= '1';
+				else
+					portb_direction_next <= cpu_data_in;
+				end if;			
+			end if;						
+
+			if(addr_decoded(2) = '1') then	
+				porta_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;						
+			
+			if(addr_decoded(3) = '1') then		
+				portb_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;															
+
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded, en, porta_input_reg, portb_input_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg, irqa_reg, irqb_reg)
+	begin
+		data_out <= X"FF";
+		read_ora <= '0';
+		read_orb <= '0';
+
+		if (EN = '1') then -- since reads have an effect here...
+			if (addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					data_out <= porta_input_reg;
+					read_ora <= '1';
+				else
+					data_out <= porta_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(1) = '1') then
+				if (portb_control_reg(2) = '1') then
+					data_out <= portb_input_reg;
+					read_orb <= '1';
+				else
+					data_out <= portb_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(2) = '1') then			
+				data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
+			end if;
+
+			if (addr_decoded(3) = '1') then			
+				data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
+			end if;
+		end if;
+		
+	end process;
+	
+	-- irq handing
+	-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
+	process (irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1, CA1_reg, ca2_in, ca2_reg, ca1_edge_reg, ca2_edge_reg)
+	begin
+		irqa_next(1) <= irqa_reg(1) and not(read_ora);
+		irqa_next(0) <= irqa_reg(0) and not(read_ora);
+				
+		ca2_output_next <= ca2_output_reg;
+
+		if (CA1 = '1' and CA1_reg = '0') then
+			irqa_next(1) <= ca1_edge_reg;
+		end if;
+		if (CA1 = '0' and CA1_reg = '1') then
+			irqa_next(1) <= not(ca1_edge_reg);
+		end if;
+		
+		if (CA2_in = '1' and CA2_reg = '0') then
+			irqa_next(0) <= ca2_edge_reg;
+		end if;
+		
+		if (CA2_in = '0' and CA2_reg = '1') then
+			irqa_next(0) <= not(ca2_edge_reg);
+		end if;	
+		
+		ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (porta_control_next(5) = '0') then -- CA2 is an input					
+		else -- CA2 is an output
+			--irqa_next(0) <= '0';
+			
+			case porta_control_next(4 downto 3) is
+				when "10" =>
+					ca2_output_next <= '0'; -- direct control
+				when "11" =>
+					ca2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					else						
+						-- clock restore
+						ca2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					elsif (irqa_reg(1) = '1') then
+						-- ca1 restore
+						ca2_output_next <= '1';	
+					end if;				
+			end case;					
+		end if;
+
+	end process;
+
+	process (irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1, CB1_reg, cb2_in, cb2_reg, cb1_edge_reg, cb2_edge_reg)
+	begin
+		irqb_next(1) <= irqb_reg(1) and not(read_orb);
+		irqb_next(0) <= irqb_reg(0) and not(read_orb);
+				
+		cb2_output_next <= cb2_output_reg;
+
+		if (CB1 = '1' and CB1_reg = '0') then
+			irqb_next(1) <= cb1_edge_reg;
+		end if;
+		if (CB1 = '0' and CB1_reg = '1') then
+			irqb_next(1) <= not(cb1_edge_reg);
+		end if;
+		
+		if (CB2_in = '1' and CB2_reg = '0') then
+			irqb_next(0) <= cb2_edge_reg;
+		end if;
+		
+		if (CB2_in = '0' and CB2_reg = '1') then
+			irqb_next(0) <= not(cb2_edge_reg);
+		end if;	
+		
+		cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (portb_control_next(5) = '0') then -- CB2 is an input					
+		else -- CB2 is an output
+			--irqb_next(0) <= '0';
+			
+			case portb_control_next(4 downto 3) is
+				when "10" =>
+					cb2_output_next <= '0'; -- direct control
+				when "11" =>
+					cb2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					else						
+						-- clock restore
+						cb2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					elsif (irqb_reg(1) = '1') then
+						-- cb1 restore
+						cb2_output_next <= '1';	
+					end if;				
+			end case;					
+		end if;
+
+	end process;
+	
+	-- output
+		-- TODO - review if ca2 and cb2 are push pull or pull up...
+	--ca2 <= CA2_output_reg when porta_control_reg(5) = '1' else 'Z';
+	--cb2 <= CB2_output_reg when portb_control_reg(5) = '1' else 'Z';
+	ca2_out <= CA2_output_reg;
+	ca2_dir_out <= porta_control_reg(5);
+	cb2_out <= CB2_output_reg;
+	cb2_dir_out <= portb_control_reg(5);
+	
+	porta_out <= porta_output_reg;
+	porta_dir_out <= porta_direction_reg;
+	porta_input_next <= porta_in;
+
+	--portb_out <= portb_output_reg;
+	-- forced to 1 when in input mode - star raiders relies on this
+	portb_out(0) <= portb_output_reg(0) when portb_direction_reg(0)='1' else '1';
+	portb_out(1) <= portb_output_reg(1) when portb_direction_reg(1)='1' else '1';
+	portb_out(2) <= portb_output_reg(2) when portb_direction_reg(2)='1' else '1';
+	portb_out(3) <= portb_output_reg(3) when portb_direction_reg(3)='1' else '1';	
+	portb_out(4) <= portb_output_reg(4) when portb_direction_reg(4)='1' else '1';
+	portb_out(5) <= portb_output_reg(5) when portb_direction_reg(5)='1' else '1';
+	portb_out(6) <= portb_output_reg(6) when portb_direction_reg(6)='1' else '1';
+	portb_out(7) <= portb_output_reg(7) when portb_direction_reg(7)='1' else '1';		
+	portb_dir_out <= portb_direction_reg;
+	portb_input_next <= portb_in;
+	
+	irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
+	irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
+	
+end vhdl;
+
+
Index: unmerged/core/de1/pll.vhd
===================================================================
--- unmerged/core/de1/pll.vhd	(nonexistent)
+++ unmerged/core/de1/pll.vhd	(revision 1)
@@ -0,0 +1,427 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (5 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		gate_lock_counter		: NATURAL;
+		gate_lock_signal		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		invalid_lock_multiplier		: NATURAL;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		valid_lock_multiplier		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (5 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		clk0_divide_by => 10,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 20,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 10,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		gate_lock_counter => 1048575,
+		gate_lock_signal => "YES",
+		inclk0_input_frequency => 20000,
+		intended_device_family => "Cyclone II",
+		invalid_lock_multiplier => 5,
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		valid_lock_multiplier => 1
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "50.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "23"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "23"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "20"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "10"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: GATE_LOCK_COUNTER NUMERIC "1048575"
+-- Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "YES"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "20000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
+-- Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
+-- Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: unmerged/core/de1/pokey_noise_filter.vhdl
===================================================================
--- unmerged/core/de1/pokey_noise_filter.vhdl	(nonexistent)
+++ unmerged/core/de1/pokey_noise_filter.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY pokey_noise_filter IS
+PORT 
+( 
+	NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+		
+	PULSE_IN : IN STD_LOGIC;
+
+	NOISE_4 : IN STD_LOGIC;
+	NOISE_5 : IN STD_LOGIC;
+	NOISE_LARGE : IN STD_LOGIC;
+	
+	PULSE_OUT : OUT STD_LOGIC
+);
+END pokey_noise_filter;
+
+ARCHITECTURE vhdl OF pokey_noise_filter IS
+	signal pulse_noise_a : std_logic;
+	signal pulse_noise_b : std_logic;
+BEGIN
+	process(pulse_in, noise_4, noise_5, noise_large, pulse_noise_a, pulse_noise_b, noise_select)
+	begin
+		pulse_noise_a <= noise_large;
+		pulse_noise_b <= noise_5 and pulse_in;
+	
+		if (NOISE_SELECT(1) = '1') then
+			pulse_noise_a <= noise_4;
+		end if;
+	
+		if (NOISE_SELECT(2) = '1') then
+			pulse_noise_b <= pulse_in;
+		end if;
+		
+		PULSE_OUT <= pulse_noise_a and pulse_noise_b;
+
+		if (NOISE_SELECT(0) = '1') then
+			PULSE_OUT <= pulse_noise_b;
+		end if;		
+	end process;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/de1/poly_5.vhdl
===================================================================
--- unmerged/core/de1/poly_5.vhdl	(nonexistent)
+++ unmerged/core/de1/poly_5.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_5 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_5;
+
+ARCHITECTURE vhdl OF poly_5 IS
+	signal shift_reg: std_logic_vector(4 downto 0);
+	signal shift_next: std_logic_vector(4 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: unmerged/core/de1/scandoubler.vhdl
===================================================================
--- unmerged/core/de1/scandoubler.vhdl	(nonexistent)
+++ unmerged/core/de1/scandoubler.vhdl	(revision 1)
@@ -0,0 +1,301 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY scandoubler IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	VGA : IN STD_LOGIC;
+	COMPOSITE_ON_HSYNC : in std_logic;
+
+	colour_enable : in std_logic;
+	doubled_enable : in std_logic;
+	
+	-- GTIA interface
+	colour_in : in std_logic_vector(7 downto 0);
+	vsync_in : in std_logic;
+	hsync_in : in std_logic;
+	
+	-- TO TV...
+	R : OUT STD_LOGIC_vector(3 downto 0);
+	G : OUT STD_LOGIC_vector(3 downto 0);
+	B : OUT STD_LOGIC_vector(3 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic
+);
+END scandoubler;
+
+ARCHITECTURE vhdl OF scandoubler IS
+
+	COMPONENT gtia_palette IS
+	PORT 
+	( 
+		ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+		
+		R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+	);
+	END component;
+	
+--	component reg_file IS
+--	generic
+--	(
+--		BYTES : natural := 1;
+--		WIDTH : natural := 1
+--	);
+--	PORT 
+--	( 
+--		CLK : IN STD_LOGIC;
+--		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+--		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+--		WR_EN : IN STD_LOGIC;
+--		
+--		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+--	);
+--	END component;
+	
+	component scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	signal colour_next : std_logic_vector(7 downto 0);
+	signal colour_reg : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+
+	signal r_next : std_logic_vector(7 downto 0);
+	signal g_next : std_logic_vector(7 downto 0);
+	signal b_next : std_logic_vector(7 downto 0);	
+	signal r_reg : std_logic_vector(7 downto 0);
+	signal g_reg : std_logic_vector(7 downto 0);
+	signal b_reg : std_logic_vector(7 downto 0);
+	
+	signal linea_address : std_logic_vector(10 downto 0);
+	signal linea_write_enable : std_logic;
+	signal linea_out : std_logic_vector(7 downto 0);
+
+	signal lineb_address : std_logic_vector(10 downto 0);
+	signal lineb_write_enable : std_logic;
+	signal lineb_out : std_logic_vector(7 downto 0);
+	
+	signal input_address_next : std_logic_vector(10 downto 0);
+	signal input_address_reg : std_logic_vector(10 downto 0);
+
+	signal output_address_next : std_logic_vector(10 downto 0);
+	signal output_address_reg : std_logic_vector(10 downto 0);
+	
+	signal buffer_select_next : std_logic;
+	signal buffer_select_reg : std_logic;
+	
+	signal hsync_in_reg : std_logic;
+	
+	signal vga_hsync_next : std_logic;
+	signal vga_hsync_reg : std_logic;
+	signal vga_hsync_start : std_logic;
+	signal vga_hsync_end : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			r_reg <= (others=>'0');
+			g_reg <= (others=>'0');
+			b_reg <= (others=>'0');			
+			colour_reg <= (others=>'0');
+			hsync_reg <= '0';
+			vsync_reg <= '0';
+			
+			input_address_reg <= (others=>'0');
+			output_address_reg <= (others=>'0');
+			
+			buffer_select_reg <= '0';
+			
+			vga_hsync_reg <= '0';
+		elsif (clk'event and clk='1') then										
+			r_reg <= r_next;
+			g_reg <= g_next;
+			b_reg <= b_next;
+			colour_reg <= colour_next;
+			hsync_reg <= hsync_next;
+			vsync_reg <= vsync_next;
+		
+			input_address_reg <= input_address_next;
+			output_address_reg <= output_address_next;
+			
+			buffer_select_reg <= buffer_select_next;
+			
+			hsync_in_reg <= hsync_in;
+			
+			vga_hsync_reg <= vga_hsync_next;
+		end if;
+	end process;
+	
+	-- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!!
+	--	linea : reg_file
+		--generic map (BYTES=>456,WIDTH=>9)
+		--port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out);
+
+	--lineb : reg_file
+	--	generic map (BYTES=>456,WIDTH=>9)
+	--	port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);	
+	
+	linea : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
+
+	lineb : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);	
+	
+	-- capture
+	process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
+	begin
+		input_address_next <= input_address_reg;
+		buffer_select_next <= buffer_select_reg;
+		
+		linea_write_enable <= '0';
+		lineb_write_enable <= '0';
+		
+		if (colour_enable = '1') then
+			input_address_next <= std_logic_vector(unsigned(input_address_reg)+1);
+			linea_write_enable <= buffer_select_reg;
+			lineb_write_enable <= not(buffer_select_reg);
+		end if;		
+		
+		if (hsync_in = '1' and hsync_in_reg = '0') then
+				input_address_next <= (others=>'0');
+				buffer_select_next <= not(buffer_select_reg);
+		end if;		
+	end process;
+	
+	-- output
+	process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable)
+	begin
+		output_address_next <= output_address_reg;
+		vga_hsync_start<='0';
+		vga_hsync_next <= vga_hsync_reg;
+		
+		if (doubled_enable = '1') then
+			output_address_next <= std_logic_vector(unsigned(output_address_reg)+1);
+			
+			if (output_address_reg = "111"&X"1F") then
+				output_address_next <= (others=>'0');
+				vga_hsync_start <= '1';
+				vga_hsync_next <= '1';
+			end if;
+		end if;
+		
+		if (vga_hsync_end = '1') then
+			vga_hsync_next <= '0';
+		end if;
+	end process;
+	
+	linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg;
+	lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg;
+	
+	hsync_delay : delay_line
+		generic map (COUNT=>128)
+		port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end);			
+	
+	-- display
+	process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out)
+	begin	
+		colour_next <= colour_reg;
+		vsync_next <= vsync_reg;
+		hsync_next <= hsync_reg;
+		
+		if (vga = '0') then
+			-- non-vga mode - pass through
+			colour_next <= colour_in;
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(hsync_in or vsync_in);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(hsync_in xor vsync_in);
+			else
+				hsync_next <= not(hsync_in);			
+			end if;
+		else
+			-- vga mode, store all inputs - then play back!			
+			if (buffer_select_reg = '0') then
+				colour_next <= linea_out; -- todo, smoothly increase/decrease...
+			else
+				colour_next <= lineb_out;
+			end if;
+			
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(vga_hsync_reg);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(vga_hsync_reg xor vsync_in);
+			else
+				hsync_next <= not(vga_hsync_reg);			
+			end if;
+		end if;
+	end process;
+
+	-- colour palette
+--	Color             Value         Color             Value
+--Black           0,      0	Medium blue     8,    128
+--Rust            1,     16       Dark blue       9,    144
+--Red-orange      2,     32       Blue-grey      10,    160
+--Dark orange     3,     48       Olive green    11,    176
+--Red             4,     64       Medium green   12,    192
+--Dk lavender     5,     80       Dark green     13,    208
+--Cobalt blue     6,     96       Orange-green   14,    224
+--Ultramarine     7,    112       Orange         15,    240
+
+-- from altirra	
+	palette1 : entity work.gtia_palette(altirra)
+		port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next);
+		
+-- from lao
+--	palette2 : entity work.gtia_palette(laoo)
+--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
+	
+	-- output	
+		-- TODO - for DE2, output full 8 bits
+	R <= R_reg(7 downto 4);
+	G <= G_reg(7 downto 4);
+	B <= B_reg(7 downto 4);
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+
+end vhdl;
+
+
Index: unmerged/core/de1/spi_master.vhd
===================================================================
--- unmerged/core/de1/spi_master.vhd	(nonexistent)
+++ unmerged/core/de1/spi_master.vhd	(revision 1)
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+--
+--   FileName:         spi_master.vhd
+--   Dependencies:     none
+--   Design Software:  Quartus II Version 9.0 Build 132 SJ Full Version
+--
+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+--   Version History
+--   Version 1.0 7/23/2010 Scott Larson
+--     Initial Public Release
+--   Version 1.1 4/11/2013 Scott Larson
+--     Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
+--    
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_master IS
+  GENERIC(
+    slaves  : INTEGER := 4;  --number of spi slaves
+    d_width : INTEGER := 2); --data bus width
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+    enable  : IN     STD_LOGIC;                             --initiate transaction
+    cpol    : IN     STD_LOGIC;                             --spi clock polarity
+    cpha    : IN     STD_LOGIC;                             --spi clock phase
+    cont    : IN     STD_LOGIC;                             --continuous mode command
+    clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+    addr    : IN     INTEGER;                               --address of slave
+    tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+    miso    : IN     STD_LOGIC;                             --master in, slave out
+    sclk    : BUFFER STD_LOGIC;                             --spi clock
+    ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+    mosi    : OUT    STD_LOGIC;                             --master out, slave in
+    busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+    rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+END spi_master;
+
+ARCHITECTURE logic OF spi_master IS
+  TYPE machine IS(ready, execute);                           --state machine data type
+  SIGNAL state       : machine;                              --current state
+  SIGNAL slave       : INTEGER;                              --slave selected for current transaction
+  SIGNAL clk_ratio   : INTEGER;                              --current clk_div
+  SIGNAL count       : INTEGER;                              --counter to trigger sclk from system clock
+  SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1;     --count spi clock toggles
+  SIGNAL assert_data : STD_LOGIC;                            --'1' is tx sclk toggle, '0' is rx sclk toggle
+  SIGNAL continue    : STD_LOGIC;                            --flag to continue transaction
+  SIGNAL rx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
+  SIGNAL tx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
+  SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2;         --last rx data bit location
+BEGIN
+  PROCESS(clock, reset_n)
+  BEGIN
+
+    IF(reset_n = '0') THEN        --reset system
+      busy <= '1';                --set busy signal
+      ss_n <= (OTHERS => '1');    --deassert all slave select lines
+      mosi <= 'Z';                --set master out to high impedance
+      rx_data <= (OTHERS => '0'); --clear receive data port
+      state <= ready;             --go to ready state when reset is exited
+
+    ELSIF(clock'EVENT AND clock = '1') THEN
+      CASE state IS               --state machine
+
+        WHEN ready =>
+          busy <= '0';             --clock out not busy signal
+          ss_n <= (OTHERS => '1'); --set all slave select outputs high
+          mosi <= 'Z';             --set mosi output high impedance
+          continue <= '0';         --clear continue flag
+
+          --user input to initiate transaction
+          IF(enable = '1') THEN       
+            busy <= '1';             --set busy signal
+            IF(addr < slaves) THEN   --check for valid slave address
+              slave <= addr;         --clock in current slave selection if valid
+            ELSE
+              slave <= 0;            --set to first slave if not valid
+            END IF;
+            IF(clk_div = 0) THEN     --check for valid spi speed
+              clk_ratio <= 1;        --set to maximum speed if zero
+              count <= 1;            --initiate system-to-spi clock counter
+            ELSE
+              clk_ratio <= clk_div;  --set to input selection if valid
+              count <= clk_div;      --initiate system-to-spi clock counter
+            END IF;
+            sclk <= cpol;            --set spi clock polarity
+            assert_data <= NOT cpha; --set spi clock phase
+            tx_buffer <= tx_data;    --clock in data for transmit into buffer
+            clk_toggles <= 0;        --initiate clock toggle counter
+            last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
+            state <= execute;        --proceed to execute state
+          ELSE
+            state <= ready;          --remain in ready state
+          END IF;
+
+        WHEN execute =>
+          busy <= '1';        --set busy signal
+          ss_n(slave) <= '0'; --set proper slave select output
+          
+          --system clock to sclk ratio is met
+          IF(count = clk_ratio) THEN        
+            count <= 1;                     --reset system-to-spi clock counter
+            assert_data <= NOT assert_data; --switch transmit/receive indicator
+            IF(clk_toggles = d_width*2 + 1) THEN
+              clk_toggles <= 0;               --reset spi clock toggles counter
+            ELSE
+              clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
+            END IF;
+            
+            --spi clock toggle needed
+            IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN 
+              sclk <= NOT sclk; --toggle spi clock
+            END IF;
+            
+            --receive spi clock toggle
+            IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN 
+              rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
+            END IF;
+            
+            --transmit spi clock toggle
+            IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN 
+              mosi <= tx_buffer(d_width-1);                     --clock out data bit
+              tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
+            END IF;
+            
+            --last data receive, but continue
+            IF(clk_toggles = last_bit_rx AND cont = '1') THEN 
+              tx_buffer <= tx_data;                       --reload transmit buffer
+              clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
+              continue <= '1';                            --set continue flag
+            END IF;
+            
+            --normal end of transaction, but continue
+            IF(continue = '1') THEN  
+              continue <= '0';      --clear continue flag
+              busy <= '0';          --clock out signal that first receive data is ready
+              rx_data <= rx_buffer; --clock out received data to output port    
+            END IF;
+            
+            --end of transaction
+            IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN   
+              busy <= '0';             --clock out not busy signal
+              ss_n <= (OTHERS => '1'); --set all slave selects high
+              mosi <= 'Z';             --set mosi output high impedance
+              rx_data <= rx_buffer;    --clock out received data to output port
+              state <= ready;          --return to ready state
+            ELSE                       --not end of transaction
+              state <= execute;        --remain in execute state
+            END IF;
+          
+          ELSE        --system clock to sclk ratio not met
+            count <= count + 1; --increment counter
+            state <= execute;   --remain in execute state
+          END IF;
+
+      END CASE;
+    END IF;
+  END PROCESS; 
+END logic;
Index: unmerged/core/de1/wide_delay_line.vhdl
===================================================================
--- unmerged/core/de1/wide_delay_line.vhdl	(nonexistent)
+++ unmerged/core/de1/wide_delay_line.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY wide_delay_line IS
+generic(COUNT : natural := 1; WIDTH : natural :=1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+);
+END wide_delay_line;
+
+ARCHITECTURE vhdl OF wide_delay_line IS
+	type shift_reg_type is array(COUNT-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
+	signal shift_reg : shift_reg_type;
+	signal shift_next : shift_reg_type;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>(others=>'0'));
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>(others=>'0'));
+		end if;		
+	end process;
+	
+	-- output
+	gen_output:
+	for index in 0 to WIDTH-1 generate
+		data_out(index) <= shift_reg(0)(index);
+	end generate;
+		
+END vhdl;
Index: unmerged/core/de1/zpu/debug.c
===================================================================
--- unmerged/core/de1/zpu/debug.c	(nonexistent)
+++ unmerged/core/de1/zpu/debug.c	(revision 1)
@@ -0,0 +1,170 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/core/de1/zpu/led.c
===================================================================
--- unmerged/core/de1/zpu/led.c	(nonexistent)
+++ unmerged/core/de1/zpu/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/core/de1/zpu/mmc.h
===================================================================
--- unmerged/core/de1/zpu/mmc.h	(nonexistent)
+++ unmerged/core/de1/zpu/mmc.h	(revision 1)
@@ -0,0 +1,145 @@
+/*! \file mmc.h \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.h'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+///	\ingroup driver_hw
+/// \defgroup mmc MultiMedia and SD Flash Card Interface (mmc.c)
+/// \code #include "mmc.h" \endcode
+/// \par Description
+///		This library offers some simple functions which can be used
+///		to read and write data on a MultiMedia or SecureDigital (SD) Flash
+///		Card.  Although MM and SD Cards are designed to operate with their own
+///		special bus wiring and protocols, both types of cards also provide a
+///		simple SPI-like interface mode which is exceptionally useful when 
+///		attempting to use the cards in embedded systems.
+///
+/// \par Wiring
+///		To work with this library, the card must be wired to the SPI port of
+///		the Atmel microcontroller as described below.  Typical cards can
+///		operate at up to 25MHz maximum SPI clock rate (thus faster than most
+///		AVR's maximum SPI clock rate).
+/// <pre>
+///	      _________________
+///	     /  1 2 3 4 5 6 78 |	<- view of MMC/SD card looking at contacts
+///	    / 9                |	Pins 8 and 9 are present only on SD cards
+///	    |    MMC/SD Card   |
+///	    |                  |
+///	    --------------------
+///	    1 - CS   (chip select)          - wire to any available I/O pin(*)
+///	    2 - DIN  (data in, card<-host)  - wire to SPI MOSI pin
+///	    3 - VSS  (ground)               - wire to ground
+///	    4 - VDD  (power, 3.3V only?)    - wire to power (MIGHT BE 3.3V ONLY!)
+///	    5 - SCLK (data clock)           - wire to SPI SCK pin
+///	    6 - VSS  (ground)               - wire to ground
+///	    7 - DOUT (data out, card->host) - wire to SPI MISO pin
+///
+///	    (*) you must define this chip select I/O pin in mmcconf.h
+/// </pre>
+/// \note This code is currently below version 1.0, and therefore is considered
+/// to be lacking in some functionality or documentation, or may not be fully
+/// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "types.h"
+
+// constants/macros/typdefs
+// MMC commands (taken from sandisk MMC reference)
+#define MMC_GO_IDLE_STATE			0		///< initialize card to SPI-type access
+#define MMC_SEND_OP_COND			1		///< set card operational mode
+#define MMC_SEND_CSD				9		///< get card's CSD
+#define MMC_SEND_CID				10		///< get card's CID
+#define MMC_SEND_STATUS				13
+#define MMC_SET_BLOCKLEN			16		///< Set number of bytes to transfer per block
+#define MMC_READ_SINGLE_BLOCK		17		///< read a block
+#define MMC_WRITE_BLOCK				24		///< write a block
+#define MMC_PROGRAM_CSD				27
+#define MMC_SET_WRITE_PROT			28
+#define MMC_CLR_WRITE_PROT			29
+#define MMC_SEND_WRITE_PROT			30
+#define MMC_TAG_SECTOR_START		32
+#define MMC_TAG_SECTOR_END			33
+#define MMC_UNTAG_SECTOR			34
+#define MMC_TAG_ERASE_GROUP_START 	35		///< Sets beginning of erase group (mass erase)
+#define MMC_TAG_ERARE_GROUP_END		36		///< Sets end of erase group (mass erase)
+#define MMC_UNTAG_ERASE_GROUP		37		///< Untag (unset) erase group (mass erase)
+#define MMC_ERASE					38		///< Perform block/mass erase
+#define MMC_CRC_ON_OFF				59		///< Turns CRC check on/off
+// R1 Response bit-defines
+#define MMC_R1_BUSY					0x80	///< R1 response: bit indicates card is busy
+#define MMC_R1_PARAMETER			0x40
+#define MMC_R1_ADDRESS				0x20
+#define MMC_R1_ERASE_SEQ			0x10
+#define MMC_R1_COM_CRC				0x08
+#define MMC_R1_ILLEGAL_COM			0x04
+#define MMC_R1_ERASE_RESET			0x02
+#define MMC_R1_IDLE_STATE			0x01
+// Data Start tokens
+#define MMC_STARTBLOCK_READ			0xFE	///< when received from card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_WRITE		0xFE	///< when sent to card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_MWRITE		0xFC
+// Data Stop tokens
+#define MMC_STOPTRAN_WRITE			0xFD
+// Data Error Token values
+#define MMC_DE_MASK					0x1F
+#define MMC_DE_ERROR				0x01
+#define MMC_DE_CC_ERROR				0x02
+#define MMC_DE_ECC_FAIL				0x04
+#define MMC_DE_OUT_OF_RANGE			0x04
+#define MMC_DE_CARD_LOCKED			0x04
+// Data Response Token values
+#define MMC_DR_MASK					0x1F
+#define MMC_DR_ACCEPT				0x05
+#define MMC_DR_REJECT_CRC			0x0B
+#define MMC_DR_REJECT_WRITE_ERROR	0x0D
+
+// functions
+
+//! Initialize AVR<->MMC hardware interface.
+/// Prepares hardware for MMC access.
+void mmcInit(void);
+
+//! Initialize the card and prepare it for use.
+/// Returns zero if successful.
+u08 mmcReset(void);
+
+//! Send card an MMC command.
+/// Returns R1 result code.
+u08 mmcSendCommand(u08 cmd, u32 arg);
+
+//! Read 512-byte sector from card to buffer
+/// Returns zero if successful.
+u08 mmcRead(u32 sector);
+
+//! Write 512-byte sector from buffer to card
+/// Returns zero if successful.
+u08 mmcWrite(u32 sector);
+
+//! Internal command function.
+/// Issues a generic MMC command as specified by cmd and arg.
+u08 mmcCommand(u08 cmd, u32 arg);
+
+#endif
Index: unmerged/core/de1/zpu/pff.c
===================================================================
--- unmerged/core/de1/zpu/pff.c	(nonexistent)
+++ unmerged/core/de1/zpu/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/core/de1/zpu/rom_epilogue.vhd
===================================================================
--- unmerged/core/de1/zpu/rom_epilogue.vhd	(nonexistent)
+++ unmerged/core/de1/zpu/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/core/de1/zpu/spi.h
===================================================================
--- unmerged/core/de1/zpu/spi.h	(nonexistent)
+++ unmerged/core/de1/zpu/spi.h	(revision 1)
@@ -0,0 +1,65 @@
+/*! \file spi.h \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.h'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup driver_avr
+/// \defgroup spi SPI (Serial Peripheral Interface) Function Library (spi.c)
+/// \code #include "spi.h" \endcode
+/// \par Overview
+///		Provides basic byte and word transmitting and receiving via the AVR
+///	SPI interface.� Due to the nature of SPI, every SPI communication operation
+/// is both a transmit and simultaneous receive.
+///
+///	\note Currently, only MASTER mode is supported.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef SPI_H
+#define SPI_H
+
+#include "types.h"
+
+// function prototypes
+void mmcChipSelect(int select);
+
+
+// SPI interface initializer
+void spiInit(void);
+
+// spiTransferByte(u08 data) waits until the SPI interface is ready
+// and then sends a single byte over the SPI port.  The function also
+// returns the byte that was received during transmission.
+u08 spiTransferByte(u08 data);
+
+// spiTransferWord(u08 data) works just like spiTransferByte but
+// operates on a whole word (16-bits of data).
+u08 spiTransferFF();
+void spiTransferTwoFF();
+
+void spiDisplay(int i);
+
+#endif
Index: unmerged/core/de1/zpu/uart.h
===================================================================
--- unmerged/core/de1/zpu/uart.h	(nonexistent)
+++ unmerged/core/de1/zpu/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/core/de1/zpu_glue.vhdl
===================================================================
--- unmerged/core/de1/zpu_glue.vhdl	(nonexistent)
+++ unmerged/core/de1/zpu_glue.vhdl	(revision 1)
@@ -0,0 +1,344 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+library work;
+use work.zpupkg.all;
+
+ENTITY zpu_glue IS
+PORT 
+(
+	CLK : in std_logic;
+	RESET : in std_logic;
+	PAUSE : in std_logic;
+
+	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
+	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+	
+	ZPU_DO : out std_logic_vector(31 downto 0);
+	
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
+	
+	-- request
+	MEMORY_FETCH : out std_logic;
+	ZPU_READ_ENABLE : out std_logic;
+	ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
+	ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
+	
+	-- config
+	ZPU_CONFIG_WRITE : out std_logic;
+	
+	-- stack request
+	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+	
+	-- response
+	MEMORY_READY : in std_logic
+);
+END zpu_glue;
+
+architecture sticky of zpu_glue is
+component ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=24;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=16;  -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+	end component;	
+			
+	signal zpu_addr_unsigned : unsigned(23 downto 0);
+	signal zpu_do_unsigned : unsigned(31 downto 0);
+	signal ZPU_DI_unsigned : unsigned(31 downto 0);
+	signal zpu_break : std_logic;
+	signal zpu_debug : zpu_dbgo_t;
+	
+	signal zpu_mem_busy : std_logic;
+	
+	signal zpu_memory_fetch_pending_next : std_logic;
+	signal zpu_memory_fetch_pending_reg : std_logic;
+	
+	signal ZPU_32bit_READ_ENABLE_temp : std_logic;
+	signal ZPU_8bit_READ_ENABLE_temp : std_logic;	
+	signal ZPU_READ_temp : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;	
+	signal ZPU_WRITE_temp : std_logic;
+	
+	signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;	
+	signal ZPU_READ_next : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;	
+	signal ZPU_READ_reg : std_logic;
+	
+	signal block_mem : std_logic;
+	signal config_mem : std_logic;
+	signal special_mem : std_logic;
+	
+	signal result_next : std_logic_vector(3 downto 0);
+	signal result_reg : std_logic_vector(3 downto 0);
+	constant result_external : std_logic_vector(3 downto 0) := "0000";
+	constant result_ram : std_logic_vector(3 downto 0) := "0001";
+	constant result_ram_8bit_0 : std_logic_vector(3 downto 0) := "0010";
+	constant result_ram_8bit_1 : std_logic_vector(3 downto 0) := "0011";
+	constant result_ram_8bit_2 : std_logic_vector(3 downto 0) := "0100";
+	constant result_ram_8bit_3 : std_logic_vector(3 downto 0) := "0101";
+	constant result_rom : std_logic_vector(3 downto 0) := "0110";
+	constant result_rom_8bit_0 : std_logic_vector(3 downto 0) := "0111";
+	constant result_rom_8bit_1 : std_logic_vector(3 downto 0) := "1000";
+	constant result_rom_8bit_2 : std_logic_vector(3 downto 0) := "1001";
+	constant result_rom_8bit_3 : std_logic_vector(3 downto 0) := "1010";	
+	constant result_config : std_logic_vector(3 downto 0) := "1011";	
+	constant result_external_special : std_logic_vector(3 downto 0) := "1100";
+
+	signal request_type : std_logic_vector(4 downto 0);
+	
+	signal zpu_di_use : std_logic_vector(31 downto 0);
+	
+	signal memORY_ACCESS : std_logic;
+
+	-- 1 cycle delay on memory read - needed to allow running at higher clock
+	signal zpu_di_next : std_logic_vector(31 downto 0);
+	signal zpu_di_reg : std_logic_vector(31 downto 0);
+	
+	signal memory_ready_next : std_logic;
+	signal memory_ready_reg : std_logic;
+	
+	signal zpu_enable : std_logic;
+	
+	signal zpu_addr_next : std_logic_vector(23 downto 0);
+	signal zpu_addr_reg : std_logic_vector(23 downto 0);
+	
+begin
+		-- register
+	process(clk,reset)
+	begin
+		if (reset='1') then
+			zpu_memory_fetch_pending_reg <= '0';
+			result_reg <= result_rom;
+			zpu_di_reg <= (others=>'0');
+			memory_ready_reg <= '0';
+			zpu_addr_reg <= (others=>'0');
+			ZPU_32BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_16BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_8BIT_WRITE_ENABLE_reg <= '0';	
+			ZPU_READ_reg <= '0';
+		elsif (clk'event and clk='1') then
+			zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
+			result_reg <= result_next;
+			zpu_di_reg <= zpu_di_next;
+			memory_ready_reg <= memORY_READY_next;
+			zpu_addr_reg <=zpu_addr_next;
+			ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
+			ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
+			ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
+			ZPU_READ_reg <= ZPU_READ_next;
+		end if;
+	end process;
+
+-- a little glue
+	process(zpu_ADDR_unsigned)
+	begin
+		block_mem <= '0';
+		config_mem <= '0';
+		special_mem <= '0';
+		-- $00000-$0FFFF = Own ROM/RAM
+		-- $10000-$1FFFF = Atari
+		-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
+		-- $40000-$4FFFF = Config area
+		if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
+			block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
+			config_mem <= zpu_addr_unsigned(18);
+			special_mem <= zpu_addr_unsigned(17);
+		end if;	
+	end process;
+
+	ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
+	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp
+			  )
+	begin
+		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+		result_next <= result_reg;
+		memory_ready_next <= memory_ready;
+		zpu_stACK_WRITE <= (others=>'0');
+		ZPU_config_write <= '0';
+		zpu_addr_next <= zpu_addr_reg;
+	
+		ZPU_MEM_BUSY <= pause;
+		
+		MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
+		
+		memory_fetch <= zpu_memory_fetch_pending_reg;
+		
+		zpu_read_next <= zpu_read_reg;
+		zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
+		zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
+		zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;	
+		
+		request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
+		case request_type is
+			when "00010"|"00110" =>
+				zpu_memory_fetch_pending_next <= '1';
+				if (special_mem='0') then
+					result_next <= result_external;
+				else
+					result_next <= result_external_special;
+				end if;
+				
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+				zpu_read_next <= zpu_read_temp;
+				zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
+				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+			when "01010" =>
+				if (zpu_8bit_read_enable_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_rom_8bit_3;										
+					when "01" =>
+						result_next <= result_rom_8bit_2;
+					when "10" =>
+						result_next <= result_rom_8bit_1;										
+					when "11" =>
+						result_next <= result_rom_8bit_0;
+					end case;
+				else
+					result_next <= result_rom;
+				end if;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "01110" =>
+				if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_ram_8bit_3;										
+						ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
+					when "01" =>
+						result_next <= result_ram_8bit_2;
+						ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
+					when "10" =>
+						result_next <= result_ram_8bit_1;					
+						ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;					
+					when "11" =>
+						result_next <= result_ram_8bit_0;
+						ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
+					end case;
+				else
+					result_next <= result_ram;
+					ZPU_STACK_WRITE <= (others=>zpu_write_temp);					
+				end if;
+				ZPU_MEM_BUSY <= '1';				
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "10110"|"10010" =>
+				result_next <= result_config;
+				ZPU_MEM_BUSY <= '1';
+				ZPU_config_write <= ZPU_WRITE_temp; 
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);				
+			when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
+				  "10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111" =>
+				ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
+				zpu_memory_fetch_pending_next <= not(memORY_READY);
+			when others =>
+				-- keep
+		end case;
+	end process;
+
+	zpu_di_next <= zpu_di;
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
+	begin
+		zpu_di_use <= (others=>'0');
+		case result_reg is 
+			when result_external =>
+				zpu_di_use <= zpu_di_reg;
+			when result_external_special =>
+				zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);				
+			when result_rom =>
+				zpu_di_use <= zpu_rom_DI;
+			when result_rom_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
+			when result_rom_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
+			when result_rom_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
+			when result_rom_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);				
+			when result_ram =>
+				zpu_di_use <= zpu_ram_DI;
+			when result_ram_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
+			when result_ram_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
+			when result_ram_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+			when result_ram_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
+			when result_config =>
+				zpu_di_use <= zpu_config_di;
+			when others =>
+				-- nothing
+		end case;
+	end process;
+
+-- zpu itself
+	--zpu_enable <= enable and not(pause);
+	zpu_enable <= '1'; -- does nothing useful...
+	
+myzpu: ZPUMediumCore
+	port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
+	data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
+	byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
+	
+	zpu_di_unsigned <= unsigned(zpu_di_use);
+	zpu_do <= std_logic_vector(zpu_do_unsigned);
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_FETCH <= zpu_addr_reg;
+		
+	zpu_read_enable <= zpu_read_reg;
+	zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
+	zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
+	zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
+
+end sticky;
Index: unmerged/core/de1/zpu/pause.h
===================================================================
--- unmerged/core/de1/zpu/pause.h	(nonexistent)
+++ unmerged/core/de1/zpu/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/core/de1/zpu/regs.h
===================================================================
--- unmerged/core/de1/zpu/regs.h	(nonexistent)
+++ unmerged/core/de1/zpu/regs.h	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_dmactl;
+
+#endif // regs_h
Index: unmerged/core/de1/zpu/spi.c
===================================================================
--- unmerged/core/de1/zpu/spi.c	(nonexistent)
+++ unmerged/core/de1/zpu/spi.c	(revision 1)
@@ -0,0 +1,116 @@
+/*! \file spi.c \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.c'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include "spi.h"
+
+#include "regs.h"
+#include "spi.h"
+
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+	updateSpiState();
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+	updateSpiState();
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+}
+
Index: unmerged/core/de1/zpu/uart.c
===================================================================
--- unmerged/core/de1/zpu/uart.c	(nonexistent)
+++ unmerged/core/de1/zpu/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/core/de1/zpu_core.vhd
===================================================================
--- unmerged/core/de1/zpu_core.vhd	(nonexistent)
+++ unmerged/core/de1/zpu_core.vhd	(revision 1)
@@ -0,0 +1,961 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium                                                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the medium size version.  ----
+----  Supports external memories.                                         ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPUMediumCore(Behave) (Entity and architecture)    ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+--
+-- write_en_o   - set to '1' for a single cycle to send off a write request.
+--                data_o is valid only while write_en_o='1'.
+-- read_en_o    - set to '1' for a single cycle to send off a read request.
+-- mem_busy_i   - It is illegal to send off a read/write request when
+--                mem_busy_i='1'.
+--                Set to '0' when data_i  is valid after a read request.
+--                If it goes to '1'(busy), it is on the cycle after read/
+--                write_en_o is '1'.
+-- addr_o       - address for read/write request
+-- data_i       - read data. Valid only on the cycle after mem_busy_i='0'
+--                after read_en_o='1' for a single cycle.
+-- data_o       - data to write
+-- break_o      - set to '1' when CPU hits break instruction
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+end entity ZPUMediumCore;
+
+architecture Behave of ZPUMediumCore is
+   constant BYTE_BITS    : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+   constant WORD_BYTES   : integer:=WORD_SIZE/OPCODE_W;
+   constant MAX_ADDR_BIT : integer:=ADDR_W-2;
+   -- Stack Pointer initial value: BRAM size-8
+   constant SP_START_1   : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
+   constant SP_START     : unsigned(ADDR_W-1 downto BYTE_BITS):=
+                           SP_START_1(ADDR_W-1 downto BYTE_BITS);
+
+   -- Update [SP+1]. We hold it in b_r, this writes the value to memory.
+   procedure FlushB(signal we     : out std_logic;
+                    signal addr   : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal inc_sp : in  unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal data   : out unsigned(WORD_SIZE-1 downto 0);
+                    signal b      : in  unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      we   <= '1';
+      addr <= inc_sp;
+      data <= b;
+   end procedure FlushB;
+
+   -- Do a simple stack push, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Push(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                  signal a      : in    unsigned(WORD_SIZE-1 downto 0);
+                  signal b      : out   unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      b  <= a;      -- Update cache [SP+1]=[SP]
+      sp <= sp-1;
+   end procedure Push;
+
+   -- Do a simple stack pop, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Pop(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                 signal a      : out   unsigned(WORD_SIZE-1 downto 0);
+                 signal b      : in    unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      a  <= b;      -- Update cache [SP]=[SP+1]
+      sp <= sp+1;
+   end procedure Pop;
+
+   -- Expand a PC value to WORD_SIZE
+   function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
+      variable nv : unsigned(WORD_SIZE-1 downto 0);
+   begin
+      nv:=(others => '0');
+      nv(ADDR_W-1 downto 0):=v;
+      return nv;
+   end function ExpandPC;
+
+   -- Program counter
+   signal pc_r          : unsigned(ADDR_W-1 downto 0):=(others => '0');
+   -- Stack pointer
+   signal sp_r          : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
+   -- SP+1, SP+2 and SP-1 are very used, these are shortcuts
+   signal inc_sp        : unsigned(ADDR_W-1 downto BYTE_BITS);
+   signal inc_inc_sp    : unsigned(ADDR_W-1 downto BYTE_BITS);
+   -- a_r is a cache for the top of the stack [SP]
+   -- Note: as this is a stack CPU this is a very important register.
+   signal a_r           : unsigned(WORD_SIZE-1 downto 0);
+   -- b_r is a cache for the next value in the stack [SP+1]
+   signal b_r           : unsigned(WORD_SIZE-1 downto 0);
+   signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_res1_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res2_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res3_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_a_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_b_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal idim_r        : std_logic;
+   signal write_en_r    : std_logic;
+	signal byte_read_r  : std_logic;
+	signal byte_write_r  : std_logic;
+	signal short_write_r : std_logic;
+   signal read_en_r     : std_logic;
+   signal addr_r        : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
+	signal addrl_r        : unsigned(BYTE_BITS-1 downto 0):=(others => '0');
+   signal fetched_w_r   : unsigned(WORD_SIZE-1 downto 0);
+
+   type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
+                   st_fetch, st_execute, st_decode, st_decode2, st_resync,
+                   st_store_sp2, st_resync2, st_resync3, st_loadb2,
+                   st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
+                   st_binary_op_res, st_idle); 
+   signal state : state_t:=st_resync;
+
+   -- Go to st_fetch state or just do its work
+   procedure DoFetch(constant FAST   : boolean;
+                     signal state    : out state_t;
+                     signal addr     : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal pc       : in  unsigned(ADDR_W-1 downto 0);
+                     signal re       : out std_logic;
+                     signal busy     : in  std_logic) is
+   begin
+      if FAST then
+         -- Equivalent to st_fetch
+         if busy='0' then
+            addr  <= pc(ADDR_W-1 downto BYTE_BITS);
+            re    <= '1';
+            state <= st_decode;
+         end if;
+      else
+         state <= st_fetch;
+      end if;
+   end procedure DoFetch;
+
+   -- Perform a "binary operation" (2 operands)
+   procedure DoBinOp(result         : in    unsigned(WORD_SIZE-1 downto 0);
+                     signal state   : out   state_t;
+                     signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal re      : out   std_logic;
+                     signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                     signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                     constant DEPTH :       natural) is
+   begin
+      if DEPTH=2 then
+         -- 2 clocks: st_binary_op_res+st_binary_op_res2
+         state  <= st_binary_op_res;
+         dest_p <= result;
+      elsif DEPTH=1 then
+         -- 1 clock: st_binary_op_res2
+         state  <= st_binary_op_res2;
+         dest_p <= result;
+      else -- 0 clocks
+         re    <= '1';
+         addr  <= sp+2;
+         sp    <= sp+1;
+         dest  <= result;
+         state <= st_popped;
+      end if;
+   end procedure DoBinOp;
+
+   -- Perform a boolean "binary operation" (2 operands)
+   procedure DoBinOpBool(result         : in    boolean;
+                         signal state   : out   state_t;
+                         signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal re      : out   std_logic;
+                         signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                         signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                         constant DEPTH :       natural) is
+      variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   begin
+      if result then
+         res(0):='1';
+      end if;
+      DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
+   end procedure DoBinOpBool;
+
+   type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
+                   dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
+                   dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
+                   dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
+                   dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
+                   dec_less_than, dec_less_than_or_equal, dec_lshr,
+                   dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
+                   dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
+                   dec_insn_fetch, dec_pop_down);
+   signal insn : insn_t;
+   type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
+   signal insns : insn_array_t;
+   type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
+   signal opcode_r : opcode_array_t;
+begin
+   -- the memory subsystem will tell us one cycle later whether or
+   -- not it is busy
+   write_en_o <= write_en_r;
+   read_en_o  <= read_en_r;
+	byte_read_o  <= byte_read_r;
+	byte_write_o  <= byte_write_r;
+	short_write_o  <= short_write_r;
+   addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
+   addr_o(BYTE_BITS-1 downto 0)      <= addrl_r;
+
+   -- SP+1 and +2
+   inc_sp     <= sp_r+1;
+   inc_inc_sp <= sp_r+2;
+
+   opcode_control:
+   process (clk_i)
+      variable topcode     : unsigned(OPCODE_W-1 downto 0);
+      variable ex_opcode   : unsigned(OPCODE_W-1 downto 0);
+      variable sp_offset   : unsigned(4 downto 0);
+      variable tsp_offset  : unsigned(4 downto 0);
+      variable next_pc     : unsigned(ADDR_W-1 downto 0);
+      variable tdecoded    : insn_t;
+      variable tinsns   : insn_array_t;
+      variable mult_res    : unsigned(WORD_SIZE*2-1 downto 0);
+      variable ipc_low     : integer range 0 to 3; -- Address inside a word (pc_r)
+      variable inpc_low    : integer range 0 to 3; -- Address inside a word (next_pc)
+      variable not_lshr    : std_logic:='1';
+   begin
+      if rising_edge(clk_i) then
+         break_o <= '0';
+         if reset_i='1' then
+            if ENA_IDLE then
+               state <= st_idle;
+            else
+               state <= st_resync;
+            end if;
+            sp_r         <= SP_START;
+            pc_r         <= (others => '0');
+            idim_r       <= '0';
+            write_en_r   <= '0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            read_en_r    <= '0';
+            mult_a_r     <= (others => '0');
+            mult_b_r     <= (others => '0');
+            dbg_o.b_inst <= '0';
+            -- Reseting add_r here makes XST fail to use BRAMs ?!
+         else -- reset_i='1'
+            if MULT_PIPE then
+               -- We must multiply unconditionally to get pipelined multiplication
+               mult_res:=mult_a_r*mult_b_r;
+               mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+               mult_res2_r <= mult_res1_r;
+               mult_res3_r <= mult_res2_r;
+               mult_a_r    <= (others => D_CARE_VAL);
+               mult_b_r    <= (others => D_CARE_VAL);
+            end if;
+
+            if BINOP_PIPE=2 then
+               bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
+            end if;
+   
+            read_en_r  <='0';
+            write_en_r <='0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            -- Allow synthesis tools to load bogus values when we don't
+            -- care about the address and output data.
+            addr_r     <= (others => D_CARE_VAL);
+            data_o     <= (others => D_CARE_VAL);
+				addrl_r    <= "00";
+   
+            if (write_en_r='1') and (read_en_r='1') then
+               report "read/write collision" severity failure;
+            end if;
+
+            ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
+            sp_offset(4):=not opcode_r(ipc_low)(4);
+            sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
+            next_pc:=pc_r+1;
+   
+            -- Prepare trace snapshot
+            dbg_o.opcode <= opcode_r(ipc_low);
+            dbg_o.pc     <= resize(pc_r,32);
+            dbg_o.stk_a  <= resize(a_r,32);
+            dbg_o.stk_b  <= resize(b_r,32);
+            dbg_o.b_inst <= '0';
+            dbg_o.sp     <= (others => '0');
+            dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+   
+            case state is
+                 when st_idle =>
+                      if enable_i='1' then
+                         state <= st_resync;
+                      end if;
+                 -- Initial state of ZPU, fetch top of stack (A/B) + first instruction
+                 when st_resync =>
+                      if mem_busy_i='0' then
+                         addr_r    <= sp_r;
+                         read_en_r <= '1';
+                         state     <= st_resync2;
+                      end if;
+                 when st_resync2 =>
+                      if mem_busy_i='0' then
+                         a_r       <= data_i;
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_resync3;
+                      end if;
+                 when st_resync3 =>
+                      if mem_busy_i='0' then
+                         b_r       <= data_i;
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 when st_decode =>
+                      if mem_busy_i='0' then
+                         -- Here we latch the fetched word to give one full clock
+                         -- cycle to the instruction decoder. This could be removed
+                         -- if using BRAMs and the decoder delay isn't important.
+                         fetched_w_r <= data_i;
+                         state       <= st_decode2;
+                      end if;
+                 when st_decode2 =>
+                      -- decode 4 instructions in parallel
+                      for i in 0 to WORD_BYTES-1 loop
+                          topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
+
+                          tsp_offset(4):=not topcode(4);
+                          tsp_offset(3 downto 0):=topcode(3 downto 0);
+
+                          opcode_r(i) <= topcode;
+                          if topcode(7 downto 7)=OPCODE_IM then
+                             tdecoded:=dec_im;
+                          elsif topcode(7 downto 5)=OPCODE_STORESP then
+                             if tsp_offset=0 then
+                                -- Special case, we can avoid a write
+                                tdecoded:=dec_pop;
+                             elsif tsp_offset=1 then
+                                -- Special case, collision
+                                tdecoded:=dec_pop_down;
+                             else
+                                tdecoded:=dec_store_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_LOADSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_dup;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_dup_stk_b;
+                             else
+                                tdecoded:=dec_load_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_EMULATE then
+                             tdecoded:=dec_emulate;
+                             if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
+                                tdecoded:=dec_neq_branch;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
+                                tdecoded:=dec_eq;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
+                                tdecoded:=dec_loadb;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
+                                tdecoded:=dec_push_sp_add;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
+                                tdecoded:=dec_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
+                                tdecoded:=dec_u_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
+                                tdecoded:=dec_mult;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
+                                tdecoded:=dec_storeb;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
+                                tdecoded:=dec_call_pc_rel;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
+                                tdecoded:=dec_sub;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+                                tdecoded:=dec_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+                                tdecoded:=dec_u_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
+                                tdecoded:=dec_call;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
+                                tdecoded:=dec_pop_pc_rel;
+                             elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+                                tdecoded:=dec_lshr;
+                             end if;
+                          elsif topcode(7 downto 4)=OPCODE_ADDSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_shift;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_add_top;
+                             else
+                                tdecoded:=dec_add_sp;
+                             end if;
+                          else -- OPCODE_SHORT
+                             case topcode(3 downto 0) is
+                                  when OPCODE_BREAK =>
+                                       tdecoded:=dec_break;
+                                  when OPCODE_PUSHSP =>
+                                       tdecoded:=dec_push_sp;
+                                  when OPCODE_POPPC =>
+                                       tdecoded:=dec_pop_pc;
+                                  when OPCODE_ADD =>
+                                       tdecoded:=dec_add;
+                                  when OPCODE_OR =>
+                                       tdecoded:=dec_or;
+                                  when OPCODE_AND =>
+                                       tdecoded:=dec_and;
+                                  when OPCODE_LOAD =>
+                                       tdecoded:=dec_load;
+                                  when OPCODE_NOT =>
+                                       tdecoded:=dec_not;
+                                  when OPCODE_FLIP =>
+                                       tdecoded:=dec_flip;
+                                  when OPCODE_STORE =>
+                                       tdecoded:=dec_store;
+                                  when OPCODE_POPSP =>
+                                       tdecoded:=dec_pop_sp;
+                                  when others => -- OPCODE_NOP and others
+                                       tdecoded:=dec_nop;
+                             end case;
+                          end if;
+                          tinsns(i):=tdecoded;
+                      end loop;
+                      
+                      insn <= tinsns(ipc_low);
+                      -- once we wrap, we need to fetch
+                      tinsns(0):=dec_insn_fetch;
+                      insns <= tinsns;
+                      state <= st_execute;
+
+                      -- Each instruction must:
+                      --
+                      -- 1. increase pc_r if applicable
+                      -- 2. set next state if applicable
+                      -- 3. do it's operation
+                 when st_execute =>
+                      -- Some shortcut to make the code readable:
+                      inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
+                      ex_opcode:=opcode_r(ipc_low);
+							 
+							 if (mem_busy_i = '0') then -- MWW, do not move on until mem is not busy!
+							 insn <= insns(inpc_low);
+							 
+                      -- Defaults used by most instructions
+                      if insn/=dec_insn_fetch and insn/=dec_im then
+                         dbg_o.b_inst <= '1';
+                         idim_r       <= '0';
+                      end if;
+							
+							case insn is
+                           when dec_insn_fetch =>
+                                -- Not a real instruction, fetch new instructions
+                                DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
+                           when dec_im =>
+                                -- Push(immediate value), IDIM=1
+                                -- if IDIM=0 Push(signed(opcode & 0x7F)) else
+                                --           Push((Pop()<<7)|(opcode&0x7F))
+                                if mem_busy_i='0' then
+                                   dbg_o.b_inst <= '1';
+                                   idim_r       <= '1';
+                                   pc_r             <= pc_r+1;
+                                   if idim_r='1' then
+                                      -- We already started an IM sequence
+                                      -- Shift left 7 bits
+                                      a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
+                                      -- Put the new value
+                                      a_r(6 downto 0) <= ex_opcode(6 downto 0);
+                                   else
+                                      -- First IM, push the value sign extended
+                                      FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                      a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
+                                      Push(sp_r,a_r,b_r);
+                                   end if;
+                                end if;
+                           when dec_store_sp =>
+                                -- [SP+Offset]=Pop()
+                                if mem_busy_i='0' then
+                                   write_en_r <= '1';
+                                   addr_r     <= sp_r+sp_offset;
+                                   data_o     <= a_r;
+                                   Pop(sp_r,a_r,b_r);
+                                   -- We need to fetch B
+                                   state      <= st_store_sp2;
+                                end if;
+                           when dec_load_sp =>
+                                -- Push([SP+Offset])
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   Push(sp_r,a_r,b_r);
+                                   -- We are flushing B cache, so we need more time to
+                                   -- read the value.
+                                   state <= st_load_sp2;
+                                end if;
+                           when dec_emulate =>
+                                -- Push(PC+1), PC=Opcode[4:0]*32
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   Push(sp_r,a_r,b_r);
+                                   -- The emulate address is:
+                                   --        98 7654 3210
+                                   -- 0000 00aa aaa0 0000
+                                   pc_r             <= (others => '0');
+                                   pc_r(9 downto 5) <= ex_opcode(4 downto 0);
+                                end if;
+                           when dec_call_pc_rel =>
+                                -- t=Pop(), Push(PC+1), PC=PC+t
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= pc_r+a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_call =>
+                                -- t=Pop(), Push(PC+1), PC=t
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_add_sp =>
+                                -- Push(Pop()+[SP+Offset])
+                                if mem_busy_i='0' then
+                                   -- Read SP+Offset
+                                   state     <= st_add_sp2;
+                                   read_en_r <= '1';
+                                   addr_r    <= sp_r+sp_offset;
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_push_sp =>
+                                -- Push(SP)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+                                   Push(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_pc =>
+                                -- PC=Pop() (return)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_pop_pc_rel =>
+                                -- PC=PC+Pop()
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_add =>
+                                -- Push(Pop()+Pop())  [A=A+B, SP++, update B]
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r+b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_sub =>
+                                -- a=Pop(), b=Pop(), Push(b-a)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
+                                           a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_pop =>
+                                -- Pop()
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   Pop(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_down =>
+                                -- t=Pop(), Pop(), Push(t)
+                                if mem_busy_i='0' then
+                                   -- PopDown leaves top of stack unchanged
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_or =>
+                                -- Push(Pop() or Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r or b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_and =>
+                                -- Push(Pop() and Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r and b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_eq =>
+                                -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than =>
+                                -- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than_or_equal =>
+                                -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_less_than =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_less_than_or_equal =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_load =>
+                                -- Push([Pop()])
+                                if mem_busy_i='0' then
+                                   state     <= st_load2;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   read_en_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_dup =>
+                                -- t=Pop(), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   -- A is dupped, no change
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_dup_stk_b =>
+                                -- Pop(), t=Pop(), Push(t), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= b_r;
+                                   -- B goes to A
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_store =>
+                                -- a=Pop(), b=Pop(), [a]=b
+                                if mem_busy_i='0' then
+                                   state      <= st_resync;
+                                   pc_r       <= pc_r+1;
+                                   addr_r     <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   data_o     <= b_r;
+                                   write_en_r <= '1';
+                                   sp_r       <= inc_inc_sp;
+                                end if;
+                           when dec_pop_sp =>
+                                -- SP=Pop()
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= pc_r+1;
+                                   sp_r  <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                end if;
+                           when dec_nop =>
+                                pc_r <= pc_r+1;
+                           when dec_not =>
+                                -- Push(not(Pop()))
+                                pc_r <= pc_r+1;
+                                a_r  <= not a_r;
+                           when dec_flip =>
+                                -- Push(flip(Pop()))
+                                pc_r <= pc_r+1;
+                                for i in 0 to WORD_SIZE-1 loop
+                                    a_r(i) <= a_r(WORD_SIZE-1-i);
+                                end loop;
+                           when dec_add_top =>
+                                -- a=Pop(), b=Pop(), Push(b), Push(a+b)
+                                pc_r <= pc_r+1;
+                                a_r  <= a_r+b_r;
+                           when dec_shift =>
+                                -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
+                                pc_r <= pc_r+1;
+                                a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
+                                a_r(0) <= '0';
+                           when dec_push_sp_add =>
+                                -- Push(Pop()+SP)
+                                if ENA_LEVEL0 then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <=
+                                      a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
+                                end if;
+                           when dec_neq_branch =>
+                                -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
+                                -- Branches are almost always taken as they form loops
+                                if ENA_LEVEL0 then
+                                   sp_r  <= inc_inc_sp;
+                                   -- Need to fetch stack again.
+                                   state <= st_resync;
+                                   if b_r/=0 then
+                                      pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   else
+                                      pc_r <= pc_r+1;
+                                   end if;
+                                end if;
+                           when dec_mult =>
+                                -- Push(Pop()*Pop())
+                                if ENA_LEVEL1 then
+                                   if MULT_PIPE then
+                                      mult_a_r <= a_r;
+                                      mult_b_r <= b_r;
+                                      state    <= st_mult2;
+                                   else
+                                      mult_res:=a_r*b_r;
+                                      mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+                                      state       <= st_mult5;
+                                   end if;
+                                end if;
+                           when dec_break =>
+                                -- Assert the break_o signal
+                                --report "Break instruction encountered" severity failure;
+                                break_o <= '1';
+                                pc_r    <= pc_r+1;
+                           when dec_loadb =>
+                                -- Push([Pop()] & 0xFF) (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   state     <= st_loadb2;                                   
+											  addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --read_en_r <= '1';
+											  byte_read_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_storeb =>
+                                -- [Pop()]=Pop() & 0xFF (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state     <= st_resync;
+											  sp_r       <= inc_inc_sp;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --write_en_r <= '1';
+											  byte_write_r <= '1';
+                                   pc_r      <= pc_r+1;
+											  --data_o(WORD_SIZE-1 downto 8) <= (others=>'0');
+											  --data_o(7 downto 0) <= b_r(7 downto 0);										  
+											  data_o(WORD_SIZE-1 downto 0) <= b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0);										  
+                                end if;
+                           when dec_lshr =>
+                                -- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
+                                if ENA_LSHR then
+                                   -- This instruction takes more than one cycle.
+                                   -- We must avoid duplications in the trace log.
+                                   dbg_o.b_inst <= not_lshr;
+                                   not_lshr:='0';
+                                   if a_r(5 downto 0)=0 then -- Only 6 bits used
+                                      -- No more shifts
+                                      if mem_busy_i='0' then
+                                         state     <= st_popped;
+                                         a_r       <= b_r;
+                                         read_en_r <= '1';
+                                         addr_r    <= inc_inc_sp;
+                                         sp_r      <= inc_sp;
+                                         not_lshr:='1';
+                                      end if;
+                                   else -- More shifts needed
+                                      b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
+                                      a_r(5 downto 0) <= a_r(5 downto 0)-1;
+                                      insn <= insn;
+                                   end if;
+                                end if;
+                           when others =>
+                                -- Undefined behavior, we shouldn't get here.
+                                -- It only helps synthesis tools.
+                                sp_r <= (others => D_CARE_VAL);
+                                report "Illegal decode instruction?!" severity failure;
+                                --break_o <= '1';
+                      end case;
+							 end if;
+                 -- The followup of operations that takes more than one execution clock
+                 when st_store_sp2 =>
+                      if mem_busy_i='0' then
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_popped;
+                      end if;
+                 when st_load_sp2 =>
+                      if mem_busy_i='0' then
+                         state     <= st_load_sp3;
+                         -- Now we can read SP+Offset (SP already decremented)
+                         read_en_r <= '1';
+                         addr_r    <= sp_r+sp_offset+1;
+                      end if;
+                 when st_load_sp3 =>
+                      if mem_busy_i='0' then
+                         -- Note: We can't increment PC in the decode stage
+                         -- because it will modify sp_offset.
+                         pc_r  <= pc_r+1;
+                         -- Finally we have the result in A
+                         state <= st_execute;
+                         a_r   <= data_i;
+                      end if;
+                 when st_add_sp2 =>
+                      if mem_busy_i='0' then
+                         state <= st_execute;
+                         a_r   <= a_r+data_i;
+                      end if;
+                 when st_load2 =>
+                      if mem_busy_i='0' then
+                         a_r   <= data_i;
+                         state <= st_execute;
+                      end if;
+                 when st_loadb2 =>
+                      if mem_busy_i='0' then
+                         a_r(WORD_SIZE-1 downto 8) <= (others => '0');								 
+								 a_r(7 downto 0) <= data_i(7 downto 0);
+                         state <= st_execute;
+                      end if;
+                 when st_fetch =>
+                      if mem_busy_i='0' then
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 -- The following states can be used to leave cycles free for
+                 -- tools that can automagically decompose the multiplication
+                 -- in various stages. Xilinx tools can do it to increase the
+                 -- multipliers performance.
+                 when st_mult2 =>
+                      state <= st_mult3;
+                 when st_mult3 =>
+                      state <= st_mult4;
+                 when st_mult4 =>
+                      state <= st_mult5;
+                 when st_mult5 =>
+                      if mem_busy_i='0' then
+                         if MULT_PIPE then
+                            a_r <= mult_res3_r;
+                         else
+                            a_r <= mult_res1_r;
+                         end if;
+                         read_en_r <= '1';
+                         addr_r    <= inc_inc_sp;
+                         sp_r      <= inc_sp;
+                         state     <= st_popped;
+                      end if;
+               when st_binary_op_res =>
+                    -- BINOP_PIPE=2
+                    state <= st_binary_op_res2;
+               when st_binary_op_res2 =>
+                    -- BINOP_PIPE>=1
+                    read_en_r <= '1';
+                    addr_r    <= inc_inc_sp;
+                    sp_r      <= inc_sp;
+                    state     <= st_popped;
+                    if BINOP_PIPE=2 then
+                       a_r <= bin_op_res2_r;
+                    else -- 1
+                       a_r <= bin_op_res1_r;
+                    end if;
+               when st_popped =>
+                    if mem_busy_i='0' then
+                       -- Note: Moving this PC++ to the decoder seems to
+                       -- consume more LUTs.
+                       pc_r  <= pc_r+1;
+                       b_r   <= data_i;
+                       state <= st_execute;
+                    end if;
+               when others =>
+                    -- Undefined behavior, we shouldn't get here.
+                    -- It only helps synthesis tools.
+                    sp_r <= (others => D_CARE_VAL);
+                    report "Illegal state?!" severity failure;
+                    --break_o <= '1';
+            end case; -- state
+         end if; -- else reset_i='1'
+      end if; -- rising_edge(clk_i)
+   end process opcode_control;
+end architecture Behave; -- Entity: ZPUMediumCore
+
Index: unmerged/core/de1/zpu/main.c
===================================================================
--- unmerged/core/de1/zpu/main.c	(nonexistent)
+++ unmerged/core/de1/zpu/main.c	(revision 1)
@@ -0,0 +1,1166 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (reset_n == 1)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<7;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (pause == 0)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<6;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+
+	if ((1&*zpu_key) == 1)
+	{
+		// stop 6502
+		pause_6502(1);
+
+		// write a display list in page 6 (TODO, backup first...)
+		*((volatile unsigned char *)(0x600 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x601 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x602 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x603 + 0x10000)) = 0x42;
+		*((volatile unsigned char *)(0x604 + 0x10000)) = 0x40;
+		*((volatile unsigned char *)(0x605 + 0x10000)) = 0x06;
+		*((volatile unsigned char *)(0x606 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x607 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x608 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x609 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60a + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60b + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60c + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60d + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60e + 0x10000)) = 0x41;
+		*((volatile unsigned char *)(0x60f + 0x10000)) = 0x00;
+		*((volatile unsigned char *)(0x610 + 0x10000)) = 0x06;
+
+		*((volatile unsigned char *)(0x640 + 0x10000)) = 'H';
+		*((volatile unsigned char *)(0x641 + 0x10000)) = 'E';
+		*((volatile unsigned char *)(0x642 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x643 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x644 + 0x10000)) = 'O';
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+
+		// wait 10 seconds
+		for (i=0; i!=10000; ++i)
+		{
+			*atari_colbk = *atari_random;
+			wait_us(1000);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		int fileno;
+		int skip;
+		int plotted = 0;
+		unsigned char volatile * mem;
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		for (;;)
+		{
+			int i = 0;
+			int go = 0;
+			fileno = 0;
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			if (FR_OK != pf_opendir(&dir,"/"))
+			{
+				debug("opendir failed\n");
+				while(1);
+			}
+
+			plotted = 0;
+			skip = 0;
+			if (selfileno>20)
+			{
+				skip = selfileno-20;
+				skip&=0xfffffffe;
+			}
+			if (selfileno<0)
+			{
+				selfileno = 0;
+			}
+			while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+			{
+				if (filinfo.fattrib & AM_SYS)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_HID)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_DIR)
+				{
+					debug("DIR ");
+				}
+				if (selfileno == fileno)
+				{
+					for (i=0;i!=256;++i)
+					{
+						atari_sector_buffer[i] = filinfo.fname[i];
+						if (0==filinfo.fname[i]) break;
+						filinfo.fname[i]+=128;
+					}
+				}
+				if (--skip<0)
+				{
+					debug(filinfo.fname);
+					++plotted;
+					if (plotted&1)
+					{
+						setxpos(20);
+					}
+					else
+					{
+						debug("\n");
+					}
+					if (plotted==40)
+					{
+						break;
+					}
+				}
+				fileno++;
+			}
+			debug("\n");
+			setypos(21);
+			openfile(atari_sector_buffer);
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					selfileno+=2;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					selfileno-=2;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					selfileno|=1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					selfileno&=0xfffffffe;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+			if (go == 1)
+			{
+				debug("Booting...");
+				wait_us(500000);
+
+				// reset process
+				reset_6502(0);
+				*atari_nmien = 0x00;
+				clear_64k_ram();
+				reset_6502(1);
+				break;
+			}
+			wait_us(80000);
+		}
+		initdebug(debugmode);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	speed = speedslow;
+	if (2==(2&(*zpu_switches)))
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+
+		wait_us(2000000);
+	}
+
+	if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	do
+	{
+		mmcInit();
+	}
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	openfile("BOOT.ATR");
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId == 0x31)
+ 	 	{
+			int sent = 0;
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/core/de1/zpu/mycrt0.s
===================================================================
--- unmerged/core/de1/zpu/mycrt0.s	(nonexistent)
+++ unmerged/core/de1/zpu/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/core/de1/zpu/regs.c
===================================================================
--- unmerged/core/de1/zpu/regs.c	(nonexistent)
+++ unmerged/core/de1/zpu/regs.c	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+
+#endif // regs_h
Index: unmerged/core/de1/zpu/setup
===================================================================
--- unmerged/core/de1/zpu/setup	(nonexistent)
+++ unmerged/core/de1/zpu/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/core/de1/zpu/types.h
===================================================================
--- unmerged/core/de1/zpu/types.h	(nonexistent)
+++ unmerged/core/de1/zpu/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/core/de1/zpu_config_regs.vhdl
===================================================================
--- unmerged/core/de1/zpu_config_regs.vhdl	(nonexistent)
+++ unmerged/core/de1/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,501 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(1 downto 0);
+	signal ram_select_reg : std_logic_vector(1 downto 0);
+	signal rom_select_next : std_logic_vector(1 downto 0);
+	signal rom_select_reg : std_logic_vector(1 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				rom_select_reg <= "01";
+				ram_select_reg <= "10";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(9 downto 8);
+				rom_select_next <= cpu_DATA_IN(13 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(9 downto 8) <= ram_select_reg;
+				data_out(13 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= SWITCH;
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= KEY;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				--data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= switch(6);
+	USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= switch(9);
+	COMPOSITE_ON_HSYNC <= switch(8);
+	GPIO_ENABLE <= gpio_enable_reg; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+end vhdl;
+
+
Index: unmerged/core/de1/zpu/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/core/de1/zpu/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/core/de1/zpu/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,4028 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b80f5;
+00a2 : 98738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
+00a9 : ff040000;
+00aa : 00000000;
+00ab : 00000000;
+00ac : 00000000;
+00ad : 00000000;
+00ae : 00000000;
+00af : 00000000;
+00b0 : 0b0b0b88;
+00b1 : d8040000;
+00b2 : 00000000;
+00b3 : 00000000;
+00b4 : 00000000;
+00b5 : 00000000;
+00b6 : 00000000;
+00b7 : 00000000;
+00b8 : 72097081;
+00b9 : 0509060a;
+00ba : 8106ff05;
+00bb : 70547106;
+00bc : 73097274;
+00bd : 05ff0506;
+00be : 07515151;
+00bf : 04000000;
+00c0 : 72097081;
+00c1 : 0509060a;
+00c2 : 098106ff;
+00c3 : 05705471;
+00c4 : 06730972;
+00c5 : 7405ff05;
+00c6 : 06075151;
+00c7 : 51040000;
+00c8 : 05ff0504;
+00c9 : 00000000;
+00ca : 00000000;
+00cb : 00000000;
+00cc : 00000000;
+00cd : 00000000;
+00ce : 00000000;
+00cf : 00000000;
+00d0 : 810b80fa;
+00d1 : ec0c5104;
+00d2 : 00000000;
+00d3 : 00000000;
+00d4 : 00000000;
+00d5 : 00000000;
+00d6 : 00000000;
+00d7 : 00007181;
+00d8 : 05520400;
+00d9 : 00000000;
+00da : 00000000;
+00db : 00000000;
+00dc : 00000000;
+00dd : 00000000;
+00de : 00000000;
+00df : 00000000;
+00e0 : 00000000;
+00e1 : 00000000;
+00e2 : 00000000;
+00e3 : 00000000;
+00e4 : 00000000;
+00e5 : 00000000;
+00e6 : 00000000;
+00e7 : 00000284;
+00e8 : 05721010;
+00e9 : 05520400;
+00ea : 00000000;
+00eb : 00000000;
+00ec : 00000000;
+00ed : 00000000;
+00ee : 00000000;
+00ef : 00000000;
+00f0 : 00000000;
+00f1 : 00000000;
+00f2 : 00000000;
+00f3 : 00000000;
+00f4 : 00000000;
+00f5 : 00000000;
+00f6 : 00000000;
+00f7 : 00007171;
+00f8 : 05ff0571;
+00f9 : 5351020d;
+00fa : 04000000;
+00fb : 00000000;
+00fc : 00000000;
+00fd : 00000000;
+00fe : 00000000;
+00ff : 00000000;
+0100 : 10101010;
+0101 : 10101010;
+0102 : 10101010;
+0103 : 10101010;
+0104 : 10101010;
+0105 : 10101010;
+0106 : 10101010;
+0107 : 10101053;
+0108 : 51047381;
+0109 : ff067383;
+010a : 06098105;
+010b : 83051010;
+010c : 102b0772;
+010d : fc060c51;
+010e : 51043c04;
+010f : 72728072;
+0110 : 8106ff05;
+0111 : 09720605;
+0112 : 71105272;
+0113 : 0a100a53;
+0114 : 72ed3851;
+0115 : 51535104;
+0116 : 83e08008;
+0117 : 83e08408;
+0118 : 83e08808;
+0119 : 757580ef;
+011a : c72d5050;
+011b : 83e08008;
+011c : 5683e088;
+011d : 0c83e084;
+011e : 0c83e080;
+011f : 0c510483;
+0120 : e0800883;
+0121 : e0840883;
+0122 : e0880875;
+0123 : 7580eddb;
+0124 : 2d505083;
+0125 : e0800856;
+0126 : 83e0880c;
+0127 : 83e0840c;
+0128 : 83e0800c;
+0129 : 51040000;
+012a : 800489aa;
+012b : 0489aa0b;
+012c : 80c0b404;
+012d : fd3d0d75;
+012e : b9297681;
+012f : 2a0580fd;
+0130 : bc085473;
+0131 : 0c853d0d;
+0132 : 04803d0d;
+0133 : 81ff5180;
+0134 : 0b83e0c8;
+0135 : 1234ff11;
+0136 : 5170f438;
+0137 : 823d0d04;
+0138 : fa3d0d78;
+0139 : 0b0b80f5;
+013a : f05383e2;
+013b : f4525680;
+013c : cd9a3f80;
+013d : 5383e080;
+013e : 08732e8a;
+013f : 387283e0;
+0140 : 800c883d;
+0141 : 0d0483e0;
+0142 : 945283e2;
+0143 : f45180ce;
+0144 : 8e3f83e0;
+0145 : 800880d5;
+0146 : 3883e09d;
+0147 : 33537280;
+0148 : 2e80ca38;
+0149 : 83e09c33;
+014a : 70822a70;
+014b : 81065154;
+014c : 5472d338;
+014d : 73812a70;
+014e : 81065153;
+014f : 72c83873;
+0150 : 842a7081;
+0151 : 06515372;
+0152 : ffbc3875;
+0153 : 83e09d56;
+0154 : 54733375;
+0155 : 33585372;
+0156 : 772e0981;
+0157 : 06ffa738;
+0158 : 72802e93;
+0159 : 38811481;
+015a : 165654e5;
+015b : 39800b83;
+015c : e0800c88;
+015d : 3d0d0483;
+015e : e0940883;
+015f : e0800c88;
+0160 : 3d0d04fd;
+0161 : 3d0d800b;
+0162 : 80fdac08;
+0163 : 5353ff72;
+0164 : 0c80fdb0;
+0165 : 0873710c;
+0166 : 5284d851;
+0167 : fe963f88;
+0168 : 800a5380;
+0169 : 73708105;
+016a : 553472a8;
+016b : 800a2e09;
+016c : 8106f038;
+016d : 80fdac08;
+016e : 5485aad5;
+016f : aad5740c;
+0170 : 80fdb008;
+0171 : 5285aad5;
+0172 : aad5720c;
+0173 : 82800a53;
+0174 : 80737084;
+0175 : 05550c72;
+0176 : 81800a2e;
+0177 : 098106f0;
+0178 : 3880740c;
+0179 : ff720c84;
+017a : d851fdc8;
+017b : 3f853d0d;
+017c : 04fd3d0d;
+017d : 800b80fd;
+017e : ac085353;
+017f : ff87c3e1;
+0180 : f0720c80;
+0181 : fdb00873;
+0182 : 710c528c;
+0183 : 9ac051fd;
+0184 : a33f8880;
+0185 : 0a538073;
+0186 : 70810555;
+0187 : 34728184;
+0188 : 80802e09;
+0189 : 8106ef38;
+018a : 80fdac08;
+018b : 5485aad5;
+018c : aad5740c;
+018d : 80fdb008;
+018e : 5285aad5;
+018f : aad5720c;
+0190 : 82800a53;
+0191 : 80737084;
+0192 : 05550c72;
+0193 : 84848080;
+0194 : 2e098106;
+0195 : ef388074;
+0196 : 0cff87c3;
+0197 : e1f0720c;
+0198 : 8c9ac051;
+0199 : fcce3f85;
+019a : 3d0d04ff;
+019b : 3d0d80fd;
+019c : c0087008;
+019d : 52527381;
+019e : 2e8b3870;
+019f : 81800772;
+01a0 : 0c833d0d;
+01a1 : 0470feff;
+01a2 : 06720c83;
+01a3 : 3d0d04ff;
+01a4 : 3d0d80fd;
+01a5 : c0087008;
+01a6 : 5252738b;
+01a7 : 3870ffbf;
+01a8 : 06720c83;
+01a9 : 3d0d0470;
+01aa : 80c00772;
+01ab : 0c833d0d;
+01ac : 04ff0b83;
+01ad : e0b00c80;
+01ae : ceac3f80;
+01af : d1b03f83;
+01b0 : e08008f3;
+01b1 : 3880d3f5;
+01b2 : 3f800b83;
+01b3 : e0800c04;
+01b4 : 803d0d70;
+01b5 : 83e0800c;
+01b6 : 823d0d04;
+01b7 : ff3d0d73;
+01b8 : 70335351;
+01b9 : 81113371;
+01ba : 34718112;
+01bb : 34833d0d;
+01bc : 04fb3d0d;
+01bd : 77028405;
+01be : a2052256;
+01bf : 56807071;
+01c0 : 55555271;
+01c1 : 7527ac38;
+01c2 : 75137033;
+01c3 : 70147081;
+01c4 : ff065551;
+01c5 : 51517174;
+01c6 : 27893881;
+01c7 : 127081ff;
+01c8 : 06535171;
+01c9 : 81147083;
+01ca : ffff0655;
+01cb : 52547473;
+01cc : 26d63871;
+01cd : 83e0800c;
+01ce : 873d0d04;
+01cf : f83d0d7a;
+01d0 : 57800b8a;
+01d1 : 3d238070;
+01d2 : 7183e2e4;
+01d3 : 0c0b0b80;
+01d4 : f5f45357;
+01d5 : 5880da88;
+01d6 : 3f765180;
+01d7 : da823f0b;
+01d8 : 0b80fab4;
+01d9 : 5180d9f8;
+01da : 3f765180;
+01db : c2ba3f83;
+01dc : e0800878;
+01dd : 2e8f380b;
+01de : 0b80f680;
+01df : 5180d9e0;
+01e0 : 3f8a3d0d;
+01e1 : 040b0b80;
+01e2 : f6885180;
+01e3 : d9d23f75;
+01e4 : 17703355;
+01e5 : 5573802e;
+01e6 : 80fd3873;
+01e7 : ae2e8638;
+01e8 : 811656eb;
+01e9 : 39800b81;
+01ea : 16335556;
+01eb : 7380d82e;
+01ec : 09810683;
+01ed : 38815673;
+01ee : 80f83270;
+01ef : 30708025;
+01f0 : 78075151;
+01f1 : 5473802e;
+01f2 : 80cd3880;
+01f3 : 0b821633;
+01f4 : 55567380;
+01f5 : c62e0981;
+01f6 : 06833881;
+01f7 : 567380e6;
+01f8 : 32703070;
+01f9 : 80257807;
+01fa : 51515473;
+01fb : 802ea838;
+01fc : 800b8316;
+01fd : 33555673;
+01fe : 80c42e09;
+01ff : 81068338;
+0200 : 81567380;
+0201 : e4327030;
+0202 : 70802578;
+0203 : 07515154;
+0204 : 73802e83;
+0205 : 38815880;
+0206 : 0b8a3d23;
+0207 : 8a3dfc05;
+0208 : 53905283;
+0209 : e2e85180;
+020a : c2be3f89;
+020b : 3d225574;
+020c : 902e8e38;
+020d : 0b0b80f6;
+020e : 8c5180d8;
+020f : a33ffec1;
+0210 : 3983e2e8;
+0211 : 51fd953f;
+0212 : 83e2ea51;
+0213 : fd8e3f83;
+0214 : e2ec51fd;
+0215 : 873f800b;
+0216 : 83e3880c;
+0217 : 77812e81;
+0218 : 8c3883e2;
+0219 : e83383e2;
+021a : e9337188;
+021b : 2b075556;
+021c : 7383ffff;
+021d : 2e82ce38;
+021e : 7385962e;
+021f : 8e380b0b;
+0220 : 80f6a451;
+0221 : 80d7d93f;
+0222 : fdf7390b;
+0223 : 0b80f6b8;
+0224 : 5180d7cc;
+0225 : 3f7483e3;
+0226 : 900c83e2;
+0227 : ec3383e2;
+0228 : ed337188;
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+0f2f : 00000000;
+0f30 : 53504446;
+0f31 : 00000000;
+0f32 : 2873656e;
+0f33 : 643a0000;
+0f34 : 3a63686b;
+0f35 : 3a000000;
+0f36 : 73646361;
+0f37 : 72640a00;
+0f38 : 6469736b;
+0f39 : 5f696e69;
+0f3a : 743a0000;
+0f3b : 6d6f756e;
+0f3c : 743a0000;
+0f3d : 6f70656e;
+0f3e : 6469723a;
+0f3f : 00000000;
+0f40 : 424f4f54;
+0f41 : 2e415452;
+0f42 : 00000000;
+0f43 : 50617573;
+0f44 : 65640a00;
+0f45 : 53746174;
+0f46 : 3a000000;
+0f47 : 3a646f6e;
+0f48 : 650a0000;
+0f49 : 53656374;
+0f4a : 6f723a00;
+0f4b : 20726563;
+0f4c : 65697665;
+0f4d : 3a000000;
+0f4e : 2073656e;
+0f4f : 64696e67;
+0f50 : 0a000000;
+0f51 : 64617461;
+0f52 : 20000000;
+0f53 : 6e616d65;
+0f54 : 20000000;
+0f55 : 6e756d74;
+0f56 : 6f627566;
+0f57 : 66657220;
+0f58 : 00000000;
+0f59 : 626f6f74;
+0f5a : 20000000;
+0f5b : 00000000;
+0f5c : 00000000;
+0f5d : 72025f07;
+0f5e : f807a900;
+0f5f : 8d04038d;
+0f60 : 4402a907;
+0f61 : 8d0503a9;
+0f62 : 708d0a03;
+0f63 : a9018d0b;
+0f64 : 03850960;
+0f65 : 7d8a4820;
+0f66 : 53e488d0;
+0f67 : fa68aa8c;
+0f68 : 8e07ad7d;
+0f69 : 07ee8e07;
+0f6a : 60a9938d;
+0f6b : e202a907;
+0f6c : 8de302a2;
+0f6d : 0220da07;
+0f6e : 954320da;
+0f6f : 07954435;
+0f70 : 43c9fff0;
+0f71 : f0caca10;
+0f72 : ec3006e6;
+0f73 : 45d002e6;
+0f74 : 4620da07;
+0f75 : a2018144;
+0f76 : b545d543;
+0f77 : d0edca10;
+0f78 : f720d207;
+0f79 : 4c9407a9;
+0f7a : 038d0fd2;
+0f7b : 6ce202ad;
+0f7c : 8e07cd7f;
+0f7d : 07d0abee;
+0f7e : 0a03d003;
+0f7f : ee0b03ad;
+0f80 : 7d070d7e;
+0f81 : 07d08e20;
+0f82 : d2076ce0;
+0f83 : 0220da07;
+0f84 : 8de00220;
+0f85 : da078de1;
+0f86 : 022de002;
+0f87 : c9fff0ed;
+0f88 : a9008d8e;
+0f89 : 07f08200;
+0f8a : 0001d20f;
+0f8b : 0001d400;
+0f8c : 0001d401;
+0f8d : 0001d409;
+0f8e : 0001d010;
+0f8f : 0001d301;
+0f90 : 0001d300;
+0f91 : 0001d20a;
+0f92 : 0001d01b;
+0f93 : 0001d018;
+0f94 : 0001d017;
+0f95 : 0001d01a;
+0f96 : 0001d403;
+0f97 : 0001d402;
+0f98 : 0001d40e;
+0f99 : 0004007c;
+0f9a : 00040078;
+0f9b : 00040074;
+0f9c : 00040068;
+0f9d : 00040060;
+0f9e : 0004005c;
+0f9f : 00040058;
+0fa0 : 00040054;
+0fa1 : 00040050;
+0fa2 : 0004004c;
+0fa3 : 00040048;
+0fa4 : 00040044;
+0fa5 : 00040040;
+0fa6 : 00040028;
+0fa7 : 00040024;
+0fa8 : 00040020;
+0fa9 : 0004001c;
+0faa : 00040018;
+0fab : 00040014;
+0fac : 00040010;
+0fad : 0004000c;
+0fae : 00040008;
+0faf : 00040004;
+0fb0 : 00040000;
+END; 
Index: unmerged/core/de1/zpu/debug.h
===================================================================
--- unmerged/core/de1/zpu/debug.h	(nonexistent)
+++ unmerged/core/de1/zpu/debug.h	(revision 1)
@@ -0,0 +1,19 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/core/de1/zpu/led.h
===================================================================
--- unmerged/core/de1/zpu/led.h	(nonexistent)
+++ unmerged/core/de1/zpu/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/core/de1/zpu/mmcconf.h
===================================================================
--- unmerged/core/de1/zpu/mmcconf.h	(nonexistent)
+++ unmerged/core/de1/zpu/mmcconf.h	(revision 1)
@@ -0,0 +1,33 @@
+/*! \file mmcconf.h \brief MultiMedia and SD Flash Card Interface Configuration. */
+//*****************************************************************************
+//
+// File Name	: 'mmcconf.h'
+// Title		: MultiMedia and SD Flash Card Interface Configuration
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef MMCCONF_H
+#define MMCCONF_H
+
+#endif
Index: unmerged/core/de1/zpu/pff.h
===================================================================
--- unmerged/core/de1/zpu/pff.h	(nonexistent)
+++ unmerged/core/de1/zpu/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/core/de1/zpu/rom_prologue.vhd
===================================================================
--- unmerged/core/de1/zpu/rom_prologue.vhd	(nonexistent)
+++ unmerged/core/de1/zpu/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/core/de1/zpu/standalone_simple.ld
===================================================================
--- unmerged/core/de1/zpu/standalone_simple.ld	(nonexistent)
+++ unmerged/core/de1/zpu/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/core/de1/zpu/zpuromgen.c
===================================================================
--- unmerged/core/de1/zpu/zpuromgen.c	(nonexistent)
+++ unmerged/core/de1/zpu/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/core/de1/zpu_ram.cmp
===================================================================
--- unmerged/core/de1/zpu_ram.cmp	(nonexistent)
+++ unmerged/core/de1/zpu_ram.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component zpu_ram
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/de1/zpu_rom.cmp
===================================================================
--- unmerged/core/de1/zpu_rom.cmp	(nonexistent)
+++ unmerged/core/de1/zpu_rom.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component zpu_rom
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mcc216/CHANGELOG
===================================================================
--- unmerged/core/mcc216/CHANGELOG	(nonexistent)
+++ unmerged/core/mcc216/CHANGELOG	(revision 1)
@@ -0,0 +1,3 @@
+Version 1
+---------
+Initial source release
Index: unmerged/core/mcc216/address_decoder.vhdl.bak
===================================================================
--- unmerged/core/mcc216/address_decoder.vhdl.bak	(nonexistent)
+++ unmerged/core/mcc216/address_decoder.vhdl.bak	(revision 1)
@@ -0,0 +1,658 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+ENTITY address_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	-- bus masters - either CPU or antic
+	-- antic has priority and is slected when ANTIC_FETCH high
+	CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	CPU_FETCH : in std_logic;
+	CPU_WRITE_N : IN STD_LOGIC;
+	CPU_WRITE_DATA : in std_logic_vector(7 downto 0);	
+	
+	ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	ANTIC_FETCH : IN STD_LOGIC;
+	antic_refresh : in std_logic; -- use for sdram refresh (sdram needs more, but this is a start)
+
+	ZPU_ADDR : in std_logic_vector(23 downto 0);	
+	ZPU_FETCH : in std_logic;
+	ZPU_READ_ENABLE : in std_logic;
+	ZPU_32BIT_WRITE_ENABLE : in std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : in std_logic; -- for sram
+	ZPU_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs	
+	ZPU_WRITE_DATA : in std_logic_vector(31 downto 0);
+	
+	-- sources of data
+	ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	-- flash rom
+	GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
+	CART_ROM_DATA : in std_logic_Vector(7 downto 0);
+	
+	-- completion flags
+	RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+	ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+	CART_REQUEST_COMPLETE : IN STD_LOGIC;
+	
+	-- configuration options	
+	PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	reset_n : in std_logic;
+	
+	rom_select : in std_logic_vector(1 downto 0);
+	
+	ram_select : in std_logic_vector(1 downto 0);
+	
+	CART_RD4 : in std_logic;
+	CART_RD5 : in std_logic;
+	
+	use_sdram : in std_logic;
+		
+	-- Memory read mux output
+	MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
+	
+	-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
+	-- Allow us to say we're not ready for a cycle
+	MEMORY_READY_ANTIC : OUT STD_LOGIC;
+	MEMORY_READY_ZPU : OUT STD_LOGIC;
+	MEMORY_READY_CPU : out std_logic;	
+	
+	-- Each chip does not have whole address bus, so several are addressed at once
+	-- For reads not an issue, but for writes we need to only write to a single place!
+		-- these all take 1 cycle, so fine to leave device selected in general
+	GTIA_WR_ENABLE : OUT STD_LOGIC;
+	POKEY_WR_ENABLE : OUT STD_LOGIC;
+	POKEY2_WR_ENABLE : OUT STD_LOGIC;
+	ANTIC_WR_ENABLE : OUT STD_LOGIC;
+	PIA_WR_ENABLE : OUT STD_LOGIC;
+	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+	RAM_WR_ENABLE : OUT STD_LOGIC;	
+	PBI_WR_ENABLE : OUT STD_LOGIC;
+	
+	-- ROM and RAM have extended address busses to allow for bank switching etc.
+	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+	PBI_ADDR : out  std_logic_vector(15 downto 0);
+	
+	RAM_REQUEST : out std_logic;
+	ROM_REQUEST : out std_logic;
+	CART_REQUEST : out std_logic;
+	
+	CART_S4_n : out std_logic;
+	CART_S5_n : out std_logic;
+	CART_CCTL_n : out std_logic;
+	
+	-- width of access
+	WIDTH_8bit_ACCESS : out std_logic;
+	WIDTH_16bit_ACCESS : out std_logic;
+	WIDTH_32bit_ACCESS : out std_logic;
+	
+		-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+	SDRAM_WRITE_EN : out std_logic;
+	SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+	SDRAM_REFRESH : out std_logic;
+
+	SDRAM_REPLY : in std_logic; -- This matches the request once complete
+	SDRAM_DATA : in std_logic_vector(31 downto 0);
+	
+	WRITE_DATA : out std_logic_vector(31 downto 0)
+);
+
+END address_decoder;
+
+ARCHITECTURE vhdl OF address_decoder IS
+	signal ADDR_next : std_logic_vector(23 downto 0);
+	signal ADDR_reg : std_logic_vector(23 downto 0);
+
+	signal DATA_WRITE_next : std_logic_vector(31 downto 0);
+	signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
+	
+	signal width_8bit_next : std_logic;
+	signal width_16bit_next : std_logic;
+	signal width_32bit_next : std_logic;
+	signal write_enable_next : std_logic;
+
+	signal width_8bit_reg : std_logic;
+	signal width_16bit_reg : std_logic;
+	signal width_32bit_reg : std_logic;
+	signal write_enable_reg : std_logic;
+	
+	signal request_complete : std_logic;
+	signal notify_antic : std_logic;
+	signal notify_zpu : std_logic;
+	signal notify_cpu : std_logic;
+	signal start_request : std_logic;
+	
+	signal extended_access_cpu_or_antic : std_logic;
+	signal extended_access_antic : std_logic;
+	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+	
+	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+
+	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_idle : std_logic_vector(1 downto 0) := "00";
+	constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
+	constant state_waiting_zpu : std_logic_vector(1 downto 0) := "10";
+	constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
+		
+	signal ram_chip_select : std_logic;
+	signal sdram_chip_select : std_logic;
+	
+	signal sdram_request_next : std_logic;
+	signal sdram_request_reg : std_logic;
+	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+	
+	signal fetch_priority : std_logic_vector(2 downto 0);
+	
+BEGIN
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			addr_reg <= (others=>'0');
+			state_reg <= state_idle;
+			width_8bit_reg <= '0';
+			width_16bit_reg <= '0';
+			width_32bit_reg <= '0';
+			write_enable_reg <= '0';
+			data_write_reg <= (others=> '0');
+			sdram_request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			addr_reg <= addr_next;
+			state_reg <= state_next;
+			width_8bit_reg <= width_8bit_next;
+			width_16bit_reg <= width_16bit_next;
+			width_32bit_reg <= width_32bit_next;
+			write_enable_reg <= write_enable_next;
+			data_write_reg <= data_WRITE_next;
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+	
+	-- ANTIC FETCH
+	
+	-- concept
+	-- bus master sends request - antic or cpu
+	-- antic has priority
+	-- cpu may be idle
+	-- once request complete MEMORY_READY is set
+	-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
+	
+	-- so
+	-- memory_ready <= device_ready;
+	
+	-- problem
+	-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
+	
+	-- state machine
+	
+	-- state machine impl
+	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+	process(state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
+	begin
+		start_request <= '0';
+		notify_antic <= '0';
+		notify_cpu <= '0';
+		notify_zpu <= '0';
+		state_next <= state_reg;
+
+		addr_next <= addr_reg;
+		data_WRITE_next <= data_WRITE_reg;
+		width_8bit_next <= width_8bit_reg;		
+		width_16bit_next <= width_16bit_reg;		
+		width_32bit_next <= width_32bit_reg;		
+		write_enable_next <= write_enable_reg;
+		
+		case state_reg is
+			when state_idle =>
+				write_enable_next <= '0';
+				width_8bit_next <= '0';
+				width_16bit_next <= '0';
+				width_32bit_next <= '0';	
+				data_WRITE_next <= (others => '0');
+				addr_next <= zpu_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);				
+				
+				case fetch_priority is
+				when "100"|"101"|"110"|"111" => -- antic wins
+					start_request <= '1';
+					addr_next <= "00000000"&antic_ADDR;
+					width_8bit_next <= '1';					
+					if (request_complete = '1') then
+						notify_antic <= '1';
+					else
+						state_next <= state_waiting_antic;
+					end if;
+				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+					start_request <= '1';
+					addr_next <= zpu_ADDR;
+					data_WRITE_next <= zpu_wRITE_DATA;
+
+					width_8bit_next <= zpu_8BIT_WRITE_ENABLE;
+					width_16bit_next <= zpu_16BIT_WRITE_ENABLE;
+					width_32bit_next <= zpu_32BIT_WRITE_ENABLE or zpu_READ_ENABLE; -- narrower devices just return 8 bits on read
+					
+					write_enable_next <= not(zpu_READ_ENABLE);
+					
+					if (request_complete = '1') then
+						notify_zpu <= '1';
+					else
+						state_next <= state_waiting_zpu;
+					end if;					
+				when "001" => -- 6502 wins
+					start_request <= '1';
+					addr_next <= "00000000"&cpu_ADDR;
+					data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
+					width_8bit_next <= '1';
+					write_enable_next <= not(cpu_WRITE_N);
+					if (request_complete = '1') then
+						notify_cpu <= '1';
+					else
+						state_next <= state_waiting_cpu;
+					end if;
+				when "000" =>
+					-- no requests
+				end case;
+			when state_waiting_antic =>
+				if (request_complete = '1') then
+					notify_antic <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_zpu =>
+				if (request_complete = '1') then
+					notify_zpu <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_cpu =>
+				if (request_complete = '1') then
+					notify_cpu <= '1';
+					state_next <= state_idle;
+				end if;				
+		end case;
+	end process;
+	
+	-- output
+	MEMORY_READY_ANTIC <= notify_antic;
+	MEMORY_READY_ZPU <= notify_zpu;
+	MEMORY_READY_CPU <= notify_cpu;
+	
+	RAM_REQUEST <= ram_chip_select;
+		
+	SDRAM_REQUEST <= sdram_request_next;
+	SDRAM_REFRESH <= '0'; -- TODO, BROKEN! antic_refresh;
+	SDRAM_READ_EN <= not(write_enable_next);
+	SDRAM_WRITE_EN <= write_enable_next;
+	
+	WIDTH_8bit_ACCESS <= width_8bit_next;
+	WIDTH_16bit_ACCESS <= width_16bit_next;
+	WIDTH_32bit_ACCESS <= width_32bit_next;	
+	
+	WRITE_DATA <= DATA_WRITE_next;
+
+	-- a little sdram glue - move to sdram wrapper? TODO
+	SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+	sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+	
+	-- Calculate which memory area to use
+	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+	extended_access_antic <= (antic_fetch and not(portb(5)));
+	extended_access_cpu <= not(antic_fetch) and not(portb(4));
+	
+	extended_access_either <= not(portb(4));
+	
+  	process(
+		-- address and writing absolutely points us at a device
+		ADDR_next,WRITE_enable_next, 
+	
+		-- except for these additional special address bits	
+		portb, 
+		antic_fetch,
+		rom_select,
+		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
+		use_sdram,
+		
+		-- input data from n sources
+		GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
+		
+		-- input data from n sources complete?
+		-- hardware regs take 1 cycle, so always complete		
+		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+		
+		-- on new access this is set - we must select the appropriate device - for this cycle only
+		start_request
+	)
+	begin
+		MEMORY_DATA <= (others => '1');
+		
+		ROM_ADDR <= (others=>'0');
+		RAM_ADDR <= addr_next(18 downto 0);
+		SDRAM_ADDR <= addr_next(22 downto 0);
+		
+		PBI_ADDR <= ADDR_next(15 downto 0);
+		
+		request_complete <= '0';
+		
+		GTIA_WR_ENABLE <= '0';
+		POKEY_WR_ENABLE <= '0';
+		POKEY2_WR_ENABLE <= '0';
+		ANTIC_WR_ENABLE <= '0';
+		PIA_WR_ENABLE <= '0';
+		PIA_RD_ENABLE <= '0';
+		PBI_WR_ENABLE <= '0';
+
+		RAM_WR_ENABLE <= write_enable_next;
+		SDRAM_WRITE_EN <= write_enable_next;		
+		
+		CART_S4_n <= '1';
+		CART_S5_n <= '1';
+		CART_CCTL_n <= '1';
+		
+		rom_request <= '0';
+		cart_request <= '0';
+		
+		ram_chip_select <= '0';
+		sdram_chip_select <= '0';
+
+	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+		if (or_reduce(addr_next(23 downto 17)) = '0' ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+
+		RAM_ADDR(18 downto 16) <= "000";	
+		SDRAM_ADDR(22 downto 16) <= "0000000";
+	
+		case addr_next(15 downto 8) is 
+				-- GTIA
+				when X"D0" =>
+					GTIA_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+					request_complete <= '1';
+			
+				-- POKEY
+				when X"D2" =>				
+					if (addr_next(4) = '0') then
+						POKEY_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY_DATA;					
+					else
+						POKEY2_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
+					end if;
+					request_complete <= '1';
+
+				-- PIA
+				when X"D3" =>
+					PIA_WR_ENABLE <= write_enable_next;
+					PIA_RD_ENABLE <= '1';
+					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+					request_complete <= '1';
+					
+				-- ANTIC
+				when X"D4" =>
+					ANTIC_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+					request_complete <= '1';
+					
+				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+				when X"D5" =>
+					if ((CART_RD4 or CART_RD5) = '1') then
+						PBI_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_CCTL_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						MEMORY_DATA(7 downto 0) <= X"FF";
+						request_complete <= '1';
+					end if;
+					
+				-- XE RAM
+				when 
+					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+					
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+					
+					case ram_select is
+						when "00" => -- 64k
+							-- default
+						when "01" => -- 128k					
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+						when "10" => -- 320k compy shop
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+						when "11" => -- 320k rambo
+							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+					end case;
+					
+				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+				when 
+					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+									
+					if (portb(7) = '0' and portb(0) = '1') then
+						request_complete <= ROM_REQUEST_COMPLETE;
+						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						rom_request <= start_request;					
+						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+						end case;														
+					else				
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+						
+						case ram_select is
+							when "00" => -- 64k
+								-- default
+							when "01" => -- 128k					
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+							when "10" => -- 320k compy shop
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							when "11" => -- 320k rambo
+								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+						end case;
+					end if;
+				
+				-- 0x80 cart
+				when
+					X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
+					|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
+		
+					if (cart_rd4 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						rom_request <= start_request;
+						CART_S4_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;	
+			
+				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+				when 
+					X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
+					|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
+					
+					if (cart_rd5 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_S5_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (portb(1) = '0') then
+							request_complete <= ROM_REQUEST_COMPLETE;
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;
+							rom_request <= start_request;
+							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+						else
+							if (use_sdram = '1') then
+								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+								sdram_chip_select <= start_request;
+								request_complete <= sdram_request_COMPLETE;														
+							else
+								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+								ram_chip_select <= start_request;
+								request_complete <= ram_request_COMPLETE;									
+							end if;
+						end if;
+					end if;
+					
+				-- OS ROM 0xc00->0xcff				
+				-- OS ROM d800->0xfff
+				when 
+					X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
+					|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
+					|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
+					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+					
+					if (portb(0) = '1') then
+						request_complete <= ROM_REQUEST_COMPLETE;
+						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						rom_request <= start_request;
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+						end case;
+								
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;
+					
+				when others =>
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+			end case;				
+		else		
+			case addr_next(23 downto 21) is			
+				when "000" =>				
+					-- internal area for zpu, never happens!
+				when "001" => -- sram, 512K
+					MEMORY_DATA(15 downto 0) <= RAM_DATA;
+					ram_chip_select <= start_request;
+					request_complete <= ram_request_COMPLETE;									
+					RAM_ADDR <= addr_next(18 downto 0);
+
+				when "010"|"011" => -- flash rom, 4MB
+					request_complete <= ROM_REQUEST_COMPLETE;
+					MEMORY_DATA(7 downto 0) <= ROM_DATA;
+					rom_request <= start_request;
+					ROM_ADDR <= addr_next(21 downto 0);
+					
+				when "100"|"101"|"110"|"111" => -- sdram, 8MB
+					MEMORY_DATA <= SDRAM_DATA;
+					sdram_chip_select <= start_request;
+					request_complete <= sdram_request_COMPLETE;	
+					SDRAM_ADDR <= addr_next(22 downto 0);				
+			end case;
+		end if;
+		
+--		case addr_next(15 downto 0) is
+--			when X"FFFC" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"FFFD" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0600" => --JSR 0610
+--				MEMORY_DATA(7 downto 0) <= X"20";
+--			when X"0601" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0602" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0603" => --JMP
+--				MEMORY_DATA(7 downto 0) <= X"4C";
+--			when X"0604" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"0605" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
+--				MEMORY_DATA(7 downto 0) <= X"AD";
+--			when X"0611" =>
+--				MEMORY_DATA(7 downto 0) <= X"0A";
+--			when X"0612" =>
+--				MEMORY_DATA(7 downto 0) <= X"D2";
+--			when X"0613" =>
+--				MEMORY_DATA(7 downto 0) <= X"85";
+--			when X"0614" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0615" =>
+--				MEMORY_DATA(7 downto 0) <= X"44";
+--			when X"0616" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0617" =>
+--				MEMORY_DATA(7 downto 0) <= X"60";
+--			when others =>
+--		end case;
+			
+	end process;
+END vhdl;
Index: unmerged/core/mcc216/antic_dma_clock.vhdl
===================================================================
--- unmerged/core/mcc216/antic_dma_clock.vhdl	(nonexistent)
+++ unmerged/core/mcc216/antic_dma_clock.vhdl	(revision 1)
@@ -0,0 +1,74 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic_dma_clock IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	enable_dma : IN STD_LOGIC;
+	
+	playfield_start : in std_logic;
+	playfield_end : in std_logic;
+	vblank : in std_logic;
+	
+	slow_dma : in std_logic;
+	medium_dma : in std_logic;
+	fast_dma : in std_logic;
+	
+	dma_clock_out_0 : out std_logic;
+	dma_clock_out_1 : out std_logic;
+	dma_clock_out_2 : out std_logic;
+	dma_clock_out_3 : out std_logic
+);
+END antic_dma_clock;
+
+ARCHITECTURE vhdl OF antic_dma_clock IS
+	signal dma_shiftreg_next : std_logic_vector(7 downto 0);
+	signal dma_shiftreg_reg : std_logic_vector(7 downto 0);
+	
+	signal tick : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			dma_shiftreg_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			dma_shiftreg_reg <= dma_shiftreg_next;
+		end if;
+	end process;
+
+	-- next state
+	tick <=(dma_shiftreg_reg(0) and slow_dma) or (dma_shiftreg_reg(4) and medium_dma) or (dma_shiftreg_reg(6) and fast_dma);
+	process(enable_dma, dma_shiftreg_reg, playfield_start, playfield_end, vblank, slow_dma, medium_dma, fast_dma, tick)
+	begin
+		dma_shiftreg_next <= dma_shiftreg_reg;
+
+		if (enable_dma = '1') then			
+			dma_shiftreg_next <= 
+				not((playfield_start nor tick)
+				or playfield_end or vblank)				
+				&dma_shiftreg_reg(7 downto 1);
+		end if;
+		
+		if (playfield_start = '1') then
+			dma_shiftreg_next(7) <= not((playfield_start nor tick) or playfield_end or vblank);
+		end if;
+	end process;
+	
+	-- output
+	dma_clock_out_0 <= dma_shiftreg_reg(6) and enable_dma;
+	dma_clock_out_1 <= dma_shiftreg_reg(5) and enable_dma;
+	dma_clock_out_2 <= dma_shiftreg_reg(4) and enable_dma;
+	dma_clock_out_3 <= dma_shiftreg_reg(3) and enable_dma;
+	
+END vhdl;
Index: unmerged/core/mcc216/atari800core.qsf.bak
===================================================================
--- unmerged/core/mcc216/atari800core.qsf.bak	(nonexistent)
+++ unmerged/core/mcc216/atari800core.qsf.bak	(revision 1)
@@ -0,0 +1,584 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_V20 -to SD_CLK
+set_location_assignment PIN_Y20 -to SD_CMD
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_W20 -to SD_DATA
+set_location_assignment PIN_U20 -to SD_THREE
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name VHDL_FILE ledsw.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE dumprom.vhdl
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE nmigen.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE tvsync.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE flashrom.vhdl
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: unmerged/core/de1/zpu_ram.vhd
===================================================================
--- unmerged/core/de1/zpu_ram.vhd	(nonexistent)
+++ unmerged/core/de1/zpu_ram.vhd	(revision 1)
@@ -0,0 +1,181 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: zpu_ram.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY zpu_ram IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END zpu_ram;
+
+
+ARCHITECTURE SYN OF zpu_ram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 10,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		data_a => data,
+		wren_a => wren,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/de1/zpupkg.vhd
===================================================================
--- unmerged/core/de1/zpupkg.vhd	(nonexistent)
+++ unmerged/core/de1/zpupkg.vhd	(revision 1)
@@ -0,0 +1,292 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Package                                                         ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the package.              ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      zpupkg, UART (Package)                             ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpupkg is
+   constant OPCODE_W : integer:=8;
+
+   -- Debug structure, currently only for the trace module
+   type zpu_dbgo_t is record
+      b_inst : std_logic;
+      opcode : unsigned(OPCODE_W-1 downto 0);
+      pc     : unsigned(31 downto 0);
+      sp     : unsigned(31 downto 0);
+      stk_a  : unsigned(31 downto 0);
+      stk_b  : unsigned(31 downto 0);
+   end record;
+
+   component Trace is
+      generic(
+         LOG_FILE   : string:="trace.txt"; -- Name of the trace file
+         ADDR_W     : integer:=16;  -- Address width
+         WORD_SIZE  : integer:=32); -- 16/32
+      port(
+         clk_i      : in std_logic;
+         dbg_i      : in zpu_dbgo_t;
+         stop_i     : in std_logic;
+         busy_i     : in std_logic
+         );
+   end component Trace;
+
+   component ZPUSmallCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'); -- Value used to fill the unsused bits
+      port(
+         clk_i        : in  std_logic; -- System Clock
+         reset_i      : in  std_logic; -- Synchronous Reset
+         interrupt_i  : in  std_logic; -- Interrupt
+         break_o      : out std_logic; -- Breakpoint opcode executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- BRAM (text, data, bss and stack)
+         a_we_o       : out std_logic; -- BRAM A port Write Enable
+         a_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+         a_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+         a_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+         b_we_o       : out std_logic; -- BRAM B port Write Enable
+         b_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+         b_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+         b_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+         -- Memory mapped I/O
+         mem_busy_i   : in  std_logic;
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0);
+         data_o       : out unsigned(WORD_SIZE-1 downto 0);
+         addr_o       : out unsigned(ADDR_W-1 downto 0);
+         write_en_o   : out std_logic;
+         read_en_o    : out std_logic);
+   end component ZPUSmallCore;
+
+   component ZPUMediumCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+         MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+         BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+         ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+         ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+         ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+         ENA_LSHR     : boolean:=true;  -- lshiftright
+         ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+         FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+      port(
+         clk_i        : in  std_logic; -- CPU Clock
+         reset_i      : in  std_logic; -- Sync Reset
+         enable_i     : in  std_logic; -- Hold the CPU (after reset)
+         break_o      : out std_logic; -- Break instruction executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- Memory interface
+         mem_busy_i   : in  std_logic; -- Memory is busy
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+         data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+         addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+         write_en_o   : out std_logic;  -- Memory write enable
+         read_en_o    : out std_logic); -- Memory read enable
+   end component ZPUMediumCore;
+
+   component Timer is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned(0 downto 0);
+         data_o   : out unsigned(31 downto 0));
+   end component Timer;
+
+   component gpio is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         --
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned( 0 downto 0);
+         data_o   : out unsigned(31 downto 0);
+         --
+         port_in  : in  std_logic_vector(31 downto 0);
+         port_out : out std_logic_vector(31 downto 0);
+         port_dir : out std_logic_vector(31 downto 0)
+         );
+   end component gpio;
+
+
+   component ZPUPhiIO is
+      generic(
+         BRDIVISOR : positive:=1;   -- Baud rate divisor i.e. br_clk/9600/4
+         ENA_LOG   : boolean:=true; -- Enable log
+         LOG_FILE  : string:="log.txt"); -- Name for the log file
+      port(
+         clk_i      : in  std_logic; -- System Clock
+         reset_i    : in  std_logic; -- Synchronous Reset
+         busy_o     : out std_logic; -- I/O is busy
+         we_i       : in  std_logic; -- Write Enable
+         re_i       : in  std_logic; -- Read Enable
+         data_i     : in  unsigned(31 downto 0);
+         data_o     : out unsigned(31 downto 0);
+         addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+         --
+         rs232_rx_i : in  std_logic;  -- UART Rx input
+         rs232_tx_o : out std_logic;  -- UART Tx output
+         br_clk_i   : in  std_logic;  -- UART base clock (enable)
+         --
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)
+         );
+   end component ZPUPhiIO;
+
+   -- Opcode decode constants
+   -- Note: these are the basic opcodes, always implemented using hardware.
+   constant OPCODE_IM        : unsigned(7 downto 7):="1";
+   constant OPCODE_STORESP   : unsigned(7 downto 5):="010";
+   constant OPCODE_LOADSP    : unsigned(7 downto 5):="011";
+   constant OPCODE_EMULATE   : unsigned(7 downto 5):="001";
+   constant OPCODE_ADDSP     : unsigned(7 downto 4):="0001";
+   constant OPCODE_SHORT     : unsigned(7 downto 4):="0000";
+   
+   constant OPCODE_BREAK     : unsigned(3 downto 0):="0000";
+   constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
+   constant OPCODE_PUSHSP    : unsigned(3 downto 0):="0010";
+   constant OPCODE_PUSHINT   : unsigned(3 downto 0):="0011";
+   
+   constant OPCODE_POPPC     : unsigned(3 downto 0):="0100";
+   constant OPCODE_ADD       : unsigned(3 downto 0):="0101";
+   constant OPCODE_AND       : unsigned(3 downto 0):="0110";
+   constant OPCODE_OR        : unsigned(3 downto 0):="0111";
+   
+   constant OPCODE_LOAD      : unsigned(3 downto 0):="1000";
+   constant OPCODE_NOT       : unsigned(3 downto 0):="1001";
+   constant OPCODE_FLIP      : unsigned(3 downto 0):="1010";
+   constant OPCODE_NOP       : unsigned(3 downto 0):="1011";
+   
+   constant OPCODE_STORE     : unsigned(3 downto 0):="1100";
+   constant OPCODE_POPSP     : unsigned(3 downto 0):="1101";
+   constant OPCODE_COMPARE   : unsigned(3 downto 0):="1110";
+   constant OPCODE_POPINT    : unsigned(3 downto 0):="1111";
+
+   -- The following instructions are emulated in the small version and
+   -- implemented as hardware in the full version.
+   -- The constants correpond to the "emulated" instruction number.
+
+   -- Enabled by the ENA_LEVEL0 generic:
+   constant OPCODE_EQ               : unsigned(5 downto 0):=to_unsigned(46,6);
+   constant OPCODE_LOADB            : unsigned(5 downto 0):=to_unsigned(51,6);
+   constant OPCODE_NEQBRANCH        : unsigned(5 downto 0):=to_unsigned(56,6);
+   constant OPCODE_PUSHSPADD        : unsigned(5 downto 0):=to_unsigned(61,6);
+   -- Enabled by the ENA_LEVEL1 generic:
+   constant OPCODE_LESSTHAN         : unsigned(5 downto 0):=to_unsigned(36,6);
+   constant OPCODE_ULESSTHAN        : unsigned(5 downto 0):=to_unsigned(38,6);
+   constant OPCODE_MULT             : unsigned(5 downto 0):=to_unsigned(41,6);
+   constant OPCODE_STOREB           : unsigned(5 downto 0):=to_unsigned(52,6);
+   constant OPCODE_CALLPCREL        : unsigned(5 downto 0):=to_unsigned(63,6);
+   constant OPCODE_SUB              : unsigned(5 downto 0):=to_unsigned(49,6);
+   -- Enabled by the ENA_LEVEL2 generic:
+   constant OPCODE_LESSTHANOREQUAL  : unsigned(5 downto 0):=to_unsigned(37,6);
+   constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
+   constant OPCODE_CALL             : unsigned(5 downto 0):=to_unsigned(45,6);
+   constant OPCODE_POPPCREL         : unsigned(5 downto 0):=to_unsigned(57,6);
+   -- Enabled by the ENA_LSHR generic:
+   constant OPCODE_LSHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(42,6);
+   -- The following opcodes are always emulated.
+   constant OPCODE_LOADH            : unsigned(5 downto 0):=to_unsigned(34,6);
+   constant OPCODE_STOREH           : unsigned(5 downto 0):=to_unsigned(35,6);
+   constant OPCODE_ASHIFTLEFT       : unsigned(5 downto 0):=to_unsigned(43,6);
+   constant OPCODE_ASHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(44,6);
+   constant OPCODE_NEQ              : unsigned(5 downto 0):=to_unsigned(47,6);
+   constant OPCODE_NEG              : unsigned(5 downto 0):=to_unsigned(48,6);
+   constant OPCODE_XOR              : unsigned(5 downto 0):=to_unsigned(50,6);
+   constant OPCODE_DIV              : unsigned(5 downto 0):=to_unsigned(53,6);
+   constant OPCODE_MOD              : unsigned(5 downto 0):=to_unsigned(54,6);
+   constant OPCODE_EQBRANCH         : unsigned(5 downto 0):=to_unsigned(55,6);
+   constant OPCODE_CONFIG           : unsigned(5 downto 0):=to_unsigned(58,6);
+   constant OPCODE_PUSHPC           : unsigned(5 downto 0):=to_unsigned(59,6);
+end package zpupkg;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package UART is
+   ----------------------
+   -- Very simple UART --
+   ----------------------
+   component RxUnit is
+      port(
+         clk_i    : in  std_logic;  -- System clock signal
+         reset_i  : in  std_logic;  -- Reset input (sync)
+         enable_i : in  std_logic;  -- Enable input (rate*4)
+         read_i   : in  std_logic;  -- Received Byte Read
+         rxd_i    : in  std_logic;  -- RS-232 data input
+         rxav_o   : out std_logic;  -- Byte available
+         datao_o  : out std_logic_vector(7 downto 0)); -- Byte received
+   end component RxUnit;
+
+   component TxUnit is
+     port (
+        clk_i    : in  std_logic;  -- Clock signal
+        reset_i  : in  std_logic;  -- Reset input
+        enable_i : in  std_logic;  -- Enable input
+        load_i   : in  std_logic;  -- Load input
+        txd_o    : out std_logic;  -- RS-232 data output
+        busy_o   : out std_logic;  -- Tx Busy
+        datai_i  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
+   end component TxUnit;
+
+   component BRGen is
+     generic(
+        COUNT : integer range 0 to 65535);-- Count revolution
+     port (
+        clk_i   : in  std_logic;  -- Clock
+        reset_i : in  std_logic;  -- Reset input
+        ce_i    : in  std_logic;  -- Chip Enable
+        o_o     : out std_logic); -- Output
+   end component BRGen;
+end package UART;
+
Index: unmerged/core/mcc216/address_decoder.vhdl
===================================================================
--- unmerged/core/mcc216/address_decoder.vhdl	(nonexistent)
+++ unmerged/core/mcc216/address_decoder.vhdl	(revision 1)
@@ -0,0 +1,711 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+
+ENTITY address_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	-- bus masters - either CPU or antic
+	-- antic has priority and is slected when ANTIC_FETCH high
+	CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	CPU_FETCH : in std_logic;
+	CPU_WRITE_N : IN STD_LOGIC;
+	CPU_WRITE_DATA : in std_logic_vector(7 downto 0);	
+	
+	ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	ANTIC_FETCH : IN STD_LOGIC;
+	antic_refresh : in std_logic; -- use for sdram refresh (sdram needs more, but this is a start)
+
+	ZPU_ADDR : in std_logic_vector(23 downto 0);	
+	ZPU_FETCH : in std_logic;
+	ZPU_READ_ENABLE : in std_logic;
+	ZPU_32BIT_WRITE_ENABLE : in std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : in std_logic; -- for sram
+	ZPU_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs	
+	ZPU_WRITE_DATA : in std_logic_vector(31 downto 0);
+	
+	-- sources of data
+	ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	-- flash rom
+	GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
+	CART_ROM_DATA : in std_logic_Vector(7 downto 0);
+	
+	-- completion flags
+	RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+	ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+	CART_REQUEST_COMPLETE : IN STD_LOGIC;
+	
+	-- configuration options	
+	PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	reset_n : in std_logic;
+	
+	rom_select : in std_logic_vector(1 downto 0);
+	
+	ram_select : in std_logic_vector(1 downto 0);
+	
+	CART_RD4 : in std_logic;
+	CART_RD5 : in std_logic;
+	
+	use_sdram : in std_logic;
+		
+	-- Memory read mux output
+	MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
+	
+	-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
+	-- Allow us to say we're not ready for a cycle
+	MEMORY_READY_ANTIC : OUT STD_LOGIC;
+	MEMORY_READY_ZPU : OUT STD_LOGIC;
+	MEMORY_READY_CPU : out std_logic;	
+	
+	-- Each chip does not have whole address bus, so several are addressed at once
+	-- For reads not an issue, but for writes we need to only write to a single place!
+		-- these all take 1 cycle, so fine to leave device selected in general
+	GTIA_WR_ENABLE : OUT STD_LOGIC;
+	POKEY_WR_ENABLE : OUT STD_LOGIC;
+	POKEY2_WR_ENABLE : OUT STD_LOGIC;
+	ANTIC_WR_ENABLE : OUT STD_LOGIC;
+	PIA_WR_ENABLE : OUT STD_LOGIC;
+	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+	RAM_WR_ENABLE : OUT STD_LOGIC;	
+	PBI_WR_ENABLE : OUT STD_LOGIC;
+	
+	-- ROM and RAM have extended address busses to allow for bank switching etc.
+	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+	PBI_ADDR : out  std_logic_vector(15 downto 0);
+	
+	RAM_REQUEST : out std_logic;
+	ROM_REQUEST : out std_logic;
+	CART_REQUEST : out std_logic;
+	
+	CART_S4_n : out std_logic;
+	CART_S5_n : out std_logic;
+	CART_CCTL_n : out std_logic;
+	
+	-- width of access
+	WIDTH_8bit_ACCESS : out std_logic;
+	WIDTH_16bit_ACCESS : out std_logic;
+	WIDTH_32bit_ACCESS : out std_logic;
+	
+		-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+	SDRAM_WRITE_EN : out std_logic;
+	--SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+	SDRAM_REQUEST : out std_logic; -- Usual pattern
+	SDRAM_REFRESH : out std_logic;
+
+	--SDRAM_REPLY : in std_logic; -- This matches the request once complete
+	SDRAM_REQUEST_COMPLETE : in std_logic;
+	SDRAM_DATA : in std_logic_vector(31 downto 0);
+	
+	WRITE_DATA : out std_logic_vector(31 downto 0)
+);
+
+END address_decoder;
+
+ARCHITECTURE vhdl OF address_decoder IS
+	signal ADDR_next : std_logic_vector(23 downto 0);
+	signal ADDR_reg : std_logic_vector(23 downto 0);
+
+	signal DATA_WRITE_next : std_logic_vector(31 downto 0);
+	signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
+	
+	signal width_8bit_next : std_logic;
+	signal width_16bit_next : std_logic;
+	signal width_32bit_next : std_logic;
+	signal write_enable_next : std_logic;
+
+	signal width_8bit_reg : std_logic;
+	signal width_16bit_reg : std_logic;
+	signal width_32bit_reg : std_logic;
+	signal write_enable_reg : std_logic;
+	
+	signal request_complete : std_logic;
+	signal notify_antic : std_logic;
+	signal notify_zpu : std_logic;
+	signal notify_cpu : std_logic;
+	signal start_request : std_logic;
+	
+	signal extended_access_cpu_or_antic : std_logic;
+	signal extended_access_antic : std_logic;
+	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+	
+	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+
+	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_idle : std_logic_vector(1 downto 0) := "00";
+	constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
+	constant state_waiting_zpu : std_logic_vector(1 downto 0) := "10";
+	constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
+		
+	signal ram_chip_select : std_logic;
+	signal sdram_chip_select : std_logic;
+	
+--	signal sdram_request_next : std_logic;
+--	signal sdram_request_reg : std_logic;
+--	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+	
+	signal fetch_priority : std_logic_vector(2 downto 0);
+	
+	signal fetch_wait_next : std_logic_vector(8 downto 0);
+	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
+	
+BEGIN
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			addr_reg <= (others=>'0');
+			state_reg <= state_idle;
+			width_8bit_reg <= '0';
+			width_16bit_reg <= '0';
+			width_32bit_reg <= '0';
+			write_enable_reg <= '0';
+			data_write_reg <= (others=> '0');
+			--sdram_request_reg <= '0';
+			fetch_wait_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			addr_reg <= addr_next;
+			state_reg <= state_next;
+			width_8bit_reg <= width_8bit_next;
+			width_16bit_reg <= width_16bit_next;
+			width_32bit_reg <= width_32bit_next;
+			write_enable_reg <= write_enable_next;
+			data_write_reg <= data_WRITE_next;
+			--sdram_request_reg <= sdram_request_next;
+			fetch_wait_reg <= fetch_wait_next;
+		end if;
+	end process;
+	
+	-- ANTIC FETCH
+	
+	-- concept
+	-- bus master sends request - antic or cpu
+	-- antic has priority
+	-- cpu may be idle
+	-- once request complete MEMORY_READY is set
+	-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
+	
+	-- so
+	-- memory_ready <= device_ready;
+	
+	-- problem
+	-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
+	
+	-- state machine
+	
+	-- state machine impl
+	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
+	begin
+		start_request <= '0';
+		notify_antic <= '0';
+		notify_cpu <= '0';
+		notify_zpu <= '0';
+		state_next <= state_reg;
+		fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1);
+
+		addr_next <= addr_reg;
+		data_WRITE_next <= data_WRITE_reg;
+		width_8bit_next <= width_8bit_reg;		
+		width_16bit_next <= width_16bit_reg;		
+		width_32bit_next <= width_32bit_reg;		
+		write_enable_next <= write_enable_reg;
+		
+		case state_reg is
+			when state_idle =>
+				fetch_wait_next <= (others=>'0');
+				write_enable_next <= '0';
+				width_8bit_next <= '0';
+				width_16bit_next <= '0';
+				width_32bit_next <= '0';	
+				data_WRITE_next <= (others => '0');
+				addr_next <= zpu_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);				
+				
+				case fetch_priority is
+				when "100"|"101"|"110"|"111" => -- antic wins
+					start_request <= '1';
+					addr_next <= "00000000"&antic_ADDR;
+					width_8bit_next <= '1';					
+					if (request_complete = '1') then
+						notify_antic <= '1';
+					else
+						state_next <= state_waiting_antic;
+					end if;
+				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+					start_request <= '1';
+					addr_next <= zpu_ADDR;
+					data_WRITE_next <= zpu_wRITE_DATA;
+
+					width_8bit_next <= zpu_8BIT_WRITE_ENABLE or (zpu_READ_ENABLE and (zpu_addr(0) or zpu_addr(1)));
+					width_16bit_next <= zpu_16BIT_WRITE_ENABLE;
+					width_32bit_next <= zpu_32BIT_WRITE_ENABLE or (zpu_READ_ENABLE and not(zpu_addr(0) or zpu_addr(1))); -- narrower devices just return 8 bits on read
+					
+					write_enable_next <= not(zpu_READ_ENABLE);
+					
+					if (request_complete = '1') then
+						notify_zpu <= '1';
+					else
+						state_next <= state_waiting_zpu;
+					end if;					
+				when "001" => -- 6502 wins
+					start_request <= '1';
+					addr_next <= "00000000"&cpu_ADDR;
+					data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
+					width_8bit_next <= '1';
+					write_enable_next <= not(cpu_WRITE_N);
+					if (request_complete = '1') then
+						notify_cpu <= '1';
+					else
+						state_next <= state_waiting_cpu;
+					end if;
+				when "000" =>
+					-- no requests
+				end case;
+			when state_waiting_antic =>
+				if (request_complete = '1') then
+					notify_antic <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_zpu =>
+				if (request_complete = '1') then
+					notify_zpu <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_cpu =>
+				if (request_complete = '1') then
+					notify_cpu <= '1';
+					state_next <= state_idle;
+				end if;				
+		end case;
+	end process;
+	
+	-- output
+	MEMORY_READY_ANTIC <= notify_antic;
+	MEMORY_READY_ZPU <= notify_zpu;
+	MEMORY_READY_CPU <= notify_cpu;
+	
+	RAM_REQUEST <= ram_chip_select;
+		
+	SDRAM_REQUEST <= sdram_chip_select;
+	--SDRAM_REQUEST <= sdram_request_next;
+	SDRAM_REFRESH <= fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+	SDRAM_READ_EN <= not(write_enable_next);
+	SDRAM_WRITE_EN <= write_enable_next;
+	
+	WIDTH_8bit_ACCESS <= width_8bit_next;
+	WIDTH_16bit_ACCESS <= width_16bit_next;
+	WIDTH_32bit_ACCESS <= width_32bit_next;	
+	
+	WRITE_DATA <= DATA_WRITE_next;
+
+	-- a little sdram glue - move to sdram wrapper? TODO
+	--SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+	
+	-- Calculate which memory area to use
+	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+	extended_access_antic <= (antic_fetch and not(portb(5)));
+	extended_access_cpu <= not(antic_fetch) and not(portb(4));
+	
+	extended_access_either <= not(portb(4));
+	
+  	process(
+		-- address and writing absolutely points us at a device
+		ADDR_next,WRITE_enable_next, 
+	
+		-- except for these additional special address bits	
+		portb, 
+		antic_fetch,
+		rom_select,
+		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
+		use_sdram,
+		
+		-- input data from n sources
+		GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
+		CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_POKEY2_DATA,CACHE_ANTIC_DATA,
+		
+		-- input data from n sources complete?
+		-- hardware regs take 1 cycle, so always complete		
+		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+		
+		-- on new access this is set - we must select the appropriate device - for this cycle only
+		start_request
+	)
+	begin
+		MEMORY_DATA <= (others => '1');
+		
+		ROM_ADDR <= (others=>'0');
+		RAM_ADDR <= addr_next(18 downto 0);
+		SDRAM_ADDR <= addr_next(22 downto 0);
+		
+		PBI_ADDR <= ADDR_next(15 downto 0);
+		
+		request_complete <= '0';
+		
+		GTIA_WR_ENABLE <= '0';
+		POKEY_WR_ENABLE <= '0';
+		POKEY2_WR_ENABLE <= '0';
+		ANTIC_WR_ENABLE <= '0';
+		PIA_WR_ENABLE <= '0';
+		PIA_RD_ENABLE <= '0';
+		PBI_WR_ENABLE <= '0';
+
+		RAM_WR_ENABLE <= write_enable_next;
+		SDRAM_WRITE_EN <= write_enable_next;		
+		
+		CART_S4_n <= '1';
+		CART_S5_n <= '1';
+		CART_CCTL_n <= '1';
+		
+		rom_request <= '0';
+		cart_request <= '0';
+		
+		ram_chip_select <= '0';
+		sdram_chip_select <= '0';
+
+	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+		if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+
+		RAM_ADDR(18 downto 16) <= "000";	
+		SDRAM_ADDR(22 downto 16) <= "0000000";
+	
+		case addr_next(15 downto 8) is 
+				-- GTIA
+				when X"D0" =>
+					GTIA_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
+					request_complete <= '1';
+			
+				-- POKEY
+				when X"D2" =>				
+					if (addr_next(4) = '0') then
+						POKEY_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY_DATA;
+					else
+						POKEY2_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
+					end if;
+					request_complete <= '1';
+
+				-- PIA
+				when X"D3" =>
+					PIA_WR_ENABLE <= write_enable_next;
+					PIA_RD_ENABLE <= '1';
+					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+					request_complete <= '1';
+					
+				-- ANTIC
+				when X"D4" =>
+					ANTIC_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
+					request_complete <= '1';
+					
+				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+				when X"D5" =>
+					if ((CART_RD4 or CART_RD5) = '1') then
+						PBI_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_CCTL_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						MEMORY_DATA(7 downto 0) <= X"FF";
+						request_complete <= '1';
+					end if;
+					
+				-- XE RAM
+				when 
+					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+					
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+					
+					case ram_select is
+						when "00" => -- 64k
+							-- default
+						when "01" => -- 128k					
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+						when "10" => -- 320k compy shop
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+						when "11" => -- 320k rambo
+							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+					end case;
+					
+				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+				when 
+					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+									
+					if (portb(7) = '0' and portb(0) = '1') then
+						--request_complete <= ROM_REQUEST_COMPLETE;
+						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						--rom_request <= start_request;					
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						
+						if (write_enable_next = '1') then
+							request_complete <= '1';
+						else
+							request_complete <= sdram_request_COMPLETE;							
+							sdram_chip_select <= start_request;							
+						end if;
+						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+						    SDRAM_ADDR <="0010000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+							 SDRAM_ADDR <="0010000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k								
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+							 SDRAM_ADDR <="0010000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k							
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+							SDRAM_ADDR <= "0010001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)								
+						end case;														
+					else				
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+						
+						case ram_select is
+							when "00" => -- 64k
+								-- default
+							when "01" => -- 128k					
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+							when "10" => -- 320k compy shop
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							when "11" => -- 320k rambo
+								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+						end case;
+					end if;
+				
+				-- 0x80 cart
+				when
+					X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
+					|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
+		
+					if (cart_rd4 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						rom_request <= start_request;
+						CART_S4_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;	
+			
+				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+				when 
+					X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
+					|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
+					
+					if (cart_rd5 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_S5_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (portb(1) = '0') then
+							--request_complete <= ROM_REQUEST_COMPLETE;
+							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+							--rom_request <= start_request;					
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							if (write_enable_next = '1') then
+								request_complete <= '1';
+							else
+								request_complete <= sdram_request_COMPLETE;							
+								sdram_chip_select <= start_request;								
+							end if;
+						
+							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+						 SDRAM_ADDR <="0010000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k							
+						else
+							if (use_sdram = '1') then
+								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+								sdram_chip_select <= start_request;
+								request_complete <= sdram_request_COMPLETE;														
+							else
+								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+								ram_chip_select <= start_request;
+								request_complete <= ram_request_COMPLETE;									
+							end if;
+						end if;
+					end if;
+					
+				-- OS ROM 0xc00->0xcff				
+				-- OS ROM d800->0xfff
+				when 
+					X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
+					|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
+					|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
+					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+					
+					if (portb(0) = '1') then
+						--request_complete <= ROM_REQUEST_COMPLETE;
+						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						--rom_request <= start_request;					
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						if (write_enable_next = '1') then
+							request_complete <= '1';
+						else
+							request_complete <= sdram_request_COMPLETE;							
+							sdram_chip_select <= start_request;							
+						end if;																			
+
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+							SDRAM_ADDR <= "0010000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+							SDRAM_ADDR <= "0010000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+							SDRAM_ADDR <= "0010000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+							SDRAM_ADDR <= "0010001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+						end case;
+								
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;
+					
+				when others =>
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+			end case;				
+		else		
+			case addr_next(23 downto 21) is			
+				when "000" =>				
+					-- internal area for zpu, never happens!
+				when "001" => -- sram, 512K
+					MEMORY_DATA(15 downto 0) <= RAM_DATA;
+					ram_chip_select <= start_request;
+					request_complete <= ram_request_COMPLETE;									
+					RAM_ADDR <= addr_next(18 downto 0);
+
+				when "010"|"011" => -- flash rom, 4MB
+					request_complete <= ROM_REQUEST_COMPLETE;
+					MEMORY_DATA(7 downto 0) <= ROM_DATA;
+					rom_request <= start_request;
+					ROM_ADDR <= addr_next(21 downto 0);
+					
+				when "100"|"101"|"110"|"111" => -- sdram, 8MB
+					MEMORY_DATA <= SDRAM_DATA;
+					sdram_chip_select <= start_request;
+					request_complete <= sdram_request_COMPLETE;	
+					SDRAM_ADDR <= addr_next(22 downto 0);				
+			end case;
+		end if;
+		
+--		case addr_next(15 downto 0) is
+--			when X"FFFC" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"FFFD" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0600" => --JSR 0610
+--				MEMORY_DATA(7 downto 0) <= X"20";
+--			when X"0601" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0602" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0603" => --JMP
+--				MEMORY_DATA(7 downto 0) <= X"4C";
+--			when X"0604" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"0605" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
+--				MEMORY_DATA(7 downto 0) <= X"AD";
+--			when X"0611" =>
+--				MEMORY_DATA(7 downto 0) <= X"0A";
+--			when X"0612" =>
+--				MEMORY_DATA(7 downto 0) <= X"D2";
+--			when X"0613" =>
+--				MEMORY_DATA(7 downto 0) <= X"85";
+--			when X"0614" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0615" =>
+--				MEMORY_DATA(7 downto 0) <= X"44";
+--			when X"0616" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0617" =>
+--				MEMORY_DATA(7 downto 0) <= X"60";
+--			when others =>
+--		end case;
+			
+	end process;
+END vhdl;
Index: unmerged/core/mcc216/antic_counter.vhdl
===================================================================
--- unmerged/core/mcc216/antic_counter.vhdl	(nonexistent)
+++ unmerged/core/mcc216/antic_counter.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY antic_counter IS
+generic
+(
+	STORE_WIDTH : natural := 1;
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+);
+END antic_counter;
+
+ARCHITECTURE vhdl OF antic_counter IS
+	signal value_next : std_logic_vector(STORE_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(STORE_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= value_reg(STORE_WIDTH-1 downto COUNT_WIDTH)&std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: unmerged/core/mcc216/atari800core.qsf
===================================================================
--- unmerged/core/mcc216/atari800core.qsf	(nonexistent)
+++ unmerged/core/mcc216/atari800core.qsf	(revision 1)
@@ -0,0 +1,348 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_134 -to VGA_R[1]
+set_location_assignment PIN_133 -to VGA_R[2]
+set_location_assignment PIN_132 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_G[0]
+set_location_assignment PIN_142 -to VGA_G[1]
+set_location_assignment PIN_143 -to VGA_G[2]
+set_location_assignment PIN_144 -to VGA_G[3]
+set_location_assignment PIN_4 -to VGA_B[0]
+set_location_assignment PIN_7 -to VGA_B[1]
+set_location_assignment PIN_10 -to VGA_B[2]
+set_location_assignment PIN_11 -to VGA_B[3]
+set_location_assignment PIN_136 -to VGA_HS
+set_location_assignment PIN_137 -to VGA_VS
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_44 -to SD_CLK
+set_location_assignment PIN_46 -to SD_CMD
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_location_assignment PIN_28 -to AUDIO_L
+set_location_assignment PIN_30 -to AUDIO_R
+set_location_assignment PIN_53 -to CPU_RESET_n
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_127 -to JOY1_n[0]
+set_location_assignment PIN_91 -to JOY1_n[1]
+set_location_assignment PIN_90 -to JOY1_n[2]
+set_location_assignment PIN_88 -to JOY1_n[3]
+set_location_assignment PIN_89 -to JOY1_n[4]
+set_location_assignment PIN_126 -to JOY1_n[5]
+set_location_assignment PIN_128 -to JOY2_n[0]
+set_location_assignment PIN_25 -to JOY2_n[1]
+set_location_assignment PIN_24 -to JOY2_n[2]
+set_location_assignment PIN_22 -to JOY2_n[3]
+set_location_assignment PIN_23 -to JOY2_n[4]
+set_location_assignment PIN_129 -to JOY2_n[5]
+set_location_assignment PIN_33 -to PS2K_DAT
+set_location_assignment PIN_39 -to PS2K_CLK
+set_location_assignment PIN_32 -to PS2M_DAT
+set_location_assignment PIN_31 -to PS2M_CLK
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_49 -to SD_DAT3
+set_location_assignment PIN_42 -to USB_P
+set_location_assignment PIN_43 -to USB_N
+set_location_assignment PIN_50 -to USB2_P
+set_location_assignment PIN_51 -to USB2_N
+set_location_assignment PIN_112 -to SDRAM_CLK
+set_location_assignment PIN_61 -to SDRAM_A[0]
+set_location_assignment PIN_60 -to SDRAM_A[1]
+set_location_assignment PIN_59 -to SDRAM_A[2]
+set_location_assignment PIN_58 -to SDRAM_A[3]
+set_location_assignment PIN_125 -to SDRAM_A[4]
+set_location_assignment PIN_121 -to SDRAM_A[5]
+set_location_assignment PIN_120 -to SDRAM_A[6]
+set_location_assignment PIN_119 -to SDRAM_A[7]
+set_location_assignment PIN_115 -to SDRAM_A[8]
+set_location_assignment PIN_114 -to SDRAM_A[9]
+set_location_assignment PIN_64 -to SDRAM_A[10]
+set_location_assignment PIN_113 -to SDRAM_A[11]
+set_location_assignment PIN_111 -to SDRAM_A[12]
+set_location_assignment PIN_66 -to SDRAM_BA[0]
+set_location_assignment PIN_65 -to SDRAM_BA[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_79 -to SDRAM_DQ[5]
+set_location_assignment PIN_77 -to SDRAM_DQ[6]
+set_location_assignment PIN_76 -to SDRAM_DQ[7]
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_67 -to SDRAM_CS_n
+set_location_assignment PIN_68 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_CAS_n
+set_location_assignment PIN_71 -to SDRAM_WE_n
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_13 -to CFG_DIN
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
+set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_L
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to AUDIO_R
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CPU_RESET_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to FPGA_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY1_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to JOY2_n[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2K_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to PS2M_DAT
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_CMD
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT0
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SD_DAT3
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_P
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_P
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to USB2_N
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_A[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_BA[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[4]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[5]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[6]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[8]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[9]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[10]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[11]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[12]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[13]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[14]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQ[15]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_RAS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_CAS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_WE_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_HS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to VGA_VS
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CLK
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_CS_n
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DIN
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to CFG_DOUT
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_R
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_G
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_B
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_HS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to VGA_VS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_RAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CAS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_WE_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CLK
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_CS_n
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to CFG_DOUT
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to CFG_DIN
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[3]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[4]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[5]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[9]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_A[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[1]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[2]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[6]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[7]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[8]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[10]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[11]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[12]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[14]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_DQ[15]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_BA[0]
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_CS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_RAS_n
+set_instance_assignment -name CLOCK_TO_OUTPUT_DELAY 1 -to SDRAM_WE_n
+set_instance_assignment -name IO_MAXIMUM_TOGGLE_RATE "0 MHz" -to VGA_B[3]
+
+
+set_global_assignment -name VERILOG_FILE hq_dac.v
+set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+set_global_assignment -name VHDL_FILE romlo.vhd
+set_global_assignment -name VHDL_FILE romhi.vhd
+set_global_assignment -name VHDL_FILE ramint.vhd
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name VHDL_FILE internalromram.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: unmerged/core/de1/zpu_ram.qip
===================================================================
--- unmerged/core/de1/zpu_ram.qip	(nonexistent)
+++ unmerged/core/de1/zpu_ram.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_ram.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_ram.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_ram.cmp"]
Index: unmerged/core/de1/zpu_rom.vhd
===================================================================
--- unmerged/core/de1/zpu_rom.vhd	(nonexistent)
+++ unmerged/core/de1/zpu_rom.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: zpu_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY zpu_rom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END zpu_rom;
+
+
+ARCHITECTURE SYN OF zpu_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./zpu/HelloTinyROM_ROM.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 4096,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 12,
+		width_a => 32,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./zpu/HelloTinyROM_ROM.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./zpu/HelloTinyROM_ROM.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mcc216/PLLJ_PLLSPE_INFO.txt
===================================================================
--- unmerged/core/mcc216/PLLJ_PLLSPE_INFO.txt	(nonexistent)
+++ unmerged/core/mcc216/PLLJ_PLLSPE_INFO.txt	(revision 1)
@@ -0,0 +1,5 @@
+PLL_Name	pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
+PLLJITTER	NA
+PLLSPEmax	84
+PLLSPEmin	-53
+
Index: unmerged/core/mcc216/antic.vhdl.bak
===================================================================
--- unmerged/core/mcc216/antic.vhdl.bak	(nonexistent)
+++ unmerged/core/mcc216/antic.vhdl.bak	(revision 1)
@@ -0,0 +1,1820 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	MEMORY_READY_ANTIC : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	ANTIC_ENABLE_179 : IN std_logic;
+	
+	PAL : IN STD_LOGIC;
+	
+	lightpen : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	NMI_N_OUT : OUT std_logic;
+	ANTIC_READY : OUT std_logic; -- taken low by wsync writes
+	
+	-- GTIA interface
+	AN : OUT STD_LOGIC_VECTOR(2 downto 0);
+	COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
+	COLOUR_CLOCK_OUT : out std_logic;
+	HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
+	
+	-- DMA fetch
+	dma_fetch_out : out std_logic;
+	dma_address_out : out std_logic_vector(15 downto 0);
+	
+	-- refresh
+	refresh_out : out std_logic; -- used by sdram
+	
+	-- for debugging
+	dma_clock_out : out std_logic
+);
+END antic;
+
+ARCHITECTURE vhdl OF antic IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT antic_dma_clock IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		enable_dma : IN STD_LOGIC;
+		
+		playfield_start : in std_logic;
+		playfield_end : in std_logic;
+		vblank : in std_logic;
+		
+		slow_dma : in std_logic;
+		medium_dma : in std_logic;
+		fast_dma : in std_logic;
+				
+		dma_clock_out_0 : out std_logic;
+		dma_clock_out_1 : out std_logic;
+		dma_clock_out_2 : out std_logic;
+		dma_clock_out_3 : out std_logic
+	);
+	END component;
+	
+	component antic_counter IS
+	generic
+	(
+		STORE_WIDTH : natural := 1;
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+		
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;	
+
+	component reg_file IS
+	generic
+	(
+		BYTES : natural := 1;
+		WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal enable_dma : std_logic;
+	signal dma_clock_character_name : std_logic;
+	signal dma_clock_character_inc : std_logic;
+	signal dma_clock_bitmap_data : std_logic;
+	signal dma_clock_character_data : std_logic;
+	
+	signal wsync_next : std_logic;
+	signal wsync_reg : std_logic;
+	signal wsync_reset : std_logic;
+	signal wsync_write : std_logic;
+	signal wsync_delayed_write : std_logic;
+	
+	signal nmi_next : std_logic;
+	signal nmi_reg : std_logic;
+	
+	signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
+	signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
+	
+	signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
+	signal nmist_reg : std_logic_vector(7 downto 5);
+	
+	signal nmist_reset : std_logic;
+	
+	signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
+	signal nmien_raw_reg : std_logic_vector(7 downto 6);
+	signal nmien_delayed_reg : std_logic_vector(7 downto 6);
+	
+	signal dli_nmi_next : std_logic;
+	signal vbi_nmi_next : std_logic;
+	signal dli_nmi_reg : std_logic;
+	signal vbi_nmi_reg : std_logic;
+	
+	signal nmi_reset : std_logic;
+	--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
+	--signal nmi_pending_reg : std_logic;
+	
+	signal playfield_dma_start : std_logic;
+	signal playfield_dma_end : std_logic;
+	signal playfield_display_active_next : std_logic;
+	signal playfield_display_active_reg : std_logic;
+	
+	signal dmactl_raw_next : std_logic_vector(6 downto 0);
+	signal dmactl_raw_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_enabled : std_logic;
+	
+	signal chactl_next : std_logic_vector(2 downto 0);
+	signal chactl_reg : std_logic_vector(2 downto 0);
+	
+	-- dma is only allowed during certain portions of the display
+	signal allow_real_dma_next : std_logic;
+	signal allow_real_dma_reg : std_logic;
+	
+	-- dma fetch handling
+	-- dma is scheduled one cycle before it happens, so that registers can directly drive output	
+	signal dma_fetch_next : std_logic;
+	signal dma_fetch_reg : std_logic;
+	signal dma_address_next : std_logic_vector(15 downto 0);
+	signal dma_address_reg : std_logic_vector(15 downto 0);
+	
+	constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
+	constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
+	constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
+	constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
+	constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
+	constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
+	signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
+	signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
+	signal dma_fetch_request : std_logic;
+	
+	signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
+	signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
+	
+	signal character_next : std_logic_vector(7 downto 0);
+	signal character_reg : std_logic_vector(7 downto 0);
+
+	signal displayed_character_next : std_logic_vector(7 downto 0);
+	signal displayed_character_reg : std_logic_vector(7 downto 0);
+	
+	-- instruction decode
+	signal instruction_next : std_logic_vector(7 downto 0);
+	signal instruction_reg : std_logic_vector(7 downto 0);
+	
+	signal first_line_of_instruction_next : std_logic;
+	signal first_line_of_instruction_reg: std_logic;
+
+	signal last_line_of_instruction_live : std_logic;
+	signal last_line_of_instruction_next : std_logic;
+	signal last_line_of_instruction_reg: std_logic;
+	
+	signal instruction_blank_reg : std_logic;
+	signal instruction_blank_next : std_logic;
+
+	--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
+	--signal dma_speed_next : dma_speed_type;
+	--signal dma_speed_reg : dma_speed_type;
+	constant no_dma : std_logic_vector(1 downto 0) := "00";
+	constant slow_dma : std_logic_vector(1 downto 0) := "01";
+	constant medium_dma : std_logic_vector(1 downto 0) := "10";
+	constant fast_dma : std_logic_vector(1 downto 0) := "11";
+	signal dma_speed_next : std_logic_vector(1 downto 0);
+	signal dma_speed_reg : std_logic_vector(1 downto 0);
+	signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
+	
+	--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
+	--signal instruction_type_next : instruction_type;
+	--signal instruction_type_reg : instruction_type;
+	constant mode_character : std_logic_vector(2 downto 0) := "000";
+	constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
+	constant mode_jvb : std_logic_vector(2 downto 0) := "010";
+	constant mode_jump : std_logic_vector(2 downto 0) := "011";
+	constant mode_blank : std_logic_vector(2 downto 0) := "100";
+	signal instruction_type_next : std_logic_vector(2 downto 0);
+	signal instruction_type_reg : std_logic_vector(2 downto 0);
+	
+	signal two_part_instruction_next : std_logic;
+	signal two_part_instruction_reg : std_logic;
+
+		-- e.g. if instruction is 8 lines long then the final row is 7
+	signal instruction_final_row_next : std_logic_vector(3 downto 0);
+	signal instruction_final_row_reg : std_logic_vector(3 downto 0);
+		
+	--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
+	--signal shift_rate_next : shift_rate_type;
+	--signal shift_rate_reg : shift_rate_type;
+	constant slow_shift : std_logic_vector(1 downto 0) := "00";
+	constant medium_shift : std_logic_vector(1 downto 0) := "01";
+	constant fast_shift : std_logic_vector(1 downto 0) := "10";
+	signal shift_rate_next : std_logic_vector(1 downto 0);
+	signal shift_rate_reg : std_logic_vector(1 downto 0);
+	
+	signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
+	signal shift_twobit_reg : std_logic;
+	
+	signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
+	signal twopixel_reg : std_logic;	
+	
+	signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
+	signal single_colour_character_reg : std_logic;
+
+	signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
+	signal multi_colour_character_reg : std_logic;
+	
+	signal twoline_character_next : std_logic; -- for antic 5/7
+	signal twoline_character_reg : std_logic;
+	
+	signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
+	signal map_background_reg : std_logic;
+	
+	signal dli_enabled_next : std_logic;
+	signal dli_enabled_reg : std_logic;
+	
+	signal descenders_next : std_logic; -- for mode 3
+	signal descenders_reg : std_logic;
+		
+	-- Shift register used to output to AN2-AN0	
+	-- Can either be loaded from memory or from the line buffer
+	signal display_shift_next : std_logic_vector(7 downto 0);
+	signal display_shift_reg : std_logic_vector(7 downto 0);
+	
+	signal delay_display_shift_next : std_logic_vector(24 downto 0);
+	signal delay_display_shift_reg : std_logic_vector(24 downto 0);
+	
+	signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
+	
+	signal load_display_shift_from_memory : std_logic;
+	signal load_display_shift_from_line_buffer : std_logic;
+	
+	signal enable_shift : std_logic;
+	signal shiftclock_next : std_logic_vector(3 downto 0);
+	signal shiftclock_reg : std_logic_vector(3 downto 0);
+	
+	signal playfield_reset : std_logic;
+	signal playfield_load : std_logic;
+	
+	-- position in frame	
+	signal hcount_next : std_logic_vector(7 downto 0);
+	signal hcount_reg : std_logic_vector(7 downto 0);
+	
+	signal vcount_next : std_logic_vector(8 downto 0);
+	signal vcount_reg : std_logic_vector(8 downto 0);
+	
+	signal vblank_next : std_logic;
+	signal vblank_reg : std_logic;
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
+	
+	signal hcount_reset : std_logic;
+	signal vcount_reset : std_logic;
+	signal vcount_increment : std_logic;
+	
+	-- scrolling	
+	signal hscrol_reg : std_logic_vector(3 downto 0);
+	signal hscrol_next : std_logic_vector(3 downto 0);
+
+	signal vscrol_raw_reg : std_logic_vector(3 downto 0);
+	signal vscrol_raw_next : std_logic_vector(3 downto 0);
+	signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
+	
+	signal vscrol_enabled_reg : std_logic;
+	signal vscrol_enabled_next : std_logic;
+	signal vscrol_last_enabled_reg : std_logic;
+	signal vscrol_last_enabled_next : std_logic;
+	
+	signal update_row_count : std_logic;
+	
+	signal hscrol_enabled_reg : std_logic;
+	signal hscrol_enabled_next : std_logic;
+
+	-- refresh
+	signal refresh_pending_next : std_logic;
+	signal refresh_pending_reg : std_logic;
+
+	signal refresh_fetch_next : std_logic;
+	signal refresh_fetch_reg : std_logic;
+	
+	-- Counter signals
+	signal increment_display_list_address : std_logic;
+	signal load_display_list_address : std_logic;
+	signal display_list_address_next : std_logic_vector(15 downto 0);
+	signal display_list_address_reg : std_logic_vector(15 downto 0);
+	signal load_display_list_address_cpu : std_logic;
+	signal load_display_list_address_dma : std_logic;
+	signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
+	signal display_list_address_next_dma : std_logic_vector(15 downto 0);	
+
+	signal increment_memory_scan_address : std_logic;
+	signal load_memory_scan_address : std_logic;
+	signal memory_scan_address_next : std_logic_vector(15 downto 0);
+	signal memory_scan_address_reg : std_logic_vector(15 downto 0);
+
+	signal increment_line_buffer_address : std_logic;
+	signal load_line_buffer_address : std_logic;
+	signal line_buffer_address_next : std_logic_vector(7 downto 0);
+	signal line_buffer_address_reg : std_logic_vector(7 downto 0);
+
+	signal increment_row_count : std_logic;
+	signal load_row_count : std_logic;
+	signal row_count_next : std_logic_vector(3 downto 0);
+	signal row_count_reg : std_logic_vector(3 downto 0);
+
+	signal increment_refresh_count : std_logic;
+	signal load_refresh_count : std_logic;
+	signal refresh_count_next : std_logic_vector(3 downto 0);
+	signal refresh_count_reg : std_logic_vector(3 downto 0);
+	
+	signal pmbase_reg : std_logic_vector(7 downto 2);
+	signal pmbase_next : std_logic_vector(7 downto 2);
+
+	signal chbase_raw_reg : std_logic_vector(7 downto 1);
+	signal chbase_raw_next : std_logic_vector(7 downto 1);
+	signal chbase_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal line_buffer_write : std_logic;
+	signal line_buffer_data_in : std_logic_vector(7 downto 0);
+	signal line_buffer_data_out : std_logic_vector(7 downto 0);
+	
+	-- output registers
+	signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
+	signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
+	signal an_prev_reg : std_logic_vector(2 downto 0);  -- previous - for hscrol
+	signal an_next : std_logic_vector(2 downto 0);
+	signal an_reg : std_logic_vector(2 downto 0);
+	
+	-- light pendin
+	signal penv_next : std_logic_vector(7 downto 0);
+	signal penv_reg : std_logic_vector(7 downto 0);
+	signal penh_next : std_logic_vector(7 downto 0);
+	signal penh_reg : std_logic_vector(7 downto 0);
+	
+	-- high res modes
+	signal colour_clock_8x : std_logic;
+	signal colour_clock_4x : std_logic;
+	signal colour_clock_2x : std_logic;
+	signal colour_clock_1x : std_logic;
+	signal colour_clock_half_x : std_logic;
+	signal colour_clock_selected : std_logic;
+	signal colour_clock_selected_highres : std_logic;
+	
+	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
+	
+	constant cycle_length : integer := 32;	
+	
+	signal memory_ready_both : std_logic;
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			nmi_reg <= '0';
+			wsync_reg <= '0';
+			vcount_reg <= (others=>'0');
+			--hcount_reg <= X"01";
+			hcount_reg <= X"00";
+			dmactl_raw_reg <= (others=>'0');
+			chactl_reg <= (others=>'0');
+			vblank_reg <= '0';			
+			vsync_reg <= '0';
+			pmbase_reg <= (others=>'0');
+			allow_real_dma_reg <= '0';
+			display_shift_reg <= (others=>'0');
+			chbase_raw_reg <= (others=>'0');
+			
+			instruction_reg <= (others=>'0');
+			first_line_of_instruction_reg <= '0';
+			last_line_of_instruction_reg <= '0';
+			dma_speed_reg <= no_dma;
+			instruction_type_reg <= mode_blank;
+			instruction_final_row_reg <= (others=>'0');
+			shift_rate_reg <= slow_shift;
+			shift_twobit_reg <= '0';
+			twopixel_reg <= '0';
+			single_colour_character_reg <= '0';
+			multi_colour_character_reg <= '0';
+			twoline_character_reg <= '0';
+			map_background_reg <= '0';
+			dli_enabled_reg <= '0';
+			two_part_instruction_reg <= '0';
+			descenders_reg <='0';
+			
+			hscrol_reg <= (others=>'0');
+			vscrol_raw_reg <= (others=>'0');			
+			vscrol_enabled_reg <= '0';
+			vscrol_last_enabled_reg <= '0';
+			hscrol_enabled_reg <= '0';
+			
+			shiftclock_reg <= (others=>'0');
+			
+			hblank_reg <= '0';
+			
+			an_reg <= (others=>'0');
+			an_prev_reg <= (others=>'0');
+			
+			dma_fetch_reg <= '0';
+			dma_address_reg <= (others=>'0');			
+			dma_fetch_destination_reg <= dma_fetch_null;
+			
+			playfield_display_active_reg <= '0';
+			
+			instruction_blank_reg <= '0';
+			
+			display_list_address_low_temp_reg <= (others=>'0');
+			
+			character_reg <= (others=>'0');
+			displayed_character_reg <= (others=>'0');
+			
+			refresh_pending_reg <= '0';
+			refresh_fetch_reg <= '0';
+			
+			--nmi_pending_reg <= '0';
+			
+			dli_nmi_reg <= '0';
+			vbi_nmi_reg <= '0';
+			nmien_raw_reg <= (others=>'0');
+			
+			delay_display_shift_reg <= (others=>'0');
+			
+			nmi_shiftreg_reg <= (others=>'1');
+			
+			penh_reg <= (others=>'0');
+			penv_reg <= (others=>'0');
+			
+			colour_clock_count_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then			
+			nmi_reg <= nmi_next;
+			wsync_reg <= wsync_next;
+			vcount_reg <= vcount_next;
+			hcount_reg <= hcount_next;
+			nmist_reg <= nmist_next;
+			dmactl_raw_reg <= dmactl_raw_next;
+			chactl_reg <= chactl_next;
+			vblank_reg <= vblank_next;
+			vsync_reg <= vsync_next;
+			pmbase_reg <= pmbase_next;
+			allow_real_dma_reg <= allow_real_dma_next;
+			display_shift_reg <= display_shift_next;
+			chbase_raw_reg <= chbase_raw_next;
+			
+			instruction_reg <= instruction_next;
+			first_line_of_instruction_reg <= first_line_of_instruction_next;
+			last_line_of_instruction_reg <= last_line_of_instruction_next;
+			dma_speed_reg <= dma_speed_next;
+			instruction_type_reg <= instruction_type_next;
+			instruction_final_row_reg <= instruction_final_row_next;
+			shift_rate_reg <= shift_rate_next;
+			shift_twobit_reg <= shift_twobit_next;
+			twopixel_reg <= twopixel_next;
+			single_colour_character_reg <= single_colour_character_next;
+			multi_colour_character_reg <= multi_colour_character_next;
+			twoline_character_reg <= twoline_character_next;
+			map_background_reg <= map_background_next;
+			dli_enabled_reg <= dli_enabled_next;
+			two_part_instruction_reg <= two_part_instruction_next;
+			descenders_reg <= descenders_next;
+			
+			hscrol_reg <= hscrol_next;
+			vscrol_raw_reg <= vscrol_raw_next;	
+			vscrol_enabled_reg <= vscrol_enabled_next;
+			vscrol_last_enabled_reg <= vscrol_last_enabled_next;
+			hscrol_enabled_reg <= hscrol_enabled_next;
+			
+			shiftclock_reg <= shiftclock_next;
+			
+			hblank_reg <= hblank_next;
+			
+			an_reg <= an_next;
+			an_prev_reg <= an_prev_next;
+			
+			dma_fetch_reg <= dma_fetch_next;
+			dma_address_reg <= dma_address_next;
+			dma_fetch_destination_reg <= dma_fetch_destination_next;
+			
+			playfield_display_active_reg <= playfield_display_active_next;
+			
+			instruction_blank_reg <= instruction_blank_next;
+			
+			display_list_address_low_temp_reg <= display_list_address_low_temp_next;
+			
+			character_reg <= character_next;
+			displayed_character_reg <= displayed_character_next;
+			
+			refresh_pending_reg <= refresh_pending_next;
+			refresh_fetch_reg <= refresh_fetch_next;
+						
+			dli_nmi_reg <= dli_nmi_next;
+			vbi_nmi_reg <= vbi_nmi_next;
+			nmien_raw_reg <= nmien_raw_next;
+			
+			delay_display_shift_reg <= delay_display_shift_next;
+			
+			nmi_shiftreg_reg <= nmi_shiftreg_next;
+			
+			penh_reg <= penh_next;
+			penv_reg <= penv_next;
+			
+			colour_clock_count_reg <= colour_clock_count_next;
+		end if;
+	end process;
+	
+	-- Colour clock (3.57MHz for PAL)
+	-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
+	-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
+	--enable_colour_clock_div : enable_divider
+		--generic map (COUNT=>7)
+		--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);	
+	process(colour_clock_count_reg, ANTIC_ENABLE_179)		
+	begin
+		colour_clock_half_x <= '0';
+		colour_clock_1x<='0';
+		colour_clock_2x<='0';
+		colour_clock_4x<='0';
+		colour_clock_8x<='0';
+	
+		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+		
+		if (ANTIC_ENABLE_179 = '1') then -- resync...
+			colour_clock_count_next <= "00001";
+		end if;
+
+		colour_clock_8x <= '1';
+		
+		case colour_clock_count_reg(4 downto 0) is
+		when "00000" =>
+			colour_clock_half_x <= '1';
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "00100" =>
+			colour_clock_4x <= '1';
+		when "01000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "01100" =>
+			colour_clock_4x <= '1';
+		when "10000" =>			
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "10100" =>
+			colour_clock_4x <= '1';
+		when "11000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "11100" =>
+			colour_clock_4x <= '1';			
+		when others =>
+			-- nop
+		end case;
+	end process;
+	
+	process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
+	begin
+		enable_dma <= colour_clock_half_x;
+		colour_clock_selected <= colour_clock_1x;
+		colour_clock_selected_highres <= colour_clock_2x;		
+		dmactl_delayed_enabled <= '0';
+		
+		case dmactl_delayed_reg(6 downto 5) is
+		when "01" =>
+			dmactl_delayed_enabled <= '1';
+		when "10" =>
+			enable_dma <= colour_clock_1x;
+			colour_clock_selected <= colour_clock_2x;		
+			colour_clock_selected_highres <= colour_clock_4x;
+			dmactl_delayed_enabled <= '1';
+		when "11" =>
+			enable_dma <= colour_clock_2x;
+			colour_clock_selected <= colour_clock_4x;
+			colour_clock_selected_highres <= colour_clock_8x;
+			dmactl_delayed_enabled <= '1';
+		when others =>
+			--nop
+		end case;		
+	end process;	
+		
+	--enable_dma_clock_div : enable_divider
+	--	generic map (COUNT=>2)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>colour_clock_selected,enable_out=>enable_dma);		
+
+	-- Counters (memory address for data, memory address for display list)
+	antic_counter_memory_scan : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
+		
+	load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
+	display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
+	antic_counter_display_list : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
+	antic_counter_line_buffer : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
+	antic_counter_row_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
+	antic_counter_refresh_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
+	
+	-- Count position on screen
+	-- horizontal
+	process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
+	begin
+		hcount_next <= hcount_reg;		
+		if (colour_clock_1x = '1') then
+			hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
+			
+			if (colour_clock_half_x = '1') then
+				hcount_next(0) <= '1';
+			end if;
+		end if;
+		
+		if (hcount_reset = '1') then
+			hcount_next <= (others=>'0');
+		end if;
+	end process;
+	
+	-- vertical
+	process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
+	begin
+		vcount_next <= vcount_reg;
+		
+		if (colour_clock_1x = '1') then		
+			if (vcount_increment = '1') then
+				vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
+			end if;
+			
+			if (vcount_reset = '1') then
+				vcount_next <= (others=>'0');
+			end if;
+		end if;
+	end process;	
+	
+	-- Actions done based on vertical position		
+	process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
+	begin
+		vblank_next <= vblank_reg;
+		vsync_next <= vsync_reg;
+		vcount_reset <= '0';
+	
+		if (colour_clock_1x='1') then
+			case vcount_reg is
+				when '0'&X"08" => 
+					vblank_next <= '0';
+				when '0'&X"F8" =>
+					vblank_next <= '1';
+				--when '1'&X"05" => (changed for testing galaxian!)
+				--	vblank_next <= '1';					
+-- PAL
+				when '1'&X"16" =>
+					vsync_next <= pal;
+				when '1'&X"19" =>
+					vsync_next <= '0';
+				when '1'&X"38" =>
+					vcount_reset <= '1'; -- Blip at 9c..., then wrap
+-- NTSC
+				when '0'&X"FA" =>
+					vsync_next <= not(pal);
+				when '0'&X"FD" =>
+					vsync_next <= '0';
+				when '1'&X"06" =>
+					vcount_reset <= not(pal); -- Blip at 9c..., then wrap
+				when others =>
+					-- nothing
+			end case;
+		end if;
+	end process;
+	
+	-- Calculate playfield start/end
+	process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
+	begin		
+		playfield_dma_start_cycle <= (others=>'1');
+		playfield_dma_end_cycle <= (others=>'1');
+		playfield_display_start_cycle <= (others=>'1');
+		playfield_display_end_cycle <= (others=>'1');
+		
+		-- DMA clock start/end
+		-- wide=3, normal=2, narrow=1
+		-- Playfield start is at (in colour clocks):
+		-- 68 + hscrol&FE - width*16
+		-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
+		-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong... 
+		-- e.g. if its 64 then we may be able to do something like base&width&
+		-- Playfield end is at (in colour clocks):
+		-- 164 + hscrol&FE + width*16
+		-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
+		
+		-- hscrol interfers with playfield dma width (for dma purposes only!)
+		if (hscrol_enabled_reg='1') then
+			case dmactl_delayed_reg(1 downto 0) is
+				when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
+					playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20  (10 in machine cycles)
+					playfield_dma_end_cycle   <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
+				when "01" => -- narrow - traated as normal due to hscrol
+					playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36  (18 in machine cycles)
+					playfield_dma_end_cycle <=   X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
+				when others =>
+					-- nothing
+			end case;
+		else
+			case dmactl_delayed_reg(1 downto 0) is
+				when "11" => -- wide
+					playfield_dma_start_cycle <= X"11";
+					playfield_dma_end_cycle   <= X"D0";
+				when "10" => -- normal
+					playfield_dma_start_cycle <= X"21";
+					playfield_dma_end_cycle   <= X"C0";
+				when "01" => -- narrow
+					playfield_dma_start_cycle <= X"31";
+					playfield_dma_end_cycle <=   X"B0";
+				when others =>
+					-- nothing
+			end case;		
+		end if;
+
+		-- background colour outside this area...
+		-- TODO - review these locations - should be clear due to garbage!
+		case dmactl_delayed_reg(1 downto 0) is
+			when "11" => -- wide
+				playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
+				if (hscrol_reg > X"C") then
+					playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol				
+				end if;
+				playfield_display_end_cycle   <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
+			when "10" => -- normal
+				playfield_display_start_cycle <= X"2F";
+				playfield_display_end_cycle   <= X"CF";
+			when "01" => -- narrow
+				playfield_display_start_cycle <= X"3F";
+				playfield_display_end_cycle <=   X"BF";
+			when others =>
+				-- nothing
+		end case;				
+	end process;
+	
+	-- Actions done based on horizontal position - notably dma!
+	process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, displayed_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg)
+	begin
+		allow_real_dma_next <= allow_real_dma_reg;
+
+		playfield_dma_start <= '0';
+		playfield_dma_end <= '0';
+		playfield_display_active_next <= playfield_display_active_reg;
+		
+		dma_fetch_request <= '0';
+		dma_address_next <= dma_address_reg;
+		dma_fetch_destination_next <= dma_fetch_destination_reg;
+		
+		first_line_of_instruction_next <= first_line_of_instruction_reg;
+		last_line_of_instruction_next <= last_line_of_instruction_reg;
+		
+		load_display_shift_from_line_buffer <= '0';
+				
+		increment_memory_scan_address <= '0';
+		
+		line_buffer_address_next <= (others=>'0');
+		load_line_buffer_address <= '0';
+		increment_line_buffer_address <= '0';
+		
+		playfield_load <= '0';
+		
+		hblank_next <= hblank_reg;
+		hcount_reset <= '0';
+		
+		vcount_increment <= '0';
+		
+		character_next <= character_reg;
+		displayed_character_next <= displayed_character_reg;
+		
+		dli_nmi_next <= dli_nmi_reg;
+		vbi_nmi_next <= vbi_nmi_reg;
+		wsync_reset <= '0';
+		
+		load_refresh_count <= '0';
+		refresh_count_next <= (others=>'0');
+		
+		update_row_count <= '0'; 
+		vscrol_last_enabled_next <= vscrol_last_enabled_reg;
+	
+		if (colour_clock_1x = '1') then	
+			-- Playfield start/end
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
+				playfield_dma_start <= '1';				
+				load_line_buffer_address <= '1';
+			end if;
+			
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
+				playfield_dma_end <= '1';
+			end if;	
+			
+			if (hcount_reg = playfield_display_start_cycle) then
+				playfield_display_active_next <= '1';				
+			end if;
+			
+			if (hcount_reg = playfield_display_end_cycle) then
+				playfield_display_active_next <= '0';
+			end if;	
+
+			if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
+				if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
+					dma_fetch_request <= '1';
+				end if;				
+
+				if (twoline_character_reg='1') then
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				else
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				end if;
+				
+				displayed_character_next <= character_reg;
+				
+				-- TODO
+				-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.				
+				dma_fetch_destination_next <= dma_fetch_shiftreg;
+				
+				load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);								
+				increment_line_buffer_address <= '1';
+			end if;						
+		
+			case hcount_reg is 		
+				when X"00" => -- missile DMA, if missile or player DMA enabled					
+					dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;									
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"02" => -- display list dma if enabled
+					first_line_of_instruction_next <= '0';
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- suppress when waiting for vblank
+						first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
+					else				
+						if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
+							dma_fetch_request <= dmactl_delayed_enabled;
+							dma_address_next <= display_list_address_reg;
+							dma_fetch_destination_next <= dma_fetch_instruction;									
+							
+							first_line_of_instruction_next <= '1';						
+							
+							vscrol_last_enabled_next <= vscrol_enabled_reg;
+						end if;
+					end if;					
+				
+				when X"03" =>				
+					update_row_count <= '1'; -- done after instruction fetch...
+					
+				when X"04"|X"06"|X"08"|X"0A" =>  -- player DMA, if enabled
+					dma_fetch_request <= dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;	
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"0C" => -- lms lower byte dma if display list dma enabled?;
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_low;
+				
+				when X"0E" => -- lms upper byte dma if display list dma enabled?
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_high;
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
+						first_line_of_instruction_next <= '0';
+					end if;
+					
+					dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
+					if (vcount_reg = '0'&X"F8") then
+						vbi_nmi_next <= '1';
+					end if;
+					
+				when X"12" =>
+					dli_nmi_next <= '0';
+					vbi_nmi_next <= '0';
+
+				when X"21" =>
+					hblank_next <= '0';					
+					
+				when X"24" => 
+					playfield_load <= '1'; -- start the shift register
+					
+				when X"31" => -- start refresh					
+					load_refresh_count <= '1';
+					refresh_count_next <= (others=>'0');
+				
+				when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
+					wsync_reset <= '1';				
+			
+				when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
+					allow_real_dma_next <= '0';				
+					load_refresh_count <= '1';
+					refresh_count_next <= "1001";
+					
+				when X"D8" => -- vscrol value checked at cycle 108
+					last_line_of_instruction_next <= last_line_of_instruction_live;
+				
+				when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
+					vcount_increment <= '1';
+										
+				when X"DD" =>
+					hblank_next <= '1';					
+					
+				when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
+					hcount_reset <= '1';
+					allow_real_dma_next <= not(vblank_reg);
+				when others =>
+					-- nothing
+			end case;	
+			
+			-- Playfield DMA
+			if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
+				dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= first_line_of_instruction_reg;
+			end if;					
+			
+			if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
+				character_next <= line_buffer_data_out;
+				increment_line_buffer_address <= '1';
+			end if;
+			
+			if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data			
+				dma_fetch_request <= dmactl_delayed_enabled;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= '1';		
+			end if;
+			
+			if (vblank_reg = '1') then
+				dma_fetch_request <= '0';
+			end if;
+			
+			if (refresh_fetch_next = '1') then
+				dma_address_next <= (others=>'0');
+			end if;
+		
+		end if;
+	end process;
+	
+	-- refresh handling
+	process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, memory_ready_antic, allow_real_dma_next)
+	begin
+		increment_refresh_count <= '0';
+		refresh_pending_next <= refresh_pending_reg;
+		refresh_fetch_next <= not(memory_ready_antic) and refresh_fetch_reg;
+		
+		if (colour_clock_1x = '1') then
+			-- do pending refresh once we have a spare cycle
+			if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
+				refresh_fetch_next <= '1';		
+				refresh_pending_next <= '0';
+			end if;
+		
+			-- do scheduled refresh - if block, enable pending one
+			if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
+				increment_refresh_count <= '1';
+				refresh_fetch_next <= not(dma_fetch_next);
+				refresh_pending_next <= dma_fetch_next;
+			end if;
+		end if;
+	end process;
+	
+	-- nmi handling
+	-- edge senstive, single cycle is enough (unless cpu disabled or  clashes)
+	-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist...	which is the goal.	
+
+	nmien_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
+		
+	nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
+	
+	process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
+	begin	
+		nmist_next(5) <= '0';
+		nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
+		nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
+	end process;
+	
+	-- dma clock	
+	process(dma_speed_reg) -- XXX TODO - remove this process!
+	begin
+		slow_dma_s <= '0';
+		medium_dma_s <= '0';
+		fast_dma_s <= '0';
+		
+		case dma_speed_reg is
+			when no_dma =>
+				-- nothing
+			when slow_dma =>
+				slow_dma_s <= '1';
+			when medium_dma =>
+				medium_dma_s <= '1';
+			when fast_dma =>
+				fast_dma_s <= '1';
+		end case;
+	end process;
+	
+	antic_dma_clock1 : antic_dma_clock
+		port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
+
+	-- line buffer
+	reg_file1 : reg_file
+		generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
+		port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);		
+		--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
+		--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
+		
+	-- vertical scrolling
+	-- load row count from vscrol must be done at time of instruction load
+	-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
+	-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
+	vscrol_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>4)
+		port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));		
+	
+	process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count)
+	begin								
+		load_row_count <= '0';
+		row_count_next <= (others=>'0');
+		increment_row_count <= '0';
+		
+		last_line_of_instruction_live <= '0';		
+		
+		if (update_row_count = '1') then							
+			if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
+				row_count_next <= vscrol_delayed_reg;
+			end if;
+		
+			if (first_line_of_instruction_reg = '1') then
+				load_row_count <= '1';
+			else
+				increment_row_count <= '1';
+			end if;
+		end if;
+		
+		if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
+			if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
+				last_line_of_instruction_live <= '1';
+			end if;
+		else -- normal
+			if (row_count_reg = instruction_final_row_reg) then
+				last_line_of_instruction_live <= '1';
+			end if;
+		end if;
+		
+		if (vblank_reg = '1') then
+			last_line_of_instruction_live <= '1';
+		end if;
+						
+	end process;
+	
+	-- chbase 2 cycle delay
+	chbase_delay : wide_delay_line
+		generic map (COUNT=>cycle_length*2,WIDTH=>7)
+		port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
+		
+	-- decode instruction	
+	process(instruction_reg)
+	begin
+		dma_speed_next <= no_dma;
+		instruction_type_next <= mode_blank;
+		shift_rate_next <= slow_shift;
+		shift_twobit_next <= '0';
+		twopixel_next <= '0';
+		single_colour_character_next <= '0';		
+		multi_colour_character_next <= '0';		
+		twoline_character_next <= '0';
+		map_background_next <= '0';
+		instruction_final_row_next <= (others=>'0');
+		two_part_instruction_next <= instruction_reg(6);
+		instruction_blank_next <= '0';
+		vscrol_enabled_next <= instruction_reg(5);
+		hscrol_enabled_next <= instruction_reg(4);
+		dli_enabled_next <= instruction_reg(7);
+		descenders_next <= '0';		
+		
+		case instruction_reg(3 downto 0) is 			
+			when X"0" =>
+				instruction_type_next <= mode_blank;
+				instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
+				two_part_instruction_next <= '0';
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				
+			when X"1" =>
+				instruction_type_next <= mode_jump;
+				instruction_final_row_next <= (others=>'0');
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				two_part_instruction_next <= '1';
+				
+				if (instruction_reg(6) = '1') then
+					instruction_type_next <= mode_jvb;
+				end if;
+				
+			when X"2" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+			when X"3" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"9";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				descenders_next <= '1';
+				
+			when X"4" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				multi_colour_character_next <= '1';
+				
+			when X"5" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';	
+				twoline_character_next <= '1';		
+				multi_colour_character_next <= '1';
+				
+			when X"6" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				
+			when X"7" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				twoline_character_next <= '1';
+				
+			when X"8" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= slow_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"9" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"A" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"B" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"C" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"D" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"E" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"F" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+		end case;
+	end process;
+
+	-- dma fetching
+	process(dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,memory_ready_both,memory_data_in,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
+	begin	
+		instruction_next <= instruction_reg;
+		dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
+		
+		display_list_address_next_dma <= display_list_address_reg;
+		load_display_list_address_dma <= '0';
+		memory_scan_address_next <= memory_scan_address_reg;
+		load_memory_scan_address <= '0';
+		increment_display_list_address <= '0';
+		
+		load_display_shift_from_memory <= '0';
+		display_list_address_low_temp_next <= display_list_address_low_temp_reg;		
+		
+		line_buffer_data_in <= (others=>'0');
+		line_buffer_write <= '0';
+		
+		if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
+			instruction_next <= (others=>'0');
+		end if;
+	
+		if (dma_fetch_reg='1' and memory_ready_both='1') then
+			case dma_fetch_destination_reg is 
+				when dma_fetch_line_buffer =>
+					line_buffer_data_in <= memory_data_in;					
+					line_buffer_write <= '1';
+				when dma_fetch_shiftreg =>
+					load_display_shift_from_memory <= '1';
+				when dma_fetch_null =>
+					-- nothing (C/G/MTIA listens to bus)
+				when dma_fetch_instruction =>
+					instruction_next <= memory_data_in;
+					
+					increment_display_list_address <= '1';
+					
+				when dma_fetch_list_low =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						--display_list_address_next_dma(7 downto 0) <= memory_data_in; Changing this so soon messes up next dma cycle
+						display_list_address_low_temp_next <= memory_data_in;
+						increment_display_list_address <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(7 downto 0) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				when dma_fetch_list_high =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						 display_list_address_next_dma <= memory_data_in&display_list_address_low_temp_reg;
+						 load_display_list_address_dma <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(15 downto 8) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				
+				when others =>
+					-- nothing
+				
+			end case;
+
+			dma_fetch_next <= '0';
+		end if;
+	end process;
+	
+	-- shift reg clock
+	playfield_reset <= hblank_reg;
+	
+	process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
+	begin
+		shiftclock_next <= shiftclock_reg;
+		enable_shift <= '0';
+	
+		if (colour_clock_selected = '1') then
+		
+			shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
+			
+			if (playfield_load='1') then
+				shiftclock_next <= "1000";
+			end if;
+			
+			if (playfield_reset='1') then
+				shiftclock_next <= "0000";
+			end if;			
+			
+			--shiftclock_next(0) <= shiftclock_reg(1);
+			--shiftclock_next(1) <= shiftclock_reg(2);
+			--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
+			--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;						
+			case shift_rate_reg is
+				when slow_shift =>
+					enable_shift <= shiftclock_reg(0);
+				when medium_shift =>
+					enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
+				when fast_shift =>			
+					enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
+				when others =>
+					-- nothing
+			end case;			
+		end if;
+	end process;
+
+	-- shift reg
+	process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, memory_data_in, line_buffer_data_out)
+	begin
+		display_shift_next <= display_shift_reg;
+		
+		if (enable_shift = '1') then
+			if (shift_twobit_reg = '1') then
+				display_shift_next <= display_shift_reg(5 downto 0)&"00";
+			else
+				display_shift_next <= display_shift_reg(6 downto 0)&"0";
+			end if;			
+		end if;
+		
+		if (load_display_shift_from_memory = '1') then
+			display_shift_next(7 downto 0) <= memory_data_in;
+		end if;
+
+		if (load_display_shift_from_line_buffer = '1') then
+			display_shift_next(7 downto 0) <= line_buffer_data_out;
+		end if;
+		
+	end process;
+	
+	-- delay shift reg output for n cycles, so we can match AN with antic output
+	process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg)
+	begin
+		delay_display_shift_next <= delay_display_shift_reg;
+		
+		if (colour_clock_selected = '1') then
+			delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
+		end if;
+		
+	end process;
+	
+	-- ANO-2
+	-- XXX - clean up!	
+	-- first process - AN with no blanking	
+	process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
+	begin
+		an_current <= (others=>'0');
+		data_live <= (others=>'0');
+		if (shift_twobit_reg = '1') then				
+			an_current(0) <= delay_display_shift_reg(0);
+			an_current(1) <= delay_display_shift_reg(1);
+			an_current(2) <= '1';
+			
+			if (instruction_type_reg = mode_character) then							
+				data_live(0) <= delay_display_shift_reg(0);
+				data_live(1) <= delay_display_shift_reg(1);
+								
+				if (descenders_reg = '1') then					
+					if (delay_display_shift_reg(3 downto 2) = "11") then
+						if (unsigned(row_count_reg)<2) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					else
+						if (unsigned(row_count_reg)>=8) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					end if;
+				end if;	
+			
+				if (delay_display_shift_reg(4)='1') then -- inverse/hidden
+					if (chactl_reg(1)='1') then
+						an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
+						an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
+					else
+						an_current(0) <= data_live(0) and not(chactl_reg(0));
+						an_current(1) <= data_live(1) and not(chactl_reg(0));					
+					end if;
+				else
+					an_current(0) <= data_live(0);
+					an_current(1) <= data_live(1);				
+				end if;
+			end if;		
+
+			if (multi_colour_character_reg = '1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "11"&delay_display_shift_reg(4);										
+				end case;				
+			end if;
+			
+			if (map_background_reg='1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "110";										
+				end case;
+			end if;
+		else
+			if (single_colour_character_reg = '1') then
+				-- i.e. antic 6,7
+				if (delay_display_shift_reg(1) = '1') then
+					an_current(0) <= delay_display_shift_reg(3);
+					an_current(1) <= delay_display_shift_reg(4);
+					an_current(2) <= '1';					
+				else
+					an_current(0) <= '0';
+					an_current(1) <= '0';
+					an_current(2) <= '0';
+				end if;			
+			end if;
+			
+			if (map_background_reg='1') then
+				if (delay_display_shift_reg(1)='1') then
+					an_current <= "100";
+				else
+					an_current <= "000";										
+				end if;
+			end if;				
+		end if;		
+	end process;
+	
+	process(colour_clock_selected, an_current, an_prev_reg)
+	begin
+		an_prev_next <= an_prev_reg;
+		
+		if (colour_clock_selected = '1') then
+			an_prev_next <= an_current;
+		end if;
+	end process;
+	
+	process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
+	begin
+		an_next <= an_reg;
+	
+		if (colour_clock_selected = '1') then	
+			an_next <= an_current;
+			
+			if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
+				an_next <= an_prev_reg;
+			end if;
+			
+			if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
+				an_next <= "000";
+			end if;
+			
+			if (vblank_reg = '1' or hblank_reg = '1') then				
+				an_next(0) <= vsync_reg or twopixel_reg;
+				an_next(1) <= not(vsync_reg);
+				an_next(2) <= not(hblank_reg) and twopixel_reg;
+				
+				--an_next <= 
+						--(twopixel_reg and not(vsync_reg or hblank_reg))
+						--&((hblank_reg or vblank_reg) and not(vsync_reg))
+						--&(vsync_reg or twopixel_reg);
+			end if;			
+			
+			-- TODO this is too simplistic:
+			-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
+			-- + odd behaviour seen during high res bug
+
+		end if;
+		
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+
+	-- wsync write takes 1 cycle to assert rdy
+	-- TODO - revisit antic delays in terms of cpu cycles
+	wsync_delay : delay_line
+		generic map (COUNT=>cycle_length+cycle_length/2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
+
+	-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
+	--dmactl_delay : wide_delay_line
+	--	generic map (COUNT=>cycle_length,WIDTH=>6)
+	--	port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
+	dmactl_delayed_reg <= dmactl_raw_next;
+	--dmactl_delayed_reg <= dmactl_raw_reg;
+		
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
+	begin		
+		nmien_raw_next <= nmien_raw_reg;
+		dmactl_raw_next <= dmactl_raw_reg;
+		chactl_next <= chactl_reg;
+		hscrol_next <= hscrol_reg;
+		vscrol_raw_next <= vscrol_raw_reg;
+		chbase_raw_next <= chbase_raw_reg;
+		pmbase_next <= pmbase_reg;
+		wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
+		nmist_reset <= '0';
+		wsync_write <= '0';
+		
+		load_display_list_address_cpu <= '0';
+		display_list_address_next_cpu <= display_list_address_reg;
+	
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				dmactl_raw_next <= cpu_data_in(6 downto 0);
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				chactl_next <= cpu_data_in(2 downto 0);
+			end if;	
+			
+			if(addr_decoded(2) = '1') then
+				display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;		
+			
+			if(addr_decoded(3) = '1') then
+				display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;
+
+			if(addr_decoded(4) = '1') then
+				hscrol_next <= cpu_data_in(3 downto 0);
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				vscrol_raw_next <= cpu_data_in(3 downto 0);
+			end if;
+			
+			if(addr_decoded(7) = '1') then
+				pmbase_next <= cpu_data_in(7 downto 2);
+			end if;		
+			
+			if(addr_decoded(9) = '1') then
+				chbase_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+
+			if(addr_decoded(10) = '1') then
+				wsync_write <= '1';
+			end if;		
+	
+			if(addr_decoded(14) = '1') then
+				nmien_raw_next <= cpu_data_in(7 downto 6);
+			end if;
+		
+			if(addr_decoded(15) = '1') then
+				nmist_reset <= '1';
+			end if;		
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
+	begin
+		data_out <= X"FF";
+
+		if (addr_decoded(8) = '1') then -- HCOUNT :-)
+			data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
+		end if;
+		
+		if(addr_decoded(11) = '1') then --VCOUNT
+			data_out <= vcount_reg(8 downto 1);
+		end if;
+		
+		if (addr_decoded(12) = '1') then -- PENH
+			data_out <= penh_reg;
+		end if;
+		
+		if (addr_decoded(13) = '1') then -- PENV
+			data_out <= penv_reg;
+		end if;
+
+		if(addr_decoded(15) = '1') then --NMIST
+			data_out <= nmist_reg&"00000";
+		end if;
+		
+	end process;
+	
+	-- nmi delay
+	nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
+	
+	-- light pen
+	process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
+	begin
+		penv_next <= penv_reg;
+		penh_next <= penh_reg;
+		
+		if (lightpen = '0') then
+			penv_next <= vcount_reg(8 downto 1);
+			penh_next <= hcount_reg;
+		end if;
+	end process;
+	
+	-- Use CPU data if virtual dma
+	MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
+	
+	-- output
+	nmi_n_out <= nmi_shiftreg_reg(0);
+	
+	dma_clock_out<=dma_clock_character_name;
+	
+	AN <= an_reg;
+	
+	antic_ready <= not(wsync_reg);
+	
+	dma_fetch_out <= refresh_fetch_reg or (allow_real_dma_reg and dma_fetch_reg);
+	dma_address_out <= dma_address_reg;
+	
+	refresh_out <= refresh_fetch_reg;
+	
+	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+	COLOUR_CLOCK_OUT <= colour_clock_selected;
+	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
+	
+END vhdl;
+
Index: unmerged/core/mcc216/atari800core.qpf
===================================================================
--- unmerged/core/mcc216/atari800core.qpf	(nonexistent)
+++ unmerged/core/mcc216/atari800core.qpf	(revision 1)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: unmerged/core/mcc216/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/core/mcc216/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/core/mcc216/atari800core.sdc.bak
===================================================================
--- unmerged/core/mcc216/atari800core.sdc.bak	(nonexistent)
+++ unmerged/core/mcc216/atari800core.sdc.bak	(revision 1)
@@ -0,0 +1,2 @@
+create_clock -period 50MHz [get_ports CLOCK_50]
+derive_pll_clocks
\ No newline at end of file
Index: unmerged/core/mcc216/countdown_timer.vhdl
===================================================================
--- unmerged/core/mcc216/countdown_timer.vhdl	(nonexistent)
+++ unmerged/core/mcc216/countdown_timer.vhdl	(revision 1)
@@ -0,0 +1,102 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_countdown_timer IS
+generic(UNDERFLOW_DELAY : natural := 3);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	ENABLE_UNDERFLOW : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	WR_EN : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+	DATA_OUT : OUT STD_LOGIC
+);
+END pokey_countdown_timer;
+
+ARCHITECTURE vhdl OF pokey_countdown_timer IS
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal count_reg : std_logic_vector(7 downto 0);
+	signal count_next: std_logic_vector(7 downto 0);
+	
+	signal underflow : std_logic;
+	
+	signal count_command : std_logic_vector(1 downto 0);	
+	signal underflow_command: std_logic_vector(1 downto 0);	
+BEGIN
+	-- Instantiate delay (provides output)
+	underflow0_delay : delay_line
+		generic map (COUNT=>UNDERFLOW_DELAY)
+		port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+		end if;
+	end process;
+
+	-- count down on enable
+	process(count_reg,enable,wr_en,count_command,data_in)
+	begin	
+		count_command <= enable&wr_en;
+		case count_command is
+			when "10" =>
+				count_next <= std_logic_vector(unsigned(count_reg) -1);
+			when "01"|"11" =>
+				count_next <= data_in;
+			when others =>
+				count_next <= count_reg;
+		end case;
+	end process;
+		
+	-- underflow
+	process(count_reg,enable,underflow_command)
+	begin
+		underflow_command <= enable & To_Std_Logic(count_reg = X"00");
+		case underflow_command is
+			when "11" =>
+				underflow <= '1';
+			when others =>
+				underflow <= '0';
+		end case;
+	end process;
+		
+END vhdl;
Index: unmerged/core/mcc216/cpu_65xx_a.vhd.bak
===================================================================
--- unmerged/core/mcc216/cpu_65xx_a.vhd.bak	(nonexistent)
+++ unmerged/core/mcc216/cpu_65xx_a.vhd.bak	(revision 1)
@@ -0,0 +1,1599 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processNmi : std_logic := '0';
+	signal processIrq : std_logic := '0';
+	signal processInt : std_logic := '0';
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal so_reg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAX  & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluInp, -- AB iLXA imm
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal Creg: std_logic; -- Carry
+	signal Zreg: std_logic; -- Zero flag
+	signal Ireg: std_logic; -- Interrupt flag
+	signal Dreg: std_logic; -- Decimal mode
+	signal Vreg: std_logic; -- Overflow
+	signal Nreg: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := Creg & aluInput;
+		when aluModeP =>
+			rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
+		when aluModeInc =>
+			rmwBits := Creg & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := Creg & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & Creg;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := Creg & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if Dreg = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if Dreg = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if Dreg = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if Dreg = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then -- and (halt = '0') then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+					
+					if theCpuCycle = cycleStack4 -- MWW
+					or reset = '1' then
+						nmiReg <= '1';
+					end if;					
+				if halt = '0' then
+					if theCpuCycle /= cycleBranchTaken then
+						-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+						-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+						processNmi <= not (nmiReg or opcInfo(opcIRQ));
+						processIrq <= not (irqReg or opcInfo(opcIRQ));
+					end if;
+				end if;
+			end if;
+			processInt <= processNmi or (processIrq and (not Ireg));
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, d, reset, processInt)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := d;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processInt = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processInt = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, halt, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if (enable = '1') and (halt = '0') then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= d;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= d;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= d;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					Creg <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Zreg <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					Ireg <= aluInput(2);
+				end if;
+			end if;
+			-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
+			if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
+				if (theOpcode = X"58") then
+					Ireg <= '0';
+				end if;
+				if (theOpcode = X"78") then
+					Ireg <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					Dreg <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					Vreg <= aluV;
+				end if;
+			end if;
+			if so_reg = '1' and so_n = '0' then
+				Vreg <= '1';
+			end if;
+			so_reg <= so_n;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					Nreg <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if (enable = '1') and (halt = '0') then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					q <= T; -- Read-modify-write write old value first.
+					doReg <= d; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	q <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+				if reset = '1' then
+					theWe <= '0';
+				end if;
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else
+							PC <= myAddr;
+						end if;
+					end if;
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when opcodeFetch =>
+			if processInt = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else
+				nextAddr <= nextAddrAbsIndexed;
+			end if;
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then
+				halt_dly <= halt;
+			end if;
+			if (enable = '1') and (halt = '0') then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
+--				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= d & T;
+				when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & d;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+			if (enable = '1') and (halt_dly = '0') then
+				case nextAddr is
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
+					else myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
+
+end architecture;
+
+
Index: unmerged/core/mcc216/flashrom.vhdl
===================================================================
--- unmerged/core/mcc216/flashrom.vhdl	(nonexistent)
+++ unmerged/core/mcc216/flashrom.vhdl	(revision 1)
@@ -0,0 +1,63 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY flashrom IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+
+	ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+	
+	REQUEST : IN STD_LOGIC;
+
+	-- takes 90+ns, wait states handled here
+	
+	-- Flash interface
+	FLASH_D : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	FLASH_CE_N : OUT STD_LOGIC;
+	FLASH_OE_N : OUT STD_LOGIC;
+	FLASH_WE_N : OUT STD_LOGIC;
+	FLASH_RESET_N : OUT STD_LOGIC;
+	FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	COMPLETE : OUT STD_LOGIC
+);
+
+END flashrom;
+
+ARCHITECTURE vhdl OF flashrom IS
+	signal complete_next : std_logic_vector(4 downto 0); --56MHZ, 17ns per cycle.
+	signal complete_reg : std_logic_vector(4 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			complete_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			complete_reg <= complete_next;
+		end if;
+	end process;
+	
+	complete_next <= request&complete_reg(complete_reg'left downto 1);
+
+	FLASH_CE_N <= '0';
+	FLASH_OE_N <= '0';
+	FLASH_WE_N <= '1';
+	FLASH_RESET_N <= RESET_N;
+	FLASH_ADDRESS <= ADDRESS;
+	
+	DOUT <= FLASH_D;
+	COMPLETE <= complete_reg(0);
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/gtia_player.vhdl
===================================================================
--- unmerged/core/mcc216/gtia_player.vhdl	(nonexistent)
+++ unmerged/core/mcc216/gtia_player.vhdl	(revision 1)
@@ -0,0 +1,108 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_player IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : in std_logic;
+	
+	COLOUR_ENABLE : IN STD_LOGIC;
+	LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+	PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+	SIZE : in std_logic_vector(1 downto 0);
+	bitmap : in std_logic_vector(7 downto 0);
+	
+	output : out std_logic
+);
+END gtia_player;
+
+ARCHITECTURE vhdl OF gtia_player IS
+
+	-- pmgs
+	signal shift_next : std_logic_vector(7 downto 0);
+	signal shift_reg : std_logic_vector(7 downto 0);
+	signal count_next : std_logic_vector(1 downto 0);
+	signal count_reg : std_logic_vector(1 downto 0);
+begin
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= (others=>'0');
+			count_reg <= (others=>'0');		
+		elsif (clk'event and clk='1') then										
+			shift_reg <= shift_next;
+			count_reg <= count_next;
+		end if;
+	end process;
+	
+	
+	process(shift_next,COLOUR_ENABLE, live_position, player_position, size, bitmap, shift_reg, count_reg)
+	begin
+		-- size is 2 bits (00 normal, 01 twice, 10 normal(bugged), 11 four times)
+		-- grafp0 is 8 bits of data (2 bits for missiles)
+		-- hposp0_reg is position - 0x30 is left side of normal playfield, 0xd0 is right size of normal playfield
+		
+		-- 'or' into shift register, so if not empty we get extra pixels
+		
+		-- counter before we shift	
+		
+		shift_next <= shift_reg;
+		count_next <= count_reg;
+		
+		output <= shift_next(7);
+		
+		if (COLOUR_ENABLE = '1') then								
+			case size is 
+				when "00" => -- normal size
+					count_next <= "00";
+					shift_next <= shift_reg(6 downto 0) &'0';
+				when "10" => -- normal size (with bug)
+					case count_reg is
+						when "00"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "01"|"10" =>
+							count_next <= "10";						
+					end case;					
+				when "01" =>					
+					case count_reg is
+						when "01"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "00"|"10" =>
+							count_next <= "01";							
+					end case;					
+
+				when "11" =>
+					case count_reg is
+						when "00" =>
+							count_next <= "01";
+						when "01" =>
+							count_next <= "10";						
+						when "10" =>
+							count_next <= "11";
+						when "11" =>
+							shift_next <= shift_reg(6 downto 0) &'0';
+							count_next <= "00";
+					end case;
+			end case;	
+
+			if (live_position = player_position) then
+				shift_next <= shift_reg(6 downto 0) &'0' or bitmap;
+				count_next <= (others=>'0');
+			end if;			
+		end if;
+		
+	end process;
+	
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/atari800core.sdc
===================================================================
--- unmerged/core/mcc216/atari800core.sdc	(nonexistent)
+++ unmerged/core/mcc216/atari800core.sdc	(revision 1)
@@ -0,0 +1,3 @@
+create_clock -period 5MHz [get_ports FPGA_CLK]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: unmerged/core/mcc216/complete_address_decoder.vhdl
===================================================================
--- unmerged/core/mcc216/complete_address_decoder.vhdl	(nonexistent)
+++ unmerged/core/mcc216/complete_address_decoder.vhdl	(revision 1)
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);	
+	
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END complete_address_decoder;
+
+--ARCHITECTURE vhdl OF complete_address_decoder IS
+--BEGIN
+--	comp_gen:
+--	for i in 0 to ((2**width)-1) generate
+--		addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
+--	end generate;
+--end vhdl;
+
+architecture tree of complete_address_decoder is
+	constant STAGE : natural:=width;
+	type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
+	signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
+	signal a: std_logic_vector(width-1 downto 0) ;
+begin
+	a<=addr_in;
+	process(a,p)
+	begin
+		p(stage,0) <= '1';
+		
+		for s in stage downto 1 loop
+			for r in 0 to (2**(stage-s)-1) loop
+				p(s-1,2*r) <= (not a(s-1)) and p(s,r);
+				p(s-1,2*r+1) <= a(s-1) and p(s,r);
+			end loop;
+		end loop;
+		
+		for i in  0 to (2**stage-1) loop
+			addr_decoded(i) <= p(0,i);
+		end loop;
+	end process;
+end tree;
\ No newline at end of file
Index: unmerged/core/mcc216/cpu_65xx_a.vhd
===================================================================
--- unmerged/core/mcc216/cpu_65xx_a.vhd	(nonexistent)
+++ unmerged/core/mcc216/cpu_65xx_a.vhd	(revision 1)
@@ -0,0 +1,1599 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processNmi : std_logic := '0';
+	signal processIrq : std_logic := '0';
+	signal processInt : std_logic := '0';
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal so_reg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAX  & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal Creg: std_logic; -- Carry
+	signal Zreg: std_logic; -- Zero flag
+	signal Ireg: std_logic; -- Interrupt flag
+	signal Dreg: std_logic; -- Decimal mode
+	signal Vreg: std_logic; -- Overflow
+	signal Nreg: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := Creg & aluInput;
+		when aluModeP =>
+			rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
+		when aluModeInc =>
+			rmwBits := Creg & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := Creg & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & Creg;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := Creg & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if Dreg = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if Dreg = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if Dreg = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if Dreg = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then -- and (halt = '0') then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+					
+					if theCpuCycle = cycleStack4 -- MWW
+					or reset = '1' then
+						nmiReg <= '1';
+					end if;					
+				if halt = '0' then
+					if theCpuCycle /= cycleBranchTaken then
+						-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+						-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+						processNmi <= not (nmiReg or opcInfo(opcIRQ));
+						processIrq <= not (irqReg or opcInfo(opcIRQ));
+					end if;
+				end if;
+			end if;
+			processInt <= processNmi or (processIrq and (not Ireg));
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, d, reset, processInt)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := d;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processInt = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processInt = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, halt, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if (enable = '1') and (halt = '0') then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= d;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= d;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= d;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					Creg <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Zreg <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					Ireg <= aluInput(2);
+				end if;
+			end if;
+			-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
+			if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
+				if (theOpcode = X"58") then
+					Ireg <= '0';
+				end if;
+				if (theOpcode = X"78") then
+					Ireg <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					Dreg <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					Vreg <= aluV;
+				end if;
+			end if;
+			if so_reg = '1' and so_n = '0' then
+				Vreg <= '1';
+			end if;
+			so_reg <= so_n;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					Nreg <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if (enable = '1') and (halt = '0') then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					q <= T; -- Read-modify-write write old value first.
+					doReg <= d; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	q <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+				if reset = '1' then
+					theWe <= '0';
+				end if;
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else
+							PC <= myAddr;
+						end if;
+					end if;
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when opcodeFetch =>
+			if processInt = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else
+				nextAddr <= nextAddrAbsIndexed;
+			end if;
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then
+				halt_dly <= halt;
+			end if;
+			if (enable = '1') and (halt = '0') then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
+--				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= d & T;
+				when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & d;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+			if (enable = '1') and (halt_dly = '0') then
+				case nextAddr is
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
+					else myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
+
+end architecture;
+
+
Index: unmerged/core/mcc216/enable_divider.vhdl
===================================================================
--- unmerged/core/mcc216/enable_divider.vhdl	(nonexistent)
+++ unmerged/core/mcc216/enable_divider.vhdl	(revision 1)
@@ -0,0 +1,76 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY enable_divider IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END enable_divider;
+
+ARCHITECTURE vhdl OF enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: unmerged/core/mcc216/gtia_palette.vhdl
===================================================================
--- unmerged/core/mcc216/gtia_palette.vhdl	(nonexistent)
+++ unmerged/core/mcc216/gtia_palette.vhdl	(revision 1)
@@ -0,0 +1,2092 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_palette IS
+PORT 
+( 
+	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+);
+END gtia_palette;
+
+ARCHITECTURE altirra OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+				when X"00" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"01" =>
+					R_next <= X"11";
+					G_next <= X"11";
+					B_next <= X"11";
+				when X"02" =>
+					R_next <= X"22";
+					G_next <= X"22";
+					B_next <= X"22";
+				when X"03" =>
+					R_next <= X"33";
+					G_next <= X"33";
+					B_next <= X"33";
+				when X"04" =>
+					R_next <= X"44";
+					G_next <= X"44";
+					B_next <= X"44";
+				when X"05" =>
+					R_next <= X"55";
+					G_next <= X"55";
+					B_next <= X"55";
+				when X"06" =>
+					R_next <= X"66";
+					G_next <= X"66";
+					B_next <= X"66";
+				when X"07" =>
+					R_next <= X"77";
+					G_next <= X"77";
+					B_next <= X"77";
+				when X"08" =>
+					R_next <= X"88";
+					G_next <= X"88";
+					B_next <= X"88";
+				when X"09" =>
+					R_next <= X"99";
+					G_next <= X"99";
+					B_next <= X"99";
+				when X"0a" =>
+					R_next <= X"aa";
+					G_next <= X"aa";
+					B_next <= X"aa";
+				when X"0b" =>
+					R_next <= X"bb";
+					G_next <= X"bb";
+					B_next <= X"bb";
+				when X"0c" =>
+					R_next <= X"cc";
+					G_next <= X"cc";
+					B_next <= X"cc";
+				when X"0d" =>
+					R_next <= X"dd";
+					G_next <= X"dd";
+					B_next <= X"dd";
+				when X"0e" =>
+					R_next <= X"ee";
+					G_next <= X"ee";
+					B_next <= X"ee";
+				when X"0f" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"10" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"11" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"12" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"13" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"14" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"15" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"16" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"17" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"18" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"19" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"1a" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"1b" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"1c" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"1d" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"1e" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"1f" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+				when X"20" =>
+					R_next <= X"50";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"21" =>
+					R_next <= X"61";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"22" =>
+					R_next <= X"72";
+					G_next <= X"03";
+					B_next <= X"00";
+				when X"23" =>
+					R_next <= X"83";
+					G_next <= X"14";
+					B_next <= X"03";
+				when X"24" =>
+					R_next <= X"94";
+					G_next <= X"25";
+					B_next <= X"14";
+				when X"25" =>
+					R_next <= X"a5";
+					G_next <= X"36";
+					B_next <= X"25";
+				when X"26" =>
+					R_next <= X"b6";
+					G_next <= X"47";
+					B_next <= X"36";
+				when X"27" =>
+					R_next <= X"c7";
+					G_next <= X"58";
+					B_next <= X"47";
+				when X"28" =>
+					R_next <= X"d8";
+					G_next <= X"69";
+					B_next <= X"58";
+				when X"29" =>
+					R_next <= X"e9";
+					G_next <= X"7a";
+					B_next <= X"69";
+				when X"2a" =>
+					R_next <= X"fa";
+					G_next <= X"8b";
+					B_next <= X"7a";
+				when X"2b" =>
+					R_next <= X"ff";
+					G_next <= X"9c";
+					B_next <= X"8b";
+				when X"2c" =>
+					R_next <= X"ff";
+					G_next <= X"ad";
+					B_next <= X"9c";
+				when X"2d" =>
+					R_next <= X"ff";
+					G_next <= X"be";
+					B_next <= X"ad";
+				when X"2e" =>
+					R_next <= X"ff";
+					G_next <= X"cf";
+					B_next <= X"be";
+				when X"2f" =>
+					R_next <= X"ff";
+					G_next <= X"e0";
+					B_next <= X"cf";
+				when X"30" =>
+					R_next <= X"54";
+					G_next <= X"00";
+					B_next <= X"03";
+				when X"31" =>
+					R_next <= X"65";
+					G_next <= X"00";
+					B_next <= X"14";
+				when X"32" =>
+					R_next <= X"76";
+					G_next <= X"00";
+					B_next <= X"25";
+				when X"33" =>
+					R_next <= X"87";
+					G_next <= X"08";
+					B_next <= X"36";
+				when X"34" =>
+					R_next <= X"98";
+					G_next <= X"19";
+					B_next <= X"47";
+				when X"35" =>
+					R_next <= X"a9";
+					G_next <= X"2a";
+					B_next <= X"58";
+				when X"36" =>
+					R_next <= X"ba";
+					G_next <= X"3b";
+					B_next <= X"69";
+				when X"37" =>
+					R_next <= X"cb";
+					G_next <= X"4c";
+					B_next <= X"7a";
+				when X"38" =>
+					R_next <= X"dc";
+					G_next <= X"5d";
+					B_next <= X"8b";
+				when X"39" =>
+					R_next <= X"ed";
+					G_next <= X"6e";
+					B_next <= X"9c";
+				when X"3a" =>
+					R_next <= X"fe";
+					G_next <= X"7f";
+					B_next <= X"ad";
+				when X"3b" =>
+					R_next <= X"ff";
+					G_next <= X"90";
+					B_next <= X"be";
+				when X"3c" =>
+					R_next <= X"ff";
+					G_next <= X"a1";
+					B_next <= X"cf";
+				when X"3d" =>
+					R_next <= X"ff";
+					G_next <= X"b2";
+					B_next <= X"e0";
+				when X"3e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"f1";
+				when X"3f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"40" =>
+					R_next <= X"4f";
+					G_next <= X"00";
+					B_next <= X"35";
+				when X"41" =>
+					R_next <= X"60";
+					G_next <= X"00";
+					B_next <= X"46";
+				when X"42" =>
+					R_next <= X"71";
+					G_next <= X"00";
+					B_next <= X"57";
+				when X"43" =>
+					R_next <= X"82";
+					G_next <= X"01";
+					B_next <= X"68";
+				when X"44" =>
+					R_next <= X"93";
+					G_next <= X"12";
+					B_next <= X"79";
+				when X"45" =>
+					R_next <= X"a4";
+					G_next <= X"23";
+					B_next <= X"8a";
+				when X"46" =>
+					R_next <= X"b5";
+					G_next <= X"34";
+					B_next <= X"9b";
+				when X"47" =>
+					R_next <= X"c6";
+					G_next <= X"45";
+					B_next <= X"ac";
+				when X"48" =>
+					R_next <= X"d7";
+					G_next <= X"56";
+					B_next <= X"bd";
+				when X"49" =>
+					R_next <= X"e8";
+					G_next <= X"67";
+					B_next <= X"ce";
+				when X"4a" =>
+					R_next <= X"f9";
+					G_next <= X"78";
+					B_next <= X"df";
+				when X"4b" =>
+					R_next <= X"ff";
+					G_next <= X"89";
+					B_next <= X"f0";
+				when X"4c" =>
+					R_next <= X"ff";
+					G_next <= X"9a";
+					B_next <= X"ff";
+				when X"4d" =>
+					R_next <= X"ff";
+					G_next <= X"ab";
+					B_next <= X"ff";
+				when X"4e" =>
+					R_next <= X"ff";
+					G_next <= X"bc";
+					B_next <= X"ff";
+				when X"4f" =>
+					R_next <= X"ff";
+					G_next <= X"cd";
+					B_next <= X"ff";
+				when X"50" =>
+					R_next <= X"3d";
+					G_next <= X"00";
+					B_next <= X"68";
+				when X"51" =>
+					R_next <= X"4e";
+					G_next <= X"00";
+					B_next <= X"79";
+				when X"52" =>
+					R_next <= X"5f";
+					G_next <= X"00";
+					B_next <= X"8a";
+				when X"53" =>
+					R_next <= X"70";
+					G_next <= X"00";
+					B_next <= X"9b";
+				when X"54" =>
+					R_next <= X"81";
+					G_next <= X"11";
+					B_next <= X"ac";
+				when X"55" =>
+					R_next <= X"92";
+					G_next <= X"22";
+					B_next <= X"bd";
+				when X"56" =>
+					R_next <= X"a3";
+					G_next <= X"33";
+					B_next <= X"ce";
+				when X"57" =>
+					R_next <= X"b4";
+					G_next <= X"44";
+					B_next <= X"df";
+				when X"58" =>
+					R_next <= X"c5";
+					G_next <= X"55";
+					B_next <= X"f0";
+				when X"59" =>
+					R_next <= X"d6";
+					G_next <= X"66";
+					B_next <= X"ff";
+				when X"5a" =>
+					R_next <= X"e7";
+					G_next <= X"77";
+					B_next <= X"ff";
+				when X"5b" =>
+					R_next <= X"f8";
+					G_next <= X"88";
+					B_next <= X"ff";
+				when X"5c" =>
+					R_next <= X"ff";
+					G_next <= X"99";
+					B_next <= X"ff";
+				when X"5d" =>
+					R_next <= X"ff";
+					G_next <= X"aa";
+					B_next <= X"ff";
+				when X"5e" =>
+					R_next <= X"ff";
+					G_next <= X"bb";
+					B_next <= X"ff";
+				when X"5f" =>
+					R_next <= X"ff";
+					G_next <= X"cc";
+					B_next <= X"ff";
+				when X"60" =>
+					R_next <= X"20";
+					G_next <= X"00";
+					B_next <= X"8b";
+				when X"61" =>
+					R_next <= X"31";
+					G_next <= X"00";
+					B_next <= X"9c";
+				when X"62" =>
+					R_next <= X"42";
+					G_next <= X"00";
+					B_next <= X"ad";
+				when X"63" =>
+					R_next <= X"53";
+					G_next <= X"08";
+					B_next <= X"be";
+				when X"64" =>
+					R_next <= X"64";
+					G_next <= X"19";
+					B_next <= X"cf";
+				when X"65" =>
+					R_next <= X"75";
+					G_next <= X"2a";
+					B_next <= X"e0";
+				when X"66" =>
+					R_next <= X"86";
+					G_next <= X"3b";
+					B_next <= X"f1";
+				when X"67" =>
+					R_next <= X"97";
+					G_next <= X"4c";
+					B_next <= X"ff";
+				when X"68" =>
+					R_next <= X"a8";
+					G_next <= X"5d";
+					B_next <= X"ff";
+				when X"69" =>
+					R_next <= X"b9";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"6a" =>
+					R_next <= X"ca";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"6b" =>
+					R_next <= X"db";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"6c" =>
+					R_next <= X"ec";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"6d" =>
+					R_next <= X"fd";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"6e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"6f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"70" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"89";
+				when X"71" =>
+					R_next <= X"00";
+					G_next <= X"08";
+					B_next <= X"9a";
+				when X"72" =>
+					R_next <= X"00";
+					G_next <= X"19";
+					B_next <= X"ab";
+				when X"73" =>
+					R_next <= X"10";
+					G_next <= X"2a";
+					B_next <= X"bc";
+				when X"74" =>
+					R_next <= X"21";
+					G_next <= X"3b";
+					B_next <= X"cd";
+				when X"75" =>
+					R_next <= X"32";
+					G_next <= X"4c";
+					B_next <= X"de";
+				when X"76" =>
+					R_next <= X"43";
+					G_next <= X"5d";
+					B_next <= X"ef";
+				when X"77" =>
+					R_next <= X"54";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"78" =>
+					R_next <= X"65";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"79" =>
+					R_next <= X"76";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"7a" =>
+					R_next <= X"87";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"7b" =>
+					R_next <= X"98";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"7c" =>
+					R_next <= X"a9";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"7d" =>
+					R_next <= X"ba";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"7e" =>
+					R_next <= X"cb";
+					G_next <= X"e5";
+					B_next <= X"ff";
+				when X"7f" =>
+					R_next <= X"dc";
+					G_next <= X"f6";
+					B_next <= X"ff";
+				when X"80" =>
+					R_next <= X"00";
+					G_next <= X"0c";
+					B_next <= X"65";
+				when X"81" =>
+					R_next <= X"00";
+					G_next <= X"1d";
+					B_next <= X"76";
+				when X"82" =>
+					R_next <= X"00";
+					G_next <= X"2e";
+					B_next <= X"87";
+				when X"83" =>
+					R_next <= X"00";
+					G_next <= X"3f";
+					B_next <= X"98";
+				when X"84" =>
+					R_next <= X"05";
+					G_next <= X"50";
+					B_next <= X"a9";
+				when X"85" =>
+					R_next <= X"16";
+					G_next <= X"61";
+					B_next <= X"ba";
+				when X"86" =>
+					R_next <= X"27";
+					G_next <= X"72";
+					B_next <= X"cb";
+				when X"87" =>
+					R_next <= X"38";
+					G_next <= X"83";
+					B_next <= X"dc";
+				when X"88" =>
+					R_next <= X"49";
+					G_next <= X"94";
+					B_next <= X"ed";
+				when X"89" =>
+					R_next <= X"5a";
+					G_next <= X"a5";
+					B_next <= X"fe";
+				when X"8a" =>
+					R_next <= X"6b";
+					G_next <= X"b6";
+					B_next <= X"ff";
+				when X"8b" =>
+					R_next <= X"7c";
+					G_next <= X"c7";
+					B_next <= X"ff";
+				when X"8c" =>
+					R_next <= X"8d";
+					G_next <= X"d8";
+					B_next <= X"ff";
+				when X"8d" =>
+					R_next <= X"9e";
+					G_next <= X"e9";
+					B_next <= X"ff";
+				when X"8e" =>
+					R_next <= X"af";
+					G_next <= X"fa";
+					B_next <= X"ff";
+				when X"8f" =>
+					R_next <= X"c0";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"90" =>
+					R_next <= X"00";
+					G_next <= X"1f";
+					B_next <= X"30";
+				when X"91" =>
+					R_next <= X"00";
+					G_next <= X"30";
+					B_next <= X"41";
+				when X"92" =>
+					R_next <= X"00";
+					G_next <= X"41";
+					B_next <= X"52";
+				when X"93" =>
+					R_next <= X"00";
+					G_next <= X"52";
+					B_next <= X"63";
+				when X"94" =>
+					R_next <= X"00";
+					G_next <= X"63";
+					B_next <= X"74";
+				when X"95" =>
+					R_next <= X"05";
+					G_next <= X"74";
+					B_next <= X"85";
+				when X"96" =>
+					R_next <= X"16";
+					G_next <= X"85";
+					B_next <= X"96";
+				when X"97" =>
+					R_next <= X"27";
+					G_next <= X"96";
+					B_next <= X"a7";
+				when X"98" =>
+					R_next <= X"38";
+					G_next <= X"a7";
+					B_next <= X"b8";
+				when X"99" =>
+					R_next <= X"49";
+					G_next <= X"b8";
+					B_next <= X"c9";
+				when X"9a" =>
+					R_next <= X"5a";
+					G_next <= X"c9";
+					B_next <= X"da";
+				when X"9b" =>
+					R_next <= X"6b";
+					G_next <= X"da";
+					B_next <= X"eb";
+				when X"9c" =>
+					R_next <= X"7c";
+					G_next <= X"eb";
+					B_next <= X"fc";
+				when X"9d" =>
+					R_next <= X"8d";
+					G_next <= X"fc";
+					B_next <= X"ff";
+				when X"9e" =>
+					R_next <= X"9e";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"9f" =>
+					R_next <= X"af";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"a0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"a1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"0e";
+				when X"a2" =>
+					R_next <= X"00";
+					G_next <= X"4d";
+					B_next <= X"1f";
+				when X"a3" =>
+					R_next <= X"00";
+					G_next <= X"5e";
+					B_next <= X"30";
+				when X"a4" =>
+					R_next <= X"00";
+					G_next <= X"6f";
+					B_next <= X"41";
+				when X"a5" =>
+					R_next <= X"01";
+					G_next <= X"80";
+					B_next <= X"52";
+				when X"a6" =>
+					R_next <= X"12";
+					G_next <= X"91";
+					B_next <= X"63";
+				when X"a7" =>
+					R_next <= X"23";
+					G_next <= X"a2";
+					B_next <= X"74";
+				when X"a8" =>
+					R_next <= X"34";
+					G_next <= X"b3";
+					B_next <= X"85";
+				when X"a9" =>
+					R_next <= X"45";
+					G_next <= X"c4";
+					B_next <= X"96";
+				when X"aa" =>
+					R_next <= X"56";
+					G_next <= X"d5";
+					B_next <= X"a7";
+				when X"ab" =>
+					R_next <= X"67";
+					G_next <= X"e6";
+					B_next <= X"b8";
+				when X"ac" =>
+					R_next <= X"78";
+					G_next <= X"f7";
+					B_next <= X"c9";
+				when X"ad" =>
+					R_next <= X"89";
+					G_next <= X"ff";
+					B_next <= X"da";
+				when X"ae" =>
+					R_next <= X"9a";
+					G_next <= X"ff";
+					B_next <= X"eb";
+				when X"af" =>
+					R_next <= X"ab";
+					G_next <= X"ff";
+					B_next <= X"fc";
+				when X"b0" =>
+					R_next <= X"00";
+					G_next <= X"33";
+					B_next <= X"00";
+				when X"b1" =>
+					R_next <= X"00";
+					G_next <= X"44";
+					B_next <= X"00";
+				when X"b2" =>
+					R_next <= X"00";
+					G_next <= X"55";
+					B_next <= X"00";
+				when X"b3" =>
+					R_next <= X"00";
+					G_next <= X"66";
+					B_next <= X"00";
+				when X"b4" =>
+					R_next <= X"07";
+					G_next <= X"77";
+					B_next <= X"00";
+				when X"b5" =>
+					R_next <= X"18";
+					G_next <= X"88";
+					B_next <= X"00";
+				when X"b6" =>
+					R_next <= X"29";
+					G_next <= X"99";
+					B_next <= X"00";
+				when X"b7" =>
+					R_next <= X"3a";
+					G_next <= X"aa";
+					B_next <= X"0f";
+				when X"b8" =>
+					R_next <= X"4b";
+					G_next <= X"bb";
+					B_next <= X"20";
+				when X"b9" =>
+					R_next <= X"5c";
+					G_next <= X"cc";
+					B_next <= X"31";
+				when X"ba" =>
+					R_next <= X"6d";
+					G_next <= X"dd";
+					B_next <= X"42";
+				when X"bb" =>
+					R_next <= X"7e";
+					G_next <= X"ee";
+					B_next <= X"53";
+				when X"bc" =>
+					R_next <= X"8f";
+					G_next <= X"ff";
+					B_next <= X"64";
+				when X"bd" =>
+					R_next <= X"a0";
+					G_next <= X"ff";
+					B_next <= X"75";
+				when X"be" =>
+					R_next <= X"b1";
+					G_next <= X"ff";
+					B_next <= X"86";
+				when X"bf" =>
+					R_next <= X"c2";
+					G_next <= X"ff";
+					B_next <= X"97";
+				when X"c0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"c1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"c2" =>
+					R_next <= X"02";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"c3" =>
+					R_next <= X"13";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"c4" =>
+					R_next <= X"24";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"c5" =>
+					R_next <= X"35";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"c6" =>
+					R_next <= X"46";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"c7" =>
+					R_next <= X"57";
+					G_next <= X"a2";
+					B_next <= X"00";
+				when X"c8" =>
+					R_next <= X"68";
+					G_next <= X"b3";
+					B_next <= X"00";
+				when X"c9" =>
+					R_next <= X"79";
+					G_next <= X"c4";
+					B_next <= X"0e";
+				when X"ca" =>
+					R_next <= X"8a";
+					G_next <= X"d5";
+					B_next <= X"1f";
+				when X"cb" =>
+					R_next <= X"9b";
+					G_next <= X"e6";
+					B_next <= X"30";
+				when X"cc" =>
+					R_next <= X"ac";
+					G_next <= X"f7";
+					B_next <= X"41";
+				when X"cd" =>
+					R_next <= X"bd";
+					G_next <= X"ff";
+					B_next <= X"52";
+				when X"ce" =>
+					R_next <= X"ce";
+					G_next <= X"ff";
+					B_next <= X"63";
+				when X"cf" =>
+					R_next <= X"df";
+					G_next <= X"ff";
+					B_next <= X"74";
+				when X"d0" =>
+					R_next <= X"01";
+					G_next <= X"1c";
+					B_next <= X"00";
+				when X"d1" =>
+					R_next <= X"12";
+					G_next <= X"2d";
+					B_next <= X"00";
+				when X"d2" =>
+					R_next <= X"23";
+					G_next <= X"3e";
+					B_next <= X"00";
+				when X"d3" =>
+					R_next <= X"34";
+					G_next <= X"4f";
+					B_next <= X"00";
+				when X"d4" =>
+					R_next <= X"45";
+					G_next <= X"60";
+					B_next <= X"00";
+				when X"d5" =>
+					R_next <= X"56";
+					G_next <= X"71";
+					B_next <= X"00";
+				when X"d6" =>
+					R_next <= X"67";
+					G_next <= X"82";
+					B_next <= X"00";
+				when X"d7" =>
+					R_next <= X"78";
+					G_next <= X"93";
+					B_next <= X"00";
+				when X"d8" =>
+					R_next <= X"89";
+					G_next <= X"a4";
+					B_next <= X"00";
+				when X"d9" =>
+					R_next <= X"9a";
+					G_next <= X"b5";
+					B_next <= X"03";
+				when X"da" =>
+					R_next <= X"ab";
+					G_next <= X"c6";
+					B_next <= X"14";
+				when X"db" =>
+					R_next <= X"bc";
+					G_next <= X"d7";
+					B_next <= X"25";
+				when X"dc" =>
+					R_next <= X"cd";
+					G_next <= X"e8";
+					B_next <= X"36";
+				when X"dd" =>
+					R_next <= X"de";
+					G_next <= X"f9";
+					B_next <= X"47";
+				when X"de" =>
+					R_next <= X"ef";
+					G_next <= X"ff";
+					B_next <= X"58";
+				when X"df" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"69";
+				when X"e0" =>
+					R_next <= X"23";
+					G_next <= X"09";
+					B_next <= X"00";
+				when X"e1" =>
+					R_next <= X"34";
+					G_next <= X"1a";
+					B_next <= X"00";
+				when X"e2" =>
+					R_next <= X"45";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"e3" =>
+					R_next <= X"56";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"e4" =>
+					R_next <= X"67";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"e5" =>
+					R_next <= X"78";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"e6" =>
+					R_next <= X"89";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"e7" =>
+					R_next <= X"9a";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"e8" =>
+					R_next <= X"ab";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"e9" =>
+					R_next <= X"bc";
+					G_next <= X"a2";
+					B_next <= X"10";
+				when X"ea" =>
+					R_next <= X"cd";
+					G_next <= X"b3";
+					B_next <= X"21";
+				when X"eb" =>
+					R_next <= X"de";
+					G_next <= X"c4";
+					B_next <= X"32";
+				when X"ec" =>
+					R_next <= X"ef";
+					G_next <= X"d5";
+					B_next <= X"43";
+				when X"ed" =>
+					R_next <= X"ff";
+					G_next <= X"e6";
+					B_next <= X"54";
+				when X"ee" =>
+					R_next <= X"ff";
+					G_next <= X"f7";
+					B_next <= X"65";
+				when X"ef" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"76";
+				when X"f0" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"f1" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"f2" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"f3" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"f4" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"f5" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"f6" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"f7" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"f8" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"f9" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"fa" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"fb" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"fc" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"fd" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"fe" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"ff" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+			end case;
+			
+		end process;
+		
+end altirra;
+
+
+ARCHITECTURE laoo OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+					when X"00" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"01" =>
+						R_next <= X"0e";
+						G_next <= X"0d";
+						B_next <= X"0e";
+					when X"02" =>
+						R_next <= X"1d";
+						G_next <= X"1d";
+						B_next <= X"1d";
+					when X"03" =>
+						R_next <= X"2e";
+						G_next <= X"2d";
+						B_next <= X"2e";
+					when X"04" =>
+						R_next <= X"3e";
+						G_next <= X"3d";
+						B_next <= X"3e";
+					when X"05" =>
+						R_next <= X"4f";
+						G_next <= X"4e";
+						B_next <= X"4f";
+					when X"06" =>
+						R_next <= X"5f";
+						G_next <= X"5e";
+						B_next <= X"5f";
+					when X"07" =>
+						R_next <= X"70";
+						G_next <= X"6f";
+						B_next <= X"6f";
+					when X"08" =>
+						R_next <= X"7a";
+						G_next <= X"7a";
+						B_next <= X"79";
+					when X"09" =>
+						R_next <= X"8b";
+						G_next <= X"8a";
+						B_next <= X"8b";
+					when X"0a" =>
+						R_next <= X"9c";
+						G_next <= X"9b";
+						B_next <= X"9b";
+					when X"0b" =>
+						R_next <= X"ad";
+						G_next <= X"ac";
+						B_next <= X"ac";
+					when X"0c" =>
+						R_next <= X"bc";
+						G_next <= X"bb";
+						B_next <= X"bb";
+					when X"0d" =>
+						R_next <= X"cd";
+						G_next <= X"cc";
+						B_next <= X"cd";
+					when X"0e" =>
+						R_next <= X"dc";
+						G_next <= X"db";
+						B_next <= X"dc";
+					when X"0f" =>
+						R_next <= X"ec";
+						G_next <= X"ec";
+						B_next <= X"ec";
+					when X"10" =>
+						R_next <= X"35";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"11" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"12" =>
+						R_next <= X"4f";
+						G_next <= X"14";
+						B_next <= X"00";
+					when X"13" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"14" =>
+						R_next <= X"6e";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"15" =>
+						R_next <= X"7f";
+						G_next <= X"45";
+						B_next <= X"03";
+					when X"16" =>
+						R_next <= X"8e";
+						G_next <= X"55";
+						B_next <= X"13";
+					when X"17" =>
+						R_next <= X"9f";
+						G_next <= X"66";
+						B_next <= X"23";
+					when X"18" =>
+						R_next <= X"a9";
+						G_next <= X"71";
+						B_next <= X"2d";
+					when X"19" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"1a" =>
+						R_next <= X"ca";
+						G_next <= X"92";
+						B_next <= X"50";
+					when X"1b" =>
+						R_next <= X"db";
+						G_next <= X"a3";
+						B_next <= X"61";
+					when X"1c" =>
+						R_next <= X"ea";
+						G_next <= X"b2";
+						B_next <= X"70";
+					when X"1d" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"1e" =>
+						R_next <= X"fe";
+						G_next <= X"d2";
+						B_next <= X"91";
+					when X"1f" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+					when X"20" =>
+						R_next <= X"3f";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"21" =>
+						R_next <= X"4b";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"22" =>
+						R_next <= X"59";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"23" =>
+						R_next <= X"69";
+						G_next <= X"19";
+						B_next <= X"03";
+					when X"24" =>
+						R_next <= X"78";
+						G_next <= X"29";
+						B_next <= X"12";
+					when X"25" =>
+						R_next <= X"88";
+						G_next <= X"3a";
+						B_next <= X"23";
+					when X"26" =>
+						R_next <= X"98";
+						G_next <= X"4a";
+						B_next <= X"34";
+					when X"27" =>
+						R_next <= X"a9";
+						G_next <= X"5b";
+						B_next <= X"45";
+					when X"28" =>
+						R_next <= X"b3";
+						G_next <= X"65";
+						B_next <= X"4f";
+					when X"29" =>
+						R_next <= X"c4";
+						G_next <= X"76";
+						B_next <= X"61";
+					when X"2a" =>
+						R_next <= X"d4";
+						G_next <= X"87";
+						B_next <= X"72";
+					when X"2b" =>
+						R_next <= X"e5";
+						G_next <= X"98";
+						B_next <= X"83";
+					when X"2c" =>
+						R_next <= X"f4";
+						G_next <= X"a7";
+						B_next <= X"92";
+					when X"2d" =>
+						R_next <= X"fd";
+						G_next <= X"b8";
+						B_next <= X"a3";
+					when X"2e" =>
+						R_next <= X"ff";
+						G_next <= X"c7";
+						B_next <= X"b3";
+					when X"2f" =>
+						R_next <= X"ff";
+						G_next <= X"d7";
+						B_next <= X"c2";
+					when X"30" =>
+						R_next <= X"3d";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"31" =>
+						R_next <= X"49";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"32" =>
+						R_next <= X"57";
+						G_next <= X"05";
+						B_next <= X"0b";
+					when X"33" =>
+						R_next <= X"68";
+						G_next <= X"15";
+						B_next <= X"1b";
+					when X"34" =>
+						R_next <= X"77";
+						G_next <= X"25";
+						B_next <= X"2a";
+					when X"35" =>
+						R_next <= X"88";
+						G_next <= X"36";
+						B_next <= X"3c";
+					when X"36" =>
+						R_next <= X"98";
+						G_next <= X"46";
+						B_next <= X"4c";
+					when X"37" =>
+						R_next <= X"a8";
+						G_next <= X"57";
+						B_next <= X"5d";
+					when X"38" =>
+						R_next <= X"b2";
+						G_next <= X"61";
+						B_next <= X"67";
+					when X"39" =>
+						R_next <= X"c3";
+						G_next <= X"72";
+						B_next <= X"79";
+					when X"3a" =>
+						R_next <= X"d3";
+						G_next <= X"83";
+						B_next <= X"89";
+					when X"3b" =>
+						R_next <= X"e4";
+						G_next <= X"94";
+						B_next <= X"9a";
+					when X"3c" =>
+						R_next <= X"f3";
+						G_next <= X"a3";
+						B_next <= X"a9";
+					when X"3d" =>
+						R_next <= X"fd";
+						G_next <= X"b4";
+						B_next <= X"ba";
+					when X"3e" =>
+						R_next <= X"ff";
+						G_next <= X"c4";
+						B_next <= X"ca";
+					when X"3f" =>
+						R_next <= X"ff";
+						G_next <= X"d4";
+						B_next <= X"d9";
+					when X"40" =>
+						R_next <= X"38";
+						G_next <= X"00";
+						B_next <= X"27";
+					when X"41" =>
+						R_next <= X"42";
+						G_next <= X"00";
+						B_next <= X"32";
+					when X"42" =>
+						R_next <= X"51";
+						G_next <= X"01";
+						B_next <= X"40";
+					when X"43" =>
+						R_next <= X"61";
+						G_next <= X"0e";
+						B_next <= X"50";
+					when X"44" =>
+						R_next <= X"70";
+						G_next <= X"1e";
+						B_next <= X"5f";
+					when X"45" =>
+						R_next <= X"81";
+						G_next <= X"2f";
+						B_next <= X"70";
+					when X"46" =>
+						R_next <= X"90";
+						G_next <= X"3f";
+						B_next <= X"81";
+					when X"47" =>
+						R_next <= X"a0";
+						G_next <= X"51";
+						B_next <= X"90";
+					when X"48" =>
+						R_next <= X"ab";
+						G_next <= X"5b";
+						B_next <= X"9a";
+					when X"49" =>
+						R_next <= X"bc";
+						G_next <= X"6c";
+						B_next <= X"ac";
+					when X"4a" =>
+						R_next <= X"cc";
+						G_next <= X"7c";
+						B_next <= X"bc";
+					when X"4b" =>
+						R_next <= X"dc";
+						G_next <= X"8d";
+						B_next <= X"cd";
+					when X"4c" =>
+						R_next <= X"ec";
+						G_next <= X"9d";
+						B_next <= X"dc";
+					when X"4d" =>
+						R_next <= X"fa";
+						G_next <= X"ae";
+						B_next <= X"ed";
+					when X"4e" =>
+						R_next <= X"fe";
+						G_next <= X"bd";
+						B_next <= X"fa";
+					when X"4f" =>
+						R_next <= X"ff";
+						G_next <= X"cd";
+						B_next <= X"fe";
+					when X"50" =>
+						R_next <= X"2c";
+						G_next <= X"00";
+						B_next <= X"46";
+					when X"51" =>
+						R_next <= X"37";
+						G_next <= X"00";
+						B_next <= X"50";
+					when X"52" =>
+						R_next <= X"46";
+						G_next <= X"01";
+						B_next <= X"5f";
+					when X"53" =>
+						R_next <= X"55";
+						G_next <= X"0e";
+						B_next <= X"6e";
+					when X"54" =>
+						R_next <= X"65";
+						G_next <= X"1e";
+						B_next <= X"7d";
+					when X"55" =>
+						R_next <= X"75";
+						G_next <= X"2f";
+						B_next <= X"8e";
+					when X"56" =>
+						R_next <= X"85";
+						G_next <= X"3f";
+						B_next <= X"9f";
+					when X"57" =>
+						R_next <= X"95";
+						G_next <= X"50";
+						B_next <= X"ae";
+					when X"58" =>
+						R_next <= X"a0";
+						G_next <= X"5b";
+						B_next <= X"b8";
+					when X"59" =>
+						R_next <= X"b1";
+						G_next <= X"6c";
+						B_next <= X"ca";
+					when X"5a" =>
+						R_next <= X"c1";
+						G_next <= X"7c";
+						B_next <= X"da";
+					when X"5b" =>
+						R_next <= X"d2";
+						G_next <= X"8d";
+						B_next <= X"eb";
+					when X"5c" =>
+						R_next <= X"e1";
+						G_next <= X"9d";
+						B_next <= X"f8";
+					when X"5d" =>
+						R_next <= X"f2";
+						G_next <= X"ae";
+						B_next <= X"fe";
+					when X"5e" =>
+						R_next <= X"fc";
+						G_next <= X"bd";
+						B_next <= X"ff";
+					when X"5f" =>
+						R_next <= X"fe";
+						G_next <= X"cd";
+						B_next <= X"ff";
+					when X"60" =>
+						R_next <= X"19";
+						G_next <= X"00";
+						B_next <= X"5e";
+					when X"61" =>
+						R_next <= X"24";
+						G_next <= X"00";
+						B_next <= X"67";
+					when X"62" =>
+						R_next <= X"34";
+						G_next <= X"03";
+						B_next <= X"76";
+					when X"63" =>
+						R_next <= X"44";
+						G_next <= X"13";
+						B_next <= X"85";
+					when X"64" =>
+						R_next <= X"53";
+						G_next <= X"22";
+						B_next <= X"94";
+					when X"65" =>
+						R_next <= X"64";
+						G_next <= X"33";
+						B_next <= X"a5";
+					when X"66" =>
+						R_next <= X"74";
+						G_next <= X"43";
+						B_next <= X"b5";
+					when X"67" =>
+						R_next <= X"85";
+						G_next <= X"55";
+						B_next <= X"c4";
+					when X"68" =>
+						R_next <= X"8f";
+						G_next <= X"5f";
+						B_next <= X"ce";
+					when X"69" =>
+						R_next <= X"a0";
+						G_next <= X"70";
+						B_next <= X"e0";
+					when X"6a" =>
+						R_next <= X"b0";
+						G_next <= X"81";
+						B_next <= X"f0";
+					when X"6b" =>
+						R_next <= X"c1";
+						G_next <= X"92";
+						B_next <= X"fc";
+					when X"6c" =>
+						R_next <= X"d0";
+						G_next <= X"a1";
+						B_next <= X"fe";
+					when X"6d" =>
+						R_next <= X"e1";
+						G_next <= X"b2";
+						B_next <= X"ff";
+					when X"6e" =>
+						R_next <= X"f0";
+						G_next <= X"c2";
+						B_next <= X"ff";
+					when X"6f" =>
+						R_next <= X"fc";
+						G_next <= X"d2";
+						B_next <= X"ff";
+					when X"70" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"5c";
+					when X"71" =>
+						R_next <= X"00";
+						G_next <= X"09";
+						B_next <= X"66";
+					when X"72" =>
+						R_next <= X"09";
+						G_next <= X"18";
+						B_next <= X"75";
+					when X"73" =>
+						R_next <= X"1a";
+						G_next <= X"29";
+						B_next <= X"84";
+					when X"74" =>
+						R_next <= X"29";
+						G_next <= X"38";
+						B_next <= X"93";
+					when X"75" =>
+						R_next <= X"3a";
+						G_next <= X"49";
+						B_next <= X"a4";
+					when X"76" =>
+						R_next <= X"4a";
+						G_next <= X"59";
+						B_next <= X"b4";
+					when X"77" =>
+						R_next <= X"5c";
+						G_next <= X"6a";
+						B_next <= X"c3";
+					when X"78" =>
+						R_next <= X"66";
+						G_next <= X"74";
+						B_next <= X"cd";
+					when X"79" =>
+						R_next <= X"77";
+						G_next <= X"85";
+						B_next <= X"df";
+					when X"7a" =>
+						R_next <= X"87";
+						G_next <= X"96";
+						B_next <= X"ef";
+					when X"7b" =>
+						R_next <= X"98";
+						G_next <= X"a7";
+						B_next <= X"fc";
+					when X"7c" =>
+						R_next <= X"a8";
+						G_next <= X"b6";
+						B_next <= X"fe";
+					when X"7d" =>
+						R_next <= X"b9";
+						G_next <= X"c7";
+						B_next <= X"ff";
+					when X"7e" =>
+						R_next <= X"c8";
+						G_next <= X"d6";
+						B_next <= X"ff";
+					when X"7f" =>
+						R_next <= X"d8";
+						G_next <= X"e7";
+						B_next <= X"ff";
+					when X"80" =>
+						R_next <= X"00";
+						G_next <= X"0b";
+						B_next <= X"45";
+					when X"81" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"4f";
+					when X"82" =>
+						R_next <= X"00";
+						G_next <= X"25";
+						B_next <= X"5d";
+					when X"83" =>
+						R_next <= X"09";
+						G_next <= X"36";
+						B_next <= X"6d";
+					when X"84" =>
+						R_next <= X"18";
+						G_next <= X"45";
+						B_next <= X"7c";
+					when X"85" =>
+						R_next <= X"29";
+						G_next <= X"56";
+						B_next <= X"8d";
+					when X"86" =>
+						R_next <= X"39";
+						G_next <= X"66";
+						B_next <= X"9d";
+					when X"87" =>
+						R_next <= X"4b";
+						G_next <= X"77";
+						B_next <= X"ac";
+					when X"88" =>
+						R_next <= X"56";
+						G_next <= X"81";
+						B_next <= X"b6";
+					when X"89" =>
+						R_next <= X"67";
+						G_next <= X"92";
+						B_next <= X"c8";
+					when X"8a" =>
+						R_next <= X"77";
+						G_next <= X"a2";
+						B_next <= X"d9";
+					when X"8b" =>
+						R_next <= X"88";
+						G_next <= X"b3";
+						B_next <= X"e9";
+					when X"8c" =>
+						R_next <= X"98";
+						G_next <= X"c3";
+						B_next <= X"f7";
+					when X"8d" =>
+						R_next <= X"a9";
+						G_next <= X"d3";
+						B_next <= X"fe";
+					when X"8e" =>
+						R_next <= X"b8";
+						G_next <= X"e3";
+						B_next <= X"ff";
+					when X"8f" =>
+						R_next <= X"c8";
+						G_next <= X"f3";
+						B_next <= X"ff";
+					when X"90" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"25";
+					when X"91" =>
+						R_next <= X"00";
+						G_next <= X"22";
+						B_next <= X"30";
+					when X"92" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"3f";
+					when X"93" =>
+						R_next <= X"01";
+						G_next <= X"42";
+						B_next <= X"4f";
+					when X"94" =>
+						R_next <= X"0c";
+						G_next <= X"51";
+						B_next <= X"5e";
+					when X"95" =>
+						R_next <= X"1e";
+						G_next <= X"62";
+						B_next <= X"6f";
+					when X"96" =>
+						R_next <= X"2e";
+						G_next <= X"72";
+						B_next <= X"80";
+					when X"97" =>
+						R_next <= X"40";
+						G_next <= X"82";
+						B_next <= X"8f";
+					when X"98" =>
+						R_next <= X"4a";
+						G_next <= X"8d";
+						B_next <= X"99";
+					when X"99" =>
+						R_next <= X"5c";
+						G_next <= X"9d";
+						B_next <= X"ab";
+					when X"9a" =>
+						R_next <= X"6c";
+						G_next <= X"ae";
+						B_next <= X"bc";
+					when X"9b" =>
+						R_next <= X"7e";
+						G_next <= X"be";
+						B_next <= X"cc";
+					when X"9c" =>
+						R_next <= X"8d";
+						G_next <= X"ce";
+						B_next <= X"db";
+					when X"9d" =>
+						R_next <= X"9e";
+						G_next <= X"de";
+						B_next <= X"ed";
+					when X"9e" =>
+						R_next <= X"ad";
+						G_next <= X"ee";
+						B_next <= X"fa";
+					when X"9f" =>
+						R_next <= X"bd";
+						G_next <= X"fc";
+						B_next <= X"fe";
+					when X"a0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"a1" =>
+						R_next <= X"00";
+						G_next <= X"2f";
+						B_next <= X"00";
+					when X"a2" =>
+						R_next <= X"00";
+						G_next <= X"3e";
+						B_next <= X"0a";
+					when X"a3" =>
+						R_next <= X"00";
+						G_next <= X"4f";
+						B_next <= X"1a";
+					when X"a4" =>
+						R_next <= X"08";
+						G_next <= X"5e";
+						B_next <= X"29";
+					when X"a5" =>
+						R_next <= X"18";
+						G_next <= X"6f";
+						B_next <= X"3b";
+					when X"a6" =>
+						R_next <= X"28";
+						G_next <= X"7f";
+						B_next <= X"4b";
+					when X"a7" =>
+						R_next <= X"3a";
+						G_next <= X"8f";
+						B_next <= X"5c";
+					when X"a8" =>
+						R_next <= X"44";
+						G_next <= X"9a";
+						B_next <= X"65";
+					when X"a9" =>
+						R_next <= X"55";
+						G_next <= X"ab";
+						B_next <= X"78";
+					when X"aa" =>
+						R_next <= X"65";
+						G_next <= X"bb";
+						B_next <= X"88";
+					when X"ab" =>
+						R_next <= X"77";
+						G_next <= X"cc";
+						B_next <= X"99";
+					when X"ac" =>
+						R_next <= X"86";
+						G_next <= X"db";
+						B_next <= X"a8";
+					when X"ad" =>
+						R_next <= X"97";
+						G_next <= X"ec";
+						B_next <= X"ba";
+					when X"ae" =>
+						R_next <= X"a6";
+						G_next <= X"fa";
+						B_next <= X"c9";
+					when X"af" =>
+						R_next <= X"b7";
+						G_next <= X"fe";
+						B_next <= X"d9";
+					when X"b0" =>
+						R_next <= X"00";
+						G_next <= X"2a";
+						B_next <= X"00";
+					when X"b1" =>
+						R_next <= X"00";
+						G_next <= X"37";
+						B_next <= X"00";
+					when X"b2" =>
+						R_next <= X"00";
+						G_next <= X"46";
+						B_next <= X"00";
+					when X"b3" =>
+						R_next <= X"01";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"b4" =>
+						R_next <= X"0f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"b5" =>
+						R_next <= X"20";
+						G_next <= X"76";
+						B_next <= X"03";
+					when X"b6" =>
+						R_next <= X"31";
+						G_next <= X"85";
+						B_next <= X"13";
+					when X"b7" =>
+						R_next <= X"42";
+						G_next <= X"96";
+						B_next <= X"24";
+					when X"b8" =>
+						R_next <= X"4c";
+						G_next <= X"a1";
+						B_next <= X"2d";
+					when X"b9" =>
+						R_next <= X"5d";
+						G_next <= X"b1";
+						B_next <= X"40";
+					when X"ba" =>
+						R_next <= X"6d";
+						G_next <= X"c1";
+						B_next <= X"51";
+					when X"bb" =>
+						R_next <= X"7f";
+						G_next <= X"d2";
+						B_next <= X"62";
+					when X"bc" =>
+						R_next <= X"8e";
+						G_next <= X"e2";
+						B_next <= X"71";
+					when X"bd" =>
+						R_next <= X"9f";
+						G_next <= X"f2";
+						B_next <= X"82";
+					when X"be" =>
+						R_next <= X"af";
+						G_next <= X"fd";
+						B_next <= X"92";
+					when X"bf" =>
+						R_next <= X"bf";
+						G_next <= X"ff";
+						B_next <= X"a1";
+					when X"c0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"c1" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"00";
+					when X"c2" =>
+						R_next <= X"05";
+						G_next <= X"40";
+						B_next <= X"00";
+					when X"c3" =>
+						R_next <= X"16";
+						G_next <= X"50";
+						B_next <= X"00";
+					when X"c4" =>
+						R_next <= X"26";
+						G_next <= X"5f";
+						B_next <= X"00";
+					when X"c5" =>
+						R_next <= X"36";
+						G_next <= X"70";
+						B_next <= X"00";
+					when X"c6" =>
+						R_next <= X"47";
+						G_next <= X"80";
+						B_next <= X"00";
+					when X"c7" =>
+						R_next <= X"58";
+						G_next <= X"90";
+						B_next <= X"08";
+					when X"c8" =>
+						R_next <= X"62";
+						G_next <= X"9b";
+						B_next <= X"12";
+					when X"c9" =>
+						R_next <= X"73";
+						G_next <= X"ac";
+						B_next <= X"24";
+					when X"ca" =>
+						R_next <= X"84";
+						G_next <= X"bc";
+						B_next <= X"35";
+					when X"cb" =>
+						R_next <= X"95";
+						G_next <= X"cd";
+						B_next <= X"46";
+					when X"cc" =>
+						R_next <= X"a4";
+						G_next <= X"dc";
+						B_next <= X"55";
+					when X"cd" =>
+						R_next <= X"b5";
+						G_next <= X"ed";
+						B_next <= X"67";
+					when X"ce" =>
+						R_next <= X"c5";
+						G_next <= X"fb";
+						B_next <= X"77";
+					when X"cf" =>
+						R_next <= X"d5";
+						G_next <= X"ff";
+						B_next <= X"86";
+					when X"d0" =>
+						R_next <= X"02";
+						G_next <= X"18";
+						B_next <= X"00";
+					when X"d1" =>
+						R_next <= X"0f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"d2" =>
+						R_next <= X"1f";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"d3" =>
+						R_next <= X"2f";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"d4" =>
+						R_next <= X"3f";
+						G_next <= X"54";
+						B_next <= X"00";
+					when X"d5" =>
+						R_next <= X"4f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"d6" =>
+						R_next <= X"60";
+						G_next <= X"75";
+						B_next <= X"00";
+					when X"d7" =>
+						R_next <= X"70";
+						G_next <= X"86";
+						B_next <= X"01";
+					when X"d8" =>
+						R_next <= X"7b";
+						G_next <= X"90";
+						B_next <= X"0a";
+					when X"d9" =>
+						R_next <= X"8c";
+						G_next <= X"a1";
+						B_next <= X"1c";
+					when X"da" =>
+						R_next <= X"9c";
+						G_next <= X"b1";
+						B_next <= X"2c";
+					when X"db" =>
+						R_next <= X"ad";
+						G_next <= X"c2";
+						B_next <= X"3e";
+					when X"dc" =>
+						R_next <= X"bd";
+						G_next <= X"d1";
+						B_next <= X"4d";
+					when X"dd" =>
+						R_next <= X"cd";
+						G_next <= X"e2";
+						B_next <= X"5e";
+					when X"de" =>
+						R_next <= X"dd";
+						G_next <= X"f1";
+						B_next <= X"6e";
+					when X"df" =>
+						R_next <= X"ed";
+						G_next <= X"fd";
+						B_next <= X"7e";
+					when X"e0" =>
+						R_next <= X"1e";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"e1" =>
+						R_next <= X"2a";
+						G_next <= X"16";
+						B_next <= X"00";
+					when X"e2" =>
+						R_next <= X"39";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"e3" =>
+						R_next <= X"49";
+						G_next <= X"36";
+						B_next <= X"00";
+					when X"e4" =>
+						R_next <= X"58";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"e5" =>
+						R_next <= X"69";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"e6" =>
+						R_next <= X"79";
+						G_next <= X"66";
+						B_next <= X"00";
+					when X"e7" =>
+						R_next <= X"8a";
+						G_next <= X"77";
+						B_next <= X"08";
+					when X"e8" =>
+						R_next <= X"94";
+						G_next <= X"81";
+						B_next <= X"12";
+					when X"e9" =>
+						R_next <= X"a5";
+						G_next <= X"92";
+						B_next <= X"24";
+					when X"ea" =>
+						R_next <= X"b5";
+						G_next <= X"a3";
+						B_next <= X"35";
+					when X"eb" =>
+						R_next <= X"c6";
+						G_next <= X"b3";
+						B_next <= X"46";
+					when X"ec" =>
+						R_next <= X"d6";
+						G_next <= X"c3";
+						B_next <= X"55";
+					when X"ed" =>
+						R_next <= X"e6";
+						G_next <= X"d4";
+						B_next <= X"66";
+					when X"ee" =>
+						R_next <= X"f6";
+						G_next <= X"e3";
+						B_next <= X"76";
+					when X"ef" =>
+						R_next <= X"fe";
+						G_next <= X"f3";
+						B_next <= X"86";
+					when X"f0" =>
+						R_next <= X"34";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"f1" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"f2" =>
+						R_next <= X"4f";
+						G_next <= X"15";
+						B_next <= X"00";
+					when X"f3" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"f4" =>
+						R_next <= X"6e";
+						G_next <= X"35";
+						B_next <= X"00";
+					when X"f5" =>
+						R_next <= X"7f";
+						G_next <= X"46";
+						B_next <= X"03";
+					when X"f6" =>
+						R_next <= X"8f";
+						G_next <= X"56";
+						B_next <= X"13";
+					when X"f7" =>
+						R_next <= X"9f";
+						G_next <= X"67";
+						B_next <= X"23";
+					when X"f8" =>
+						R_next <= X"aa";
+						G_next <= X"71";
+						B_next <= X"2e";
+					when X"f9" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"fa" =>
+						R_next <= X"cb";
+						G_next <= X"92";
+						B_next <= X"51";
+					when X"fb" =>
+						R_next <= X"dc";
+						G_next <= X"a3";
+						B_next <= X"62";
+					when X"fc" =>
+						R_next <= X"eb";
+						G_next <= X"b3";
+						B_next <= X"71";
+					when X"fd" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"fe" =>
+						R_next <= X"fe";
+						G_next <= X"d3";
+						B_next <= X"92";
+					when X"ff" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+			end case;
+			
+		end process;
+		
+end laoo;
Index: unmerged/core/de1/zpu_rom.qip
===================================================================
--- unmerged/core/de1/zpu_rom.qip	(nonexistent)
+++ unmerged/core/de1/zpu_rom.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_rom.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.cmp"]
Index: unmerged/core/mcc216/COPYRIGHT_NOTICE
===================================================================
--- unmerged/core/mcc216/COPYRIGHT_NOTICE	(nonexistent)
+++ unmerged/core/mcc216/COPYRIGHT_NOTICE	(revision 1)
@@ -0,0 +1,129 @@
+(c) 2013 Mark Watson
+I am happy for anyone to use these for non-commercial use.
+If my vhdl files are used commercially or sold please contact me for explicit permission at scrameta@gmail.com.
+This applies for source and binary form and derived works.
+
+pokey.vhdl
+pokey_noise_filter.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_ps2_decoder.vhdl
+pokey_mixer.vhdl
+poly_4.vhdl
+poly_5.vhdl
+poly_17_9.vhdl
+
+gtia.vhdl
+gtia_priority.vhdl
+gtia_palette.vhdl // Palette data itself from laoo and Altirra
+gtia_player.vhdl
+
+antic.vhdl
+antic_dma_clock.vhdl
+antic_counter.vhdl
+
+pia.vhdl
+
+cpu.vhd
+shared_enable.vhdl
+irq_glue.vhdl
+
+ps2_keyboard.vhdl
+
+scandoubler.vhdl
+scandouble_ram_infer.vhdl
+
+zpu_glue.vhdl
+zpu_config_regs.vhdl
+
+// utils
+synchronizer.vhdl
+delay_line.vhdl
+wide_delay_line.vhdl
+reg_file.vhdl
+enable_divider.vhdl
+syncreset_enable_divider.vhd
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+simple_counter.vhdl
+
+// semi de1 specific
+sram.vhdl
+flashrom.vhdl
+sdram_statemachine.vhdl
+address_decoder.vhdl
+
+// de1 specific
+atari800core.vhd // top level for DE1
+i2sslave.vhdl
+hexdecoder.vhd
+gpio.vhd
+ledsw.vhd
+
+// altera megafunctions
+pll.vhd 
+zpu_ram.vhd
+zpu_rom.vhd
+
+-----------------------------------------------------------------------------------
+(c) Mike Stirling (from Spectrum core)
+See header for Mike's copyright note
+Parameters modified for my use case
+
+i2c_loader.vhd
+i2s_intf.vhd
+
+-----------------------------------------------------------------------------------
+(c) Peter Wendrich
+Please contact Peter if you wish to use them. I have permission for use as part of the Atari800 core.
+
+cpu_6510.vhd
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+
+-----------------------------------------------------------------------------------
+---- Copyright (c) 2008 Ãvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+ZPU implementation. See headers for more details
+I made a few fixes to make it work for my use case.
+
+zpu_core.vhd
+zpupkg.vhd
+
+-----------------------------------------------------------------------------------
+(c) Scott Larson
+See file header
+
+spi_master.vhd
+
+-----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+zpu/*.[ch]
+SD card/OSD
+-----------------------------------------------------------------------------------
+(c) Mark Watson
+Also some portions taken from SDrive, so (c) Bob and Raster
+
+I am happy for these to be used freely for commercial and non-commercial use.
+
+debug.h  led.h   pause.h  regs.h  types.h  uart.h
+bootdump.c  debug.c  led.c  main.c  regs.c  test.c  uart.c
+
+zpuromgen.c
+
+----------------------------------------------------------------------------------
+(c) Pascal Stang + Bob and Raster
+spi.c
+spi.h
+mmc.c  
+mmc.h
+mmcconf.h 
+
+-----------------------------------------------------------------------------------
+(c) ChaN
+Petit File System
+
+integer.h  
+diskio.h  
+pff.h
+pff.c  
Index: unmerged/core/mcc216/antic.vhdl
===================================================================
--- unmerged/core/mcc216/antic.vhdl	(nonexistent)
+++ unmerged/core/mcc216/antic.vhdl	(revision 1)
@@ -0,0 +1,1824 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	MEMORY_READY_ANTIC : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	ANTIC_ENABLE_179 : IN std_logic;
+	
+	PAL : IN STD_LOGIC;
+	
+	lightpen : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	NMI_N_OUT : OUT std_logic;
+	ANTIC_READY : OUT std_logic; -- taken low by wsync writes
+	
+	-- GTIA interface
+	AN : OUT STD_LOGIC_VECTOR(2 downto 0);
+	COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
+	COLOUR_CLOCK_OUT : out std_logic;
+	HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
+	
+	-- DMA fetch
+	dma_fetch_out : out std_logic;
+	dma_address_out : out std_logic_vector(15 downto 0);
+	
+	-- refresh
+	refresh_out : out std_logic; -- used by sdram
+	
+	-- for debugging
+	dma_clock_out : out std_logic
+);
+END antic;
+
+ARCHITECTURE vhdl OF antic IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT antic_dma_clock IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		enable_dma : IN STD_LOGIC;
+		
+		playfield_start : in std_logic;
+		playfield_end : in std_logic;
+		vblank : in std_logic;
+		
+		slow_dma : in std_logic;
+		medium_dma : in std_logic;
+		fast_dma : in std_logic;
+				
+		dma_clock_out_0 : out std_logic;
+		dma_clock_out_1 : out std_logic;
+		dma_clock_out_2 : out std_logic;
+		dma_clock_out_3 : out std_logic
+	);
+	END component;
+	
+	component antic_counter IS
+	generic
+	(
+		STORE_WIDTH : natural := 1;
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+		
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;	
+
+	component reg_file IS
+	generic
+	(
+		BYTES : natural := 1;
+		WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal enable_dma : std_logic;
+	signal dma_clock_character_name : std_logic;
+	signal dma_clock_character_inc : std_logic;
+	signal dma_clock_bitmap_data : std_logic;
+	signal dma_clock_character_data : std_logic;
+	
+	signal wsync_next : std_logic;
+	signal wsync_reg : std_logic;
+	signal wsync_reset : std_logic;
+	signal wsync_write : std_logic;
+	signal wsync_delayed_write : std_logic;
+	
+	signal nmi_next : std_logic;
+	signal nmi_reg : std_logic;
+	
+	signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
+	signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
+	
+	signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
+	signal nmist_reg : std_logic_vector(7 downto 5);
+	
+	signal nmist_reset : std_logic;
+	
+	signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
+	signal nmien_raw_reg : std_logic_vector(7 downto 6);
+	signal nmien_delayed_reg : std_logic_vector(7 downto 6);
+	
+	signal dli_nmi_next : std_logic;
+	signal vbi_nmi_next : std_logic;
+	signal dli_nmi_reg : std_logic;
+	signal vbi_nmi_reg : std_logic;
+	
+	signal nmi_reset : std_logic;
+	--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
+	--signal nmi_pending_reg : std_logic;
+	
+	signal playfield_dma_start : std_logic;
+	signal playfield_dma_end : std_logic;
+	signal playfield_display_active_next : std_logic;
+	signal playfield_display_active_reg : std_logic;
+	
+	signal dmactl_raw_next : std_logic_vector(6 downto 0);
+	signal dmactl_raw_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_enabled : std_logic;
+	
+	signal chactl_next : std_logic_vector(2 downto 0);
+	signal chactl_reg : std_logic_vector(2 downto 0);
+	
+	-- dma is only allowed during certain portions of the display
+	signal allow_real_dma_next : std_logic;
+	signal allow_real_dma_reg : std_logic;
+	
+	-- dma fetch handling
+	-- dma is scheduled one cycle before it happens, so that registers can directly drive output	
+	signal dma_fetch_next : std_logic;
+	signal dma_fetch_reg : std_logic;
+	signal dma_address_next : std_logic_vector(15 downto 0);
+	signal dma_address_reg : std_logic_vector(15 downto 0);
+	
+	constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
+	constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
+	constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
+	constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
+	constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
+	constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
+	signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
+	signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
+	signal dma_fetch_request : std_logic;
+	
+	signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
+	signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
+	
+	signal character_next : std_logic_vector(7 downto 0);
+	signal character_reg : std_logic_vector(7 downto 0);
+
+	signal displayed_character_next : std_logic_vector(7 downto 0);
+	signal displayed_character_reg : std_logic_vector(7 downto 0);
+	
+	-- instruction decode
+	signal instruction_next : std_logic_vector(7 downto 0);
+	signal instruction_reg : std_logic_vector(7 downto 0);
+	
+	signal first_line_of_instruction_next : std_logic;
+	signal first_line_of_instruction_reg: std_logic;
+
+	signal last_line_of_instruction_live : std_logic;
+	signal last_line_of_instruction_next : std_logic;
+	signal last_line_of_instruction_reg: std_logic;
+	
+	signal force_final_row : std_logic;
+	
+	signal instruction_blank_reg : std_logic;
+	signal instruction_blank_next : std_logic;
+
+	--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
+	--signal dma_speed_next : dma_speed_type;
+	--signal dma_speed_reg : dma_speed_type;
+	constant no_dma : std_logic_vector(1 downto 0) := "00";
+	constant slow_dma : std_logic_vector(1 downto 0) := "01";
+	constant medium_dma : std_logic_vector(1 downto 0) := "10";
+	constant fast_dma : std_logic_vector(1 downto 0) := "11";
+	signal dma_speed_next : std_logic_vector(1 downto 0);
+	signal dma_speed_reg : std_logic_vector(1 downto 0);
+	signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
+	
+	--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
+	--signal instruction_type_next : instruction_type;
+	--signal instruction_type_reg : instruction_type;
+	constant mode_character : std_logic_vector(2 downto 0) := "000";
+	constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
+	constant mode_jvb : std_logic_vector(2 downto 0) := "010";
+	constant mode_jump : std_logic_vector(2 downto 0) := "011";
+	constant mode_blank : std_logic_vector(2 downto 0) := "100";
+	signal instruction_type_next : std_logic_vector(2 downto 0);
+	signal instruction_type_reg : std_logic_vector(2 downto 0);
+	
+	signal two_part_instruction_next : std_logic;
+	signal two_part_instruction_reg : std_logic;
+
+		-- e.g. if instruction is 8 lines long then the final row is 7
+	signal instruction_final_row_next : std_logic_vector(3 downto 0);
+	signal instruction_final_row_reg : std_logic_vector(3 downto 0);
+		
+	--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
+	--signal shift_rate_next : shift_rate_type;
+	--signal shift_rate_reg : shift_rate_type;
+	constant slow_shift : std_logic_vector(1 downto 0) := "00";
+	constant medium_shift : std_logic_vector(1 downto 0) := "01";
+	constant fast_shift : std_logic_vector(1 downto 0) := "10";
+	signal shift_rate_next : std_logic_vector(1 downto 0);
+	signal shift_rate_reg : std_logic_vector(1 downto 0);
+	
+	signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
+	signal shift_twobit_reg : std_logic;
+	
+	signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
+	signal twopixel_reg : std_logic;	
+	
+	signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
+	signal single_colour_character_reg : std_logic;
+
+	signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
+	signal multi_colour_character_reg : std_logic;
+	
+	signal twoline_character_next : std_logic; -- for antic 5/7
+	signal twoline_character_reg : std_logic;
+	
+	signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
+	signal map_background_reg : std_logic;
+	
+	signal dli_enabled_next : std_logic;
+	signal dli_enabled_reg : std_logic;
+	
+	signal descenders_next : std_logic; -- for mode 3
+	signal descenders_reg : std_logic;
+		
+	-- Shift register used to output to AN2-AN0	
+	-- Can either be loaded from memory or from the line buffer
+	signal display_shift_next : std_logic_vector(7 downto 0);
+	signal display_shift_reg : std_logic_vector(7 downto 0);
+	
+	signal delay_display_shift_next : std_logic_vector(24 downto 0);
+	signal delay_display_shift_reg : std_logic_vector(24 downto 0);
+	
+	signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
+	
+	signal load_display_shift_from_memory : std_logic;
+	signal load_display_shift_from_line_buffer : std_logic;
+	
+	signal enable_shift : std_logic;
+	signal shiftclock_next : std_logic_vector(3 downto 0);
+	signal shiftclock_reg : std_logic_vector(3 downto 0);
+	
+	signal playfield_reset : std_logic;
+	signal playfield_load : std_logic;
+	
+	-- position in frame	
+	signal hcount_next : std_logic_vector(7 downto 0);
+	signal hcount_reg : std_logic_vector(7 downto 0);
+	
+	signal vcount_next : std_logic_vector(8 downto 0);
+	signal vcount_reg : std_logic_vector(8 downto 0);
+	
+	signal vblank_next : std_logic;
+	signal vblank_reg : std_logic;
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
+	
+	signal hcount_reset : std_logic;
+	signal vcount_reset : std_logic;
+	signal vcount_increment : std_logic;
+	
+	-- scrolling	
+	signal hscrol_reg : std_logic_vector(3 downto 0);
+	signal hscrol_next : std_logic_vector(3 downto 0);
+
+	signal vscrol_raw_reg : std_logic_vector(3 downto 0);
+	signal vscrol_raw_next : std_logic_vector(3 downto 0);
+	signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
+	
+	signal vscrol_enabled_reg : std_logic;
+	signal vscrol_enabled_next : std_logic;
+	signal vscrol_last_enabled_reg : std_logic;
+	signal vscrol_last_enabled_next : std_logic;
+	
+	signal update_row_count : std_logic;
+	
+	signal hscrol_enabled_reg : std_logic;
+	signal hscrol_enabled_next : std_logic;
+
+	-- refresh
+	signal refresh_pending_next : std_logic;
+	signal refresh_pending_reg : std_logic;
+
+	signal refresh_fetch_next : std_logic;
+	signal refresh_fetch_reg : std_logic;
+	
+	-- Counter signals
+	signal increment_display_list_address : std_logic;
+	signal load_display_list_address : std_logic;
+	signal display_list_address_next : std_logic_vector(15 downto 0);
+	signal display_list_address_reg : std_logic_vector(15 downto 0);
+	signal load_display_list_address_cpu : std_logic;
+	signal load_display_list_address_dma : std_logic;
+	signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
+	signal display_list_address_next_dma : std_logic_vector(15 downto 0);	
+
+	signal increment_memory_scan_address : std_logic;
+	signal load_memory_scan_address : std_logic;
+	signal memory_scan_address_next : std_logic_vector(15 downto 0);
+	signal memory_scan_address_reg : std_logic_vector(15 downto 0);
+
+	signal increment_line_buffer_address : std_logic;
+	signal load_line_buffer_address : std_logic;
+	signal line_buffer_address_next : std_logic_vector(7 downto 0);
+	signal line_buffer_address_reg : std_logic_vector(7 downto 0);
+
+	signal increment_row_count : std_logic;
+	signal load_row_count : std_logic;
+	signal row_count_next : std_logic_vector(3 downto 0);
+	signal row_count_reg : std_logic_vector(3 downto 0);
+
+	signal increment_refresh_count : std_logic;
+	signal load_refresh_count : std_logic;
+	signal refresh_count_next : std_logic_vector(3 downto 0);
+	signal refresh_count_reg : std_logic_vector(3 downto 0);
+	
+	signal pmbase_reg : std_logic_vector(7 downto 2);
+	signal pmbase_next : std_logic_vector(7 downto 2);
+
+	signal chbase_raw_reg : std_logic_vector(7 downto 1);
+	signal chbase_raw_next : std_logic_vector(7 downto 1);
+	signal chbase_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal line_buffer_write : std_logic;
+	signal line_buffer_data_in : std_logic_vector(7 downto 0);
+	signal line_buffer_data_out : std_logic_vector(7 downto 0);
+	
+	-- output registers
+	signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
+	signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
+	signal an_prev_reg : std_logic_vector(2 downto 0);  -- previous - for hscrol
+	signal an_next : std_logic_vector(2 downto 0);
+	signal an_reg : std_logic_vector(2 downto 0);
+	
+	-- light pendin
+	signal penv_next : std_logic_vector(7 downto 0);
+	signal penv_reg : std_logic_vector(7 downto 0);
+	signal penh_next : std_logic_vector(7 downto 0);
+	signal penh_reg : std_logic_vector(7 downto 0);
+	
+	-- high res modes
+	signal colour_clock_8x : std_logic;
+	signal colour_clock_4x : std_logic;
+	signal colour_clock_2x : std_logic;
+	signal colour_clock_1x : std_logic;
+	signal colour_clock_half_x : std_logic;
+	signal colour_clock_selected : std_logic;
+	signal colour_clock_selected_highres : std_logic;
+	
+	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
+	
+	constant cycle_length : integer := 32;	
+	
+	signal memory_ready_both : std_logic;
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			nmi_reg <= '0';
+			wsync_reg <= '0';
+			vcount_reg <= (others=>'0');
+			--hcount_reg <= X"01";
+			hcount_reg <= X"00";
+			dmactl_raw_reg <= (others=>'0');
+			chactl_reg <= (others=>'0');
+			vblank_reg <= '0';			
+			vsync_reg <= '0';
+			pmbase_reg <= (others=>'0');
+			allow_real_dma_reg <= '0';
+			display_shift_reg <= (others=>'0');
+			chbase_raw_reg <= (others=>'0');
+			
+			instruction_reg <= (others=>'0');
+			first_line_of_instruction_reg <= '0';
+			last_line_of_instruction_reg <= '0';
+			dma_speed_reg <= no_dma;
+			instruction_type_reg <= mode_blank;
+			instruction_final_row_reg <= (others=>'0');
+			shift_rate_reg <= slow_shift;
+			shift_twobit_reg <= '0';
+			twopixel_reg <= '0';
+			single_colour_character_reg <= '0';
+			multi_colour_character_reg <= '0';
+			twoline_character_reg <= '0';
+			map_background_reg <= '0';
+			dli_enabled_reg <= '0';
+			two_part_instruction_reg <= '0';
+			descenders_reg <='0';
+			
+			hscrol_reg <= (others=>'0');
+			vscrol_raw_reg <= (others=>'0');			
+			vscrol_enabled_reg <= '0';
+			vscrol_last_enabled_reg <= '0';
+			hscrol_enabled_reg <= '0';
+			
+			shiftclock_reg <= (others=>'0');
+			
+			hblank_reg <= '0';
+			
+			an_reg <= (others=>'0');
+			an_prev_reg <= (others=>'0');
+			
+			dma_fetch_reg <= '0';
+			dma_address_reg <= (others=>'0');			
+			dma_fetch_destination_reg <= dma_fetch_null;
+			
+			playfield_display_active_reg <= '0';
+			
+			instruction_blank_reg <= '0';
+			
+			display_list_address_low_temp_reg <= (others=>'0');
+			
+			character_reg <= (others=>'0');
+			displayed_character_reg <= (others=>'0');
+			
+			refresh_pending_reg <= '0';
+			refresh_fetch_reg <= '0';
+			
+			--nmi_pending_reg <= '0';
+			
+			dli_nmi_reg <= '0';
+			vbi_nmi_reg <= '0';
+			nmien_raw_reg <= (others=>'0');
+			
+			delay_display_shift_reg <= (others=>'0');
+			
+			nmi_shiftreg_reg <= (others=>'1');
+			
+			penh_reg <= (others=>'0');
+			penv_reg <= (others=>'0');
+			
+			colour_clock_count_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then			
+			nmi_reg <= nmi_next;
+			wsync_reg <= wsync_next;
+			vcount_reg <= vcount_next;
+			hcount_reg <= hcount_next;
+			nmist_reg <= nmist_next;
+			dmactl_raw_reg <= dmactl_raw_next;
+			chactl_reg <= chactl_next;
+			vblank_reg <= vblank_next;
+			vsync_reg <= vsync_next;
+			pmbase_reg <= pmbase_next;
+			allow_real_dma_reg <= allow_real_dma_next;
+			display_shift_reg <= display_shift_next;
+			chbase_raw_reg <= chbase_raw_next;
+			
+			instruction_reg <= instruction_next;
+			first_line_of_instruction_reg <= first_line_of_instruction_next;
+			last_line_of_instruction_reg <= last_line_of_instruction_next;
+			dma_speed_reg <= dma_speed_next;
+			instruction_type_reg <= instruction_type_next;
+			instruction_final_row_reg <= instruction_final_row_next;
+			shift_rate_reg <= shift_rate_next;
+			shift_twobit_reg <= shift_twobit_next;
+			twopixel_reg <= twopixel_next;
+			single_colour_character_reg <= single_colour_character_next;
+			multi_colour_character_reg <= multi_colour_character_next;
+			twoline_character_reg <= twoline_character_next;
+			map_background_reg <= map_background_next;
+			dli_enabled_reg <= dli_enabled_next;
+			two_part_instruction_reg <= two_part_instruction_next;
+			descenders_reg <= descenders_next;
+			
+			hscrol_reg <= hscrol_next;
+			vscrol_raw_reg <= vscrol_raw_next;	
+			vscrol_enabled_reg <= vscrol_enabled_next;
+			vscrol_last_enabled_reg <= vscrol_last_enabled_next;
+			hscrol_enabled_reg <= hscrol_enabled_next;
+			
+			shiftclock_reg <= shiftclock_next;
+			
+			hblank_reg <= hblank_next;
+			
+			an_reg <= an_next;
+			an_prev_reg <= an_prev_next;
+			
+			dma_fetch_reg <= dma_fetch_next;
+			dma_address_reg <= dma_address_next;
+			dma_fetch_destination_reg <= dma_fetch_destination_next;
+			
+			playfield_display_active_reg <= playfield_display_active_next;
+			
+			instruction_blank_reg <= instruction_blank_next;
+			
+			display_list_address_low_temp_reg <= display_list_address_low_temp_next;
+			
+			character_reg <= character_next;
+			displayed_character_reg <= displayed_character_next;
+			
+			refresh_pending_reg <= refresh_pending_next;
+			refresh_fetch_reg <= refresh_fetch_next;
+						
+			dli_nmi_reg <= dli_nmi_next;
+			vbi_nmi_reg <= vbi_nmi_next;
+			nmien_raw_reg <= nmien_raw_next;
+			
+			delay_display_shift_reg <= delay_display_shift_next;
+			
+			nmi_shiftreg_reg <= nmi_shiftreg_next;
+			
+			penh_reg <= penh_next;
+			penv_reg <= penv_next;
+			
+			colour_clock_count_reg <= colour_clock_count_next;
+		end if;
+	end process;
+	
+	-- Colour clock (3.57MHz for PAL)
+	-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
+	-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
+	--enable_colour_clock_div : enable_divider
+		--generic map (COUNT=>7)
+		--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);	
+	process(colour_clock_count_reg, ANTIC_ENABLE_179)		
+	begin
+		colour_clock_half_x <= '0';
+		colour_clock_1x<='0';
+		colour_clock_2x<='0';
+		colour_clock_4x<='0';
+		colour_clock_8x<='0';
+	
+		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+		
+		if (ANTIC_ENABLE_179 = '1') then -- resync...
+			colour_clock_count_next <= "00001";
+		end if;
+
+		colour_clock_8x <= '1';
+		
+		case colour_clock_count_reg(4 downto 0) is
+		when "00000" =>
+			colour_clock_half_x <= '1';
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "00100" =>
+			colour_clock_4x <= '1';
+		when "01000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "01100" =>
+			colour_clock_4x <= '1';
+		when "10000" =>			
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "10100" =>
+			colour_clock_4x <= '1';
+		when "11000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "11100" =>
+			colour_clock_4x <= '1';			
+		when others =>
+			-- nop
+		end case;
+	end process;
+	
+	process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
+	begin
+		enable_dma <= colour_clock_half_x;
+		colour_clock_selected <= colour_clock_1x;
+		colour_clock_selected_highres <= colour_clock_2x;		
+		dmactl_delayed_enabled <= '0';
+		
+		case dmactl_delayed_reg(6 downto 5) is
+		when "01" =>
+			dmactl_delayed_enabled <= '1';
+		when "10" =>
+			enable_dma <= colour_clock_1x;
+			colour_clock_selected <= colour_clock_2x;		
+			colour_clock_selected_highres <= colour_clock_4x;
+			dmactl_delayed_enabled <= '1';
+		when "11" =>
+			enable_dma <= colour_clock_2x;
+			colour_clock_selected <= colour_clock_4x;
+			colour_clock_selected_highres <= colour_clock_8x;
+			dmactl_delayed_enabled <= '1';
+		when others =>
+			--nop
+		end case;		
+	end process;	
+		
+	--enable_dma_clock_div : enable_divider
+	--	generic map (COUNT=>2)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>colour_clock_selected,enable_out=>enable_dma);		
+
+	-- Counters (memory address for data, memory address for display list)
+	antic_counter_memory_scan : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
+		
+	load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
+	display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
+	antic_counter_display_list : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
+	antic_counter_line_buffer : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
+	antic_counter_row_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
+	antic_counter_refresh_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
+	
+	-- Count position on screen
+	-- horizontal
+	process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
+	begin
+		hcount_next <= hcount_reg;		
+		if (colour_clock_1x = '1') then
+			hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
+			
+			if (colour_clock_half_x = '1') then
+				hcount_next(0) <= '1';
+			end if;
+		end if;
+		
+		if (hcount_reset = '1') then
+			hcount_next <= (others=>'0');
+		end if;
+	end process;
+	
+	-- vertical
+	process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
+	begin
+		vcount_next <= vcount_reg;
+		
+		if (colour_clock_1x = '1') then		
+			if (vcount_increment = '1') then
+				vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
+			end if;
+			
+			if (vcount_reset = '1') then
+				vcount_next <= (others=>'0');
+			end if;
+		end if;
+	end process;	
+	
+	-- Actions done based on vertical position		
+	process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
+	begin
+		vblank_next <= vblank_reg;
+		vsync_next <= vsync_reg;
+		vcount_reset <= '0';
+	
+		if (colour_clock_1x='1') then
+			case vcount_reg is
+				when '0'&X"08" => 
+					vblank_next <= '0';
+				when '0'&X"F8" =>
+					vblank_next <= '1';
+				--when '1'&X"05" => (changed for testing galaxian!)
+				--	vblank_next <= '1';					
+-- PAL
+				when '1'&X"16" =>
+					vsync_next <= pal;
+				when '1'&X"19" =>
+					vsync_next <= '0';
+				when '1'&X"38" =>
+					vcount_reset <= '1'; -- Blip at 9c..., then wrap
+-- NTSC
+				when '0'&X"FA" =>
+					vsync_next <= not(pal);
+				when '0'&X"FD" =>
+					vsync_next <= '0';
+				when '1'&X"06" =>
+					vcount_reset <= not(pal); -- Blip at 9c..., then wrap
+				when others =>
+					-- nothing
+			end case;
+		end if;
+	end process;
+	
+	-- Calculate playfield start/end
+	process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
+	begin		
+		playfield_dma_start_cycle <= (others=>'1');
+		playfield_dma_end_cycle <= (others=>'1');
+		playfield_display_start_cycle <= (others=>'1');
+		playfield_display_end_cycle <= (others=>'1');
+		
+		-- DMA clock start/end
+		-- wide=3, normal=2, narrow=1
+		-- Playfield start is at (in colour clocks):
+		-- 68 + hscrol&FE - width*16
+		-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
+		-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong... 
+		-- e.g. if its 64 then we may be able to do something like base&width&
+		-- Playfield end is at (in colour clocks):
+		-- 164 + hscrol&FE + width*16
+		-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
+		
+		-- hscrol interfers with playfield dma width (for dma purposes only!)
+		if (hscrol_enabled_reg='1') then
+			case dmactl_delayed_reg(1 downto 0) is
+				when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
+					playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20  (10 in machine cycles)
+					playfield_dma_end_cycle   <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
+				when "01" => -- narrow - traated as normal due to hscrol
+					playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36  (18 in machine cycles)
+					playfield_dma_end_cycle <=   X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
+				when others =>
+					-- nothing
+			end case;
+		else
+			case dmactl_delayed_reg(1 downto 0) is
+				when "11" => -- wide
+					playfield_dma_start_cycle <= X"11";
+					playfield_dma_end_cycle   <= X"D0";
+				when "10" => -- normal
+					playfield_dma_start_cycle <= X"21";
+					playfield_dma_end_cycle   <= X"C0";
+				when "01" => -- narrow
+					playfield_dma_start_cycle <= X"31";
+					playfield_dma_end_cycle <=   X"B0";
+				when others =>
+					-- nothing
+			end case;		
+		end if;
+
+		-- background colour outside this area...
+		-- TODO - review these locations - should be clear due to garbage!
+		case dmactl_delayed_reg(1 downto 0) is
+			when "11" => -- wide
+				playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
+				if (hscrol_reg > X"C") then
+					playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol				
+				end if;
+				playfield_display_end_cycle   <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
+			when "10" => -- normal
+				playfield_display_start_cycle <= X"2F";
+				playfield_display_end_cycle   <= X"CF";
+			when "01" => -- narrow
+				playfield_display_start_cycle <= X"3F";
+				playfield_display_end_cycle <=   X"BF";
+			when others =>
+				-- nothing
+		end case;				
+	end process;
+	
+	-- Actions done based on horizontal position - notably dma!
+	process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, displayed_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg)
+	begin
+		allow_real_dma_next <= allow_real_dma_reg;
+
+		playfield_dma_start <= '0';
+		playfield_dma_end <= '0';
+		playfield_display_active_next <= playfield_display_active_reg;
+		
+		dma_fetch_request <= '0';
+		dma_address_next <= dma_address_reg;
+		dma_fetch_destination_next <= dma_fetch_destination_reg;
+		
+		first_line_of_instruction_next <= first_line_of_instruction_reg;
+		last_line_of_instruction_next <= last_line_of_instruction_reg;
+		
+		load_display_shift_from_line_buffer <= '0';
+				
+		increment_memory_scan_address <= '0';
+		
+		line_buffer_address_next <= (others=>'0');
+		load_line_buffer_address <= '0';
+		increment_line_buffer_address <= '0';
+		
+		playfield_load <= '0';
+		
+		hblank_next <= hblank_reg;
+		hcount_reset <= '0';
+		
+		vcount_increment <= '0';
+		
+		character_next <= character_reg;
+		displayed_character_next <= displayed_character_reg;
+		
+		dli_nmi_next <= dli_nmi_reg;
+		vbi_nmi_next <= vbi_nmi_reg;
+		wsync_reset <= '0';
+		
+		load_refresh_count <= '0';
+		refresh_count_next <= (others=>'0');
+		
+		update_row_count <= '0'; 
+		vscrol_last_enabled_next <= vscrol_last_enabled_reg;
+	
+		if (colour_clock_1x = '1') then	
+			-- Playfield start/end
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
+				playfield_dma_start <= '1';				
+				load_line_buffer_address <= '1';
+			end if;
+			
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
+				playfield_dma_end <= '1';
+			end if;	
+			
+			if (hcount_reg = playfield_display_start_cycle) then
+				playfield_display_active_next <= '1';				
+			end if;
+			
+			if (hcount_reg = playfield_display_end_cycle) then
+				playfield_display_active_next <= '0';
+			end if;	
+
+			if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
+				if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
+					dma_fetch_request <= '1';
+				end if;				
+
+				if (twoline_character_reg='1') then
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				else
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				end if;
+				
+				displayed_character_next <= character_reg;
+				
+				-- TODO
+				-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.				
+				dma_fetch_destination_next <= dma_fetch_shiftreg;
+				
+				load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);								
+				increment_line_buffer_address <= '1';
+			end if;						
+		
+			case hcount_reg is 		
+				when X"00" => -- missile DMA, if missile or player DMA enabled					
+					dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;									
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"02" => -- display list dma if enabled
+					first_line_of_instruction_next <= '0';
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- suppress when waiting for vblank
+						first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
+					else				
+						if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
+							dma_fetch_request <= dmactl_delayed_enabled;
+							dma_address_next <= display_list_address_reg;
+							dma_fetch_destination_next <= dma_fetch_instruction;									
+							
+							first_line_of_instruction_next <= '1';						
+							
+							vscrol_last_enabled_next <= vscrol_enabled_reg;
+						end if;
+					end if;					
+				
+				when X"03" =>				
+					update_row_count <= '1'; -- done after instruction fetch...
+					
+				when X"04"|X"06"|X"08"|X"0A" =>  -- player DMA, if enabled
+					dma_fetch_request <= dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;	
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"0C" => -- lms lower byte dma if display list dma enabled?;
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_low;
+				
+				when X"0E" => -- lms upper byte dma if display list dma enabled?
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_high;
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
+						first_line_of_instruction_next <= '0';
+					end if;
+					
+					dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
+					if (vcount_reg = '0'&X"F8") then
+						vbi_nmi_next <= '1';
+					end if;
+					
+				when X"12" =>
+					dli_nmi_next <= '0';
+					vbi_nmi_next <= '0';
+
+				when X"21" =>
+					hblank_next <= '0';					
+					
+				when X"24" => 
+					playfield_load <= '1'; -- start the shift register
+					
+				when X"31" => -- start refresh					
+					load_refresh_count <= '1';
+					refresh_count_next <= (others=>'0');
+				
+				when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
+					wsync_reset <= '1';				
+			
+				when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
+					allow_real_dma_next <= '0';				
+					load_refresh_count <= '1';
+					refresh_count_next <= "1001";
+					
+				when X"D8" => -- vscrol value checked at cycle 108
+					last_line_of_instruction_next <= last_line_of_instruction_live;
+				
+				when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
+					vcount_increment <= '1';
+										
+				when X"DD" =>
+					hblank_next <= '1';					
+					
+				when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
+					hcount_reset <= '1';
+					allow_real_dma_next <= not(vblank_reg);
+				when others =>
+					-- nothing
+			end case;	
+			
+			-- Playfield DMA
+			if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
+				dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= first_line_of_instruction_reg;
+			end if;					
+			
+			if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
+				character_next <= line_buffer_data_out;
+				increment_line_buffer_address <= '1';
+			end if;
+			
+			if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data			
+				dma_fetch_request <= dmactl_delayed_enabled;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= '1';		
+			end if;
+			
+			if (vblank_reg = '1') then
+				dma_fetch_request <= '0';
+			end if;
+			
+			if (refresh_fetch_next = '1') then
+				dma_address_next <= (others=>'0');
+			end if;
+		
+		end if;
+	end process;
+	
+	-- refresh handling
+	process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, memory_ready_antic, allow_real_dma_next)
+	begin
+		increment_refresh_count <= '0';
+		refresh_pending_next <= refresh_pending_reg;
+		refresh_fetch_next <= not(memory_ready_antic) and refresh_fetch_reg;
+		
+		if (colour_clock_1x = '1') then
+			-- do pending refresh once we have a spare cycle
+			if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
+				refresh_fetch_next <= '1';		
+				refresh_pending_next <= '0';
+			end if;
+		
+			-- do scheduled refresh - if block, enable pending one
+			if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
+				increment_refresh_count <= '1';
+				refresh_fetch_next <= not(dma_fetch_next);
+				refresh_pending_next <= dma_fetch_next;
+			end if;
+		end if;
+	end process;
+	
+	-- nmi handling
+	-- edge senstive, single cycle is enough (unless cpu disabled or  clashes)
+	-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist...	which is the goal.	
+
+	nmien_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
+		
+	nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
+	
+	process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
+	begin	
+		nmist_next(5) <= '0';
+		nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
+		nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
+	end process;
+	
+	-- dma clock	
+	process(dma_speed_reg) -- XXX TODO - remove this process!
+	begin
+		slow_dma_s <= '0';
+		medium_dma_s <= '0';
+		fast_dma_s <= '0';
+		
+		case dma_speed_reg is
+			when no_dma =>
+				-- nothing
+			when slow_dma =>
+				slow_dma_s <= '1';
+			when medium_dma =>
+				medium_dma_s <= '1';
+			when fast_dma =>
+				fast_dma_s <= '1';
+		end case;
+	end process;
+	
+	antic_dma_clock1 : antic_dma_clock
+		port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
+
+	-- line buffer
+	reg_file1 : reg_file
+		generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
+		port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);		
+		--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
+		--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
+		
+	-- vertical scrolling
+	-- load row count from vscrol must be done at time of instruction load
+	-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
+	-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
+	vscrol_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>4)
+		port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));		
+	
+	process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count, force_final_row)
+	begin								
+		load_row_count <= '0';
+		row_count_next <= (others=>'0');
+		increment_row_count <= '0';
+		
+		last_line_of_instruction_live <= '0';		
+		
+		if (update_row_count = '1') then							
+			if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
+				row_count_next <= vscrol_delayed_reg;
+			end if;
+		
+			if (first_line_of_instruction_reg = '1') then
+				load_row_count <= '1';
+			else
+				increment_row_count <= '1';
+			end if;
+		end if;
+		
+		if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
+			if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
+				last_line_of_instruction_live <= '1';
+			end if;
+		else -- normal
+			if (row_count_reg = instruction_final_row_reg) then
+				last_line_of_instruction_live <= '1';
+			end if;
+		end if;
+		
+		if (vblank_reg = '1' or force_final_row = '1') then
+			last_line_of_instruction_live <= '1';
+		end if;
+						
+	end process;
+	
+	-- chbase 2 cycle delay
+	chbase_delay : wide_delay_line
+		generic map (COUNT=>cycle_length*2,WIDTH=>7)
+		port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
+		
+	-- decode instruction	
+	process(instruction_reg)
+	begin
+		dma_speed_next <= no_dma;
+		instruction_type_next <= mode_blank;
+		shift_rate_next <= slow_shift;
+		shift_twobit_next <= '0';
+		twopixel_next <= '0';
+		single_colour_character_next <= '0';		
+		multi_colour_character_next <= '0';		
+		twoline_character_next <= '0';
+		map_background_next <= '0';
+		instruction_final_row_next <= (others=>'0');
+		two_part_instruction_next <= instruction_reg(6);
+		instruction_blank_next <= '0';
+		vscrol_enabled_next <= instruction_reg(5);
+		hscrol_enabled_next <= instruction_reg(4);
+		dli_enabled_next <= instruction_reg(7);
+		descenders_next <= '0';		
+		force_final_row <= '0';
+		
+		case instruction_reg(3 downto 0) is 			
+			when X"0" =>
+				instruction_type_next <= mode_blank;
+				instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
+				two_part_instruction_next <= '0';
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				
+			when X"1" =>
+				instruction_type_next <= mode_jump;
+				instruction_final_row_next <= (others=>'0');
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				two_part_instruction_next <= '1';
+				
+				if (instruction_reg(6) = '1') then
+					instruction_type_next <= mode_jvb;
+					force_final_row <= '1';
+				end if;
+				
+			when X"2" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+			when X"3" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"9";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				descenders_next <= '1';
+				
+			when X"4" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				multi_colour_character_next <= '1';
+				
+			when X"5" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';	
+				twoline_character_next <= '1';		
+				multi_colour_character_next <= '1';
+				
+			when X"6" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				
+			when X"7" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				twoline_character_next <= '1';
+				
+			when X"8" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= slow_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"9" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"A" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"B" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"C" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"D" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"E" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"F" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+		end case;
+	end process;
+
+	-- dma fetching
+	process(dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,memory_ready_both,memory_data_in,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
+	begin	
+		instruction_next <= instruction_reg;
+		dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
+		
+		display_list_address_next_dma <= display_list_address_reg;
+		load_display_list_address_dma <= '0';
+		memory_scan_address_next <= memory_scan_address_reg;
+		load_memory_scan_address <= '0';
+		increment_display_list_address <= '0';
+		
+		load_display_shift_from_memory <= '0';
+		display_list_address_low_temp_next <= display_list_address_low_temp_reg;		
+		
+		line_buffer_data_in <= (others=>'0');
+		line_buffer_write <= '0';
+		
+		if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
+			instruction_next <= (others=>'0');
+		end if;
+	
+		if (dma_fetch_reg='1' and memory_ready_both='1') then
+			case dma_fetch_destination_reg is 
+				when dma_fetch_line_buffer =>
+					line_buffer_data_in <= memory_data_in;					
+					line_buffer_write <= '1';
+				when dma_fetch_shiftreg =>
+					load_display_shift_from_memory <= '1';
+				when dma_fetch_null =>
+					-- nothing (C/G/MTIA listens to bus)
+				when dma_fetch_instruction =>
+					instruction_next <= memory_data_in;
+					
+					increment_display_list_address <= '1';
+					
+				when dma_fetch_list_low =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						--display_list_address_next_dma(7 downto 0) <= memory_data_in; Changing this so soon messes up next dma cycle
+						display_list_address_low_temp_next <= memory_data_in;
+						increment_display_list_address <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(7 downto 0) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				when dma_fetch_list_high =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						 display_list_address_next_dma <= memory_data_in&display_list_address_low_temp_reg;
+						 load_display_list_address_dma <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(15 downto 8) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				
+				when others =>
+					-- nothing
+				
+			end case;
+
+			dma_fetch_next <= '0';
+		end if;
+	end process;
+	
+	-- shift reg clock
+	playfield_reset <= hblank_reg;
+	
+	process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
+	begin
+		shiftclock_next <= shiftclock_reg;
+		enable_shift <= '0';
+	
+		if (colour_clock_selected = '1') then
+		
+			shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
+			
+			if (playfield_load='1') then
+				shiftclock_next <= "1000";
+			end if;
+			
+			if (playfield_reset='1') then
+				shiftclock_next <= "0000";
+			end if;			
+			
+			--shiftclock_next(0) <= shiftclock_reg(1);
+			--shiftclock_next(1) <= shiftclock_reg(2);
+			--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
+			--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;						
+			case shift_rate_reg is
+				when slow_shift =>
+					enable_shift <= shiftclock_reg(0);
+				when medium_shift =>
+					enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
+				when fast_shift =>			
+					enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
+				when others =>
+					-- nothing
+			end case;			
+		end if;
+	end process;
+
+	-- shift reg
+	process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, memory_data_in, line_buffer_data_out)
+	begin
+		display_shift_next <= display_shift_reg;
+		
+		if (enable_shift = '1') then
+			if (shift_twobit_reg = '1') then
+				display_shift_next <= display_shift_reg(5 downto 0)&"00";
+			else
+				display_shift_next <= display_shift_reg(6 downto 0)&"0";
+			end if;			
+		end if;
+		
+		if (load_display_shift_from_memory = '1') then
+			display_shift_next(7 downto 0) <= memory_data_in;
+		end if;
+
+		if (load_display_shift_from_line_buffer = '1') then
+			display_shift_next(7 downto 0) <= line_buffer_data_out;
+		end if;
+		
+	end process;
+	
+	-- delay shift reg output for n cycles, so we can match AN with antic output
+	process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg)
+	begin
+		delay_display_shift_next <= delay_display_shift_reg;
+		
+		if (colour_clock_selected = '1') then
+			delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
+		end if;
+		
+	end process;
+	
+	-- ANO-2
+	-- XXX - clean up!	
+	-- first process - AN with no blanking	
+	process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
+	begin
+		an_current <= (others=>'0');
+		data_live <= (others=>'0');
+		if (shift_twobit_reg = '1') then				
+			an_current(0) <= delay_display_shift_reg(0);
+			an_current(1) <= delay_display_shift_reg(1);
+			an_current(2) <= '1';
+			
+			if (instruction_type_reg = mode_character) then							
+				data_live(0) <= delay_display_shift_reg(0);
+				data_live(1) <= delay_display_shift_reg(1);
+								
+				if (descenders_reg = '1') then					
+					if (delay_display_shift_reg(3 downto 2) = "11") then
+						if (unsigned(row_count_reg)<2) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					else
+						if (unsigned(row_count_reg)>=8) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					end if;
+				end if;	
+			
+				if (delay_display_shift_reg(4)='1') then -- inverse/hidden
+					if (chactl_reg(1)='1') then
+						an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
+						an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
+					else
+						an_current(0) <= data_live(0) and not(chactl_reg(0));
+						an_current(1) <= data_live(1) and not(chactl_reg(0));					
+					end if;
+				else
+					an_current(0) <= data_live(0);
+					an_current(1) <= data_live(1);				
+				end if;
+			end if;		
+
+			if (multi_colour_character_reg = '1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "11"&delay_display_shift_reg(4);										
+				end case;				
+			end if;
+			
+			if (map_background_reg='1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "110";										
+				end case;
+			end if;
+		else
+			if (single_colour_character_reg = '1') then
+				-- i.e. antic 6,7
+				if (delay_display_shift_reg(1) = '1') then
+					an_current(0) <= delay_display_shift_reg(3);
+					an_current(1) <= delay_display_shift_reg(4);
+					an_current(2) <= '1';					
+				else
+					an_current(0) <= '0';
+					an_current(1) <= '0';
+					an_current(2) <= '0';
+				end if;			
+			end if;
+			
+			if (map_background_reg='1') then
+				if (delay_display_shift_reg(1)='1') then
+					an_current <= "100";
+				else
+					an_current <= "000";										
+				end if;
+			end if;				
+		end if;		
+	end process;
+	
+	process(colour_clock_selected, an_current, an_prev_reg)
+	begin
+		an_prev_next <= an_prev_reg;
+		
+		if (colour_clock_selected = '1') then
+			an_prev_next <= an_current;
+		end if;
+	end process;
+	
+	process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
+	begin
+		an_next <= an_reg;
+	
+		if (colour_clock_selected = '1') then	
+			an_next <= an_current;
+			
+			if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
+				an_next <= an_prev_reg;
+			end if;
+			
+			if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
+				an_next <= "000";
+			end if;
+			
+			if (vblank_reg = '1' or hblank_reg = '1') then				
+				an_next(0) <= vsync_reg or twopixel_reg;
+				an_next(1) <= not(vsync_reg);
+				an_next(2) <= not(hblank_reg) and twopixel_reg;
+				
+				--an_next <= 
+						--(twopixel_reg and not(vsync_reg or hblank_reg))
+						--&((hblank_reg or vblank_reg) and not(vsync_reg))
+						--&(vsync_reg or twopixel_reg);
+			end if;			
+			
+			-- TODO this is too simplistic:
+			-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
+			-- + odd behaviour seen during high res bug
+
+		end if;
+		
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+
+	-- wsync write takes 1 cycle to assert rdy
+	-- TODO - revisit antic delays in terms of cpu cycles
+	wsync_delay : delay_line
+		generic map (COUNT=>cycle_length+cycle_length/2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
+
+	-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
+	--dmactl_delay : wide_delay_line
+	--	generic map (COUNT=>cycle_length,WIDTH=>6)
+	--	port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
+	dmactl_delayed_reg <= dmactl_raw_next;
+	--dmactl_delayed_reg <= dmactl_raw_reg;
+		
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
+	begin		
+		nmien_raw_next <= nmien_raw_reg;
+		dmactl_raw_next <= dmactl_raw_reg;
+		chactl_next <= chactl_reg;
+		hscrol_next <= hscrol_reg;
+		vscrol_raw_next <= vscrol_raw_reg;
+		chbase_raw_next <= chbase_raw_reg;
+		pmbase_next <= pmbase_reg;
+		wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
+		nmist_reset <= '0';
+		wsync_write <= '0';
+		
+		load_display_list_address_cpu <= '0';
+		display_list_address_next_cpu <= display_list_address_reg;
+	
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				dmactl_raw_next <= cpu_data_in(6 downto 0);
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				chactl_next <= cpu_data_in(2 downto 0);
+			end if;	
+			
+			if(addr_decoded(2) = '1') then
+				display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;		
+			
+			if(addr_decoded(3) = '1') then
+				display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;
+
+			if(addr_decoded(4) = '1') then
+				hscrol_next <= cpu_data_in(3 downto 0);
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				vscrol_raw_next <= cpu_data_in(3 downto 0);
+			end if;
+			
+			if(addr_decoded(7) = '1') then
+				pmbase_next <= cpu_data_in(7 downto 2);
+			end if;		
+			
+			if(addr_decoded(9) = '1') then
+				chbase_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+
+			if(addr_decoded(10) = '1') then
+				wsync_write <= '1';
+			end if;		
+	
+			if(addr_decoded(14) = '1') then
+				nmien_raw_next <= cpu_data_in(7 downto 6);
+			end if;
+		
+			if(addr_decoded(15) = '1') then
+				nmist_reset <= '1';
+			end if;		
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
+	begin
+		data_out <= X"FF";
+
+		if (addr_decoded(8) = '1') then -- HCOUNT :-)
+			data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
+		end if;
+		
+		if(addr_decoded(11) = '1') then --VCOUNT
+			data_out <= vcount_reg(8 downto 1);
+		end if;
+		
+		if (addr_decoded(12) = '1') then -- PENH
+			data_out <= penh_reg;
+		end if;
+		
+		if (addr_decoded(13) = '1') then -- PENV
+			data_out <= penv_reg;
+		end if;
+
+		if(addr_decoded(15) = '1') then --NMIST
+			data_out <= nmist_reg&"00000";
+		end if;
+		
+	end process;
+	
+	-- nmi delay
+	nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
+	
+	-- light pen
+	process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
+	begin
+		penv_next <= penv_reg;
+		penh_next <= penh_reg;
+		
+		if (lightpen = '0') then
+			penv_next <= vcount_reg(8 downto 1);
+			penh_next <= hcount_reg;
+		end if;
+	end process;
+	
+	-- Use CPU data if virtual dma
+	MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
+	
+	-- output
+	nmi_n_out <= nmi_shiftreg_reg(0);
+	
+	dma_clock_out<=dma_clock_character_name;
+	
+	AN <= an_reg;
+	
+	antic_ready <= not(wsync_reg);
+	
+	dma_fetch_out <= refresh_fetch_reg or (allow_real_dma_reg and dma_fetch_reg);
+	dma_address_out <= dma_address_reg;
+	
+	refresh_out <= refresh_fetch_reg;
+	
+	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+	COLOUR_CLOCK_OUT <= colour_clock_selected;
+	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
+	
+END vhdl;
+
Index: unmerged/core/mcc216/atari800core.jdi
===================================================================
--- unmerged/core/mcc216/atari800core.jdi	(nonexistent)
+++ unmerged/core/mcc216/atari800core.jdi	(revision 1)
@@ -0,0 +1,6 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="00000000000000000000"/>
+  </project>
+  <file_info/>
+</sld_project_info>
Index: unmerged/core/mcc216/atari800core.qsf~
===================================================================
--- unmerged/core/mcc216/atari800core.qsf~	(nonexistent)
+++ unmerged/core/mcc216/atari800core.qsf~	(revision 1)
@@ -0,0 +1,688 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_134 -to VGA_R[1]
+set_location_assignment PIN_133 -to VGA_R[2]
+set_location_assignment PIN_132 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_G[0]
+set_location_assignment PIN_142 -to VGA_G[1]
+set_location_assignment PIN_143 -to VGA_G[2]
+set_location_assignment PIN_144 -to VGA_G[3]
+set_location_assignment PIN_4 -to VGA_B[0]
+set_location_assignment PIN_7 -to VGA_B[1]
+set_location_assignment PIN_10 -to VGA_B[2]
+set_location_assignment PIN_11 -to VGA_B[3]
+set_location_assignment PIN_136 -to VGA_HS
+set_location_assignment PIN_137 -to VGA_VS
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_44 -to SD_CLK
+set_location_assignment PIN_46 -to SD_CMD
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_location_assignment PIN_28 -to AUDIO_L
+set_location_assignment PIN_30 -to AUDIO_R
+set_location_assignment PIN_53 -to CPU_RESET_n
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_127 -to JOY1_n[0]
+set_location_assignment PIN_91 -to JOY1_n[1]
+set_location_assignment PIN_90 -to JOY1_n[2]
+set_location_assignment PIN_88 -to JOY1_n[3]
+set_location_assignment PIN_89 -to JOY1_n[4]
+set_location_assignment PIN_126 -to JOY1_n[5]
+set_location_assignment PIN_128 -to JOY2_n[0]
+set_location_assignment PIN_25 -to JOY2_n[1]
+set_location_assignment PIN_24 -to JOY2_n[2]
+set_location_assignment PIN_22 -to JOY2_n[3]
+set_location_assignment PIN_23 -to JOY2_n[4]
+set_location_assignment PIN_129 -to JOY2_n[5]
+set_location_assignment PIN_33 -to PS2K_DAT
+set_location_assignment PIN_39 -to PS2K_CLK
+set_location_assignment PIN_32 -to PS2M_DAT
+set_location_assignment PIN_31 -to PS2M_CLK
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_49 -to SD_DAT3
+set_location_assignment PIN_42 -to USB_P
+set_location_assignment PIN_43 -to USB_N
+set_location_assignment PIN_50 -to USB2_P
+set_location_assignment PIN_51 -to USB2_N
+set_location_assignment PIN_112 -to SDRAM_CLK
+set_location_assignment PIN_61 -to SDRAM_A[0]
+set_location_assignment PIN_60 -to SDRAM_A[1]
+set_location_assignment PIN_59 -to SDRAM_A[2]
+set_location_assignment PIN_58 -to SDRAM_A[3]
+set_location_assignment PIN_125 -to SDRAM_A[4]
+set_location_assignment PIN_121 -to SDRAM_A[5]
+set_location_assignment PIN_120 -to SDRAM_A[6]
+set_location_assignment PIN_119 -to SDRAM_A[7]
+set_location_assignment PIN_115 -to SDRAM_A[8]
+set_location_assignment PIN_114 -to SDRAM_A[9]
+set_location_assignment PIN_64 -to SDRAM_A[10]
+set_location_assignment PIN_113 -to SDRAM_A[11]
+set_location_assignment PIN_111 -to SDRAM_A[12]
+set_location_assignment PIN_66 -to SDRAM_BA[0]
+set_location_assignment PIN_65 -to SDRAM_BA[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_79 -to SDRAM_DQ[5]
+set_location_assignment PIN_77 -to SDRAM_DQ[6]
+set_location_assignment PIN_76 -to SDRAM_DQ[7]
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_67 -to SDRAM_CS_n
+set_location_assignment PIN_68 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_CAS_n
+set_location_assignment PIN_71 -to SDRAM_WE_n
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_13 -to CFG_DIN
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
+set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+set_global_assignment -name VHDL_FILE romlo.vhd
+set_global_assignment -name VHDL_FILE romhi.vhd
+set_global_assignment -name VHDL_FILE ramint.vhd
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name VHDL_FILE internalromram.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "sdram_statemachine_mcc:b2v_inst20|CLK_SDRAM" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=221" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=221" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=686" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=45961" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=45082" -section_id auto_signaltap_0
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: unmerged/core/mcc216/atari800core.vhd
===================================================================
--- unmerged/core/mcc216/atari800core.vhd	(nonexistent)
+++ unmerged/core/mcc216/atari800core.vhd	(revision 1)
@@ -0,0 +1,1349 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		FPGA_CLK :  IN  STD_LOGIC;
+		PS2K_CLK :  IN  STD_LOGIC;
+		PS2K_DAT :  IN  STD_LOGIC;
+		PS2M_CLK :  IN  STD_LOGIC;
+		PS2M_DAT :  IN  STD_LOGIC;		
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		
+		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_CS_N :  OUT  STD_LOGIC;
+		SDRAM_RAS_N :  OUT  STD_LOGIC;
+		SDRAM_CAS_N :  OUT  STD_LOGIC;
+		SDRAM_WE_N :  OUT  STD_LOGIC;
+		SDRAM_DQM_n :  OUT  STD_LOGIC_vector(1 downto 0);
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		--SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+		SD_DAT0 :  IN  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_DAT3 :  OUT  STD_LOGIC
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+	
+END component;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+	);
+END COMPONENT;
+
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 REPLY : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+component sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END component;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+signal CART_CCTL_N : std_logic;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+--SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal UART_TXD_dummy : std_logic;
+
+BEGIN 
+
+
+
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+LIGHTPEN <= '1';
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+		 
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_left&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_right&"0000",
+  dac_out => audio_r
+);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2K_CLK,
+		 PS2_DAT => PS2K_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+GPIO_CA2_IN <= CA2_OUT;
+GPIO_CB2_IN <= CB2_OUT;
+GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+b2v_inst18 : pokey_ps2_decoder
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_CODE => SYNTHESIZED_WIRE_11,
+		 KEY_HELD => KEY_HELD,
+		 SHIFT_PRESSED => SHIFT_PRESSED,
+		 BREAK_PRESSED => BREAK_PRESSED,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+		 KBCODE => KBCODE,
+		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+
+-- no cart!
+CART_RD4 <= '0';
+CART_RD5 <= '0';
+CART_REQUEST_COMPLETE <= '0';
+CART_ROM_DO <= (others=>'0');
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT,
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT,
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA);
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+SYNC_KEYS <= (others=> '0');
+SYNC_SWITCHES <= (others=> '1');
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DAT0,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_DAT3,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG_dummy,
+		 LEDR => LEDR_dummy,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX);
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => FPGA_CLK,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 locked => PLL_LOCKED);
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD_dummy,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+	begin	
+		keyboard_response <= (others=>'1');
+		
+		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;		 
+		 	 
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+		 TRIG2 => VIRTUAL_TRIGGERS(2),
+		 TRIG3 => VIRTUAL_TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+irr : internalromram
+  PORT map(
+    clock => clk,
+    reset_n => reset_n,
+
+	ROM_ADDR =>rom_addr,
+	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
+	ROM_REQUEST => rom_REQUEST,
+	ROM_DATA => rom_DO,
+	
+	RAM_ADDR => ram_addr,
+	RAM_WR_ENABLE => ram_WRITE_ENABLE,
+	RAM_DATA_IN => wriTE_DATA(7 downto 0),
+	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
+	RAM_REQUEST => ram_REQUEST,
+	RAM_DATA => ram_do(7 downto 0)
+	);
+
+--b2v_inst20 : sdram_statemachine
+--GENERIC MAP(ADDRESS_WIDTH => 22,
+--			AP_BIT => 10,
+--			COLUMN_WIDTH => 8,
+--			ROW_WIDTH => 12
+--			)
+--PORT MAP(CLK_SYSTEM => CLK,
+--		 CLK_SDRAM => CLK_SDRAM,
+--		 RESET_N => RESET_N,
+--		 READ_EN => SDRAM_READ_ENABLE,
+--		 WRITE_EN => SDRAM_WRITE_ENABLE,
+--		 REQUEST => SDRAM_REQUEST,
+--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+--		 REFRESH => SDRAM_REFRESH,
+--		 ADDRESS_IN => SDRAM_ADDR,
+--		 DATA_IN => WRITE_DATA,
+--		 SDRAM_DQ => SDRAM_DQ,
+--		 REPLY => SDRAM_REPLY,
+--		 SDRAM_BA0 => SDRAM_BA(0),
+--		 SDRAM_BA1 => SDRAM_BA(1),
+--		 SDRAM_CKE => SDRAM_A(12),
+--		 SDRAM_CS_N => SDRAM_CS_N,
+--		 SDRAM_RAS_N => SDRAM_RAS_N,
+--		 SDRAM_CAS_N => SDRAM_CAS_N,
+--		 SDRAM_WE_N => SDRAM_WE_N,
+--		 SDRAM_ldqm => SDRAM_DQM_n(0),
+--		 SDRAM_udqm => SDRAM_DQM_n(1),
+--		 DATA_OUT => SDRAM_DO,
+--		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+
+b2v_inst20 : sdram_statemachine_mcc
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => SDRAM_DQ,
+		 REPLY => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => SDRAM_BA(0),
+		 SDRAM_BA1 => SDRAM_BA(1),
+		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+		 SDRAM_CS_N => SDRAM_CS_N,
+		 SDRAM_RAS_N => SDRAM_RAS_N,
+		 SDRAM_CAS_N => SDRAM_CAS_N,
+		 SDRAM_WE_N => SDRAM_WE_N,
+		 SDRAM_ldqm => SDRAM_DQM_n(0),
+		 SDRAM_udqm => SDRAM_DQM_n(1),
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
+
+		
+END bdf_type;
\ No newline at end of file
Index: unmerged/core/mcc216/cpu.vhd
===================================================================
--- unmerged/core/mcc216/cpu.vhd	(nonexistent)
+++ unmerged/core/mcc216/cpu.vhd	(revision 1)
@@ -0,0 +1,142 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+ENTITY cpu IS
+PORT 
+(
+	CLK,RESET,ENABLE : IN STD_logic;
+	DI : IN std_logic_vector(7 downto 0);
+	IRQ_n   : in  std_logic;
+	NMI_n   : in  std_logic;
+	MEMORY_READY : in std_logic;
+	THROTTLE : in std_logic;
+	RDY : in std_logic;
+	DO : OUT std_logic_vector(7 downto 0);
+	A : OUT std_logic_vector(15 downto 0);
+	R_W_n : OUT std_logic;
+	CPU_FETCH : out std_logic
+);
+END cpu;
+
+architecture vhdl of cpu is
+component cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end component;
+
+	signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle
+		
+	-- Support for Peter's core (NMI patch applied)
+	signal debugOpcode : unsigned(7 downto 0);
+	signal debugPc : unsigned(15 downto 0);
+	signal debugA : unsigned(7 downto 0);
+	signal debugX : unsigned(7 downto 0);
+	signal debugY : unsigned(7 downto 0);
+	signal debugS : unsigned(7 downto 0);
+	signal di_unsigned : unsigned(7 downto 0);
+   signal do_unsigned : unsigned(7 downto 0);
+	signal addr_unsigned : unsigned(15 downto 0);
+	signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line
+	signal WE : std_logic;
+	signal nmi_pending_next : std_logic; -- NMI during RDY
+	signal nmi_pending_reg : std_logic;
+	signal nmi_n_adjusted : std_logic;
+	signal nmi_n_reg : std_logic;
+	signal nmi_edge : std_logic;
+	
+	signal CPU_ENABLE_RESET : std_logic;
+	signal not_rdy : std_logic;	
+	
+BEGIN
+	CPU_ENABLE <= ENABLE and memory_ready and THROTTLE;
+	
+	-- CPU designed by Peter W - as used in Chameleon
+	di_unsigned <= unsigned(di);
+	cpu_6502_peter:cpu_65xx
+		generic map
+		(
+			pipelineOpcode => false,
+			pipelineAluMux => false,
+			pipelineAluOut => false
+		)
+		port map (
+			clk => clk,
+			enable => CPU_ENABLE_RDY,
+			halt => '0',
+			reset=>reset,
+			nmi_n=>nmi_n_adjusted,
+			irq_n=>irq_n,
+			d=>di_unsigned,
+			q=>do_unsigned,
+			addr=>addr_unsigned,
+			WE=>WE,
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugOpcode,
+			debugS => debugS
+		);
+		CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
+		
+		CPU_ENABLE_RESET <= CPU_ENABLE or reset;
+		not_rdy <= not(rdy);
+		
+		nmi_edge <= not(nmi_n) and nmi_n_reg;
+		nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable));
+		nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n;
+		
+	-- register
+	process(clk,reset)
+	begin
+		if (RESET = '1') then
+			nmi_pending_reg <= '0';
+			nmi_n_reg <= '1';
+		elsif (clk'event and clk='1') then						
+			nmi_pending_reg <= nmi_pending_next;		
+			nmi_n_reg <= nmi_n;
+		end if;
+	end process;	
+
+	-- outputs
+	r_w_n <= not(we);
+	do <= std_logic_vector(do_unsigned);
+	a <= std_logic_vector(addr_unsigned);
+		
+	CPU_FETCH <= ENABLE and THROTTLE;
+
+END vhdl;
Index: unmerged/core/mcc216/cpu_65xx_e.vhd
===================================================================
--- unmerged/core/mcc216/cpu_65xx_e.vhd	(nonexistent)
+++ unmerged/core/mcc216/cpu_65xx_e.vhd	(revision 1)
@@ -0,0 +1,52 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Interface to 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end entity;
Index: unmerged/core/mcc216/gpio.vhd
===================================================================
--- unmerged/core/mcc216/gpio.vhd	(nonexistent)
+++ unmerged/core/mcc216/gpio.vhd	(revision 1)
@@ -0,0 +1,413 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio is
+port
+(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal read_write_n : std_logic;	
+	signal cart_data_read_async : std_logic_vector(7 downto 0);
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+	
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0');
+	GPIO_0_OUT(7 downto 5) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= '1';
+	GPIO_0_OUT(4) <= MONITOR; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= read_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable;
+	GPIO_0_OUT(33) <= pbi_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable;
+	GPIO_0_OUT(32) <= pbi_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and pbi_write_enable; -- d7
+	GPIO_0_OUT(31) <= cart_data_write(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and pbi_write_enable; -- d3
+	GPIO_0_OUT(30) <= cart_data_write(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable;
+	GPIO_0_OUT(29) <= pbi_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable;
+	GPIO_0_OUT(28) <= pbi_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable;
+	GPIO_0_OUT(27) <= pbi_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable;
+	GPIO_0_OUT(26) <= pbi_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable;
+	GPIO_0_OUT(25) <= pbi_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable;
+	GPIO_0_OUT(24) <= pbi_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable;
+	GPIO_0_OUT(23) <= pbi_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable;
+	GPIO_0_OUT(21) <= S4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable;
+	GPIO_0_OUT(20) <= pbi_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable;
+	GPIO_0_OUT(19) <= pbi_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable;
+	GPIO_0_OUT(18) <= pbi_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable;
+	GPIO_0_OUT(17) <= pbi_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and pbi_write_enable; -- d4
+	GPIO_0_OUT(16) <= cart_data_write(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and pbi_write_enable; -- d5
+	GPIO_0_OUT(15) <= cart_data_write(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and pbi_write_enable; -- d2
+	GPIO_0_OUT(14) <= cart_data_write(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and pbi_write_enable; -- d1
+	GPIO_0_OUT(13) <= cart_data_write(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and pbi_write_enable; -- d0
+	GPIO_0_OUT(12) <= cart_data_write(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and pbi_write_enable; -- d6
+	GPIO_0_OUT(11) <= cart_data_write(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable;
+	GPIO_0_OUT(10) <= S5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
+	GPIO_0_OUT(8) <= CCTL_n; -- cart control
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0'); -- unused
+	GPIO_0_OUT(7 downto 5) <= (others=>'0'); -- unused	
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4) when virtual_stick_in(7 downto 4) = "1111" else virtual_stick_in(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0) when virtual_stick_in(3 downto 0) = "1111" else virtual_stick_in(3 downto 0);
+		
+	--trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&gpio_enable&gpio_enable) or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= GPIO_1_IN(7)& GPIO_1_IN(6);
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	process(gpio_enable, keyboard_scan, keyboard_response_gpio, virtual_keycode, virtual_keyheld, virtual_shift_pressed, virtual_control_pressed, virtual_break_pressed, virtual_stick_in, virtual_trig_in)
+	begin	
+		keyboard_response <= keyboard_response_gpio;
+		
+		if (gpio_enable = '0') then
+			keyboard_response <= (others=>'1');
+		end if;
+		
+		if (virtual_keyheld='1' and virtual_keycode = not(keyboard_scan)) then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and virtual_break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and virtual_shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and virtual_control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;	
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+	
+	read_write_n <= not(pbi_write_enable);
+	
+	cart_complete <= cart_request; -- TODO!
+	
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	cart_data_read_async <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+	cart_data0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+	cart_data1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+	cart_data2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+	cart_data3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+	cart_data4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+	cart_data5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+	cart_data6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+	cart_data7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: unmerged/core/mcc216/gtia_priority.vhdl
===================================================================
--- unmerged/core/mcc216/gtia_priority.vhdl	(nonexistent)
+++ unmerged/core/mcc216/gtia_priority.vhdl	(revision 1)
@@ -0,0 +1,175 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_priority IS
+PORT 
+( 
+	CLK : in std_logic;
+	colour_enable : in std_logic;
+
+	PRIOR : in std_logic_vector(7 downto 0);
+	P0 : in std_logic;
+	P1 : in std_logic;
+	P2	: in std_logic;
+	P3 : in std_logic;
+	PF0 : in std_logic;
+	PF1 : in std_logic;
+	PF2 : in std_logic;
+	PF3 : in std_logic;
+	BK : in std_logic;
+	
+	P0_OUT : out std_logic;
+	P1_OUT : out std_logic;
+	P2_OUT : out std_logic;
+	P3_OUT : out std_logic;
+	PF0_OUT : out std_logic;
+	PF1_OUT : out std_logic;
+	PF2_OUT : out std_logic;
+	PF3_OUT : out std_logic;
+	BK_OUT : out std_logic
+);
+END gtia_priority;
+
+ARCHITECTURE vhdl OF gtia_priority IS
+	signal P01 : std_logic;
+	signal P23 : std_logic;
+	
+	signal PF01 : std_logic;
+	signal PF23 : std_logic;
+	
+	signal PRI01 : std_logic;
+	signal PRI12 : std_logic;
+	signal PRI23 : std_logic;
+	signal PRI03 : std_logic;
+	
+	signal PRI0 : std_logic;
+	signal PRI1 : std_logic;
+	signal PRI2 : std_logic;
+	signal PRI3 : std_logic;
+	signal MULTI : std_logic;
+	
+	signal SP0 : std_logic;
+	signal SP1 : std_logic;
+	signal SP2 : std_logic;
+	signal SP3 : std_logic;	
+	signal SF0 : std_logic;
+	signal SF1 : std_logic;
+	signal SF2 : std_logic;
+	signal SF3 : std_logic;	
+	signal SB : std_logic;
+	
+	signal SP0_next : std_logic;
+	signal SP1_next : std_logic;
+	signal SP2_next : std_logic;
+	signal SP3_next : std_logic;	
+	signal SF0_next : std_logic;
+	signal SF1_next : std_logic;
+	signal SF2_next : std_logic;
+	signal SF3_next : std_logic;	
+	signal SB_next : std_logic;
+
+	signal SP0_reg : std_logic;
+	signal SP1_reg : std_logic;
+	signal SP2_reg : std_logic;
+	signal SP3_reg : std_logic;	
+	signal SF0_reg : std_logic;
+	signal SF1_reg : std_logic;
+	signal SF2_reg : std_logic;
+	signal SF3_reg : std_logic;	
+	signal SB_reg : std_logic;
+begin
+	-- Use actual GTIA logic...
+	P01 <= P0 or P1;
+	P23 <= P2 or P3;
+
+	PF01 <= PF0 or PF1;
+	PF23 <= PF2 or PF3;
+	
+	PRI0 <= prior(0);
+	PRI1 <= prior(1);
+	PRI2 <= prior(2);
+	PRI3 <= prior(3);
+	MULTI <= prior(5);
+	
+	PRI01 <= PRI0  or  PRI1;
+	PRI12 <= PRI1  or  PRI2;
+	PRI23 <= PRI2  or  PRI3;
+	PRI03 <= PRI0  or  PRI3;
+	
+	SP0 <= P0  and   not (PF01 and PRI23)  and   not (PRI2 and PF23);
+	SP1 <= P1  and   not (PF01 and PRI23)  and   not (PRI2 and PF23)  and  ( not P0  or  MULTI);
+	SP2 <= P2  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0);
+	SP3 <= P3  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0)  and  ( not P2  or  MULTI);
+	SF0 <= PF0  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF1 <= PF1  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF2 <= PF2  and   not (P23 and PRI03)  and   not (P01 and  not PRI2)  and   not SF3;
+	SF3 <= PF3  and   not (P23 and PRI03)  and   not (P01 and  not PRI2);
+	SB <=  not P01  and   not P23  and   not PF01  and   not PF23;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+		SP0_reg <= SP0_next;
+		SP1_reg <= SP1_next;
+		SP2_reg <= SP2_next;
+		SP3_reg <= SP3_next;
+		
+		SF0_reg <= SF0_next;
+		SF1_reg <= SF1_next;
+		SF2_reg <= SF2_next;
+		SF3_reg <= SF3_next;
+		
+		SB_reg <= SB_next;
+		end if;
+	end process;
+	
+	-- need to register this to get same position as GTIA modes - i.e. two colour clocks after AN data received
+	process(colour_enable,SP0_reg,SP1_reg,SP2_reg,SP3_reg,SF0_reg,SF1_reg,SF2_reg,SF3_reg,SB_reg,SP0,SP1,SP2,SP3,SF0,SF1,SF2,SF3,SB)
+	begin
+		SP0_next <= SP0_reg;
+		SP1_next <= SP1_reg;
+		SP2_next <= SP2_reg;
+		SP3_next <= SP3_reg;
+		
+		SF0_next <= SF0_reg;
+		SF1_next <= SF1_reg;
+		SF2_next <= SF2_reg;
+		SF3_next <= SF3_reg;
+		
+		SB_next <= SB_reg;
+		
+		if (colour_enable = '1') then	
+			SP0_next <= SP0;
+			SP1_next <= SP1;
+			SP2_next <= SP2;
+			SP3_next <= SP3;
+			
+			SF0_next <= SF0;
+			SF1_next <= SF1;
+			SF2_next <= SF2;
+			SF3_next <= SF3;
+			
+			SB_next <= SB;	
+		end if;
+	end process;
+		
+	-- output
+	P0_OUT <= SP0_reg;
+	P1_OUT <= SP1_reg;
+	P2_OUT <= SP2_reg;
+	P3_OUT <= SP3_reg;
+	PF0_OUT <= SF0_reg;
+	PF1_OUT <= SF1_reg;
+	PF2_OUT <= SF2_reg;
+	PF3_OUT <= SF3_reg;
+	BK_OUT <= SB_reg;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/i2c_loader.vhd
===================================================================
--- unmerged/core/mcc216/i2c_loader.vhd	(nonexistent)
+++ unmerged/core/mcc216/i2c_loader.vhd	(revision 1)
@@ -0,0 +1,302 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
+use IEEE.NUMERIC_STD.ALL;
+
+entity i2c_loader is
+generic (
+	-- Address of slave to be loaded
+	device_address : integer := 16#1a#;
+	-- Number of retries to allow before stopping
+	num_retries : integer := 0;
+	-- Length of clock divider in bits.  Resulting bus frequency is
+	-- CLK/2^(log2_divider + 2)
+	log2_divider : integer := 7
+);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	I2C_SCL		:	inout	std_logic;
+	I2C_SDA		:	inout	std_logic;
+	
+	IS_DONE		:	out std_logic;
+	IS_ERROR	:	out	std_logic
+	);
+end i2c_loader;
+
+architecture i2c_loader_arch of i2c_loader is
+type regs is array(0 to 19) of std_logic_vector(7 downto 0);
+constant init_regs : regs := (
+	-- Left line in, 0dB, mute
+	X"00", X"97",
+	-- Right line in, 0dB, mute
+	X"02", X"97",
+	-- Left headphone out, -29dB, zero cross disabled
+	--X"04", X"58",
+	X"04", X"78",
+	-- Right headphone out, -29dB, zero cross disabled
+	--X"06", X"58",
+	X"06", X"78",
+	-- Audio path, DAC enabled, Line in, Bypass off, mic muted
+	X"08", X"12",
+	-- Digital path, Unmute, HP filter enabled
+	X"0A", X"00",
+	-- Power down mic, clkout and xtal osc, line in and adc
+	X"0C", X"67",
+	-- Format 16-bit I2S, no bit inversion or phase changes, MASTER
+	X"0E", X"42",
+	-- Sampling control, Normal mode, mclk/2 used, We should provide 12.288MHz but will provide 12.25MHz - making 96KHz notional, 97.656KHz actual 
+	X"10", X"DC",
+	-- Activate
+	X"12", X"01"
+	);
+-- Number of bursts (i.e. total number of registers)
+constant burst_length : positive := 2;
+-- Number of bytes to transfer per burst
+constant num_bursts : positive := (init_regs'length / burst_length);
+	
+type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
+signal state : state_t;
+signal phase : std_logic_vector(1 downto 0);
+subtype nbit_t is integer range 0 to 7;
+signal nbit : nbit_t;
+subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
+signal nbyte : nbyte_t;
+subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
+signal thisbyte : thisbyte_t;
+subtype retries_t is integer range 0 to num_retries;
+signal retries : retries_t;
+
+signal clken : std_logic;
+signal divider : std_logic_vector(log2_divider-1 downto 0);
+signal shiftreg : std_logic_vector(7 downto 0);
+signal scl_out : std_logic;
+signal sda_out : std_logic;
+signal nak : std_logic;
+begin
+	-- Create open-drain outputs for I2C bus
+	I2C_SCL <= '0' when scl_out = '0' else 'Z';
+	I2C_SDA <= '0' when sda_out = '0' else 'Z';
+	-- Status outputs are driven both ways
+	IS_DONE <= '1' when state = Done else '0';
+	IS_ERROR <= nak;
+	
+	-- Generate clock enable for desired bus speed
+	clken <= AND_REDUCE(divider);
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			divider <= (others => '0');
+		elsif falling_edge(CLK) then
+			divider <= divider + '1';
+		end if;
+	end process;
+
+	-- The I2C loader process
+	process(nRESET,CLK,clken)
+	begin
+		if nRESET = '0' then
+			scl_out <= '1';
+			sda_out <= '1';
+			state <= Idle;
+			phase <= "00";
+			nbit <= 0;
+			nbyte <= 0;
+			thisbyte <= 0;
+			shiftreg <= (others => '0');
+			nak <= '0'; -- No error
+			retries <= num_retries;
+		elsif rising_edge(CLK) and clken = '1' then
+  			-- Next phase by default
+			phase <= phase + 1;
+
+			-- STATE: IDLE
+			if state = Idle then
+				-- Start loading the device registers straight away
+				-- A 'GO' bit could be polled here if required
+				state <= Start;
+				phase <= "00";
+				scl_out <= '1';
+				sda_out <= '1';
+				
+			-- STATE: START
+			elsif state = Start then
+				-- Generate START condition
+				case phase is
+				when "00" =>
+					-- Drop SDA first
+					sda_out <= '0';
+				when "10" =>
+					-- Then drop SCL
+					scl_out <= '0';
+				when "11" =>
+					-- Advance to next state
+					-- Shift register loaded with device slave address
+					state <= Data;
+					nbit <= 7;
+					shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
+					nbyte <= burst_length;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: DATA
+			elsif state = Data then
+				-- Generate data
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Output data and shift (MSb first)
+					sda_out <= shiftreg(7);
+					shiftreg <= shiftreg(6 downto 0) & '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Next bit or advance to next state when done
+					if nbit = 0 then
+						state <= Ack;
+					else
+						nbit <= nbit - 1;
+					end if;
+				when others =>
+				  null;
+				end case;
+				
+			-- STATE: ACK
+			elsif state = Ack then
+				-- Generate ACK clock and check for error condition
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Float data
+					sda_out <= '1';
+				when "10" =>
+					-- Sample ack bit
+					nak <= I2C_SDA;
+					if I2C_SDA = '1' then
+						-- Error
+						nbyte <= 0; -- Close this burst and skip remaining registers
+						thisbyte <= init_regs'length;
+					else
+						-- Hold ACK to avoid spurious stops - this seems to fix a
+						-- problem with the Wolfson codec which releases the ACK
+						-- right on the falling edge of the clock pulse.  It looks like
+						-- the device interprets this is a STOP condition and then fails
+						-- to acknowledge the next byte.  We can avoid this by holding the
+						-- ACK condition for a little longer.
+						sda_out <= '0';
+					end if;
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Advance to next state
+					if nbyte = 0 then
+						-- No more bytes in this burst - generate a STOP
+						state <= Stop;
+					else
+						-- Generate next byte
+						state <= Data;
+						nbit <= 7;
+						shiftreg <= init_regs(thisbyte);
+						nbyte <= nbyte - 1;
+						thisbyte <= thisbyte + 1;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: STOP
+			elsif state = Stop then
+				-- Generate STOP condition
+				case phase is
+				when "00" =>
+					-- Drop SCL first
+					scl_out <= '0';
+				when "01" =>
+					-- Drop SDA
+					sda_out <= '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					if thisbyte = init_regs'length then
+						-- All registers done, advance to finished state.  This will
+						-- bring SDA high while SCL is still high, completing the STOP
+						-- condition
+						state <= Done;
+					else
+						-- Load the next register after a short delay
+						state <= Pause;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: PAUSE
+			elsif state = Pause then
+				-- Delay for one cycle of 'phase' then start the next burst
+				scl_out <= '1';
+				sda_out <= '1';
+				if phase = "11" then
+					state <= Start;
+				end if;
+				
+			-- STATE: DONE
+			else
+				-- Finished
+				scl_out <= '1';
+				sda_out <= '1';
+				
+				if nak = '1' and retries > 0 then
+					-- We can retry in the event of a NAK in case the
+					-- slave got out of sync for some reason
+					retries <= retries - 1;
+					state <= Idle;
+				end if;
+			end if;
+		end if;
+	end process;
+end i2c_loader_arch;
+
Index: unmerged/core/mcc216/internalromram.vhd.bak
===================================================================
--- unmerged/core/mcc216/internalromram.vhd.bak	(nonexistent)
+++ unmerged/core/mcc216/internalromram.vhd.bak	(revision 1)
@@ -0,0 +1,19 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+	 
+END internalromram;
+
+
+	IROM_DATA <= IROMLO_DATA when addr(15 downto 12)=X"D" else IROMHI_DATA;		
+		if (int_ram = '1') then
+		
+			if (not(addr(15 downto 13) = "000")) then
+				USE_RAM_DATA <= X"FF";
+				RAM_WR_ENABLE <= '0'; -- ban writes over 8k when using int ram - HACK
\ No newline at end of file
Index: unmerged/core/mcc216/pll.bsf
===================================================================
--- unmerged/core/mcc216/pll.bsf	(nonexistent)
+++ unmerged/core/mcc216/pll.bsf	(revision 1)
@@ -0,0 +1,100 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 248 184)
+	(text "pll" (rect 118 0 133 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 248 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 232 50 242 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 248 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 232 66 240 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 248 96)
+		(output)
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 232 82 242 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 248 112)
+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 213 98 242 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 186 168 417 347)(font "Arial" ))
+		(text "inclk0 frequency: 5.000 MHz" (rect 50 59 218 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 93 225 197)(font "Arial" ))
+		(text "DC (%)" (rect 132 93 294 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "23/2" (rect 74 107 164 225)(font "Arial" ))
+		(text "0.00" (rect 104 107 224 225)(font "Arial" ))
+		(text "50.00" (rect 136 107 293 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "23/2" (rect 74 121 164 253)(font "Arial" ))
+		(text "0.00" (rect 104 121 224 253)(font "Arial" ))
+		(text "50.00" (rect 136 121 293 253)(font "Arial" ))
+		(text "c2" (rect 54 135 116 281)(font "Arial" ))
+		(text "23/2" (rect 74 135 164 281)(font "Arial" ))
+		(text "0.00" (rect 104 135 224 281)(font "Arial" ))
+		(text "50.00" (rect 136 135 293 281)(font "Arial" ))
+		(line (pt 0 0)(pt 249 0))
+		(line (pt 249 0)(pt 249 185))
+		(line (pt 0 185)(pt 249 185))
+		(line (pt 0 0)(pt 0 185))
+		(line (pt 48 91)(pt 164 91))
+		(line (pt 48 104)(pt 164 104))
+		(line (pt 48 118)(pt 164 118))
+		(line (pt 48 132)(pt 164 132))
+		(line (pt 48 146)(pt 164 146))
+		(line (pt 48 91)(pt 48 146))
+		(line (pt 69 91)(pt 69 146)(line_width 3))
+		(line (pt 95 91)(pt 95 146)(line_width 3))
+		(line (pt 129 91)(pt 129 146)(line_width 3))
+		(line (pt 163 91)(pt 163 146))
+		(line (pt 40 48)(pt 199 48))
+		(line (pt 199 48)(pt 199 167))
+		(line (pt 40 167)(pt 199 167))
+		(line (pt 40 48)(pt 40 167))
+		(line (pt 247 64)(pt 199 64))
+		(line (pt 247 80)(pt 199 80))
+		(line (pt 247 96)(pt 199 96))
+		(line (pt 247 112)(pt 199 112))
+	)
+)
Index: unmerged/core/mcc216/pll.vhd
===================================================================
--- unmerged/core/mcc216/pll.vhd	(nonexistent)
+++ unmerged/core/mcc216/pll.vhd	(revision 1)
@@ -0,0 +1,424 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 2,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 2,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 2,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "20"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "57.500000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: unmerged/core/mcc216/pokey_mixer.vhdl
===================================================================
--- unmerged/core/mcc216/pokey_mixer.vhdl	(nonexistent)
+++ unmerged/core/mcc216/pokey_mixer.vhdl	(revision 1)
@@ -0,0 +1,231 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_mixer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
+		
+	CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	GTIA_SOUND : IN STD_LOGIC;
+	
+	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+);
+END pokey_mixer;
+
+ARCHITECTURE vhdl OF pokey_mixer IS
+	signal volume_reg : std_logic_vector(15 downto 0);
+	signal volume_next : std_logic_vector(15 downto 0);
+	
+	signal volume_sum : std_logic_vector(5 downto 0);
+	
+	signal channel_0_en : std_logic_vector(3 downto 0);
+	signal channel_1_en : std_logic_vector(3 downto 0);
+	signal channel_2_en : std_logic_vector(3 downto 0);
+	signal channel_3_en : std_logic_vector(3 downto 0);
+	
+	signal gtia_en : std_logic_vector(5 downto 0);
+BEGIN
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			volume_reg <= volume_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(channel_enable,channel_0,channel_1,channel_2,channel_3)
+	begin
+		channel_0_en <= channel_0;
+		channel_1_en <= channel_1;
+		channel_2_en <= channel_2;
+		channel_3_en <= channel_3;
+	
+--		if (channel_enable(3)='0') then
+--			channel_0_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(2)='0') then
+--			channel_1_en <= X"0";
+--		end if;
+--
+--		if (channel_enable(1)='0') then
+--			channel_2_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(0)='0') then
+--			channel_3_en <= X"0";
+--		end if;
+	end process;
+	
+	gtia_en <= "0000"&gtia_sound&gtia_sound;  -- only room for 3 more! TODO, regenerate...
+	
+	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
+	begin
+		volume_sum <= 
+			std_logic_vector
+			(
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_0_en)
+						+ unsigned('0'&CHANNEL_1_en)
+					)) 
+					+ 
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_2_en) + 
+						unsigned('0'&CHANNEL_3_en)
+					))
+					+ 
+					unsigned(gtia_en)
+			);
+	end process;
+	
+	process (volume_sum)
+	begin
+		case volume_sum is 
+			when "000000" =>
+				volume_next <= X"0000";
+			when "000001" =>
+				volume_next <= X"05e4";
+			when "000010" =>
+				volume_next <= X"0b90";
+			when "000011" =>
+				volume_next <= X"1107";
+			when "000100" =>
+				volume_next <= X"1649";
+			when "000101" =>
+				volume_next <= X"1b57";
+			when "000110" =>
+				volume_next <= X"2032";
+			when "000111" =>
+				volume_next <= X"24db";
+			when "001000" =>
+				volume_next <= X"2954";
+			when "001001" =>
+				volume_next <= X"2d9d";
+			when "001010" =>
+				volume_next <= X"31b8";
+			when "001011" =>
+				volume_next <= X"35a6";
+			when "001100" =>
+				volume_next <= X"3968";
+			when "001101" =>
+				volume_next <= X"3cff";
+			when "001110" =>
+				volume_next <= X"406b";
+			when "001111" =>
+				volume_next <= X"43af";
+			when "010000" =>
+				volume_next <= X"46cc";
+			when "010001" =>
+				volume_next <= X"49c2";
+			when "010010" =>
+				volume_next <= X"4c92";
+			when "010011" =>
+				volume_next <= X"4f3e";
+			when "010100" =>
+				volume_next <= X"51c7";
+			when "010101" =>
+				volume_next <= X"542d";
+			when "010110" =>
+				volume_next <= X"5673";
+			when "010111" =>
+				volume_next <= X"5898";
+			when "011000" =>
+				volume_next <= X"5a9f";
+			when "011001" =>
+				volume_next <= X"5c88";
+			when "011010" =>
+				volume_next <= X"5e55";
+			when "011011" =>
+				volume_next <= X"6006";
+			when "011100" =>
+				volume_next <= X"619d";
+			when "011101" =>
+				volume_next <= X"631a";
+			when "011110" =>
+				volume_next <= X"647f";
+			when "011111" =>
+				volume_next <= X"65ce";
+			when "100000" =>
+				volume_next <= X"6706";
+			when "100001" =>
+				volume_next <= X"682a";
+			when "100010" =>
+				volume_next <= X"6939";
+			when "100011" =>
+				volume_next <= X"6a37";
+			when "100100" =>
+				volume_next <= X"6b22";
+			when "100101" =>
+				volume_next <= X"6bfe";
+			when "100110" =>
+				volume_next <= X"6cca";
+			when "100111" =>
+				volume_next <= X"6d88";
+			when "101000" =>
+				volume_next <= X"6e38";
+			when "101001" =>
+				volume_next <= X"6edd";
+			when "101010" =>
+				volume_next <= X"6f77";
+			when "101011" =>
+				volume_next <= X"7008";
+			when "101100" =>
+				volume_next <= X"708f";
+			when "101101" =>
+				volume_next <= X"710f";
+			when "101110" =>
+				volume_next <= X"7189";
+			when "101111" =>
+				volume_next <= X"71fe";
+			when "110000" =>
+				volume_next <= X"726e";
+			when "110001" =>
+				volume_next <= X"72db";
+			when "110010" =>
+				volume_next <= X"7347";
+			when "110011" =>
+				volume_next <= X"73b1";
+			when "110100" =>
+				volume_next <= X"741c";
+			when "110101" =>
+				volume_next <= X"7488";
+			when "110110" =>
+				volume_next <= X"74f6";
+			when "110111" =>
+				volume_next <= X"7568";
+			when "111000" =>
+				volume_next <= X"75df";
+			when "111001" =>
+				volume_next <= X"765c";
+			when "111010" =>
+				volume_next <= X"76df";
+			when "111011" =>
+				volume_next <= X"776b";
+			when "111100" =>
+				volume_next <= X"7800";				
+			when others =>
+				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+		end case;
+		
+	end process;
+			
+	-- output
+	volume_out <= volume_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/hq_dac.v
===================================================================
--- unmerged/core/mcc216/hq_dac.v	(nonexistent)
+++ unmerged/core/mcc216/hq_dac.v	(revision 1)
@@ -0,0 +1,100 @@
+`timescale 1ns / 1ps
+
+// This module is a third order delta/sigma modulator
+// It uses no multiply only shifts by 1, 2 or 13
+// There are only 7 adders used, it takes around 110 LUTs
+module hq_dac
+(
+  input         reset,
+  input         clk,
+  input         clk_ena,
+  input  [19:0] pcm_in,
+  output reg    dac_out
+);
+
+// ======================================
+// ============== Stage #1 ==============
+// ======================================
+wire [23:0] w_data_in_p0;
+wire [23:0] w_data_err_p0;
+wire [23:0] w_data_int_p0;
+reg  [23:0] r_data_fwd_p1;
+
+// PCM input extended to 24 bits
+assign w_data_in_p0  = { {4{pcm_in[19]}}, pcm_in };
+
+// Error between the input and the quantizer output
+assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
+
+// First integrator adder
+assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+                     + r_data_fwd_p1;
+
+// First integrator forward delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_fwd_p1 <= 24'd0;
+  else if (clk_ena)
+    r_data_fwd_p1 <= w_data_int_p0;
+
+// ======================================
+// ============== Stage #2 ==============
+// ======================================
+wire [23:0] w_data_fb1_p1;
+wire [23:0] w_data_fb2_p1;
+wire [23:0] w_data_lpf_p1;
+reg  [23:0] r_data_lpf_p2;
+
+// Feedback from the quantizer output
+assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
+                     - { {3{w_data_qt_p2[23]}},  w_data_qt_p2[22:2] }; // Divide by 4
+
+// Feedback from the third stage
+assign w_data_fb2_p1 = w_data_fb1_p1
+                     - { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
+
+// Low pass filter
+assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
+
+// Low pass filter feedback delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_lpf_p2 <= 24'd0;
+  else if (clk_ena)
+    r_data_lpf_p2 <= w_data_lpf_p1;
+
+// ======================================
+// ============== Stage #3 ==============
+// ======================================
+wire [23:0] w_data_fb3_p1;
+wire [23:0] w_data_int_p1;
+reg  [23:0] r_data_fwd_p2;
+
+// Feedback from the quantizer output
+assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
+                     - { {2{w_data_qt_p2[23]}},  w_data_qt_p2[22:1] }; // Divide by 2
+
+// Second integrator adder
+assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
+
+// Second integrator forward delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_fwd_p2 <= 24'd0;
+  else if (clk_ena)
+    r_data_fwd_p2 <= w_data_int_p1;
+
+// =====================================
+// ========== 1-bit quantizer ==========
+// =====================================
+wire [23:0] w_data_qt_p2;
+
+assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
+
+always @(posedge reset or posedge clk)
+  if (reset)
+    dac_out <= 1'b0;
+  else if (clk_ena)
+    dac_out <= ~r_data_fwd_p2[23];
+
+endmodule
Index: unmerged/core/mcc216/internalromram.vhd
===================================================================
--- unmerged/core/mcc216/internalromram.vhd	(nonexistent)
+++ unmerged/core/mcc216/internalromram.vhd	(revision 1)
@@ -0,0 +1,99 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+END internalromram;
+
+architecture vhdl of internalromram is
+component ramint IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+component romlo IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+component romhi IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+	signal rom_request_reg : std_logic;
+	signal ram_request_reg : std_logic;
+	
+	signal ROMLO_DATA : std_logic_vector(7 downto 0);
+	signal ROMHI_DATA : std_logic_vector(7 downto 0);
+	
+	signal RAM_WR_ENABLE_REAL : std_logic;
+	signal IRAM_DATA : std_logic_vector(7 downto 0);
+
+begin
+	process(clock,reset_n)
+	begin
+		if (reset_n ='0') then
+			rom_request_reg <= '0';
+			ram_request_reg <= '0';
+		elsif (clock'event and clock='1') then
+			rom_request_reg <= rom_request;
+			ram_request_reg <= ram_request;
+		end if;
+	end process;
+
+	rom_request_complete <= rom_request_reg;
+	ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
+	romlo1 : romlo
+	PORT MAP(clock => clock,
+			 address => rom_addr(10 downto 0),
+			 q => ROMLO_data
+			 );	
+	romhi1 : romhi
+	PORT MAP(clock => clock,
+			 address => rom_addr(12 downto 0),
+			 q => ROMHI_data
+			 );
+	
+	ramint1 : ramint
+	PORT MAP(clock => clock,
+			 address => ram_addr(12 downto 0),
+			 data => ram_data_in(7 downto 0),
+			 wren => RAM_WR_ENABLE_REAL,
+			 q => iram_data
+			 );	
+	ram_request_complete <= ram_request_reg;
+	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
+	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/pia.vhdl
===================================================================
--- unmerged/core/mcc216/pia.vhdl	(nonexistent)
+++ unmerged/core/mcc216/pia.vhdl	(revision 1)
@@ -0,0 +1,402 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;	
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- pull up - i.e. 0 driven only
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC
+);
+END pia;
+
+ARCHITECTURE vhdl OF pia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	signal addr_decoded : std_logic_vector(3 downto 0);
+	
+	signal porta_output_next : std_logic_vector(7 downto 0);
+	signal porta_output_reg : std_logic_vector(7 downto 0);
+	signal porta_input_reg : std_logic_vector(7 downto 0);
+	signal porta_input_next : std_logic_vector(7 downto 0);
+
+	signal porta_direction_next : std_logic_vector(7 downto 0);
+	signal porta_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal porta_control_next : std_logic_vector(5 downto 0);
+	signal porta_control_reg : std_logic_vector(5 downto 0);
+	
+	signal portb_output_next : std_logic_vector(7 downto 0);
+	signal portb_output_reg : std_logic_vector(7 downto 0);
+	signal portb_input_reg : std_logic_vector(7 downto 0);
+	signal portb_input_next : std_logic_vector(7 downto 0);	
+
+	signal portb_direction_next : std_logic_vector(7 downto 0);
+	signal portb_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal portb_control_next : std_logic_vector(5 downto 0);
+	signal portb_control_reg : std_logic_vector(5 downto 0);
+	
+	signal irqa_next : std_logic_vector(1 downto 0);
+	signal irqa_reg : std_logic_vector(1 downto 0);
+	signal irqb_next : std_logic_vector(1 downto 0);
+	signal irqb_reg : std_logic_vector(1 downto 0);
+	
+	signal CA1_reg : std_logic;
+	signal CA2_reg : std_logic;
+	signal CB1_reg : std_logic;
+	signal CB2_reg : std_logic;
+
+	signal CA2_output_next : std_logic;
+	signal CA2_output_reg : std_logic;
+	signal CB2_output_next : std_logic;
+	signal CB2_output_reg : std_logic;
+	
+	signal read_ora : std_logic;
+	signal read_orb : std_logic;
+	
+	signal write_ora : std_logic;
+	signal write_orb : std_logic;
+
+	signal ca1_edge_next : std_logic;
+	signal ca1_edge_reg : std_logic;	
+	signal ca2_edge_next : std_logic;
+	signal ca2_edge_reg : std_logic;
+	
+	signal cb1_edge_next : std_logic;
+	signal cb1_edge_reg : std_logic;	
+	signal cb2_edge_next : std_logic;
+	signal cb2_edge_reg : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			porta_output_reg <= (others=>'0');
+			porta_input_reg <= (others=>'0');
+			porta_direction_reg <= (others=>'0'); -- default to input
+			porta_control_reg <= (others=>'0');
+			
+			portb_output_reg <= X"FF"; -- all high to ensure we have OS Rom enabled
+			portb_input_reg <= (others=>'0');
+			portb_direction_reg <= (others=>'1'); -- default to ouput
+			portb_control_reg <= (others=>'0');
+			
+			irqa_reg <= (others=>'0');
+			irqb_reg <= (others=>'0');
+			
+			CA1_reg	<= '0';
+			CA2_reg	<= '0';
+			CB1_reg	<= '0';
+			CB2_reg	<= '0';
+			
+			CA2_output_reg <= '0';
+			CB2_output_reg <= '0';
+			
+			ca1_edge_reg <= '0';
+			ca2_edge_reg <= '0';
+			
+			cb1_edge_reg <= '0';
+			cb2_edge_reg <= '0';
+			
+		elsif (clk'event and clk='1') then						
+			porta_output_reg <= porta_output_next;
+			porta_input_reg <= porta_input_next;
+			porta_direction_reg <= porta_direction_next;
+			porta_control_reg <= porta_control_next;
+			
+			portb_output_reg <= portb_output_next;
+			portb_input_reg <= PORTB_input_next;
+			portb_direction_reg <= portb_direction_next;
+			portb_control_reg <= portb_control_next;	
+	
+			irqa_reg <= irqa_next;
+			irqb_reg <= irqb_next;
+	
+			CA1_reg	<= CA1;
+			CA2_reg	<= CA2_in;
+			CB1_reg	<= CB1;
+			CB2_reg	<= CB2_in;
+			
+			CA2_output_reg <= CA2_output_next;
+			CB2_output_reg <= CB2_output_next;
+
+			ca1_edge_reg <= ca1_edge_next;			
+			ca2_edge_reg <= ca2_edge_next;
+			
+			cb1_edge_reg <= cb1_edge_next;			
+			cb2_edge_reg <= cb2_edge_next;			
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>2)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded, porta_output_reg, portb_output_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg)
+	begin
+		porta_output_next <= porta_output_reg;
+		portb_output_next <= portb_output_reg;
+		porta_direction_next <= porta_direction_reg;
+		portb_direction_next <= portb_direction_reg;
+		porta_control_next(5 downto 0) <= porta_control_reg(5 downto 0);
+		portb_control_next(5 downto 0) <= portb_control_reg(5 downto 0);
+		
+		write_ora <= '0';
+		write_orb <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					porta_output_next <= cpu_data_in;
+					write_ora <= '1';
+				else
+					porta_direction_next <= cpu_data_in;
+				end if;
+			end if;	
+
+			if(addr_decoded(1) = '1') then				
+				if (portb_control_reg(2) = '1') then
+					portb_output_next <= cpu_data_in;
+					write_orb <= '1';
+				else
+					portb_direction_next <= cpu_data_in;
+				end if;			
+			end if;						
+
+			if(addr_decoded(2) = '1') then	
+				porta_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;						
+			
+			if(addr_decoded(3) = '1') then		
+				portb_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;															
+
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded, en, porta_input_reg, portb_input_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg, irqa_reg, irqb_reg)
+	begin
+		data_out <= X"FF";
+		read_ora <= '0';
+		read_orb <= '0';
+
+		if (EN = '1') then -- since reads have an effect here...
+			if (addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					data_out <= porta_input_reg;
+					read_ora <= '1';
+				else
+					data_out <= porta_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(1) = '1') then
+				if (portb_control_reg(2) = '1') then
+					data_out <= portb_input_reg;
+					read_orb <= '1';
+				else
+					data_out <= portb_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(2) = '1') then			
+				data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
+			end if;
+
+			if (addr_decoded(3) = '1') then			
+				data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
+			end if;
+		end if;
+		
+	end process;
+	
+	-- irq handing
+	-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
+	process (irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1, CA1_reg, ca2_in, ca2_reg, ca1_edge_reg, ca2_edge_reg)
+	begin
+		irqa_next(1) <= irqa_reg(1) and not(read_ora);
+		irqa_next(0) <= irqa_reg(0) and not(read_ora);
+				
+		ca2_output_next <= ca2_output_reg;
+
+		if (CA1 = '1' and CA1_reg = '0') then
+			irqa_next(1) <= ca1_edge_reg;
+		end if;
+		if (CA1 = '0' and CA1_reg = '1') then
+			irqa_next(1) <= not(ca1_edge_reg);
+		end if;
+		
+		if (CA2_in = '1' and CA2_reg = '0') then
+			irqa_next(0) <= ca2_edge_reg;
+		end if;
+		
+		if (CA2_in = '0' and CA2_reg = '1') then
+			irqa_next(0) <= not(ca2_edge_reg);
+		end if;	
+		
+		ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (porta_control_next(5) = '0') then -- CA2 is an input					
+		else -- CA2 is an output
+			--irqa_next(0) <= '0';
+			
+			case porta_control_next(4 downto 3) is
+				when "10" =>
+					ca2_output_next <= '0'; -- direct control
+				when "11" =>
+					ca2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					else						
+						-- clock restore
+						ca2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					elsif (irqa_reg(1) = '1') then
+						-- ca1 restore
+						ca2_output_next <= '1';	
+					end if;				
+			end case;					
+		end if;
+
+	end process;
+
+	process (irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1, CB1_reg, cb2_in, cb2_reg, cb1_edge_reg, cb2_edge_reg)
+	begin
+		irqb_next(1) <= irqb_reg(1) and not(read_orb);
+		irqb_next(0) <= irqb_reg(0) and not(read_orb);
+				
+		cb2_output_next <= cb2_output_reg;
+
+		if (CB1 = '1' and CB1_reg = '0') then
+			irqb_next(1) <= cb1_edge_reg;
+		end if;
+		if (CB1 = '0' and CB1_reg = '1') then
+			irqb_next(1) <= not(cb1_edge_reg);
+		end if;
+		
+		if (CB2_in = '1' and CB2_reg = '0') then
+			irqb_next(0) <= cb2_edge_reg;
+		end if;
+		
+		if (CB2_in = '0' and CB2_reg = '1') then
+			irqb_next(0) <= not(cb2_edge_reg);
+		end if;	
+		
+		cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (portb_control_next(5) = '0') then -- CB2 is an input					
+		else -- CB2 is an output
+			--irqb_next(0) <= '0';
+			
+			case portb_control_next(4 downto 3) is
+				when "10" =>
+					cb2_output_next <= '0'; -- direct control
+				when "11" =>
+					cb2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					else						
+						-- clock restore
+						cb2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					elsif (irqb_reg(1) = '1') then
+						-- cb1 restore
+						cb2_output_next <= '1';	
+					end if;				
+			end case;					
+		end if;
+
+	end process;
+	
+	-- output
+		-- TODO - review if ca2 and cb2 are push pull or pull up...
+	--ca2 <= CA2_output_reg when porta_control_reg(5) = '1' else 'Z';
+	--cb2 <= CB2_output_reg when portb_control_reg(5) = '1' else 'Z';
+	ca2_out <= CA2_output_reg;
+	ca2_dir_out <= porta_control_reg(5);
+	cb2_out <= CB2_output_reg;
+	cb2_dir_out <= portb_control_reg(5);
+	
+	porta_out <= porta_output_reg;
+	porta_dir_out <= porta_direction_reg;
+	porta_input_next <= porta_in;
+
+	--portb_out <= portb_output_reg;
+	-- forced to 1 when in input mode - star raiders relies on this
+	portb_out(0) <= portb_output_reg(0) when portb_direction_reg(0)='1' else '1';
+	portb_out(1) <= portb_output_reg(1) when portb_direction_reg(1)='1' else '1';
+	portb_out(2) <= portb_output_reg(2) when portb_direction_reg(2)='1' else '1';
+	portb_out(3) <= portb_output_reg(3) when portb_direction_reg(3)='1' else '1';	
+	portb_out(4) <= portb_output_reg(4) when portb_direction_reg(4)='1' else '1';
+	portb_out(5) <= portb_output_reg(5) when portb_direction_reg(5)='1' else '1';
+	portb_out(6) <= portb_output_reg(6) when portb_direction_reg(6)='1' else '1';
+	portb_out(7) <= portb_output_reg(7) when portb_direction_reg(7)='1' else '1';		
+	portb_dir_out <= portb_direction_reg;
+	portb_input_next <= portb_in;
+	
+	irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
+	irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
+	
+end vhdl;
+
+
Index: unmerged/core/mcc216/pll.qip
===================================================================
--- unmerged/core/mcc216/pll.qip	(nonexistent)
+++ unmerged/core/mcc216/pll.qip	(revision 1)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: unmerged/core/mcc216/pokey_keyboard_scanner.vhdl
===================================================================
--- unmerged/core/mcc216/pokey_keyboard_scanner.vhdl	(nonexistent)
+++ unmerged/core/mcc216/pokey_keyboard_scanner.vhdl	(revision 1)
@@ -0,0 +1,179 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pokey_keyboard_scanner is
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	enable : in std_logic; -- typically hsync or equiv timing
+	keyboard_response : in std_logic_vector(1 downto 0);
+	debounce_disable : in std_logic;
+	scan_enable : in std_logic;
+	
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	
+	shift_pressed : out std_logic;
+	control_pressed : out std_logic;
+	break_pressed : out std_logic;
+	key_held : out std_logic;
+	keycode : out std_logic_vector(5 downto 0);
+	other_key_irq : out std_logic
+);
+end pokey_keyboard_scanner;
+
+architecture vhdl of pokey_keyboard_scanner is
+	signal bincnt_next : std_logic_vector(5 downto 0);
+	signal bincnt_reg : std_logic_vector(5 downto 0);
+
+	signal break_pressed_next : std_logic;
+	signal break_pressed_reg : std_logic;
+
+	signal shift_pressed_next : std_logic;
+	signal shift_pressed_reg : std_logic;
+	
+	signal control_pressed_next : std_logic;
+	signal control_pressed_reg : std_logic;	
+	
+	signal compare_latch_next : std_logic_vector(5 downto 0);
+	signal compare_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal keycode_latch_next : std_logic_vector(5 downto 0);
+	signal keycode_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal irq_next : std_logic;
+	signal irq_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal my_key : std_logic;
+	
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_wait_key : std_logic_vector(1 downto 0) := "00";
+	constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
+	constant state_valid_key : std_logic_vector(1 downto 0) := "10";
+	constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
+begin
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			bincnt_reg <= (others=>'0');
+			break_pressed_reg <= '0';
+			shift_pressed_reg <= '0';
+			control_pressed_reg <= '0';
+			compare_latch_reg <= (others=>'0');
+			keycode_latch_reg <= (others=>'1');
+			key_held_reg <= '0';
+			state_reg <= state_wait_key;
+			irq_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			bincnt_reg <= bincnt_next;
+			state_reg <= state_next;
+			break_pressed_reg <= break_pressed_next;
+			shift_pressed_reg <= shift_pressed_next;
+			control_pressed_reg <= control_pressed_next;
+			compare_latch_reg <= compare_latch_next;
+			keycode_latch_reg <= keycode_latch_next;
+			key_held_reg <= key_held_next;
+			state_reg <= state_next;
+			irq_reg <= irq_next;
+		end if;
+	end process;
+
+	process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_reg, shift_pressed_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
+	begin
+		bincnt_next <= bincnt_reg;
+		state_next <= state_reg;
+		compare_latch_next <= compare_latch_reg;
+		irq_next <= '0';
+		break_pressed_next <= break_pressed_reg;
+		shift_pressed_next <= shift_pressed_reg;
+		control_pressed_next <= control_pressed_reg;
+		keycode_latch_next <= keycode_latch_reg;
+		key_held_next <= key_held_reg;
+		
+		my_key <= '0';
+		if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
+			my_key <= '1';
+		end if;
+		
+		if (enable = '1' and scan_enable='1') then			
+			bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
+		
+			key_held_next<= '0';
+		
+			case state_reg is
+			when state_wait_key =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					state_next <= state_key_bounce;
+					compare_latch_next <= bincnt_reg;
+				end if;
+				
+			when state_key_bounce =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					if (my_key = '1') then -- same key
+						keycode_latch_next <= compare_latch_reg;
+						irq_next <= '1';
+						key_held_next<= '1';
+						state_next <= state_valid_key;
+					else -- different key (multiple keys pressed)
+						state_next <= state_wait_key;
+					end if;
+				else -- key not pressed
+					if (my_key = '1') then -- same key, no longer pressed
+						state_next <= state_wait_key;
+					end if;
+				end if;
+			
+			when state_valid_key =>
+				key_held_next<= '1';
+				if (my_key = '1') then -- only response to my key
+					if (keyboard_response(0) = '1') then -- no longer pressed
+						state_next <= state_key_debounce;
+					end if;					
+				end if;
+				
+			when state_key_debounce =>
+				if (my_key = '1') then
+					state_next <= state_wait_key;
+				end if;
+			end case;
+
+			if (bincnt_reg(3 downto 0)  = "0000") then
+				case bincnt_reg(5 downto 4) is
+				when "11" =>
+					break_pressed_next <= not(keyboard_response(1)); --0x30
+				when "01" =>
+					shift_pressed_next <= not(keyboard_response(1)); --0x10
+				when "00" =>
+					control_pressed_next <= not(keyboard_response(1)); -- 0x00
+				when others =>
+					--
+				end case;
+			end if;
+		end if;
+	end process;
+	
+	-- outputs
+	keyboard_scan <= not(bincnt_reg);
+	
+	key_held <= key_held_reg;	
+	keycode <= keycode_latch_reg;
+	break_pressed <= break_pressed_reg;
+	shift_pressed <= shift_pressed_reg;
+	control_pressed <= control_pressed_reg;
+	other_key_irq <= irq_reg;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/atari800core.vhd.bak
===================================================================
--- unmerged/core/mcc216/atari800core.vhd.bak	(nonexistent)
+++ unmerged/core/mcc216/atari800core.vhd.bak	(revision 1)
@@ -0,0 +1,1395 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLOCK_50 :  IN  STD_LOGIC;
+		AUD_BCLK :  IN  STD_LOGIC;
+		AUD_DACLRCK :  IN  STD_LOGIC;
+		PS2_CLK :  IN  STD_LOGIC;
+		PS2_DAT :  IN  STD_LOGIC;
+		UART_RXD :  IN  STD_LOGIC;
+		SD_DATA :  IN  STD_LOGIC;
+		I2C_SCLK :  INOUT  STD_LOGIC;
+		I2C_SDAT :  INOUT  STD_LOGIC;
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		AUD_XCK :  OUT  STD_LOGIC;
+		AUD_DACDAT :  OUT  STD_LOGIC;
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		FL_OE_N :  OUT  STD_LOGIC;
+		FL_WE_N :  OUT  STD_LOGIC;
+		FL_RST_N :  OUT  STD_LOGIC;
+		SRAM_CE_N :  OUT  STD_LOGIC;
+		SRAM_OE_N :  OUT  STD_LOGIC;
+		SRAM_WE_N :  OUT  STD_LOGIC;
+		SRAM_LB_N :  OUT  STD_LOGIC;
+		SRAM_UB_N :  OUT  STD_LOGIC;
+		UART_TXD :  OUT  STD_LOGIC;
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_THREE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT hexdecoder
+	PORT(CLK : IN STD_LOGIC;
+		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sram
+	PORT(WREN : IN STD_LOGIC;
+		 clk : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 request : IN STD_LOGIC;
+		 width_16bit : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_CE_N : OUT STD_LOGIC;
+		 SRAM_OE_N : OUT STD_LOGIC;
+		 SRAM_WE_N : OUT STD_LOGIC;
+		 SRAM_LB_N : OUT STD_LOGIC;
+		 SRAM_UB_N : OUT STD_LOGIC;
+		 complete : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT gpio
+	PORT(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+	);
+END COMPONENT;
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REPLY : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 REPLY : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 TURBO : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT i2c_loader
+GENERIC (device_address : INTEGER;
+			log2_divider : INTEGER;
+			num_retries : INTEGER
+			);
+	PORT(CLK : IN STD_LOGIC;
+		 nRESET : IN STD_LOGIC;
+		 I2C_SCL : INOUT STD_LOGIC;
+		 I2C_SDA : INOUT STD_LOGIC;
+		 IS_DONE : OUT STD_LOGIC;
+		 IS_ERROR : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT flashrom
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_CE_N : OUT STD_LOGIC;
+		 FLASH_OE_N : OUT STD_LOGIC;
+		 FLASH_WE_N : OUT STD_LOGIC;
+		 FLASH_RESET_N : OUT STD_LOGIC;
+		 COMPLETE : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT i2sslave
+	PORT(CLK : IN STD_LOGIC;
+		 BCLK : IN STD_LOGIC;
+		 DACLRC : IN STD_LOGIC;
+		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 MCLK_2 : OUT STD_LOGIC;
+		 DACDAT : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+SIGNAL	CART_CCTL_N :  STD_LOGIC;
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	TURBO :  STD_LOGIC;
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+
+BEGIN 
+
+
+
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+
+b2v_hex0_inst : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(3 DOWNTO 0),
+		 DIGIT => HEX0);
+
+
+b2v_hex0_inst2 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(7 DOWNTO 4),
+		 DIGIT => HEX1);
+
+
+b2v_hex0_inst3 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(11 DOWNTO 8),
+		 DIGIT => HEX2);
+
+
+b2v_hex0_inst4 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(15 DOWNTO 12),
+		 DIGIT => HEX3);
+
+
+b2v_inst : sram
+PORT MAP(WREN => RAM_WRITE_ENABLE,
+		 clk => CLK,
+		 reset_n => RESET_N,
+		 request => RAM_REQUEST,
+		 width_16bit => WIDTH_16BIT_ACCESS,
+		 ADDRESS => RAM_ADDR,
+		 DIN => WRITE_DATA(15 DOWNTO 0),
+		 SRAM_DQ => SRAM_DQ,
+		 SRAM_CE_N => SRAM_CE_N,
+		 SRAM_OE_N => SRAM_OE_N,
+		 SRAM_WE_N => SRAM_WE_N,
+		 SRAM_LB_N => SRAM_LB_N,
+		 SRAM_UB_N => SRAM_UB_N,
+		 complete => RAM_REQUEST_COMPLETE,
+		 DOUT => RAM_DO,
+		 SRAM_ADDR => SRAM_ADDR);
+
+
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+
+b2v_inst10 : ledsw
+PORT MAP(CLK => CLK,
+		 KEY => KEY,
+		 SW => SW,
+		 SYNC_KEYS => SYNC_KEYS,
+		 SYNC_SWITCHES => SYNC_SWITCHES);
+
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2_CLK,
+		 PS2_DAT => PS2_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+b2v_inst18 : pokey_ps2_decoder
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_CODE => SYNTHESIZED_WIRE_11,
+		 KEY_HELD => KEY_HELD,
+		 SHIFT_PRESSED => SHIFT_PRESSED,
+		 BREAK_PRESSED => BREAK_PRESSED,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+		 KBCODE => KBCODE,
+		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
+
+gpio0_gen:
+   for I in 0 to 35 generate
+		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+   end generate gpio0_gen;
+
+gpio1_gen:
+   for I in 0 to 35 generate
+		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+   end generate gpio1_gen;
+	
+b2v_inst19 : gpio
+PORT MAP(clk => CLK,
+		 gpio_enable => GPIO_ENABLE,
+		 pot_reset => POT_RESET,
+		 virtual_keyheld => KEY_HELD,
+		 virtual_shift_pressed => SHIFT_PRESSED,
+		 virtual_control_pressed => KBCODE(7),
+		 virtual_break_pressed => BREAK_PRESSED,
+		 pbi_write_enable => PBI_WRITE_ENABLE,
+		 cart_request => CART_REQUEST,
+		 s4_n => CART_S4_n,
+		 s5_n => CART_S5_N,
+		 cctl_n => CART_CCTL_N,
+		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+		 GPIO_0_IN => GPIO_0,
+		 GPIO_0_OUT => GPIO_0_OUT,
+		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+		 GPIO_1_IN => GPIO_1,
+		 GPIO_1_OUT => GPIO_1_OUT,
+		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN,
+		 pbi_addr_out => PBI_ADDR,
+		 porta_out => PORTA_OUT,
+		 porta_output => PORTA_DIR_OUT,
+		 virtual_keycode => KBCODE(5 DOWNTO 0),
+		 virtual_stick_in => VIRTUAL_STICKS,
+		 virtual_trig_in => VIRTUAL_TRIGGERS,
+		 lightpen => LIGHTPEN,
+		 cart_complete => CART_REQUEST_COMPLETE,
+		 rd4 => CART_RD4,
+		 rd5 => CART_RD5,
+		 cart_data_read => CART_ROM_DO,
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 porta_in => GPIO_PORTA_IN,
+		 pot_in => POT_IN,
+		 trig_in => TRIGGERS,
+		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_OUT => CA2_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_OUT => CB2_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 SIO_IN => GPIO_SIO_IN,
+		 SIO_OUT => GPIO_SIO_OUT
+		 );
+
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REPLY => SDRAM_REPLY,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT,
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT,
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA);
+
+
+b2v_inst20 : sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => DRAM_DQ,
+		 REPLY => SDRAM_REPLY,
+		 SDRAM_BA0 => DRAM_BA_0,
+		 SDRAM_BA1 => DRAM_BA_1,
+		 SDRAM_CKE => DRAM_CKE,
+		 SDRAM_CS_N => DRAM_CS_N,
+		 SDRAM_RAS_N => DRAM_RAS_N,
+		 SDRAM_CAS_N => DRAM_CAS_N,
+		 SDRAM_WE_N => DRAM_WE_N,
+		 SDRAM_ldqm => DRAM_LDQM,
+		 SDRAM_udqm => DRAM_UDQM,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => DRAM_ADDR);
+
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DATA,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_THREE,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG,
+		 LEDR => LEDR,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX);
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst3 : i2c_loader
+GENERIC MAP(device_address => 26,
+			log2_divider => 6,
+			num_retries => 0
+			)
+PORT MAP(CLK => CLK,
+		 nRESET => RESET_N,
+		 I2C_SCL => I2C_SCLK,
+		 I2C_SDA => I2C_SDAT);
+
+
+b2v_inst4 : flashrom
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 REQUEST => ROM_REQUEST,
+		 ADDRESS => ROM_ADDR,
+		 FLASH_D => FL_DQ,
+		 FLASH_OE_N => FL_OE_N,
+		 FLASH_WE_N => FL_WE_N,
+		 FLASH_RESET_N => FL_RST_N,
+		 COMPLETE => ROM_REQUEST_COMPLETE,
+		 DOUT => ROM_DO,
+		 FLASH_ADDRESS => FL_ADDR);
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => CLOCK_50,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+
+
+b2v_inst6 : i2sslave
+PORT MAP(CLK => CLK,
+		 BCLK => AUD_BCLK,
+		 DACLRC => AUD_DACLRCK,
+		 LEFT_IN => AUDIO_LEFT,
+		 RIGHT_IN => AUDIO_RIGHT,
+		 MCLK_2 => AUD_XCK,
+		 DACDAT => AUD_DACDAT);
+
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => UART_RXD,
+		 SIO_IN2 => GPIO_SIO_IN,
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => TRIGGERS(0),
+		 TRIG1 => TRIGGERS(1),
+		 TRIG2 => TRIGGERS(2),
+		 TRIG3 => TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+
+END bdf_type;
\ No newline at end of file
Index: unmerged/core/mcc216/cpu_6510.vhd
===================================================================
--- unmerged/core/mcc216/cpu_6510.vhd	(nonexistent)
+++ unmerged/core/mcc216/cpu_6510.vhd	(revision 1)
@@ -0,0 +1,201 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- 6510 wrapper for 65xx core
+-- Adds 8 bit I/O port mapped at addresses $0000 to $0001
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_6510 is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean;
+		emulate_bitfade : boolean
+	);
+	port (
+		clk : in std_logic;
+		ena_1khz : in std_logic := '0';
+		enable : in std_logic;
+		halt : in std_logic;
+		reset : in std_logic;
+		nmi_n : in std_logic;
+		irq_n : in std_logic;
+
+		we : out std_logic;
+		a : out unsigned(15 downto 0);
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+
+		diIO : in unsigned(7 downto 0);
+		doIO : out unsigned(7 downto 0);
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0);
+		debug_io : out unsigned(7 downto 0)
+	);
+end cpu_6510;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_6510 is
+	signal localA : unsigned(15 downto 0);
+	signal localD : unsigned(7 downto 0);
+	signal localQ : unsigned(7 downto 0);
+	signal localWe : std_logic;
+
+	signal currentIO : unsigned(7 downto 0);
+	signal ioDir : unsigned(7 downto 0);
+	signal ioData : unsigned(7 downto 0);
+	
+	signal accessIO : std_logic;
+	signal ioFade : unsigned(7 downto 0) := (others => '0');
+begin
+	cpuInstance: entity work.cpu_65xx
+		generic map (
+			pipelineOpcode => pipelineOpcode,
+			pipelineAluMux => pipelineAluMux,
+			pipelineAluOut => pipelineAluOut
+		)
+		port map (
+			clk => clk,
+			enable => enable,
+			halt => halt,
+			reset => reset,
+			nmi_n => nmi_n,
+			irq_n => irq_n,
+
+			d => localD,
+			q => localQ,
+			addr => localA,
+			we => localWe,
+
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugY,
+			debugS => debugS,
+			debug_flags => debug_flags
+		);
+	
+	MyBitfade: if emulate_bitfade generate
+		bitfade7 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(7),
+				d => ioData(7),
+				q => ioFade(7)
+			);
+		bitfade6 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(6),
+				d => ioData(6),
+				q => ioFade(6)
+			);
+		bitfade3 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(3),
+				d => ioData(3),
+				q => ioFade(3)
+			);
+	end generate;
+	
+	process(localA)
+	begin
+		accessIO <= '0';
+		if localA(15 downto 1) = 0 then
+			accessIO <= '1';
+		end if;
+	end process;
+	
+	process(d, localA, ioDir, currentIO, accessIO)
+	begin
+		localD <= d;
+		if accessIO = '1' then
+			if localA(0) = '0' then
+				localD <= ioDir;
+			else
+				localD <= currentIO;
+			end if;
+		end if;
+	end process;
+	
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if accessIO = '1' then
+				if localWe = '1'
+				and enable = '1' then
+					if localA(0) = '0' then
+						ioDir <= localQ;
+					else
+						ioData <= localQ;
+					end if;
+				end if;
+			end if;
+			if reset = '1' then
+				ioDir <= (others => '0');
+			end if;
+		end if;
+	end process;
+	
+	process(ioDir, ioData, diIO)
+	begin
+		for i in 0 to 7 loop
+			if ioDir(i) = '0' then
+				currentIO(i) <= diIO(i);
+			else
+				currentIO(i) <= ioData(i);
+			end if;
+		end loop;
+		if emulate_bitfade then
+			currentIO(7) <= ioFade(7);
+			currentIO(6) <= ioFade(6);
+			currentIO(3) <= ioFade(3);
+		end if;
+	end process;
+	
+	-- Cunnect zee wires
+	a <= localA;
+	q <= localQ;
+	we <= localWe;
+	doIO <= currentIO;
+	debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
+end architecture;
Index: unmerged/core/mcc216/delay_line.vhdl
===================================================================
--- unmerged/core/mcc216/delay_line.vhdl	(nonexistent)
+++ unmerged/core/mcc216/delay_line.vhdl	(revision 1)
@@ -0,0 +1,57 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY delay_line IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC
+);
+END delay_line;
+
+ARCHITECTURE vhdl OF delay_line IS
+	signal shift_reg : std_logic_vector(COUNT-1 downto 0);
+	signal shift_next : std_logic_vector(COUNT-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>'0');
+		end if;		
+	end process;
+	
+	-- output
+	data_out <= shift_reg(0) and enable;
+		
+END vhdl;
Index: unmerged/core/mcc216/gtia.vhdl
===================================================================
--- unmerged/core/mcc216/gtia.vhdl	(nonexistent)
+++ unmerged/core/mcc216/gtia.vhdl	(revision 1)
@@ -0,0 +1,1556 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	CPU_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_FETCH : IN STD_LOGIC;
+	
+	CPU_ENABLE_ORIGINAL : in std_logic;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	PAL : IN STD_LOGIC;
+	
+	-- ANTIC interface
+	COLOUR_CLOCK_ORIGINAL : in std_logic;
+	COLOUR_CLOCK : in std_logic;
+	COLOUR_CLOCK_HIGHRES : in std_logic;
+	AN : IN STD_LOGIC_VECTOR(2 downto 0);
+	
+	-- keyboard interface
+	CONSOL_START : IN STD_LOGIC;
+	CONSOL_SELECT : IN STD_LOGIC;
+	CONSOL_OPTION : IN STD_LOGIC;
+	
+	-- keyboard interface
+	TRIG0 : IN STD_LOGIC;
+	TRIG1 : IN STD_LOGIC;
+	TRIG2 : IN STD_LOGIC;
+	TRIG3 : IN STD_LOGIC;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	-- TO scandoubler...
+	COLOUR_out : out std_logic_vector(7 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic;
+	
+	-- To speaker
+	sound : out std_logic
+);
+END gtia;
+
+ARCHITECTURE vhdl OF gtia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component gtia_player IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : in std_logic;
+		
+		COLOUR_ENABLE : IN STD_LOGIC;
+		LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+		PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+		SIZE : in std_logic_vector(1 downto 0);
+		bitmap : in std_logic_vector(7 downto 0);
+		
+		output : out std_logic
+	);
+	END component;
+	
+	component gtia_priority IS
+	PORT 
+	( 
+		CLK : in std_logic;
+		colour_enable : in std_logic;
+		PRIOR : in std_logic_vector(7 downto 0);
+		P0 : in std_logic;
+		P1 : in std_logic;
+		P2	: in std_logic;
+		P3 : in std_logic;
+		PF0 : in std_logic;
+		PF1 : in std_logic;
+		PF2 : in std_logic;
+		PF3 : in std_logic;
+		BK : in std_logic;
+		
+		P0_OUT : out std_logic;
+		P1_OUT : out std_logic;
+		P2_OUT : out std_logic;
+		P3_OUT : out std_logic;
+		PF0_OUT : out std_logic;
+		PF1_OUT : out std_logic;
+		PF2_OUT : out std_logic;
+		PF3_OUT : out std_logic;
+		BK_OUT : out std_logic
+	);
+	END component;	
+	
+	signal addr_decoded : std_logic_vector(31 downto 0);
+	
+	signal hposp0_raw_next : std_logic_vector(7 downto 0);
+	signal hposp0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp1_raw_next : std_logic_vector(7 downto 0);
+	signal hposp1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp2_raw_next : std_logic_vector(7 downto 0);
+	signal hposp2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp3_raw_next : std_logic_vector(7 downto 0);
+	signal hposp3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp3_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal hposm0_raw_next : std_logic_vector(7 downto 0);
+	signal hposm0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm1_raw_next : std_logic_vector(7 downto 0);
+	signal hposm1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm2_raw_next : std_logic_vector(7 downto 0);
+	signal hposm2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm3_raw_next : std_logic_vector(7 downto 0);
+	signal hposm3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm3_delayed_reg : std_logic_vector(7 downto 0);	
+	
+	signal sizep0_raw_next : std_logic_vector(1 downto 0);
+	signal sizep0_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep1_raw_next : std_logic_vector(1 downto 0);
+	signal sizep1_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep2_raw_next : std_logic_vector(1 downto 0);
+	signal sizep2_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep3_raw_next : std_logic_vector(1 downto 0);
+	signal sizep3_raw_reg : std_logic_vector(1 downto 0);
+
+	signal sizem_raw_next : std_logic_vector(7 downto 0);
+	signal sizem_raw_reg : std_logic_vector(7 downto 0);
+
+	signal sizep0_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep1_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep2_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep3_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizem_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal grafp0_next : std_logic_vector(7 downto 0);
+	signal grafp0_reg : std_logic_vector(7 downto 0);
+	signal grafp1_next : std_logic_vector(7 downto 0);
+	signal grafp1_reg : std_logic_vector(7 downto 0);
+	signal grafp2_next : std_logic_vector(7 downto 0);
+	signal grafp2_reg : std_logic_vector(7 downto 0);
+	signal grafp3_next : std_logic_vector(7 downto 0);
+	signal grafp3_reg : std_logic_vector(7 downto 0);
+	
+	signal grafm_next : std_logic_vector(7 downto 0);
+	signal grafm_reg : std_logic_vector(7 downto 0);
+
+	signal colpm0_raw_next : std_logic_vector(7 downto 1);
+	signal colpm0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm1_raw_next : std_logic_vector(7 downto 1);
+	signal colpm1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm2_raw_next : std_logic_vector(7 downto 1);
+	signal colpm2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm3_raw_next : std_logic_vector(7 downto 1);
+	signal colpm3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colpf0_raw_next : std_logic_vector(7 downto 1);
+	signal colpf0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf1_raw_next : std_logic_vector(7 downto 1);
+	signal colpf1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf2_raw_next : std_logic_vector(7 downto 1);
+	signal colpf2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf3_raw_next : std_logic_vector(7 downto 1);
+	signal colpf3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colbk_raw_next : std_logic_vector(7 downto 1);
+	signal colbk_raw_reg : std_logic_vector(7 downto 1);
+	signal colbk_delayed_reg : std_logic_vector(7 downto 1);	
+	
+	signal prior_raw_next : std_logic_vector(7 downto 0);
+	signal prior_raw_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed2_reg : std_logic_vector(7 downto 6);
+	
+	signal vdelay_next : std_logic_vector(7 downto 0);
+	signal vdelay_reg : std_logic_vector(7 downto 0);
+
+	signal gractl_next : std_logic_vector(2 downto 0);
+	signal gractl_reg : std_logic_vector(2 downto 0);
+	
+	signal consol_output_next : std_logic_vector(3 downto 0);
+	signal consol_output_reg : std_logic_vector(3 downto 0);
+	
+	signal trig0_next : std_logic;
+	signal trig0_reg : std_logic;
+	signal trig1_next : std_logic;
+	signal trig1_reg : std_logic;
+	signal trig2_next : std_logic;
+	signal trig2_reg : std_logic;
+	signal trig3_next : std_logic;
+	signal trig3_reg : std_logic;
+	
+	-- collisions
+	signal hitclr_write : std_logic;
+	
+	signal m0pf_next : std_logic_vector(3 downto 0);
+	signal m0pf_reg : std_logic_vector(3 downto 0);
+	signal m1pf_next : std_logic_vector(3 downto 0);
+	signal m1pf_reg : std_logic_vector(3 downto 0);
+	signal m2pf_next : std_logic_vector(3 downto 0);
+	signal m2pf_reg : std_logic_vector(3 downto 0);
+	signal m3pf_next : std_logic_vector(3 downto 0);
+	signal m3pf_reg : std_logic_vector(3 downto 0);
+
+	signal m0pl_next : std_logic_vector(3 downto 0);
+	signal m0pl_reg : std_logic_vector(3 downto 0);
+	signal m1pl_next : std_logic_vector(3 downto 0);
+	signal m1pl_reg : std_logic_vector(3 downto 0);
+	signal m2pl_next : std_logic_vector(3 downto 0);
+	signal m2pl_reg : std_logic_vector(3 downto 0);
+	signal m3pl_next : std_logic_vector(3 downto 0);
+	signal m3pl_reg : std_logic_vector(3 downto 0);
+	
+	signal p0pf_next : std_logic_vector(3 downto 0);
+	signal p0pf_reg : std_logic_vector(3 downto 0);
+	signal p1pf_next : std_logic_vector(3 downto 0);
+	signal p1pf_reg : std_logic_vector(3 downto 0);
+	signal p2pf_next : std_logic_vector(3 downto 0);
+	signal p2pf_reg : std_logic_vector(3 downto 0);
+	signal p3pf_next : std_logic_vector(3 downto 0);
+	signal p3pf_reg : std_logic_vector(3 downto 0);	
+	
+	signal p0pl_next : std_logic_vector(3 downto 0);
+	signal p0pl_reg : std_logic_vector(3 downto 0);
+	signal p1pl_next : std_logic_vector(3 downto 0);
+	signal p1pl_reg : std_logic_vector(3 downto 0);
+	signal p2pl_next : std_logic_vector(3 downto 0);
+	signal p2pl_reg : std_logic_vector(3 downto 0);
+	signal p3pl_next : std_logic_vector(3 downto 0);
+	signal p3pl_reg : std_logic_vector(3 downto 0);		
+	
+	-- priority
+	signal set_p0 : std_logic;
+	signal set_p1 : std_logic;
+	signal set_p2 : std_logic;
+	signal set_p3 : std_logic;
+	signal set_pf0 : std_logic;
+	signal set_pf1 : std_logic;
+	signal set_pf2 : std_logic;
+	signal set_pf3 : std_logic;
+	signal set_bk : std_logic;	
+	
+	-- ouput/sync
+	signal COLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal COLOUR_REG : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_REG : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+	
+	signal hsync_start : std_logic;
+	signal hsync_end : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	-- visible region (no collision detection outside this)
+	signal visible_live : std_logic;
+	
+	-- antic input decode
+	signal an_prev3_next : std_logic_vector(2 downto 0);
+	signal an_prev3_reg : std_logic_vector(2 downto 0);	
+	signal an_prev2_next : std_logic_vector(2 downto 0);
+	signal an_prev2_reg : std_logic_vector(2 downto 0);	
+	signal an_prev_next : std_logic_vector(2 downto 0);
+	signal an_prev_reg : std_logic_vector(2 downto 0);
+	
+	signal active_bk_modify_next : std_logic_vector(7 downto 0);
+	signal active_bk_modify_reg : std_logic_vector(7 downto 0);
+	signal active_bk_valid_next : std_logic_vector(7 downto 0);
+	signal active_bk_valid_reg : std_logic_vector(7 downto 0);
+	signal active_bk_live : std_logic;
+	signal active_pf0_live : std_logic;
+	signal active_pf1_live : std_logic;
+	signal active_pf2_live : std_logic;
+	signal active_pf2_collision_live : std_logic;
+	signal active_pf3_live : std_logic;
+	signal active_pf3_collision_live : std_logic;
+	signal active_pm0_live : std_logic;
+	signal active_pm1_live : std_logic;
+	signal active_pm2_live : std_logic;
+	signal active_pm3_live : std_logic;
+	
+	signal active_p0_live : std_logic;
+	signal active_p1_live : std_logic;
+	signal active_p2_live : std_logic;
+	signal active_p3_live : std_logic;
+	signal active_m0_live : std_logic;
+	signal active_m1_live : std_logic;
+	signal active_m2_live : std_logic;
+	signal active_m3_live : std_logic;
+	
+	signal active_hr_next : std_logic_vector(1 downto 0);
+	signal active_hr_reg : std_logic_vector(1 downto 0);
+	signal highres_next : std_logic;
+	signal highres_reg : std_logic;
+	
+	-- horizontal position counter
+	signal hpos_reg : std_logic_vector(7 downto 0);
+	signal reset_counter : std_logic;
+	signal counter_load_value : std_logic_vector(7 downto 0);
+	
+	-- sub colour clock highres mode	
+	signal trigger_secondhalf : std_logic;
+	
+	-- pmg dma
+	signal grafm_dma_load : std_logic;
+	signal grafm_dma_next : std_logic_vector(7 downto 0);
+	signal grafp0_dma_load : std_logic;
+	signal grafp0_dma_next : std_logic_vector(7 downto 0);
+	signal grafp1_dma_load : std_logic;
+	signal grafp1_dma_next : std_logic_vector(7 downto 0);
+	signal grafp2_dma_load : std_logic;
+	signal grafp2_dma_next : std_logic_vector(7 downto 0);
+	signal grafp3_dma_load : std_logic;
+	signal grafp3_dma_next : std_logic_vector(7 downto 0);
+	signal odd_scanline_next : std_logic;
+	signal odd_scanline_reg : std_logic;
+	
+	signal pmg_dma_state_next : std_logic_vector(2 downto 0);
+	signal pmg_dma_state_reg : std_logic_vector(2 downto 0);
+	constant pmg_dma_missile : std_logic_vector(2 downto 0) := "000";
+	constant pmg_dma_player0 : std_logic_vector(2 downto 0) := "001";
+	constant pmg_dma_player1 : std_logic_vector(2 downto 0) := "010";
+	constant pmg_dma_player2 : std_logic_vector(2 downto 0) := "011";
+	constant pmg_dma_player3 : std_logic_vector(2 downto 0) := "100";
+	constant pmg_dma_done    : std_logic_vector(2 downto 0) := "101";	
+	constant pmg_dma_instruction : std_logic_vector(2 downto 0) := "110";	
+	
+	signal memory_ready : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			hposp0_raw_reg <= (others=>'0');
+			hposp1_raw_reg <= (others=>'0');
+			hposp2_raw_reg <= (others=>'0');
+			hposp3_raw_reg <= (others=>'0');
+
+			hposm0_raw_reg <= (others=>'0');
+			hposm1_raw_reg <= (others=>'0');
+			hposm2_raw_reg <= (others=>'0');
+			hposm3_raw_reg <= (others=>'0');			
+
+			sizep0_raw_reg <= (others=>'0');
+			sizep1_raw_reg <= (others=>'0');
+			sizep2_raw_reg <= (others=>'0');
+			sizep3_raw_reg <= (others=>'0');
+
+			sizem_raw_reg <= (others=>'0');
+			
+			grafp0_reg <= (others=>'0');
+			grafp1_reg <= (others=>'0');
+			grafp2_reg <= (others=>'0');
+			grafp3_reg <= (others=>'0');
+
+			grafm_reg <= (others=>'0');
+			
+			colpm0_raw_reg <= (others=>'0');
+			colpm1_raw_reg <= (others=>'0');
+			colpm2_raw_reg <= (others=>'0');
+			colpm3_raw_reg <= (others=>'0');
+
+			colpf0_raw_reg <= (others=>'0');
+			colpf1_raw_reg <= (others=>'0');
+			colpf2_raw_reg <= (others=>'0');
+			colpf3_raw_reg <= (others=>'0');
+			
+			colbk_raw_reg <= (others=>'0');
+			
+			prior_raw_reg <= (others=>'0');
+			
+			vdelay_reg <= (others=>'0');
+			
+			gractl_reg <= (others=>'0');
+			
+			consol_output_reg <= (others=>'1');
+			
+			COLOUR_REG <= (OTHERS=>'0');
+			HRCOLOUR_REG <= (OTHERS=>'0');
+			
+			vsync_reg <= '0';
+			hsync_reg <= '0';
+			hblank_reg <= '0';
+			
+			an_prev_reg <= (others=>'0');
+			an_prev2_reg <= (others=>'0');
+			an_prev3_reg <= (others=>'0');
+			
+			highres_reg <= '0';
+			active_hr_reg <= (others=>'0');
+			
+			trig0_reg <= '0';
+			trig1_reg <= '0';
+			trig2_reg <= '0';
+			trig3_reg <= '0';
+			
+			odd_scanline_reg <= '0';
+			
+			pmg_dma_state_reg <= pmg_dma_done;
+			
+			m0pf_reg <= (others=>'0');
+			m1pf_reg <= (others=>'0');
+			m2pf_reg <= (others=>'0');
+			m3pf_reg <= (others=>'0');
+			m0pl_reg <= (others=>'0');
+			m1pl_reg <= (others=>'0');
+			m2pl_reg <= (others=>'0');
+			m3pl_reg <= (others=>'0');
+			
+			p0pf_reg <= (others=>'0');
+			p1pf_reg <= (others=>'0');
+			p2pf_reg <= (others=>'0');
+			p3pf_reg <= (others=>'0');
+			p0pl_reg <= (others=>'0');
+			p1pl_reg <= (others=>'0');
+			p2pl_reg <= (others=>'0');
+			p3pl_reg <= (others=>'0');	
+			
+			active_bk_modify_reg <= (others=>'0');
+			active_bk_valid_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then										
+			hposp0_raw_reg <= hposp0_raw_next;
+			hposp1_raw_reg <= hposp1_raw_next;
+			hposp2_raw_reg <= hposp2_raw_next;
+			hposp3_raw_reg <= hposp3_raw_next;
+
+			hposm0_raw_reg <= hposm0_raw_next;
+			hposm1_raw_reg <= hposm1_raw_next;
+			hposm2_raw_reg <= hposm2_raw_next;
+			hposm3_raw_reg <= hposm3_raw_next;			
+
+			sizep0_raw_reg <= sizep0_raw_next;
+			sizep1_raw_reg <= sizep1_raw_next;
+			sizep2_raw_reg <= sizep2_raw_next;
+			sizep3_raw_reg <= sizep3_raw_next;
+
+			sizem_raw_reg <= sizem_raw_next;
+			
+			grafp0_reg <= grafp0_next;
+			grafp1_reg <= grafp1_next;
+			grafp2_reg <= grafp2_next;
+			grafp3_reg <= grafp3_next;
+
+			grafm_reg <= grafm_next;
+			
+			colpm0_raw_reg <= colpm0_raw_next;
+			colpm1_raw_reg <= colpm1_raw_next;
+			colpm2_raw_reg <= colpm2_raw_next;
+			colpm3_raw_reg <= colpm3_raw_next;
+
+			colpf0_raw_reg <= colpf0_raw_next;
+			colpf1_raw_reg <= colpf1_raw_next;
+			colpf2_raw_reg <= colpf2_raw_next;
+			colpf3_raw_reg <= colpf3_raw_next;
+			
+			colbk_raw_reg <= colbk_raw_next;
+			
+			prior_raw_reg <= prior_raw_next;
+			
+			vdelay_reg <= vdelay_next;
+			
+			gractl_reg <= gractl_next;
+			
+			consol_output_reg <= consol_output_next;		
+
+			COLOUR_REG <= colour_next;
+			HRCOLOUR_REG <= hrcolour_next;
+			
+			vsync_reg <= vsync_next;
+			hsync_reg <= hsync_next;
+			hblank_reg <= hblank_next;
+			
+			an_prev_reg <= an_prev_next;
+			an_prev2_reg <= an_prev2_next;
+			an_prev3_reg <= an_prev3_next;
+	
+			highres_reg <= highres_next;
+			active_hr_reg <= active_hr_next;
+			
+			trig0_reg <= trig0_next;
+			trig1_reg <= trig1_next;
+			trig2_reg <= trig2_next;
+			trig3_reg <= trig3_next;
+			
+			odd_scanline_reg <= odd_scanline_next;
+			
+			pmg_dma_state_reg <= pmg_dma_state_next;
+			
+			m0pf_reg <= m0pf_next;
+			m1pf_reg <= m1pf_next;
+			m2pf_reg <= m2pf_next;
+			m3pf_reg <= m3pf_next;
+			m0pl_reg <= m0pl_next;
+			m1pl_reg <= m1pl_next;
+			m2pl_reg <= m2pl_next;
+			m3pl_reg <= m3pl_next;
+			
+			p0pf_reg <= p0pf_next;
+			p1pf_reg <= p1pf_next;
+			p2pf_reg <= p2pf_next;
+			p3pf_reg <= p3pf_next;
+			p0pl_reg <= p0pl_next;
+			p1pl_reg <= p1pl_next;
+			p2pl_reg <= p2pl_next;
+			p3pl_reg <= p3pl_next;
+			
+			active_bk_modify_reg <= active_bk_modify_next;
+			active_bk_valid_reg <= active_bk_valid_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>5)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+		
+	-- decode antic input
+	process (AN, COLOUR_CLOCK, COLOUR_CLOCK_ORIGINAL, an_prev_reg, an_prev2_reg, an_prev3_reg, hblank_reg, vsync_reg, highres_reg, odd_scanline_reg, prior_delayed_reg, prior_delayed2_reg, hpos_reg, active_p0_live, active_p1_live, active_p2_live, active_p3_live, active_m0_live, active_m1_live, active_m2_live, active_m3_live, active_pf3_collision_live, active_bk_modify_reg, active_bk_modify_next, active_bk_valid_reg, active_hr_reg, visible_live)
+	begin	
+		hblank_next <= hblank_reg;
+		reset_counter <= '0';
+		counter_load_value <= (others=>'0');
+		vsync_next <= vsync_reg;
+		
+		odd_scanline_next <= odd_scanline_reg;
+			
+		-- NB high res mode gives pf2 - which is or of the two pixels
+		highres_next <= highres_reg;
+		
+		-- for gtia modes
+		an_prev_next <= an_prev_reg;
+		an_prev2_next <= an_prev2_reg;
+		an_prev3_next <= an_prev3_reg;
+		
+		-- decoded AN
+		visible_live <= '0';
+		
+		active_hr_next <= active_hr_reg;
+		
+		active_bk_modify_next <= active_bk_modify_reg;
+		active_bk_valid_next <= active_bk_valid_reg;
+		active_bk_live <= '0';
+		active_pf0_live <= '0';
+		active_pf1_live <= '0';
+		active_pf2_live <= '0';
+		active_pf2_collision_live <= '0';
+		active_pf3_live <= '0';
+		active_pf3_collision_live <= '0';
+		active_pm0_live <= '0';
+		active_pm1_live <= '0';
+		active_pm2_live <= '0';
+		active_pm3_live <= '0';
+		
+		if (COLOUR_CLOCK = '1') then	
+			visible_live <= '1';
+			vsync_next <= '0';
+			hblank_next <= '0';
+			an_prev_next <= an;
+			an_prev2_next <= an_prev_reg;
+			an_prev3_next <= an_prev2_reg;
+			
+			active_pm0_live <= active_p0_live or (active_m0_live and not(prior_delayed_reg(4)));
+			active_pm1_live <= active_p1_live or (active_m1_live and not(prior_delayed_reg(4)));
+			active_pm2_live <= active_p2_live or (active_m2_live and not(prior_delayed_reg(4)));
+			active_pm3_live <= active_p3_live or (active_m3_live and not(prior_delayed_reg(4)));			
+			
+			active_bk_modify_next <= (others=>'0');
+			active_bk_valid_next <= (others=>'1');
+			
+			active_hr_next <= (others=>'0');
+		
+			-- 000 background colour
+			-- 001 vsync
+			-- 01X hsync (low bit is high res mode - i.e. 2 pixels per colour clock)
+			-- 1XX colour 0 to colour 3
+			
+			-- in gtia modes then we listen for 2 colour clocks to get one pixels
+			-- 1ZY (giving signal ZYXV for 4 bit colour reg/luminance - unfortunately we only have 9 colour regs!)
+			-- 1XV
+			
+			if (highres_reg = '1') then
+				if (an(2) = '1') then
+					active_hr_next <= AN(1 downto 0);				
+				end if;
+				
+				active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= an(2);
+				active_pf2_collision_live <= an(2) and (an(1) or an(0));
+				active_pf3_collision_live <= '0';				
+			else								
+				-- gtia modes										
+				case prior_delayed_reg(7 downto 6) is
+					when "00" => 
+						-- normal mode
+						active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+						active_pf0_live <= an(2) and not(an(1)) and not(an(0));
+						active_pf1_live <= an(2) and not(an(1)) and an(0);
+						active_pf2_live <= an(2) and      an(1) and not(an(0));
+						active_pf2_collision_live <= an(2) and      an(1) and not(an(0));
+						active_pf3_collision_live <= an(2) and      an(1) and an(0);
+					when "01" =>
+						-- 1 colour/16 luminance
+						-- no playfield collisions
+						-- 5th player gets my luminance
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';						
+						active_bk_live <= '1';
+						
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(3 downto 0) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(3 downto 0) <= active_bk_modify_reg(3 downto 0);
+						end if;
+					when "10" => 
+						-- 9 colour
+						-- playfield collisions
+						-- no missile/player collisions from 'playfield' data though		
+						-- offset by 1 colour clock...
+						if (hpos_reg(0) = '1') then
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev_reg(1 downto 0)&an(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an(2);
+									active_pf2_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;
+						else
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev2_reg(1 downto 0)&an_prev_reg(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an_prev_reg(2);
+									active_pf2_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;									
+						end if;
+						
+					when "11" =>
+						-- 16 colour/1 luminance
+						-- no playfield collisions
+						-- 5th player gets our luminance
+						active_bk_live <= '1';
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';	
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(7 downto 4) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(7 downto 4) <= active_bk_modify_reg(7 downto 4);
+						end if;
+						
+						if (active_bk_modify_next(7 downto 4) = "0000") then
+							active_bk_valid_next(3 downto 0) <= "0000";
+						end if;
+				end case;
+			end if;
+			
+			if (prior_delayed_reg(4) = '1') then
+				active_pf3_live <= active_pf3_collision_live or active_m0_live or active_m1_live or active_m2_live or active_m3_live;
+			else
+				active_pf3_live <= active_pf3_collision_live;
+			end if;
+			
+			if (not (prior_delayed2_reg(7 downto 6) = "00")) then
+				-- force off flip flop when in gtia mode
+				highres_next <= '0';
+			end if;
+			
+			-- hblank
+			if (an_prev_reg(2 downto 1) = "01") then
+				hblank_next <= '1';
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				highres_next <= an_prev_reg(0);
+			
+				if (COLOUR_CLOCK_ORIGINAL='1') then				
+					if (hblank_reg = '0' and vsync_reg = '0') then
+						reset_counter <= '1';
+						counter_load_value <= X"E0"; -- 2 lower than antic
+						odd_scanline_next <= not(odd_scanline_reg);
+					end if;
+				end if;
+			end if;
+			if (an(2 downto 1) = "01") then
+				visible_live <= '0';
+			end if;			
+	
+			-- vsync
+			if (an_prev_reg = "001") then
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				
+				vsync_next <= '1';
+
+				odd_scanline_next <= '0';
+				
+				visible_live <= '0';
+			end if;
+			
+			-- during vblank we reset our own counter - since Antic does not clear hblank_reg
+			if (hpos_reg = X"E3" and COLOUR_CLOCK_ORIGINAL='1') then
+				reset_counter <= '1';
+				counter_load_value <= X"00";
+			end if;
+
+		end if;
+	end process;
+	
+	-- hpos
+	counter_hpos : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>COLOUR_CLOCK_ORIGINAL, load=>reset_counter, load_value=>counter_load_value, current_value=>hpos_reg);
+	
+	-- visible region
+--	process(hpos_reg,vpos_reg)
+--	begin		
+--		visible_live <= '1';
+--		
+----		if (unsigned(vpos_reg) < to_unsigned(8,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(vpos_reg) > to_unsigned(247,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) <= to_unsigned(34,8)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) > to_unsigned(221,8)) then
+----			visible_live <= '0';
+----		end if;		
+--	end process;
+	
+	-- generate hsync
+	process(hpos_reg, hsync_reg, hsync_end, vsync_reg, vsync_next)
+	begin
+		hsync_start <= '0';
+		hsync_next <= hsync_reg;
+
+		if (unsigned(hpos_reg) = X"D4" and vsync_reg = '1') then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+	
+		if (unsigned(hpos_reg) = X"0" and vsync_reg = '0' ) then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+			
+		if (hsync_end = '1') then
+			hsync_next <= '0';
+		end if;
+		
+		if (vsync_next = '0' and vsync_reg = '1') then
+			hsync_next <= '0';
+		end if;
+	end process;
+
+	hsync_delay : delay_line
+		generic map (COUNT=>15)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hsync_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hsync_end);	
+
+	-- pmg dma
+	MEMORY_READY <= CPU_MEMORY_READY or ANTIC_MEMORY_READY; -- TODO, REVIEW timing vs CPU/ANTIC - simpler may be possible now
+	process(antic_fetch,CPU_ENABLE_ORIGINAL,memory_ready,memory_data_in,hsync_start,pmg_dma_state_reg,gractl_reg,odd_scanline_reg,vdelay_reg,grafm_reg, visible_live,hpos_reg, hblank_reg)
+	begin
+		pmg_dma_state_next <= pmg_dma_state_reg;
+		grafm_dma_load <= '0';
+		grafm_dma_next <= grafm_reg;		
+		grafp0_dma_load <= '0';
+		grafp0_dma_next <= (others=>'0');
+		grafp1_dma_load <= '0';
+		grafp1_dma_next <= (others=>'0');
+		grafp2_dma_load <= '0';
+		grafp2_dma_next <= (others=>'0');
+		grafp3_dma_load <= '0';
+		grafp3_dma_next <= (others=>'0');
+	
+		-- pull pmg data from bus
+		if (hpos_reg = X"E1") then
+			pmg_dma_state_next <= pmg_dma_missile;
+		end if;
+		
+		-- we start from the first antic refresh cycle
+		-- TODO - CPU enable does not identify next 'antic' cycle in turbo mode...
+		case pmg_dma_state_reg is
+			when pmg_dma_missile =>
+				if (antic_fetch = '1' and memory_ready = '1' and hblank_reg = '1' and visible_live = '0' and hpos_reg(7 downto 4) = "0000") then
+					-- here we have the missile0					
+					grafm_dma_load <= gractl_reg(0);
+				
+					if ((odd_scanline_reg or not(vdelay_reg(0))) = '1') then
+						grafm_dma_next(1 downto 0) <= memory_data_in(1 downto 0);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(1))) = '1') then
+						grafm_dma_next(3 downto 2) <= memory_data_in(3 downto 2);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(2))) = '1') then
+						grafm_dma_next(5 downto 4) <= memory_data_in(5 downto 4);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(3))) = '1') then
+						grafm_dma_next(7 downto 6) <= memory_data_in(7 downto 6);
+					end if;
+					
+					pmg_dma_state_next <= pmg_dma_instruction;
+				end if;
+			when pmg_dma_instruction =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					pmg_dma_state_next <= pmg_dma_player0;
+				end if;			
+			when pmg_dma_player0 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player0
+					grafp0_dma_next <= memory_data_in;				
+					grafp0_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(4)));
+					pmg_dma_state_next <= pmg_dma_player1;
+				end if;
+			when pmg_dma_player1 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp1_dma_next <= memory_data_in;
+					grafp1_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(5)));
+					pmg_dma_state_next <= pmg_dma_player2;
+				end if;
+			when pmg_dma_player2 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp2_dma_next <= memory_data_in;
+					grafp2_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(6)));
+					pmg_dma_state_next <= pmg_dma_player3;
+				end if;				
+			when pmg_dma_player3 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp3_dma_next <= memory_data_in;				
+					grafp3_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(7)));
+					pmg_dma_state_next <= pmg_dma_done;
+				end if;
+			when others =>
+				-- nop
+		end case;
+	end process;
+		
+	-- pmg display - same for all pmgs
+	-- TODO: priority
+	player0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp0_delayed_reg,size=>sizep0_delayed_reg(1 downto 0),bitmap=>grafp0_reg, output=>active_p0_live);	
+	player1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp1_delayed_reg,size=>sizep1_delayed_reg(1 downto 0),bitmap=>grafp1_reg, output=>active_p1_live);	
+	player2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp2_delayed_reg,size=>sizep2_delayed_reg(1 downto 0),bitmap=>grafp2_reg, output=>active_p2_live);	
+	player3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);				
+
+	missile0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg(1 downto 0)&"000000", output=>active_m0_live);
+	missile1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg(3 downto 2)&"000000", output=>active_m1_live);
+	missile2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg(5 downto 4)&"000000", output=>active_m2_live);
+	missile3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg(7 downto 6)&"000000", output=>active_m3_live);
+		
+	-- calculate atari colour
+	priority_rules : gtia_priority
+		port map(clk=>clk, colour_enable=>colour_clock, prior=>prior_delayed_reg,p0=>active_pm0_live,p1=>active_pm1_live,p2=>active_pm2_live,p3=>active_pm3_live,pf0=>active_pf0_live,pf1=>active_pf1_live,pf2=>active_pf2_live,pf3=>active_pf3_live,bk=>active_bk_live,p0_out=>set_p0,p1_out=>set_p1,p2_out=>set_p2,p3_out=>set_p3,pf0_out=>set_pf0,pf1_out=>set_pf1,pf2_out=>set_pf2,pf3_out=>set_pf3,bk_out=>set_bk);	
+
+	trigger_secondhalf <= colour_clock_HIGHRES and not colour_clock;
+	process(set_p0,set_p1,set_p2,set_p3,set_pf0,set_pf1,set_pf2,set_pf3,set_bk,highres_reg, active_hr_reg, colbk_delayed_reg, colpf0_delayed_reg, colpf1_delayed_reg, colpf2_delayed_reg, colpf3_delayed_reg, colpm0_delayed_reg, colpm1_delayed_reg, colpm2_delayed_reg, colpm3_delayed_reg, trigger_secondhalf, colour_clock, COLOUR_REG, hrcolour_reg, visible_live, active_bk_modify_next, active_bk_valid_next)
+	begin
+		colour_next <= colour_reg;
+		hrcolour_next <= hrcolour_reg;
+		
+		if (trigger_secondhalf = '1') then
+			if (highres_reg = '1') then
+				colour_next <= hrcolour_reg;
+			end if;
+		end if;		
+		
+		if (colour_clock = '1') then 
+			colour_next <= 
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+			hrcolour_next <= -- SAME FIXME
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+						
+			-- finally high-res mode overrides the luma
+			if (set_bk = '0' and highres_reg = '1') then
+			
+				if (active_hr_reg(1) = '1') then
+					colour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';						
+				end if;
+				
+				if (active_hr_reg(0) = '1') then						
+					hrcolour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
+				end if;
+			end if;				
+			
+			if (visible_live = '0') then
+				colour_next <= X"00";
+				hrcolour_next <= X"00";
+			end if;			
+		end if;
+	end process;
+
+	-- collision detection
+	process (colour_clock, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg,hitclr_write,active_pf0_live,active_pf1_live,active_pf2_collision_live,active_pf3_collision_live,active_p0_live,active_p1_live,active_p2_live,active_p3_live,active_m0_live,active_m1_live,active_m2_live,active_m3_live, visible_live)
+	begin
+		m0pf_next <= m0pf_reg;
+		m1pf_next <= m1pf_reg;
+		m2pf_next <= m2pf_reg;
+		m3pf_next <= m3pf_reg;
+		m0pl_next <= m0pl_reg;
+		m1pl_next <= m1pl_reg;
+		m2pl_next <= m2pl_reg;
+		m3pl_next <= m3pl_reg;
+		
+		p0pf_next <= p0pf_reg;
+		p1pf_next <= p1pf_reg;
+		p2pf_next <= p2pf_reg;
+		p3pf_next <= p3pf_reg;
+		p0pl_next <= p0pl_reg;
+		p1pl_next <= p1pl_reg;
+		p2pl_next <= p2pl_reg;
+		p3pl_next <= p3pl_reg;	
+		
+		if (hitclr_write = '1') then
+			m0pf_next <= (others=>'0');
+			m1pf_next <= (others=>'0');
+			m2pf_next <= (others=>'0');
+			m3pf_next <= (others=>'0');
+			m0pl_next <= (others=>'0');
+			m1pl_next <= (others=>'0');
+			m2pl_next <= (others=>'0');
+			m3pl_next <= (others=>'0');
+			
+			p0pf_next <= (others=>'0');
+			p1pf_next <= (others=>'0');
+			p2pf_next <= (others=>'0');
+			p3pf_next <= (others=>'0');
+			p0pl_next <= (others=>'0');
+			p1pl_next <= (others=>'0');
+			p2pl_next <= (others=>'0');
+			p3pl_next <= (others=>'0');
+		else
+			if (visible_live = '1' and colour_clock = '1') then
+				m0pl_next <= m0pl_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m1pl_next <= m1pl_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m2pl_next <= m2pl_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m3pl_next <= m3pl_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+
+				m0pf_next <= m0pf_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m1pf_next <= m1pf_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m2pf_next <= m2pf_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m3pf_next <= m3pf_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				
+				p0pl_next <= p0pl_reg or (active_p0_live&active_p0_live&active_p0_live&'0'        and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p1pl_next <= p1pl_reg or (active_p1_live&active_p1_live&'0'       &active_p1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p2pl_next <= p2pl_reg or (active_p2_live&'0'       &active_p2_live&active_p2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p3pl_next <= p3pl_reg or ('0'       &active_p3_live&active_p3_live&active_p3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);	
+				
+				p0pf_next <= p0pf_reg or (active_p0_live&active_p0_live&active_p0_live&active_p0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p1pf_next <= p1pf_reg or (active_p1_live&active_p1_live&active_p1_live&active_p1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p2pf_next <= p2pf_reg or (active_p2_live&active_p2_live&active_p2_live&active_p2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p3pf_next <= p3pf_reg or (active_p3_live&active_p3_live&active_p3_live&active_p3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);			
+			end if;
+		end if;
+		
+	end process;
+
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,hposp0_raw_reg,hposp1_raw_reg,hposp2_raw_reg,hposp3_raw_reg,hposm0_raw_reg,hposm1_raw_reg,hposm2_raw_reg,hposm3_raw_reg,sizep0_raw_reg,sizep1_raw_reg,sizep2_raw_reg,sizep3_raw_reg,sizem_raw_reg,grafp0_reg,grafp1_reg,grafp2_reg,grafp3_reg, grafm_reg, colpm0_raw_reg, colpm1_raw_reg, colpm2_raw_reg, colpm3_raw_reg, colpf0_raw_reg, colpf1_raw_reg,colpf2_raw_reg, colpf3_raw_reg, colbk_raw_reg, prior_raw_reg, vdelay_reg, gractl_reg, consol_output_reg, grafm_dma_load, grafm_dma_next, grafp0_dma_load, grafp0_dma_next, grafp1_dma_load, grafp1_dma_next, grafp2_dma_load, grafp2_dma_next, grafp3_dma_load, grafp3_dma_next)
+	begin
+		hposp0_raw_next <= hposp0_raw_reg;
+		hposp1_raw_next <= hposp1_raw_reg;
+		hposp2_raw_next <= hposp2_raw_reg;
+		hposp3_raw_next <= hposp3_raw_reg;
+
+		hposm0_raw_next <= hposm0_raw_reg;
+		hposm1_raw_next <= hposm1_raw_reg;
+		hposm2_raw_next <= hposm2_raw_reg;
+		hposm3_raw_next <= hposm3_raw_reg;			
+
+		sizep0_raw_next <= sizep0_raw_reg;
+		sizep1_raw_next <= sizep1_raw_reg;
+		sizep2_raw_next <= sizep2_raw_reg;
+		sizep3_raw_next <= sizep3_raw_reg;
+
+		sizem_raw_next <= sizem_raw_reg;
+		
+		grafp0_next <= grafp0_reg;
+		grafp1_next <= grafp1_reg;
+		grafp2_next <= grafp2_reg;
+		grafp3_next <= grafp3_reg;
+
+		grafm_next <= grafm_reg;
+		
+		colpm0_raw_next <= colpm0_raw_reg;
+		colpm1_raw_next <= colpm1_raw_reg;
+		colpm2_raw_next <= colpm2_raw_reg;
+		colpm3_raw_next <= colpm3_raw_reg;
+
+		colpf0_raw_next <= colpf0_raw_reg;
+		colpf1_raw_next <= colpf1_raw_reg;
+		colpf2_raw_next <= colpf2_raw_reg;
+		colpf3_raw_next <= colpf3_raw_reg;
+		
+		colbk_raw_next <= colbk_raw_reg;
+		
+		prior_raw_next <= prior_raw_reg;
+		
+		vdelay_next <= vdelay_reg;
+		
+		gractl_next <= gractl_reg;
+		
+		consol_output_next <= consol_output_reg;	
+		
+		hitclr_write <= '0';
+		
+		if (grafm_dma_load = '1') then
+			grafm_next <= grafm_dma_next;
+		end if;
+
+		if (grafp0_dma_load = '1') then
+			grafp0_next <= grafp0_dma_next;
+		end if;
+
+		if (grafp1_dma_load = '1') then
+			grafp1_next <= grafp1_dma_next;
+		end if;
+
+		if (grafp2_dma_load = '1') then
+			grafp2_next <= grafp2_dma_next;
+		end if;
+
+		if (grafp3_dma_load = '1') then
+			grafp3_next <= grafp3_dma_next;
+		end if;
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				hposp0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				hposp1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(2) = '1') then
+				hposp2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				hposp3_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(4) = '1') then
+				hposm0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				hposm1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(6) = '1') then
+				hposm2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(7) = '1') then
+				hposm3_raw_next <= cpu_data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				sizep0_raw_next <= cpu_data_in(1 downto 0);
+			end if;	
+
+			if(addr_decoded(9) = '1') then
+				sizep1_raw_next <= cpu_data_in(1 downto 0);
+			end if;		
+			
+			if(addr_decoded(10) = '1') then
+				sizep2_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+
+			if(addr_decoded(11) = '1') then
+				sizep3_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+			
+			if(addr_decoded(12) = '1') then
+				sizem_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(13) = '1') then
+				grafp0_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(14) = '1') then
+				grafp1_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(15) = '1') then
+				grafp2_next <= cpu_data_in;
+			end if;			
+			
+			if(addr_decoded(16) = '1') then
+				grafp3_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(17) = '1') then
+				grafm_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(18) = '1') then
+				colpm0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(19) = '1') then
+				colpm1_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(20) = '1') then
+				colpm2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(21) = '1') then
+				colpm3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(22) = '1') then
+				colpf0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(23) = '1') then
+				colpf1_raw_next <= cpu_data_in(7 downto 1);
+			end if;									
+
+			if(addr_decoded(24) = '1') then
+				colpf2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(25) = '1') then
+				colpf3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(26) = '1') then
+				colbk_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(27) = '1') then
+				prior_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(28) = '1') then
+				vdelay_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(29) = '1') then
+				gractl_next <= cpu_data_in(2 downto 0);
+			end if;		
+			
+			if(addr_decoded(30) = '1') then
+				-- clear the collision regs
+				hitclr_write <= '1';
+			end if;
+
+			if(addr_decoded(31) = '1') then
+				consol_output_next <= cpu_data_in(3 downto 0);
+			end if;				
+			
+		end if;
+	end process;
+	
+	-- delays...
+		-- TODO - needs more attention ... 
+		-- The prior behaviour here in real hardware is all over the place...
+		-- THESE CAN TAKE MUCH LESS SPACE - only need to store per CPU cycle, not per colour clock original
+	prior_short_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>6)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(5 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(5 downto 0));
+
+	prior_long_delay : wide_delay_line
+		generic map (COUNT=>3, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(7 downto 6));
+
+	prior_longer_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed2_reg(7 downto 6));		
+		
+	colbk_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colbk_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colbk_delayed_reg(7 downto 1));	
+
+	colpm0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm0_delayed_reg(7 downto 1));		
+	colpm1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm1_delayed_reg(7 downto 1));		
+	colpm2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm2_delayed_reg(7 downto 1));		
+	colpm3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm3_delayed_reg(7 downto 1));		
+
+	colpf0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf0_delayed_reg(7 downto 1));		
+	colpf1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf1_delayed_reg(7 downto 1));		
+	colpf2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf2_delayed_reg(7 downto 1));		
+	colpf3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf3_delayed_reg(7 downto 1));				
+
+	hposp0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp0_delayed_reg(7 downto 0));		
+	hposp1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp1_delayed_reg(7 downto 0));		
+	hposp2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp2_delayed_reg(7 downto 0));		
+	hposp3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp3_delayed_reg(7 downto 0));				
+
+	hposm0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm0_delayed_reg(7 downto 0));		
+	hposm1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm1_delayed_reg(7 downto 0));		
+	hposm2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm2_delayed_reg(7 downto 0));		
+	hposm3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm3_delayed_reg(7 downto 0));				
+		
+	sizep0_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep0_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep0_delayed_reg(1 downto 0));		
+	sizep1_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep1_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep1_delayed_reg(1 downto 0));		
+	sizep2_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep2_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep2_delayed_reg(1 downto 0));		
+	sizep3_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep3_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep3_delayed_reg(1 downto 0));		
+	sizem_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizem_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizem_delayed_reg(7 downto 0));				
+		
+	-- joystick
+	process(trig0_reg, trig1_reg, trig2_reg, trig3_reg, trig0, trig1, trig2, trig3, gractl_reg)
+	begin	
+		trig0_next <= trig0;
+		trig1_next <= trig1;
+		trig2_next <= trig2;
+		trig3_next <= trig3;
+		
+		if (gractl_reg(2) = '1') then
+			trig0_next <= trig0_reg and trig0;
+			trig1_next <= trig1_reg and trig1;
+			trig2_next <= trig2_reg and trig2;
+			trig3_next <= trig3_reg and trig3;
+		end if;
+	end process;
+	
+	-- Read from registers		
+	process(addr_decoded, CONSOL_OPTION, CONSOL_SELECT, CONSOL_START, consol_output_reg, trig0_reg, trig1_reg, trig2_reg, trig3_reg, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg, pal)
+	begin
+		data_out <= X"0F";
+
+		if (addr_decoded(0) = '1') then
+			data_out <= "0000"&m0pf_reg;
+		end if;
+
+		if (addr_decoded(1) = '1') then
+			data_out <= "0000"&m1pf_reg;
+		end if;
+		
+		if (addr_decoded(2) = '1') then
+			data_out <= "0000"&m2pf_reg;
+		end if;
+
+		if (addr_decoded(3) = '1') then
+			data_out <= "0000"&m3pf_reg;
+		end if;
+
+		if (addr_decoded(4) = '1') then
+			data_out <= "0000"&p0pf_reg;
+		end if;
+
+		if (addr_decoded(5) = '1') then
+			data_out <= "0000"&p1pf_reg;
+		end if;
+		
+		if (addr_decoded(6) = '1') then
+			data_out <= "0000"&p2pf_reg;
+		end if;
+
+		if (addr_decoded(7) = '1') then
+			data_out <= "0000"&p3pf_reg;
+		end if;
+		
+		if (addr_decoded(8) = '1') then
+			data_out <= "0000"&m0pl_reg;
+		end if;
+
+		if (addr_decoded(9) = '1') then
+			data_out <= "0000"&m1pl_reg;
+		end if;
+		
+		if (addr_decoded(10) = '1') then
+			data_out <= "0000"&m2pl_reg;
+		end if;
+
+		if (addr_decoded(11) = '1') then
+			data_out <= "0000"&m3pl_reg;
+		end if;		
+
+		if (addr_decoded(12) = '1') then
+			data_out <= "0000"&p0pl_reg;
+		end if;
+
+		if (addr_decoded(13) = '1') then
+			data_out <= "0000"&p1pl_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then
+			data_out <= "0000"&p2pl_reg;
+		end if;
+
+		if (addr_decoded(15) = '1') then
+			data_out <= "0000"&p3pl_reg;
+		end if;		
+		
+		if (addr_decoded(16) = '1') then
+			data_out <= "0000000"&trig0_reg;
+		end if;
+
+		if (addr_decoded(17) = '1') then
+			data_out <= "0000000"&trig1_reg;
+		end if;
+
+		if (addr_decoded(18) = '1') then
+			data_out <= "0000000"&trig2_reg;
+		end if;
+		
+		if (addr_decoded(19) = '1') then
+			data_out <= "0000000"&trig3_reg;
+		end if;
+		
+		if (addr_decoded(20) = '1') then
+			data_out <= "00000"&not(pal&pal&pal);
+		end if;
+
+		if (addr_decoded(31) = '1') then
+			data_out <= "0000"&('0'&not(CONSOL_OPTION)&not(CONSOL_SELECT)&not(CONSOL_START) and (not consol_output_reg));
+		end if;
+		
+	end process;
+	
+	-- output	
+	colour_out <= colour_reg;
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+	
+	sound <= consol_output_reg(3);
+
+end vhdl;
+
+
Index: unmerged/core/mcc216/hexdecoder.vhd
===================================================================
--- unmerged/core/mcc216/hexdecoder.vhd	(nonexistent)
+++ unmerged/core/mcc216/hexdecoder.vhd	(revision 1)
@@ -0,0 +1,75 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY hexdecoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+);
+END hexdecoder;
+
+ARCHITECTURE vhdl OF hexdecoder IS
+	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
+	signal digit_next : std_logic_vector(6 downto 0);
+	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
+BEGIN
+	--numinv <= not(NUMBER);
+	numinv <= NUMBER;
+	process(numinv)
+	begin
+		case numinv is
+			when "0000" =>
+				digit_next <= "1111111";
+			when "0001" =>
+				digit_next <= "1111001";
+			when "0010" =>
+				digit_next <= "0100100";
+			when "0011" =>
+				digit_next <= "0110000";
+			when "0100" =>
+				digit_next <= "0011001";
+			when "0101" =>
+				digit_next <= "0010010";
+			when "0110" =>
+				digit_next <= "0000010";
+			when "0111" =>
+				digit_next <= "1111000";
+			when "1000" =>
+				digit_next <= "0000000";
+			when "1001" =>
+				digit_next <= "0011000";
+			when "1010" =>
+				digit_next <= "0001000";
+			when "1011" =>
+				digit_next <= "0000011";
+			when "1100" =>
+				digit_next <= "1000110";
+			when "1101" =>
+				digit_next <= "0100001";
+			when "1110" =>
+				digit_next <= "0000110";
+			when "1111" =>
+				digit_next <= "0001110";
+			when others =>
+				digit_next <= "1111111";
+		end case;
+	end process;
+	
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	digit<=digit_reg;
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/i2sslave.vhdl
===================================================================
--- unmerged/core/mcc216/i2sslave.vhdl	(nonexistent)
+++ unmerged/core/mcc216/i2sslave.vhdl	(revision 1)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY i2sslave IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	BCLK : IN STD_LOGIC;
+	DACLRC : IN STD_LOGIC;
+	
+	LEFT_IN : in std_logic_vector(15 downto 0);
+	RIGHT_IN : in std_logic_vector(15 downto 0);
+	
+	MCLK_2 : OUT STD_LOGIC;
+	DACDAT : OUT STD_LOGIC
+);
+END i2sslave;
+
+ARCHITECTURE vhdl OF i2sslave IS
+	signal bclk_reg : std_logic;
+	signal bclk_last_reg : std_logic;
+	signal daclrc_reg : std_logic;
+	signal daclrc_last_reg : std_logic;
+	
+	signal shiftreg_reg : std_logic_vector(15 downto 0);
+	signal shiftreg_next : std_logic_vector(15 downto 0);
+	
+	signal CLK_FAKE : std_logic;
+BEGIN
+	MCLK_2 <= CLK_FAKE; -- bad practice, but pll out of...
+	
+	-- Data read on bclk low->high transition
+	-- daclrc is set on bclk high->low transition
+	
+	-- register inputs
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			CLK_FAKE <= not(CLK_FAKE);
+		end if;
+	end process;
+	
+	process(CLK_FAKE)
+	begin	
+		if (CLK_FAKE'event and CLK_FAKE='1') then
+			bclk_reg <= bclk;
+			bclk_last_reg <= bclk_reg;
+			daclrc_reg <= daclrc;
+			daclrc_last_reg <= daclrc_reg;
+			shiftreg_reg <= shiftreg_next;
+		end if;
+	end process;
+	
+	-- sample on change to daclrc, shift out bit if required
+	process(daclrc_reg,daclrc_last_reg,bclk_reg,shiftreg_reg,left_in,right_in,bclk_last_reg)
+		variable reload : std_logic;
+	begin
+		reload := '0';
+		shiftreg_next <= shiftreg_reg;
+		
+		if (daclrc_reg = '1' and daclrc_last_reg = '0') then
+			shiftreg_next <= right_in;
+			reload := '1';
+		end if;
+		
+		if (daclrc_reg = '0' and daclrc_last_reg = '1') then
+			shiftreg_next <= left_in;
+			reload := '1';
+		end if;
+		
+		if (bclk_reg = '0' and bclk_last_reg = '1' and reload='0') then
+				shiftreg_next <= shiftreg_reg(14 downto 0)&'0';
+		end if;
+			
+	end process;
+	
+	DACDAT <= shiftreg_reg(15);
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/ledsw.vhd
===================================================================
--- unmerged/core/mcc216/ledsw.vhd	(nonexistent)
+++ unmerged/core/mcc216/ledsw.vhd	(revision 1)
@@ -0,0 +1,70 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+-- Simple module that connects the SW switches to the LEDR lights
+ENTITY ledsw IS
+PORT ( 
+	CLK : IN STD_LOGIC;
+
+	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	SYNC_KEYS : out std_logic_vector(3 downto 0);
+	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
+); 
+END ledsw;
+
+ARCHITECTURE Behavior OF ledsw IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+		
+	signal sw_reg : std_logic_vector(9 downto 0);
+	signal key_reg : std_logic_vector(3 downto 0);
+	
+BEGIN
+	sw9_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
+	sw8_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
+	sw7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
+	sw6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
+	sw5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
+	sw4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
+	sw3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
+	sw2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
+	sw1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
+	sw0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
+
+	key3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
+	key2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
+	key1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
+	key0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
+	
+	-- outputs
+	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
+	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
+END Behavior;
Index: unmerged/core/mcc216/pll.ppf
===================================================================
--- unmerged/core/mcc216/pll.ppf	(nonexistent)
+++ unmerged/core/mcc216/pll.ppf	(revision 1)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: unmerged/core/mcc216/pokey.vhdl
===================================================================
--- unmerged/core/mcc216/pokey.vhdl	(nonexistent)
+++ unmerged/core/mcc216/pokey.vhdl	(revision 1)
@@ -0,0 +1,1229 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Problem - UART on the DE1 does not have all pins connected. Need to use...
+
+ENTITY pokey IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	--ENABLE_179 :in std_logic;
+	CPU_MEMORY_READY :in std_logic;
+	ANTIC_MEMORY_READY :in std_logic;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	-- keyboard interface
+--	KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
+--	KEY_HELD : IN STD_LOGIC;
+--	SHIFT_PRESSED : IN STD_LOGIC;
+--	BREAK_PRESSED : IN STD_LOGIC;
+--	KEY_INTERRUPT : IN STD_LOGIC;
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	keyboard_response : in std_logic_vector(1 downto 0);
+	
+	-- pots - go high as capacitor charges
+	POT_IN : in std_logic_vector(7 downto 0);
+	
+	-- sio interface
+	SIO_IN1 : IN std_logic;
+	SIO_IN2 : IN std_logic;
+	SIO_IN3 : IN std_logic;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	
+	IRQ_N_OUT : OUT std_logic;
+	
+	SIO_OUT1 : OUT std_logic;
+	SIO_OUT2 : OUT std_logic;
+	SIO_OUT3 : OUT std_logic;
+	
+	SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+	
+	POT_RESET : out std_logic
+);
+END pokey;
+
+ARCHITECTURE vhdl OF pokey IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+
+	component syncreset_enable_divider IS
+	generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		syncreset : in std_logic;
+		reset_n : in std_logic;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_17_9 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC;
+		
+		RAND_OUT : OUT std_logic_vector(7 downto 0)
+	);
+	END component;
+	
+	component poly_5 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_4 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_countdown_timer IS
+	generic(UNDERFLOW_DELAY : natural := 3);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		ENABLE_UNDERFLOW : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		WR_EN : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_noise_filter IS
+	PORT 
+	( 
+		NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+			
+		PULSE_IN : IN STD_LOGIC;
+
+		NOISE_4 : IN STD_LOGIC;
+		NOISE_5 : IN STD_LOGIC;
+		NOISE_LARGE : IN STD_LOGIC;
+		
+		PULSE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_keyboard_scanner is
+	port
+	(
+		clk : in std_logic;
+		reset_n : in std_logic;
+		
+		enable : in std_logic; -- typically hsync or equiv timing
+		keyboard_response : in std_logic_vector(1 downto 0);
+		debounce_disable : in std_logic;
+		scan_enable : in std_logic;
+		
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		
+		shift_pressed : out std_logic;
+		control_pressed : out std_logic;
+		break_pressed : out std_logic;
+		key_held : out std_logic;
+		keycode : out std_logic_vector(5 downto 0);
+		other_key_irq : out std_logic
+	);
+	end component;
+	
+	--signal enable_179 : std_logic;
+	signal enable_64 : std_logic;
+	signal enable_15 : std_logic;
+
+	signal audf0_reg : std_logic_vector(7 downto 0);
+	signal audc0_reg : std_logic_vector(7 downto 0);
+	signal audf1_reg : std_logic_vector(7 downto 0);
+	signal audc1_reg : std_logic_vector(7 downto 0);
+	signal audf2_reg : std_logic_vector(7 downto 0);
+	signal audc2_reg : std_logic_vector(7 downto 0);
+	signal audf3_reg : std_logic_vector(7 downto 0);
+	signal audc3_reg : std_logic_vector(7 downto 0);
+	signal audctl_reg : std_logic_vector(7 downto 0);	
+	signal audf0_next : std_logic_vector(7 downto 0);
+	signal audc0_next : std_logic_vector(7 downto 0);
+	signal audf1_next : std_logic_vector(7 downto 0);
+	signal audc1_next : std_logic_vector(7 downto 0);
+	signal audf2_next : std_logic_vector(7 downto 0);
+	signal audc2_next : std_logic_vector(7 downto 0);
+	signal audf3_next : std_logic_vector(7 downto 0);
+	signal audc3_next : std_logic_vector(7 downto 0);
+	signal audctl_next : std_logic_vector(7 downto 0);
+
+	signal audf0_pulse : std_logic;
+	signal audf1_pulse : std_logic;
+	signal audf2_pulse : std_logic;
+	signal audf3_pulse : std_logic;
+	
+	signal audf0_reload : std_logic;
+	signal audf1_reload : std_logic;
+	signal audf2_reload : std_logic;
+	signal audf3_reload : std_logic;
+	
+	signal stimer_write : std_logic;
+	signal stimer_write_delayed : std_logic;
+	
+	signal audf0_pulse_noise : std_logic;
+	signal audf1_pulse_noise : std_logic;
+	signal audf2_pulse_noise : std_logic;
+	signal audf3_pulse_noise : std_logic;
+	
+	signal audf0_enable : std_logic;
+	signal audf1_enable : std_logic;
+	signal audf2_enable : std_logic;
+	signal audf3_enable : std_logic;
+	
+	signal chan0_output_next : std_logic;
+	signal chan1_output_next : std_logic;
+	signal chan2_output_next : std_logic;
+	signal chan3_output_next : std_logic;
+	signal chan0_output_reg : std_logic;
+	signal chan1_output_reg : std_logic;
+	signal chan2_output_reg : std_logic;
+	signal chan3_output_reg : std_logic;
+	
+	signal highpass0_next : std_logic;
+	signal highpass1_next : std_logic;	
+	signal highpass0_reg : std_logic;
+	signal highpass1_reg : std_logic;
+	
+	signal volume_channel_0_next : std_logic_vector(3 downto 0);
+	signal volume_channel_1_next : std_logic_vector(3 downto 0);
+	signal volume_channel_2_next : std_logic_vector(3 downto 0);
+	signal volume_channel_3_next : std_logic_vector(3 downto 0);
+	signal volume_channel_0_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_1_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_2_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_3_reg : std_logic_vector(3 downto 0);
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal noise_4 : std_logic;
+	signal noise_5 : std_logic;
+	signal noise_large : std_logic;
+	signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
+	
+	signal initmode : std_logic;
+	
+	signal irqen_next : std_logic_vector(7 downto 0);
+	signal irqen_reg : std_logic_vector(7 downto 0);
+
+	signal irqst_next : std_logic_vector(7 downto 0);
+	signal irqst_reg : std_logic_vector(7 downto 0);
+	
+	signal irq_n_next : std_logic;
+	signal irq_n_reg : std_logic; -- for output
+	
+	-- serial ports!
+	signal serial_ip_ready_interrupt : std_logic;
+	signal serial_ip_framing_next : std_logic;
+	signal serial_ip_framing_reg : std_logic;
+	signal serial_ip_overrun_next : std_logic;
+	signal serial_ip_overrun_reg : std_logic;
+	signal serial_op_needed_interrupt : std_logic;
+	
+	signal skctl_next : std_logic_vector(7 downto 0);
+	signal skctl_reg : std_logic_vector(7 downto 0);
+	
+	signal serin_shift_next : std_logic_vector(9 downto 0);
+	signal serin_shift_reg : std_logic_vector(9 downto 0);
+	signal serin_next : std_logic_vector(7 downto 0);
+	signal serin_reg : std_logic_vector(7 downto 0);
+	signal serin_bitcount_next : std_logic_vector(3 downto 0);
+	signal serin_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal sio_in1_reg : std_logic;
+	signal sio_in2_reg : std_logic;
+	signal sio_in3_reg : std_logic;
+	signal sio_in_next : std_logic;
+	signal sio_in_reg : std_logic;
+	
+	signal sio_out_next : std_logic;
+	signal sio_out_reg : std_logic;
+	signal serial_out_next : std_logic;
+	signal serial_out_reg : std_logic;
+	
+	signal serout_shift_next : std_logic_vector(9 downto 0);
+	signal serout_shift_reg : std_logic_vector(9 downto 0);
+	
+	signal serout_holding_full_next : std_logic;
+	signal serout_holding_full_reg : std_logic;
+	signal serout_holding_next : std_logic_vector(7 downto 0);
+	signal serout_holding_reg : std_logic_vector(7 downto 0);
+	signal serout_holding_load : std_logic;
+
+	signal serout_bitcount_next : std_logic_vector(3 downto 0);
+	signal serout_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal serout_active_next : std_logic;
+	signal serout_active_reg : std_logic;
+	
+	signal serial_reset : std_logic;
+	signal skrest_write : std_logic;
+	
+	signal serout_enable : std_logic;
+	signal serout_enable_delayed : std_logic;
+	signal serin_enable : std_logic;
+	
+	signal async_serial_reset : std_logic;
+	signal waiting_for_start_bit : std_logic;
+	
+	signal serin_clock_next : std_logic;
+	signal serin_clock_reg : std_logic;
+	signal serin_clock_last_next : std_logic;
+	signal serin_clock_last_reg : std_logic;
+
+	signal serout_clock_next : std_logic;
+	signal serout_clock_reg : std_logic;
+	signal serout_clock_last_next : std_logic;
+	signal serout_clock_last_reg : std_logic;
+	
+	signal twotone_reset : std_logic;
+	signal twotone_next : std_logic;
+	signal twotone_reg : std_logic;
+	
+	signal clock_next : std_logic;
+	signal clock_reg : std_logic;
+	signal clock_sync_next : std_logic;
+	signal clock_sync_reg : std_logic;
+	signal clock_input : std_logic;
+	
+	-- keyboard
+	signal keyboard_overrun_next : std_logic;
+	signal keyboard_overrun_reg : std_logic;
+	
+	signal shift_pressed : std_logic;
+	signal control_pressed : std_logic;
+	signal break_pressed : std_logic;
+	signal key_held : std_logic;
+	signal other_key_irq : std_logic;
+	
+	signal kbcode : std_logic_vector(5 downto 0);
+	
+	-- pots
+	signal pot0_next : std_logic_vector(7 downto 0);
+	signal pot0_reg : std_logic_vector(7 downto 0);
+	signal pot1_next : std_logic_vector(7 downto 0);
+	signal pot1_reg : std_logic_vector(7 downto 0);
+	signal pot2_next : std_logic_vector(7 downto 0);
+	signal pot2_reg : std_logic_vector(7 downto 0);
+	signal pot3_next : std_logic_vector(7 downto 0);
+	signal pot3_reg : std_logic_vector(7 downto 0);
+	signal pot4_next : std_logic_vector(7 downto 0);
+	signal pot4_reg : std_logic_vector(7 downto 0);
+	signal pot5_next : std_logic_vector(7 downto 0);
+	signal pot5_reg : std_logic_vector(7 downto 0);	
+	signal pot6_next : std_logic_vector(7 downto 0);
+	signal pot6_reg : std_logic_vector(7 downto 0);
+	signal pot7_next : std_logic_vector(7 downto 0);
+	signal pot7_reg : std_logic_vector(7 downto 0);	
+	
+	signal pot_counter_next : std_logic_vector(7 downto 0);
+	signal pot_counter_reg : std_logic_vector(7 downto 0);
+	
+	signal potgo_write : std_logic;
+	
+	signal pot_reset_next : std_logic;
+	signal pot_reset_reg : std_logic;
+	
+	signal enable_179 : std_logic;
+BEGIN
+	--HACK FIXME TODO
+	enable_179 <= cpu_MEMORY_READY or antIC_MEMORY_READY;
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
+			audf0_reg <= X"00";
+			audc0_reg <= X"00";
+			audf1_reg <= X"00";
+			audc1_reg <= X"00";
+			audf2_reg <= X"00";
+			audc2_reg <= X"00";
+			audf3_reg <= X"00";
+			audc3_reg <= X"00";
+			audctl_reg <= X"00";
+			
+			irqen_reg <= X"00";
+			irqst_reg <= X"FF";
+			irq_n_reg <= '1';
+			
+			skctl_reg <= X"00";
+			
+			highpass0_reg <= '0';
+			highpass1_reg <= '0';
+			
+			chan0_output_reg <= '0';
+			chan1_output_reg <= '0';
+			chan2_output_reg <= '0';
+			chan3_output_reg <= '0';
+			
+			volume_channel_0_reg <= (others=>'0');
+			volume_channel_1_reg <= (others=>'0');
+			volume_channel_2_reg <= (others=>'0');
+			volume_channel_3_reg <= (others=>'0');
+			
+			serin_reg <= (others=>'0');
+			serin_shift_reg <= (others=>'0');
+			serin_bitcount_reg <= (others=>'0');
+			serout_shift_reg <= (others=>'0');
+			serout_holding_reg <= (others=>'0');
+			serout_holding_full_reg <= '0';
+			serout_active_reg <= '0';		
+			sio_out_reg <= '1';
+			serial_out_reg <= '1';
+			
+			serial_ip_framing_reg <= '0';
+			serial_ip_overrun_reg <= '0';
+			
+			clock_reg <= '0';
+			clock_sync_reg <= '0';
+	
+			keyboard_overrun_reg <= '0';
+			
+			serin_clock_reg <= '0';
+			serin_clock_last_reg <= '0';
+			serout_clock_reg <= '0';
+			serout_clock_last_reg <= '0';
+			
+			twotone_reg <= '0';
+			
+			sio_in_reg <= '0';
+			
+			pot0_reg <= (others=>'0');
+			pot1_reg <= (others=>'0');
+			pot2_reg <= (others=>'0');
+			pot3_reg <= (others=>'0');
+			pot4_reg <= (others=>'0');
+			pot5_reg <= (others=>'0');
+			pot6_reg <= (others=>'0');
+			pot7_reg <= (others=>'0');
+			
+			pot_counter_reg <= (others=>'0');
+			
+			pot_reset_reg <= '1';
+			
+		elsif (clk'event and clk='1') then			
+			audf0_reg <= audf0_next;
+			audc0_reg <= audc0_next;
+			audf1_reg <= audf1_next;
+			audc1_reg <= audc1_next;
+			audf2_reg <= audf2_next;
+			audc2_reg <= audc2_next;
+			audf3_reg <= audf3_next;
+			audc3_reg <= audc3_next;
+			audctl_reg <= audctl_next;
+			
+			irqen_reg <= irqen_next;
+			irqst_reg <= irqst_next;
+			irq_n_reg <= irq_n_next;
+			
+			skctl_reg <= skctl_next;
+			
+			highpass0_reg <= highpass0_next;
+			highpass1_reg <= highpass1_next;
+			
+			chan0_output_reg <= chan0_output_next;
+			chan1_output_reg <= chan1_output_next;
+			chan2_output_reg <= chan2_output_next;
+			chan3_output_reg <= chan3_output_next;
+			
+			volume_channel_0_reg<= volume_channel_0_next;
+			volume_channel_1_reg<= volume_channel_1_next;
+			volume_channel_2_reg<= volume_channel_2_next;
+			volume_channel_3_reg<= volume_channel_3_next;
+			
+			serin_reg <= serin_next;
+			serin_shift_reg <= serin_shift_next;
+			serin_bitcount_reg <= serin_bitcount_next;
+			serout_shift_reg <= serout_shift_next;
+			serout_bitcount_reg <= serout_bitcount_next;
+			
+			serout_holding_reg<=serout_holding_next;
+			serout_holding_full_reg<=serout_holding_full_next;
+			serout_active_reg <= serout_active_next;
+			
+			sio_out_reg <= sio_out_next;
+			serial_out_reg <= serial_out_next;
+			
+			serial_ip_framing_reg <= serial_ip_framing_next;
+			serial_ip_overrun_reg <= serial_ip_overrun_next;
+			
+			clock_reg <= clock_next;
+			clock_sync_reg <= clock_sync_next;
+			
+			keyboard_overrun_reg <= keyboard_overrun_next;
+			
+			serin_clock_reg <= serin_clock_next;
+			serin_clock_last_reg <= serin_clock_last_next;
+			serout_clock_reg <= serout_clock_next;
+			serout_clock_last_reg <= serout_clock_last_next;
+			
+			twotone_reg <= twotone_next;
+			
+			sio_in_reg <= sio_in_next;
+			
+			pot0_reg <= pot0_next;
+			pot1_reg <= pot1_next;
+			pot2_reg <= pot2_next;
+			pot3_reg <= pot3_next;
+			pot4_reg <= pot4_next;
+			pot5_reg <= pot5_next;
+			pot6_reg <= pot6_next;
+			pot7_reg <= pot7_next;
+			
+			pot_counter_reg <= pot_counter_next;
+			
+			pot_reset_reg <= pot_reset_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+	
+	-- clock selection
+	process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
+	begin
+		audf0_enable <= enable_64;
+		audf1_enable <= enable_64;
+		audf2_enable <= enable_64;
+		audf3_enable <= enable_64;		
+		
+		if (audctl_reg(0) = '1') then
+			audf0_enable <= enable_15;
+			audf1_enable <= enable_15;
+			audf2_enable <= enable_15;
+			audf3_enable <= enable_15;
+		end if;
+
+		if (audctl_reg(6) = '1') then
+			audf0_enable <= enable_179;
+		end if;
+		
+		if (audctl_reg(5) = '1') then
+			audf2_enable <= enable_179;
+		end if;
+		
+		if(audctl_reg(4) = '1') then
+			audf1_enable <= audf0_pulse;
+		end if;
+		
+		if(audctl_reg(3) = '1') then
+			audf3_enable <= audf2_pulse;
+		end if;
+	end process;
+	
+	-- Instantiate timers
+	timer0 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
+	timer1 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
+	timer2 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
+	timer3 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);		
+		
+	-- Timer reloading
+	process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
+	begin
+		audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
+		audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
+		audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
+		audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
+	end process;
+	
+	-- Writes to registers
+	process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
+	begin
+		audf0_next <= audf0_reg;
+		audc0_next <= audc0_reg;
+		audf1_next <= audf1_reg;
+		audc1_next <= audc1_reg;
+		audf2_next <= audf2_reg;
+		audc2_next <= audc2_reg;
+		audf3_next <= audf3_reg;
+		audc3_next <= audc3_reg;
+		audctl_next <= audctl_reg;		
+		
+		irqen_next <= irqen_reg;
+		skctl_next <= skctl_reg;
+		
+		stimer_write <= '0';
+		
+		serout_holding_load <= '0';
+		serout_holding_next <= serout_holding_reg;
+		
+		serial_reset <= '0';
+		skrest_write <= '0';
+		potgo_write <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				audf0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(1) = '1') then
+				audc0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(2) = '1') then
+				audf1_next <= data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				audc1_next <= data_in;
+			end if;
+			
+			if(addr_decoded(4) = '1') then
+				audf2_next <= data_in;
+			end if;
+
+			if(addr_decoded(5) = '1') then
+				audc2_next <= data_in;
+			end if;
+			
+			if(addr_decoded(6) = '1') then
+				audf3_next <= data_in;
+			end if;		
+
+			if(addr_decoded(7) = '1') then
+				audc3_next <= data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				audctl_next <= data_in;
+			end if;
+			
+			if (addr_decoded(9) = '1') then --STIMER
+				stimer_write <= '1';
+			end if;
+			
+			if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
+				skrest_write <= '1';
+			end if;
+
+			if (addr_decoded(11) = '1') then -- POTGO - start POT scan
+				potgo_write <= '1';
+			end if;
+			
+			if (addr_decoded(13) = '1') then --SEROUT								
+				serout_holding_next <= data_in;
+				serout_holding_load <= '1';
+			end if;
+			
+			if (addr_decoded(14) = '1') then --IRQEN
+				irqen_next <= data_in;
+			end if;
+
+			if (addr_decoded(15) = '1') then --SKCTL
+				skctl_next <= data_in;
+				
+				if (data_in(6 downto 4)="000") then
+					serial_reset <= '1';
+				end if;
+			end if;	
+	
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin
+		data_out <= X"FF";
+
+		if(addr_decoded(0) = '1') then --POT0
+			data_out <= pot0_reg;
+		end if;
+
+		if(addr_decoded(1) = '1') then --POT1
+			data_out <= pot1_reg;
+		end if;
+
+		if(addr_decoded(2) = '1') then --POT2
+			data_out <= pot2_reg;
+		end if;
+
+		if(addr_decoded(3) = '1') then --POT3
+			data_out <= pot3_reg;
+		end if;
+		
+		if(addr_decoded(4) = '1') then --POT4
+			data_out <= pot4_reg;
+		end if;
+
+		if(addr_decoded(5) = '1') then --POT5
+			data_out <= pot5_reg;
+		end if;
+
+		if(addr_decoded(6) = '1') then --POT6
+			data_out <= pot6_reg;
+		end if;
+
+		if(addr_decoded(7) = '1') then --POT7
+			data_out <= pot7_reg;
+		end if;
+
+		if(addr_decoded(8) = '1') then --ALLPOT
+			data_out <= not(pot_in);
+		end if;
+		
+		if(addr_decoded(9) = '1') then --KBCODE
+			data_out <= control_pressed&shift_pressed&kbcode;
+		end if;
+		
+		if(addr_decoded(10) = '1') then -- RANDOM
+			data_out <= RAND_OUT;
+		end if;
+
+		if (addr_decoded(13) = '1') then --SERIN			
+			data_out <= serin_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
+			data_out <= IRQST_REG;
+			--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
+		end if;		
+
+		if (addr_decoded(15) = '1') then --SKSTAT
+			data_out <= not(serial_ip_framing_reg)&not(serial_ip_overrun_reg)&not(keyboard_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
+		end if;		
+		
+	end process;
+	
+	-- Fire interrupts
+	process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
+	begin
+		-- clear interrupts
+		irqst_next <= irqst_reg or not(irqen_reg);
+				
+		irq_n_next <= '0';
+
+		if ((irqst_reg or "0000"&not(irqen_reg(3))&"000") = X"FF") then
+			irq_n_next <= '1';
+		end if;
+	
+		-- set interrupts
+		if (audf0_pulse = '1') then
+			irqst_next(0) <= not(irqen_reg(0));
+		end if;
+
+		if (audf1_pulse = '1') then
+			irqst_next(1) <= not(irqen_reg(1));
+		end if;
+
+		if (audf3_pulse = '1') then
+			irqst_next(2) <= not(irqen_reg(2));
+		end if;
+		
+		if (other_key_irq = '1') then
+			irqst_next(6) <= not(irqen_reg(6));			
+		end if;
+		
+		if (break_pressed = '1') then
+			irqst_next(7) <= not(irqen_reg(7));			
+		end if;		
+	
+		if (serial_ip_ready_interrupt = '1') then
+			irqst_next(5) <= not(irqen_reg(5));
+		end if;
+		
+		irqst_next(3) <= serout_active_reg;
+		
+		if (serial_op_needed_interrupt = '1') then
+			irqst_next(4) <= not(irqen_reg(4));
+		end if;
+		
+	end process;
+	
+	-- Instantiate delay for stimer reload_request
+	stimer_delay : delay_line
+		generic map (count=>3)
+		port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
+		
+	--stimer_write_delayed <= stimer_write;
+	
+	-- Instantiate audio noise filters
+	pokey_noise_filter0 : pokey_noise_filter
+		port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter1 : pokey_noise_filter
+		port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter2 : pokey_noise_filter
+		port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter3 : pokey_noise_filter
+		port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	
+	-- Audio output stage
+	process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
+	begin
+		chan0_output_next <= chan0_output_reg;
+		chan1_output_next <= chan1_output_reg;
+		chan2_output_next <= chan2_output_reg;
+		chan3_output_next <= chan3_output_reg;
+		
+		if (audf0_pulse_noise = '1') then
+			chan0_output_next <= not(chan0_output_reg);
+		end if;
+		
+		if (audf1_pulse_noise = '1') then
+			chan1_output_next <= not(chan1_output_reg);
+		end if;
+		
+		if (audf2_pulse_noise = '1') then
+			chan2_output_next <= not(chan2_output_reg);
+		end if;
+		
+		if (audf3_pulse_noise = '1') then
+			chan3_output_next <= not(chan3_output_reg);
+		end if;
+	end process;
+	
+	-- High pass filters
+	process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
+	begin
+		highpass0_next <= highpass0_reg;
+		highpass1_next <= highpass1_reg;
+		
+		if (audctl_reg(2) = '1') then
+			if (audf2_pulse = '1') then
+				highpass0_next <= chan0_output_reg;
+			end if;
+		else
+			highpass0_next <= '1';
+		end if;
+		
+		if (audctl_reg(1) = '1') then
+			if (audf3_pulse = '1') then
+				highpass1_next <= chan1_output_reg;
+			end if;
+		else
+			highpass1_next <= '1';
+		end if;
+		
+	end process;
+	
+	-- Instantiate key pokey clocks
+	-- ~1.79MHz - from 25MHz/14
+	-- ~64KHz - from 1.79MHz/28
+	-- ~15KHz - from 1.79MHz/114
+	--enable_179_div : enable_divider
+	--	generic map (COUNT=>14)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);		
+		
+	-- resetcount 6/33
+	enable_64_div : syncreset_enable_divider
+		generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
+		
+	enable_15_div : syncreset_enable_divider
+		generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
+		
+	-- Instantiate pokey noise circuits (lfsr)
+	initmode <= skctl_next(1) nor skctl_next(0);
+	poly_17_19_lfsr : poly_17_9
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
+		
+	poly_5_lfsr : poly_5
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
+		
+	poly_4_lfsr : poly_4
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
+	
+	--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
+	process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
+	begin
+		volume_channel_0_next <= "0000";
+		volume_channel_1_next <= "0000";
+		volume_channel_2_next <= "0000";
+		volume_channel_3_next <= "0000";
+			
+		if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
+			volume_channel_0_next <= audc0_reg(3 downto 0);
+		end if;
+		
+		if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
+			volume_channel_1_next <= audc1_reg(3 downto 0);
+		end if;
+		
+		if ((chan2_output_reg or audc2_reg(4)) = '1') then
+			volume_channel_2_next <= audc2_reg(3 downto 0);
+		end if;
+		
+		if ((chan3_output_reg or audc3_reg(4)) = '1') then
+			volume_channel_3_next <= audc3_reg(3 downto 0);
+		end if;
+		
+	end process;
+	
+	-- serial port output	
+	-- urghhh
+	serout_clock_delay : delay_line
+		generic map (count=>2)
+		port map (clk=>clk, sync_reset=>serial_reset or stimer_write_delayed,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+		
+	
+	process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
+	begin
+		serout_clock_next <= serout_clock_reg;
+		serout_clock_last_next <= serout_clock_reg;
+	
+		serout_shift_next <= serout_shift_reg;
+		serout_bitcount_next <= serout_bitcount_reg;
+		serout_holding_full_next <= serout_holding_full_reg;
+		serout_active_next <= serout_active_reg;
+		
+		serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
+		sio_out_next <= serial_out_reg;		
+	
+		-- two tone output
+		twotone_next <= twotone_reg;
+		twotone_reset <= '0';
+		
+		if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
+			twotone_next <= not(twotone_reg);
+			twotone_reset <= skctl_reg(3);
+		end if;
+		
+		if (skctl_reg(3) = '1') then
+			sio_out_next <= twotone_reg;
+		end if;
+	
+		-- force break
+		if (skctl_reg(7) = '1') then
+			sio_out_next <= '0';
+		end if;
+		
+		serial_op_needed_interrupt <= '0';		
+		
+		-- generate clock from enable signals
+		if (serout_enable_delayed = '1') then
+			serout_clock_next <= not(serout_clock_reg);
+		end if;
+		
+		-- output bits over sio
+		if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then			
+			serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
+			serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
+				
+			-- reload			
+			if (serout_bitcount_reg = X"0") then
+				if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
+					serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
+					serout_shift_next <= '1'&serout_holding_reg&'0';
+					serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
+					serout_holding_full_next <= '0';					
+					serial_op_needed_interrupt <= '1'; -- more data please!
+					serout_active_next <= '1';
+				else
+					serout_active_next <= '0';
+					serial_out_next <= '1'; -- remove blip! 
+				end if;
+			else
+				serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
+			end if;
+		end if;
+		
+		-- register to load has been written too, update our state to reflect that it is full
+		if (serout_holding_load = '1') then
+			serout_holding_full_next <= '1';
+		end if;
+		
+		if (serial_reset = '1') then
+			twotone_next <= '0';
+			serout_bitcount_next <= (others=>'0');
+			serout_shift_next <= (others=>'0');
+			serout_holding_full_next <= '0';
+			serout_clock_next <= '0';
+			serout_clock_last_next <= '0';
+			serout_active_next <= '0';
+		end if;
+	end process;
+	
+	-- serial port input
+	sio_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);	
+	sio_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);	
+	sio_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);	
+	sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
+		
+	waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
+	process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
+	begin
+		serin_clock_next <= serin_clock_reg;
+		serin_clock_last_next <= serin_clock_reg;
+	
+		serin_shift_next <= serin_shift_reg;
+		serin_bitcount_next <= serin_bitcount_reg;
+		serin_next <= serin_reg;
+		
+		serial_ip_overrun_next <= serial_ip_overrun_reg;
+		serial_ip_framing_next <= serial_ip_framing_reg;
+		serial_ip_ready_interrupt <= '0';
+		
+		async_serial_reset <= '0';
+		
+		-- generate clock from enable signals
+		if (serin_enable = '1') then
+			serin_clock_next <= not(serin_clock_reg);
+		end if;
+		
+		-- resync clock on receipt of start bit
+		if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
+			async_serial_reset <= '1';
+			serin_clock_next <= '1';
+		end if;
+		
+		-- receive bits into shift reg		
+		if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge					
+			if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then				
+				serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
+			
+				if (serin_bitcount_reg = X"0") then -- full byte
+					serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
+					
+					serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
+					
+					-- irq to alert new data avilable
+					serial_ip_ready_interrupt <= '1';
+					
+					-- flag up overrun
+					if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
+						serial_ip_overrun_next <= '1';
+					end if;				
+					
+					-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
+					if (sio_in_reg='0') then
+						serial_ip_framing_next <= '1';
+					end if;
+				else			
+					serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
+				end if;
+			end if;
+		end if;
+		
+		if (skrest_write = '1') then
+			serial_ip_overrun_next <= '0';
+			serial_ip_framing_next <= '0';
+		end if;
+		
+		if (serial_reset = '1') then
+			serin_clock_next <= '0';
+			serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
+			serin_shift_next <= (others=>'0');			
+		end if;		
+	end process;
+	
+	-- serial clocks
+	process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
+	begin
+		clock_next <= sio_clock;
+		clock_sync_next <= clock_reg;
+	
+		serout_enable <= '0';
+		serin_enable <= '0';
+		clock_input <= '1'; -- when output, outputs channel 4
+		
+		case skctl_reg(6 downto 4) is
+			when "000" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "001" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "010" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+				clock_input <= '0';
+			when "011" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "100" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= audf3_pulse;
+			when "101" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "110" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+				clock_input <= '0';
+			when "111" =>			
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+		end case;
+	end process;
+	
+	-- keyboard overrun (i.e. second key pressed before interrupt cleared)
+	process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
+	begin
+		keyboard_overrun_next <= keyboard_overrun_reg;
+		
+		if (other_key_irq='1' and irqst_reg(6)='0') then
+			keyboard_overrun_next <= '1';
+		end if;
+		
+		if (skrest_write = '1') then
+			keyboard_overrun_next <= '0';
+		end if;
+	end process;
+	
+	-- keyboard scan
+	pokey_keyboard_scanner1 : pokey_keyboard_scanner
+		port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);	
+	
+	-- POT scan
+	process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin	
+		pot0_next <= pot0_reg;
+		pot1_next <= pot1_reg;
+		pot2_next <= pot2_reg;
+		pot3_next <= pot3_reg;
+		pot4_next <= pot4_reg;
+		pot5_next <= pot5_reg;
+		pot6_next <= pot6_reg;
+		pot7_next <= pot7_reg;
+		
+		pot_reset_next <= pot_reset_reg;
+		
+		pot_counter_next <= pot_counter_reg;
+		
+		if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
+			pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
+			if (pot_counter_reg = X"E4") then
+				pot_reset_next <= '1'; -- turn on pot dump transistors
+			end if;
+			
+			if (pot_reset_reg = '0') then
+				if (pot_in(0) = '0') then -- pot now high, latch
+					pot0_next <= pot_counter_reg;
+				end if;
+				if (pot_in(1) = '0') then -- pot now high, latch
+					pot1_next <= pot_counter_reg;
+				end if;				
+				if (pot_in(2) = '0') then -- pot now high, latch
+					pot2_next <= pot_counter_reg;
+				end if;
+				if (pot_in(3) = '0') then -- pot now high, latch
+					pot3_next <= pot_counter_reg;
+				end if;
+				if (pot_in(4) = '0') then -- pot now high, latch
+					pot4_next <= pot_counter_reg;
+				end if;
+				if (pot_in(5) = '0') then -- pot now high, latch
+					pot5_next <= pot_counter_reg;
+				end if;
+				if (pot_in(6) = '0') then -- pot now high, latch
+					pot6_next <= pot_counter_reg;
+				end if;
+				if (pot_in(7) = '0') then -- pot now high, latch
+					pot7_next <= pot_counter_reg;
+				end if;
+			end if;			
+		end if;
+			
+		if (potgo_write = '1') then
+			pot_counter_next <= (others=>'0');
+			pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
+		end if;		
+	end process;
+	
+	-- Outputs
+	irq_n_out <= irq_n_reg;	
+	
+	CHANNEL_0_OUT <= volume_channel_0_reg;
+	CHANNEL_1_OUT <= volume_channel_1_reg;
+	CHANNEL_2_OUT <= volume_channel_2_reg;
+	CHANNEL_3_OUT <= volume_channel_3_reg;
+	
+	sio_out1 <= sio_out_reg;	
+	sio_out2 <= sio_out_reg;	
+	sio_out3 <= sio_out_reg;	
+	
+	sio_clock <= audf3_pulse when clock_input='0' else 'Z';
+	
+	pot_reset <= pot_reset_reg;
+		
+END vhdl;
+
+
Index: unmerged/core/mcc216/pokey_ps2_decoder.vhdl
===================================================================
--- unmerged/core/mcc216/pokey_ps2_decoder.vhdl	(nonexistent)
+++ unmerged/core/mcc216/pokey_ps2_decoder.vhdl	(revision 1)
@@ -0,0 +1,468 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_ps2_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : std_logic;
+	-- ENABLE : IN STD_LOGIC; TODO Pokey debounce and scanning can be disabled
+	
+	-- ps2 keyboard input
+	KEY_EVENT : IN STD_LOGIC;
+	KEY_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
+	KEY_EXTENDED : IN STD_LOGIC;
+	KEY_UP : IN STD_LOGIC;
+	
+	-- pokey output
+	KBCODE : OUT STD_LOGIC_VECTOR(7 downto 0);
+	KEY_HELD : OUT STD_LOGIC;
+	SHIFT_PRESSED : OUT STD_LOGIC;
+	BREAK_PRESSED : OUT STD_LOGIC;
+	KEY_INTERRUPT : OUT STD_LOGIC;
+	
+	-- other output
+	CONSOL_START : OUT STD_LOGIC;
+	CONSOL_SELECT : OUT STD_LOGIC;
+	CONSOL_OPTION : OUT STD_LOGIC;
+	
+	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+	
+	SYSTEM_RESET : out std_logic;
+	
+	VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+);
+END pokey_ps2_decoder;
+
+ARCHITECTURE vhdl OF pokey_ps2_decoder IS
+	signal left_shift_pressed_reg : std_logic;
+	signal left_shift_pressed_next : std_logic;
+	signal right_shift_pressed_reg : std_logic;
+	signal right_shift_pressed_next : std_logic;	
+	
+	signal left_control_pressed_reg : std_logic;
+	signal left_control_pressed_next : std_logic;	
+	signal right_control_pressed_reg : std_logic;
+	signal right_control_pressed_next : std_logic;	
+	
+	signal kbcode_next : std_logic_vector(7 downto 0);
+	signal kbcode_reg : std_logic_vector(7 downto 0); -- XXX remove unused upper bits
+	
+	signal interrupt_next : std_logic;
+	signal interrupt_reg : std_logic;
+	
+	signal break_next : std_logic;
+	signal break_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal start_next : std_logic;
+	signal start_reg : std_logic;
+	signal select_next : std_logic;
+	signal select_reg : std_logic;	
+	signal option_next : std_logic;
+	signal option_reg : std_logic;
+	
+	signal virtual_up_next : std_logic;
+	signal virtual_up_reg : std_logic;
+	signal virtual_down_next : std_logic;
+	signal virtual_down_reg : std_logic;
+	signal virtual_left_next : std_logic;
+	signal virtual_left_reg : std_logic;
+	signal virtual_right_next : std_logic;
+	signal virtual_right_reg : std_logic;
+	signal virtual_stick_pressed_next : std_logic;
+	signal virtual_stick_pressed_reg : std_logic;
+	
+	signal system_reset_next : std_logic;
+	signal system_reset_reg : std_logic;	
+
+	signal virtual_keys_next : std_logic_vector(3 downto 0);
+	signal virtual_keys_reg : std_logic_vector(3 downto 0);	
+	
+	signal no_kbcode_update : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			left_shift_pressed_reg <= '0';
+			right_shift_pressed_reg <= '0';
+			
+			left_control_pressed_reg <= '0';
+			right_control_pressed_reg <= '0';
+			
+			kbcode_reg <= X"3F";
+			
+			interrupt_reg <= '0';
+			
+			break_reg <= '0';
+			
+			key_held_reg <= '0';
+			
+			start_reg <= '0';
+			select_reg <= '0';
+			option_reg <= '0';
+			
+			virtual_up_reg <= '0';
+			virtual_down_reg <= '0';
+			virtual_left_reg <= '0';
+			virtual_right_reg <= '0';
+			virtual_stick_pressed_reg <= '0';
+			
+			system_reset_reg <= '0';
+			
+			virtual_keys_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			left_shift_pressed_reg <= left_shift_pressed_next;
+			right_shift_pressed_reg <= right_shift_pressed_next;
+			
+			left_control_pressed_reg <= left_control_pressed_next;
+			right_control_pressed_reg <= right_control_pressed_next;			
+			
+			kbcode_reg <= kbcode_next;
+			
+			interrupt_reg <= interrupt_next;
+			
+			break_reg <= break_next;
+			
+			key_held_reg <= key_held_next;
+			
+			start_reg <= start_next;
+			select_reg <= select_next;
+			option_reg <= option_next;
+			
+			virtual_up_reg <= virtual_up_next;
+			virtual_down_reg <= virtual_down_next;
+			virtual_left_reg <= virtual_left_next;
+			virtual_right_reg <= virtual_right_next;
+			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+			
+			system_reset_reg <= system_reset_next;
+			virtual_keys_reg <= virtual_keys_next;
+		end if;
+	end process;
+	
+	-- update key pressed
+	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg, virtual_keys_reg)
+	begin
+		left_shift_pressed_next <= left_shift_pressed_reg;
+		right_shift_pressed_next <= right_shift_pressed_reg;
+		
+		left_control_pressed_next <= left_control_pressed_reg;
+		right_control_pressed_next <= right_control_pressed_reg;		
+	
+		kbcode_next <= kbcode_reg;
+		interrupt_next <= '0';
+		
+		break_next <= break_reg;
+	
+		start_next <= start_reg;
+		select_next <= select_reg;
+		option_next <= option_reg;
+		
+		virtual_up_next <= virtual_up_reg;
+		virtual_down_next <= virtual_down_reg;
+		virtual_left_next <= virtual_left_reg;
+		virtual_right_next <= virtual_right_reg;				
+		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+		
+		system_reset_next <= system_reset_reg;
+		virtual_keys_next <= virtual_keys_reg;
+		
+		key_held_next <= key_held_reg;
+		
+		no_kbcode_update <= '0';
+	
+		-- Core functionality exactly as the Atari layout
+		if (key_event = '1') then
+			interrupt_next <= not(key_up);			
+			key_held_next <= not(key_up);
+			
+			case key_extended&key_code is 
+			
+				-- Basic mapping - should allow all keys on Atari, just fiddly
+				when 
+					'0'&X"AA"|'1'&X"AA"|  -- BAT SUCCESSFUL
+					'0'&X"FC"|'1'&X"FC"   -- BAT FAIL
+					=>
+					no_kbcode_update <= '1';
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"4B" => --L
+					kbcode_next <= X"00";
+				when '0'&X"3B" => --J
+					kbcode_next <= X"01";					
+				when '0'&X"4C" => --;
+					kbcode_next <= X"02";										
+				when '0'&X"42" => --K
+					kbcode_next <= X"05";				
+				when '0'&X"79" => --+
+					kbcode_next <= X"06";
+				when '0'&X"7C" => --*
+					kbcode_next <= X"07";
+				when '0'&X"44" => --O
+					kbcode_next <= X"08";
+				when '0'&X"4D" => --P
+					kbcode_next <= X"0A";
+				when '0'&X"3C" => --U
+					kbcode_next <= X"0B";
+				when '0'&X"5A" => --Enter
+					kbcode_next <= X"0C";
+				when '0'&X"43" => --I
+					kbcode_next <= X"0D";
+				when '0'&X"4E" => -- -
+					kbcode_next <= X"0E";
+				when '0'&X"55" => -- =
+					kbcode_next <= X"0F";
+
+				when '0'&X"2A" => --V
+					kbcode_next <= X"10";
+				when '0'&X"05" => --Help (Using F1)
+					kbcode_next <= X"11";					
+				when '0'&X"21" => --C
+					kbcode_next <= X"12";										
+				when '0'&X"32" => --B
+					kbcode_next <= X"15";				
+				when '0'&X"22" => --X
+					kbcode_next <= X"16";
+				when '0'&X"1A" => --Z
+					kbcode_next <= X"17";
+				when '0'&X"25" => --4
+					kbcode_next <= X"18";
+				when '0'&X"26" => --3
+					kbcode_next <= X"1A";
+				when '0'&X"36" => --6
+					kbcode_next <= X"1B";
+				when '0'&X"76" => --Esc
+					kbcode_next <= X"1C";
+				when '0'&X"2E" => --5
+					kbcode_next <= X"1D";
+				when '0'&X"1E" => --2
+					kbcode_next <= X"1E";
+				when '0'&X"16" => --1
+					kbcode_next <= X"1F";
+
+				when '0'&X"41" => --,
+					kbcode_next <= X"20";
+				when '0'&X"29" => --Spc
+					kbcode_next <= X"21";					
+				when '0'&X"49" => --.
+					kbcode_next <= X"22";										
+				when '0'&X"31" => --N
+					kbcode_next <= X"23";
+				when '0'&X"3A" => --M
+					kbcode_next <= X"25";				
+				when '0'&X"4A" => --/
+					kbcode_next <= X"26";
+				when '1'&X"11" => --Inv
+					kbcode_next <= X"27";
+				when '0'&X"2D" => --R
+					kbcode_next <= X"28";
+				when '0'&X"24" => --E
+					kbcode_next <= X"2A";
+				when '0'&X"35" => --Y
+					kbcode_next <= X"2B";
+				when '0'&X"0D" => --Tab
+					kbcode_next <= X"2C";
+				when '0'&X"2C" => --T
+					kbcode_next <= X"2D";
+				when '0'&X"1D" => --W
+					kbcode_next <= X"2E";
+				when '0'&X"15" => --Q
+					kbcode_next <= X"2F";					
+					
+				when '0'&X"46" => --9
+					kbcode_next <= X"30";				
+				when '0'&X"45" => --0
+					kbcode_next <= X"32";										
+				when '0'&X"3D" => --7
+					kbcode_next <= X"33";
+				when '0'&X"66" => --Backspace
+					kbcode_next <= X"34";						
+				when '0'&X"3E" => --8
+					kbcode_next <= X"35";				
+				when '0'&X"54" => --< (using [)
+					kbcode_next <= X"36";
+				when '0'&X"5B" => --> (using ])
+					kbcode_next <= X"37";
+				when '0'&X"2B" => --F
+					kbcode_next <= X"38";
+				when '0'&X"33" => --H
+					kbcode_next <= X"39";					
+				when '0'&X"23" => --D
+					kbcode_next <= X"3A";
+				when '0'&X"58" => --Caps
+					kbcode_next <= X"3C";
+				when '0'&X"34" => --G
+					kbcode_next <= X"3D";
+				when '0'&X"1B" => --S
+					kbcode_next <= X"3E";
+				when '0'&X"1C" => --A
+					kbcode_next <= X"3F";
+
+				when '0'&X"77" => --Break - XXX BUG, also presses 14, since E1 ext code...
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+				when '1'&X"77" => --Break
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+					
+				-- XXX BUGS
+				-- i) press shift when already holding key - does not update kbcode
+				-- ii) press key, then press another, then release second key. Should go back to first...
+				when '0'&X"12" => --Left shift
+					no_kbcode_update <= '1';
+					left_shift_pressed_next <= not(key_UP);					
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"59" => --Right shift
+					no_kbcode_update <= '1';
+					right_shift_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+					
+				when '0'&X"14" => --Left control
+					no_kbcode_update <= '1';
+					left_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '1'&X"14" => --Right control
+					no_kbcode_update <= '1';
+					right_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';			
+					key_held_next <= '0';
+					
+				when '0'&X"06" => --Start (F2)
+					no_kbcode_update <= '1';
+					start_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"04" => --Select (F3)
+					no_kbcode_update <= '1';
+					select_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"0C" => --Option (F4)
+					no_kbcode_update <= '1';
+					option_next <= not(key_UP);
+					interrupt_next <= '0';					
+					key_held_next <= '0';
+
+				-- TODO will also be useful to cursor control...
+				when '1'&X"75" => -- up
+					no_kbcode_update <= '1';
+					virtual_up_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"72" => -- down
+					no_kbcode_update <= '1';
+					virtual_down_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"6b" => -- left
+					no_kbcode_update <= '1';
+					virtual_left_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"74" => -- right
+					no_kbcode_update <= '1';
+					virtual_right_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';
+				when '1'&X"27" => -- right windows key -> fire button
+					no_kbcode_update <= '1';
+					virtual_stick_pressed_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"0a" => -- f8 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(0) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"01" => -- f9 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(1) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';						
+					
+				when '0'&X"09" => -- f10 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(2) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';						
+					
+				when '0'&X"78" => -- f11 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(3) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"07" => -- f12 => system reset
+					no_kbcode_update <= '1';
+					system_reset_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';										
+					
+				when others =>
+					no_kbcode_update <= '1';
+					-- nop
+				-- Idea: Use Windows key and Alt for atari shift/control. Then use keyboard ones for 'nice' mapping as displayed on keyboard?
+			end case;
+			
+			if (key_up = '1' or no_kbcode_update = '1') then
+				kbcode_next <= kbcode_reg;				
+			else
+				kbcode_next(7 downto 6) <= (left_control_pressed_reg or right_control_pressed_reg)&(left_shift_pressed_reg or right_shift_pressed_reg);
+			end if;
+		end if;
+		
+		-- Then override a few for convenience
+		-- e.g. if we press '#' on the keyboard we want to see '#' on the atari, even though on the atari its shift a different key.
+
+--http://atariwiki.de/wiki/Wiki.jsp?page=KBCODE
+-- 			$00	$01	$02	$03	$04	$05	$06	$07	$08	$09	$0A	$0B	$0C	$0D	$0E	$0F
+--		$00	L		J		;		F1		F2		K		+		*		O	 			P		U		CR		I		-		=
+--		$10	V		Help	C		F3		F4		B		X		Z		4	 			3		6		Esc	5		2		1
+--		$20	,		Spc	.		N	 			M		/		Inv	R	 			E		Y		Tab	T		W		Q
+--		$30	9	 			0		7		BS		8		<		>		F		H		D	 			Caps	G		S		A
+--together with Shift Key: add +$40
+--together with Control key: add +$80
+
+-- Would be great to have option of using real Atari keyboard, but probably not worthwhile yet.
+
+	end process;
+			
+	-- output
+	kbcode <= kbcode_reg;
+	KEY_HELD <= key_held_reg;
+	shift_pressed <= left_shift_pressed_reg or right_shift_pressed_reg;
+	break_pressed <= break_reg;
+	
+	key_interrupt <= interrupt_reg;
+	
+	consol_start <= start_reg;
+	consol_select <= select_reg;
+	consol_option <= option_reg;
+	
+	VIRTUAL_STICKS <= not(virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg&virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg);
+	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+	
+	system_reset <= system_reset_reg;
+	virtual_keys <= virtual_keys_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/poly_17_9.vhdl
===================================================================
--- unmerged/core/mcc216/poly_17_9.vhdl	(nonexistent)
+++ unmerged/core/mcc216/poly_17_9.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_17_9 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC;
+	
+	RAND_OUT : OUT std_logic_vector(7 downto 0)
+);
+END poly_17_9;
+
+ARCHITECTURE vhdl OF poly_17_9 IS
+	signal shift_reg: std_logic_vector(16 downto 0);
+	signal shift_next: std_logic_vector(16 downto 0);
+	
+	signal feedback : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010101010101010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state (as pokey decap)
+	feedback <= shift_reg(13) xnor shift_reg(8);
+	process(enable,shift_reg,feedback,select_9_17,init)
+	begin
+		shift_next <= shift_reg;
+		
+		if (enable = '1') then	
+			shift_next(15 downto 8) <= shift_reg(16 downto 9);	
+			shift_next(7) <= feedback;
+			shift_next(6 downto 0) <= shift_reg(7 downto 1);
+
+			shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
+		end if;
+	end process;
+	
+		-- output
+	bit_out <= shift_reg(9);
+	RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
+		
+END vhdl;
Index: unmerged/core/mcc216/ramint.bsf
===================================================================
--- unmerged/core/mcc216/ramint.bsf	(nonexistent)
+++ unmerged/core/mcc216/ramint.bsf	(revision 1)
@@ -0,0 +1,105 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "ramint" (rect 90 0 132 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 4 18 47 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 88 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "address[12..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
+		(text "address[12..0]" (rect 4 50 72 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 88 64)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 80 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 136 32)(line_width 3))
+	)
+	(drawing
+		(text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical))
+		(text "8192 words" (rect 120 12 214 177)(font "Arial" )(vertical))
+		(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 88 43)(pt 96 43))
+		(line (pt 96 43)(pt 96 55))
+		(line (pt 96 55)(pt 88 55))
+		(line (pt 88 55)(pt 88 43))
+		(line (pt 88 50)(pt 90 52))
+		(line (pt 90 52)(pt 88 54))
+		(line (pt 80 52)(pt 88 52))
+		(line (pt 96 48)(pt 104 48))
+		(line (pt 88 59)(pt 96 59))
+		(line (pt 96 59)(pt 96 71))
+		(line (pt 96 71)(pt 88 71))
+		(line (pt 88 71)(pt 88 59))
+		(line (pt 88 66)(pt 90 68))
+		(line (pt 90 68)(pt 88 70))
+		(line (pt 80 68)(pt 88 68))
+		(line (pt 96 64)(pt 104 64)(line_width 3))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
Index: unmerged/core/mcc216/reg_file.vhdl
===================================================================
--- unmerged/core/mcc216/reg_file.vhdl	(nonexistent)
+++ unmerged/core/mcc216/reg_file.vhdl	(revision 1)
@@ -0,0 +1,85 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END reg_file;
+
+ARCHITECTURE vhdl OF reg_file IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+
+	type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
+
+	signal digit_next : reg_file_type;
+	signal digit_reg : reg_file_type;
+	
+	signal addr_decoded : std_logic_vector(2**width-1 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => WIDTH)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(digit_reg,addr_decoded,data_in,WR_EN)
+	begin
+		digit_next <= digit_reg;
+		
+		if (WR_EN = '1') then		
+			comp_gen:
+			for i in 0 to (BYTES-1) loop
+				if (addr_decoded(i) = '1') then				
+					digit_next(i) <= data_in;
+				end if;
+			end loop;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	-- output
+	process(addr_decoded,digit_reg)
+	begin
+		data_out <= X"FF";
+		comp_gen:
+		for i in 0 to (BYTES-1) loop
+			if (addr_decoded(i) = '1') then				
+				data_out <= digit_reg(i);
+			end if;
+		end loop;	
+	end process;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/romhi.vhd
===================================================================
--- unmerged/core/mcc216/romhi.vhd	(nonexistent)
+++ unmerged/core/mcc216/romhi.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: romhi.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY romhi IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END romhi;
+
+
+ARCHITECTURE SYN OF romhi IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_8k.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 8192,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 13,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_8k.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_8k.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mcc216/romlo.vhd
===================================================================
--- unmerged/core/mcc216/romlo.vhd	(nonexistent)
+++ unmerged/core/mcc216/romlo.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: romlo.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY romlo IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END romlo;
+
+
+ARCHITECTURE SYN OF romlo IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_2k.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 11,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_2k.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_2k.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mcc216/pokey_ps2_decoder.vhdl.bak
===================================================================
--- unmerged/core/mcc216/pokey_ps2_decoder.vhdl.bak	(nonexistent)
+++ unmerged/core/mcc216/pokey_ps2_decoder.vhdl.bak	(revision 1)
@@ -0,0 +1,434 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_ps2_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : std_logic;
+	-- ENABLE : IN STD_LOGIC; TODO Pokey debounce and scanning can be disabled
+	
+	-- ps2 keyboard input
+	KEY_EVENT : IN STD_LOGIC;
+	KEY_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
+	KEY_EXTENDED : IN STD_LOGIC;
+	KEY_UP : IN STD_LOGIC;
+	
+	-- pokey output
+	KBCODE : OUT STD_LOGIC_VECTOR(7 downto 0);
+	KEY_HELD : OUT STD_LOGIC;
+	SHIFT_PRESSED : OUT STD_LOGIC;
+	BREAK_PRESSED : OUT STD_LOGIC;
+	KEY_INTERRUPT : OUT STD_LOGIC;
+	
+	-- other output
+	CONSOL_START : OUT STD_LOGIC;
+	CONSOL_SELECT : OUT STD_LOGIC;
+	CONSOL_OPTION : OUT STD_LOGIC;
+	
+	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+	
+	SYSTEM_RESET : out std_logic
+);
+END pokey_ps2_decoder;
+
+ARCHITECTURE vhdl OF pokey_ps2_decoder IS
+	signal left_shift_pressed_reg : std_logic;
+	signal left_shift_pressed_next : std_logic;
+	signal right_shift_pressed_reg : std_logic;
+	signal right_shift_pressed_next : std_logic;	
+	
+	signal left_control_pressed_reg : std_logic;
+	signal left_control_pressed_next : std_logic;	
+	signal right_control_pressed_reg : std_logic;
+	signal right_control_pressed_next : std_logic;	
+	
+	signal kbcode_next : std_logic_vector(7 downto 0);
+	signal kbcode_reg : std_logic_vector(7 downto 0); -- XXX remove unused upper bits
+	
+	signal interrupt_next : std_logic;
+	signal interrupt_reg : std_logic;
+	
+	signal break_next : std_logic;
+	signal break_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal start_next : std_logic;
+	signal start_reg : std_logic;
+	signal select_next : std_logic;
+	signal select_reg : std_logic;	
+	signal option_next : std_logic;
+	signal option_reg : std_logic;
+	
+	signal virtual_up_next : std_logic;
+	signal virtual_up_reg : std_logic;
+	signal virtual_down_next : std_logic;
+	signal virtual_down_reg : std_logic;
+	signal virtual_left_next : std_logic;
+	signal virtual_left_reg : std_logic;
+	signal virtual_right_next : std_logic;
+	signal virtual_right_reg : std_logic;
+	signal virtual_stick_pressed_next : std_logic;
+	signal virtual_stick_pressed_reg : std_logic;
+	
+	signal system_reset_next : std_logic;
+	signal system_reset_reg : std_logic;	
+	
+	signal no_kbcode_update : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			left_shift_pressed_reg <= '0';
+			right_shift_pressed_reg <= '0';
+			
+			left_control_pressed_reg <= '0';
+			right_control_pressed_reg <= '0';
+			
+			kbcode_reg <= X"3F";
+			
+			interrupt_reg <= '0';
+			
+			break_reg <= '0';
+			
+			key_held_reg <= '0';
+			
+			start_reg <= '0';
+			select_reg <= '0';
+			option_reg <= '0';
+			
+			virtual_up_reg <= '0';
+			virtual_down_reg <= '0';
+			virtual_left_reg <= '0';
+			virtual_right_reg <= '0';
+			virtual_stick_pressed_reg <= '0';
+			
+			system_reset_reg <= '0';
+		elsif (clk'event and clk='1') then
+			left_shift_pressed_reg <= left_shift_pressed_next;
+			right_shift_pressed_reg <= right_shift_pressed_next;
+			
+			left_control_pressed_reg <= left_control_pressed_next;
+			right_control_pressed_reg <= right_control_pressed_next;			
+			
+			kbcode_reg <= kbcode_next;
+			
+			interrupt_reg <= interrupt_next;
+			
+			break_reg <= break_next;
+			
+			key_held_reg <= key_held_next;
+			
+			start_reg <= start_next;
+			select_reg <= select_next;
+			option_reg <= option_next;
+			
+			virtual_up_reg <= virtual_up_next;
+			virtual_down_reg <= virtual_down_next;
+			virtual_left_reg <= virtual_left_next;
+			virtual_right_reg <= virtual_right_next;
+			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+			
+			system_reset_reg <= system_reset_next;
+		end if;
+	end process;
+	
+	-- update key pressed
+	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg)
+	begin
+		left_shift_pressed_next <= left_shift_pressed_reg;
+		right_shift_pressed_next <= right_shift_pressed_reg;
+		
+		left_control_pressed_next <= left_control_pressed_reg;
+		right_control_pressed_next <= right_control_pressed_reg;		
+	
+		kbcode_next <= kbcode_reg;
+		interrupt_next <= '0';
+		
+		break_next <= break_reg;
+	
+		start_next <= start_reg;
+		select_next <= select_reg;
+		option_next <= option_reg;
+		
+		virtual_up_next <= virtual_up_reg;
+		virtual_down_next <= virtual_down_reg;
+		virtual_left_next <= virtual_left_reg;
+		virtual_right_next <= virtual_right_reg;				
+		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+		
+		system_reset_next <= system_reset_reg;
+		
+		key_held_next <= key_held_reg;
+		
+		no_kbcode_update <= '0';
+	
+		-- Core functionality exactly as the Atari layout
+		if (key_event = '1') then
+			interrupt_next <= not(key_up);			
+			key_held_next <= not(key_up);
+			
+			case key_extended&key_code is 
+			
+				-- Basic mapping - should allow all keys on Atari, just fiddly
+				when 
+					'0'&X"AA"|'1'&X"AA"|  -- BAT SUCCESSFUL
+					'0'&X"FC"|'1'&X"FC"   -- BAT FAIL
+					=>
+					no_kbcode_update <= '1';
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"4B" => --L
+					kbcode_next <= X"00";
+				when '0'&X"3B" => --J
+					kbcode_next <= X"01";					
+				when '0'&X"4C" => --;
+					kbcode_next <= X"02";										
+				when '0'&X"42" => --K
+					kbcode_next <= X"05";				
+				when '0'&X"79" => --+
+					kbcode_next <= X"06";
+				when '0'&X"7C" => --*
+					kbcode_next <= X"07";
+				when '0'&X"44" => --O
+					kbcode_next <= X"08";
+				when '0'&X"4D" => --P
+					kbcode_next <= X"0A";
+				when '0'&X"3C" => --U
+					kbcode_next <= X"0B";
+				when '0'&X"5A" => --Enter
+					kbcode_next <= X"0C";
+				when '0'&X"43" => --I
+					kbcode_next <= X"0D";
+				when '0'&X"4E" => -- -
+					kbcode_next <= X"0E";
+				when '0'&X"55" => -- =
+					kbcode_next <= X"0F";
+
+				when '0'&X"2A" => --V
+					kbcode_next <= X"10";
+				when '0'&X"05" => --Help (Using F1)
+					kbcode_next <= X"11";					
+				when '0'&X"21" => --C
+					kbcode_next <= X"12";										
+				when '0'&X"32" => --B
+					kbcode_next <= X"15";				
+				when '0'&X"22" => --X
+					kbcode_next <= X"16";
+				when '0'&X"1A" => --Z
+					kbcode_next <= X"17";
+				when '0'&X"25" => --4
+					kbcode_next <= X"18";
+				when '0'&X"26" => --3
+					kbcode_next <= X"1A";
+				when '0'&X"36" => --6
+					kbcode_next <= X"1B";
+				when '0'&X"76" => --Esc
+					kbcode_next <= X"1C";
+				when '0'&X"2E" => --5
+					kbcode_next <= X"1D";
+				when '0'&X"1E" => --2
+					kbcode_next <= X"1E";
+				when '0'&X"16" => --1
+					kbcode_next <= X"1F";
+
+				when '0'&X"41" => --,
+					kbcode_next <= X"20";
+				when '0'&X"29" => --Spc
+					kbcode_next <= X"21";					
+				when '0'&X"49" => --.
+					kbcode_next <= X"22";										
+				when '0'&X"31" => --N
+					kbcode_next <= X"23";
+				when '0'&X"3A" => --M
+					kbcode_next <= X"25";				
+				when '0'&X"4A" => --/
+					kbcode_next <= X"26";
+				when '1'&X"11" => --Inv
+					kbcode_next <= X"27";
+				when '0'&X"2D" => --R
+					kbcode_next <= X"28";
+				when '0'&X"24" => --E
+					kbcode_next <= X"2A";
+				when '0'&X"35" => --Y
+					kbcode_next <= X"2B";
+				when '0'&X"0D" => --Tab
+					kbcode_next <= X"2C";
+				when '0'&X"2C" => --T
+					kbcode_next <= X"2D";
+				when '0'&X"1D" => --W
+					kbcode_next <= X"2E";
+				when '0'&X"15" => --Q
+					kbcode_next <= X"2F";					
+					
+				when '0'&X"46" => --9
+					kbcode_next <= X"30";				
+				when '0'&X"45" => --0
+					kbcode_next <= X"32";										
+				when '0'&X"3D" => --7
+					kbcode_next <= X"33";
+				when '0'&X"66" => --Backspace
+					kbcode_next <= X"34";						
+				when '0'&X"3E" => --8
+					kbcode_next <= X"35";				
+				when '0'&X"54" => --< (using [)
+					kbcode_next <= X"36";
+				when '0'&X"5B" => --> (using ])
+					kbcode_next <= X"37";
+				when '0'&X"2B" => --F
+					kbcode_next <= X"38";
+				when '0'&X"33" => --H
+					kbcode_next <= X"39";					
+				when '0'&X"23" => --D
+					kbcode_next <= X"3A";
+				when '0'&X"58" => --Caps
+					kbcode_next <= X"3C";
+				when '0'&X"34" => --G
+					kbcode_next <= X"3D";
+				when '0'&X"1B" => --S
+					kbcode_next <= X"3E";
+				when '0'&X"1C" => --A
+					kbcode_next <= X"3F";
+
+				when '0'&X"77" => --Break - XXX BUG, also presses 14, since E1 ext code...
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+				when '1'&X"77" => --Break
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+					
+				-- XXX BUGS
+				-- i) press shift when already holding key - does not update kbcode
+				-- ii) press key, then press another, then release second key. Should go back to first...
+				when '0'&X"12" => --Left shift
+					no_kbcode_update <= '1';
+					left_shift_pressed_next <= not(key_UP);					
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"59" => --Right shift
+					no_kbcode_update <= '1';
+					right_shift_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+					
+				when '0'&X"14" => --Left control
+					no_kbcode_update <= '1';
+					left_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '1'&X"14" => --Right control
+					no_kbcode_update <= '1';
+					right_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';			
+					key_held_next <= '0';
+					
+				when '0'&X"06" => --Start (F2)
+					no_kbcode_update <= '1';
+					start_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"04" => --Select (F3)
+					no_kbcode_update <= '1';
+					select_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"0C" => --Option (F4)
+					no_kbcode_update <= '1';
+					option_next <= not(key_UP);
+					interrupt_next <= '0';					
+					key_held_next <= '0';
+
+				-- TODO will also be useful to cursor control...
+				when '1'&X"75" => -- up
+					no_kbcode_update <= '1';
+					virtual_up_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"72" => -- down
+					no_kbcode_update <= '1';
+					virtual_down_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"6b" => -- left
+					no_kbcode_update <= '1';
+					virtual_left_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"74" => -- right
+					no_kbcode_update <= '1';
+					virtual_right_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';
+				when '1'&X"27" => -- right windows key -> fire button
+					no_kbcode_update <= '1';
+					virtual_stick_pressed_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';					
+					
+				when '0'&X"07" => -- f12 => system reset
+					no_kbcode_update <= '1';
+					system_reset_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';										
+					
+				when others =>
+					no_kbcode_update <= '1';
+					-- nop
+				-- Idea: Use Windows key and Alt for atari shift/control. Then use keyboard ones for 'nice' mapping as displayed on keyboard?
+			end case;
+			
+			if (key_up = '1' or no_kbcode_update = '1') then
+				kbcode_next <= kbcode_reg;				
+			else
+				kbcode_next(7 downto 6) <= (left_control_pressed_reg or right_control_pressed_reg)&(left_shift_pressed_reg or right_shift_pressed_reg);
+			end if;
+		end if;
+		
+		-- Then override a few for convenience
+		-- e.g. if we press '#' on the keyboard we want to see '#' on the atari, even though on the atari its shift a different key.
+
+--http://atariwiki.de/wiki/Wiki.jsp?page=KBCODE
+-- 			$00	$01	$02	$03	$04	$05	$06	$07	$08	$09	$0A	$0B	$0C	$0D	$0E	$0F
+--		$00	L		J		;		F1		F2		K		+		*		O	 			P		U		CR		I		-		=
+--		$10	V		Help	C		F3		F4		B		X		Z		4	 			3		6		Esc	5		2		1
+--		$20	,		Spc	.		N	 			M		/		Inv	R	 			E		Y		Tab	T		W		Q
+--		$30	9	 			0		7		BS		8		<		>		F		H		D	 			Caps	G		S		A
+--together with Shift Key: add +$40
+--together with Control key: add +$80
+
+-- Would be great to have option of using real Atari keyboard, but probably not worthwhile yet.
+
+	end process;
+			
+	-- output
+	kbcode <= kbcode_reg;
+	KEY_HELD <= key_held_reg;
+	shift_pressed <= left_shift_pressed_reg or right_shift_pressed_reg;
+	break_pressed <= break_reg;
+	
+	key_interrupt <= interrupt_reg;
+	
+	consol_start <= start_reg;
+	consol_select <= select_reg;
+	consol_option <= option_reg;
+	
+	VIRTUAL_STICKS <= not(virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg&virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg);
+	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+	
+	system_reset <= system_reset_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/ps2_keyboard.vhdl
===================================================================
--- unmerged/core/mcc216/ps2_keyboard.vhdl	(nonexistent)
+++ unmerged/core/mcc216/ps2_keyboard.vhdl	(revision 1)
@@ -0,0 +1,266 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+--	KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code
+	
+--	KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed
+--	SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held
+--	CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held
+--	BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers)
+
+ENTITY ps2_keyboard IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	PS2_CLK : IN STD_LOGIC;
+	PS2_DAT : IN STD_LOGIC;
+	
+	KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released
+	KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code
+	KEY_EXTENDED : OUT STD_LOGIC;           -- valid on event, if scan code extended
+	KEY_UP : OUT STD_LOGIC                 -- value on event, if key released
+);
+END ps2_keyboard;
+
+ARCHITECTURE vhdl OF ps2_keyboard IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	-- PS2 keyboard sends on its own clock high->low transition
+	-- start, 8 data bits, parity, stop
+	
+	-- Codes are either 1 bytes or 2 bytes (extended) on press
+	-- XX
+	-- EX YY
+	-- Codes are eighter 2 bytes or 3 bytes (extended) on release
+	-- F0 XX
+	-- EX F0 YY
+	
+	-- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77
+	
+	-- LSB first
+	-- Start bit 0
+	-- Stop bit 1
+	-- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7))
+	-- e.g. 
+	-- '0 1100 0010 0 1'
+	-- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0
+	
+
+	-- Receive raw data from ps2 serial interface
+	signal ps2_shiftreg_next : std_logic_vector(10 downto 0);
+	signal ps2_shiftreg_reg : std_logic_vector(10 downto 0);
+	
+	signal idle_next : std_logic_vector(3 downto 0);
+	signal idle_reg : std_logic_vector(3 downto 0);	
+
+	signal bitcount_next : std_logic_vector(3 downto 0);
+	signal bitcount_reg : std_logic_vector(3 downto 0);	
+	
+	signal enable_ps2 : std_logic;
+	
+	signal last_ps2_clk_next : std_logic;
+	signal last_ps2_clk_reg : std_logic;
+	
+	signal ps2_clk_reg : std_logic;
+	signal ps2_dat_reg : std_logic;
+	
+	signal parity : std_logic;
+	
+	-- Once we have whole parity checked bytes
+	signal byte_next : std_logic_vector(7 downto 0);
+	signal byte_reg : std_logic_vector(7 downto 0);
+	
+	signal byte_received_next : std_logic;
+	signal byte_received_reg : std_logic;	
+	
+	-- Decode if they are press(or repeat)/release or extended
+	signal pending_extended_next : std_logic;
+	signal pending_extended_reg : std_logic;
+	
+	signal pending_keyup_next : std_logic;
+	signal pending_keyup_reg : std_logic;
+	
+	-- To eventually get the code itself
+	signal key_event_next : std_logic;
+	signal key_event_reg : std_logic;
+	
+	signal key_value_next : std_logic_vector(9 downto 0);
+	signal key_value_reg : std_logic_vector(9 downto 0);
+	
+	-- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard
+	signal key_value_last_next : std_logic_vector(9 downto 0);
+	signal key_value_last_reg : std_logic_vector(9 downto 0);
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			ps2_clk_reg <= '0';
+			ps2_dat_reg <= '0';
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= '0';
+			
+			ps2_shiftreg_reg<= (others=>'0');		
+			idle_reg <= (others=>'0');
+			bitcount_reg <= (others=>'0');
+			
+			byte_received_reg <= '0';
+			byte_reg <= (others=>'0');
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= '0';
+			pending_keyup_reg <= '0';			
+
+			-- Output registers
+			key_event_reg <= '0';
+			key_value_reg <= (others=>'0');
+			
+			key_value_last_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			-- Raw interface
+			-- async - do we need some form of synchronizer?
+			ps2_clk_reg <= ps2_clk;
+			ps2_dat_reg <= ps2_dat;
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= last_ps2_clk_next;
+			
+			ps2_shiftreg_reg<= ps2_shiftreg_next;		
+			idle_reg <= idle_next;
+			bitcount_reg <= bitcount_next;
+			
+			byte_received_reg <= byte_received_next;
+			byte_reg <= byte_next;
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= pending_extended_next;
+			pending_keyup_reg <= pending_keyup_next;			
+
+			-- Output registers
+			key_event_reg <= key_event_next;
+			key_value_reg <= key_value_next;
+			
+			key_value_last_reg <= key_value_last_next;
+			
+		end if;
+	end process;
+
+	-- Divide clock by 256 to get approx 4*ps2 clock
+	enable_div : enable_divider
+		generic map (COUNT=>256)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2);
+	
+	-- capture bytes from ps2
+	parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor  ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1));
+	process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity)
+	begin	
+		ps2_shiftreg_next <= ps2_shiftreg_reg;
+		last_ps2_clk_next <= last_ps2_clk_reg;
+		
+		bitcount_next <= bitcount_reg;
+		
+		idle_next <= idle_reg;
+		
+		byte_received_next <= '0';
+		byte_next <= (others=>'0');
+		
+		if (enable_ps2 = '1') then		
+			last_ps2_clk_next <= ps2_clk_reg;
+			
+			-- sample on falling edge
+			if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then
+				ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1);
+				bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1);
+			end if;
+			
+			-- output to next stage when done
+			if (bitcount_reg = X"B") then
+				byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10);
+				byte_next <= ps2_shiftreg_reg(8 downto 1);
+				bitcount_next <= (others=>'0');
+			end if;
+			
+			-- reset if both high for a time period
+			idle_next <= std_logic_vector(unsigned(idle_reg) +1);
+			if (idle_reg = X"F") then
+				ps2_shiftreg_next <= (others=>'0');
+				bitcount_next <= (others=>'0');
+			end if;
+			if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then
+				idle_next <= X"0";
+			end if;		
+		end if;
+	end process;
+	
+	-- process bytes
+	process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg)
+	begin
+		pending_extended_next <=  pending_extended_reg;
+		pending_keyup_next <=  pending_keyup_reg;
+		
+		key_event_next <= '0';
+		key_value_next <= (others =>'0');
+		
+		key_value_last_next <= key_value_last_reg;
+		
+		if (byte_received_reg = '1') then		
+			case byte_reg is 
+				when X"E0" =>
+					pending_extended_next <= '1';					
+				when X"E1" =>
+					pending_extended_next <= '1';
+				when X"F0" =>
+					pending_keyup_next <= '1';
+				when others => 
+					pending_extended_next <= '0';
+					pending_keyup_next <= '0';	
+					
+					if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then
+						key_event_next <= '1';
+						key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+						
+						key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+					end if;
+			end case;
+		end if;
+	end process;
+			
+	-- Output
+	key_event <= key_event_reg;
+	key_value <= key_value_reg(7 downto 0);
+	key_extended <= key_value_reg(8);
+	key_up <= key_value_reg(9);
+		
+END vhdl;
Index: unmerged/core/mcc216/ramint.vhd
===================================================================
--- unmerged/core/mcc216/ramint.vhd	(nonexistent)
+++ unmerged/core/mcc216/ramint.vhd	(revision 1)
@@ -0,0 +1,181 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: ramint.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ramint IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END ramint;
+
+
+ARCHITECTURE SYN OF ramint IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 8192,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 13,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		data_a => data,
+		wren_a => wren,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mcc216/romhi.qip
===================================================================
--- unmerged/core/mcc216/romhi.qip	(nonexistent)
+++ unmerged/core/mcc216/romhi.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "romhi.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romhi.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romhi.cmp"]
Index: unmerged/core/mcc216/romlo.qip
===================================================================
--- unmerged/core/mcc216/romlo.qip	(nonexistent)
+++ unmerged/core/mcc216/romlo.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "romlo.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romlo.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romlo.cmp"]
Index: unmerged/core/mcc216/sdram_ctrl_4_ports.v
===================================================================
--- unmerged/core/mcc216/sdram_ctrl_4_ports.v	(nonexistent)
+++ unmerged/core/mcc216/sdram_ctrl_4_ports.v	(revision 1)
@@ -0,0 +1,561 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    	 
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b1000;
+            r_ram_ph  <= 4'b1000;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+					 //r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+                r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            //r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+            //          | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b0_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: unmerged/core/mcc216/i2s_intf.vhd
===================================================================
--- unmerged/core/mcc216/i2s_intf.vhd	(nonexistent)
+++ unmerged/core/mcc216/i2s_intf.vhd	(revision 1)
@@ -0,0 +1,183 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+-- Modified by Mark Watson for the Atari800
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity i2s_intf is
+generic(
+   inclk_rate : positive := 25000000;
+	sample_rate : positive := 8000;
+	preamble : positive := 1; -- I2S
+	word_length : positive := 16
+	);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	-- Parallel IO
+	PCM_INL		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_INR		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTL	:	in	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTR	:	in	std_logic_vector(word_length - 1 downto 0);
+	
+	-- Codec interface (right justified mode)
+	-- LRCLK is equal to the sample rate and is synchronous to
+	-- MCLK.  It must be related to MCLK by the oversampling ratio
+	-- given in the codec datasheet.
+	I2S_LRCLK	:	out	std_logic;
+	
+	-- Data is shifted out on the falling edge of BCLK, sampled
+	-- on the rising edge.  The bit rate is determined such that
+	-- it is fast enough to fit preamble + word_length bits into
+	-- each LRCLK half cycle.  The last cycle of each word may be 
+	-- stretched to fit to LRCLK.  This is OK at least for the 
+	-- WM8731 codec.
+	-- The first falling edge of each timeslot is always synchronised
+	-- with the LRCLK edge.
+	I2S_BCLK	:	out	std_logic;
+	-- Output bitstream
+	I2S_DOUT	:	out	std_logic;
+	-- Input bitstream
+	I2S_DIN		:	in	std_logic
+	);
+end i2s_intf;
+
+architecture i2s_intf_arch of i2s_intf is
+constant ratio_mclk_fs : positive := (inclk_rate / sample_rate);
+constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
+constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
+constant nbits : positive := preamble + word_length;
+
+subtype lrdivider_t is integer range 0 to lrdivider_top;
+subtype bdivider_t is integer range 0 to bdivider_top;
+subtype bitcount_t is integer range 0 to nbits;
+
+signal lrdivider : lrdivider_t; 
+signal bdivider : bdivider_t;
+signal bitcount : bitcount_t;
+
+signal lrclk_r : std_logic;
+signal bclk_r : std_logic;
+
+-- Shift register is long enough for the number of data bits
+-- plus the preamble, plus an extra bit on the right to register
+-- the incoming data
+signal shiftreg : std_logic_vector(nbits downto 0);
+begin
+	I2S_LRCLK <= lrclk_r;
+	I2S_BCLK <= bclk_r;
+	I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
+
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			PCM_INL <= (others => '0');
+			PCM_INR <= (others => '0');
+						
+			-- Preload down-counters for clock generation
+			lrdivider <= lrdivider_top;
+			bdivider <= bdivider_top;
+			bitcount <= nbits;
+			
+			lrclk_r <= '0';
+			bclk_r <= '0';
+			shiftreg <= (others => '0');
+		elsif rising_edge(CLK) then		
+			-- Generate LRCLK at rate specified by codec configuration
+			if lrdivider = 0 then
+				-- LRCLK divider has reached 0 - start again from the top
+				lrdivider <= lrdivider_top;
+				
+				-- Generate LRCLK edge and sync the BCLK counter
+				lrclk_r <= not lrclk_r;
+				bclk_r <= '0';
+				bitcount <= nbits; -- 1 extra required for setup
+				bdivider <= bdivider_top;
+				
+				-- Load shift register with output data padding preamble
+				-- with 0s.  Load output buses with input word from the 
+				-- previous timeslot.
+				shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
+				if lrclk_r = '0' then
+					-- Previous channel input is LEFT.  This is available in the
+					-- shift register at the end of a cycle, right justified
+					PCM_INL <= shiftreg(word_length - 1 downto 0);
+					-- Next channel to output is RIGHT.  Load this into the
+					-- shift register at the start of a cycle, left justified
+					shiftreg(word_length downto 1) <= PCM_OUTR;
+				else
+					-- Previous channel input is RIGHT
+					PCM_INR <= shiftreg(word_length - 1 downto 0);
+					-- Next channel is LEFT
+					shiftreg(word_length downto 1) <= PCM_OUTL;
+				end if;
+			else
+				-- Decrement the LRCLK counter
+				lrdivider <= lrdivider - 1;
+				
+				-- Generate BCLK at a suitable rate to fit the required number
+				-- of bits into each timeslot.  Data is changed on the falling edge,
+				-- sampled on the rising edge
+				if bdivider = 0 then
+					-- If all bits have been output for this phase then
+					-- stop and wait to sync back up with LRCLK
+					if bitcount > 0 then
+						-- Reset
+						bdivider <= bdivider_top;
+						
+						-- Toggle BCLK
+						bclk_r <= not bclk_r;
+						if bclk_r = '0' then
+							-- Rising edge - shift in current bit and decrement bit counter
+							bitcount <= bitcount - 1;
+							shiftreg(0) <= I2S_DIN;
+						else
+							-- Falling edge - shift out next bit
+							shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
+						end if;
+					end if;
+				else
+					-- Decrement the BCLK counter
+					bdivider <= bdivider - 1;
+				end if;
+			end if;
+			
+		end if;
+	end process;
+end i2s_intf_arch;
+
Index: unmerged/core/mcc216/irq_glue.vhdl
===================================================================
--- unmerged/core/mcc216/irq_glue.vhdl	(nonexistent)
+++ unmerged/core/mcc216/irq_glue.vhdl	(revision 1)
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY irq_glue IS
+PORT 
+( 
+	pokey_irq : in std_logic;
+	pia_irqa : in std_logic;
+	pia_irqb : in std_logic;
+	
+	combined_irq : out std_logic
+);
+end irq_glue;
+
+architecture vhdl of irq_glue is
+begin
+	combined_irq <= pokey_irq and pia_irqa and pia_irqb;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/pll.cmp
===================================================================
--- unmerged/core/mcc216/pll.cmp	(nonexistent)
+++ unmerged/core/mcc216/pll.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: unmerged/core/mcc216/pll.vhd.bak
===================================================================
--- unmerged/core/mcc216/pll.vhd.bak	(nonexistent)
+++ unmerged/core/mcc216/pll.vhd.bak	(revision 1)
@@ -0,0 +1,424 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 2,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: unmerged/core/mcc216/pokey_noise_filter.vhdl
===================================================================
--- unmerged/core/mcc216/pokey_noise_filter.vhdl	(nonexistent)
+++ unmerged/core/mcc216/pokey_noise_filter.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY pokey_noise_filter IS
+PORT 
+( 
+	NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+		
+	PULSE_IN : IN STD_LOGIC;
+
+	NOISE_4 : IN STD_LOGIC;
+	NOISE_5 : IN STD_LOGIC;
+	NOISE_LARGE : IN STD_LOGIC;
+	
+	PULSE_OUT : OUT STD_LOGIC
+);
+END pokey_noise_filter;
+
+ARCHITECTURE vhdl OF pokey_noise_filter IS
+	signal pulse_noise_a : std_logic;
+	signal pulse_noise_b : std_logic;
+BEGIN
+	process(pulse_in, noise_4, noise_5, noise_large, pulse_noise_a, pulse_noise_b, noise_select)
+	begin
+		pulse_noise_a <= noise_large;
+		pulse_noise_b <= noise_5 and pulse_in;
+	
+		if (NOISE_SELECT(1) = '1') then
+			pulse_noise_a <= noise_4;
+		end if;
+	
+		if (NOISE_SELECT(2) = '1') then
+			pulse_noise_b <= pulse_in;
+		end if;
+		
+		PULSE_OUT <= pulse_noise_a and pulse_noise_b;
+
+		if (NOISE_SELECT(0) = '1') then
+			PULSE_OUT <= pulse_noise_b;
+		end if;		
+	end process;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/poly_4.vhdl
===================================================================
--- unmerged/core/mcc216/poly_4.vhdl	(nonexistent)
+++ unmerged/core/mcc216/poly_4.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_4 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;	
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_4;
+
+ARCHITECTURE vhdl OF poly_4 IS
+	signal shift_reg: std_logic_vector(3 downto 0);
+	signal shift_next: std_logic_vector(3 downto 0);
+BEGIN
+	-- register
+	process(clk, reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "1010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: unmerged/core/mcc216/ramint.cmp
===================================================================
--- unmerged/core/mcc216/ramint.cmp	(nonexistent)
+++ unmerged/core/mcc216/ramint.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component ramint
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mcc216/romhi.bsf
===================================================================
--- unmerged/core/mcc216/romhi.bsf	(nonexistent)
+++ unmerged/core/mcc216/romhi.bsf	(revision 1)
@@ -0,0 +1,75 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "romhi" (rect 92 0 129 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "address[12..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
+		(text "address[12..0]" (rect 4 18 72 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 80 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 136 32)(line_width 3))
+	)
+	(drawing
+		(text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical))
+		(text "8192 words" (rect 120 12 214 177)(font "Arial" )(vertical))
+		(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
Index: unmerged/core/mcc216/romlo.bsf
===================================================================
--- unmerged/core/mcc216/romlo.bsf	(nonexistent)
+++ unmerged/core/mcc216/romlo.bsf	(revision 1)
@@ -0,0 +1,75 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "romlo" (rect 92 0 129 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
+		(text "address[10..0]" (rect 4 18 72 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 80 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 136 32)(line_width 3))
+	)
+	(drawing
+		(text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical))
+		(text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical))
+		(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
Index: unmerged/core/mcc216/scandouble_ram_infer.vhdl
===================================================================
--- unmerged/core/mcc216/scandouble_ram_infer.vhdl	(nonexistent)
+++ unmerged/core/mcc216/scandouble_ram_infer.vhdl	(revision 1)
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+END scandouble_ram_infer;
+
+ARCHITECTURE rtl OF scandouble_ram_infer IS
+   TYPE mem IS ARRAY(0 TO 1824) OF std_logic_vector(7 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(address) <= data;
+         END IF;
+         q <= ram_block(address);
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: unmerged/core/mcc216/sdram_ctrl_4_ports.v.bak
===================================================================
--- unmerged/core/mcc216/sdram_ctrl_4_ports.v.bak	(nonexistent)
+++ unmerged/core/mcc216/sdram_ctrl_4_ports.v.bak	(revision 1)
@@ -0,0 +1,558 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b0001;
+            r_ram_ph  <= 4'b0001;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+                r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: unmerged/core/mcc216/sdram_statemachine_mcc.vhdl.bak
===================================================================
Index: unmerged/core/mcc216/sram.vhdl
===================================================================
--- unmerged/core/mcc216/sram.vhdl	(nonexistent)
+++ unmerged/core/mcc216/sram.vhdl	(revision 1)
@@ -0,0 +1,143 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY sram IS
+PORT 
+( 
+	ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+	DIN : IN STD_LOGIC_vector(15 downto 0);
+	WREN : IN STD_LOGIC;
+	
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	request : in std_logic;
+	
+	width_16bit : in std_logic;
+	
+	-- SRAM interface
+	SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
+	SRAM_CE_N: OUT STD_LOGIC;
+	SRAM_OE_N: OUT STD_LOGIC;
+	SRAM_WE_N: OUT STD_LOGIC;
+
+	SRAM_LB_N: OUT STD_LOGIC;
+	SRAM_UB_N: OUT STD_LOGIC;
+	
+	SRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
+	complete : out std_logic
+);
+
+END sram;
+
+-- TODO, implement 32-bit accesses in two cycles
+
+-- first cycle, capture inputs
+-- second cycle, sram access
+ARCHITECTURE slow OF sram IS
+	signal oe_n_next : std_logic;
+	signal oe_n_reg : std_logic;
+	
+	signal we_n_next : std_logic;
+	signal we_n_reg : std_logic;	
+	
+	signal data_next : std_logic_vector(15 downto 0);
+	signal data_reg : std_logic_vector(15 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+	signal low_byte : std_logic_vector(7 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			oe_n_reg <= '1';
+			we_n_reg <= '1';
+			data_reg <= (others=>'0');
+			request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			oe_n_reg <= oe_n_next;
+			we_n_reg <= we_n_next;
+			data_reg <= data_next;
+			request_reg <= request_next;
+		end if;
+	end process;
+
+	-- next state
+	process(din,wren,request,request_reg,width_16bit)
+	begin		
+		data_next <= din;
+		request_next <= '0';
+		
+		oe_n_next <= '0';
+		we_n_next <= '1';
+		
+		if (width_16bit = '0') then
+			data_next <= din(7 downto 0)&din(7 downto 0);
+		end if;
+		
+		if (request = '1') then
+			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
+			oe_n_next <= wren;
+			we_n_next <= not(wren);		
+			request_next <= '1';
+		end if;
+	end process;
+	
+	LOW_BYTE <= SRAM_DQ(7 downto 0) when address(0)='0' else SRAM_DQ(15 downto 8);
+	
+	-- output
+	SRAM_ADDR <= address(18 downto 1);
+	SRAM_CE_N <= '0';
+	SRAM_OE_N <= oe_n_reg;
+	SRAM_WE_N <= we_n_reg;
+	SRAM_LB_N <= not(width_16bit) and address(0);
+	SRAM_UB_N <= not(width_16bit) and NOT(address(0));
+	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+
+	DOUT <= SRAM_DQ(15 downto 8)&LOW_BYTE;
+			
+	complete <= request_reg;		
+		
+	--GPIO <= (others=>'0');
+END slow;
+
+--ARCHITECTURE fast OF sram IS
+--	signal we_n : std_logic;
+--	signal dq : std_logic_vector(7 downto 0);
+--	
+--BEGIN
+--	we_n <= not(clk) nand WREN;
+--	dq <= SRAM_DQ(7 downto 0) when address(0)='0' else
+--		SRAM_DQ(15 downto 8);
+--		
+--	-- output
+--	SRAM_ADDR <= ADDRESS(18 downto 1);
+--	--SRAM_ADDR <= ADDRESS(17 downto 0);
+--	SRAM_CE_N <= '0';
+--	SRAM_OE_N <= WREN;
+--	SRAM_WE_N <= we_n;
+--	
+--	SRAM_LB_N <= ADDRESS(0);
+--	SRAM_UB_N <= NOT(ADDRESS(0));
+--	--SRAM_LB_N <= '0';
+--	--SRAM_UB_N <= '0';
+--		
+--	DOUT <= dq;		
+--	SRAM_DQ <= DIN&DIN when wren='1' else (others=>'Z');
+--	
+--	-- immediate completion
+--	complete <= request;
+--END fast;
\ No newline at end of file
Index: unmerged/core/mcc216/poly_5.vhdl
===================================================================
--- unmerged/core/mcc216/poly_5.vhdl	(nonexistent)
+++ unmerged/core/mcc216/poly_5.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_5 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_5;
+
+ARCHITECTURE vhdl OF poly_5 IS
+	signal shift_reg: std_logic_vector(4 downto 0);
+	signal shift_next: std_logic_vector(4 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: unmerged/core/mcc216/ramint.qip
===================================================================
--- unmerged/core/mcc216/ramint.qip	(nonexistent)
+++ unmerged/core/mcc216/ramint.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ramint.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ramint.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ramint.cmp"]
Index: unmerged/core/mcc216/romhi.cmp
===================================================================
--- unmerged/core/mcc216/romhi.cmp	(nonexistent)
+++ unmerged/core/mcc216/romhi.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component romhi
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mcc216/romlo.cmp
===================================================================
--- unmerged/core/mcc216/romlo.cmp	(nonexistent)
+++ unmerged/core/mcc216/romlo.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component romlo
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mcc216/scandoubler.vhdl
===================================================================
--- unmerged/core/mcc216/scandoubler.vhdl	(nonexistent)
+++ unmerged/core/mcc216/scandoubler.vhdl	(revision 1)
@@ -0,0 +1,301 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY scandoubler IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	VGA : IN STD_LOGIC;
+	COMPOSITE_ON_HSYNC : in std_logic;
+
+	colour_enable : in std_logic;
+	doubled_enable : in std_logic;
+	
+	-- GTIA interface
+	colour_in : in std_logic_vector(7 downto 0);
+	vsync_in : in std_logic;
+	hsync_in : in std_logic;
+	
+	-- TO TV...
+	R : OUT STD_LOGIC_vector(3 downto 0);
+	G : OUT STD_LOGIC_vector(3 downto 0);
+	B : OUT STD_LOGIC_vector(3 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic
+);
+END scandoubler;
+
+ARCHITECTURE vhdl OF scandoubler IS
+
+	COMPONENT gtia_palette IS
+	PORT 
+	( 
+		ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+		
+		R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+	);
+	END component;
+	
+--	component reg_file IS
+--	generic
+--	(
+--		BYTES : natural := 1;
+--		WIDTH : natural := 1
+--	);
+--	PORT 
+--	( 
+--		CLK : IN STD_LOGIC;
+--		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+--		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+--		WR_EN : IN STD_LOGIC;
+--		
+--		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+--	);
+--	END component;
+	
+	component scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	signal colour_next : std_logic_vector(7 downto 0);
+	signal colour_reg : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+
+	signal r_next : std_logic_vector(7 downto 0);
+	signal g_next : std_logic_vector(7 downto 0);
+	signal b_next : std_logic_vector(7 downto 0);	
+	signal r_reg : std_logic_vector(7 downto 0);
+	signal g_reg : std_logic_vector(7 downto 0);
+	signal b_reg : std_logic_vector(7 downto 0);
+	
+	signal linea_address : std_logic_vector(10 downto 0);
+	signal linea_write_enable : std_logic;
+	signal linea_out : std_logic_vector(7 downto 0);
+
+	signal lineb_address : std_logic_vector(10 downto 0);
+	signal lineb_write_enable : std_logic;
+	signal lineb_out : std_logic_vector(7 downto 0);
+	
+	signal input_address_next : std_logic_vector(10 downto 0);
+	signal input_address_reg : std_logic_vector(10 downto 0);
+
+	signal output_address_next : std_logic_vector(10 downto 0);
+	signal output_address_reg : std_logic_vector(10 downto 0);
+	
+	signal buffer_select_next : std_logic;
+	signal buffer_select_reg : std_logic;
+	
+	signal hsync_in_reg : std_logic;
+	
+	signal vga_hsync_next : std_logic;
+	signal vga_hsync_reg : std_logic;
+	signal vga_hsync_start : std_logic;
+	signal vga_hsync_end : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			r_reg <= (others=>'0');
+			g_reg <= (others=>'0');
+			b_reg <= (others=>'0');			
+			colour_reg <= (others=>'0');
+			hsync_reg <= '0';
+			vsync_reg <= '0';
+			
+			input_address_reg <= (others=>'0');
+			output_address_reg <= (others=>'0');
+			
+			buffer_select_reg <= '0';
+			
+			vga_hsync_reg <= '0';
+		elsif (clk'event and clk='1') then										
+			r_reg <= r_next;
+			g_reg <= g_next;
+			b_reg <= b_next;
+			colour_reg <= colour_next;
+			hsync_reg <= hsync_next;
+			vsync_reg <= vsync_next;
+		
+			input_address_reg <= input_address_next;
+			output_address_reg <= output_address_next;
+			
+			buffer_select_reg <= buffer_select_next;
+			
+			hsync_in_reg <= hsync_in;
+			
+			vga_hsync_reg <= vga_hsync_next;
+		end if;
+	end process;
+	
+	-- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!!
+	--	linea : reg_file
+		--generic map (BYTES=>456,WIDTH=>9)
+		--port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out);
+
+	--lineb : reg_file
+	--	generic map (BYTES=>456,WIDTH=>9)
+	--	port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);	
+	
+	linea : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
+
+	lineb : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);	
+	
+	-- capture
+	process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
+	begin
+		input_address_next <= input_address_reg;
+		buffer_select_next <= buffer_select_reg;
+		
+		linea_write_enable <= '0';
+		lineb_write_enable <= '0';
+		
+		if (colour_enable = '1') then
+			input_address_next <= std_logic_vector(unsigned(input_address_reg)+1);
+			linea_write_enable <= buffer_select_reg;
+			lineb_write_enable <= not(buffer_select_reg);
+		end if;		
+		
+		if (hsync_in = '1' and hsync_in_reg = '0') then
+				input_address_next <= (others=>'0');
+				buffer_select_next <= not(buffer_select_reg);
+		end if;		
+	end process;
+	
+	-- output
+	process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable)
+	begin
+		output_address_next <= output_address_reg;
+		vga_hsync_start<='0';
+		vga_hsync_next <= vga_hsync_reg;
+		
+		if (doubled_enable = '1') then
+			output_address_next <= std_logic_vector(unsigned(output_address_reg)+1);
+			
+			if (output_address_reg = "111"&X"1F") then
+				output_address_next <= (others=>'0');
+				vga_hsync_start <= '1';
+				vga_hsync_next <= '1';
+			end if;
+		end if;
+		
+		if (vga_hsync_end = '1') then
+			vga_hsync_next <= '0';
+		end if;
+	end process;
+	
+	linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg;
+	lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg;
+	
+	hsync_delay : delay_line
+		generic map (COUNT=>128)
+		port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end);			
+	
+	-- display
+	process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out)
+	begin	
+		colour_next <= colour_reg;
+		vsync_next <= vsync_reg;
+		hsync_next <= hsync_reg;
+		
+		if (vga = '0') then
+			-- non-vga mode - pass through
+			colour_next <= colour_in;
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(hsync_in or vsync_in);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(hsync_in xor vsync_in);
+			else
+				hsync_next <= not(hsync_in);			
+			end if;
+		else
+			-- vga mode, store all inputs - then play back!			
+			if (buffer_select_reg = '0') then
+				colour_next <= linea_out; -- todo, smoothly increase/decrease...
+			else
+				colour_next <= lineb_out;
+			end if;
+			
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(vga_hsync_reg);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(vga_hsync_reg xor vsync_in);
+			else
+				hsync_next <= not(vga_hsync_reg);			
+			end if;
+		end if;
+	end process;
+
+	-- colour palette
+--	Color             Value         Color             Value
+--Black           0,      0	Medium blue     8,    128
+--Rust            1,     16       Dark blue       9,    144
+--Red-orange      2,     32       Blue-grey      10,    160
+--Dark orange     3,     48       Olive green    11,    176
+--Red             4,     64       Medium green   12,    192
+--Dk lavender     5,     80       Dark green     13,    208
+--Cobalt blue     6,     96       Orange-green   14,    224
+--Ultramarine     7,    112       Orange         15,    240
+
+-- from altirra	
+	palette1 : entity work.gtia_palette(altirra)
+		port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next);
+		
+-- from lao
+--	palette2 : entity work.gtia_palette(laoo)
+--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
+	
+	-- output	
+		-- TODO - for DE2, output full 8 bits
+	R <= R_reg(7 downto 4);
+	G <= G_reg(7 downto 4);
+	B <= B_reg(7 downto 4);
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+
+end vhdl;
+
+
Index: unmerged/core/mcc216/sdram_statemachine_mcc.vhdl
===================================================================
--- unmerged/core/mcc216/sdram_statemachine_mcc.vhdl	(nonexistent)
+++ unmerged/core/mcc216/sdram_statemachine_mcc.vhdl	(revision 1)
@@ -0,0 +1,480 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine_mcc;
+
+ARCHITECTURE vhdl OF sdram_statemachine_mcc IS
+component sdram_ctrl
+port
+(
+--    //-----------------------------
+--    // Clock and reset
+--    //-----------------------------
+--    input         rst,             // Global reset
+--    input         clk,             // Master clock (72 MHz)
+--    
+--    output        ram_rdy_n,       // SDRAM ready
+--    output        ram_ref,         // SDRAM refresh
+--    output  [3:0] ram_cyc,         // SDRAM cycles
+--    output  [3:0] ram_ph,          // SDRAM phases
+--    output  [8:0] ram_ph_ctr,      // Phase counter
+    rst : in std_logic;
+	 clk : in std_logic;
+	 
+	 ram_rdy_n : out std_logic;
+	 ram_ref : out std_logic;
+	 ram_cyc : out std_logic_vector(3 downto 0);
+	 ram_ph : out std_logic_vector(3 downto 0);
+	 ram_ph_ctr : out std_logic_vector(8 downto 0);
+	
+	rden_b0 : in std_logic;
+	wren_b0 : in std_logic;
+	addr_b0 : in std_logic_vector(22 downto 2);
+	valid_b0 : out std_logic;
+	fetch_b0 : out std_logic;
+	rdata_b0 : out std_logic_vector(15 downto 0);
+	wdata_b0 : in std_logic_vector(15 downto 0);
+	bena_b0 : in std_logic_vector(1 downto 0);
+
+	rden_b1 : in std_logic;
+	wren_b1 : in std_logic;
+	addr_b1 : in std_logic_vector(22 downto 2);
+	valid_b1 : out std_logic;
+	fetch_b1 : out std_logic;
+	rdata_b1 : out std_logic_vector(15 downto 0);
+	wdata_b1 : in std_logic_vector(15 downto 0);
+	bena_b1 : in std_logic_vector(1 downto 0);
+
+	rden_b2 : in std_logic;
+	wren_b2 : in std_logic;
+	addr_b2 : in std_logic_vector(22 downto 2);
+	valid_b2 : out std_logic;
+	fetch_b2 : out std_logic;
+	rdata_b2 : out std_logic_vector(15 downto 0);
+	wdata_b2 : in std_logic_vector(15 downto 0);
+	bena_b2 : in std_logic_vector(1 downto 0);
+
+	rden_b3 : in std_logic;
+	wren_b3 : in std_logic;
+	addr_b3 : in std_logic_vector(22 downto 2);
+	valid_b3 : out std_logic;
+	fetch_b3 : out std_logic;
+	rdata_b3 : out std_logic_vector(15 downto 0);
+	wdata_b3 : in std_logic_vector(15 downto 0);
+	bena_b3 : in std_logic_vector(1 downto 0);
+	
+--    //-----------------------------
+--    // Access bank #0
+--    //-----------------------------
+--    input         rden_b0,         // Read enable
+--    input         wren_b0,         // Write enable
+--    input  [22:2] addr_b0,         // Address (up to 8 MB)
+--    output        valid_b0,        // Read data valid
+--    output        fetch_b0,        // Write data fetch
+--    output [15:0] rdata_b0,        // Read data
+--    input  [15:0] wdata_b0,        // Write data
+--    input   [1:0] bena_b0,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #1
+--    //-----------------------------
+--    input         rden_b1,         // Read enable
+--    input         wren_b1,         // Write enable
+--    input  [22:2] addr_b1,         // Address (up to 8 MB)
+--    output        valid_b1,        // Read data valid
+--    output        fetch_b1,        // Write data fetch
+--    output [15:0] rdata_b1,        // Read data
+--    input  [15:0] wdata_b1,        // Write data
+--    input   [1:0] bena_b1,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #2
+--    //-----------------------------
+--    input         rden_b2,         // Read enable
+--    input         wren_b2,         // Write enable
+--    input  [22:2] addr_b2,         // Address (up to 8 MB)
+--    output        valid_b2,        // Read data valid
+--    output        fetch_b2,        // Write data fetch
+--    output [15:0] rdata_b2,        // Read data
+--    input  [15:0] wdata_b2,        // Write data
+--    input   [1:0] bena_b2,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #3
+--    //-----------------------------
+--    input         rden_b3,         // Read enable
+--    input         wren_b3,         // Write enable
+--    input  [22:2] addr_b3,         // Address (up to 8 MB)
+--    output        valid_b3,        // Read data valid
+--    output        fetch_b3,        // Write data fetch
+--    output [15:0] rdata_b3,        // Read data
+--    input  [15:0] wdata_b3,        // Write data
+--    input   [1:0] bena_b3,         // Byte enable
+    
+--    //-----------------------------
+--    // SDRAM memory signals
+--    //-----------------------------
+--    output            sdram_cs_n,  // SDRAM chip select
+--    output reg        sdram_ras_n, // SDRAM row address strobe
+--    output reg        sdram_cas_n, // SDRAM column address strobe
+--    output reg        sdram_we_n,  // SDRAM write enable
+--    //
+--    output reg  [1:0] sdram_ba,    // SDRAM bank address
+--    output reg [12:0] sdram_addr,  // SDRAM address
+--    //
+--    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+--    output reg        sdram_dq_oe, // SDRAM data output enable
+--    output reg [31:0] sdram_dq_o,  // SDRAM data output
+--    input      [31:0] sdram_dq_i   // SDRAM data input
+
+	sdram_cs_n : out std_logic;
+	sdram_ras_n : out std_logic;
+	sdram_cas_n : out std_logic;
+	sdram_we_n : out std_logic;
+	sdram_ba : out std_logic_vector(1 downto 0);
+	sdram_addr : out std_logic_vector(12 downto 0);
+	sdram_dqm_n : out std_logic_vector(3 downto 0);
+	sdram_dq_oe : out std_logic;
+	sdram_dq_o : out std_logic_vector(31 downto 0);
+	sdram_dq_i : in std_logic_vector(31 downto 0)
+);
+end component;
+
+signal SDRAM_CKE_dummy : std_logic;
+
+signal sdram_valid_b0_dummy : std_logic;
+signal sdram_valid_b1_dummy : std_logic;
+signal sdram_valid_b2_dummy : std_logic;
+signal sdram_valid_b3_dummy : std_logic;
+
+signal sdram_fetch_b0_dummy : std_logic;
+signal sdram_fetch_b1_dummy : std_logic;
+signal sdram_fetch_b2_dummy : std_logic;
+signal sdram_fetch_b3_dummy : std_logic;
+
+signal sdram_read_b0_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b1_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b2_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b3_dummy : std_logic_vector(15 downto 0);
+
+signal reset : std_logic;
+
+signal sdram_ctl_rdy_dummy : std_logic;
+signal sdram_ctl_ref_dummy : std_logic;
+signal sdram_ctl_cyc_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_ctr_dummy : std_logic_vector(8 downto 0);
+
+signal SDRAM_VALID : std_logic;
+signal SDRAM_FETCH : std_logic;
+
+signal SDRAM_dq_oe : std_logic;
+signal sdram_dq_o : std_logic_vector(31 downto 0);
+signal sdram_dq_i : std_logic_vector(31 downto 0);
+signal sdram_dqm_N_temp : std_logic_vector(3 downto 0);
+
+signal sdram_ba : std_logic_vector(1 downto 0);
+
+signal sdram_enable_byte : std_logic_vector(1 downto 0);
+
+signal sdram_reply_reg : std_logic;
+signal state_reg : std_logic_vector(2 downto 0);
+signal store_data_in_reg : std_logic_vector(47 downto 0);
+signal data_out_reg : std_logic_vector(31 downto 0);
+signal sdram_reply_next : std_logic;
+signal state_next : std_logic_vector(2 downto 0);
+signal store_data_in_next : std_logic_vector(47 downto 0);
+signal data_out_next : std_logic_vector(31 downto 0);
+
+constant state_idle : std_logic_vector(2 downto 0) := "000";
+constant state_write_wait_1 : std_logic_vector(2 downto 0) := "001";
+constant state_write_wait_2 : std_logic_vector(2 downto 0) := "010";
+constant state_write_wait_3 : std_logic_vector(2 downto 0) := "111";
+constant state_read_wait_1 : std_logic_vector(2 downto 0) := "011";
+constant state_read_wait_2 : std_logic_vector(2 downto 0) := "100";
+constant state_read_wait_3 : std_logic_vector(2 downto 0) := "101";
+constant state_read_wait_4 : std_logic_vector(2 downto 0) := "110";
+
+
+signal internal_data_in : std_logic_vector(15 downto 0);
+signal internal_data_out : std_logic_vector(15 downto 0);
+
+signal write_en_next : std_logic;
+signal write_en_reg : std_logic;
+
+signal read_en_next : std_logic;
+signal read_en_reg : std_logic;
+
+signal SDRAM_ADDR_temp : std_logic_vector(12 downto 0);
+
+begin
+
+
+reset <= not(reset_n);
+
+process(clk_system, reset_n)
+begin
+	if (reset_n = '0') then
+		sdram_reply_reg <= '0';
+		state_reg <= state_idle;
+		store_data_in_reg <= (others=>'0');
+		data_out_reg <= (others=>'0');
+		write_en_reg <= '0';
+		read_en_reg <= '0';
+	elsif (clk_system'event and clk_system = '1') then
+		sdram_reply_reg <= sdram_reply_next;
+		state_reg <= state_next;
+		store_data_in_reg <= store_data_in_next;
+		data_out_reg <= data_out_next;
+		write_en_reg <= write_en_next;
+		read_en_reg <= read_en_next;		
+	end if;
+end process;	
+
+data_out <= data_out_reg;
+reply <= sdram_reply_reg;
+
+process(read_en_reg, write_en_reg, state_reg, request, write_en, store_data_in_reg, internal_data_in, data_in, sdram_reply_reg, byte_access, longword_access, address_in, sdram_valid, sdram_fetch)
+begin
+	sdram_reply_next <= sdram_reply_reg;
+	state_next <= state_reg;
+	store_data_in_next <= store_data_in_reg;
+	data_out_next <= (others=>'0');
+	
+	read_en_next <= read_en_reg;
+	write_en_next <= write_en_reg;
+	
+	internal_data_out <= (others=>'0');
+	sdram_enable_byte <= "11";
+
+	case state_reg is
+	when state_idle => 
+		sdram_reply_next <= '0';
+		if (request = '1') then
+			if (write_en = '1') then
+				-- 4 byte write
+				state_next <= state_write_wait_1;
+				write_en_next <= '1';
+			else
+				-- 8 byte read
+				state_next <= state_read_wait_1;
+				read_en_next <= '1';
+				-- TODO - read from cached?
+			end if;
+		end if;
+	when state_write_wait_1 =>
+		if (sdram_fetch = '1') then
+			state_next <= state_write_wait_2;
+		end if;
+		internal_data_out <= data_in(31 downto 16);
+	when state_write_wait_2 =>
+		state_next <= state_write_wait_3;
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "01";
+			when "01" =>	
+				sdram_enable_byte <= "10";				
+			when "10" =>
+				sdram_enable_byte <= "00";								
+			when "11" =>	
+				sdram_enable_byte <= "00";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(15 downto 0);
+		end if;
+		sdram_reply_next <= '1';	
+	when state_write_wait_3 =>
+		state_next <= state_idle;
+		write_en_next <= '0';		
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "00";
+			when "01" =>	
+				sdram_enable_byte <= "00";				
+			when "10" =>
+				sdram_enable_byte <= "01";								
+			when "11" =>	
+				sdram_enable_byte <= "10";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(31 downto 16);
+		end if;
+		sdram_reply_next <= '0';
+	when state_read_wait_1 =>
+		if (sdram_valid = '1') then
+			state_next <= state_read_wait_2;
+			store_data_in_next(15 downto 0) <= internal_data_in;
+		end if;
+	when state_read_wait_2 =>
+		state_next <= state_read_wait_3;
+		store_data_in_next(31 downto 16) <= internal_data_in;
+	when state_read_wait_3 =>
+		state_next <= state_read_wait_4;
+		store_data_in_next(47 downto 32) <= internal_data_in;
+	when state_read_wait_4 =>
+		read_en_next <= '0';
+		state_next <= state_idle;
+		--store_data_in_next(63 downto 48) <= internal_data_in;
+		sdram_reply_next <= '1';
+		if (byte_access = '1') then
+			case address_in(2 downto 0) is
+			when "000" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(7 downto 0);
+			when "001" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(15 downto 8);
+			when "010" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(23 downto 16);
+			when "011" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(31 downto 24);
+			when "100" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(39 downto 32);
+			when "101" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(47 downto 40);
+			when "110" =>
+				data_out_next(7 downto 0) <= internal_data_in(7 downto 0);
+			when "111" =>
+				data_out_next(7 downto 0) <= internal_data_in(15 downto 8);
+			end case;
+		elsif (longword_access = '1') then
+			case address_in(2 downto 0) is -- aligned only!
+			when "000" =>
+				data_out_next <= store_data_in_reg(31 downto 0);
+			when "100" =>
+				data_out_next <= internal_data_in&store_data_in_reg(47 downto 32);
+			when others =>
+				-- NOP
+			end case;		
+		end if;
+	end case;	
+end process;
+
+
+sdram_mcc : sdram_ctrl 
+	PORT map
+	(
+		rst => reset,
+		clk => clk_SYSTEM,
+		
+		ram_rdy_n => sdram_ctl_rdy_dummy,
+		ram_ref => sdram_ctl_ref_dummy,
+		ram_cyc => sdram_ctl_cyc_dummy,
+		ram_ph => sdram_ctl_ph_dummy,
+		ram_ph_ctr => sdram_ctl_ph_ctr_dummy,
+
+		 --BYTE_ACCESS : IN STD_LOGIC;
+		 --WORD_ACCESS : IN STD_LOGIC;
+		 --LONGWORD_ACCESS : IN STD_LOGIC;		
+		 
+		rden_b0 => READ_EN_reg,
+		wren_b0 => WRITE_EN_reg,
+		addr_b0 => ADDRESS_IN(22 downto 2),
+		valid_b0 => SDRAM_VALID,
+		fetch_b0 => SDRAM_FETCH,
+		rdata_b0 => INTERNAL_DATA_IN(15 downto 0),
+		wdata_b0 => INTERNAL_DATA_OUT(15 downto 0),
+		bena_b0 => sdram_enable_byte,
+
+		rden_b1 => '0',
+		wren_b1 => '0',
+		addr_b1 => (others=>'0'),
+		valid_b1 => sdram_valid_b1_dummy,
+		fetch_b1 => sdram_fetch_b1_dummy,
+		rdata_b1 => sdram_read_b1_dummy,
+		wdata_b1 => (others=>'0'),
+		bena_b1 => "00",
+
+		rden_b2 => '0',
+		wren_b2 => '0',
+		addr_b2 => (others=>'0'),
+		valid_b2 => sdram_valid_b2_dummy,
+		fetch_b2 => sdram_fetch_b2_dummy,
+		rdata_b2 => sdram_read_b2_dummy,
+		wdata_b2 => (others=>'0'),
+		bena_b2 => "00",
+
+		rden_b3 => '0',
+		wren_b3 => '0',
+		addr_b3 => (others=>'0'),
+		valid_b3 => sdram_valid_b3_dummy,
+		fetch_b3 => sdram_fetch_b3_dummy,		
+		rdata_b3 => sdram_read_b3_dummy,
+		wdata_b3 => (others=>'0'),
+		bena_b3 => "00",	
+		
+		sdram_cs_n => SDRAM_CS_N,
+		sdram_ras_n => SDRAM_RAS_N,
+		sdram_cas_n => SDRAM_CAS_N,
+		sdram_we_n => SDRAM_WE_N,
+		sdram_ba => SDRAM_BA,
+		sdram_addr => SDRAM_ADDR_temp,
+		sdram_dqm_n => sdram_dqm_N_temp,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+);
+sdram_dq <= sdram_dq_o(15 downto 0) when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i(15 downto 0) <= sdram_dq;
+sdram_dq_i(31 downto 16) <= (others=>'0');
+SDRAM_LDQM<= sdram_dqm_N_temp(0);
+SDRAM_UDQM<= sdram_dqm_N_temp(1);
+SDRAM_BA0 <= sdram_ba(0);
+SDRAM_BA1 <= sdram_ba(1);
+
+SDRAM_ADDR(12) <= '1';
+SDRAM_ADDR(11 downto 0) <= SDRAM_ADDR_temp(11 downto 0);
+
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mcc216/spi_master.vhd
===================================================================
--- unmerged/core/mcc216/spi_master.vhd	(nonexistent)
+++ unmerged/core/mcc216/spi_master.vhd	(revision 1)
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+--
+--   FileName:         spi_master.vhd
+--   Dependencies:     none
+--   Design Software:  Quartus II Version 9.0 Build 132 SJ Full Version
+--
+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+--   Version History
+--   Version 1.0 7/23/2010 Scott Larson
+--     Initial Public Release
+--   Version 1.1 4/11/2013 Scott Larson
+--     Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
+--    
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_master IS
+  GENERIC(
+    slaves  : INTEGER := 4;  --number of spi slaves
+    d_width : INTEGER := 2); --data bus width
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+    enable  : IN     STD_LOGIC;                             --initiate transaction
+    cpol    : IN     STD_LOGIC;                             --spi clock polarity
+    cpha    : IN     STD_LOGIC;                             --spi clock phase
+    cont    : IN     STD_LOGIC;                             --continuous mode command
+    clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+    addr    : IN     INTEGER;                               --address of slave
+    tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+    miso    : IN     STD_LOGIC;                             --master in, slave out
+    sclk    : BUFFER STD_LOGIC;                             --spi clock
+    ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+    mosi    : OUT    STD_LOGIC;                             --master out, slave in
+    busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+    rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+END spi_master;
+
+ARCHITECTURE logic OF spi_master IS
+  TYPE machine IS(ready, execute);                           --state machine data type
+  SIGNAL state       : machine;                              --current state
+  SIGNAL slave       : INTEGER;                              --slave selected for current transaction
+  SIGNAL clk_ratio   : INTEGER;                              --current clk_div
+  SIGNAL count       : INTEGER;                              --counter to trigger sclk from system clock
+  SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1;     --count spi clock toggles
+  SIGNAL assert_data : STD_LOGIC;                            --'1' is tx sclk toggle, '0' is rx sclk toggle
+  SIGNAL continue    : STD_LOGIC;                            --flag to continue transaction
+  SIGNAL rx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
+  SIGNAL tx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
+  SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2;         --last rx data bit location
+BEGIN
+  PROCESS(clock, reset_n)
+  BEGIN
+
+    IF(reset_n = '0') THEN        --reset system
+      busy <= '1';                --set busy signal
+      ss_n <= (OTHERS => '1');    --deassert all slave select lines
+      mosi <= 'Z';                --set master out to high impedance
+      rx_data <= (OTHERS => '0'); --clear receive data port
+      state <= ready;             --go to ready state when reset is exited
+
+    ELSIF(clock'EVENT AND clock = '1') THEN
+      CASE state IS               --state machine
+
+        WHEN ready =>
+          busy <= '0';             --clock out not busy signal
+          ss_n <= (OTHERS => '1'); --set all slave select outputs high
+          mosi <= 'Z';             --set mosi output high impedance
+          continue <= '0';         --clear continue flag
+
+          --user input to initiate transaction
+          IF(enable = '1') THEN       
+            busy <= '1';             --set busy signal
+            IF(addr < slaves) THEN   --check for valid slave address
+              slave <= addr;         --clock in current slave selection if valid
+            ELSE
+              slave <= 0;            --set to first slave if not valid
+            END IF;
+            IF(clk_div = 0) THEN     --check for valid spi speed
+              clk_ratio <= 1;        --set to maximum speed if zero
+              count <= 1;            --initiate system-to-spi clock counter
+            ELSE
+              clk_ratio <= clk_div;  --set to input selection if valid
+              count <= clk_div;      --initiate system-to-spi clock counter
+            END IF;
+            sclk <= cpol;            --set spi clock polarity
+            assert_data <= NOT cpha; --set spi clock phase
+            tx_buffer <= tx_data;    --clock in data for transmit into buffer
+            clk_toggles <= 0;        --initiate clock toggle counter
+            last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
+            state <= execute;        --proceed to execute state
+          ELSE
+            state <= ready;          --remain in ready state
+          END IF;
+
+        WHEN execute =>
+          busy <= '1';        --set busy signal
+          ss_n(slave) <= '0'; --set proper slave select output
+          
+          --system clock to sclk ratio is met
+          IF(count = clk_ratio) THEN        
+            count <= 1;                     --reset system-to-spi clock counter
+            assert_data <= NOT assert_data; --switch transmit/receive indicator
+            IF(clk_toggles = d_width*2 + 1) THEN
+              clk_toggles <= 0;               --reset spi clock toggles counter
+            ELSE
+              clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
+            END IF;
+            
+            --spi clock toggle needed
+            IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN 
+              sclk <= NOT sclk; --toggle spi clock
+            END IF;
+            
+            --receive spi clock toggle
+            IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN 
+              rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
+            END IF;
+            
+            --transmit spi clock toggle
+            IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN 
+              mosi <= tx_buffer(d_width-1);                     --clock out data bit
+              tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
+            END IF;
+            
+            --last data receive, but continue
+            IF(clk_toggles = last_bit_rx AND cont = '1') THEN 
+              tx_buffer <= tx_data;                       --reload transmit buffer
+              clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
+              continue <= '1';                            --set continue flag
+            END IF;
+            
+            --normal end of transaction, but continue
+            IF(continue = '1') THEN  
+              continue <= '0';      --clear continue flag
+              busy <= '0';          --clock out signal that first receive data is ready
+              rx_data <= rx_buffer; --clock out received data to output port    
+            END IF;
+            
+            --end of transaction
+            IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN   
+              busy <= '0';             --clock out not busy signal
+              ss_n <= (OTHERS => '1'); --set all slave selects high
+              mosi <= 'Z';             --set mosi output high impedance
+              rx_data <= rx_buffer;    --clock out received data to output port
+              state <= ready;          --return to ready state
+            ELSE                       --not end of transaction
+              state <= execute;        --remain in execute state
+            END IF;
+          
+          ELSE        --system clock to sclk ratio not met
+            count <= count + 1; --increment counter
+            state <= execute;   --remain in execute state
+          END IF;
+
+      END CASE;
+    END IF;
+  END PROCESS; 
+END logic;
Index: unmerged/core/mcc216/wide_delay_line.vhdl
===================================================================
--- unmerged/core/mcc216/wide_delay_line.vhdl	(nonexistent)
+++ unmerged/core/mcc216/wide_delay_line.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY wide_delay_line IS
+generic(COUNT : natural := 1; WIDTH : natural :=1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+);
+END wide_delay_line;
+
+ARCHITECTURE vhdl OF wide_delay_line IS
+	type shift_reg_type is array(COUNT-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
+	signal shift_reg : shift_reg_type;
+	signal shift_next : shift_reg_type;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>(others=>'0'));
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>(others=>'0'));
+		end if;		
+	end process;
+	
+	-- output
+	gen_output:
+	for index in 0 to WIDTH-1 generate
+		data_out(index) <= shift_reg(0)(index);
+	end generate;
+		
+END vhdl;
Index: unmerged/core/mcc216/zpu/debug.c
===================================================================
--- unmerged/core/mcc216/zpu/debug.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/debug.c	(revision 1)
@@ -0,0 +1,170 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/core/mcc216/sdram_statemachine.vhdl
===================================================================
--- unmerged/core/mcc216/sdram_statemachine.vhdl	(nonexistent)
+++ unmerged/core/mcc216/sdram_statemachine.vhdl	(revision 1)
@@ -0,0 +1,515 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CKE : out std_logic;
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine;
+
+ARCHITECTURE vhdl OF sdram_statemachine IS
+	function repeat(N: natural; B: std_logic) 
+	return std_logic_vector
+	is
+	variable result: std_logic_vector(1 to N);
+	begin
+	for i in 1 to N loop
+	result(i) := B;
+	end loop;
+	return result;
+	end;
+
+	-- bits are: CS_n, RAS_n, CAS_n,WE_n
+	constant sdram_command_inhibit                  : std_logic_vector(3 downto 0) := "1000";
+	constant sdram_command_no_operation             : std_logic_vector(3 downto 0) := "0111";
+	constant sdram_command_device_burst_stop        : std_logic_vector(3 downto 0) := "0110";
+	constant sdram_command_read                     : std_logic_vector(3 downto 0) := "0101";
+	constant sdram_command_write                    : std_logic_vector(3 downto 0) := "0100";
+	constant sdram_command_bank_activate            : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
+	constant sdram_command_precharge                : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
+	constant sdram_command_mode_register            : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
+	constant sdram_command_refresh                  : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
+	
+	signal command_next : std_logic_vector(3 downto 0);
+	
+--	constant bank_state_idle                 : std_logic_vector(3 downto 0) := "0000";
+--	constant bank_state_row_active           : std_logic_vector(3 downto 0) := "0001";
+--	constant bank_state_read                 : std_logic_vector(3 downto 0) := "0010";
+--	constant bank_state_write                : std_logic_vector(3 downto 0) := "0011";
+--	constant bank_state_read_pre             : std_logic_vector(3 downto 0) := "0100";
+--	constant bank_state_write_pre            : std_logic_vector(3 downto 0) := "0101";
+--	constant bank_state_precharging          : std_logic_vector(3 downto 0) := "0111";
+--	constant bank_state_row_activating       : std_logic_vector(3 downto 0) := "1000";
+--	constant bank_state_write_recovering     : std_logic_vector(3 downto 0) := "1001";
+--	constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
+--	constant bank_state_refresh              : std_logic_vector(3 downto 0) := "1011";
+--	constant bank_state_mode_access          : std_logic_vector(3 downto 0) := "1100"; 
+--	constant bank_state_init                 : std_logic_vector(3 downto 0) := "1101"; 
+-- Banks each have their own state, but since read/write lines are shared they are not truly independent
+-- Also for auto-refresh all banks must be in idle state
+
+	constant sdram_state_powerup        : std_logic_vector(2 downto 0) := "000"; -- requires standard init
+	constant sdram_state_init           : std_logic_vector(2 downto 0) := "001"; -- requires standard init
+	constant sdram_state_idle           : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
+	constant sdram_state_refresh        : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
+	constant sdram_state_read           : std_logic_vector(2 downto 0) := "100"; -- processing a read request
+	constant sdram_state_write          : std_logic_vector(2 downto 0) := "101"; -- processing a write request
+	constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
+	
+	signal sdram_state_next : std_logic_vector(2 downto 0);
+	signal sdram_state_reg : std_logic_vector(2 downto 0);
+	
+	signal delay_next : std_logic_vector(13 downto 0);
+	signal delay_reg : std_logic_vector(13 downto 0);
+	
+	signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
+	signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
+	
+	signal refresh_pending_next : std_logic_vector(11 downto 0);
+	signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
+	
+	signal suggest_refresh : std_logic; -- i.e. do we have any pending?
+	signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
+	signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time	
+	signal refreshing_now : std_logic;
+	
+	signal idle_priority : std_logic_vector(3 downto 0);
+
+	signal data_out_next : std_logic_vector(31 downto 0);
+	signal data_out_reg : std_logic_vector(31 downto 0);
+	
+	signal reply_next : std_logic;
+	signal reply_reg : std_logic;
+	
+	-- track the active bank
+	-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
+	-- CAS,NOP,NOP,DATA
+	-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
+	--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	
+	-- capture inputs
+	signal DATA_IN_snext      : std_logic_vector(31 downto 0);
+	signal DATA_IN_sreg       : std_logic_vector(31 downto 0);
+	signal ADDRESS_IN_snext   : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal ADDRESS_IN_sreg    : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal READ_EN_snext      : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal READ_EN_sreg       : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal WRITE_EN_snext     : std_logic;
+	signal WRITE_EN_sreg      : std_logic;	
+	signal dqm_mask_snext     : std_logic_vector(3 downto 0);
+	signal dqm_mask_sreg      : std_logic_vector(3 downto 0);
+	signal request_snext      : std_logic;
+	signal request_sreg       : std_logic;
+	signal refresh_snext      : std_logic;
+	signal refresh_sreg       : std_logic;
+	
+	-- slow clock output regs
+	signal DATA_OUT_snext     : std_logic_vector(31 downto 0);
+	signal DATA_OUT_sreg      : std_logic_vector(31 downto 0);
+	
+	signal reply_snext : std_logic;
+	signal reply_sreg  : std_logic;
+	
+	-- sdram output registers 
+	signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_next : std_logic_vector(15 downto 0);
+	signal dq_output_next : std_logic;
+	signal dq_in_next  : std_logic_vector(15 downto 0);	
+	signal ba_next : std_logic_vector(1 downto 0);
+	signal cs_n_next : std_logic;
+	signal ras_n_next : std_logic;
+	signal cas_n_next : std_logic;
+	signal we_n_next : std_logic;
+	signal ldqm_next : std_logic;
+	signal udqm_next : std_logic;
+	signal cke_next : std_logic;
+	
+	signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_reg : std_logic_vector(15 downto 0);
+	signal dq_output_reg : std_logic;
+	signal ba_reg : std_logic_vector(1 downto 0);
+	signal cs_n_reg : std_logic;
+	signal ras_n_reg : std_logic;
+	signal cas_n_reg : std_logic;
+	signal we_n_reg : std_logic;
+	signal ldqm_reg : std_logic;
+	signal udqm_reg : std_logic;
+	signal cke_reg : std_logic;
+	
+BEGIN
+	-- register
+	process(CLK_SDRAM,reset_n)
+	begin
+		if (reset_N = '0') then
+			sdram_state_reg <= sdram_state_init;
+			delay_reg <= (others=>'0');
+			refresh_pending_reg <= (others=>'0');
+			cycles_since_refresh_reg <= (others=>'0');
+			data_out_reg <= (others=>'0');
+			reply_reg <= '0';
+			
+			addr_reg <= (others => '0');
+			dq_out_reg <= (others=> '0');
+			dq_output_reg <= '0';
+			ba_reg <= (others=>'0');
+			cs_n_reg <= '0';
+			ras_n_reg <= '0';
+			cas_n_reg <= '0';
+			we_n_reg <= '0';
+			ldqm_reg <= '0';
+			udqm_reg <= '0';
+			cke_reg <= '0';
+			
+			--bank_row_reg <= (others=>(others=>'0'));
+		elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
+			sdram_state_reg <= sdram_state_next;
+			delay_reg <= delay_next;
+			refresh_pending_reg <= refresh_pending_next;
+			cycles_since_refresh_reg <= cycles_since_refresh_next;
+			data_out_reg <= data_out_next;
+			reply_reg <= reply_next;
+			
+			addr_reg <= addr_next;
+			dq_out_reg <= dq_out_next;
+			dq_output_reg <= dq_output_next;
+			ba_reg <= ba_next;
+			cs_n_reg <= cs_n_next;
+			ras_n_reg <= ras_n_next;
+			cas_n_reg <= cas_n_next;
+			we_n_reg <= we_n_next;
+			ldqm_reg <=ldqm_next;
+			udqm_reg <= udqm_next;
+			cke_reg <= cke_next;
+			
+			--bank_row_reg <= bank_row_next;
+		end if;
+	end process;
+
+	-- register request	
+	process(CLK_SYSTEM,reset_n)
+	begin
+		if (reset_N = '0') then
+			data_in_sreg <= (others=>'0');
+			address_in_sreg <= (others=>'0');
+			read_en_sreg <= '0';
+			write_en_sreg <= '0';
+			request_sreg <= '0';
+			dqm_mask_sreg <= (others=>'1');
+			refresh_sreg <= '0';
+			
+			data_out_sreg <= (others=>'0');
+			reply_sreg <= '0';
+		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+			data_in_sreg <= data_in_snext;
+			address_in_sreg <= address_in_snext;
+			read_en_sreg <= read_en_snext;
+			write_en_sreg <= write_en_snext;
+			request_sreg <= request_snext;
+			dqm_mask_sreg <= dqm_mask_snext;
+			refresh_sreg <= refresh_snext;
+			
+			data_out_sreg <= data_out_snext;
+			reply_sreg <= reply_snext;
+		end if;
+	end process;
+
+	-- Inputs - NB, clocked at a smaller multiple
+	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, request, byte_access, word_access, longword_access, refresh)
+	begin
+		data_in_snext <= data_in_sreg;
+		address_in_snext <= address_in_sreg;
+		read_en_snext <= read_en_sreg;
+		write_en_snext <= write_en_sreg;
+		request_snext <= request_sreg;
+		dqm_mask_snext <= dqm_mask_sreg;
+		
+		refresh_snext <= refresh; -- independent of memory requests
+	
+		-- only snap inputs on new request
+		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+		if ((request xor request_sreg) = '1') then
+			data_in_snext <= data_in;
+			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+			read_en_snext <= read_en;
+			write_en_snext <= write_en;
+			request_snext <= request;
+			
+			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+			dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
+			dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
+		end if;
+	end process;
+	
+	-- refresh counters
+	process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
+	begin
+		cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
+		refresh_pending_next <= refresh_pending_reg;
+		suggest_refresh <= '0';
+		force_refresh <= '0';
+		
+		if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
+			suggest_refresh <= '1';
+		end if;
+		
+		if (refresh_pending_reg = X"FFF") then
+			force_refresh <= '1';
+		end if;
+		
+		require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
+		
+		if (refreshing_now = '1') then
+			-- refreshing right now
+			cycles_since_refresh_next <= (others=>'0');
+			
+			-- This is one of our pending refreshes (if we have any)			
+			if (suggest_refresh = '1') then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
+			end if;
+		else
+			if (cycles_since_refresh_reg = "11111111111") then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
+				cycles_since_refresh_next <= (others=>'0');
+			end if;
+		end if;
+
+	end process;
+	
+	--
+	process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
+	begin
+		idle_priority <= (others=>'0');
+		refreshing_now <= '0';
+	
+		sdram_state_next <= sdram_state_reg;
+		
+		command_next <= sdram_command_no_operation;
+		
+		delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
+		
+		data_out_next <= data_out_reg;
+		reply_next <= reply_reg;
+		
+		-- Set some default for when we're sending NOP
+		dq_out_next <= (others=>'0');
+		dq_output_next <= '0';
+		cke_next <= '1';
+		ldqm_next <= '1';
+		udqm_next <= '1';
+		ba_next <= (others=>'0');
+		addr_next <= (others=>'1');
+
+		-- TODO - use bank states!!
+		-- TODO - MUCH MORE SMART STUFF!
+		-- Lets do them once we have Hello World running...
+		case sdram_state_reg is
+		when sdram_state_powerup =>			
+			-- wait 100us (min)
+			if (delay_reg(13) = '1') then
+				sdram_state_next <= sdram_state_init_precharge;
+				delay_next <= (others=>'0');
+			end if;			
+		when sdram_state_init =>			
+			case delay_reg(5 downto 3)&delay_reg(0) is
+			when "0001" =>
+				command_next <= sdram_command_precharge;
+				addr_next(AP_BIT) <= '1'; --all banks
+			when "0010" =>
+				command_next <= sdram_command_refresh;				
+				-- cke still high, so auto refresh
+			when "0100" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+			when "1000" =>
+				command_next <= sdram_command_mode_register;
+				--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
+				addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
+				addr_next(3) <= '0'; -- sequential
+				addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
+				addr_next(8 downto 7) <= "00"; -- standard operation
+				addr_next(9) <= '0'; -- programmed burst access - of single cycle!
+				addr_next(11 downto 10) <= "00"; -- reserved
+			when "1010" =>
+				sdram_state_next <= sdram_state_idle;
+				delay_next <= (others=>'0');
+			when others =>
+				-- nop
+			end case;
+		when sdram_state_idle =>
+			delay_next <= (others=>'0');						
+			
+			idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
+			case idle_priority is -- priority encoder...
+			when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
+				sdram_state_next <= sdram_state_refresh;
+			when "1010"|"1011" =>				
+				sdram_state_next <= sdram_state_write;
+			when "1001" =>
+				sdram_state_next <= sdram_state_read;
+			when others =>
+				-- stay here
+			end case;
+		when sdram_state_read =>
+			-- TODO - if same bank we can save some time... ?
+			-- Only do precharge on switching bank?
+				
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_read;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+			when X"4" =>  -- command actually sent now
+				ldqm_next <= dqm_mask_sreg(0);  -- for first read
+				udqm_next <= dqm_mask_sreg(1);
+			
+			when X"5" =>  -- dqm for 1st read is sent
+				ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
+				udqm_next <= dqm_mask_sreg(3);				
+			when X"7" => 
+				data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				data_out_next(15 downto 8) <= dq_in_next(15 downto 8);				
+			when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
+				data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
+				data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
+				
+				reply_next <= request_sreg;
+				sdram_state_next <= sdram_state_idle;
+				-- after 3 cycles we can do the next ACT (21 ns psc)
+				-- TODO - directly switch to next action so as not to waste a cycle
+			when others =>
+			end case;				
+		when sdram_state_write =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_write; 
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
+				dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
+				ldqm_next <= dqm_mask_sreg(0);
+				udqm_next <= dqm_mask_sreg(1);
+			when X"4" =>
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
+				ldqm_next <= dqm_mask_sreg(2);
+				udqm_next <= dqm_mask_sreg(3);
+
+				reply_next <= request_sreg;				
+			when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
+				sdram_state_next <= sdram_state_idle;		
+				-- TODO - directly switch to next action to match read
+			when others =>
+			end case;				
+		when sdram_state_refresh =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+				refreshing_now <= '1';
+			when X"8" =>
+				sdram_state_next <= sdram_state_idle;
+			when others =>
+			end case;
+		when others =>
+			sdram_state_next <= sdram_state_init;			
+		end case;
+	end process;
+	
+	-- command_next directly translates to lines to send
+	-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
+	process(command_next)
+	begin
+		cs_n_next <= command_next(3);
+		ras_n_next <= command_next(2);
+		cas_n_next <= command_next(1);
+		we_n_next <= command_next(0);
+	end process;
+	
+	-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
+	SDRAM_ADDR <= addr_reg;
+	SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
+	SDRAM_BA0 <= ba_reg(0);
+	SDRAM_BA1 <= ba_reg(1);
+	SDRAM_CS_N <= cs_n_reg;
+	SDRAM_RAS_N <= ras_n_reg;
+	SDRAM_CAS_N <= cas_n_reg;
+	SDRAM_WE_N <= we_n_reg;
+	SDRAM_ldqm <= ldqm_reg;
+	SDRAM_udqm <= udqm_reg;
+	SDRAM_CKE <= cke_reg;
+	
+	-- inputs from SDRAM
+	dq_in_next <= SDRAM_DQ;
+	
+	-- back to slower clock
+	reply_snext <= reply_reg;
+	data_out_snext <= data_out_reg;
+	
+	-- outputs to rest of system
+	REPLY <= reply_sreg;
+	DATA_OUT <= DATA_OUT_sreg;
+		
+END vhdl;
Index: unmerged/core/mcc216/shared_enable.vhdl
===================================================================
--- unmerged/core/mcc216/shared_enable.vhdl	(nonexistent)
+++ unmerged/core/mcc216/shared_enable.vhdl	(revision 1)
@@ -0,0 +1,163 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY shared_enable IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;	
+	RESET_N : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	MEMORY_READY_ANTIC : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	PAUSE_6502 : in std_logic;
+	THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
+
+	POKEY_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same
+	ANTIC_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same - 1 cycle early
+	oldcpu_enable : OUT STD_LOGIC;     -- always about 1.79MHz to keep sound the same - expanded to next ready
+	CPU_ENABLE_OUT : OUT STD_LOGIC;    -- for compatibility run at 1.79MHz, for speed run as fast as we can
+	
+	SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC; -- double antic's rate - due to high-res mode
+	SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC -- four times antic's rate - due to high-res mode
+	
+	-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by 31 cycles vs CPU_ENABLE (when in 1.79MHz mode)
+	-- XXX watch out on clock speed change from 56MHz!
+);
+END shared_enable;
+
+ARCHITECTURE vhdl OF shared_enable IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;		
+	
+	signal enable_179 : std_logic;
+	signal enable_179_early : std_logic;
+	signal enable_179_late : std_logic;
+	signal cpu_enable : std_logic;
+	
+	signal cpu_extra_enable_next : std_logic;
+	signal cpu_extra_enable_reg : std_logic;
+	
+	signal turbo_next : std_logic;
+	signal turbo_reg : std_logic;	
+
+	signal throttle_count_next : std_logic_vector(5 downto 0);
+	signal throttle_count_reg : std_logic_vector(5 downto 0);	
+	
+	-- TODO - clean up
+	signal oldcpu_extra_enable_next : std_logic;
+	signal oldcpu_extra_enable_reg : std_logic;
+	signal enable_179_expanded : std_logic;
+	
+	signal memory_ready : std_logic;
+begin
+	-- instantiate some clock calcs
+	SCANDOUBLER_ENABLE_HIGH <= '1';
+		
+	sl_enable_colour_clock_div : enable_divider
+		generic map (COUNT=>2)
+		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
+
+	enable_179_clock_div : enable_divider
+		--generic map (COUNT=>16)
+		generic map (COUNT=>32)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
+		
+	process(THROTTLE_COUNT_6502, throttle_count_reg, enable_179)
+	begin
+		turbo_next <= '0';
+		throttle_count_next <= std_logic_vector(unsigned(throttle_count_reg) + 1);
+
+		--011111/31/1f = run every 32 cycles
+		
+		if (throttle_count_reg = THROTTLE_COUNT_6502) then
+			throttle_count_next <= (others=>'0');
+			turbo_next <= '1';
+		end if;
+		
+		if (enable_179 = '1') then -- synchronize
+			throttle_count_next <= "000001";
+		end if;
+		--0000000000111111111122222222223333
+		--0123456789012345678901234567890123
+		--X-------------------------------X
+		--
+		--000000000011111111112222222222333
+		--R12345678901234567890123456789012
+		---------------------------------NT
+		
+		--000000000011111100000000001111111
+		--R12345678901234501234567890123456
+		-----------------NT--------------NT
+	end process;
+
+	delay_line_phase : delay_line
+		--generic map (COUNT=>15)
+		generic map (COUNT=>31)
+		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+
+	delay_line_phase2 : delay_line
+		--generic map (COUNT=>15)
+		generic map (COUNT=>16)
+		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+	
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			cpu_extra_enable_reg <= '0';
+			oldcpu_extra_enable_reg <= '0';
+			turbo_reg <= '0';
+			throttle_count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then										
+			cpu_extra_enable_reg <= cpu_extra_enable_next;
+			oldcpu_extra_enable_reg <= oldcpu_extra_enable_next;
+			turbo_reg <= turbo_next;
+			throttle_count_reg <= throttle_count_next;
+		end if;
+	end process;
+	
+	-- next state
+	memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
+	cpu_enable <= (turbo_reg or cpu_extra_enable_reg or enable_179) and not(pause_6502);
+	cpu_extra_enable_next <= cpu_enable and not(memory_ready);
+	
+	oldcpu_extra_enable_next <= enable_179_expanded and not(memory_ready);
+	enable_179_expanded <= oldcpu_extra_enable_reg or enable_179;
+	
+	-- output
+	POKEY_ENABLE_179 <= enable_179_late; -- aka enable_179_late!  TODO!!!
+	oldcpu_enable <= enable_179_expanded;
+	ANTIC_ENABLE_179 <= enable_179_early;
+	
+	CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
+
+end vhdl;
Index: unmerged/core/mcc216/zpu/led.c
===================================================================
--- unmerged/core/mcc216/zpu/led.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/core/mcc216/zpu/mmc.h
===================================================================
--- unmerged/core/mcc216/zpu/mmc.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/mmc.h	(revision 1)
@@ -0,0 +1,145 @@
+/*! \file mmc.h \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.h'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+///	\ingroup driver_hw
+/// \defgroup mmc MultiMedia and SD Flash Card Interface (mmc.c)
+/// \code #include "mmc.h" \endcode
+/// \par Description
+///		This library offers some simple functions which can be used
+///		to read and write data on a MultiMedia or SecureDigital (SD) Flash
+///		Card.  Although MM and SD Cards are designed to operate with their own
+///		special bus wiring and protocols, both types of cards also provide a
+///		simple SPI-like interface mode which is exceptionally useful when 
+///		attempting to use the cards in embedded systems.
+///
+/// \par Wiring
+///		To work with this library, the card must be wired to the SPI port of
+///		the Atmel microcontroller as described below.  Typical cards can
+///		operate at up to 25MHz maximum SPI clock rate (thus faster than most
+///		AVR's maximum SPI clock rate).
+/// <pre>
+///	      _________________
+///	     /  1 2 3 4 5 6 78 |	<- view of MMC/SD card looking at contacts
+///	    / 9                |	Pins 8 and 9 are present only on SD cards
+///	    |    MMC/SD Card   |
+///	    |                  |
+///	    --------------------
+///	    1 - CS   (chip select)          - wire to any available I/O pin(*)
+///	    2 - DIN  (data in, card<-host)  - wire to SPI MOSI pin
+///	    3 - VSS  (ground)               - wire to ground
+///	    4 - VDD  (power, 3.3V only?)    - wire to power (MIGHT BE 3.3V ONLY!)
+///	    5 - SCLK (data clock)           - wire to SPI SCK pin
+///	    6 - VSS  (ground)               - wire to ground
+///	    7 - DOUT (data out, card->host) - wire to SPI MISO pin
+///
+///	    (*) you must define this chip select I/O pin in mmcconf.h
+/// </pre>
+/// \note This code is currently below version 1.0, and therefore is considered
+/// to be lacking in some functionality or documentation, or may not be fully
+/// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "types.h"
+
+// constants/macros/typdefs
+// MMC commands (taken from sandisk MMC reference)
+#define MMC_GO_IDLE_STATE			0		///< initialize card to SPI-type access
+#define MMC_SEND_OP_COND			1		///< set card operational mode
+#define MMC_SEND_CSD				9		///< get card's CSD
+#define MMC_SEND_CID				10		///< get card's CID
+#define MMC_SEND_STATUS				13
+#define MMC_SET_BLOCKLEN			16		///< Set number of bytes to transfer per block
+#define MMC_READ_SINGLE_BLOCK		17		///< read a block
+#define MMC_WRITE_BLOCK				24		///< write a block
+#define MMC_PROGRAM_CSD				27
+#define MMC_SET_WRITE_PROT			28
+#define MMC_CLR_WRITE_PROT			29
+#define MMC_SEND_WRITE_PROT			30
+#define MMC_TAG_SECTOR_START		32
+#define MMC_TAG_SECTOR_END			33
+#define MMC_UNTAG_SECTOR			34
+#define MMC_TAG_ERASE_GROUP_START 	35		///< Sets beginning of erase group (mass erase)
+#define MMC_TAG_ERARE_GROUP_END		36		///< Sets end of erase group (mass erase)
+#define MMC_UNTAG_ERASE_GROUP		37		///< Untag (unset) erase group (mass erase)
+#define MMC_ERASE					38		///< Perform block/mass erase
+#define MMC_CRC_ON_OFF				59		///< Turns CRC check on/off
+// R1 Response bit-defines
+#define MMC_R1_BUSY					0x80	///< R1 response: bit indicates card is busy
+#define MMC_R1_PARAMETER			0x40
+#define MMC_R1_ADDRESS				0x20
+#define MMC_R1_ERASE_SEQ			0x10
+#define MMC_R1_COM_CRC				0x08
+#define MMC_R1_ILLEGAL_COM			0x04
+#define MMC_R1_ERASE_RESET			0x02
+#define MMC_R1_IDLE_STATE			0x01
+// Data Start tokens
+#define MMC_STARTBLOCK_READ			0xFE	///< when received from card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_WRITE		0xFE	///< when sent to card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_MWRITE		0xFC
+// Data Stop tokens
+#define MMC_STOPTRAN_WRITE			0xFD
+// Data Error Token values
+#define MMC_DE_MASK					0x1F
+#define MMC_DE_ERROR				0x01
+#define MMC_DE_CC_ERROR				0x02
+#define MMC_DE_ECC_FAIL				0x04
+#define MMC_DE_OUT_OF_RANGE			0x04
+#define MMC_DE_CARD_LOCKED			0x04
+// Data Response Token values
+#define MMC_DR_MASK					0x1F
+#define MMC_DR_ACCEPT				0x05
+#define MMC_DR_REJECT_CRC			0x0B
+#define MMC_DR_REJECT_WRITE_ERROR	0x0D
+
+// functions
+
+//! Initialize AVR<->MMC hardware interface.
+/// Prepares hardware for MMC access.
+void mmcInit(void);
+
+//! Initialize the card and prepare it for use.
+/// Returns zero if successful.
+u08 mmcReset(void);
+
+//! Send card an MMC command.
+/// Returns R1 result code.
+u08 mmcSendCommand(u08 cmd, u32 arg);
+
+//! Read 512-byte sector from card to buffer
+/// Returns zero if successful.
+u08 mmcRead(u32 sector);
+
+//! Write 512-byte sector from buffer to card
+/// Returns zero if successful.
+u08 mmcWrite(u32 sector);
+
+//! Internal command function.
+/// Issues a generic MMC command as specified by cmd and arg.
+u08 mmcCommand(u08 cmd, u32 arg);
+
+#endif
Index: unmerged/core/mcc216/synchronizer.vhdl
===================================================================
--- unmerged/core/mcc216/synchronizer.vhdl	(nonexistent)
+++ unmerged/core/mcc216/synchronizer.vhdl	(revision 1)
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END synchronizer;
+
+ARCHITECTURE vhdl OF synchronizer IS
+	signal ff_next : std_logic_vector(2 downto 0);
+	signal ff_reg : std_logic_vector(2 downto 0);
+begin
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then						
+			ff_reg <= ff_next;	
+		end if;
+	end process;
+	
+	ff_next <= RAW&ff_reg(2 downto 1);
+	
+	SYNC <= ff_reg(0);
+
+end vhdl;
+
+
Index: unmerged/core/mcc216/zpu/Makefile
===================================================================
--- unmerged/core/mcc216/zpu/Makefile	(nonexistent)
+++ unmerged/core/mcc216/zpu/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c mmc.c    spi.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/core/mcc216/zpu/diskio.h
===================================================================
--- unmerged/core/mcc216/zpu/diskio.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/core/mcc216/sdram_statemachine.vhdl.bak
===================================================================
--- unmerged/core/mcc216/sdram_statemachine.vhdl.bak	(nonexistent)
+++ unmerged/core/mcc216/sdram_statemachine.vhdl.bak	(revision 1)
@@ -0,0 +1,515 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CKE : out std_logic;
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine;
+
+ARCHITECTURE vhdl OF sdram_statemachine IS
+	function repeat(N: natural; B: std_logic) 
+	return std_logic_vector
+	is
+	variable result: std_logic_vector(1 to N);
+	begin
+	for i in 1 to N loop
+	result(i) := B;
+	end loop;
+	return result;
+	end;
+
+	-- bits are: CS_n, RAS_n, CAS_n,WE_n
+	constant sdram_command_inhibit                  : std_logic_vector(3 downto 0) := "1000";
+	constant sdram_command_no_operation             : std_logic_vector(3 downto 0) := "0111";
+	constant sdram_command_device_burst_stop        : std_logic_vector(3 downto 0) := "0110";
+	constant sdram_command_read                     : std_logic_vector(3 downto 0) := "0101";
+	constant sdram_command_write                    : std_logic_vector(3 downto 0) := "0100";
+	constant sdram_command_bank_activate            : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
+	constant sdram_command_precharge                : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
+	constant sdram_command_mode_register            : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
+	constant sdram_command_refresh                  : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
+	
+	signal command_next : std_logic_vector(3 downto 0);
+	
+--	constant bank_state_idle                 : std_logic_vector(3 downto 0) := "0000";
+--	constant bank_state_row_active           : std_logic_vector(3 downto 0) := "0001";
+--	constant bank_state_read                 : std_logic_vector(3 downto 0) := "0010";
+--	constant bank_state_write                : std_logic_vector(3 downto 0) := "0011";
+--	constant bank_state_read_pre             : std_logic_vector(3 downto 0) := "0100";
+--	constant bank_state_write_pre            : std_logic_vector(3 downto 0) := "0101";
+--	constant bank_state_precharging          : std_logic_vector(3 downto 0) := "0111";
+--	constant bank_state_row_activating       : std_logic_vector(3 downto 0) := "1000";
+--	constant bank_state_write_recovering     : std_logic_vector(3 downto 0) := "1001";
+--	constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
+--	constant bank_state_refresh              : std_logic_vector(3 downto 0) := "1011";
+--	constant bank_state_mode_access          : std_logic_vector(3 downto 0) := "1100"; 
+--	constant bank_state_init                 : std_logic_vector(3 downto 0) := "1101"; 
+-- Banks each have their own state, but since read/write lines are shared they are not truly independent
+-- Also for auto-refresh all banks must be in idle state
+
+	constant sdram_state_powerup        : std_logic_vector(2 downto 0) := "000"; -- requires standard init
+	constant sdram_state_init           : std_logic_vector(2 downto 0) := "001"; -- requires standard init
+	constant sdram_state_idle           : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
+	constant sdram_state_refresh        : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
+	constant sdram_state_read           : std_logic_vector(2 downto 0) := "100"; -- processing a read request
+	constant sdram_state_write          : std_logic_vector(2 downto 0) := "101"; -- processing a write request
+	constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
+	
+	signal sdram_state_next : std_logic_vector(2 downto 0);
+	signal sdram_state_reg : std_logic_vector(2 downto 0);
+	
+	signal delay_next : std_logic_vector(13 downto 0);
+	signal delay_reg : std_logic_vector(13 downto 0);
+	
+	signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
+	signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
+	
+	signal refresh_pending_next : std_logic_vector(11 downto 0);
+	signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
+	
+	signal suggest_refresh : std_logic; -- i.e. do we have any pending?
+	signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
+	signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time	
+	signal refreshing_now : std_logic;
+	
+	signal idle_priority : std_logic_vector(3 downto 0);
+
+	signal data_out_next : std_logic_vector(31 downto 0);
+	signal data_out_reg : std_logic_vector(31 downto 0);
+	
+	signal reply_next : std_logic;
+	signal reply_reg : std_logic;
+	
+	-- track the active bank
+	-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
+	-- CAS,NOP,NOP,DATA
+	-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
+	--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	
+	-- capture inputs
+	signal DATA_IN_snext      : std_logic_vector(31 downto 0);
+	signal DATA_IN_sreg       : std_logic_vector(31 downto 0);
+	signal ADDRESS_IN_snext   : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal ADDRESS_IN_sreg    : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal READ_EN_snext      : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal READ_EN_sreg       : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal WRITE_EN_snext     : std_logic;
+	signal WRITE_EN_sreg      : std_logic;	
+	signal dqm_mask_snext     : std_logic_vector(3 downto 0);
+	signal dqm_mask_sreg      : std_logic_vector(3 downto 0);
+	signal request_snext      : std_logic;
+	signal request_sreg       : std_logic;
+	signal refresh_snext      : std_logic;
+	signal refresh_sreg       : std_logic;
+	
+	-- slow clock output regs
+	signal DATA_OUT_snext     : std_logic_vector(31 downto 0);
+	signal DATA_OUT_sreg      : std_logic_vector(31 downto 0);
+	
+	signal reply_snext : std_logic;
+	signal reply_sreg  : std_logic;
+	
+	-- sdram output registers 
+	signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_next : std_logic_vector(15 downto 0);
+	signal dq_output_next : std_logic;
+	signal dq_in_next  : std_logic_vector(15 downto 0);	
+	signal ba_next : std_logic_vector(1 downto 0);
+	signal cs_n_next : std_logic;
+	signal ras_n_next : std_logic;
+	signal cas_n_next : std_logic;
+	signal we_n_next : std_logic;
+	signal ldqm_next : std_logic;
+	signal udqm_next : std_logic;
+	signal cke_next : std_logic;
+	
+	signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_reg : std_logic_vector(15 downto 0);
+	signal dq_output_reg : std_logic;
+	signal ba_reg : std_logic_vector(1 downto 0);
+	signal cs_n_reg : std_logic;
+	signal ras_n_reg : std_logic;
+	signal cas_n_reg : std_logic;
+	signal we_n_reg : std_logic;
+	signal ldqm_reg : std_logic;
+	signal udqm_reg : std_logic;
+	signal cke_reg : std_logic;
+	
+BEGIN
+	-- register
+	process(CLK_SDRAM,reset_n)
+	begin
+		if (reset_N = '0') then
+			sdram_state_reg <= sdram_state_init;
+			delay_reg <= (others=>'0');
+			refresh_pending_reg <= (others=>'0');
+			cycles_since_refresh_reg <= (others=>'0');
+			data_out_reg <= (others=>'0');
+			reply_reg <= '0';
+			
+			addr_reg <= (others => '0');
+			dq_out_reg <= (others=> '0');
+			dq_output_reg <= '0';
+			ba_reg <= (others=>'0');
+			cs_n_reg <= '0';
+			ras_n_reg <= '0';
+			cas_n_reg <= '0';
+			we_n_reg <= '0';
+			ldqm_reg <= '1';
+			udqm_reg <= '1';
+			cke_reg <= '0';
+			
+			--bank_row_reg <= (others=>(others=>'0'));
+		elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
+			sdram_state_reg <= sdram_state_next;
+			delay_reg <= delay_next;
+			refresh_pending_reg <= refresh_pending_next;
+			cycles_since_refresh_reg <= cycles_since_refresh_next;
+			data_out_reg <= data_out_next;
+			reply_reg <= reply_next;
+			
+			addr_reg <= addr_next;
+			dq_out_reg <= dq_out_next;
+			dq_output_reg <= dq_output_next;
+			ba_reg <= ba_next;
+			cs_n_reg <= cs_n_next;
+			ras_n_reg <= ras_n_next;
+			cas_n_reg <= cas_n_next;
+			we_n_reg <= we_n_next;
+			ldqm_reg <=ldqm_next;
+			udqm_reg <= udqm_next;
+			cke_reg <= cke_next;
+			
+			--bank_row_reg <= bank_row_next;
+		end if;
+	end process;
+
+	-- register request	
+	process(CLK_SYSTEM,reset_n)
+	begin
+		if (reset_N = '0') then
+			data_in_sreg <= (others=>'0');
+			address_in_sreg <= (others=>'0');
+			read_en_sreg <= '0';
+			write_en_sreg <= '0';
+			request_sreg <= '0';
+			dqm_mask_sreg <= (others=>'1');
+			refresh_sreg <= '0';
+			
+			data_out_sreg <= (others=>'0');
+			reply_sreg <= '0';
+		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+			data_in_sreg <= data_in_snext;
+			address_in_sreg <= address_in_snext;
+			read_en_sreg <= read_en_snext;
+			write_en_sreg <= write_en_snext;
+			request_sreg <= request_snext;
+			dqm_mask_sreg <= dqm_mask_snext;
+			refresh_sreg <= refresh_snext;
+			
+			data_out_sreg <= data_out_snext;
+			reply_sreg <= reply_snext;
+		end if;
+	end process;
+
+	-- Inputs - NB, clocked at a smaller multiple
+	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, request, byte_access, word_access, longword_access, refresh)
+	begin
+		data_in_snext <= data_in_sreg;
+		address_in_snext <= address_in_sreg;
+		read_en_snext <= read_en_sreg;
+		write_en_snext <= write_en_sreg;
+		request_snext <= request_sreg;
+		dqm_mask_snext <= dqm_mask_sreg;
+		
+		refresh_snext <= refresh; -- independent of memory requests
+	
+		-- only snap inputs on new request
+		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+		if ((request xor request_sreg) = '1') then
+			data_in_snext <= data_in;
+			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+			read_en_snext <= read_en;
+			write_en_snext <= write_en;
+			request_snext <= request;
+			
+			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+			dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
+			dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
+		end if;
+	end process;
+	
+	-- refresh counters
+	process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
+	begin
+		cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
+		refresh_pending_next <= refresh_pending_reg;
+		suggest_refresh <= '0';
+		force_refresh <= '0';
+		
+		if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
+			suggest_refresh <= '1';
+		end if;
+		
+		if (refresh_pending_reg = X"FFF") then
+			force_refresh <= '1';
+		end if;
+		
+		require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
+		
+		if (refreshing_now = '1') then
+			-- refreshing right now
+			cycles_since_refresh_next <= (others=>'0');
+			
+			-- This is one of our pending refreshes (if we have any)			
+			if (suggest_refresh = '1') then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
+			end if;
+		else
+			if (cycles_since_refresh_reg = "11111111111") then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
+				cycles_since_refresh_next <= (others=>'0');
+			end if;
+		end if;
+
+	end process;
+	
+	--
+	process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
+	begin
+		idle_priority <= (others=>'0');
+		refreshing_now <= '0';
+	
+		sdram_state_next <= sdram_state_reg;
+		
+		command_next <= sdram_command_no_operation;
+		
+		delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
+		
+		data_out_next <= data_out_reg;
+		reply_next <= reply_reg;
+		
+		-- Set some default for when we're sending NOP
+		dq_out_next <= (others=>'0');
+		dq_output_next <= '0';
+		cke_next <= '1';
+		ldqm_next <= '1';
+		udqm_next <= '1';
+		ba_next <= (others=>'0');
+		addr_next <= (others=>'1');
+
+		-- TODO - use bank states!!
+		-- TODO - MUCH MORE SMART STUFF!
+		-- Lets do them once we have Hello World running...
+		case sdram_state_reg is
+		when sdram_state_powerup =>			
+			-- wait 100us (min)
+			if (delay_reg(13) = '1') then
+				sdram_state_next <= sdram_state_init_precharge;
+				delay_next <= (others=>'0');
+			end if;			
+		when sdram_state_init =>			
+			case delay_reg(5 downto 3)&delay_reg(0) is
+			when "0001" =>
+				command_next <= sdram_command_precharge;
+				addr_next(AP_BIT) <= '1'; --all banks
+			when "0010" =>
+				command_next <= sdram_command_refresh;				
+				-- cke still high, so auto refresh
+			when "0100" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+			when "1000" =>
+				command_next <= sdram_command_mode_register;
+				--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
+				addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
+				addr_next(3) <= '0'; -- sequential
+				addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
+				addr_next(8 downto 7) <= "00"; -- standard operation
+				addr_next(9) <= '0'; -- programmed burst access - of single cycle!
+				addr_next(11 downto 10) <= "00"; -- reserved
+			when "1010" =>
+				sdram_state_next <= sdram_state_idle;
+				delay_next <= (others=>'0');
+			when others =>
+				-- nop
+			end case;
+		when sdram_state_idle =>
+			delay_next <= (others=>'0');						
+			
+			idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
+			case idle_priority is -- priority encoder...
+			when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
+				sdram_state_next <= sdram_state_refresh;
+			when "1010"|"1011" =>				
+				sdram_state_next <= sdram_state_write;
+			when "1001" =>
+				sdram_state_next <= sdram_state_read;
+			when others =>
+				-- stay here
+			end case;
+		when sdram_state_read =>
+			-- TODO - if same bank we can save some time... ?
+			-- Only do precharge on switching bank?
+				
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_read;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+			when X"4" =>  -- command actually sent now
+				ldqm_next <= dqm_mask_sreg(0);  -- for first read
+				udqm_next <= dqm_mask_sreg(1);
+			
+			when X"5" =>  -- dqm for 1st read is sent
+				ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
+				udqm_next <= dqm_mask_sreg(3);				
+			when X"7" => 
+				data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				data_out_next(15 downto 8) <= dq_in_next(15 downto 8);				
+			when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
+				data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
+				data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
+				
+				reply_next <= request_sreg;
+				sdram_state_next <= sdram_state_idle;
+				-- after 3 cycles we can do the next ACT (21 ns psc)
+				-- TODO - directly switch to next action so as not to waste a cycle
+			when others =>
+			end case;				
+		when sdram_state_write =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_write; 
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
+				dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
+				ldqm_next <= dqm_mask_sreg(0);
+				udqm_next <= dqm_mask_sreg(1);
+			when X"4" =>
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
+				ldqm_next <= dqm_mask_sreg(2);
+				udqm_next <= dqm_mask_sreg(3);
+
+				reply_next <= request_sreg;				
+			when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
+				sdram_state_next <= sdram_state_idle;		
+				-- TODO - directly switch to next action to match read
+			when others =>
+			end case;				
+		when sdram_state_refresh =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+				refreshing_now <= '1';
+			when X"8" =>
+				sdram_state_next <= sdram_state_idle;
+			when others =>
+			end case;
+		when others =>
+			sdram_state_next <= sdram_state_init;			
+		end case;
+	end process;
+	
+	-- command_next directly translates to lines to send
+	-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
+	process(command_next)
+	begin
+		cs_n_next <= command_next(3);
+		ras_n_next <= command_next(2);
+		cas_n_next <= command_next(1);
+		we_n_next <= command_next(0);
+	end process;
+	
+	-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
+	SDRAM_ADDR <= addr_reg;
+	SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
+	SDRAM_BA0 <= ba_reg(0);
+	SDRAM_BA1 <= ba_reg(1);
+	SDRAM_CS_N <= cs_n_reg;
+	SDRAM_RAS_N <= ras_n_reg;
+	SDRAM_CAS_N <= cas_n_reg;
+	SDRAM_WE_N <= we_n_reg;
+	SDRAM_ldqm <= ldqm_reg;
+	SDRAM_udqm <= udqm_reg;
+	SDRAM_CKE <= cke_reg;
+	
+	-- inputs from SDRAM
+	dq_in_next <= SDRAM_DQ;
+	
+	-- back to slower clock
+	reply_snext <= reply_reg;
+	data_out_snext <= data_out_reg;
+	
+	-- outputs to rest of system
+	REPLY <= reply_sreg;
+	DATA_OUT <= DATA_OUT_sreg;
+		
+END vhdl;
Index: unmerged/core/mcc216/simple_counter.vhdl
===================================================================
--- unmerged/core/mcc216/simple_counter.vhdl	(nonexistent)
+++ unmerged/core/mcc216/simple_counter.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY simple_counter IS
+generic
+(
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+);
+END simple_counter;
+
+ARCHITECTURE vhdl OF simple_counter IS
+	signal value_next : std_logic_vector(COUNT_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(COUNT_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: unmerged/core/mcc216/zpu/pff.c
===================================================================
--- unmerged/core/mcc216/zpu/pff.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/core/mcc216/zpu/rom_epilogue.vhd
===================================================================
--- unmerged/core/mcc216/zpu/rom_epilogue.vhd	(nonexistent)
+++ unmerged/core/mcc216/zpu/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/core/mcc216/zpu/spi.h
===================================================================
--- unmerged/core/mcc216/zpu/spi.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/spi.h	(revision 1)
@@ -0,0 +1,65 @@
+/*! \file spi.h \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.h'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup driver_avr
+/// \defgroup spi SPI (Serial Peripheral Interface) Function Library (spi.c)
+/// \code #include "spi.h" \endcode
+/// \par Overview
+///		Provides basic byte and word transmitting and receiving via the AVR
+///	SPI interface.� Due to the nature of SPI, every SPI communication operation
+/// is both a transmit and simultaneous receive.
+///
+///	\note Currently, only MASTER mode is supported.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef SPI_H
+#define SPI_H
+
+#include "types.h"
+
+// function prototypes
+void mmcChipSelect(int select);
+
+
+// SPI interface initializer
+void spiInit(void);
+
+// spiTransferByte(u08 data) waits until the SPI interface is ready
+// and then sends a single byte over the SPI port.  The function also
+// returns the byte that was received during transmission.
+u08 spiTransferByte(u08 data);
+
+// spiTransferWord(u08 data) works just like spiTransferByte but
+// operates on a whole word (16-bits of data).
+u08 spiTransferFF();
+void spiTransferTwoFF();
+
+void spiDisplay(int i);
+
+#endif
Index: unmerged/core/mcc216/zpu/uart.h
===================================================================
--- unmerged/core/mcc216/zpu/uart.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/core/mcc216/zpu_core.vhd
===================================================================
--- unmerged/core/mcc216/zpu_core.vhd	(nonexistent)
+++ unmerged/core/mcc216/zpu_core.vhd	(revision 1)
@@ -0,0 +1,961 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium                                                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the medium size version.  ----
+----  Supports external memories.                                         ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPUMediumCore(Behave) (Entity and architecture)    ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+--
+-- write_en_o   - set to '1' for a single cycle to send off a write request.
+--                data_o is valid only while write_en_o='1'.
+-- read_en_o    - set to '1' for a single cycle to send off a read request.
+-- mem_busy_i   - It is illegal to send off a read/write request when
+--                mem_busy_i='1'.
+--                Set to '0' when data_i  is valid after a read request.
+--                If it goes to '1'(busy), it is on the cycle after read/
+--                write_en_o is '1'.
+-- addr_o       - address for read/write request
+-- data_i       - read data. Valid only on the cycle after mem_busy_i='0'
+--                after read_en_o='1' for a single cycle.
+-- data_o       - data to write
+-- break_o      - set to '1' when CPU hits break instruction
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+end entity ZPUMediumCore;
+
+architecture Behave of ZPUMediumCore is
+   constant BYTE_BITS    : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+   constant WORD_BYTES   : integer:=WORD_SIZE/OPCODE_W;
+   constant MAX_ADDR_BIT : integer:=ADDR_W-2;
+   -- Stack Pointer initial value: BRAM size-8
+   constant SP_START_1   : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
+   constant SP_START     : unsigned(ADDR_W-1 downto BYTE_BITS):=
+                           SP_START_1(ADDR_W-1 downto BYTE_BITS);
+
+   -- Update [SP+1]. We hold it in b_r, this writes the value to memory.
+   procedure FlushB(signal we     : out std_logic;
+                    signal addr   : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal inc_sp : in  unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal data   : out unsigned(WORD_SIZE-1 downto 0);
+                    signal b      : in  unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      we   <= '1';
+      addr <= inc_sp;
+      data <= b;
+   end procedure FlushB;
+
+   -- Do a simple stack push, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Push(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                  signal a      : in    unsigned(WORD_SIZE-1 downto 0);
+                  signal b      : out   unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      b  <= a;      -- Update cache [SP+1]=[SP]
+      sp <= sp-1;
+   end procedure Push;
+
+   -- Do a simple stack pop, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Pop(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                 signal a      : out   unsigned(WORD_SIZE-1 downto 0);
+                 signal b      : in    unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      a  <= b;      -- Update cache [SP]=[SP+1]
+      sp <= sp+1;
+   end procedure Pop;
+
+   -- Expand a PC value to WORD_SIZE
+   function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
+      variable nv : unsigned(WORD_SIZE-1 downto 0);
+   begin
+      nv:=(others => '0');
+      nv(ADDR_W-1 downto 0):=v;
+      return nv;
+   end function ExpandPC;
+
+   -- Program counter
+   signal pc_r          : unsigned(ADDR_W-1 downto 0):=(others => '0');
+   -- Stack pointer
+   signal sp_r          : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
+   -- SP+1, SP+2 and SP-1 are very used, these are shortcuts
+   signal inc_sp        : unsigned(ADDR_W-1 downto BYTE_BITS);
+   signal inc_inc_sp    : unsigned(ADDR_W-1 downto BYTE_BITS);
+   -- a_r is a cache for the top of the stack [SP]
+   -- Note: as this is a stack CPU this is a very important register.
+   signal a_r           : unsigned(WORD_SIZE-1 downto 0);
+   -- b_r is a cache for the next value in the stack [SP+1]
+   signal b_r           : unsigned(WORD_SIZE-1 downto 0);
+   signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_res1_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res2_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res3_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_a_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_b_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal idim_r        : std_logic;
+   signal write_en_r    : std_logic;
+	signal byte_read_r  : std_logic;
+	signal byte_write_r  : std_logic;
+	signal short_write_r : std_logic;
+   signal read_en_r     : std_logic;
+   signal addr_r        : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
+	signal addrl_r        : unsigned(BYTE_BITS-1 downto 0):=(others => '0');
+   signal fetched_w_r   : unsigned(WORD_SIZE-1 downto 0);
+
+   type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
+                   st_fetch, st_execute, st_decode, st_decode2, st_resync,
+                   st_store_sp2, st_resync2, st_resync3, st_loadb2,
+                   st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
+                   st_binary_op_res, st_idle); 
+   signal state : state_t:=st_resync;
+
+   -- Go to st_fetch state or just do its work
+   procedure DoFetch(constant FAST   : boolean;
+                     signal state    : out state_t;
+                     signal addr     : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal pc       : in  unsigned(ADDR_W-1 downto 0);
+                     signal re       : out std_logic;
+                     signal busy     : in  std_logic) is
+   begin
+      if FAST then
+         -- Equivalent to st_fetch
+         if busy='0' then
+            addr  <= pc(ADDR_W-1 downto BYTE_BITS);
+            re    <= '1';
+            state <= st_decode;
+         end if;
+      else
+         state <= st_fetch;
+      end if;
+   end procedure DoFetch;
+
+   -- Perform a "binary operation" (2 operands)
+   procedure DoBinOp(result         : in    unsigned(WORD_SIZE-1 downto 0);
+                     signal state   : out   state_t;
+                     signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal re      : out   std_logic;
+                     signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                     signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                     constant DEPTH :       natural) is
+   begin
+      if DEPTH=2 then
+         -- 2 clocks: st_binary_op_res+st_binary_op_res2
+         state  <= st_binary_op_res;
+         dest_p <= result;
+      elsif DEPTH=1 then
+         -- 1 clock: st_binary_op_res2
+         state  <= st_binary_op_res2;
+         dest_p <= result;
+      else -- 0 clocks
+         re    <= '1';
+         addr  <= sp+2;
+         sp    <= sp+1;
+         dest  <= result;
+         state <= st_popped;
+      end if;
+   end procedure DoBinOp;
+
+   -- Perform a boolean "binary operation" (2 operands)
+   procedure DoBinOpBool(result         : in    boolean;
+                         signal state   : out   state_t;
+                         signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal re      : out   std_logic;
+                         signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                         signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                         constant DEPTH :       natural) is
+      variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   begin
+      if result then
+         res(0):='1';
+      end if;
+      DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
+   end procedure DoBinOpBool;
+
+   type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
+                   dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
+                   dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
+                   dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
+                   dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
+                   dec_less_than, dec_less_than_or_equal, dec_lshr,
+                   dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
+                   dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
+                   dec_insn_fetch, dec_pop_down);
+   signal insn : insn_t;
+   type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
+   signal insns : insn_array_t;
+   type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
+   signal opcode_r : opcode_array_t;
+begin
+   -- the memory subsystem will tell us one cycle later whether or
+   -- not it is busy
+   write_en_o <= write_en_r;
+   read_en_o  <= read_en_r;
+	byte_read_o  <= byte_read_r;
+	byte_write_o  <= byte_write_r;
+	short_write_o  <= short_write_r;
+   addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
+   addr_o(BYTE_BITS-1 downto 0)      <= addrl_r;
+
+   -- SP+1 and +2
+   inc_sp     <= sp_r+1;
+   inc_inc_sp <= sp_r+2;
+
+   opcode_control:
+   process (clk_i)
+      variable topcode     : unsigned(OPCODE_W-1 downto 0);
+      variable ex_opcode   : unsigned(OPCODE_W-1 downto 0);
+      variable sp_offset   : unsigned(4 downto 0);
+      variable tsp_offset  : unsigned(4 downto 0);
+      variable next_pc     : unsigned(ADDR_W-1 downto 0);
+      variable tdecoded    : insn_t;
+      variable tinsns   : insn_array_t;
+      variable mult_res    : unsigned(WORD_SIZE*2-1 downto 0);
+      variable ipc_low     : integer range 0 to 3; -- Address inside a word (pc_r)
+      variable inpc_low    : integer range 0 to 3; -- Address inside a word (next_pc)
+      variable not_lshr    : std_logic:='1';
+   begin
+      if rising_edge(clk_i) then
+         break_o <= '0';
+         if reset_i='1' then
+            if ENA_IDLE then
+               state <= st_idle;
+            else
+               state <= st_resync;
+            end if;
+            sp_r         <= SP_START;
+            pc_r         <= (others => '0');
+            idim_r       <= '0';
+            write_en_r   <= '0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            read_en_r    <= '0';
+            mult_a_r     <= (others => '0');
+            mult_b_r     <= (others => '0');
+            dbg_o.b_inst <= '0';
+            -- Reseting add_r here makes XST fail to use BRAMs ?!
+         else -- reset_i='1'
+            if MULT_PIPE then
+               -- We must multiply unconditionally to get pipelined multiplication
+               mult_res:=mult_a_r*mult_b_r;
+               mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+               mult_res2_r <= mult_res1_r;
+               mult_res3_r <= mult_res2_r;
+               mult_a_r    <= (others => D_CARE_VAL);
+               mult_b_r    <= (others => D_CARE_VAL);
+            end if;
+
+            if BINOP_PIPE=2 then
+               bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
+            end if;
+   
+            read_en_r  <='0';
+            write_en_r <='0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            -- Allow synthesis tools to load bogus values when we don't
+            -- care about the address and output data.
+            addr_r     <= (others => D_CARE_VAL);
+            data_o     <= (others => D_CARE_VAL);
+				addrl_r    <= "00";
+   
+            if (write_en_r='1') and (read_en_r='1') then
+               report "read/write collision" severity failure;
+            end if;
+
+            ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
+            sp_offset(4):=not opcode_r(ipc_low)(4);
+            sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
+            next_pc:=pc_r+1;
+   
+            -- Prepare trace snapshot
+            dbg_o.opcode <= opcode_r(ipc_low);
+            dbg_o.pc     <= resize(pc_r,32);
+            dbg_o.stk_a  <= resize(a_r,32);
+            dbg_o.stk_b  <= resize(b_r,32);
+            dbg_o.b_inst <= '0';
+            dbg_o.sp     <= (others => '0');
+            dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+   
+            case state is
+                 when st_idle =>
+                      if enable_i='1' then
+                         state <= st_resync;
+                      end if;
+                 -- Initial state of ZPU, fetch top of stack (A/B) + first instruction
+                 when st_resync =>
+                      if mem_busy_i='0' then
+                         addr_r    <= sp_r;
+                         read_en_r <= '1';
+                         state     <= st_resync2;
+                      end if;
+                 when st_resync2 =>
+                      if mem_busy_i='0' then
+                         a_r       <= data_i;
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_resync3;
+                      end if;
+                 when st_resync3 =>
+                      if mem_busy_i='0' then
+                         b_r       <= data_i;
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 when st_decode =>
+                      if mem_busy_i='0' then
+                         -- Here we latch the fetched word to give one full clock
+                         -- cycle to the instruction decoder. This could be removed
+                         -- if using BRAMs and the decoder delay isn't important.
+                         fetched_w_r <= data_i;
+                         state       <= st_decode2;
+                      end if;
+                 when st_decode2 =>
+                      -- decode 4 instructions in parallel
+                      for i in 0 to WORD_BYTES-1 loop
+                          topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
+
+                          tsp_offset(4):=not topcode(4);
+                          tsp_offset(3 downto 0):=topcode(3 downto 0);
+
+                          opcode_r(i) <= topcode;
+                          if topcode(7 downto 7)=OPCODE_IM then
+                             tdecoded:=dec_im;
+                          elsif topcode(7 downto 5)=OPCODE_STORESP then
+                             if tsp_offset=0 then
+                                -- Special case, we can avoid a write
+                                tdecoded:=dec_pop;
+                             elsif tsp_offset=1 then
+                                -- Special case, collision
+                                tdecoded:=dec_pop_down;
+                             else
+                                tdecoded:=dec_store_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_LOADSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_dup;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_dup_stk_b;
+                             else
+                                tdecoded:=dec_load_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_EMULATE then
+                             tdecoded:=dec_emulate;
+                             if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
+                                tdecoded:=dec_neq_branch;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
+                                tdecoded:=dec_eq;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
+                                tdecoded:=dec_loadb;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
+                                tdecoded:=dec_push_sp_add;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
+                                tdecoded:=dec_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
+                                tdecoded:=dec_u_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
+                                tdecoded:=dec_mult;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
+                                tdecoded:=dec_storeb;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
+                                tdecoded:=dec_call_pc_rel;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
+                                tdecoded:=dec_sub;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+                                tdecoded:=dec_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+                                tdecoded:=dec_u_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
+                                tdecoded:=dec_call;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
+                                tdecoded:=dec_pop_pc_rel;
+                             elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+                                tdecoded:=dec_lshr;
+                             end if;
+                          elsif topcode(7 downto 4)=OPCODE_ADDSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_shift;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_add_top;
+                             else
+                                tdecoded:=dec_add_sp;
+                             end if;
+                          else -- OPCODE_SHORT
+                             case topcode(3 downto 0) is
+                                  when OPCODE_BREAK =>
+                                       tdecoded:=dec_break;
+                                  when OPCODE_PUSHSP =>
+                                       tdecoded:=dec_push_sp;
+                                  when OPCODE_POPPC =>
+                                       tdecoded:=dec_pop_pc;
+                                  when OPCODE_ADD =>
+                                       tdecoded:=dec_add;
+                                  when OPCODE_OR =>
+                                       tdecoded:=dec_or;
+                                  when OPCODE_AND =>
+                                       tdecoded:=dec_and;
+                                  when OPCODE_LOAD =>
+                                       tdecoded:=dec_load;
+                                  when OPCODE_NOT =>
+                                       tdecoded:=dec_not;
+                                  when OPCODE_FLIP =>
+                                       tdecoded:=dec_flip;
+                                  when OPCODE_STORE =>
+                                       tdecoded:=dec_store;
+                                  when OPCODE_POPSP =>
+                                       tdecoded:=dec_pop_sp;
+                                  when others => -- OPCODE_NOP and others
+                                       tdecoded:=dec_nop;
+                             end case;
+                          end if;
+                          tinsns(i):=tdecoded;
+                      end loop;
+                      
+                      insn <= tinsns(ipc_low);
+                      -- once we wrap, we need to fetch
+                      tinsns(0):=dec_insn_fetch;
+                      insns <= tinsns;
+                      state <= st_execute;
+
+                      -- Each instruction must:
+                      --
+                      -- 1. increase pc_r if applicable
+                      -- 2. set next state if applicable
+                      -- 3. do it's operation
+                 when st_execute =>
+                      -- Some shortcut to make the code readable:
+                      inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
+                      ex_opcode:=opcode_r(ipc_low);
+							 
+							 if (mem_busy_i = '0') then -- MWW, do not move on until mem is not busy!
+							 insn <= insns(inpc_low);
+							 
+                      -- Defaults used by most instructions
+                      if insn/=dec_insn_fetch and insn/=dec_im then
+                         dbg_o.b_inst <= '1';
+                         idim_r       <= '0';
+                      end if;
+							
+							case insn is
+                           when dec_insn_fetch =>
+                                -- Not a real instruction, fetch new instructions
+                                DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
+                           when dec_im =>
+                                -- Push(immediate value), IDIM=1
+                                -- if IDIM=0 Push(signed(opcode & 0x7F)) else
+                                --           Push((Pop()<<7)|(opcode&0x7F))
+                                if mem_busy_i='0' then
+                                   dbg_o.b_inst <= '1';
+                                   idim_r       <= '1';
+                                   pc_r             <= pc_r+1;
+                                   if idim_r='1' then
+                                      -- We already started an IM sequence
+                                      -- Shift left 7 bits
+                                      a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
+                                      -- Put the new value
+                                      a_r(6 downto 0) <= ex_opcode(6 downto 0);
+                                   else
+                                      -- First IM, push the value sign extended
+                                      FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                      a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
+                                      Push(sp_r,a_r,b_r);
+                                   end if;
+                                end if;
+                           when dec_store_sp =>
+                                -- [SP+Offset]=Pop()
+                                if mem_busy_i='0' then
+                                   write_en_r <= '1';
+                                   addr_r     <= sp_r+sp_offset;
+                                   data_o     <= a_r;
+                                   Pop(sp_r,a_r,b_r);
+                                   -- We need to fetch B
+                                   state      <= st_store_sp2;
+                                end if;
+                           when dec_load_sp =>
+                                -- Push([SP+Offset])
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   Push(sp_r,a_r,b_r);
+                                   -- We are flushing B cache, so we need more time to
+                                   -- read the value.
+                                   state <= st_load_sp2;
+                                end if;
+                           when dec_emulate =>
+                                -- Push(PC+1), PC=Opcode[4:0]*32
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   Push(sp_r,a_r,b_r);
+                                   -- The emulate address is:
+                                   --        98 7654 3210
+                                   -- 0000 00aa aaa0 0000
+                                   pc_r             <= (others => '0');
+                                   pc_r(9 downto 5) <= ex_opcode(4 downto 0);
+                                end if;
+                           when dec_call_pc_rel =>
+                                -- t=Pop(), Push(PC+1), PC=PC+t
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= pc_r+a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_call =>
+                                -- t=Pop(), Push(PC+1), PC=t
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_add_sp =>
+                                -- Push(Pop()+[SP+Offset])
+                                if mem_busy_i='0' then
+                                   -- Read SP+Offset
+                                   state     <= st_add_sp2;
+                                   read_en_r <= '1';
+                                   addr_r    <= sp_r+sp_offset;
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_push_sp =>
+                                -- Push(SP)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+                                   Push(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_pc =>
+                                -- PC=Pop() (return)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_pop_pc_rel =>
+                                -- PC=PC+Pop()
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_add =>
+                                -- Push(Pop()+Pop())  [A=A+B, SP++, update B]
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r+b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_sub =>
+                                -- a=Pop(), b=Pop(), Push(b-a)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
+                                           a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_pop =>
+                                -- Pop()
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   Pop(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_down =>
+                                -- t=Pop(), Pop(), Push(t)
+                                if mem_busy_i='0' then
+                                   -- PopDown leaves top of stack unchanged
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_or =>
+                                -- Push(Pop() or Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r or b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_and =>
+                                -- Push(Pop() and Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r and b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_eq =>
+                                -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than =>
+                                -- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than_or_equal =>
+                                -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_less_than =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_less_than_or_equal =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_load =>
+                                -- Push([Pop()])
+                                if mem_busy_i='0' then
+                                   state     <= st_load2;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   read_en_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_dup =>
+                                -- t=Pop(), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   -- A is dupped, no change
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_dup_stk_b =>
+                                -- Pop(), t=Pop(), Push(t), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= b_r;
+                                   -- B goes to A
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_store =>
+                                -- a=Pop(), b=Pop(), [a]=b
+                                if mem_busy_i='0' then
+                                   state      <= st_resync;
+                                   pc_r       <= pc_r+1;
+                                   addr_r     <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   data_o     <= b_r;
+                                   write_en_r <= '1';
+                                   sp_r       <= inc_inc_sp;
+                                end if;
+                           when dec_pop_sp =>
+                                -- SP=Pop()
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= pc_r+1;
+                                   sp_r  <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                end if;
+                           when dec_nop =>
+                                pc_r <= pc_r+1;
+                           when dec_not =>
+                                -- Push(not(Pop()))
+                                pc_r <= pc_r+1;
+                                a_r  <= not a_r;
+                           when dec_flip =>
+                                -- Push(flip(Pop()))
+                                pc_r <= pc_r+1;
+                                for i in 0 to WORD_SIZE-1 loop
+                                    a_r(i) <= a_r(WORD_SIZE-1-i);
+                                end loop;
+                           when dec_add_top =>
+                                -- a=Pop(), b=Pop(), Push(b), Push(a+b)
+                                pc_r <= pc_r+1;
+                                a_r  <= a_r+b_r;
+                           when dec_shift =>
+                                -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
+                                pc_r <= pc_r+1;
+                                a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
+                                a_r(0) <= '0';
+                           when dec_push_sp_add =>
+                                -- Push(Pop()+SP)
+                                if ENA_LEVEL0 then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <=
+                                      a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
+                                end if;
+                           when dec_neq_branch =>
+                                -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
+                                -- Branches are almost always taken as they form loops
+                                if ENA_LEVEL0 then
+                                   sp_r  <= inc_inc_sp;
+                                   -- Need to fetch stack again.
+                                   state <= st_resync;
+                                   if b_r/=0 then
+                                      pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   else
+                                      pc_r <= pc_r+1;
+                                   end if;
+                                end if;
+                           when dec_mult =>
+                                -- Push(Pop()*Pop())
+                                if ENA_LEVEL1 then
+                                   if MULT_PIPE then
+                                      mult_a_r <= a_r;
+                                      mult_b_r <= b_r;
+                                      state    <= st_mult2;
+                                   else
+                                      mult_res:=a_r*b_r;
+                                      mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+                                      state       <= st_mult5;
+                                   end if;
+                                end if;
+                           when dec_break =>
+                                -- Assert the break_o signal
+                                --report "Break instruction encountered" severity failure;
+                                break_o <= '1';
+                                pc_r    <= pc_r+1;
+                           when dec_loadb =>
+                                -- Push([Pop()] & 0xFF) (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   state     <= st_loadb2;                                   
+											  addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --read_en_r <= '1';
+											  byte_read_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_storeb =>
+                                -- [Pop()]=Pop() & 0xFF (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state     <= st_resync;
+											  sp_r       <= inc_inc_sp;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --write_en_r <= '1';
+											  byte_write_r <= '1';
+                                   pc_r      <= pc_r+1;
+											  --data_o(WORD_SIZE-1 downto 8) <= (others=>'0');
+											  --data_o(7 downto 0) <= b_r(7 downto 0);										  
+											  data_o(WORD_SIZE-1 downto 0) <= b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0);										  
+                                end if;
+                           when dec_lshr =>
+                                -- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
+                                if ENA_LSHR then
+                                   -- This instruction takes more than one cycle.
+                                   -- We must avoid duplications in the trace log.
+                                   dbg_o.b_inst <= not_lshr;
+                                   not_lshr:='0';
+                                   if a_r(5 downto 0)=0 then -- Only 6 bits used
+                                      -- No more shifts
+                                      if mem_busy_i='0' then
+                                         state     <= st_popped;
+                                         a_r       <= b_r;
+                                         read_en_r <= '1';
+                                         addr_r    <= inc_inc_sp;
+                                         sp_r      <= inc_sp;
+                                         not_lshr:='1';
+                                      end if;
+                                   else -- More shifts needed
+                                      b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
+                                      a_r(5 downto 0) <= a_r(5 downto 0)-1;
+                                      insn <= insn;
+                                   end if;
+                                end if;
+                           when others =>
+                                -- Undefined behavior, we shouldn't get here.
+                                -- It only helps synthesis tools.
+                                sp_r <= (others => D_CARE_VAL);
+                                report "Illegal decode instruction?!" severity failure;
+                                --break_o <= '1';
+                      end case;
+							 end if;
+                 -- The followup of operations that takes more than one execution clock
+                 when st_store_sp2 =>
+                      if mem_busy_i='0' then
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_popped;
+                      end if;
+                 when st_load_sp2 =>
+                      if mem_busy_i='0' then
+                         state     <= st_load_sp3;
+                         -- Now we can read SP+Offset (SP already decremented)
+                         read_en_r <= '1';
+                         addr_r    <= sp_r+sp_offset+1;
+                      end if;
+                 when st_load_sp3 =>
+                      if mem_busy_i='0' then
+                         -- Note: We can't increment PC in the decode stage
+                         -- because it will modify sp_offset.
+                         pc_r  <= pc_r+1;
+                         -- Finally we have the result in A
+                         state <= st_execute;
+                         a_r   <= data_i;
+                      end if;
+                 when st_add_sp2 =>
+                      if mem_busy_i='0' then
+                         state <= st_execute;
+                         a_r   <= a_r+data_i;
+                      end if;
+                 when st_load2 =>
+                      if mem_busy_i='0' then
+                         a_r   <= data_i;
+                         state <= st_execute;
+                      end if;
+                 when st_loadb2 =>
+                      if mem_busy_i='0' then
+                         a_r(WORD_SIZE-1 downto 8) <= (others => '0');								 
+								 a_r(7 downto 0) <= data_i(7 downto 0);
+                         state <= st_execute;
+                      end if;
+                 when st_fetch =>
+                      if mem_busy_i='0' then
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 -- The following states can be used to leave cycles free for
+                 -- tools that can automagically decompose the multiplication
+                 -- in various stages. Xilinx tools can do it to increase the
+                 -- multipliers performance.
+                 when st_mult2 =>
+                      state <= st_mult3;
+                 when st_mult3 =>
+                      state <= st_mult4;
+                 when st_mult4 =>
+                      state <= st_mult5;
+                 when st_mult5 =>
+                      if mem_busy_i='0' then
+                         if MULT_PIPE then
+                            a_r <= mult_res3_r;
+                         else
+                            a_r <= mult_res1_r;
+                         end if;
+                         read_en_r <= '1';
+                         addr_r    <= inc_inc_sp;
+                         sp_r      <= inc_sp;
+                         state     <= st_popped;
+                      end if;
+               when st_binary_op_res =>
+                    -- BINOP_PIPE=2
+                    state <= st_binary_op_res2;
+               when st_binary_op_res2 =>
+                    -- BINOP_PIPE>=1
+                    read_en_r <= '1';
+                    addr_r    <= inc_inc_sp;
+                    sp_r      <= inc_sp;
+                    state     <= st_popped;
+                    if BINOP_PIPE=2 then
+                       a_r <= bin_op_res2_r;
+                    else -- 1
+                       a_r <= bin_op_res1_r;
+                    end if;
+               when st_popped =>
+                    if mem_busy_i='0' then
+                       -- Note: Moving this PC++ to the decoder seems to
+                       -- consume more LUTs.
+                       pc_r  <= pc_r+1;
+                       b_r   <= data_i;
+                       state <= st_execute;
+                    end if;
+               when others =>
+                    -- Undefined behavior, we shouldn't get here.
+                    -- It only helps synthesis tools.
+                    sp_r <= (others => D_CARE_VAL);
+                    report "Illegal state?!" severity failure;
+                    --break_o <= '1';
+            end case; -- state
+         end if; -- else reset_i='1'
+      end if; -- rising_edge(clk_i)
+   end process opcode_control;
+end architecture Behave; -- Entity: ZPUMediumCore
+
Index: unmerged/core/mcc216/zpu_ram.qip
===================================================================
--- unmerged/core/mcc216/zpu_ram.qip	(nonexistent)
+++ unmerged/core/mcc216/zpu_ram.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_ram.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_ram.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_ram.cmp"]
Index: unmerged/core/mcc216/zpu_rom.vhd
===================================================================
--- unmerged/core/mcc216/zpu_rom.vhd	(nonexistent)
+++ unmerged/core/mcc216/zpu_rom.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: zpu_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY zpu_rom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END zpu_rom;
+
+
+ARCHITECTURE SYN OF zpu_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./zpu/HelloTinyROM_ROM.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 4096,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 12,
+		width_a => 32,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./zpu/HelloTinyROM_ROM.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./zpu/HelloTinyROM_ROM.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/PLLJ_PLLSPE_INFO.txt
===================================================================
--- unmerged/core/mist/PLLJ_PLLSPE_INFO.txt	(nonexistent)
+++ unmerged/core/mist/PLLJ_PLLSPE_INFO.txt	(revision 1)
@@ -0,0 +1,5 @@
+PLL_Name	pll:b2v_inst5|altpll:altpll_component|pll_altpll:auto_generated|pll1
+PLLJITTER	26
+PLLSPEmax	84
+PLLSPEmin	-53
+
Index: unmerged/core/mcc216/syncreset_enable_divider.vhd
===================================================================
--- unmerged/core/mcc216/syncreset_enable_divider.vhd	(nonexistent)
+++ unmerged/core/mcc216/syncreset_enable_divider.vhd	(revision 1)
@@ -0,0 +1,81 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY syncreset_enable_divider IS
+generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNCRESET : in std_logic;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END syncreset_enable_divider;
+
+ARCHITECTURE vhdl OF syncreset_enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg,syncreset)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+		
+		if (syncreset='1') then
+			count_next <= std_logic_vector(to_unsigned(resetcount,width));
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: unmerged/core/mcc216/zpu/bootdump.c
===================================================================
--- unmerged/core/mcc216/zpu/bootdump.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/core/mcc216/zpu/integer.h
===================================================================
--- unmerged/core/mcc216/zpu/integer.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/core/mcc216/zpu/mmc.c
===================================================================
--- unmerged/core/mcc216/zpu/mmc.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/mmc.c	(revision 1)
@@ -0,0 +1,269 @@
+/*! \file mmc.c \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.c'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+//----- Include Files ---------------------------------------------------------
+#include "spi.h"		// include spi bus support
+
+
+//#define spiTransferTwoFF()	{ spiTransferFF(); spiTransferFF(); }
+
+
+#include "mmc.h"
+
+// include project-specific hardware configuration
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+	// initialize SPI interface
+	spiInit();
+	// release chip select
+	mmcChipSelect(0);
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(1);
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+	u08 retry=0xff;	//255x
+	//
+
+	spiTransferFF();
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+	//
+	spiTransferByte(arg>>24);
+	spiTransferByte(arg>>16);
+	spiTransferByte(arg>>8);
+	spiTransferByte(arg);
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+		retry--;
+	}
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
Index: unmerged/core/mcc216/zpu/pause.h
===================================================================
--- unmerged/core/mcc216/zpu/pause.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/core/mcc216/zpu/regs.h
===================================================================
--- unmerged/core/mcc216/zpu/regs.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/regs.h	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_dmactl;
+
+#endif // regs_h
Index: unmerged/core/mcc216/zpu/spi.c
===================================================================
--- unmerged/core/mcc216/zpu/spi.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/spi.c	(revision 1)
@@ -0,0 +1,116 @@
+/*! \file spi.c \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.c'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include "spi.h"
+
+#include "regs.h"
+#include "spi.h"
+
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+	updateSpiState();
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+	updateSpiState();
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+}
+
Index: unmerged/core/mcc216/zpu/uart.c
===================================================================
--- unmerged/core/mcc216/zpu/uart.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/core/mcc216/zpu_config_regs.vhdl.bak
===================================================================
--- unmerged/core/mcc216/zpu_config_regs.vhdl.bak	(nonexistent)
+++ unmerged/core/mcc216/zpu_config_regs.vhdl.bak	(revision 1)
@@ -0,0 +1,475 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	TURBO : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+			else
+				config_6502_reg <= config_6502_next;
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_6502: TODO 
+	-- 	W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= SWITCH;
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= KEY;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				--data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1';
+	TURBO <= '0';
+	USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= "00";
+	VGA <= switch(9);
+	COMPOSITE_ON_HSYNC <= switch(8);
+	GPIO_ENABLE <= '0'; -- need to fix carts! TODO FIXME XXX
+	ROM_SELECT <= switch(6 downto 5);
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+end vhdl;
+
+
Index: unmerged/core/mcc216/zpu_ram.cmp
===================================================================
--- unmerged/core/mcc216/zpu_ram.cmp	(nonexistent)
+++ unmerged/core/mcc216/zpu_ram.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component zpu_ram
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mcc216/zpu_rom.qip
===================================================================
--- unmerged/core/mcc216/zpu_rom.qip	(nonexistent)
+++ unmerged/core/mcc216/zpu_rom.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_rom.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.cmp"]
Index: unmerged/core/mist/COPYRIGHT_NOTICE
===================================================================
--- unmerged/core/mist/COPYRIGHT_NOTICE	(nonexistent)
+++ unmerged/core/mist/COPYRIGHT_NOTICE	(revision 1)
@@ -0,0 +1,129 @@
+(c) 2013 Mark Watson
+I am happy for anyone to use these for non-commercial use.
+If my vhdl files are used commercially or sold please contact me for explicit permission at scrameta@gmail.com.
+This applies for source and binary form and derived works.
+
+pokey.vhdl
+pokey_noise_filter.vhdl
+pokey_keyboard_scanner.vhdl
+pokey_ps2_decoder.vhdl
+pokey_mixer.vhdl
+poly_4.vhdl
+poly_5.vhdl
+poly_17_9.vhdl
+
+gtia.vhdl
+gtia_priority.vhdl
+gtia_palette.vhdl // Palette data itself from laoo and Altirra
+gtia_player.vhdl
+
+antic.vhdl
+antic_dma_clock.vhdl
+antic_counter.vhdl
+
+pia.vhdl
+
+cpu.vhd
+shared_enable.vhdl
+irq_glue.vhdl
+
+ps2_keyboard.vhdl
+
+scandoubler.vhdl
+scandouble_ram_infer.vhdl
+
+zpu_glue.vhdl
+zpu_config_regs.vhdl
+
+// utils
+synchronizer.vhdl
+delay_line.vhdl
+wide_delay_line.vhdl
+reg_file.vhdl
+enable_divider.vhdl
+syncreset_enable_divider.vhd
+complete_address_decoder.vhdl
+countdown_timer.vhdl
+simple_counter.vhdl
+
+// semi de1 specific
+sram.vhdl
+flashrom.vhdl
+sdram_statemachine.vhdl
+address_decoder.vhdl
+
+// de1 specific
+atari800core.vhd // top level for DE1
+i2sslave.vhdl
+hexdecoder.vhd
+gpio.vhd
+ledsw.vhd
+
+// altera megafunctions
+pll.vhd 
+zpu_ram.vhd
+zpu_rom.vhd
+
+-----------------------------------------------------------------------------------
+(c) Mike Stirling (from Spectrum core)
+See header for Mike's copyright note
+Parameters modified for my use case
+
+i2c_loader.vhd
+i2s_intf.vhd
+
+-----------------------------------------------------------------------------------
+(c) Peter Wendrich
+Please contact Peter if you wish to use them. I have permission for use as part of the Atari800 core.
+
+cpu_6510.vhd
+cpu_65xx_e.vhd
+cpu_65xx_a.vhd
+
+-----------------------------------------------------------------------------------
+---- Copyright (c) 2008 Ãvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+ZPU implementation. See headers for more details
+I made a few fixes to make it work for my use case.
+
+zpu_core.vhd
+zpupkg.vhd
+
+-----------------------------------------------------------------------------------
+(c) Scott Larson
+See file header
+
+spi_master.vhd
+
+-----------------------------------------------------------------------------------
+-----------------------------------------------------------------------------------
+zpu/*.[ch]
+SD card/OSD
+-----------------------------------------------------------------------------------
+(c) Mark Watson
+Also some portions taken from SDrive, so (c) Bob and Raster
+
+I am happy for these to be used freely for commercial and non-commercial use.
+
+debug.h  led.h   pause.h  regs.h  types.h  uart.h
+bootdump.c  debug.c  led.c  main.c  regs.c  test.c  uart.c
+
+zpuromgen.c
+
+----------------------------------------------------------------------------------
+(c) Pascal Stang + Bob and Raster
+spi.c
+spi.h
+mmc.c  
+mmc.h
+mmcconf.h 
+
+-----------------------------------------------------------------------------------
+(c) ChaN
+Petit File System
+
+integer.h  
+diskio.h  
+pff.h
+pff.c  
Index: unmerged/core/mist/antic.vhdl
===================================================================
--- unmerged/core/mist/antic.vhdl	(nonexistent)
+++ unmerged/core/mist/antic.vhdl	(revision 1)
@@ -0,0 +1,1824 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	MEMORY_READY_ANTIC : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	ANTIC_ENABLE_179 : IN std_logic;
+	
+	PAL : IN STD_LOGIC;
+	
+	lightpen : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	NMI_N_OUT : OUT std_logic;
+	ANTIC_READY : OUT std_logic; -- taken low by wsync writes
+	
+	-- GTIA interface
+	AN : OUT STD_LOGIC_VECTOR(2 downto 0);
+	COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
+	COLOUR_CLOCK_OUT : out std_logic;
+	HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
+	
+	-- DMA fetch
+	dma_fetch_out : out std_logic;
+	dma_address_out : out std_logic_vector(15 downto 0);
+	
+	-- refresh
+	refresh_out : out std_logic; -- used by sdram
+	
+	-- for debugging
+	dma_clock_out : out std_logic
+);
+END antic;
+
+ARCHITECTURE vhdl OF antic IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT antic_dma_clock IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		enable_dma : IN STD_LOGIC;
+		
+		playfield_start : in std_logic;
+		playfield_end : in std_logic;
+		vblank : in std_logic;
+		
+		slow_dma : in std_logic;
+		medium_dma : in std_logic;
+		fast_dma : in std_logic;
+				
+		dma_clock_out_0 : out std_logic;
+		dma_clock_out_1 : out std_logic;
+		dma_clock_out_2 : out std_logic;
+		dma_clock_out_3 : out std_logic
+	);
+	END component;
+	
+	component antic_counter IS
+	generic
+	(
+		STORE_WIDTH : natural := 1;
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+		
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;	
+
+	component reg_file IS
+	generic
+	(
+		BYTES : natural := 1;
+		WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal enable_dma : std_logic;
+	signal dma_clock_character_name : std_logic;
+	signal dma_clock_character_inc : std_logic;
+	signal dma_clock_bitmap_data : std_logic;
+	signal dma_clock_character_data : std_logic;
+	
+	signal wsync_next : std_logic;
+	signal wsync_reg : std_logic;
+	signal wsync_reset : std_logic;
+	signal wsync_write : std_logic;
+	signal wsync_delayed_write : std_logic;
+	
+	signal nmi_next : std_logic;
+	signal nmi_reg : std_logic;
+	
+	signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
+	signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
+	
+	signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
+	signal nmist_reg : std_logic_vector(7 downto 5);
+	
+	signal nmist_reset : std_logic;
+	
+	signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
+	signal nmien_raw_reg : std_logic_vector(7 downto 6);
+	signal nmien_delayed_reg : std_logic_vector(7 downto 6);
+	
+	signal dli_nmi_next : std_logic;
+	signal vbi_nmi_next : std_logic;
+	signal dli_nmi_reg : std_logic;
+	signal vbi_nmi_reg : std_logic;
+	
+	signal nmi_reset : std_logic;
+	--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
+	--signal nmi_pending_reg : std_logic;
+	
+	signal playfield_dma_start : std_logic;
+	signal playfield_dma_end : std_logic;
+	signal playfield_display_active_next : std_logic;
+	signal playfield_display_active_reg : std_logic;
+	
+	signal dmactl_raw_next : std_logic_vector(6 downto 0);
+	signal dmactl_raw_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_enabled : std_logic;
+	
+	signal chactl_next : std_logic_vector(2 downto 0);
+	signal chactl_reg : std_logic_vector(2 downto 0);
+	
+	-- dma is only allowed during certain portions of the display
+	signal allow_real_dma_next : std_logic;
+	signal allow_real_dma_reg : std_logic;
+	
+	-- dma fetch handling
+	-- dma is scheduled one cycle before it happens, so that registers can directly drive output	
+	signal dma_fetch_next : std_logic;
+	signal dma_fetch_reg : std_logic;
+	signal dma_address_next : std_logic_vector(15 downto 0);
+	signal dma_address_reg : std_logic_vector(15 downto 0);
+	
+	constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
+	constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
+	constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
+	constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
+	constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
+	constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
+	signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
+	signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
+	signal dma_fetch_request : std_logic;
+	
+	signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
+	signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
+	
+	signal character_next : std_logic_vector(7 downto 0);
+	signal character_reg : std_logic_vector(7 downto 0);
+
+	signal displayed_character_next : std_logic_vector(7 downto 0);
+	signal displayed_character_reg : std_logic_vector(7 downto 0);
+	
+	-- instruction decode
+	signal instruction_next : std_logic_vector(7 downto 0);
+	signal instruction_reg : std_logic_vector(7 downto 0);
+	
+	signal first_line_of_instruction_next : std_logic;
+	signal first_line_of_instruction_reg: std_logic;
+
+	signal last_line_of_instruction_live : std_logic;
+	signal last_line_of_instruction_next : std_logic;
+	signal last_line_of_instruction_reg: std_logic;
+	
+	signal force_final_row : std_logic;
+	
+	signal instruction_blank_reg : std_logic;
+	signal instruction_blank_next : std_logic;
+
+	--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
+	--signal dma_speed_next : dma_speed_type;
+	--signal dma_speed_reg : dma_speed_type;
+	constant no_dma : std_logic_vector(1 downto 0) := "00";
+	constant slow_dma : std_logic_vector(1 downto 0) := "01";
+	constant medium_dma : std_logic_vector(1 downto 0) := "10";
+	constant fast_dma : std_logic_vector(1 downto 0) := "11";
+	signal dma_speed_next : std_logic_vector(1 downto 0);
+	signal dma_speed_reg : std_logic_vector(1 downto 0);
+	signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
+	
+	--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
+	--signal instruction_type_next : instruction_type;
+	--signal instruction_type_reg : instruction_type;
+	constant mode_character : std_logic_vector(2 downto 0) := "000";
+	constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
+	constant mode_jvb : std_logic_vector(2 downto 0) := "010";
+	constant mode_jump : std_logic_vector(2 downto 0) := "011";
+	constant mode_blank : std_logic_vector(2 downto 0) := "100";
+	signal instruction_type_next : std_logic_vector(2 downto 0);
+	signal instruction_type_reg : std_logic_vector(2 downto 0);
+	
+	signal two_part_instruction_next : std_logic;
+	signal two_part_instruction_reg : std_logic;
+
+		-- e.g. if instruction is 8 lines long then the final row is 7
+	signal instruction_final_row_next : std_logic_vector(3 downto 0);
+	signal instruction_final_row_reg : std_logic_vector(3 downto 0);
+		
+	--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
+	--signal shift_rate_next : shift_rate_type;
+	--signal shift_rate_reg : shift_rate_type;
+	constant slow_shift : std_logic_vector(1 downto 0) := "00";
+	constant medium_shift : std_logic_vector(1 downto 0) := "01";
+	constant fast_shift : std_logic_vector(1 downto 0) := "10";
+	signal shift_rate_next : std_logic_vector(1 downto 0);
+	signal shift_rate_reg : std_logic_vector(1 downto 0);
+	
+	signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
+	signal shift_twobit_reg : std_logic;
+	
+	signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
+	signal twopixel_reg : std_logic;	
+	
+	signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
+	signal single_colour_character_reg : std_logic;
+
+	signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
+	signal multi_colour_character_reg : std_logic;
+	
+	signal twoline_character_next : std_logic; -- for antic 5/7
+	signal twoline_character_reg : std_logic;
+	
+	signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
+	signal map_background_reg : std_logic;
+	
+	signal dli_enabled_next : std_logic;
+	signal dli_enabled_reg : std_logic;
+	
+	signal descenders_next : std_logic; -- for mode 3
+	signal descenders_reg : std_logic;
+		
+	-- Shift register used to output to AN2-AN0	
+	-- Can either be loaded from memory or from the line buffer
+	signal display_shift_next : std_logic_vector(7 downto 0);
+	signal display_shift_reg : std_logic_vector(7 downto 0);
+	
+	signal delay_display_shift_next : std_logic_vector(24 downto 0);
+	signal delay_display_shift_reg : std_logic_vector(24 downto 0);
+	
+	signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
+	
+	signal load_display_shift_from_memory : std_logic;
+	signal load_display_shift_from_line_buffer : std_logic;
+	
+	signal enable_shift : std_logic;
+	signal shiftclock_next : std_logic_vector(3 downto 0);
+	signal shiftclock_reg : std_logic_vector(3 downto 0);
+	
+	signal playfield_reset : std_logic;
+	signal playfield_load : std_logic;
+	
+	-- position in frame	
+	signal hcount_next : std_logic_vector(7 downto 0);
+	signal hcount_reg : std_logic_vector(7 downto 0);
+	
+	signal vcount_next : std_logic_vector(8 downto 0);
+	signal vcount_reg : std_logic_vector(8 downto 0);
+	
+	signal vblank_next : std_logic;
+	signal vblank_reg : std_logic;
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
+	
+	signal hcount_reset : std_logic;
+	signal vcount_reset : std_logic;
+	signal vcount_increment : std_logic;
+	
+	-- scrolling	
+	signal hscrol_reg : std_logic_vector(3 downto 0);
+	signal hscrol_next : std_logic_vector(3 downto 0);
+
+	signal vscrol_raw_reg : std_logic_vector(3 downto 0);
+	signal vscrol_raw_next : std_logic_vector(3 downto 0);
+	signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
+	
+	signal vscrol_enabled_reg : std_logic;
+	signal vscrol_enabled_next : std_logic;
+	signal vscrol_last_enabled_reg : std_logic;
+	signal vscrol_last_enabled_next : std_logic;
+	
+	signal update_row_count : std_logic;
+	
+	signal hscrol_enabled_reg : std_logic;
+	signal hscrol_enabled_next : std_logic;
+
+	-- refresh
+	signal refresh_pending_next : std_logic;
+	signal refresh_pending_reg : std_logic;
+
+	signal refresh_fetch_next : std_logic;
+	signal refresh_fetch_reg : std_logic;
+	
+	-- Counter signals
+	signal increment_display_list_address : std_logic;
+	signal load_display_list_address : std_logic;
+	signal display_list_address_next : std_logic_vector(15 downto 0);
+	signal display_list_address_reg : std_logic_vector(15 downto 0);
+	signal load_display_list_address_cpu : std_logic;
+	signal load_display_list_address_dma : std_logic;
+	signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
+	signal display_list_address_next_dma : std_logic_vector(15 downto 0);	
+
+	signal increment_memory_scan_address : std_logic;
+	signal load_memory_scan_address : std_logic;
+	signal memory_scan_address_next : std_logic_vector(15 downto 0);
+	signal memory_scan_address_reg : std_logic_vector(15 downto 0);
+
+	signal increment_line_buffer_address : std_logic;
+	signal load_line_buffer_address : std_logic;
+	signal line_buffer_address_next : std_logic_vector(7 downto 0);
+	signal line_buffer_address_reg : std_logic_vector(7 downto 0);
+
+	signal increment_row_count : std_logic;
+	signal load_row_count : std_logic;
+	signal row_count_next : std_logic_vector(3 downto 0);
+	signal row_count_reg : std_logic_vector(3 downto 0);
+
+	signal increment_refresh_count : std_logic;
+	signal load_refresh_count : std_logic;
+	signal refresh_count_next : std_logic_vector(3 downto 0);
+	signal refresh_count_reg : std_logic_vector(3 downto 0);
+	
+	signal pmbase_reg : std_logic_vector(7 downto 2);
+	signal pmbase_next : std_logic_vector(7 downto 2);
+
+	signal chbase_raw_reg : std_logic_vector(7 downto 1);
+	signal chbase_raw_next : std_logic_vector(7 downto 1);
+	signal chbase_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal line_buffer_write : std_logic;
+	signal line_buffer_data_in : std_logic_vector(7 downto 0);
+	signal line_buffer_data_out : std_logic_vector(7 downto 0);
+	
+	-- output registers
+	signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
+	signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
+	signal an_prev_reg : std_logic_vector(2 downto 0);  -- previous - for hscrol
+	signal an_next : std_logic_vector(2 downto 0);
+	signal an_reg : std_logic_vector(2 downto 0);
+	
+	-- light pendin
+	signal penv_next : std_logic_vector(7 downto 0);
+	signal penv_reg : std_logic_vector(7 downto 0);
+	signal penh_next : std_logic_vector(7 downto 0);
+	signal penh_reg : std_logic_vector(7 downto 0);
+	
+	-- high res modes
+	signal colour_clock_8x : std_logic;
+	signal colour_clock_4x : std_logic;
+	signal colour_clock_2x : std_logic;
+	signal colour_clock_1x : std_logic;
+	signal colour_clock_half_x : std_logic;
+	signal colour_clock_selected : std_logic;
+	signal colour_clock_selected_highres : std_logic;
+	
+	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
+	
+	constant cycle_length : integer := 32;	
+	
+	signal memory_ready_both : std_logic;
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			nmi_reg <= '0';
+			wsync_reg <= '0';
+			vcount_reg <= (others=>'0');
+			--hcount_reg <= X"01";
+			hcount_reg <= X"00";
+			dmactl_raw_reg <= (others=>'0');
+			chactl_reg <= (others=>'0');
+			vblank_reg <= '0';			
+			vsync_reg <= '0';
+			pmbase_reg <= (others=>'0');
+			allow_real_dma_reg <= '0';
+			display_shift_reg <= (others=>'0');
+			chbase_raw_reg <= (others=>'0');
+			
+			instruction_reg <= (others=>'0');
+			first_line_of_instruction_reg <= '0';
+			last_line_of_instruction_reg <= '0';
+			dma_speed_reg <= no_dma;
+			instruction_type_reg <= mode_blank;
+			instruction_final_row_reg <= (others=>'0');
+			shift_rate_reg <= slow_shift;
+			shift_twobit_reg <= '0';
+			twopixel_reg <= '0';
+			single_colour_character_reg <= '0';
+			multi_colour_character_reg <= '0';
+			twoline_character_reg <= '0';
+			map_background_reg <= '0';
+			dli_enabled_reg <= '0';
+			two_part_instruction_reg <= '0';
+			descenders_reg <='0';
+			
+			hscrol_reg <= (others=>'0');
+			vscrol_raw_reg <= (others=>'0');			
+			vscrol_enabled_reg <= '0';
+			vscrol_last_enabled_reg <= '0';
+			hscrol_enabled_reg <= '0';
+			
+			shiftclock_reg <= (others=>'0');
+			
+			hblank_reg <= '0';
+			
+			an_reg <= (others=>'0');
+			an_prev_reg <= (others=>'0');
+			
+			dma_fetch_reg <= '0';
+			dma_address_reg <= (others=>'0');			
+			dma_fetch_destination_reg <= dma_fetch_null;
+			
+			playfield_display_active_reg <= '0';
+			
+			instruction_blank_reg <= '0';
+			
+			display_list_address_low_temp_reg <= (others=>'0');
+			
+			character_reg <= (others=>'0');
+			displayed_character_reg <= (others=>'0');
+			
+			refresh_pending_reg <= '0';
+			refresh_fetch_reg <= '0';
+			
+			--nmi_pending_reg <= '0';
+			
+			dli_nmi_reg <= '0';
+			vbi_nmi_reg <= '0';
+			nmien_raw_reg <= (others=>'0');
+			
+			delay_display_shift_reg <= (others=>'0');
+			
+			nmi_shiftreg_reg <= (others=>'1');
+			
+			penh_reg <= (others=>'0');
+			penv_reg <= (others=>'0');
+			
+			colour_clock_count_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then			
+			nmi_reg <= nmi_next;
+			wsync_reg <= wsync_next;
+			vcount_reg <= vcount_next;
+			hcount_reg <= hcount_next;
+			nmist_reg <= nmist_next;
+			dmactl_raw_reg <= dmactl_raw_next;
+			chactl_reg <= chactl_next;
+			vblank_reg <= vblank_next;
+			vsync_reg <= vsync_next;
+			pmbase_reg <= pmbase_next;
+			allow_real_dma_reg <= allow_real_dma_next;
+			display_shift_reg <= display_shift_next;
+			chbase_raw_reg <= chbase_raw_next;
+			
+			instruction_reg <= instruction_next;
+			first_line_of_instruction_reg <= first_line_of_instruction_next;
+			last_line_of_instruction_reg <= last_line_of_instruction_next;
+			dma_speed_reg <= dma_speed_next;
+			instruction_type_reg <= instruction_type_next;
+			instruction_final_row_reg <= instruction_final_row_next;
+			shift_rate_reg <= shift_rate_next;
+			shift_twobit_reg <= shift_twobit_next;
+			twopixel_reg <= twopixel_next;
+			single_colour_character_reg <= single_colour_character_next;
+			multi_colour_character_reg <= multi_colour_character_next;
+			twoline_character_reg <= twoline_character_next;
+			map_background_reg <= map_background_next;
+			dli_enabled_reg <= dli_enabled_next;
+			two_part_instruction_reg <= two_part_instruction_next;
+			descenders_reg <= descenders_next;
+			
+			hscrol_reg <= hscrol_next;
+			vscrol_raw_reg <= vscrol_raw_next;	
+			vscrol_enabled_reg <= vscrol_enabled_next;
+			vscrol_last_enabled_reg <= vscrol_last_enabled_next;
+			hscrol_enabled_reg <= hscrol_enabled_next;
+			
+			shiftclock_reg <= shiftclock_next;
+			
+			hblank_reg <= hblank_next;
+			
+			an_reg <= an_next;
+			an_prev_reg <= an_prev_next;
+			
+			dma_fetch_reg <= dma_fetch_next;
+			dma_address_reg <= dma_address_next;
+			dma_fetch_destination_reg <= dma_fetch_destination_next;
+			
+			playfield_display_active_reg <= playfield_display_active_next;
+			
+			instruction_blank_reg <= instruction_blank_next;
+			
+			display_list_address_low_temp_reg <= display_list_address_low_temp_next;
+			
+			character_reg <= character_next;
+			displayed_character_reg <= displayed_character_next;
+			
+			refresh_pending_reg <= refresh_pending_next;
+			refresh_fetch_reg <= refresh_fetch_next;
+						
+			dli_nmi_reg <= dli_nmi_next;
+			vbi_nmi_reg <= vbi_nmi_next;
+			nmien_raw_reg <= nmien_raw_next;
+			
+			delay_display_shift_reg <= delay_display_shift_next;
+			
+			nmi_shiftreg_reg <= nmi_shiftreg_next;
+			
+			penh_reg <= penh_next;
+			penv_reg <= penv_next;
+			
+			colour_clock_count_reg <= colour_clock_count_next;
+		end if;
+	end process;
+	
+	-- Colour clock (3.57MHz for PAL)
+	-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
+	-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
+	--enable_colour_clock_div : enable_divider
+		--generic map (COUNT=>7)
+		--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);	
+	process(colour_clock_count_reg, ANTIC_ENABLE_179)		
+	begin
+		colour_clock_half_x <= '0';
+		colour_clock_1x<='0';
+		colour_clock_2x<='0';
+		colour_clock_4x<='0';
+		colour_clock_8x<='0';
+	
+		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+		
+		if (ANTIC_ENABLE_179 = '1') then -- resync...
+			colour_clock_count_next <= "00001";
+		end if;
+
+		colour_clock_8x <= '1';
+		
+		case colour_clock_count_reg(4 downto 0) is
+		when "00000" =>
+			colour_clock_half_x <= '1';
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "00100" =>
+			colour_clock_4x <= '1';
+		when "01000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "01100" =>
+			colour_clock_4x <= '1';
+		when "10000" =>			
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "10100" =>
+			colour_clock_4x <= '1';
+		when "11000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "11100" =>
+			colour_clock_4x <= '1';			
+		when others =>
+			-- nop
+		end case;
+	end process;
+	
+	process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
+	begin
+		enable_dma <= colour_clock_half_x;
+		colour_clock_selected <= colour_clock_1x;
+		colour_clock_selected_highres <= colour_clock_2x;		
+		dmactl_delayed_enabled <= '0';
+		
+		case dmactl_delayed_reg(6 downto 5) is
+		when "01" =>
+			dmactl_delayed_enabled <= '1';
+		when "10" =>
+			enable_dma <= colour_clock_1x;
+			colour_clock_selected <= colour_clock_2x;		
+			colour_clock_selected_highres <= colour_clock_4x;
+			dmactl_delayed_enabled <= '1';
+		when "11" =>
+			enable_dma <= colour_clock_2x;
+			colour_clock_selected <= colour_clock_4x;
+			colour_clock_selected_highres <= colour_clock_8x;
+			dmactl_delayed_enabled <= '1';
+		when others =>
+			--nop
+		end case;		
+	end process;	
+		
+	--enable_dma_clock_div : enable_divider
+	--	generic map (COUNT=>2)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>colour_clock_selected,enable_out=>enable_dma);		
+
+	-- Counters (memory address for data, memory address for display list)
+	antic_counter_memory_scan : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
+		
+	load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
+	display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
+	antic_counter_display_list : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
+	antic_counter_line_buffer : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
+	antic_counter_row_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
+	antic_counter_refresh_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
+	
+	-- Count position on screen
+	-- horizontal
+	process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
+	begin
+		hcount_next <= hcount_reg;		
+		if (colour_clock_1x = '1') then
+			hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
+			
+			if (colour_clock_half_x = '1') then
+				hcount_next(0) <= '1';
+			end if;
+		end if;
+		
+		if (hcount_reset = '1') then
+			hcount_next <= (others=>'0');
+		end if;
+	end process;
+	
+	-- vertical
+	process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
+	begin
+		vcount_next <= vcount_reg;
+		
+		if (colour_clock_1x = '1') then		
+			if (vcount_increment = '1') then
+				vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
+			end if;
+			
+			if (vcount_reset = '1') then
+				vcount_next <= (others=>'0');
+			end if;
+		end if;
+	end process;	
+	
+	-- Actions done based on vertical position		
+	process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
+	begin
+		vblank_next <= vblank_reg;
+		vsync_next <= vsync_reg;
+		vcount_reset <= '0';
+	
+		if (colour_clock_1x='1') then
+			case vcount_reg is
+				when '0'&X"08" => 
+					vblank_next <= '0';
+				when '0'&X"F8" =>
+					vblank_next <= '1';
+				--when '1'&X"05" => (changed for testing galaxian!)
+				--	vblank_next <= '1';					
+-- PAL
+				when '1'&X"16" =>
+					vsync_next <= pal;
+				when '1'&X"19" =>
+					vsync_next <= '0';
+				when '1'&X"38" =>
+					vcount_reset <= '1'; -- Blip at 9c..., then wrap
+-- NTSC
+				when '0'&X"FA" =>
+					vsync_next <= not(pal);
+				when '0'&X"FD" =>
+					vsync_next <= '0';
+				when '1'&X"06" =>
+					vcount_reset <= not(pal); -- Blip at 9c..., then wrap
+				when others =>
+					-- nothing
+			end case;
+		end if;
+	end process;
+	
+	-- Calculate playfield start/end
+	process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
+	begin		
+		playfield_dma_start_cycle <= (others=>'1');
+		playfield_dma_end_cycle <= (others=>'1');
+		playfield_display_start_cycle <= (others=>'1');
+		playfield_display_end_cycle <= (others=>'1');
+		
+		-- DMA clock start/end
+		-- wide=3, normal=2, narrow=1
+		-- Playfield start is at (in colour clocks):
+		-- 68 + hscrol&FE - width*16
+		-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
+		-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong... 
+		-- e.g. if its 64 then we may be able to do something like base&width&
+		-- Playfield end is at (in colour clocks):
+		-- 164 + hscrol&FE + width*16
+		-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
+		
+		-- hscrol interfers with playfield dma width (for dma purposes only!)
+		if (hscrol_enabled_reg='1') then
+			case dmactl_delayed_reg(1 downto 0) is
+				when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
+					playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20  (10 in machine cycles)
+					playfield_dma_end_cycle   <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
+				when "01" => -- narrow - traated as normal due to hscrol
+					playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36  (18 in machine cycles)
+					playfield_dma_end_cycle <=   X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
+				when others =>
+					-- nothing
+			end case;
+		else
+			case dmactl_delayed_reg(1 downto 0) is
+				when "11" => -- wide
+					playfield_dma_start_cycle <= X"11";
+					playfield_dma_end_cycle   <= X"D0";
+				when "10" => -- normal
+					playfield_dma_start_cycle <= X"21";
+					playfield_dma_end_cycle   <= X"C0";
+				when "01" => -- narrow
+					playfield_dma_start_cycle <= X"31";
+					playfield_dma_end_cycle <=   X"B0";
+				when others =>
+					-- nothing
+			end case;		
+		end if;
+
+		-- background colour outside this area...
+		-- TODO - review these locations - should be clear due to garbage!
+		case dmactl_delayed_reg(1 downto 0) is
+			when "11" => -- wide
+				playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
+				if (hscrol_reg > X"C") then
+					playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol				
+				end if;
+				playfield_display_end_cycle   <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
+			when "10" => -- normal
+				playfield_display_start_cycle <= X"2F";
+				playfield_display_end_cycle   <= X"CF";
+			when "01" => -- narrow
+				playfield_display_start_cycle <= X"3F";
+				playfield_display_end_cycle <=   X"BF";
+			when others =>
+				-- nothing
+		end case;				
+	end process;
+	
+	-- Actions done based on horizontal position - notably dma!
+	process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, displayed_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg)
+	begin
+		allow_real_dma_next <= allow_real_dma_reg;
+
+		playfield_dma_start <= '0';
+		playfield_dma_end <= '0';
+		playfield_display_active_next <= playfield_display_active_reg;
+		
+		dma_fetch_request <= '0';
+		dma_address_next <= dma_address_reg;
+		dma_fetch_destination_next <= dma_fetch_destination_reg;
+		
+		first_line_of_instruction_next <= first_line_of_instruction_reg;
+		last_line_of_instruction_next <= last_line_of_instruction_reg;
+		
+		load_display_shift_from_line_buffer <= '0';
+				
+		increment_memory_scan_address <= '0';
+		
+		line_buffer_address_next <= (others=>'0');
+		load_line_buffer_address <= '0';
+		increment_line_buffer_address <= '0';
+		
+		playfield_load <= '0';
+		
+		hblank_next <= hblank_reg;
+		hcount_reset <= '0';
+		
+		vcount_increment <= '0';
+		
+		character_next <= character_reg;
+		displayed_character_next <= displayed_character_reg;
+		
+		dli_nmi_next <= dli_nmi_reg;
+		vbi_nmi_next <= vbi_nmi_reg;
+		wsync_reset <= '0';
+		
+		load_refresh_count <= '0';
+		refresh_count_next <= (others=>'0');
+		
+		update_row_count <= '0'; 
+		vscrol_last_enabled_next <= vscrol_last_enabled_reg;
+	
+		if (colour_clock_1x = '1') then	
+			-- Playfield start/end
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
+				playfield_dma_start <= '1';				
+				load_line_buffer_address <= '1';
+			end if;
+			
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
+				playfield_dma_end <= '1';
+			end if;	
+			
+			if (hcount_reg = playfield_display_start_cycle) then
+				playfield_display_active_next <= '1';				
+			end if;
+			
+			if (hcount_reg = playfield_display_end_cycle) then
+				playfield_display_active_next <= '0';
+			end if;	
+
+			if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
+				if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
+					dma_fetch_request <= '1';
+				end if;				
+
+				if (twoline_character_reg='1') then
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				else
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				end if;
+				
+				displayed_character_next <= character_reg;
+				
+				-- TODO
+				-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.				
+				dma_fetch_destination_next <= dma_fetch_shiftreg;
+				
+				load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);								
+				increment_line_buffer_address <= '1';
+			end if;						
+		
+			case hcount_reg is 		
+				when X"00" => -- missile DMA, if missile or player DMA enabled					
+					dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;									
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"02" => -- display list dma if enabled
+					first_line_of_instruction_next <= '0';
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- suppress when waiting for vblank
+						first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
+					else				
+						if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
+							dma_fetch_request <= dmactl_delayed_enabled;
+							dma_address_next <= display_list_address_reg;
+							dma_fetch_destination_next <= dma_fetch_instruction;									
+							
+							first_line_of_instruction_next <= '1';						
+							
+							vscrol_last_enabled_next <= vscrol_enabled_reg;
+						end if;
+					end if;					
+				
+				when X"03" =>				
+					update_row_count <= '1'; -- done after instruction fetch...
+					
+				when X"04"|X"06"|X"08"|X"0A" =>  -- player DMA, if enabled
+					dma_fetch_request <= dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;	
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"0C" => -- lms lower byte dma if display list dma enabled?;
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_low;
+				
+				when X"0E" => -- lms upper byte dma if display list dma enabled?
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_high;
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
+						first_line_of_instruction_next <= '0';
+					end if;
+					
+					dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
+					if (vcount_reg = '0'&X"F8") then
+						vbi_nmi_next <= '1';
+					end if;
+					
+				when X"12" =>
+					dli_nmi_next <= '0';
+					vbi_nmi_next <= '0';
+
+				when X"21" =>
+					hblank_next <= '0';					
+					
+				when X"24" => 
+					playfield_load <= '1'; -- start the shift register
+					
+				when X"31" => -- start refresh					
+					load_refresh_count <= '1';
+					refresh_count_next <= (others=>'0');
+				
+				when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
+					wsync_reset <= '1';				
+			
+				when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
+					allow_real_dma_next <= '0';				
+					load_refresh_count <= '1';
+					refresh_count_next <= "1001";
+					
+				when X"D8" => -- vscrol value checked at cycle 108
+					last_line_of_instruction_next <= last_line_of_instruction_live;
+				
+				when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
+					vcount_increment <= '1';
+										
+				when X"DD" =>
+					hblank_next <= '1';					
+					
+				when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
+					hcount_reset <= '1';
+					allow_real_dma_next <= not(vblank_reg);
+				when others =>
+					-- nothing
+			end case;	
+			
+			-- Playfield DMA
+			if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
+				dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= first_line_of_instruction_reg;
+			end if;					
+			
+			if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
+				character_next <= line_buffer_data_out;
+				increment_line_buffer_address <= '1';
+			end if;
+			
+			if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data			
+				dma_fetch_request <= dmactl_delayed_enabled;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= '1';		
+			end if;
+			
+			if (vblank_reg = '1') then
+				dma_fetch_request <= '0';
+			end if;
+			
+			if (refresh_fetch_next = '1') then
+				dma_address_next <= (others=>'0');
+			end if;
+		
+		end if;
+	end process;
+	
+	-- refresh handling
+	process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, memory_ready_antic, allow_real_dma_next)
+	begin
+		increment_refresh_count <= '0';
+		refresh_pending_next <= refresh_pending_reg;
+		refresh_fetch_next <= not(memory_ready_antic) and refresh_fetch_reg;
+		
+		if (colour_clock_1x = '1') then
+			-- do pending refresh once we have a spare cycle
+			if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
+				refresh_fetch_next <= '1';		
+				refresh_pending_next <= '0';
+			end if;
+		
+			-- do scheduled refresh - if block, enable pending one
+			if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
+				increment_refresh_count <= '1';
+				refresh_fetch_next <= not(dma_fetch_next);
+				refresh_pending_next <= dma_fetch_next;
+			end if;
+		end if;
+	end process;
+	
+	-- nmi handling
+	-- edge senstive, single cycle is enough (unless cpu disabled or  clashes)
+	-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist...	which is the goal.	
+
+	nmien_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
+		
+	nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
+	
+	process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
+	begin	
+		nmist_next(5) <= '0';
+		nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
+		nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
+	end process;
+	
+	-- dma clock	
+	process(dma_speed_reg) -- XXX TODO - remove this process!
+	begin
+		slow_dma_s <= '0';
+		medium_dma_s <= '0';
+		fast_dma_s <= '0';
+		
+		case dma_speed_reg is
+			when no_dma =>
+				-- nothing
+			when slow_dma =>
+				slow_dma_s <= '1';
+			when medium_dma =>
+				medium_dma_s <= '1';
+			when fast_dma =>
+				fast_dma_s <= '1';
+		end case;
+	end process;
+	
+	antic_dma_clock1 : antic_dma_clock
+		port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
+
+	-- line buffer
+	reg_file1 : reg_file
+		generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
+		port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);		
+		--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
+		--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
+		
+	-- vertical scrolling
+	-- load row count from vscrol must be done at time of instruction load
+	-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
+	-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
+	vscrol_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>4)
+		port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));		
+	
+	process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count, force_final_row)
+	begin								
+		load_row_count <= '0';
+		row_count_next <= (others=>'0');
+		increment_row_count <= '0';
+		
+		last_line_of_instruction_live <= '0';		
+		
+		if (update_row_count = '1') then							
+			if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
+				row_count_next <= vscrol_delayed_reg;
+			end if;
+		
+			if (first_line_of_instruction_reg = '1') then
+				load_row_count <= '1';
+			else
+				increment_row_count <= '1';
+			end if;
+		end if;
+		
+		if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
+			if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
+				last_line_of_instruction_live <= '1';
+			end if;
+		else -- normal
+			if (row_count_reg = instruction_final_row_reg) then
+				last_line_of_instruction_live <= '1';
+			end if;
+		end if;
+		
+		if (vblank_reg = '1' or force_final_row = '1') then
+			last_line_of_instruction_live <= '1';
+		end if;
+						
+	end process;
+	
+	-- chbase 2 cycle delay
+	chbase_delay : wide_delay_line
+		generic map (COUNT=>cycle_length*2,WIDTH=>7)
+		port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
+		
+	-- decode instruction	
+	process(instruction_reg)
+	begin
+		dma_speed_next <= no_dma;
+		instruction_type_next <= mode_blank;
+		shift_rate_next <= slow_shift;
+		shift_twobit_next <= '0';
+		twopixel_next <= '0';
+		single_colour_character_next <= '0';		
+		multi_colour_character_next <= '0';		
+		twoline_character_next <= '0';
+		map_background_next <= '0';
+		instruction_final_row_next <= (others=>'0');
+		two_part_instruction_next <= instruction_reg(6);
+		instruction_blank_next <= '0';
+		vscrol_enabled_next <= instruction_reg(5);
+		hscrol_enabled_next <= instruction_reg(4);
+		dli_enabled_next <= instruction_reg(7);
+		descenders_next <= '0';		
+		force_final_row <= '0';
+		
+		case instruction_reg(3 downto 0) is 			
+			when X"0" =>
+				instruction_type_next <= mode_blank;
+				instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
+				two_part_instruction_next <= '0';
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				
+			when X"1" =>
+				instruction_type_next <= mode_jump;
+				instruction_final_row_next <= (others=>'0');
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				two_part_instruction_next <= '1';
+				
+				if (instruction_reg(6) = '1') then
+					instruction_type_next <= mode_jvb;
+					force_final_row <= '1';
+				end if;
+				
+			when X"2" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+			when X"3" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"9";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				descenders_next <= '1';
+				
+			when X"4" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				multi_colour_character_next <= '1';
+				
+			when X"5" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';	
+				twoline_character_next <= '1';		
+				multi_colour_character_next <= '1';
+				
+			when X"6" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				
+			when X"7" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				twoline_character_next <= '1';
+				
+			when X"8" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= slow_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"9" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"A" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"B" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"C" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"D" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"E" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"F" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+		end case;
+	end process;
+
+	-- dma fetching
+	process(dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,memory_ready_both,memory_data_in,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
+	begin	
+		instruction_next <= instruction_reg;
+		dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
+		
+		display_list_address_next_dma <= display_list_address_reg;
+		load_display_list_address_dma <= '0';
+		memory_scan_address_next <= memory_scan_address_reg;
+		load_memory_scan_address <= '0';
+		increment_display_list_address <= '0';
+		
+		load_display_shift_from_memory <= '0';
+		display_list_address_low_temp_next <= display_list_address_low_temp_reg;		
+		
+		line_buffer_data_in <= (others=>'0');
+		line_buffer_write <= '0';
+		
+		if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
+			instruction_next <= (others=>'0');
+		end if;
+	
+		if (dma_fetch_reg='1' and memory_ready_both='1') then
+			case dma_fetch_destination_reg is 
+				when dma_fetch_line_buffer =>
+					line_buffer_data_in <= memory_data_in;					
+					line_buffer_write <= '1';
+				when dma_fetch_shiftreg =>
+					load_display_shift_from_memory <= '1';
+				when dma_fetch_null =>
+					-- nothing (C/G/MTIA listens to bus)
+				when dma_fetch_instruction =>
+					instruction_next <= memory_data_in;
+					
+					increment_display_list_address <= '1';
+					
+				when dma_fetch_list_low =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						--display_list_address_next_dma(7 downto 0) <= memory_data_in; Changing this so soon messes up next dma cycle
+						display_list_address_low_temp_next <= memory_data_in;
+						increment_display_list_address <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(7 downto 0) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				when dma_fetch_list_high =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						 display_list_address_next_dma <= memory_data_in&display_list_address_low_temp_reg;
+						 load_display_list_address_dma <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(15 downto 8) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				
+				when others =>
+					-- nothing
+				
+			end case;
+
+			dma_fetch_next <= '0';
+		end if;
+	end process;
+	
+	-- shift reg clock
+	playfield_reset <= hblank_reg;
+	
+	process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
+	begin
+		shiftclock_next <= shiftclock_reg;
+		enable_shift <= '0';
+	
+		if (colour_clock_selected = '1') then
+		
+			shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
+			
+			if (playfield_load='1') then
+				shiftclock_next <= "1000";
+			end if;
+			
+			if (playfield_reset='1') then
+				shiftclock_next <= "0000";
+			end if;			
+			
+			--shiftclock_next(0) <= shiftclock_reg(1);
+			--shiftclock_next(1) <= shiftclock_reg(2);
+			--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
+			--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;						
+			case shift_rate_reg is
+				when slow_shift =>
+					enable_shift <= shiftclock_reg(0);
+				when medium_shift =>
+					enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
+				when fast_shift =>			
+					enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
+				when others =>
+					-- nothing
+			end case;			
+		end if;
+	end process;
+
+	-- shift reg
+	process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, memory_data_in, line_buffer_data_out)
+	begin
+		display_shift_next <= display_shift_reg;
+		
+		if (enable_shift = '1') then
+			if (shift_twobit_reg = '1') then
+				display_shift_next <= display_shift_reg(5 downto 0)&"00";
+			else
+				display_shift_next <= display_shift_reg(6 downto 0)&"0";
+			end if;			
+		end if;
+		
+		if (load_display_shift_from_memory = '1') then
+			display_shift_next(7 downto 0) <= memory_data_in;
+		end if;
+
+		if (load_display_shift_from_line_buffer = '1') then
+			display_shift_next(7 downto 0) <= line_buffer_data_out;
+		end if;
+		
+	end process;
+	
+	-- delay shift reg output for n cycles, so we can match AN with antic output
+	process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg)
+	begin
+		delay_display_shift_next <= delay_display_shift_reg;
+		
+		if (colour_clock_selected = '1') then
+			delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
+		end if;
+		
+	end process;
+	
+	-- ANO-2
+	-- XXX - clean up!	
+	-- first process - AN with no blanking	
+	process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
+	begin
+		an_current <= (others=>'0');
+		data_live <= (others=>'0');
+		if (shift_twobit_reg = '1') then				
+			an_current(0) <= delay_display_shift_reg(0);
+			an_current(1) <= delay_display_shift_reg(1);
+			an_current(2) <= '1';
+			
+			if (instruction_type_reg = mode_character) then							
+				data_live(0) <= delay_display_shift_reg(0);
+				data_live(1) <= delay_display_shift_reg(1);
+								
+				if (descenders_reg = '1') then					
+					if (delay_display_shift_reg(3 downto 2) = "11") then
+						if (unsigned(row_count_reg)<2) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					else
+						if (unsigned(row_count_reg)>=8) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					end if;
+				end if;	
+			
+				if (delay_display_shift_reg(4)='1') then -- inverse/hidden
+					if (chactl_reg(1)='1') then
+						an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
+						an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
+					else
+						an_current(0) <= data_live(0) and not(chactl_reg(0));
+						an_current(1) <= data_live(1) and not(chactl_reg(0));					
+					end if;
+				else
+					an_current(0) <= data_live(0);
+					an_current(1) <= data_live(1);				
+				end if;
+			end if;		
+
+			if (multi_colour_character_reg = '1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "11"&delay_display_shift_reg(4);										
+				end case;				
+			end if;
+			
+			if (map_background_reg='1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "110";										
+				end case;
+			end if;
+		else
+			if (single_colour_character_reg = '1') then
+				-- i.e. antic 6,7
+				if (delay_display_shift_reg(1) = '1') then
+					an_current(0) <= delay_display_shift_reg(3);
+					an_current(1) <= delay_display_shift_reg(4);
+					an_current(2) <= '1';					
+				else
+					an_current(0) <= '0';
+					an_current(1) <= '0';
+					an_current(2) <= '0';
+				end if;			
+			end if;
+			
+			if (map_background_reg='1') then
+				if (delay_display_shift_reg(1)='1') then
+					an_current <= "100";
+				else
+					an_current <= "000";										
+				end if;
+			end if;				
+		end if;		
+	end process;
+	
+	process(colour_clock_selected, an_current, an_prev_reg)
+	begin
+		an_prev_next <= an_prev_reg;
+		
+		if (colour_clock_selected = '1') then
+			an_prev_next <= an_current;
+		end if;
+	end process;
+	
+	process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
+	begin
+		an_next <= an_reg;
+	
+		if (colour_clock_selected = '1') then	
+			an_next <= an_current;
+			
+			if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
+				an_next <= an_prev_reg;
+			end if;
+			
+			if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
+				an_next <= "000";
+			end if;
+			
+			if (vblank_reg = '1' or hblank_reg = '1') then				
+				an_next(0) <= vsync_reg or twopixel_reg;
+				an_next(1) <= not(vsync_reg);
+				an_next(2) <= not(hblank_reg) and twopixel_reg;
+				
+				--an_next <= 
+						--(twopixel_reg and not(vsync_reg or hblank_reg))
+						--&((hblank_reg or vblank_reg) and not(vsync_reg))
+						--&(vsync_reg or twopixel_reg);
+			end if;			
+			
+			-- TODO this is too simplistic:
+			-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
+			-- + odd behaviour seen during high res bug
+
+		end if;
+		
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+
+	-- wsync write takes 1 cycle to assert rdy
+	-- TODO - revisit antic delays in terms of cpu cycles
+	wsync_delay : delay_line
+		generic map (COUNT=>cycle_length+cycle_length/2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
+
+	-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
+	--dmactl_delay : wide_delay_line
+	--	generic map (COUNT=>cycle_length,WIDTH=>6)
+	--	port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
+	dmactl_delayed_reg <= dmactl_raw_next;
+	--dmactl_delayed_reg <= dmactl_raw_reg;
+		
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
+	begin		
+		nmien_raw_next <= nmien_raw_reg;
+		dmactl_raw_next <= dmactl_raw_reg;
+		chactl_next <= chactl_reg;
+		hscrol_next <= hscrol_reg;
+		vscrol_raw_next <= vscrol_raw_reg;
+		chbase_raw_next <= chbase_raw_reg;
+		pmbase_next <= pmbase_reg;
+		wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
+		nmist_reset <= '0';
+		wsync_write <= '0';
+		
+		load_display_list_address_cpu <= '0';
+		display_list_address_next_cpu <= display_list_address_reg;
+	
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				dmactl_raw_next <= cpu_data_in(6 downto 0);
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				chactl_next <= cpu_data_in(2 downto 0);
+			end if;	
+			
+			if(addr_decoded(2) = '1') then
+				display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;		
+			
+			if(addr_decoded(3) = '1') then
+				display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;
+
+			if(addr_decoded(4) = '1') then
+				hscrol_next <= cpu_data_in(3 downto 0);
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				vscrol_raw_next <= cpu_data_in(3 downto 0);
+			end if;
+			
+			if(addr_decoded(7) = '1') then
+				pmbase_next <= cpu_data_in(7 downto 2);
+			end if;		
+			
+			if(addr_decoded(9) = '1') then
+				chbase_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+
+			if(addr_decoded(10) = '1') then
+				wsync_write <= '1';
+			end if;		
+	
+			if(addr_decoded(14) = '1') then
+				nmien_raw_next <= cpu_data_in(7 downto 6);
+			end if;
+		
+			if(addr_decoded(15) = '1') then
+				nmist_reset <= '1';
+			end if;		
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
+	begin
+		data_out <= X"FF";
+
+		if (addr_decoded(8) = '1') then -- HCOUNT :-)
+			data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
+		end if;
+		
+		if(addr_decoded(11) = '1') then --VCOUNT
+			data_out <= vcount_reg(8 downto 1);
+		end if;
+		
+		if (addr_decoded(12) = '1') then -- PENH
+			data_out <= penh_reg;
+		end if;
+		
+		if (addr_decoded(13) = '1') then -- PENV
+			data_out <= penv_reg;
+		end if;
+
+		if(addr_decoded(15) = '1') then --NMIST
+			data_out <= nmist_reg&"00000";
+		end if;
+		
+	end process;
+	
+	-- nmi delay
+	nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
+	
+	-- light pen
+	process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
+	begin
+		penv_next <= penv_reg;
+		penh_next <= penh_reg;
+		
+		if (lightpen = '0') then
+			penv_next <= vcount_reg(8 downto 1);
+			penh_next <= hcount_reg;
+		end if;
+	end process;
+	
+	-- Use CPU data if virtual dma
+	MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
+	
+	-- output
+	nmi_n_out <= nmi_shiftreg_reg(0);
+	
+	dma_clock_out<=dma_clock_character_name;
+	
+	AN <= an_reg;
+	
+	antic_ready <= not(wsync_reg);
+	
+	dma_fetch_out <= refresh_fetch_reg or (allow_real_dma_reg and dma_fetch_reg);
+	dma_address_out <= dma_address_reg;
+	
+	refresh_out <= refresh_fetch_reg;
+	
+	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+	COLOUR_CLOCK_OUT <= colour_clock_selected;
+	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
+	
+END vhdl;
+
Index: unmerged/core/mcc216/zpu/main.c
===================================================================
--- unmerged/core/mcc216/zpu/main.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/main.c	(revision 1)
@@ -0,0 +1,1166 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (reset_n == 1)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<7;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (pause == 0)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<6;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+
+	if ((1&*zpu_key) == 1)
+	{
+		// stop 6502
+		pause_6502(1);
+
+		// write a display list in page 6 (TODO, backup first...)
+		*((volatile unsigned char *)(0x600 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x601 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x602 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x603 + 0x10000)) = 0x42;
+		*((volatile unsigned char *)(0x604 + 0x10000)) = 0x40;
+		*((volatile unsigned char *)(0x605 + 0x10000)) = 0x06;
+		*((volatile unsigned char *)(0x606 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x607 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x608 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x609 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60a + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60b + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60c + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60d + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60e + 0x10000)) = 0x41;
+		*((volatile unsigned char *)(0x60f + 0x10000)) = 0x00;
+		*((volatile unsigned char *)(0x610 + 0x10000)) = 0x06;
+
+		*((volatile unsigned char *)(0x640 + 0x10000)) = 'H';
+		*((volatile unsigned char *)(0x641 + 0x10000)) = 'E';
+		*((volatile unsigned char *)(0x642 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x643 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x644 + 0x10000)) = 'O';
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+
+		// wait 10 seconds
+		for (i=0; i!=10000; ++i)
+		{
+			*atari_colbk = *atari_random;
+			wait_us(1000);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		int fileno;
+		int skip;
+		int plotted = 0;
+		unsigned char volatile * mem;
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		for (;;)
+		{
+			int i = 0;
+			int go = 0;
+			fileno = 0;
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			if (FR_OK != pf_opendir(&dir,"/"))
+			{
+				debug("opendir failed\n");
+				while(1);
+			}
+
+			plotted = 0;
+			skip = 0;
+			if (selfileno>20)
+			{
+				skip = selfileno-20;
+				skip&=0xfffffffe;
+			}
+			if (selfileno<0)
+			{
+				selfileno = 0;
+			}
+			while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+			{
+				if (filinfo.fattrib & AM_SYS)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_HID)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_DIR)
+				{
+					debug("DIR ");
+				}
+				if (selfileno == fileno)
+				{
+					for (i=0;i!=256;++i)
+					{
+						atari_sector_buffer[i] = filinfo.fname[i];
+						if (0==filinfo.fname[i]) break;
+						filinfo.fname[i]+=128;
+					}
+				}
+				if (--skip<0)
+				{
+					debug(filinfo.fname);
+					++plotted;
+					if (plotted&1)
+					{
+						setxpos(20);
+					}
+					else
+					{
+						debug("\n");
+					}
+					if (plotted==40)
+					{
+						break;
+					}
+				}
+				fileno++;
+			}
+			debug("\n");
+			setypos(21);
+			openfile(atari_sector_buffer);
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					selfileno+=2;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					selfileno-=2;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					selfileno|=1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					selfileno&=0xfffffffe;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+			if (go == 1)
+			{
+				debug("Booting...");
+				wait_us(500000);
+
+				// reset process
+				reset_6502(0);
+				*atari_nmien = 0x00;
+				clear_64k_ram();
+				reset_6502(1);
+				break;
+			}
+			wait_us(80000);
+		}
+		initdebug(debugmode);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	speed = speedslow;
+	if (2==(2&(*zpu_switches)))
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+
+		wait_us(2000000);
+	}
+
+	if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	do
+	{
+		mmcInit();
+	}
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	openfile("BOOT.ATR");
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId == 0x31)
+ 	 	{
+			int sent = 0;
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/core/mcc216/zpu/mycrt0.s
===================================================================
--- unmerged/core/mcc216/zpu/mycrt0.s	(nonexistent)
+++ unmerged/core/mcc216/zpu/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/core/mcc216/zpu/regs.c
===================================================================
--- unmerged/core/mcc216/zpu/regs.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/regs.c	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+
+#endif // regs_h
Index: unmerged/core/mcc216/zpu/setup
===================================================================
--- unmerged/core/mcc216/zpu/setup	(nonexistent)
+++ unmerged/core/mcc216/zpu/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/core/mcc216/zpu/types.h
===================================================================
--- unmerged/core/mcc216/zpu/types.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/core/mcc216/zpu_config_regs.vhdl
===================================================================
--- unmerged/core/mcc216/zpu_config_regs.vhdl	(nonexistent)
+++ unmerged/core/mcc216/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,501 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(1 downto 0);
+	signal ram_select_reg : std_logic_vector(1 downto 0);
+	signal rom_select_next : std_logic_vector(1 downto 0);
+	signal rom_select_reg : std_logic_vector(1 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				rom_select_reg <= "01";
+				ram_select_reg <= "10";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(9 downto 8);
+				rom_select_next <= cpu_DATA_IN(13 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(9 downto 8) <= ram_select_reg;
+				data_out(13 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= key;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				--data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1'; -- TODO
+	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= '1';
+	COMPOSITE_ON_HSYNC <= '0';
+	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+end vhdl;
+
+
Index: unmerged/core/mcc216/zpu_glue.vhdl.bak
===================================================================
--- unmerged/core/mcc216/zpu_glue.vhdl.bak	(nonexistent)
+++ unmerged/core/mcc216/zpu_glue.vhdl.bak	(revision 1)
@@ -0,0 +1,332 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+library work;
+use work.zpupkg.all;
+
+ENTITY zpu_glue IS
+PORT 
+(
+	CLK : in std_logic;
+	RESET : in std_logic;
+	PAUSE : in std_logic;
+
+	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
+	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+	
+	ZPU_DO : out std_logic_vector(31 downto 0);
+	
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
+	
+	-- request
+	MEMORY_FETCH : out std_logic;
+	ZPU_READ_ENABLE : out std_logic;
+	ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
+	ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
+	
+	-- config
+	ZPU_CONFIG_WRITE : out std_logic;
+	
+	-- stack request
+	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+	
+	-- response
+	MEMORY_READY : in std_logic
+);
+END zpu_glue;
+
+architecture sticky of zpu_glue is
+component ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=24;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=16;  -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+	end component;	
+			
+	signal zpu_addr_unsigned : unsigned(23 downto 0);
+	signal zpu_do_unsigned : unsigned(31 downto 0);
+	signal ZPU_DI_unsigned : unsigned(31 downto 0);
+	signal zpu_break : std_logic;
+	signal zpu_debug : zpu_dbgo_t;
+	
+	signal zpu_mem_busy : std_logic;
+	
+	signal zpu_memory_fetch_pending_next : std_logic;
+	signal zpu_memory_fetch_pending_reg : std_logic;
+	
+	signal ZPU_32bit_READ_ENABLE_temp : std_logic;
+	signal ZPU_8bit_READ_ENABLE_temp : std_logic;	
+	signal ZPU_READ_temp : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;	
+	signal ZPU_WRITE_temp : std_logic;
+	
+	signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;	
+	signal ZPU_READ_next : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;	
+	signal ZPU_READ_reg : std_logic;
+	
+	signal block_mem : std_logic;
+	signal config_mem : std_logic;
+	
+	signal result_next : std_logic_vector(3 downto 0);
+	signal result_reg : std_logic_vector(3 downto 0);
+	constant result_external : std_logic_vector(3 downto 0) := "0000";
+	constant result_ram : std_logic_vector(3 downto 0) := "0001";
+	constant result_ram_8bit_0 : std_logic_vector(3 downto 0) := "0010";
+	constant result_ram_8bit_1 : std_logic_vector(3 downto 0) := "0011";
+	constant result_ram_8bit_2 : std_logic_vector(3 downto 0) := "0100";
+	constant result_ram_8bit_3 : std_logic_vector(3 downto 0) := "0101";
+	constant result_rom : std_logic_vector(3 downto 0) := "0110";
+	constant result_rom_8bit_0 : std_logic_vector(3 downto 0) := "0111";
+	constant result_rom_8bit_1 : std_logic_vector(3 downto 0) := "1000";
+	constant result_rom_8bit_2 : std_logic_vector(3 downto 0) := "1001";
+	constant result_rom_8bit_3 : std_logic_vector(3 downto 0) := "1010";	
+	constant result_config : std_logic_vector(3 downto 0) := "1011";	
+
+	signal request_type : std_logic_vector(4 downto 0);
+	
+	signal zpu_di_use : std_logic_vector(31 downto 0);
+	
+	signal memORY_ACCESS : std_logic;
+
+	-- 1 cycle delay on memory read - needed to allow running at higher clock
+	signal zpu_di_next : std_logic_vector(31 downto 0);
+	signal zpu_di_reg : std_logic_vector(31 downto 0);
+	
+	signal memory_ready_next : std_logic;
+	signal memory_ready_reg : std_logic;
+	
+	signal zpu_enable : std_logic;
+	
+	signal zpu_addr_next : std_logic_vector(23 downto 0);
+	signal zpu_addr_reg : std_logic_vector(23 downto 0);
+	
+begin
+		-- register
+	process(clk,reset)
+	begin
+		if (reset='1') then
+			zpu_memory_fetch_pending_reg <= '0';
+			result_reg <= result_rom;
+			zpu_di_reg <= (others=>'0');
+			memory_ready_reg <= '0';
+			zpu_addr_reg <= (others=>'0');
+			ZPU_32BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_16BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_8BIT_WRITE_ENABLE_reg <= '0';	
+			ZPU_READ_reg <= '0';
+		elsif (clk'event and clk='1') then
+			zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
+			result_reg <= result_next;
+			zpu_di_reg <= zpu_di_next;
+			memory_ready_reg <= memORY_READY_next;
+			zpu_addr_reg <=zpu_addr_next;
+			ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
+			ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
+			ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
+			ZPU_READ_reg <= ZPU_READ_next;
+		end if;
+	end process;
+
+-- a little glue
+	process(zpu_ADDR_unsigned)
+	begin
+		block_mem <= '0';
+		config_mem <= '0';
+		-- $00000-$0FFFF = Own ROM/RAM
+		-- $10000-$1FFFF = Atari
+		-- $20000-$2FFFF = Config area
+		if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
+			block_mem <= zpu_addr_unsigned(17) nor zpu_addr_unsigned(16);
+			config_mem <= zpu_addr_unsigned(17);
+		end if;	
+	end process;
+
+	ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
+	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp
+			  )
+	begin
+		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+		result_next <= result_reg;
+		memory_ready_next <= memory_ready;
+		zpu_stACK_WRITE <= (others=>'0');
+		ZPU_config_write <= '0';
+		zpu_addr_next <= zpu_addr_reg;
+	
+		ZPU_MEM_BUSY <= pause;
+		
+		MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
+		
+		memory_fetch <= zpu_memory_fetch_pending_reg;
+		
+		zpu_read_next <= zpu_read_reg;
+		zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
+		zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
+		zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;	
+		
+		request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
+		case request_type is
+			when "00010"|"00110" =>
+				zpu_memory_fetch_pending_next <= '1';
+				result_next <= result_external;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+				zpu_read_next <= zpu_read_temp;
+				zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
+				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+			when "01010" =>
+				if (zpu_8bit_read_enable_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_rom_8bit_3;										
+					when "01" =>
+						result_next <= result_rom_8bit_2;
+					when "10" =>
+						result_next <= result_rom_8bit_1;										
+					when "11" =>
+						result_next <= result_rom_8bit_0;
+					end case;
+				else
+					result_next <= result_rom;
+				end if;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "01110" =>
+				if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_ram_8bit_3;										
+						ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
+					when "01" =>
+						result_next <= result_ram_8bit_2;
+						ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
+					when "10" =>
+						result_next <= result_ram_8bit_1;					
+						ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;					
+					when "11" =>
+						result_next <= result_ram_8bit_0;
+						ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
+					end case;
+				else
+					result_next <= result_ram;
+					ZPU_STACK_WRITE <= (others=>zpu_write_temp);					
+				end if;
+				ZPU_MEM_BUSY <= '1';				
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "10110"|"10010" =>
+				result_next <= result_config;
+				ZPU_MEM_BUSY <= '1';
+				ZPU_config_write <= ZPU_WRITE_temp; 
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);				
+			when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
+				  "10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111" =>
+				ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
+				zpu_memory_fetch_pending_next <= not(memORY_READY);
+			when others =>
+				-- keep
+		end case;
+	end process;
+
+	zpu_di_next <= zpu_di;
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
+	begin
+		zpu_di_use <= (others=>'0');
+		case result_reg is 
+			when result_external =>
+				zpu_di_use <= zpu_di_reg;
+			when result_rom =>
+				zpu_di_use <= zpu_rom_DI;
+			when result_rom_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
+			when result_rom_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
+			when result_rom_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
+			when result_rom_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);				
+			when result_ram =>
+				zpu_di_use <= zpu_ram_DI;
+			when result_ram_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
+			when result_ram_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
+			when result_ram_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+			when result_ram_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
+			when result_config =>
+				zpu_di_use <= zpu_config_di;
+			when others =>
+				-- nothing
+		end case;
+	end process;
+
+-- zpu itself
+	--zpu_enable <= enable and not(pause);
+	zpu_enable <= '1'; -- does nothing useful...
+	
+myzpu: ZPUMediumCore
+	port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
+	data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
+	byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
+	
+	zpu_di_unsigned <= unsigned(zpu_di_use);
+	zpu_do <= std_logic_vector(zpu_do_unsigned);
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_FETCH <= zpu_addr_reg;
+		
+	zpu_read_enable <= zpu_read_reg;
+	zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
+	zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
+	zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
+
+end sticky;
Index: unmerged/core/mcc216/zpu_rom.cmp
===================================================================
--- unmerged/core/mcc216/zpu_rom.cmp	(nonexistent)
+++ unmerged/core/mcc216/zpu_rom.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component zpu_rom
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/CHANGELOG
===================================================================
--- unmerged/core/mist/CHANGELOG	(nonexistent)
+++ unmerged/core/mist/CHANGELOG	(revision 1)
@@ -0,0 +1,3 @@
+Version 1
+---------
+Initial source release
Index: unmerged/core/mist/address_decoder.vhdl.bak
===================================================================
--- unmerged/core/mist/address_decoder.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/address_decoder.vhdl.bak	(revision 1)
@@ -0,0 +1,658 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+ENTITY address_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	-- bus masters - either CPU or antic
+	-- antic has priority and is slected when ANTIC_FETCH high
+	CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	CPU_FETCH : in std_logic;
+	CPU_WRITE_N : IN STD_LOGIC;
+	CPU_WRITE_DATA : in std_logic_vector(7 downto 0);	
+	
+	ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	ANTIC_FETCH : IN STD_LOGIC;
+	antic_refresh : in std_logic; -- use for sdram refresh (sdram needs more, but this is a start)
+
+	ZPU_ADDR : in std_logic_vector(23 downto 0);	
+	ZPU_FETCH : in std_logic;
+	ZPU_READ_ENABLE : in std_logic;
+	ZPU_32BIT_WRITE_ENABLE : in std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : in std_logic; -- for sram
+	ZPU_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs	
+	ZPU_WRITE_DATA : in std_logic_vector(31 downto 0);
+	
+	-- sources of data
+	ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	-- flash rom
+	GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
+	CART_ROM_DATA : in std_logic_Vector(7 downto 0);
+	
+	-- completion flags
+	RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+	ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+	CART_REQUEST_COMPLETE : IN STD_LOGIC;
+	
+	-- configuration options	
+	PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	reset_n : in std_logic;
+	
+	rom_select : in std_logic_vector(1 downto 0);
+	
+	ram_select : in std_logic_vector(1 downto 0);
+	
+	CART_RD4 : in std_logic;
+	CART_RD5 : in std_logic;
+	
+	use_sdram : in std_logic;
+		
+	-- Memory read mux output
+	MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
+	
+	-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
+	-- Allow us to say we're not ready for a cycle
+	MEMORY_READY_ANTIC : OUT STD_LOGIC;
+	MEMORY_READY_ZPU : OUT STD_LOGIC;
+	MEMORY_READY_CPU : out std_logic;	
+	
+	-- Each chip does not have whole address bus, so several are addressed at once
+	-- For reads not an issue, but for writes we need to only write to a single place!
+		-- these all take 1 cycle, so fine to leave device selected in general
+	GTIA_WR_ENABLE : OUT STD_LOGIC;
+	POKEY_WR_ENABLE : OUT STD_LOGIC;
+	POKEY2_WR_ENABLE : OUT STD_LOGIC;
+	ANTIC_WR_ENABLE : OUT STD_LOGIC;
+	PIA_WR_ENABLE : OUT STD_LOGIC;
+	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+	RAM_WR_ENABLE : OUT STD_LOGIC;	
+	PBI_WR_ENABLE : OUT STD_LOGIC;
+	
+	-- ROM and RAM have extended address busses to allow for bank switching etc.
+	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+	PBI_ADDR : out  std_logic_vector(15 downto 0);
+	
+	RAM_REQUEST : out std_logic;
+	ROM_REQUEST : out std_logic;
+	CART_REQUEST : out std_logic;
+	
+	CART_S4_n : out std_logic;
+	CART_S5_n : out std_logic;
+	CART_CCTL_n : out std_logic;
+	
+	-- width of access
+	WIDTH_8bit_ACCESS : out std_logic;
+	WIDTH_16bit_ACCESS : out std_logic;
+	WIDTH_32bit_ACCESS : out std_logic;
+	
+		-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+	SDRAM_WRITE_EN : out std_logic;
+	SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+	SDRAM_REFRESH : out std_logic;
+
+	SDRAM_REPLY : in std_logic; -- This matches the request once complete
+	SDRAM_DATA : in std_logic_vector(31 downto 0);
+	
+	WRITE_DATA : out std_logic_vector(31 downto 0)
+);
+
+END address_decoder;
+
+ARCHITECTURE vhdl OF address_decoder IS
+	signal ADDR_next : std_logic_vector(23 downto 0);
+	signal ADDR_reg : std_logic_vector(23 downto 0);
+
+	signal DATA_WRITE_next : std_logic_vector(31 downto 0);
+	signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
+	
+	signal width_8bit_next : std_logic;
+	signal width_16bit_next : std_logic;
+	signal width_32bit_next : std_logic;
+	signal write_enable_next : std_logic;
+
+	signal width_8bit_reg : std_logic;
+	signal width_16bit_reg : std_logic;
+	signal width_32bit_reg : std_logic;
+	signal write_enable_reg : std_logic;
+	
+	signal request_complete : std_logic;
+	signal notify_antic : std_logic;
+	signal notify_zpu : std_logic;
+	signal notify_cpu : std_logic;
+	signal start_request : std_logic;
+	
+	signal extended_access_cpu_or_antic : std_logic;
+	signal extended_access_antic : std_logic;
+	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+	
+	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+
+	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_idle : std_logic_vector(1 downto 0) := "00";
+	constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
+	constant state_waiting_zpu : std_logic_vector(1 downto 0) := "10";
+	constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
+		
+	signal ram_chip_select : std_logic;
+	signal sdram_chip_select : std_logic;
+	
+	signal sdram_request_next : std_logic;
+	signal sdram_request_reg : std_logic;
+	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+	
+	signal fetch_priority : std_logic_vector(2 downto 0);
+	
+BEGIN
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			addr_reg <= (others=>'0');
+			state_reg <= state_idle;
+			width_8bit_reg <= '0';
+			width_16bit_reg <= '0';
+			width_32bit_reg <= '0';
+			write_enable_reg <= '0';
+			data_write_reg <= (others=> '0');
+			sdram_request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			addr_reg <= addr_next;
+			state_reg <= state_next;
+			width_8bit_reg <= width_8bit_next;
+			width_16bit_reg <= width_16bit_next;
+			width_32bit_reg <= width_32bit_next;
+			write_enable_reg <= write_enable_next;
+			data_write_reg <= data_WRITE_next;
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+	
+	-- ANTIC FETCH
+	
+	-- concept
+	-- bus master sends request - antic or cpu
+	-- antic has priority
+	-- cpu may be idle
+	-- once request complete MEMORY_READY is set
+	-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
+	
+	-- so
+	-- memory_ready <= device_ready;
+	
+	-- problem
+	-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
+	
+	-- state machine
+	
+	-- state machine impl
+	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+	process(state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
+	begin
+		start_request <= '0';
+		notify_antic <= '0';
+		notify_cpu <= '0';
+		notify_zpu <= '0';
+		state_next <= state_reg;
+
+		addr_next <= addr_reg;
+		data_WRITE_next <= data_WRITE_reg;
+		width_8bit_next <= width_8bit_reg;		
+		width_16bit_next <= width_16bit_reg;		
+		width_32bit_next <= width_32bit_reg;		
+		write_enable_next <= write_enable_reg;
+		
+		case state_reg is
+			when state_idle =>
+				write_enable_next <= '0';
+				width_8bit_next <= '0';
+				width_16bit_next <= '0';
+				width_32bit_next <= '0';	
+				data_WRITE_next <= (others => '0');
+				addr_next <= zpu_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);				
+				
+				case fetch_priority is
+				when "100"|"101"|"110"|"111" => -- antic wins
+					start_request <= '1';
+					addr_next <= "00000000"&antic_ADDR;
+					width_8bit_next <= '1';					
+					if (request_complete = '1') then
+						notify_antic <= '1';
+					else
+						state_next <= state_waiting_antic;
+					end if;
+				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+					start_request <= '1';
+					addr_next <= zpu_ADDR;
+					data_WRITE_next <= zpu_wRITE_DATA;
+
+					width_8bit_next <= zpu_8BIT_WRITE_ENABLE;
+					width_16bit_next <= zpu_16BIT_WRITE_ENABLE;
+					width_32bit_next <= zpu_32BIT_WRITE_ENABLE or zpu_READ_ENABLE; -- narrower devices just return 8 bits on read
+					
+					write_enable_next <= not(zpu_READ_ENABLE);
+					
+					if (request_complete = '1') then
+						notify_zpu <= '1';
+					else
+						state_next <= state_waiting_zpu;
+					end if;					
+				when "001" => -- 6502 wins
+					start_request <= '1';
+					addr_next <= "00000000"&cpu_ADDR;
+					data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
+					width_8bit_next <= '1';
+					write_enable_next <= not(cpu_WRITE_N);
+					if (request_complete = '1') then
+						notify_cpu <= '1';
+					else
+						state_next <= state_waiting_cpu;
+					end if;
+				when "000" =>
+					-- no requests
+				end case;
+			when state_waiting_antic =>
+				if (request_complete = '1') then
+					notify_antic <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_zpu =>
+				if (request_complete = '1') then
+					notify_zpu <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_cpu =>
+				if (request_complete = '1') then
+					notify_cpu <= '1';
+					state_next <= state_idle;
+				end if;				
+		end case;
+	end process;
+	
+	-- output
+	MEMORY_READY_ANTIC <= notify_antic;
+	MEMORY_READY_ZPU <= notify_zpu;
+	MEMORY_READY_CPU <= notify_cpu;
+	
+	RAM_REQUEST <= ram_chip_select;
+		
+	SDRAM_REQUEST <= sdram_request_next;
+	SDRAM_REFRESH <= '0'; -- TODO, BROKEN! antic_refresh;
+	SDRAM_READ_EN <= not(write_enable_next);
+	SDRAM_WRITE_EN <= write_enable_next;
+	
+	WIDTH_8bit_ACCESS <= width_8bit_next;
+	WIDTH_16bit_ACCESS <= width_16bit_next;
+	WIDTH_32bit_ACCESS <= width_32bit_next;	
+	
+	WRITE_DATA <= DATA_WRITE_next;
+
+	-- a little sdram glue - move to sdram wrapper? TODO
+	SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+	sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+	
+	-- Calculate which memory area to use
+	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+	extended_access_antic <= (antic_fetch and not(portb(5)));
+	extended_access_cpu <= not(antic_fetch) and not(portb(4));
+	
+	extended_access_either <= not(portb(4));
+	
+  	process(
+		-- address and writing absolutely points us at a device
+		ADDR_next,WRITE_enable_next, 
+	
+		-- except for these additional special address bits	
+		portb, 
+		antic_fetch,
+		rom_select,
+		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
+		use_sdram,
+		
+		-- input data from n sources
+		GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
+		
+		-- input data from n sources complete?
+		-- hardware regs take 1 cycle, so always complete		
+		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+		
+		-- on new access this is set - we must select the appropriate device - for this cycle only
+		start_request
+	)
+	begin
+		MEMORY_DATA <= (others => '1');
+		
+		ROM_ADDR <= (others=>'0');
+		RAM_ADDR <= addr_next(18 downto 0);
+		SDRAM_ADDR <= addr_next(22 downto 0);
+		
+		PBI_ADDR <= ADDR_next(15 downto 0);
+		
+		request_complete <= '0';
+		
+		GTIA_WR_ENABLE <= '0';
+		POKEY_WR_ENABLE <= '0';
+		POKEY2_WR_ENABLE <= '0';
+		ANTIC_WR_ENABLE <= '0';
+		PIA_WR_ENABLE <= '0';
+		PIA_RD_ENABLE <= '0';
+		PBI_WR_ENABLE <= '0';
+
+		RAM_WR_ENABLE <= write_enable_next;
+		SDRAM_WRITE_EN <= write_enable_next;		
+		
+		CART_S4_n <= '1';
+		CART_S5_n <= '1';
+		CART_CCTL_n <= '1';
+		
+		rom_request <= '0';
+		cart_request <= '0';
+		
+		ram_chip_select <= '0';
+		sdram_chip_select <= '0';
+
+	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+		if (or_reduce(addr_next(23 downto 17)) = '0' ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+
+		RAM_ADDR(18 downto 16) <= "000";	
+		SDRAM_ADDR(22 downto 16) <= "0000000";
+	
+		case addr_next(15 downto 8) is 
+				-- GTIA
+				when X"D0" =>
+					GTIA_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+					request_complete <= '1';
+			
+				-- POKEY
+				when X"D2" =>				
+					if (addr_next(4) = '0') then
+						POKEY_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY_DATA;					
+					else
+						POKEY2_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
+					end if;
+					request_complete <= '1';
+
+				-- PIA
+				when X"D3" =>
+					PIA_WR_ENABLE <= write_enable_next;
+					PIA_RD_ENABLE <= '1';
+					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+					request_complete <= '1';
+					
+				-- ANTIC
+				when X"D4" =>
+					ANTIC_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+					request_complete <= '1';
+					
+				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+				when X"D5" =>
+					if ((CART_RD4 or CART_RD5) = '1') then
+						PBI_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_CCTL_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						MEMORY_DATA(7 downto 0) <= X"FF";
+						request_complete <= '1';
+					end if;
+					
+				-- XE RAM
+				when 
+					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+					
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+					
+					case ram_select is
+						when "00" => -- 64k
+							-- default
+						when "01" => -- 128k					
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+						when "10" => -- 320k compy shop
+							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+						when "11" => -- 320k rambo
+							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+					end case;
+					
+				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+				when 
+					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+									
+					if (portb(7) = '0' and portb(0) = '1') then
+						request_complete <= ROM_REQUEST_COMPLETE;
+						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						rom_request <= start_request;					
+						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+						end case;														
+					else				
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+						
+						case ram_select is
+							when "00" => -- 64k
+								-- default
+							when "01" => -- 128k					
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+							when "10" => -- 320k compy shop
+								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+							when "11" => -- 320k rambo
+								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+						end case;
+					end if;
+				
+				-- 0x80 cart
+				when
+					X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
+					|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
+		
+					if (cart_rd4 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						rom_request <= start_request;
+						CART_S4_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;	
+			
+				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+				when 
+					X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
+					|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
+					
+					if (cart_rd5 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_S5_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						if (portb(1) = '0') then
+							request_complete <= ROM_REQUEST_COMPLETE;
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;
+							rom_request <= start_request;
+							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+						else
+							if (use_sdram = '1') then
+								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+								sdram_chip_select <= start_request;
+								request_complete <= sdram_request_COMPLETE;														
+							else
+								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+								ram_chip_select <= start_request;
+								request_complete <= ram_request_COMPLETE;									
+							end if;
+						end if;
+					end if;
+					
+				-- OS ROM 0xc00->0xcff				
+				-- OS ROM d800->0xfff
+				when 
+					X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
+					|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
+					|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
+					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+					
+					if (portb(0) = '1') then
+						request_complete <= ROM_REQUEST_COMPLETE;
+						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						rom_request <= start_request;
+						case rom_select is
+							when "00" =>
+								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+							when "01" =>
+								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+							when "10" =>
+								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+							when "11" =>
+								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+						end case;
+								
+					else
+						if (use_sdram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							sdram_chip_select <= start_request;
+							request_complete <= sdram_request_COMPLETE;														
+						else
+							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+							ram_chip_select <= start_request;
+							request_complete <= ram_request_COMPLETE;									
+						end if;
+					end if;
+					
+				when others =>
+					if (use_sdram = '1') then
+						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						sdram_chip_select <= start_request;
+						request_complete <= sdram_request_COMPLETE;														
+					else
+						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+						ram_chip_select <= start_request;
+						request_complete <= ram_request_COMPLETE;									
+					end if;
+			end case;				
+		else		
+			case addr_next(23 downto 21) is			
+				when "000" =>				
+					-- internal area for zpu, never happens!
+				when "001" => -- sram, 512K
+					MEMORY_DATA(15 downto 0) <= RAM_DATA;
+					ram_chip_select <= start_request;
+					request_complete <= ram_request_COMPLETE;									
+					RAM_ADDR <= addr_next(18 downto 0);
+
+				when "010"|"011" => -- flash rom, 4MB
+					request_complete <= ROM_REQUEST_COMPLETE;
+					MEMORY_DATA(7 downto 0) <= ROM_DATA;
+					rom_request <= start_request;
+					ROM_ADDR <= addr_next(21 downto 0);
+					
+				when "100"|"101"|"110"|"111" => -- sdram, 8MB
+					MEMORY_DATA <= SDRAM_DATA;
+					sdram_chip_select <= start_request;
+					request_complete <= sdram_request_COMPLETE;	
+					SDRAM_ADDR <= addr_next(22 downto 0);				
+			end case;
+		end if;
+		
+--		case addr_next(15 downto 0) is
+--			when X"FFFC" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"FFFD" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0600" => --JSR 0610
+--				MEMORY_DATA(7 downto 0) <= X"20";
+--			when X"0601" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0602" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0603" => --JMP
+--				MEMORY_DATA(7 downto 0) <= X"4C";
+--			when X"0604" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"0605" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
+--				MEMORY_DATA(7 downto 0) <= X"AD";
+--			when X"0611" =>
+--				MEMORY_DATA(7 downto 0) <= X"0A";
+--			when X"0612" =>
+--				MEMORY_DATA(7 downto 0) <= X"D2";
+--			when X"0613" =>
+--				MEMORY_DATA(7 downto 0) <= X"85";
+--			when X"0614" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0615" =>
+--				MEMORY_DATA(7 downto 0) <= X"44";
+--			when X"0616" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0617" =>
+--				MEMORY_DATA(7 downto 0) <= X"60";
+--			when others =>
+--		end case;
+			
+	end process;
+END vhdl;
Index: unmerged/core/mcc216/zpu/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/core/mcc216/zpu/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/core/mcc216/zpu/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,4044 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b80f5;
+00a2 : d0738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
+00a9 : ff040000;
+00aa : 00000000;
+00ab : 00000000;
+00ac : 00000000;
+00ad : 00000000;
+00ae : 00000000;
+00af : 00000000;
+00b0 : 0b0b0b88;
+00b1 : d8040000;
+00b2 : 00000000;
+00b3 : 00000000;
+00b4 : 00000000;
+00b5 : 00000000;
+00b6 : 00000000;
+00b7 : 00000000;
+00b8 : 72097081;
+00b9 : 0509060a;
+00ba : 8106ff05;
+00bb : 70547106;
+00bc : 73097274;
+00bd : 05ff0506;
+00be : 07515151;
+00bf : 04000000;
+00c0 : 72097081;
+00c1 : 0509060a;
+00c2 : 098106ff;
+00c3 : 05705471;
+00c4 : 06730972;
+00c5 : 7405ff05;
+00c6 : 06075151;
+00c7 : 51040000;
+00c8 : 05ff0504;
+00c9 : 00000000;
+00ca : 00000000;
+00cb : 00000000;
+00cc : 00000000;
+00cd : 00000000;
+00ce : 00000000;
+00cf : 00000000;
+00d0 : 810b80fb;
+00d1 : ac0c5104;
+00d2 : 00000000;
+00d3 : 00000000;
+00d4 : 00000000;
+00d5 : 00000000;
+00d6 : 00000000;
+00d7 : 00007181;
+00d8 : 05520400;
+00d9 : 00000000;
+00da : 00000000;
+00db : 00000000;
+00dc : 00000000;
+00dd : 00000000;
+00de : 00000000;
+00df : 00000000;
+00e0 : 00000000;
+00e1 : 00000000;
+00e2 : 00000000;
+00e3 : 00000000;
+00e4 : 00000000;
+00e5 : 00000000;
+00e6 : 00000000;
+00e7 : 00000284;
+00e8 : 05721010;
+00e9 : 05520400;
+00ea : 00000000;
+00eb : 00000000;
+00ec : 00000000;
+00ed : 00000000;
+00ee : 00000000;
+00ef : 00000000;
+00f0 : 00000000;
+00f1 : 00000000;
+00f2 : 00000000;
+00f3 : 00000000;
+00f4 : 00000000;
+00f5 : 00000000;
+00f6 : 00000000;
+00f7 : 00007171;
+00f8 : 05ff0571;
+00f9 : 5351020d;
+00fa : 04000000;
+00fb : 00000000;
+00fc : 00000000;
+00fd : 00000000;
+00fe : 00000000;
+00ff : 00000000;
+0100 : 10101010;
+0101 : 10101010;
+0102 : 10101010;
+0103 : 10101010;
+0104 : 10101010;
+0105 : 10101010;
+0106 : 10101010;
+0107 : 10101053;
+0108 : 51047381;
+0109 : ff067383;
+010a : 06098105;
+010b : 83051010;
+010c : 102b0772;
+010d : fc060c51;
+010e : 51043c04;
+010f : 72728072;
+0110 : 8106ff05;
+0111 : 09720605;
+0112 : 71105272;
+0113 : 0a100a53;
+0114 : 72ed3851;
+0115 : 51535104;
+0116 : 83e08008;
+0117 : 83e08408;
+0118 : 83e08808;
+0119 : 757580ef;
+011a : fe2d5050;
+011b : 83e08008;
+011c : 5683e088;
+011d : 0c83e084;
+011e : 0c83e080;
+011f : 0c510483;
+0120 : e0800883;
+0121 : e0840883;
+0122 : e0880875;
+0123 : 7580ee92;
+0124 : 2d505083;
+0125 : e0800856;
+0126 : 83e0880c;
+0127 : 83e0840c;
+0128 : 83e0800c;
+0129 : 51040000;
+012a : 800489aa;
+012b : 0489aa0b;
+012c : 80c1a404;
+012d : fd3d0d75;
+012e : b9297681;
+012f : 2a0580fd;
+0130 : fc085473;
+0131 : 0c853d0d;
+0132 : 04803d0d;
+0133 : 81ff5180;
+0134 : 0b83e0c8;
+0135 : 1234ff11;
+0136 : 5170f438;
+0137 : 823d0d04;
+0138 : fa3d0d78;
+0139 : 0b0b80f6;
+013a : a85383e2;
+013b : f4525680;
+013c : cdd13f80;
+013d : 5383e080;
+013e : 08732e8a;
+013f : 387283e0;
+0140 : 800c883d;
+0141 : 0d0483e0;
+0142 : 945283e2;
+0143 : f45180ce;
+0144 : c53f83e0;
+0145 : 800880d5;
+0146 : 3883e09d;
+0147 : 33537280;
+0148 : 2e80ca38;
+0149 : 83e09c33;
+014a : 70822a70;
+014b : 81065154;
+014c : 5472d338;
+014d : 73812a70;
+014e : 81065153;
+014f : 72c83873;
+0150 : 842a7081;
+0151 : 06515372;
+0152 : ffbc3875;
+0153 : 83e09d56;
+0154 : 54733375;
+0155 : 33585372;
+0156 : 772e0981;
+0157 : 06ffa738;
+0158 : 72802e93;
+0159 : 38811481;
+015a : 165654e5;
+015b : 39800b83;
+015c : e0800c88;
+015d : 3d0d0483;
+015e : e0940883;
+015f : e0800c88;
+0160 : 3d0d04fd;
+0161 : 3d0d800b;
+0162 : 80fdec08;
+0163 : 5353ff72;
+0164 : 0c80fdf0;
+0165 : 0873710c;
+0166 : 5284d851;
+0167 : fe963f88;
+0168 : 800a5380;
+0169 : 73708105;
+016a : 553472a8;
+016b : 800a2e09;
+016c : 8106f038;
+016d : 80fdec08;
+016e : 5485aad5;
+016f : aad5740c;
+0170 : 80fdf008;
+0171 : 5285aad5;
+0172 : aad5720c;
+0173 : 82800a53;
+0174 : 80737084;
+0175 : 05550c72;
+0176 : 81800a2e;
+0177 : 098106f0;
+0178 : 3880740c;
+0179 : ff720c84;
+017a : d851fdc8;
+017b : 3f853d0d;
+017c : 04fd3d0d;
+017d : 800b80fd;
+017e : ec085353;
+017f : ff87c3e1;
+0180 : f0720c80;
+0181 : fdf00873;
+0182 : 710c528c;
+0183 : 9ac051fd;
+0184 : a33f8880;
+0185 : 0a538073;
+0186 : 70810555;
+0187 : 34728184;
+0188 : 80802e09;
+0189 : 8106ef38;
+018a : 80fdec08;
+018b : 5485aad5;
+018c : aad5740c;
+018d : 80fdf008;
+018e : 5285aad5;
+018f : aad5720c;
+0190 : 82800a53;
+0191 : 80737084;
+0192 : 05550c72;
+0193 : 84848080;
+0194 : 2e098106;
+0195 : ef388074;
+0196 : 0cff87c3;
+0197 : e1f0720c;
+0198 : 8c9ac051;
+0199 : fcce3f85;
+019a : 3d0d04ff;
+019b : 3d0d80fe;
+019c : 80087008;
+019d : 52527381;
+019e : 2e8b3870;
+019f : 81800772;
+01a0 : 0c833d0d;
+01a1 : 0470feff;
+01a2 : 06720c83;
+01a3 : 3d0d04ff;
+01a4 : 3d0d80fe;
+01a5 : 80087008;
+01a6 : 5252738b;
+01a7 : 3870ffbf;
+01a8 : 06720c83;
+01a9 : 3d0d0470;
+01aa : 80c00772;
+01ab : 0c833d0d;
+01ac : 04ff0b83;
+01ad : e0b00c80;
+01ae : cee33f80;
+01af : d1e73f83;
+01b0 : e08008f3;
+01b1 : 3880d4ac;
+01b2 : 3f800b83;
+01b3 : e0800c04;
+01b4 : 803d0d70;
+01b5 : 83e0800c;
+01b6 : 823d0d04;
+01b7 : ff3d0d73;
+01b8 : 70335351;
+01b9 : 81113371;
+01ba : 34718112;
+01bb : 34833d0d;
+01bc : 04fb3d0d;
+01bd : 77028405;
+01be : a2052256;
+01bf : 56807071;
+01c0 : 55555271;
+01c1 : 7527ac38;
+01c2 : 75137033;
+01c3 : 70147081;
+01c4 : ff065551;
+01c5 : 51517174;
+01c6 : 27893881;
+01c7 : 127081ff;
+01c8 : 06535171;
+01c9 : 81147083;
+01ca : ffff0655;
+01cb : 52547473;
+01cc : 26d63871;
+01cd : 83e0800c;
+01ce : 873d0d04;
+01cf : f83d0d7a;
+01d0 : 57800b8a;
+01d1 : 3d238070;
+01d2 : 7183e2e4;
+01d3 : 0c0b0b80;
+01d4 : f6ac5357;
+01d5 : 5880dabf;
+01d6 : 3f765180;
+01d7 : dab93f0b;
+01d8 : 0b80faf4;
+01d9 : 5180daaf;
+01da : 3f765180;
+01db : c2f13f83;
+01dc : e0800878;
+01dd : 2e8f380b;
+01de : 0b80f6b8;
+01df : 5180da97;
+01e0 : 3f8a3d0d;
+01e1 : 040b0b80;
+01e2 : f6c05180;
+01e3 : da893f75;
+01e4 : 17703355;
+01e5 : 5573802e;
+01e6 : 80fd3873;
+01e7 : ae2e8638;
+01e8 : 811656eb;
+01e9 : 39800b81;
+01ea : 16335556;
+01eb : 7380d82e;
+01ec : 09810683;
+01ed : 38815673;
+01ee : 80f83270;
+01ef : 30708025;
+01f0 : 78075151;
+01f1 : 5473802e;
+01f2 : 80cd3880;
+01f3 : 0b821633;
+01f4 : 55567380;
+01f5 : c62e0981;
+01f6 : 06833881;
+01f7 : 567380e6;
+01f8 : 32703070;
+01f9 : 80257807;
+01fa : 51515473;
+01fb : 802ea838;
+01fc : 800b8316;
+01fd : 33555673;
+01fe : 80c42e09;
+01ff : 81068338;
+0200 : 81567380;
+0201 : e4327030;
+0202 : 70802578;
+0203 : 07515154;
+0204 : 73802e83;
+0205 : 38815880;
+0206 : 0b8a3d23;
+0207 : 8a3dfc05;
+0208 : 53905283;
+0209 : e2e85180;
+020a : c2f53f89;
+020b : 3d225574;
+020c : 902e8e38;
+020d : 0b0b80f6;
+020e : c45180d8;
+020f : da3ffec1;
+0210 : 3983e2e8;
+0211 : 51fd953f;
+0212 : 83e2ea51;
+0213 : fd8e3f83;
+0214 : e2ec51fd;
+0215 : 873f800b;
+0216 : 83e3880c;
+0217 : 77812e81;
+0218 : 8c3883e2;
+0219 : e83383e2;
+021a : e9337188;
+021b : 2b075556;
+021c : 7383ffff;
+021d : 2e82ce38;
+021e : 7385962e;
+021f : 8e380b0b;
+0220 : 80f6dc51;
+0221 : 80d8903f;
+0222 : fdf7390b;
+0223 : 0b80f6f0;
+0224 : 5180d883;
+0225 : 3f7483e3;
+0226 : 900c83e2;
+0227 : ec3383e2;
+0228 : ed337188;
+0229 : 2b075555;
+022a : 7381802e;
+022b : 81d33873;
+022c : 82802e84;
+022d : 81387381;
+022e : ff2681b8;
+022f : 380b0b80;
+0230 : f6f85180;
+0231 : d7d13f83;
+0232 : e2ea3383;
+0233 : e2eb3371;
+0234 : 882b0752;
+0235 : 5680d8ce;
+0236 : 3f0b0b80;
+0237 : f6fc5180;
+0238 : d7b53f81;
+0239 : 0b83e2e4;
+023a : 0c8a3d0d;
+023b : 040b0b80;
+023c : f7805180;
+023d : d7a13f80;
+023e : 0b83e390;
+023f : 0c820b83;
+0240 : e2e834ff;
+0241 : 960b83e2;
+0242 : e9347651;
+0243 : f7d23f83;
+0244 : e0800854;
+0245 : 800b83e0;
+0246 : 800824a9;
+0247 : 3873842c;
+0248 : 7083ffff;
+0249 : 0670882a;
+024a : 57515474;
+024b : 83e2ea34;
+024c : 7383e2eb;
+024d : 34800b83;
+024e : e2ec34ff;
+024f : 800b83e2;
+0250 : ed34fed6;
+0251 : 3983e080;
+0252 : 088f0570;
+0253 : 842c7083;
+0254 : ffff0670;
+0255 : 882a5851;
+0256 : 51547483;
+0257 : e2ea3473;
+0258 : 83e2eb34;
+0259 : 800b83e2;
+025a : ec34ff80;
+025b : 0b83e2ed;
+025c : 34fea739;
+025d : 0b0b80f7;
+025e : 885180d6;
+025f : 9a3ffc81;
+0260 : 3983e2ea;
+0261 : 3383e2eb;
+0262 : 3371882b;
+0263 : 075558ad;
+0264 : 80742781;
+0265 : f2380b0b;
+0266 : 80f79851;
+0267 : 80d5f83f;
+0268 : 83e2ea33;
+0269 : 83e2eb33;
+026a : 71882b07;
+026b : 525680d6;
+026c : f53f0b0b;
+026d : 80f6fc51;
+026e : 80d5dc3f;
+026f : 810b83e2;
+0270 : e40cfea5;
+0271 : 390b0b80;
+0272 : f79c5180;
+0273 : d5c93ffe;
+0274 : 800b83e3;
+0275 : 900c810b;
+0276 : 83e3880c;
+0277 : ff0b83e2;
+0278 : e834ff0b;
+0279 : 83e2e934;
+027a : 7651f5f4;
+027b : 3f83e080;
+027c : 0883e394;
+027d : 0c83e080;
+027e : 0854800b;
+027f : 83e08008;
+0280 : 2480d338;
+0281 : 73842c70;
+0282 : 83ffff06;
+0283 : 70882a57;
+0284 : 51547483;
+0285 : e2ea3473;
+0286 : 83e2eb34;
+0287 : 800b83e2;
+0288 : ec34ff80;
+0289 : 0b83e2ed;
+028a : 34805574;
+028b : 17547333;
+028c : 83e2d816;
+028d : 34811555;
+028e : 748c2efc;
+028f : dd387417;
+0290 : 54733383;
+0291 : e2d81634;
+0292 : 81155574;
+0293 : 8c2e0981;
+0294 : 06d938fc;
+0295 : c53983e0;
+0296 : 80088f05;
+0297 : 70842c70;
+0298 : 83ffff06;
+0299 : 70882a58;
+029a : 51515474;
+029b : 83e2ea34;
+029c : 7383e2eb;
+029d : 34800b83;
+029e : e2ec34ff;
+029f : 800b83e2;
+02a0 : ed348055;
+02a1 : ffa5390b;
+02a2 : 0b80f7a4;
+02a3 : 5180d487;
+02a4 : 3f83e2ea;
+02a5 : 3383e2eb;
+02a6 : 3371882b;
+02a7 : 07525680;
+02a8 : d5843f0b;
+02a9 : 0b80f6fc;
+02aa : 5180d3eb;
+02ab : 3f810b83;
+02ac : e2e40cfc;
+02ad : b4390b0b;
+02ae : 80f7a851;
+02af : 80d3d83f;
+02b0 : 83e2ea33;
+02b1 : 83e2eb33;
+02b2 : 71882b07;
+02b3 : 525680d4;
+02b4 : d53f0b0b;
+02b5 : 80f6fc51;
+02b6 : 80d3bc3f;
+02b7 : 810b83e2;
+02b8 : e40cfc85;
+02b9 : 39f73d0d;
+02ba : 7b5a8c9a;
+02bb : c051f3c4;
+02bc : 3f805780;
+02bd : d0f83f76;
+02be : 54800b86;
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+0ef8 : 00000000;
+0ef9 : 2d2d2d2d;
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+0efb : 2d2d2d2d;
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+0f39 : 00000000;
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+0f3b : 00000000;
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+0f3d : 00000000;
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+0f4d : 00000000;
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+0f50 : 00000000;
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+0f54 : 00000000;
+0f55 : 53746174;
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+0f6a : 00000000;
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+0f6c : 00000000;
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+0f97 : c9fff0ed;
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+0f99 : 07f08200;
+0f9a : 0001d20f;
+0f9b : 0001d400;
+0f9c : 0001d401;
+0f9d : 0001d409;
+0f9e : 0001d010;
+0f9f : 0001d301;
+0fa0 : 0001d300;
+0fa1 : 0001d20a;
+0fa2 : 0001d01b;
+0fa3 : 0001d018;
+0fa4 : 0001d017;
+0fa5 : 0001d01a;
+0fa6 : 0001d403;
+0fa7 : 0001d402;
+0fa8 : 0001d40e;
+0fa9 : 0004007c;
+0faa : 00040078;
+0fab : 00040074;
+0fac : 00040068;
+0fad : 00040060;
+0fae : 0004005c;
+0faf : 00040058;
+0fb0 : 00040054;
+0fb1 : 00040050;
+0fb2 : 0004004c;
+0fb3 : 00040048;
+0fb4 : 00040044;
+0fb5 : 00040040;
+0fb6 : 00040028;
+0fb7 : 00040024;
+0fb8 : 00040020;
+0fb9 : 0004001c;
+0fba : 00040018;
+0fbb : 00040014;
+0fbc : 00040010;
+0fbd : 0004000c;
+0fbe : 00040008;
+0fbf : 00040004;
+0fc0 : 00040000;
+END; 
Index: unmerged/core/mcc216/zpu/debug.h
===================================================================
--- unmerged/core/mcc216/zpu/debug.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/debug.h	(revision 1)
@@ -0,0 +1,19 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/core/mcc216/zpu/led.h
===================================================================
--- unmerged/core/mcc216/zpu/led.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/core/mcc216/zpu/mmcconf.h
===================================================================
--- unmerged/core/mcc216/zpu/mmcconf.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/mmcconf.h	(revision 1)
@@ -0,0 +1,33 @@
+/*! \file mmcconf.h \brief MultiMedia and SD Flash Card Interface Configuration. */
+//*****************************************************************************
+//
+// File Name	: 'mmcconf.h'
+// Title		: MultiMedia and SD Flash Card Interface Configuration
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef MMCCONF_H
+#define MMCCONF_H
+
+#endif
Index: unmerged/core/mcc216/zpu/pff.h
===================================================================
--- unmerged/core/mcc216/zpu/pff.h	(nonexistent)
+++ unmerged/core/mcc216/zpu/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/core/mcc216/zpu/rom_prologue.vhd
===================================================================
--- unmerged/core/mcc216/zpu/rom_prologue.vhd	(nonexistent)
+++ unmerged/core/mcc216/zpu/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/core/mcc216/zpu/standalone_simple.ld
===================================================================
--- unmerged/core/mcc216/zpu/standalone_simple.ld	(nonexistent)
+++ unmerged/core/mcc216/zpu/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/core/mcc216/zpu/zpuromgen.c
===================================================================
--- unmerged/core/mcc216/zpu/zpuromgen.c	(nonexistent)
+++ unmerged/core/mcc216/zpu/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/core/mcc216/zpu_glue.vhdl
===================================================================
--- unmerged/core/mcc216/zpu_glue.vhdl	(nonexistent)
+++ unmerged/core/mcc216/zpu_glue.vhdl	(revision 1)
@@ -0,0 +1,344 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+library work;
+use work.zpupkg.all;
+
+ENTITY zpu_glue IS
+PORT 
+(
+	CLK : in std_logic;
+	RESET : in std_logic;
+	PAUSE : in std_logic;
+
+	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
+	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+	
+	ZPU_DO : out std_logic_vector(31 downto 0);
+	
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
+	
+	-- request
+	MEMORY_FETCH : out std_logic;
+	ZPU_READ_ENABLE : out std_logic;
+	ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
+	ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
+	
+	-- config
+	ZPU_CONFIG_WRITE : out std_logic;
+	
+	-- stack request
+	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+	
+	-- response
+	MEMORY_READY : in std_logic
+);
+END zpu_glue;
+
+architecture sticky of zpu_glue is
+component ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=24;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=16;  -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+	end component;	
+			
+	signal zpu_addr_unsigned : unsigned(23 downto 0);
+	signal zpu_do_unsigned : unsigned(31 downto 0);
+	signal ZPU_DI_unsigned : unsigned(31 downto 0);
+	signal zpu_break : std_logic;
+	signal zpu_debug : zpu_dbgo_t;
+	
+	signal zpu_mem_busy : std_logic;
+	
+	signal zpu_memory_fetch_pending_next : std_logic;
+	signal zpu_memory_fetch_pending_reg : std_logic;
+	
+	signal ZPU_32bit_READ_ENABLE_temp : std_logic;
+	signal ZPU_8bit_READ_ENABLE_temp : std_logic;	
+	signal ZPU_READ_temp : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;	
+	signal ZPU_WRITE_temp : std_logic;
+	
+	signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;	
+	signal ZPU_READ_next : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;	
+	signal ZPU_READ_reg : std_logic;
+	
+	signal block_mem : std_logic;
+	signal config_mem : std_logic;
+	signal special_mem : std_logic;
+	
+	signal result_next : std_logic_vector(3 downto 0);
+	signal result_reg : std_logic_vector(3 downto 0);
+	constant result_external : std_logic_vector(3 downto 0) := "0000";
+	constant result_ram : std_logic_vector(3 downto 0) := "0001";
+	constant result_ram_8bit_0 : std_logic_vector(3 downto 0) := "0010";
+	constant result_ram_8bit_1 : std_logic_vector(3 downto 0) := "0011";
+	constant result_ram_8bit_2 : std_logic_vector(3 downto 0) := "0100";
+	constant result_ram_8bit_3 : std_logic_vector(3 downto 0) := "0101";
+	constant result_rom : std_logic_vector(3 downto 0) := "0110";
+	constant result_rom_8bit_0 : std_logic_vector(3 downto 0) := "0111";
+	constant result_rom_8bit_1 : std_logic_vector(3 downto 0) := "1000";
+	constant result_rom_8bit_2 : std_logic_vector(3 downto 0) := "1001";
+	constant result_rom_8bit_3 : std_logic_vector(3 downto 0) := "1010";	
+	constant result_config : std_logic_vector(3 downto 0) := "1011";	
+	constant result_external_special : std_logic_vector(3 downto 0) := "1100";
+
+	signal request_type : std_logic_vector(4 downto 0);
+	
+	signal zpu_di_use : std_logic_vector(31 downto 0);
+	
+	signal memORY_ACCESS : std_logic;
+
+	-- 1 cycle delay on memory read - needed to allow running at higher clock
+	signal zpu_di_next : std_logic_vector(31 downto 0);
+	signal zpu_di_reg : std_logic_vector(31 downto 0);
+	
+	signal memory_ready_next : std_logic;
+	signal memory_ready_reg : std_logic;
+	
+	signal zpu_enable : std_logic;
+	
+	signal zpu_addr_next : std_logic_vector(23 downto 0);
+	signal zpu_addr_reg : std_logic_vector(23 downto 0);
+	
+begin
+		-- register
+	process(clk,reset)
+	begin
+		if (reset='1') then
+			zpu_memory_fetch_pending_reg <= '0';
+			result_reg <= result_rom;
+			zpu_di_reg <= (others=>'0');
+			memory_ready_reg <= '0';
+			zpu_addr_reg <= (others=>'0');
+			ZPU_32BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_16BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_8BIT_WRITE_ENABLE_reg <= '0';	
+			ZPU_READ_reg <= '0';
+		elsif (clk'event and clk='1') then
+			zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
+			result_reg <= result_next;
+			zpu_di_reg <= zpu_di_next;
+			memory_ready_reg <= memORY_READY_next;
+			zpu_addr_reg <=zpu_addr_next;
+			ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
+			ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
+			ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
+			ZPU_READ_reg <= ZPU_READ_next;
+		end if;
+	end process;
+
+-- a little glue
+	process(zpu_ADDR_unsigned)
+	begin
+		block_mem <= '0';
+		config_mem <= '0';
+		special_mem <= '0';
+		-- $00000-$0FFFF = Own ROM/RAM
+		-- $10000-$1FFFF = Atari
+		-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
+		-- $40000-$4FFFF = Config area
+		if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
+			block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
+			config_mem <= zpu_addr_unsigned(18);
+			special_mem <= zpu_addr_unsigned(17);
+		end if;	
+	end process;
+
+	ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
+	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp
+			  )
+	begin
+		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+		result_next <= result_reg;
+		memory_ready_next <= memory_ready;
+		zpu_stACK_WRITE <= (others=>'0');
+		ZPU_config_write <= '0';
+		zpu_addr_next <= zpu_addr_reg;
+	
+		ZPU_MEM_BUSY <= pause;
+		
+		MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
+		
+		memory_fetch <= zpu_memory_fetch_pending_reg;
+		
+		zpu_read_next <= zpu_read_reg;
+		zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
+		zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
+		zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;	
+		
+		request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
+		case request_type is
+			when "00010"|"00110" =>
+				zpu_memory_fetch_pending_next <= '1';
+				if (special_mem='0') then
+					result_next <= result_external;
+				else
+					result_next <= result_external_special;
+				end if;
+				
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+				zpu_read_next <= zpu_read_temp;
+				zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
+				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+			when "01010" =>
+				if (zpu_8bit_read_enable_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_rom_8bit_3;										
+					when "01" =>
+						result_next <= result_rom_8bit_2;
+					when "10" =>
+						result_next <= result_rom_8bit_1;										
+					when "11" =>
+						result_next <= result_rom_8bit_0;
+					end case;
+				else
+					result_next <= result_rom;
+				end if;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "01110" =>
+				if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_ram_8bit_3;										
+						ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
+					when "01" =>
+						result_next <= result_ram_8bit_2;
+						ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
+					when "10" =>
+						result_next <= result_ram_8bit_1;					
+						ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;					
+					when "11" =>
+						result_next <= result_ram_8bit_0;
+						ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
+					end case;
+				else
+					result_next <= result_ram;
+					ZPU_STACK_WRITE <= (others=>zpu_write_temp);					
+				end if;
+				ZPU_MEM_BUSY <= '1';				
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "10110"|"10010" =>
+				result_next <= result_config;
+				ZPU_MEM_BUSY <= '1';
+				ZPU_config_write <= ZPU_WRITE_temp; 
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);				
+			when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
+				  "10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111" =>
+				ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
+				zpu_memory_fetch_pending_next <= not(memORY_READY);
+			when others =>
+				-- keep
+		end case;
+	end process;
+
+	zpu_di_next <= zpu_di;
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
+	begin
+		zpu_di_use <= (others=>'0');
+		case result_reg is 
+			when result_external =>
+				zpu_di_use <= zpu_di_reg;
+			when result_external_special =>
+				zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);				
+			when result_rom =>
+				zpu_di_use <= zpu_rom_DI;
+			when result_rom_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
+			when result_rom_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
+			when result_rom_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
+			when result_rom_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);				
+			when result_ram =>
+				zpu_di_use <= zpu_ram_DI;
+			when result_ram_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
+			when result_ram_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
+			when result_ram_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+			when result_ram_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
+			when result_config =>
+				zpu_di_use <= zpu_config_di;
+			when others =>
+				-- nothing
+		end case;
+	end process;
+
+-- zpu itself
+	--zpu_enable <= enable and not(pause);
+	zpu_enable <= '1'; -- does nothing useful...
+	
+myzpu: ZPUMediumCore
+	port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
+	data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
+	byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
+	
+	zpu_di_unsigned <= unsigned(zpu_di_use);
+	zpu_do <= std_logic_vector(zpu_do_unsigned);
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_FETCH <= zpu_addr_reg;
+		
+	zpu_read_enable <= zpu_read_reg;
+	zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
+	zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
+	zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
+
+end sticky;
Index: unmerged/core/mcc216/zpu_ram.vhd
===================================================================
--- unmerged/core/mcc216/zpu_ram.vhd	(nonexistent)
+++ unmerged/core/mcc216/zpu_ram.vhd	(revision 1)
@@ -0,0 +1,181 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: zpu_ram.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY zpu_ram IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END zpu_ram;
+
+
+ARCHITECTURE SYN OF zpu_ram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 10,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		data_a => data,
+		wren_a => wren,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mcc216/zpupkg.vhd
===================================================================
--- unmerged/core/mcc216/zpupkg.vhd	(nonexistent)
+++ unmerged/core/mcc216/zpupkg.vhd	(revision 1)
@@ -0,0 +1,292 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Package                                                         ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the package.              ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      zpupkg, UART (Package)                             ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpupkg is
+   constant OPCODE_W : integer:=8;
+
+   -- Debug structure, currently only for the trace module
+   type zpu_dbgo_t is record
+      b_inst : std_logic;
+      opcode : unsigned(OPCODE_W-1 downto 0);
+      pc     : unsigned(31 downto 0);
+      sp     : unsigned(31 downto 0);
+      stk_a  : unsigned(31 downto 0);
+      stk_b  : unsigned(31 downto 0);
+   end record;
+
+   component Trace is
+      generic(
+         LOG_FILE   : string:="trace.txt"; -- Name of the trace file
+         ADDR_W     : integer:=16;  -- Address width
+         WORD_SIZE  : integer:=32); -- 16/32
+      port(
+         clk_i      : in std_logic;
+         dbg_i      : in zpu_dbgo_t;
+         stop_i     : in std_logic;
+         busy_i     : in std_logic
+         );
+   end component Trace;
+
+   component ZPUSmallCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'); -- Value used to fill the unsused bits
+      port(
+         clk_i        : in  std_logic; -- System Clock
+         reset_i      : in  std_logic; -- Synchronous Reset
+         interrupt_i  : in  std_logic; -- Interrupt
+         break_o      : out std_logic; -- Breakpoint opcode executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- BRAM (text, data, bss and stack)
+         a_we_o       : out std_logic; -- BRAM A port Write Enable
+         a_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+         a_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+         a_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+         b_we_o       : out std_logic; -- BRAM B port Write Enable
+         b_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+         b_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+         b_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+         -- Memory mapped I/O
+         mem_busy_i   : in  std_logic;
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0);
+         data_o       : out unsigned(WORD_SIZE-1 downto 0);
+         addr_o       : out unsigned(ADDR_W-1 downto 0);
+         write_en_o   : out std_logic;
+         read_en_o    : out std_logic);
+   end component ZPUSmallCore;
+
+   component ZPUMediumCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+         MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+         BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+         ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+         ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+         ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+         ENA_LSHR     : boolean:=true;  -- lshiftright
+         ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+         FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+      port(
+         clk_i        : in  std_logic; -- CPU Clock
+         reset_i      : in  std_logic; -- Sync Reset
+         enable_i     : in  std_logic; -- Hold the CPU (after reset)
+         break_o      : out std_logic; -- Break instruction executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- Memory interface
+         mem_busy_i   : in  std_logic; -- Memory is busy
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+         data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+         addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+         write_en_o   : out std_logic;  -- Memory write enable
+         read_en_o    : out std_logic); -- Memory read enable
+   end component ZPUMediumCore;
+
+   component Timer is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned(0 downto 0);
+         data_o   : out unsigned(31 downto 0));
+   end component Timer;
+
+   component gpio is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         --
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned( 0 downto 0);
+         data_o   : out unsigned(31 downto 0);
+         --
+         port_in  : in  std_logic_vector(31 downto 0);
+         port_out : out std_logic_vector(31 downto 0);
+         port_dir : out std_logic_vector(31 downto 0)
+         );
+   end component gpio;
+
+
+   component ZPUPhiIO is
+      generic(
+         BRDIVISOR : positive:=1;   -- Baud rate divisor i.e. br_clk/9600/4
+         ENA_LOG   : boolean:=true; -- Enable log
+         LOG_FILE  : string:="log.txt"); -- Name for the log file
+      port(
+         clk_i      : in  std_logic; -- System Clock
+         reset_i    : in  std_logic; -- Synchronous Reset
+         busy_o     : out std_logic; -- I/O is busy
+         we_i       : in  std_logic; -- Write Enable
+         re_i       : in  std_logic; -- Read Enable
+         data_i     : in  unsigned(31 downto 0);
+         data_o     : out unsigned(31 downto 0);
+         addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+         --
+         rs232_rx_i : in  std_logic;  -- UART Rx input
+         rs232_tx_o : out std_logic;  -- UART Tx output
+         br_clk_i   : in  std_logic;  -- UART base clock (enable)
+         --
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)
+         );
+   end component ZPUPhiIO;
+
+   -- Opcode decode constants
+   -- Note: these are the basic opcodes, always implemented using hardware.
+   constant OPCODE_IM        : unsigned(7 downto 7):="1";
+   constant OPCODE_STORESP   : unsigned(7 downto 5):="010";
+   constant OPCODE_LOADSP    : unsigned(7 downto 5):="011";
+   constant OPCODE_EMULATE   : unsigned(7 downto 5):="001";
+   constant OPCODE_ADDSP     : unsigned(7 downto 4):="0001";
+   constant OPCODE_SHORT     : unsigned(7 downto 4):="0000";
+   
+   constant OPCODE_BREAK     : unsigned(3 downto 0):="0000";
+   constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
+   constant OPCODE_PUSHSP    : unsigned(3 downto 0):="0010";
+   constant OPCODE_PUSHINT   : unsigned(3 downto 0):="0011";
+   
+   constant OPCODE_POPPC     : unsigned(3 downto 0):="0100";
+   constant OPCODE_ADD       : unsigned(3 downto 0):="0101";
+   constant OPCODE_AND       : unsigned(3 downto 0):="0110";
+   constant OPCODE_OR        : unsigned(3 downto 0):="0111";
+   
+   constant OPCODE_LOAD      : unsigned(3 downto 0):="1000";
+   constant OPCODE_NOT       : unsigned(3 downto 0):="1001";
+   constant OPCODE_FLIP      : unsigned(3 downto 0):="1010";
+   constant OPCODE_NOP       : unsigned(3 downto 0):="1011";
+   
+   constant OPCODE_STORE     : unsigned(3 downto 0):="1100";
+   constant OPCODE_POPSP     : unsigned(3 downto 0):="1101";
+   constant OPCODE_COMPARE   : unsigned(3 downto 0):="1110";
+   constant OPCODE_POPINT    : unsigned(3 downto 0):="1111";
+
+   -- The following instructions are emulated in the small version and
+   -- implemented as hardware in the full version.
+   -- The constants correpond to the "emulated" instruction number.
+
+   -- Enabled by the ENA_LEVEL0 generic:
+   constant OPCODE_EQ               : unsigned(5 downto 0):=to_unsigned(46,6);
+   constant OPCODE_LOADB            : unsigned(5 downto 0):=to_unsigned(51,6);
+   constant OPCODE_NEQBRANCH        : unsigned(5 downto 0):=to_unsigned(56,6);
+   constant OPCODE_PUSHSPADD        : unsigned(5 downto 0):=to_unsigned(61,6);
+   -- Enabled by the ENA_LEVEL1 generic:
+   constant OPCODE_LESSTHAN         : unsigned(5 downto 0):=to_unsigned(36,6);
+   constant OPCODE_ULESSTHAN        : unsigned(5 downto 0):=to_unsigned(38,6);
+   constant OPCODE_MULT             : unsigned(5 downto 0):=to_unsigned(41,6);
+   constant OPCODE_STOREB           : unsigned(5 downto 0):=to_unsigned(52,6);
+   constant OPCODE_CALLPCREL        : unsigned(5 downto 0):=to_unsigned(63,6);
+   constant OPCODE_SUB              : unsigned(5 downto 0):=to_unsigned(49,6);
+   -- Enabled by the ENA_LEVEL2 generic:
+   constant OPCODE_LESSTHANOREQUAL  : unsigned(5 downto 0):=to_unsigned(37,6);
+   constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
+   constant OPCODE_CALL             : unsigned(5 downto 0):=to_unsigned(45,6);
+   constant OPCODE_POPPCREL         : unsigned(5 downto 0):=to_unsigned(57,6);
+   -- Enabled by the ENA_LSHR generic:
+   constant OPCODE_LSHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(42,6);
+   -- The following opcodes are always emulated.
+   constant OPCODE_LOADH            : unsigned(5 downto 0):=to_unsigned(34,6);
+   constant OPCODE_STOREH           : unsigned(5 downto 0):=to_unsigned(35,6);
+   constant OPCODE_ASHIFTLEFT       : unsigned(5 downto 0):=to_unsigned(43,6);
+   constant OPCODE_ASHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(44,6);
+   constant OPCODE_NEQ              : unsigned(5 downto 0):=to_unsigned(47,6);
+   constant OPCODE_NEG              : unsigned(5 downto 0):=to_unsigned(48,6);
+   constant OPCODE_XOR              : unsigned(5 downto 0):=to_unsigned(50,6);
+   constant OPCODE_DIV              : unsigned(5 downto 0):=to_unsigned(53,6);
+   constant OPCODE_MOD              : unsigned(5 downto 0):=to_unsigned(54,6);
+   constant OPCODE_EQBRANCH         : unsigned(5 downto 0):=to_unsigned(55,6);
+   constant OPCODE_CONFIG           : unsigned(5 downto 0):=to_unsigned(58,6);
+   constant OPCODE_PUSHPC           : unsigned(5 downto 0):=to_unsigned(59,6);
+end package zpupkg;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package UART is
+   ----------------------
+   -- Very simple UART --
+   ----------------------
+   component RxUnit is
+      port(
+         clk_i    : in  std_logic;  -- System clock signal
+         reset_i  : in  std_logic;  -- Reset input (sync)
+         enable_i : in  std_logic;  -- Enable input (rate*4)
+         read_i   : in  std_logic;  -- Received Byte Read
+         rxd_i    : in  std_logic;  -- RS-232 data input
+         rxav_o   : out std_logic;  -- Byte available
+         datao_o  : out std_logic_vector(7 downto 0)); -- Byte received
+   end component RxUnit;
+
+   component TxUnit is
+     port (
+        clk_i    : in  std_logic;  -- Clock signal
+        reset_i  : in  std_logic;  -- Reset input
+        enable_i : in  std_logic;  -- Enable input
+        load_i   : in  std_logic;  -- Load input
+        txd_o    : out std_logic;  -- RS-232 data output
+        busy_o   : out std_logic;  -- Tx Busy
+        datai_i  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
+   end component TxUnit;
+
+   component BRGen is
+     generic(
+        COUNT : integer range 0 to 65535);-- Count revolution
+     port (
+        clk_i   : in  std_logic;  -- Clock
+        reset_i : in  std_logic;  -- Reset input
+        ce_i    : in  std_logic;  -- Chip Enable
+        o_o     : out std_logic); -- Output
+   end component BRGen;
+end package UART;
+
Index: unmerged/core/mist/address_decoder.vhdl
===================================================================
--- unmerged/core/mist/address_decoder.vhdl	(nonexistent)
+++ unmerged/core/mist/address_decoder.vhdl	(revision 1)
@@ -0,0 +1,766 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use IEEE.STD_LOGIC_MISC.all;
+
+
+ENTITY address_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	-- bus masters - either CPU or antic
+	-- antic has priority and is slected when ANTIC_FETCH high
+	CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	CPU_FETCH : in std_logic;
+	CPU_WRITE_N : IN STD_LOGIC;
+	CPU_WRITE_DATA : in std_logic_vector(7 downto 0);	
+	
+	ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+	ANTIC_FETCH : IN STD_LOGIC;
+	antic_refresh : in std_logic; -- use for sdram refresh (sdram needs more, but this is a start)
+
+	ZPU_ADDR : in std_logic_vector(23 downto 0);	
+	ZPU_FETCH : in std_logic;
+	ZPU_READ_ENABLE : in std_logic;
+	ZPU_32BIT_WRITE_ENABLE : in std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : in std_logic; -- for sram
+	ZPU_8BIT_WRITE_ENABLE : in std_logic; -- for hardware regs	
+	ZPU_WRITE_DATA : in std_logic_vector(31 downto 0);
+	
+	-- sources of data
+	ROM_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	-- flash rom
+	GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 downto 0);	
+	PIA_DATA : IN STD_LOGIC_VECTOR(7 downto 0);
+	RAM_DATA : IN STD_LOGIC_VECTOR(15 downto 0);
+	CART_ROM_DATA : in std_logic_Vector(7 downto 0);
+	
+	-- completion flags
+	RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+	ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+	CART_REQUEST_COMPLETE : IN STD_LOGIC;
+	
+	-- configuration options	
+	PORTB : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	reset_n : in std_logic;
+	
+	rom_select : in std_logic_vector(5 downto 0);
+	cart_select : in std_logic_vector(6 downto 0);
+	cart_activate : in std_logic;
+	
+	ram_select : in std_logic_vector(2 downto 0);
+	
+	CART_RD4 : in std_logic;
+	CART_RD5 : in std_logic;
+	
+	use_sdram : in std_logic;
+		
+	-- Memory read mux output
+	MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 downto 0);
+	
+	-- Flash and internal RAM take 2 cycles to access. SRAM takes 1 cycle.
+	-- Allow us to say we're not ready for a cycle
+	MEMORY_READY_ANTIC : OUT STD_LOGIC;
+	MEMORY_READY_ZPU : OUT STD_LOGIC;
+	MEMORY_READY_CPU : out std_logic;	
+	
+	-- Each chip does not have whole address bus, so several are addressed at once
+	-- For reads not an issue, but for writes we need to only write to a single place!
+		-- these all take 1 cycle, so fine to leave device selected in general
+	GTIA_WR_ENABLE : OUT STD_LOGIC;
+	POKEY_WR_ENABLE : OUT STD_LOGIC;
+	POKEY2_WR_ENABLE : OUT STD_LOGIC;
+	ANTIC_WR_ENABLE : OUT STD_LOGIC;
+	PIA_WR_ENABLE : OUT STD_LOGIC;
+	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+	RAM_WR_ENABLE : OUT STD_LOGIC;	
+	PBI_WR_ENABLE : OUT STD_LOGIC;
+	D6_WR_ENABLE : OUT STD_LOGIC;
+ 	
+	-- ROM and RAM have extended address busses to allow for bank switching etc.
+	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+	PBI_ADDR : out  std_logic_vector(15 downto 0);
+	
+	RAM_REQUEST : out std_logic;
+	ROM_REQUEST : out std_logic;
+	CART_REQUEST : out std_logic;
+	
+	CART_S4_n : out std_logic;
+	CART_S5_n : out std_logic;
+	CART_CCTL_n : out std_logic;
+	
+	-- width of access
+	WIDTH_8bit_ACCESS : out std_logic;
+	WIDTH_16bit_ACCESS : out std_logic;
+	WIDTH_32bit_ACCESS : out std_logic;
+	
+		-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	SDRAM_ADDR : out std_logic_vector(22 downto 0); -- 1 extra bit for byte alignment
+	SDRAM_READ_EN : out std_logic; -- if no reads pending may be a good time to do a refresh
+	SDRAM_WRITE_EN : out std_logic;
+	--SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+	SDRAM_REQUEST : out std_logic; -- Usual pattern
+	SDRAM_REFRESH : out std_logic;
+
+	--SDRAM_REPLY : in std_logic; -- This matches the request once complete
+	SDRAM_REQUEST_COMPLETE : in std_logic;
+	SDRAM_DATA : in std_logic_vector(31 downto 0);
+	
+	WRITE_DATA : out std_logic_vector(31 downto 0)
+);
+
+END address_decoder;
+
+ARCHITECTURE vhdl OF address_decoder IS
+	signal ADDR_next : std_logic_vector(23 downto 0);
+	signal ADDR_reg : std_logic_vector(23 downto 0);
+
+	signal DATA_WRITE_next : std_logic_vector(31 downto 0);
+	signal DATA_WRITE_reg : std_logic_vector(31 downto 0);
+	
+	signal width_8bit_next : std_logic;
+	signal width_16bit_next : std_logic;
+	signal width_32bit_next : std_logic;
+	signal write_enable_next : std_logic;
+
+	signal width_8bit_reg : std_logic;
+	signal width_16bit_reg : std_logic;
+	signal width_32bit_reg : std_logic;
+	signal write_enable_reg : std_logic;
+	
+	signal request_complete : std_logic;
+	signal notify_antic : std_logic;
+	signal notify_zpu : std_logic;
+	signal notify_cpu : std_logic;
+	signal start_request : std_logic;
+	
+	signal extended_access_addr : std_logic;
+	signal extended_access_cpu_or_antic : std_logic;
+	signal extended_access_antic : std_logic;
+	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+	
+	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+
+	signal extended_self_test : std_logic;
+	signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
+	
+	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_idle : std_logic_vector(1 downto 0) := "00";
+	constant state_waiting_cpu : std_logic_vector(1 downto 0) := "01";
+	constant state_waiting_zpu : std_logic_vector(1 downto 0) := "10";
+	constant state_waiting_antic : std_logic_vector(1 downto 0) := "11";
+		
+	signal ram_chip_select : std_logic;
+	signal sdram_chip_select : std_logic;
+	
+--	signal sdram_request_next : std_logic;
+--	signal sdram_request_reg : std_logic;
+--	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+	
+	signal fetch_priority : std_logic_vector(2 downto 0);
+	
+	signal fetch_wait_next : std_logic_vector(8 downto 0);
+	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
+	
+	signal rom_in_ram : std_logic;
+	
+	signal antic_fetch_real_next : std_logic;
+	signal antic_fetch_real_reg : std_logic;
+	signal cpu_fetch_real_next : std_logic;
+	signal cpu_fetch_real_reg : std_logic;
+
+	signal SDRAM_CART_ADDR   : std_logic_vector(22 downto 0);
+	signal SDRAM_BASIC_ROM_ADDR  : std_logic_vector(22 downto 0);
+	signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
+	
+	signal sdram_only_bank : std_logic;
+	
+BEGIN
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			addr_reg <= (others=>'0');
+			state_reg <= state_idle;
+			width_8bit_reg <= '0';
+			width_16bit_reg <= '0';
+			width_32bit_reg <= '0';
+			write_enable_reg <= '0';
+			data_write_reg <= (others=> '0');
+			--sdram_request_reg <= '0';
+			fetch_wait_reg <= (others=>'0');
+
+			cpu_fetch_real_reg <= '0';
+			antic_fetch_real_reg <= '0';	
+	elsif (clk'event and clk='1') then
+			addr_reg <= addr_next;
+			state_reg <= state_next;
+			width_8bit_reg <= width_8bit_next;
+			width_16bit_reg <= width_16bit_next;
+			width_32bit_reg <= width_32bit_next;
+			write_enable_reg <= write_enable_next;
+			data_write_reg <= data_WRITE_next;
+			--sdram_request_reg <= sdram_request_next;
+			fetch_wait_reg <= fetch_wait_next;
+			
+			cpu_fetch_real_reg <= cpu_fetch_real_next;
+			antic_fetch_real_reg <= antic_fetch_real_next;
+		end if;
+	end process;
+	
+	-- ANTIC FETCH
+	
+	-- concept
+	-- bus master sends request - antic or cpu
+	-- antic has priority
+	-- cpu may be idle
+	-- once request complete MEMORY_READY is set
+	-- if request interrupted then results are LOST - memory ready not set until priority request satisfied
+	
+	-- so
+	-- memory_ready <= device_ready;
+	
+	-- problem
+	-- request -> device access -> interrupt -> device finishes -> ignored? -> device access
+	
+	-- state machine
+	
+	-- state machine impl
+	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
+	begin
+		start_request <= '0';
+		notify_antic <= '0';
+		notify_cpu <= '0';
+		notify_zpu <= '0';
+		state_next <= state_reg;
+		fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1);
+
+		addr_next <= addr_reg;
+		data_WRITE_next <= data_WRITE_reg;
+		width_8bit_next <= width_8bit_reg;		
+		width_16bit_next <= width_16bit_reg;		
+		width_32bit_next <= width_32bit_reg;		
+		write_enable_next <= write_enable_reg;
+		
+		antic_fetch_real_next <= antic_fetch_real_reg;
+		cpu_fetch_real_next <= cpu_fetch_real_reg;
+		
+		case state_reg is
+			when state_idle =>
+				fetch_wait_next <= (others=>'0');
+				write_enable_next <= '0';
+				width_8bit_next <= '0';
+				width_16bit_next <= '0';
+				width_32bit_next <= '0';	
+				data_WRITE_next <= (others => '0');
+				addr_next <= zpu_ADDR(23 downto 16)&cpu_ADDR(15 downto 0);				
+				
+				case fetch_priority is
+				when "100"|"101"|"110"|"111" => -- antic wins
+					start_request <= '1';
+					addr_next <= "00000000"&antic_ADDR;
+					width_8bit_next <= '1';					
+					if (request_complete = '1') then
+						notify_antic <= '1';
+					else
+						state_next <= state_waiting_antic;
+					end if;
+					antic_fetch_real_next <= '1';
+				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+					start_request <= '1';
+					addr_next <= zpu_ADDR;
+					data_WRITE_next <= zpu_wRITE_DATA;
+
+					width_8bit_next <= zpu_8BIT_WRITE_ENABLE or (zpu_READ_ENABLE and (zpu_addr(0) or zpu_addr(1)));
+					width_16bit_next <= zpu_16BIT_WRITE_ENABLE;
+					width_32bit_next <= zpu_32BIT_WRITE_ENABLE or (zpu_READ_ENABLE and not(zpu_addr(0) or zpu_addr(1))); -- narrower devices just return 8 bits on read
+					
+					write_enable_next <= not(zpu_READ_ENABLE);
+					
+					if (request_complete = '1') then
+						notify_zpu <= '1';
+					else
+						state_next <= state_waiting_zpu;
+					end if;					
+				when "001" => -- 6502 wins
+					start_request <= '1';
+					addr_next <= "00000000"&cpu_ADDR;
+					data_WRITE_next(7 downto 0) <= cpu_WRITE_DATA;
+					width_8bit_next <= '1';
+					write_enable_next <= not(cpu_WRITE_N);
+					if (request_complete = '1') then
+						notify_cpu <= '1';
+					else
+						state_next <= state_waiting_cpu;
+					end if;
+					cpu_fetch_real_next <= '1';
+				when "000" =>
+					-- no requests
+				end case;
+			when state_waiting_antic =>
+				if (request_complete = '1') then
+					notify_antic <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_zpu =>
+				if (request_complete = '1') then
+					notify_zpu <= '1';
+					state_next <= state_idle;
+				end if;
+			when state_waiting_cpu =>
+				if (request_complete = '1') then
+					notify_cpu <= '1';
+					state_next <= state_idle;
+				end if;				
+		end case;
+	end process;
+	
+	-- output
+	MEMORY_READY_ANTIC <= notify_antic;
+	MEMORY_READY_ZPU <= notify_zpu;
+	MEMORY_READY_CPU <= notify_cpu;
+	
+	RAM_REQUEST <= ram_chip_select;
+		
+	SDRAM_REQUEST <= sdram_chip_select;
+	--SDRAM_REQUEST <= sdram_request_next;
+	SDRAM_REFRESH <= '0'; --fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+	SDRAM_READ_EN <= not(write_enable_next);
+	SDRAM_WRITE_EN <= write_enable_next;
+	
+	WIDTH_8bit_ACCESS <= width_8bit_next;
+	WIDTH_16bit_ACCESS <= width_16bit_next;
+	WIDTH_32bit_ACCESS <= width_32bit_next;	
+	
+	WRITE_DATA <= DATA_WRITE_next;
+
+	-- a little sdram glue - move to sdram wrapper? TODO
+	--SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+	
+	-- Calculate which memory area to use
+	extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
+	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+	extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
+	extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
+	extended_access_either <= extended_access_addr and not(portb(4));
+	sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
+	
+	process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
+	begin	
+		extended_bank <= "0000000"&addr_next(15 downto 14);
+		extended_self_test <= '1';
+		
+		case ram_select is
+			when "000" => -- 64k
+				-- default
+			when "001" => -- 128k			
+				if (extended_access_cpu_or_antic='1') then
+					extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
+				end if;
+			when "010" => -- 320k compy shop
+				if (extended_access_cpu_or_antic='1') then
+					extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
+					extended_self_test <= '0';
+				end if;
+			when "011" => -- 320k rambo
+				if (extended_access_either='1')then
+					extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
+				end if;
+			when "100" => -- 576k compy shop
+				if (extended_access_cpu_or_antic='1') then
+					extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
+					extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
+					extended_self_test <= '0';
+				end if;
+			when "101" => -- 576k rambo
+				if (extended_access_either='1') then
+					extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
+					extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
+				end if;
+			when "110" => -- 1088k rambo
+				if (extended_access_either='1') then
+					extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
+					extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
+					extended_self_test <= '0';
+				end if;
+			when "111" => -- 4MB!	
+				if (extended_access_addr='1') then
+					extended_bank(7 downto 0) <= portb(7 downto 0);				
+					extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
+					extended_self_test <= and_reduce(portb(6 downto 4));	 -- which means self-test is in the middle of half the banks - euuugh, oh well!						
+				end if;
+			when others =>
+				-- TODO - portc!
+		end case;
+	end process;
+
+	
+	-- SRAM memory map (512k)
+	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
+	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP)
+	-- SDRAM memory map (8MB)
+	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
+	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP) 
+	-- to 4MB RAM    - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
+	-- +64k          - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
+	-- SCRATCH       - 4MB+64k-5MB
+	-- CARTS         -              "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
+	SDRAM_CART_ADDR      <= "101"&cart_select& "0000000000000";
+	-- BASIC/OS ROM  -              "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K				
+	SDRAM_BASIC_ROM_ADDR <= "111"&"000000"   &"00000000000000";
+	SDRAM_OS_ROM_ADDR    <= "111"&rom_select &"00000000000000";
+	-- SYSTEM        -              "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
+	
+  	process(
+		-- address and writing absolutely points us at a device
+		ADDR_next,WRITE_enable_next, 
+	
+		-- except for these additional special address bits	
+		portb, 
+		antic_fetch,
+		rom_select,
+		ram_select,cart_rd4,cart_rd5,
+		use_sdram,
+		
+		-- input data from n sources
+		GTIA_DATA,POKEY_DATA,POKEY2_DATA,PIA_DATA,ANTIC_DATA,CART_ROM_DATA,ROM_DATA,RAM_DATA,SDRAM_DATA,
+		CACHE_GTIA_DATA,CACHE_POKEY_DATA,CACHE_POKEY2_DATA,CACHE_ANTIC_DATA,
+		
+		-- input data from n sources complete?
+		-- hardware regs take 1 cycle, so always complete		
+		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+		
+		-- on new access this is set - we must select the appropriate device - for this cycle only
+		start_request,
+		
+		rom_in_ram,
+		
+		-- SDRAM base addresses
+		extended_self_test,extended_bank,sdram_only_bank,
+		SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
+		
+	)
+	begin
+		MEMORY_DATA <= (others => '1');
+		
+		ROM_ADDR <= (others=>'0');
+		RAM_ADDR <= addr_next(18 downto 0);
+		SDRAM_ADDR <= addr_next(22 downto 0);
+		
+		PBI_ADDR <= ADDR_next(15 downto 0);
+		
+		request_complete <= '0';
+		
+		GTIA_WR_ENABLE <= '0';
+		POKEY_WR_ENABLE <= '0';
+		POKEY2_WR_ENABLE <= '0';
+		ANTIC_WR_ENABLE <= '0';
+		PIA_WR_ENABLE <= '0';
+		PIA_RD_ENABLE <= '0';
+		PBI_WR_ENABLE <= '0';
+		D6_WR_ENABLE <= '0';
+
+		RAM_WR_ENABLE <= write_enable_next;
+		SDRAM_WRITE_EN <= write_enable_next;		
+		
+		CART_S4_n <= '1';
+		CART_S5_n <= '1';
+		CART_CCTL_n <= '1';
+		
+		rom_request <= '0';
+		cart_request <= '0';
+		
+		ram_chip_select <= '0';
+		sdram_chip_select <= '0';
+		
+		rom_in_ram <= '1';
+
+	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+		if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+
+		SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
+		SDRAM_ADDR(22 downto 14) <= extended_bank;
+		RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
+		RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
+					
+		if ((use_sdram or sdram_only_bank)='1') then
+			MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+			sdram_chip_select <= start_request;
+			request_complete <= sdram_request_COMPLETE;														
+		else
+			MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+			ram_chip_select <= start_request;
+			request_complete <= ram_request_COMPLETE;									
+		end if;
+		
+		case addr_next(15 downto 8) is 
+				-- GTIA
+				when X"D0" =>
+					GTIA_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';
+			
+				-- POKEY
+				when X"D2" =>				
+					if (addr_next(4) = '0') then
+						POKEY_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY_DATA;
+					else
+						POKEY2_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= POKEY2_DATA;
+						MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
+					end if;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';					
+
+				-- PIA
+				when X"D3" =>
+					PIA_WR_ENABLE <= write_enable_next;
+					PIA_RD_ENABLE <= '1';
+					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';					
+					
+				-- ANTIC
+				when X"D4" =>
+					ANTIC_WR_ENABLE <= write_enable_next;
+					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+					MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
+					request_complete <= '1';
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';					
+					
+				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+				when X"D5" =>
+					sdram_chip_select <= '0';
+					ram_chip_select <= '0';				
+					if ((CART_RD4 or CART_RD5) = '1') then
+						PBI_WR_ENABLE <= write_enable_next;
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_CCTL_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+					else
+						MEMORY_DATA(7 downto 0) <= X"FF";
+						request_complete <= '1';
+					end if;
+					
+				when X"D6" =>
+					D6_WR_ENABLE <= write_enable_next;
+					-- TODO - should this still have RAM with covox here?
+										
+				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+				when 
+					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+									
+					if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';	
+						
+						if (rom_in_ram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						else
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+						end if;
+						
+						if (write_enable_next = '1') then
+							request_complete <= '1';
+						else
+							if (rom_in_ram = '1') then
+								request_complete <= sdram_request_COMPLETE;							
+								sdram_chip_select <= start_request;							
+							else
+								request_complete <= rom_request_COMPLETE;							
+								rom_request <= start_request;															
+							end if;
+						end if;
+						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
+						SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
+						ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k						
+					end if;
+				
+				-- 0x80 cart
+				when
+					X"80"|X"81"|X"82"|X"83"|X"84"|X"85"|X"86"|X"87"|X"88"|X"89"|X"8A"|X"8B"|X"8C"|X"8D"|X"8E"|X"8F"
+					|X"90"|X"91"|X"92"|X"93"|X"94"|X"95"|X"96"|X"97"|X"98"|X"99"|X"9A"|X"9B"|X"9C"|X"9D"|X"9E"|X"9F" =>
+		
+					if (cart_rd4 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						rom_request <= start_request;
+						CART_S4_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';							
+					end if;	
+			
+				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+				when 
+					X"A0"|X"A1"|X"A2"|X"A3"|X"A4"|X"A5"|X"A6"|X"A7"|X"A8"|X"A9"|X"AA"|X"AB"|X"AC"|X"AD"|X"AE"|X"AF"
+					|X"B0"|X"B1"|X"B2"|X"B3"|X"B4"|X"B5"|X"B6"|X"B7"|X"B8"|X"B9"|X"BA"|X"BB"|X"BC"|X"BD"|X"BE"|X"BF" =>
+					
+					if (cart_rd5 = '1') then
+						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+						cart_request <= start_request;
+						CART_S5_n <= '0';
+						request_complete <= CART_REQUEST_COMPLETE;
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';													
+					else
+						if (portb(1) = '0') then
+							sdram_chip_select <= '0';
+							ram_chip_select <= '0';							
+							--request_complete <= ROM_REQUEST_COMPLETE;
+							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+							--rom_request <= start_request;					
+							if (rom_in_ram = '1') then
+								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+							else
+								MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+							end if;
+							if (write_enable_next = '1') then
+								request_complete <= '1';
+							else
+								if (rom_in_ram = '1') then
+									request_complete <= sdram_request_COMPLETE;							
+									sdram_chip_select <= start_request;							
+								else
+									request_complete <= rom_request_COMPLETE;							
+									rom_request <= start_request;															
+								end if;
+							end if;
+						
+							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+						 SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
+						 SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k							
+						end if;
+					end if;
+					
+				-- OS ROM 0xc00->0xcff				
+				-- OS ROM d800->0xfff
+				when 
+					X"C0"|X"C1"|X"C2"|X"C3"|X"C4"|X"C5"|X"C6"|X"C7"|X"C8"|X"C9"|X"CA"|X"CB"|X"CC"|X"CD"|X"CE"|X"CF"
+					|X"D8"|X"D9"|X"DA"|X"DB"|X"DC"|X"DD"|X"DE"|X"DF"
+					|X"E0"|X"E1"|X"E2"|X"E3"|X"E4"|X"E5"|X"E6"|X"E7"|X"E8"|X"E9"|X"EA"|X"EB"|X"EC"|X"ED"|X"EE"|X"EF"
+					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+					
+					if (portb(0) = '1') then
+						sdram_chip_select <= '0';
+						ram_chip_select <= '0';																		
+						--request_complete <= ROM_REQUEST_COMPLETE;
+						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+						--rom_request <= start_request;					
+						if (rom_in_ram = '1') then
+							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+						else
+							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+						end if;
+						if (write_enable_next = '1') then
+							request_complete <= '1';
+						else
+								if (rom_in_ram = '1') then
+									request_complete <= sdram_request_COMPLETE;							
+									sdram_chip_select <= start_request;							
+								else
+									request_complete <= rom_request_COMPLETE;							
+									rom_request <= start_request;															
+								end if;						
+						end if;																			
+
+						ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
+						SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
+					end if;
+					
+				when others =>
+			end case;				
+		else		
+			sdram_chip_select <= '0';
+			ram_chip_select <= '0';													
+			case addr_next(23 downto 21) is			
+				when "000" =>				
+					-- internal area for zpu, never happens!
+				when "001" => -- sram, 512K
+					MEMORY_DATA(15 downto 0) <= RAM_DATA;
+					ram_chip_select <= start_request;
+					request_complete <= ram_request_COMPLETE;									
+					RAM_ADDR <= addr_next(18 downto 0);
+
+				when "010"|"011" => -- flash rom, 4MB
+					request_complete <= ROM_REQUEST_COMPLETE;
+					MEMORY_DATA(7 downto 0) <= ROM_DATA;
+					rom_request <= start_request;
+					ROM_ADDR <= addr_next(21 downto 0);
+					
+				when "100"|"101"|"110"|"111" => -- sdram, 8MB
+					MEMORY_DATA <= SDRAM_DATA;
+					sdram_chip_select <= start_request;
+					request_complete <= sdram_request_COMPLETE;	
+					SDRAM_ADDR <= addr_next(22 downto 0);				
+			end case;
+		end if;
+		
+--		case addr_next(15 downto 0) is
+--			when X"FFFC" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"FFFD" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0600" => --JSR 0610
+--				MEMORY_DATA(7 downto 0) <= X"20";
+--			when X"0601" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0602" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0603" => --JMP
+--				MEMORY_DATA(7 downto 0) <= X"4C";
+--			when X"0604" =>
+--				MEMORY_DATA(7 downto 0) <= X"00";
+--			when X"0605" =>
+--				MEMORY_DATA(7 downto 0) <= X"06";
+--			when X"0610" => --LDA RANDOM, STA 0x10, LDA 0x10, RTS
+--				MEMORY_DATA(7 downto 0) <= X"AD";
+--			when X"0611" =>
+--				MEMORY_DATA(7 downto 0) <= X"0A";
+--			when X"0612" =>
+--				MEMORY_DATA(7 downto 0) <= X"D2";
+--			when X"0613" =>
+--				MEMORY_DATA(7 downto 0) <= X"85";
+--			when X"0614" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0615" =>
+--				MEMORY_DATA(7 downto 0) <= X"44";
+--			when X"0616" =>
+--				MEMORY_DATA(7 downto 0) <= X"10";
+--			when X"0617" =>
+--				MEMORY_DATA(7 downto 0) <= X"60";
+--			when others =>
+--		end case;
+			
+	end process;
+END vhdl;
Index: unmerged/core/mist/antic_counter.vhdl
===================================================================
--- unmerged/core/mist/antic_counter.vhdl	(nonexistent)
+++ unmerged/core/mist/antic_counter.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY antic_counter IS
+generic
+(
+	STORE_WIDTH : natural := 1;
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+);
+END antic_counter;
+
+ARCHITECTURE vhdl OF antic_counter IS
+	signal value_next : std_logic_vector(STORE_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(STORE_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= value_reg(STORE_WIDTH-1 downto COUNT_WIDTH)&std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: unmerged/core/mist/atari800core.qsf
===================================================================
--- unmerged/core/mist/atari800core.qsf	(nonexistent)
+++ unmerged/core/mist/atari800core.qsf	(revision 1)
@@ -0,0 +1,634 @@
+# Copyright (C) 1991-2007 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+# The default values for assignments are stored in the file
+#		minimig_de1_assignment_defaults.qdf
+# If this file doesn't exist, and for assignments not listed, see file
+#		assignment_defaults.qdf
+
+# Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_22 -to CLOCK_50[0]
+set_location_assignment PIN_23 -to CLOCK_50[1]
+set_location_assignment PIN_128 -to CLOCK_32[0]
+set_location_assignment PIN_129 -to CLOCK_32[1]
+set_location_assignment PIN_54 -to CLOCK_27[0]
+set_location_assignment PIN_55 -to CLOCK_27[1]
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
+set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name TPD_REQUIREMENT "2 ns"
+set_global_assignment -name TSU_REQUIREMENT "2 ns"
+set_global_assignment -name TCO_REQUIREMENT "2 ns"
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
+set_global_assignment -name AUTO_RAM_RECOGNITION ON
+set_global_assignment -name AUTO_ROM_RECOGNITION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top
+set_global_assignment -name MISC_FILE atari800core.dpf
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
+
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF
+
+#set_parameter -name ENABLE_RUNTIME_MOD YES -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+#set_parameter -name INSTANCE_NAME mig -to "Minimig1:minimig|amiga_boot:BOOTROM1|altsyncram:Ram0_rtl_10"
+
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+
+
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
+
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
+
+
+set_global_assignment -name VHDL_FILE data_io.vhdl
+set_global_assignment -name QIP_FILE basic.qip
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name VERILOG_FILE hq_dac.v
+set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+set_global_assignment -name VHDL_FILE ramint.vhd
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name VHDL_FILE internalromram.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name QIP_FILE rom16.qip
+set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SPI_DI -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SPI_DO -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SPI_SS2 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "data_io:mist_spi_interface|SPI_CLK" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
+set_global_assignment -name QIP_FILE mist_sector_buffer.qip
+set_global_assignment -name VHDL_FILE covox.vhd
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to CONF_DATA0 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SPI_DI -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SPI_DO -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SPI_SS2 -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "data_io:mist_spi_interface|ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "data_io:mist_spi_interface|ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "data_io:mist_spi_interface|ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "data_io:mist_spi_interface|ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "data_io:mist_spi_interface|ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "data_io:mist_spi_interface|ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "data_io:mist_spi_interface|ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "data_io:mist_spi_interface|ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "data_io:mist_spi_interface|ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "data_io:mist_spi_interface|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "data_io:mist_spi_interface|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "data_io:mist_spi_interface|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "data_io:mist_spi_interface|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "data_io:mist_spi_interface|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "data_io:mist_spi_interface|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "data_io:mist_spi_interface|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "data_io:mist_spi_interface|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "data_io:mist_spi_interface|WR_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "data_io:mist_spi_interface|cmd_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "data_io:mist_spi_interface|cmd_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "data_io:mist_spi_interface|cmd_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "data_io:mist_spi_interface|cmd_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "data_io:mist_spi_interface|cmd_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "data_io:mist_spi_interface|cmd_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "data_io:mist_spi_interface|cmd_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "data_io:mist_spi_interface|cmd_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "data_io:mist_spi_interface|cnt_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "data_io:mist_spi_interface|cnt_reg[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "data_io:mist_spi_interface|cnt_reg[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "data_io:mist_spi_interface|cnt_reg[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "data_io:mist_spi_interface|cnt_reg[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "data_io:mist_spi_interface|cnt_reg[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "data_io:mist_spi_interface|cnt_reg[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "data_io:mist_spi_interface|cnt_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "data_io:mist_spi_interface|cnt_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "data_io:mist_spi_interface|cnt_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "data_io:mist_spi_interface|cnt_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "data_io:mist_spi_interface|cnt_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "data_io:mist_spi_interface|cnt_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "data_io:mist_spi_interface|cnt_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "data_io:mist_spi_interface|cnt_reg[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "data_io:mist_spi_interface|cnt_reg[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "data_io:mist_spi_interface|ready" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=2048" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=2048" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "data_io:mist_spi_interface|request" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "data_io:mist_spi_interface|sbuf_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "data_io:mist_spi_interface|sbuf_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "data_io:mist_spi_interface|sbuf_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "data_io:mist_spi_interface|sbuf_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "data_io:mist_spi_interface|sbuf_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "data_io:mist_spi_interface|sbuf_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "data_io:mist_spi_interface|sbuf_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "data_io:mist_spi_interface|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "data_io:mist_spi_interface|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "data_io:mist_spi_interface|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "data_io:mist_spi_interface|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "data_io:mist_spi_interface|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "data_io:mist_spi_interface|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "data_io:mist_spi_interface|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "data_io:mist_spi_interface|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "data_io:mist_spi_interface|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "data_io:mist_spi_interface|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "data_io:mist_spi_interface|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "data_io:mist_spi_interface|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "data_io:mist_spi_interface|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "data_io:mist_spi_interface|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "data_io:mist_spi_interface|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "data_io:mist_spi_interface|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "data_io:mist_spi_interface|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "data_io:mist_spi_interface|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "data_io:mist_spi_interface|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "data_io:mist_spi_interface|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "data_io:mist_spi_interface|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "data_io:mist_spi_interface|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "data_io:mist_spi_interface|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "data_io:mist_spi_interface|sector[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "pia:b2v_inst16|portb_output_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "pia:b2v_inst16|portb_output_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "pia:b2v_inst16|portb_output_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "pia:b2v_inst16|portb_output_reg[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "pia:b2v_inst16|portb_output_reg[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "pia:b2v_inst16|portb_output_reg[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "pia:b2v_inst16|portb_output_reg[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "pia:b2v_inst16|portb_output_reg[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "zpu_config_regs:b2v_inst24|sector[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "zpu_config_regs:b2v_inst24|sector[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "zpu_config_regs:b2v_inst24|sector[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "zpu_config_regs:b2v_inst24|sector[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "zpu_config_regs:b2v_inst24|sector[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "zpu_config_regs:b2v_inst24|sector[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "zpu_config_regs:b2v_inst24|sector[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "zpu_config_regs:b2v_inst24|sector[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "zpu_config_regs:b2v_inst24|sector[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "zpu_config_regs:b2v_inst24|sector[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "zpu_config_regs:b2v_inst24|sector[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "zpu_config_regs:b2v_inst24|sector[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "zpu_config_regs:b2v_inst24|sector[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "zpu_config_regs:b2v_inst24|sector[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "zpu_config_regs:b2v_inst24|sector[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "zpu_config_regs:b2v_inst24|sector[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "zpu_config_regs:b2v_inst24|sector[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "zpu_config_regs:b2v_inst24|sector[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "zpu_config_regs:b2v_inst24|sector[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "zpu_config_regs:b2v_inst24|sector[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "zpu_config_regs:b2v_inst24|sector[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "zpu_config_regs:b2v_inst24|sector[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "zpu_config_regs:b2v_inst24|sector[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "zpu_config_regs:b2v_inst24|sector[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "zpu_config_regs:b2v_inst24|sector[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "zpu_config_regs:b2v_inst24|sector[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "zpu_config_regs:b2v_inst24|sector[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "zpu_config_regs:b2v_inst24|sector[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "zpu_config_regs:b2v_inst24|sector[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "zpu_config_regs:b2v_inst24|sector[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "zpu_config_regs:b2v_inst24|sector[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "zpu_config_regs:b2v_inst24|sector[9]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=119" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=119" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=382" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=25945" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=37736" -section_id auto_signaltap_0
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: unmerged/core/mist/antic.vhdl.bak
===================================================================
--- unmerged/core/mist/antic.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/antic.vhdl.bak	(revision 1)
@@ -0,0 +1,1820 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	MEMORY_READY_ANTIC : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	ANTIC_ENABLE_179 : IN std_logic;
+	
+	PAL : IN STD_LOGIC;
+	
+	lightpen : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	NMI_N_OUT : OUT std_logic;
+	ANTIC_READY : OUT std_logic; -- taken low by wsync writes
+	
+	-- GTIA interface
+	AN : OUT STD_LOGIC_VECTOR(2 downto 0);
+	COLOUR_CLOCK_ORIGINAL_OUT : out std_logic;
+	COLOUR_CLOCK_OUT : out std_logic;
+	HIGHRES_COLOUR_CLOCK_OUT : out std_logic; -- 2x to allow for half pixel modes
+	
+	-- DMA fetch
+	dma_fetch_out : out std_logic;
+	dma_address_out : out std_logic_vector(15 downto 0);
+	
+	-- refresh
+	refresh_out : out std_logic; -- used by sdram
+	
+	-- for debugging
+	dma_clock_out : out std_logic
+);
+END antic;
+
+ARCHITECTURE vhdl OF antic IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT antic_dma_clock IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		enable_dma : IN STD_LOGIC;
+		
+		playfield_start : in std_logic;
+		playfield_end : in std_logic;
+		vblank : in std_logic;
+		
+		slow_dma : in std_logic;
+		medium_dma : in std_logic;
+		fast_dma : in std_logic;
+				
+		dma_clock_out_0 : out std_logic;
+		dma_clock_out_1 : out std_logic;
+		dma_clock_out_2 : out std_logic;
+		dma_clock_out_3 : out std_logic
+	);
+	END component;
+	
+	component antic_counter IS
+	generic
+	(
+		STORE_WIDTH : natural := 1;
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(STORE_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(STORE_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+		
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;	
+
+	component reg_file IS
+	generic
+	(
+		BYTES : natural := 1;
+		WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal enable_dma : std_logic;
+	signal dma_clock_character_name : std_logic;
+	signal dma_clock_character_inc : std_logic;
+	signal dma_clock_bitmap_data : std_logic;
+	signal dma_clock_character_data : std_logic;
+	
+	signal wsync_next : std_logic;
+	signal wsync_reg : std_logic;
+	signal wsync_reset : std_logic;
+	signal wsync_write : std_logic;
+	signal wsync_delayed_write : std_logic;
+	
+	signal nmi_next : std_logic;
+	signal nmi_reg : std_logic;
+	
+	signal nmi_shiftreg_next : std_logic_vector(15 downto 0);
+	signal nmi_shiftreg_reg : std_logic_vector(15 downto 0);
+	
+	signal nmist_next : std_logic_vector(7 downto 5); -- dli/vbi/reset
+	signal nmist_reg : std_logic_vector(7 downto 5);
+	
+	signal nmist_reset : std_logic;
+	
+	signal nmien_raw_next : std_logic_vector(7 downto 6); -- dli/vbi (reset always active)
+	signal nmien_raw_reg : std_logic_vector(7 downto 6);
+	signal nmien_delayed_reg : std_logic_vector(7 downto 6);
+	
+	signal dli_nmi_next : std_logic;
+	signal vbi_nmi_next : std_logic;
+	signal dli_nmi_reg : std_logic;
+	signal vbi_nmi_reg : std_logic;
+	
+	signal nmi_reset : std_logic;
+	--signal nmi_pending_next : std_logic; -- looks like on t65 the nmi_n is blocked by rdy being low, but not on real hardware?? XXX verify
+	--signal nmi_pending_reg : std_logic;
+	
+	signal playfield_dma_start : std_logic;
+	signal playfield_dma_end : std_logic;
+	signal playfield_display_active_next : std_logic;
+	signal playfield_display_active_reg : std_logic;
+	
+	signal dmactl_raw_next : std_logic_vector(6 downto 0);
+	signal dmactl_raw_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_reg : std_logic_vector(6 downto 0);
+	signal dmactl_delayed_enabled : std_logic;
+	
+	signal chactl_next : std_logic_vector(2 downto 0);
+	signal chactl_reg : std_logic_vector(2 downto 0);
+	
+	-- dma is only allowed during certain portions of the display
+	signal allow_real_dma_next : std_logic;
+	signal allow_real_dma_reg : std_logic;
+	
+	-- dma fetch handling
+	-- dma is scheduled one cycle before it happens, so that registers can directly drive output	
+	signal dma_fetch_next : std_logic;
+	signal dma_fetch_reg : std_logic;
+	signal dma_address_next : std_logic_vector(15 downto 0);
+	signal dma_address_reg : std_logic_vector(15 downto 0);
+	
+	constant dma_fetch_line_buffer : std_logic_vector(2 downto 0) := "000";
+	constant dma_fetch_shiftreg : std_logic_vector(2 downto 0) := "001";
+	constant dma_fetch_null : std_logic_vector(2 downto 0) := "010";
+	constant dma_fetch_instruction : std_logic_vector(2 downto 0) := "011";
+	constant dma_fetch_list_low : std_logic_vector(2 downto 0) := "100";
+	constant dma_fetch_list_high : std_logic_vector(2 downto 0) := "101";
+	signal dma_fetch_destination_next : std_logic_vector(2 downto 0);
+	signal dma_fetch_destination_reg : std_logic_vector(2 downto 0);
+	signal dma_fetch_request : std_logic;
+	
+	signal display_list_address_low_temp_next : std_logic_vector(7 downto 0);
+	signal display_list_address_low_temp_reg : std_logic_vector(7 downto 0);
+	
+	signal character_next : std_logic_vector(7 downto 0);
+	signal character_reg : std_logic_vector(7 downto 0);
+
+	signal displayed_character_next : std_logic_vector(7 downto 0);
+	signal displayed_character_reg : std_logic_vector(7 downto 0);
+	
+	-- instruction decode
+	signal instruction_next : std_logic_vector(7 downto 0);
+	signal instruction_reg : std_logic_vector(7 downto 0);
+	
+	signal first_line_of_instruction_next : std_logic;
+	signal first_line_of_instruction_reg: std_logic;
+
+	signal last_line_of_instruction_live : std_logic;
+	signal last_line_of_instruction_next : std_logic;
+	signal last_line_of_instruction_reg: std_logic;
+	
+	signal instruction_blank_reg : std_logic;
+	signal instruction_blank_next : std_logic;
+
+	--type dma_speed_type is (no_dma,slow_dma,medium_dma,fast_dma);
+	--signal dma_speed_next : dma_speed_type;
+	--signal dma_speed_reg : dma_speed_type;
+	constant no_dma : std_logic_vector(1 downto 0) := "00";
+	constant slow_dma : std_logic_vector(1 downto 0) := "01";
+	constant medium_dma : std_logic_vector(1 downto 0) := "10";
+	constant fast_dma : std_logic_vector(1 downto 0) := "11";
+	signal dma_speed_next : std_logic_vector(1 downto 0);
+	signal dma_speed_reg : std_logic_vector(1 downto 0);
+	signal slow_dma_s,medium_dma_s,fast_dma_s : std_logic; -- remove me XXX
+	
+	--type instruction_type is (mode_character, mode_bitmap, mode_jvb, mode_jump, mode_blank);
+	--signal instruction_type_next : instruction_type;
+	--signal instruction_type_reg : instruction_type;
+	constant mode_character : std_logic_vector(2 downto 0) := "000";
+	constant mode_bitmap : std_logic_vector(2 downto 0) := "001";
+	constant mode_jvb : std_logic_vector(2 downto 0) := "010";
+	constant mode_jump : std_logic_vector(2 downto 0) := "011";
+	constant mode_blank : std_logic_vector(2 downto 0) := "100";
+	signal instruction_type_next : std_logic_vector(2 downto 0);
+	signal instruction_type_reg : std_logic_vector(2 downto 0);
+	
+	signal two_part_instruction_next : std_logic;
+	signal two_part_instruction_reg : std_logic;
+
+		-- e.g. if instruction is 8 lines long then the final row is 7
+	signal instruction_final_row_next : std_logic_vector(3 downto 0);
+	signal instruction_final_row_reg : std_logic_vector(3 downto 0);
+		
+	--type shift_rate_type is (slow_shift,medium_shift,fast_shift);
+	--signal shift_rate_next : shift_rate_type;
+	--signal shift_rate_reg : shift_rate_type;
+	constant slow_shift : std_logic_vector(1 downto 0) := "00";
+	constant medium_shift : std_logic_vector(1 downto 0) := "01";
+	constant fast_shift : std_logic_vector(1 downto 0) := "10";
+	signal shift_rate_next : std_logic_vector(1 downto 0);
+	signal shift_rate_reg : std_logic_vector(1 downto 0);
+	
+	signal shift_twobit_next : std_logic; -- Provide AN0 and AN1, or just AN0
+	signal shift_twobit_reg : std_logic;
+	
+	signal twopixel_next : std_logic; -- GTIA should interpret output as two pixels
+	signal twopixel_reg : std_logic;	
+	
+	signal single_colour_character_next : std_logic; -- for antic 6/7 where high two bits of character code determine colour
+	signal single_colour_character_reg : std_logic;
+
+	signal multi_colour_character_next : std_logic; -- for antic 4/5 where 2 bits + 1 bit of of character code determin colour
+	signal multi_colour_character_reg : std_logic;
+	
+	signal twoline_character_next : std_logic; -- for antic 5/7
+	signal twoline_character_reg : std_logic;
+	
+	signal map_background_next : std_logic; -- background,pf0,pf1,pf2 graphics modes or background,pf0 modes
+	signal map_background_reg : std_logic;
+	
+	signal dli_enabled_next : std_logic;
+	signal dli_enabled_reg : std_logic;
+	
+	signal descenders_next : std_logic; -- for mode 3
+	signal descenders_reg : std_logic;
+		
+	-- Shift register used to output to AN2-AN0	
+	-- Can either be loaded from memory or from the line buffer
+	signal display_shift_next : std_logic_vector(7 downto 0);
+	signal display_shift_reg : std_logic_vector(7 downto 0);
+	
+	signal delay_display_shift_next : std_logic_vector(24 downto 0);
+	signal delay_display_shift_reg : std_logic_vector(24 downto 0);
+	
+	signal data_live : std_logic_vector(1 downto 0); -- helper for chatctl
+	
+	signal load_display_shift_from_memory : std_logic;
+	signal load_display_shift_from_line_buffer : std_logic;
+	
+	signal enable_shift : std_logic;
+	signal shiftclock_next : std_logic_vector(3 downto 0);
+	signal shiftclock_reg : std_logic_vector(3 downto 0);
+	
+	signal playfield_reset : std_logic;
+	signal playfield_load : std_logic;
+	
+	-- position in frame	
+	signal hcount_next : std_logic_vector(7 downto 0);
+	signal hcount_reg : std_logic_vector(7 downto 0);
+	
+	signal vcount_next : std_logic_vector(8 downto 0);
+	signal vcount_reg : std_logic_vector(8 downto 0);
+	
+	signal vblank_next : std_logic;
+	signal vblank_reg : std_logic;
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	signal playfield_dma_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_dma_end_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_start_cycle : std_logic_vector(7 downto 0);
+	signal playfield_display_end_cycle : std_logic_vector(7 downto 0);
+	
+	signal hcount_reset : std_logic;
+	signal vcount_reset : std_logic;
+	signal vcount_increment : std_logic;
+	
+	-- scrolling	
+	signal hscrol_reg : std_logic_vector(3 downto 0);
+	signal hscrol_next : std_logic_vector(3 downto 0);
+
+	signal vscrol_raw_reg : std_logic_vector(3 downto 0);
+	signal vscrol_raw_next : std_logic_vector(3 downto 0);
+	signal vscrol_delayed_reg : std_logic_vector(3 downto 0);
+	
+	signal vscrol_enabled_reg : std_logic;
+	signal vscrol_enabled_next : std_logic;
+	signal vscrol_last_enabled_reg : std_logic;
+	signal vscrol_last_enabled_next : std_logic;
+	
+	signal update_row_count : std_logic;
+	
+	signal hscrol_enabled_reg : std_logic;
+	signal hscrol_enabled_next : std_logic;
+
+	-- refresh
+	signal refresh_pending_next : std_logic;
+	signal refresh_pending_reg : std_logic;
+
+	signal refresh_fetch_next : std_logic;
+	signal refresh_fetch_reg : std_logic;
+	
+	-- Counter signals
+	signal increment_display_list_address : std_logic;
+	signal load_display_list_address : std_logic;
+	signal display_list_address_next : std_logic_vector(15 downto 0);
+	signal display_list_address_reg : std_logic_vector(15 downto 0);
+	signal load_display_list_address_cpu : std_logic;
+	signal load_display_list_address_dma : std_logic;
+	signal display_list_address_next_cpu : std_logic_vector(15 downto 0);
+	signal display_list_address_next_dma : std_logic_vector(15 downto 0);	
+
+	signal increment_memory_scan_address : std_logic;
+	signal load_memory_scan_address : std_logic;
+	signal memory_scan_address_next : std_logic_vector(15 downto 0);
+	signal memory_scan_address_reg : std_logic_vector(15 downto 0);
+
+	signal increment_line_buffer_address : std_logic;
+	signal load_line_buffer_address : std_logic;
+	signal line_buffer_address_next : std_logic_vector(7 downto 0);
+	signal line_buffer_address_reg : std_logic_vector(7 downto 0);
+
+	signal increment_row_count : std_logic;
+	signal load_row_count : std_logic;
+	signal row_count_next : std_logic_vector(3 downto 0);
+	signal row_count_reg : std_logic_vector(3 downto 0);
+
+	signal increment_refresh_count : std_logic;
+	signal load_refresh_count : std_logic;
+	signal refresh_count_next : std_logic_vector(3 downto 0);
+	signal refresh_count_reg : std_logic_vector(3 downto 0);
+	
+	signal pmbase_reg : std_logic_vector(7 downto 2);
+	signal pmbase_next : std_logic_vector(7 downto 2);
+
+	signal chbase_raw_reg : std_logic_vector(7 downto 1);
+	signal chbase_raw_next : std_logic_vector(7 downto 1);
+	signal chbase_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal line_buffer_write : std_logic;
+	signal line_buffer_data_in : std_logic_vector(7 downto 0);
+	signal line_buffer_data_out : std_logic_vector(7 downto 0);
+	
+	-- output registers
+	signal an_current : std_logic_vector(2 downto 0); -- live unregistered calculation of next output (not gated by cc)
+	signal an_prev_next : std_logic_vector(2 downto 0); -- previous - for hscrol
+	signal an_prev_reg : std_logic_vector(2 downto 0);  -- previous - for hscrol
+	signal an_next : std_logic_vector(2 downto 0);
+	signal an_reg : std_logic_vector(2 downto 0);
+	
+	-- light pendin
+	signal penv_next : std_logic_vector(7 downto 0);
+	signal penv_reg : std_logic_vector(7 downto 0);
+	signal penh_next : std_logic_vector(7 downto 0);
+	signal penh_reg : std_logic_vector(7 downto 0);
+	
+	-- high res modes
+	signal colour_clock_8x : std_logic;
+	signal colour_clock_4x : std_logic;
+	signal colour_clock_2x : std_logic;
+	signal colour_clock_1x : std_logic;
+	signal colour_clock_half_x : std_logic;
+	signal colour_clock_selected : std_logic;
+	signal colour_clock_selected_highres : std_logic;
+	
+	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
+	
+	constant cycle_length : integer := 32;	
+	
+	signal memory_ready_both : std_logic;
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			nmi_reg <= '0';
+			wsync_reg <= '0';
+			vcount_reg <= (others=>'0');
+			--hcount_reg <= X"01";
+			hcount_reg <= X"00";
+			dmactl_raw_reg <= (others=>'0');
+			chactl_reg <= (others=>'0');
+			vblank_reg <= '0';			
+			vsync_reg <= '0';
+			pmbase_reg <= (others=>'0');
+			allow_real_dma_reg <= '0';
+			display_shift_reg <= (others=>'0');
+			chbase_raw_reg <= (others=>'0');
+			
+			instruction_reg <= (others=>'0');
+			first_line_of_instruction_reg <= '0';
+			last_line_of_instruction_reg <= '0';
+			dma_speed_reg <= no_dma;
+			instruction_type_reg <= mode_blank;
+			instruction_final_row_reg <= (others=>'0');
+			shift_rate_reg <= slow_shift;
+			shift_twobit_reg <= '0';
+			twopixel_reg <= '0';
+			single_colour_character_reg <= '0';
+			multi_colour_character_reg <= '0';
+			twoline_character_reg <= '0';
+			map_background_reg <= '0';
+			dli_enabled_reg <= '0';
+			two_part_instruction_reg <= '0';
+			descenders_reg <='0';
+			
+			hscrol_reg <= (others=>'0');
+			vscrol_raw_reg <= (others=>'0');			
+			vscrol_enabled_reg <= '0';
+			vscrol_last_enabled_reg <= '0';
+			hscrol_enabled_reg <= '0';
+			
+			shiftclock_reg <= (others=>'0');
+			
+			hblank_reg <= '0';
+			
+			an_reg <= (others=>'0');
+			an_prev_reg <= (others=>'0');
+			
+			dma_fetch_reg <= '0';
+			dma_address_reg <= (others=>'0');			
+			dma_fetch_destination_reg <= dma_fetch_null;
+			
+			playfield_display_active_reg <= '0';
+			
+			instruction_blank_reg <= '0';
+			
+			display_list_address_low_temp_reg <= (others=>'0');
+			
+			character_reg <= (others=>'0');
+			displayed_character_reg <= (others=>'0');
+			
+			refresh_pending_reg <= '0';
+			refresh_fetch_reg <= '0';
+			
+			--nmi_pending_reg <= '0';
+			
+			dli_nmi_reg <= '0';
+			vbi_nmi_reg <= '0';
+			nmien_raw_reg <= (others=>'0');
+			
+			delay_display_shift_reg <= (others=>'0');
+			
+			nmi_shiftreg_reg <= (others=>'1');
+			
+			penh_reg <= (others=>'0');
+			penv_reg <= (others=>'0');
+			
+			colour_clock_count_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then			
+			nmi_reg <= nmi_next;
+			wsync_reg <= wsync_next;
+			vcount_reg <= vcount_next;
+			hcount_reg <= hcount_next;
+			nmist_reg <= nmist_next;
+			dmactl_raw_reg <= dmactl_raw_next;
+			chactl_reg <= chactl_next;
+			vblank_reg <= vblank_next;
+			vsync_reg <= vsync_next;
+			pmbase_reg <= pmbase_next;
+			allow_real_dma_reg <= allow_real_dma_next;
+			display_shift_reg <= display_shift_next;
+			chbase_raw_reg <= chbase_raw_next;
+			
+			instruction_reg <= instruction_next;
+			first_line_of_instruction_reg <= first_line_of_instruction_next;
+			last_line_of_instruction_reg <= last_line_of_instruction_next;
+			dma_speed_reg <= dma_speed_next;
+			instruction_type_reg <= instruction_type_next;
+			instruction_final_row_reg <= instruction_final_row_next;
+			shift_rate_reg <= shift_rate_next;
+			shift_twobit_reg <= shift_twobit_next;
+			twopixel_reg <= twopixel_next;
+			single_colour_character_reg <= single_colour_character_next;
+			multi_colour_character_reg <= multi_colour_character_next;
+			twoline_character_reg <= twoline_character_next;
+			map_background_reg <= map_background_next;
+			dli_enabled_reg <= dli_enabled_next;
+			two_part_instruction_reg <= two_part_instruction_next;
+			descenders_reg <= descenders_next;
+			
+			hscrol_reg <= hscrol_next;
+			vscrol_raw_reg <= vscrol_raw_next;	
+			vscrol_enabled_reg <= vscrol_enabled_next;
+			vscrol_last_enabled_reg <= vscrol_last_enabled_next;
+			hscrol_enabled_reg <= hscrol_enabled_next;
+			
+			shiftclock_reg <= shiftclock_next;
+			
+			hblank_reg <= hblank_next;
+			
+			an_reg <= an_next;
+			an_prev_reg <= an_prev_next;
+			
+			dma_fetch_reg <= dma_fetch_next;
+			dma_address_reg <= dma_address_next;
+			dma_fetch_destination_reg <= dma_fetch_destination_next;
+			
+			playfield_display_active_reg <= playfield_display_active_next;
+			
+			instruction_blank_reg <= instruction_blank_next;
+			
+			display_list_address_low_temp_reg <= display_list_address_low_temp_next;
+			
+			character_reg <= character_next;
+			displayed_character_reg <= displayed_character_next;
+			
+			refresh_pending_reg <= refresh_pending_next;
+			refresh_fetch_reg <= refresh_fetch_next;
+						
+			dli_nmi_reg <= dli_nmi_next;
+			vbi_nmi_reg <= vbi_nmi_next;
+			nmien_raw_reg <= nmien_raw_next;
+			
+			delay_display_shift_reg <= delay_display_shift_next;
+			
+			nmi_shiftreg_reg <= nmi_shiftreg_next;
+			
+			penh_reg <= penh_next;
+			penv_reg <= penv_next;
+			
+			colour_clock_count_reg <= colour_clock_count_next;
+		end if;
+	end process;
+	
+	-- Colour clock (3.57MHz for PAL)
+	-- TODO - allow double for 640 pixel width and quadruple for 1280 pixel width)
+	-- TODO - allow other clocks for driving VGA (mostly higher dot clock + line doubling (buffer between antic and gtia??))
+	--enable_colour_clock_div : enable_divider
+		--generic map (COUNT=>7)
+		--port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_colour_clock);	
+	process(colour_clock_count_reg, ANTIC_ENABLE_179)		
+	begin
+		colour_clock_half_x <= '0';
+		colour_clock_1x<='0';
+		colour_clock_2x<='0';
+		colour_clock_4x<='0';
+		colour_clock_8x<='0';
+	
+		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+		
+		if (ANTIC_ENABLE_179 = '1') then -- resync...
+			colour_clock_count_next <= "00001";
+		end if;
+
+		colour_clock_8x <= '1';
+		
+		case colour_clock_count_reg(4 downto 0) is
+		when "00000" =>
+			colour_clock_half_x <= '1';
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "00100" =>
+			colour_clock_4x <= '1';
+		when "01000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "01100" =>
+			colour_clock_4x <= '1';
+		when "10000" =>			
+			colour_clock_1x <= '1';
+			colour_clock_2x <= '1';
+			colour_clock_4x <= '1';
+		when "10100" =>
+			colour_clock_4x <= '1';
+		when "11000" =>
+			colour_clock_2x <= '1';			
+			colour_clock_4x <= '1';			
+		when "11100" =>
+			colour_clock_4x <= '1';			
+		when others =>
+			-- nop
+		end case;
+	end process;
+	
+	process(colour_clock_half_x,colour_clock_1x,colour_clock_2x, colour_clock_4x, colour_clock_8x, dmactl_delayed_reg)
+	begin
+		enable_dma <= colour_clock_half_x;
+		colour_clock_selected <= colour_clock_1x;
+		colour_clock_selected_highres <= colour_clock_2x;		
+		dmactl_delayed_enabled <= '0';
+		
+		case dmactl_delayed_reg(6 downto 5) is
+		when "01" =>
+			dmactl_delayed_enabled <= '1';
+		when "10" =>
+			enable_dma <= colour_clock_1x;
+			colour_clock_selected <= colour_clock_2x;		
+			colour_clock_selected_highres <= colour_clock_4x;
+			dmactl_delayed_enabled <= '1';
+		when "11" =>
+			enable_dma <= colour_clock_2x;
+			colour_clock_selected <= colour_clock_4x;
+			colour_clock_selected_highres <= colour_clock_8x;
+			dmactl_delayed_enabled <= '1';
+		when others =>
+			--nop
+		end case;		
+	end process;	
+		
+	--enable_dma_clock_div : enable_divider
+	--	generic map (COUNT=>2)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>colour_clock_selected,enable_out=>enable_dma);		
+
+	-- Counters (memory address for data, memory address for display list)
+	antic_counter_memory_scan : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>12)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_memory_scan_address, load=>load_memory_scan_address, load_value=>memory_scan_address_next, current_value=>memory_scan_address_reg);
+		
+	load_display_list_address <= load_display_list_address_cpu or load_display_list_address_dma;
+	display_list_address_next <= display_list_address_next_cpu when load_display_list_address_cpu='1' else display_list_address_next_dma;
+	antic_counter_display_list : antic_counter
+		generic map (STORE_WIDTH=>16, COUNT_WIDTH=>10)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_display_list_address, load=>load_display_list_address, load_value=>display_list_address_next, current_value=>display_list_address_reg);
+	antic_counter_line_buffer : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_line_buffer_address, load=>load_line_buffer_address, load_value=>line_buffer_address_next, current_value=>line_buffer_address_reg);
+	antic_counter_row_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_row_count, load=>load_row_count, load_value=>row_count_next, current_value=>row_count_reg);
+	antic_counter_refresh_count : simple_counter
+		generic map (COUNT_WIDTH=>4)
+		port map (clk=>clk, reset_n=>reset_n, increment=>increment_refresh_count, load=>load_refresh_count, load_value=>refresh_count_next, current_value=>refresh_count_reg);
+	
+	-- Count position on screen
+	-- horizontal
+	process(hcount_reg, colour_clock_1x, colour_clock_half_x, hcount_reset)
+	begin
+		hcount_next <= hcount_reg;		
+		if (colour_clock_1x = '1') then
+			hcount_next <= std_logic_vector(unsigned(hcount_reg)+1);
+			
+			if (colour_clock_half_x = '1') then
+				hcount_next(0) <= '1';
+			end if;
+		end if;
+		
+		if (hcount_reset = '1') then
+			hcount_next <= (others=>'0');
+		end if;
+	end process;
+	
+	-- vertical
+	process(vcount_reg, vcount_increment, vcount_reset, colour_clock_1x)
+	begin
+		vcount_next <= vcount_reg;
+		
+		if (colour_clock_1x = '1') then		
+			if (vcount_increment = '1') then
+				vcount_next <= std_logic_vector(unsigned(vcount_reg)+1);
+			end if;
+			
+			if (vcount_reset = '1') then
+				vcount_next <= (others=>'0');
+			end if;
+		end if;
+	end process;	
+	
+	-- Actions done based on vertical position		
+	process(vcount_reg, vblank_reg, vsync_reg, colour_clock_1x,vcount_increment,pal)
+	begin
+		vblank_next <= vblank_reg;
+		vsync_next <= vsync_reg;
+		vcount_reset <= '0';
+	
+		if (colour_clock_1x='1') then
+			case vcount_reg is
+				when '0'&X"08" => 
+					vblank_next <= '0';
+				when '0'&X"F8" =>
+					vblank_next <= '1';
+				--when '1'&X"05" => (changed for testing galaxian!)
+				--	vblank_next <= '1';					
+-- PAL
+				when '1'&X"16" =>
+					vsync_next <= pal;
+				when '1'&X"19" =>
+					vsync_next <= '0';
+				when '1'&X"38" =>
+					vcount_reset <= '1'; -- Blip at 9c..., then wrap
+-- NTSC
+				when '0'&X"FA" =>
+					vsync_next <= not(pal);
+				when '0'&X"FD" =>
+					vsync_next <= '0';
+				when '1'&X"06" =>
+					vcount_reset <= not(pal); -- Blip at 9c..., then wrap
+				when others =>
+					-- nothing
+			end case;
+		end if;
+	end process;
+	
+	-- Calculate playfield start/end
+	process(hscrol_enabled_reg, dmactl_delayed_reg, hscrol_reg)
+	begin		
+		playfield_dma_start_cycle <= (others=>'1');
+		playfield_dma_end_cycle <= (others=>'1');
+		playfield_display_start_cycle <= (others=>'1');
+		playfield_display_end_cycle <= (others=>'1');
+		
+		-- DMA clock start/end
+		-- wide=3, normal=2, narrow=1
+		-- Playfield start is at (in colour clocks):
+		-- 68 + hscrol&FE - width*16
+		-- i.e. for width=3 and hscrol=0 -> 68+0-48 = 20 (10 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 68+0-32 = 36 (18 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 68+0-16 = 52 (26 in cycles)
+		-- MUST BE A NICE EASY WAY TO GET THIS - expect offset is wrong... 
+		-- e.g. if its 64 then we may be able to do something like base&width&
+		-- Playfield end is at (in colour clocks):
+		-- 164 + hscrol&FE + width*16
+		-- i.e. for width=3 and hscrol=0 -> 164+0+48 = 212 (106 in cycles)
+		-- i.e. for width=2 and hscrol=0 -> 164+0+32 = 192 (96 in cycles)
+		-- i.e. for width=1 and hscrol=0 -> 164+0+16 = 180 (92 in cycles)
+		
+		-- hscrol interfers with playfield dma width (for dma purposes only!)
+		if (hscrol_enabled_reg='1') then
+			case dmactl_delayed_reg(1 downto 0) is
+				when "10"|"11" => -- normal and wide - both treated as wide due to hscrol
+					playfield_dma_start_cycle <= X"1"&hscrol_reg(3 downto 1)&'1'; -- 20  (10 in machine cycles)
+					playfield_dma_end_cycle   <= X"D"&hscrol_reg(3 downto 1)&'0'; -- 212 (106 in machine cycles)
+				when "01" => -- narrow - traated as normal due to hscrol
+					playfield_dma_start_cycle <= X"2"&hscrol_reg(3 downto 1)&'1'; -- 36  (18 in machine cycles)
+					playfield_dma_end_cycle <=   X"C"&hscrol_reg(3 downto 1)&'0'; -- 196 (98 in machine cycles)
+				when others =>
+					-- nothing
+			end case;
+		else
+			case dmactl_delayed_reg(1 downto 0) is
+				when "11" => -- wide
+					playfield_dma_start_cycle <= X"11";
+					playfield_dma_end_cycle   <= X"D0";
+				when "10" => -- normal
+					playfield_dma_start_cycle <= X"21";
+					playfield_dma_end_cycle   <= X"C0";
+				when "01" => -- narrow
+					playfield_dma_start_cycle <= X"31";
+					playfield_dma_end_cycle <=   X"B0";
+				when others =>
+					-- nothing
+			end case;		
+		end if;
+
+		-- background colour outside this area...
+		-- TODO - review these locations - should be clear due to garbage!
+		case dmactl_delayed_reg(1 downto 0) is
+			when "11" => -- wide
+				playfield_display_start_cycle <= X"2B"; -- TODO work out correct noise on left for large hscrol
+				if (hscrol_reg > X"C") then
+					playfield_display_start_cycle <= X"2F"; -- TODO work out correct noise on left for large hscrol				
+				end if;
+				playfield_display_end_cycle   <= X"DD"; -- last two colour clocks are corrupt (ie dc to dd), then there are two missing...
+			when "10" => -- normal
+				playfield_display_start_cycle <= X"2F";
+				playfield_display_end_cycle   <= X"CF";
+			when "01" => -- narrow
+				playfield_display_start_cycle <= X"3F";
+				playfield_display_end_cycle <=   X"BF";
+			when others =>
+				-- nothing
+		end case;				
+	end process;
+	
+	-- Actions done based on horizontal position - notably dma!
+	process (dmactl_delayed_enabled, hcount_reg, vcount_reg, vblank_reg, hblank_reg, dmactl_delayed_reg, playfield_dma_start_cycle, playfield_dma_end_cycle, playfield_display_start_cycle, playfield_display_end_cycle, instruction_final_row_reg, display_list_address_reg, pmbase_reg, first_line_of_instruction_reg, last_line_of_instruction_live, last_line_of_instruction_reg, instruction_type_reg, dma_clock_character_name, dma_clock_character_data, dma_clock_bitmap_data, allow_real_dma_reg, row_count_reg, dma_address_reg, memory_scan_address_reg, chbase_delayed_reg, line_buffer_data_out, enable_dma, colour_clock_1x, two_part_instruction_reg, dma_fetch_destination_reg, playfield_display_active_reg, character_reg, dma_clock_character_inc, single_colour_character_reg, twoline_character_reg, displayed_character_reg, instruction_reg, dli_enabled_reg, refresh_fetch_next, chactl_reg, vscrol_enabled_reg, vscrol_last_enabled_reg,twopixel_reg,dli_nmi_reg,vbi_nmi_reg)
+	begin
+		allow_real_dma_next <= allow_real_dma_reg;
+
+		playfield_dma_start <= '0';
+		playfield_dma_end <= '0';
+		playfield_display_active_next <= playfield_display_active_reg;
+		
+		dma_fetch_request <= '0';
+		dma_address_next <= dma_address_reg;
+		dma_fetch_destination_next <= dma_fetch_destination_reg;
+		
+		first_line_of_instruction_next <= first_line_of_instruction_reg;
+		last_line_of_instruction_next <= last_line_of_instruction_reg;
+		
+		load_display_shift_from_line_buffer <= '0';
+				
+		increment_memory_scan_address <= '0';
+		
+		line_buffer_address_next <= (others=>'0');
+		load_line_buffer_address <= '0';
+		increment_line_buffer_address <= '0';
+		
+		playfield_load <= '0';
+		
+		hblank_next <= hblank_reg;
+		hcount_reset <= '0';
+		
+		vcount_increment <= '0';
+		
+		character_next <= character_reg;
+		displayed_character_next <= displayed_character_reg;
+		
+		dli_nmi_next <= dli_nmi_reg;
+		vbi_nmi_next <= vbi_nmi_reg;
+		wsync_reset <= '0';
+		
+		load_refresh_count <= '0';
+		refresh_count_next <= (others=>'0');
+		
+		update_row_count <= '0'; 
+		vscrol_last_enabled_next <= vscrol_last_enabled_reg;
+	
+		if (colour_clock_1x = '1') then	
+			-- Playfield start/end
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_start_cycle))) then
+				playfield_dma_start <= '1';				
+				load_line_buffer_address <= '1';
+			end if;
+			
+			if (unsigned(hcount_reg) = (unsigned(playfield_dma_end_cycle))) then
+				playfield_dma_end <= '1';
+			end if;	
+			
+			if (hcount_reg = playfield_display_start_cycle) then
+				playfield_display_active_next <= '1';				
+			end if;
+			
+			if (hcount_reg = playfield_display_end_cycle) then
+				playfield_display_active_next <= '0';
+			end if;	
+
+			if (dma_clock_character_data = '1') then -- Final cycle of this is cycle 114 (0 based) - aka cycle 0... Which clashes with pmg dma.
+				if (dmactl_delayed_enabled='1' and instruction_type_reg = mode_character) then -- Sooo only enable, never disable
+					dma_fetch_request <= '1';
+				end if;				
+
+				if (twoline_character_reg='1') then
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(3 downto 1)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				else
+					if (single_colour_character_reg='1') then
+						dma_address_next <= chbase_delayed_reg(7 downto 1)&character_reg(5 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					else
+						dma_address_next <= chbase_delayed_reg(7 downto 2)&character_reg(6 downto 0)&(row_count_reg(2 downto 0)xor chactl_reg(2)&chactl_reg(2)&chactl_reg(2));
+					end if;
+				end if;
+				
+				displayed_character_next <= character_reg;
+				
+				-- TODO
+				-- Logic depends on mode - e.g. some 128 char, some 64 char etc. Line count is complex, depends on vscrol etc.				
+				dma_fetch_destination_next <= dma_fetch_shiftreg;
+				
+				load_display_shift_from_line_buffer <= to_std_logic(instruction_type_reg = mode_bitmap);								
+				increment_line_buffer_address <= '1';
+			end if;						
+		
+			case hcount_reg is 		
+				when X"00" => -- missile DMA, if missile or player DMA enabled					
+					dma_fetch_request <= dmactl_delayed_reg(2) or dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;									
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&"011"&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&"011"&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"02" => -- display list dma if enabled
+					first_line_of_instruction_next <= '0';
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- suppress when waiting for vblank
+						first_line_of_instruction_next <= first_line_of_instruction_reg or vblank_reg;
+					else				
+						if (last_line_of_instruction_reg = '1') then -- set on previous line at cycle 108
+							dma_fetch_request <= dmactl_delayed_enabled;
+							dma_address_next <= display_list_address_reg;
+							dma_fetch_destination_next <= dma_fetch_instruction;									
+							
+							first_line_of_instruction_next <= '1';						
+							
+							vscrol_last_enabled_next <= vscrol_enabled_reg;
+						end if;
+					end if;					
+				
+				when X"03" =>				
+					update_row_count <= '1'; -- done after instruction fetch...
+					
+				when X"04"|X"06"|X"08"|X"0A" =>  -- player DMA, if enabled
+					dma_fetch_request <= dmactl_delayed_reg(3);
+					dma_fetch_destination_next <= dma_fetch_null;	
+					if (dmactl_delayed_reg(4) = '1') then -- single line resolution
+						dma_address_next <= pmbase_reg(7 downto 3)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 0);
+					else
+						dma_address_next <= pmbase_reg(7 downto 2)&std_logic_vector(unsigned(hcount_reg(3 downto 1))+2)&vcount_reg(7 downto 1);
+					end if;
+					
+				when X"0C" => -- lms lower byte dma if display list dma enabled?;
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_low;
+				
+				when X"0E" => -- lms upper byte dma if display list dma enabled?
+					dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg and two_part_instruction_reg;
+					dma_address_next <= display_list_address_reg;				
+					dma_fetch_destination_next <= dma_fetch_list_high;
+					
+					if (instruction_type_reg = mode_jvb) then
+						-- turn off this extra dma for jvb mode, re-enabled by vblank_reg
+						first_line_of_instruction_next <= '0';
+					end if;
+					
+					dli_nmi_next <= dli_enabled_reg and last_line_of_instruction_live and not vblank_reg;
+					if (vcount_reg = '0'&X"F8") then
+						vbi_nmi_next <= '1';
+					end if;
+					
+				when X"12" =>
+					dli_nmi_next <= '0';
+					vbi_nmi_next <= '0';
+
+				when X"21" =>
+					hblank_next <= '0';					
+					
+				when X"24" => 
+					playfield_load <= '1'; -- start the shift register
+					
+				when X"31" => -- start refresh					
+					load_refresh_count <= '1';
+					refresh_count_next <= (others=>'0');
+				
+				when X"D2" => -- cycle 105 - reset wsync so we process from 105 on
+					wsync_reset <= '1';				
+			
+				when X"D4" => -- Force playfield DMA into virtual mode (cycle 105)
+					allow_real_dma_next <= '0';				
+					load_refresh_count <= '1';
+					refresh_count_next <= "1001";
+					
+				when X"D8" => -- vscrol value checked at cycle 108
+					last_line_of_instruction_next <= last_line_of_instruction_live;
+				
+				when X"DE" => -- Increment vcount immediately before cycle 111 (again the 4 offset as seen in hscrol...)
+					vcount_increment <= '1';
+										
+				when X"DD" =>
+					hblank_next <= '1';					
+					
+				when X"E3" => -- Wrap hcount after 227 (i.e. 0 to 227)
+					hcount_reset <= '1';
+					allow_real_dma_next <= not(vblank_reg);
+				when others =>
+					-- nothing
+			end case;	
+			
+			-- Playfield DMA
+			if (instruction_type_reg = mode_character and dma_clock_character_name = '1') then -- for character name
+				dma_fetch_request <= dmactl_delayed_enabled and first_line_of_instruction_reg;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= first_line_of_instruction_reg;
+			end if;					
+			
+			if (instruction_type_reg = mode_character and dma_clock_character_inc = '1') then -- next character
+				character_next <= line_buffer_data_out;
+				increment_line_buffer_address <= '1';
+			end if;
+			
+			if (instruction_type_reg = mode_bitmap and dma_clock_bitmap_data = '1' and first_line_of_instruction_reg='1') then -- bitmap data			
+				dma_fetch_request <= dmactl_delayed_enabled;
+				dma_address_next <= memory_scan_address_reg;
+				dma_fetch_destination_next <= dma_fetch_line_buffer;
+				increment_memory_scan_address <= '1';		
+			end if;
+			
+			if (vblank_reg = '1') then
+				dma_fetch_request <= '0';
+			end if;
+			
+			if (refresh_fetch_next = '1') then
+				dma_address_next <= (others=>'0');
+			end if;
+		
+		end if;
+	end process;
+	
+	-- refresh handling
+	process(hcount_reg,refresh_count_reg,colour_clock_1x,dma_fetch_next,refresh_pending_reg, refresh_fetch_reg, memory_ready_antic, allow_real_dma_next)
+	begin
+		increment_refresh_count <= '0';
+		refresh_pending_next <= refresh_pending_reg;
+		refresh_fetch_next <= not(memory_ready_antic) and refresh_fetch_reg;
+		
+		if (colour_clock_1x = '1') then
+			-- do pending refresh once we have a spare cycle
+			if (refresh_pending_reg='1' and (dma_fetch_next='0' or allow_real_dma_next='0') and hcount_reg(0) = '0') then
+				refresh_fetch_next <= '1';		
+				refresh_pending_next <= '0';
+			end if;
+		
+			-- do scheduled refresh - if block, enable pending one
+			if (hcount_reg(2 downto 0) = "010" and unsigned(refresh_count_reg)<9) then
+				increment_refresh_count <= '1';
+				refresh_fetch_next <= not(dma_fetch_next);
+				refresh_pending_next <= dma_fetch_next;
+			end if;
+		end if;
+	end process;
+	
+	-- nmi handling
+	-- edge senstive, single cycle is enough (unless cpu disabled or  clashes)
+	-- antic asserts for 2 old cycles - if we stick to that then in turbo mode it fixes most nmi bugs, in normal mode they still exist...	which is the goal.	
+
+	nmien_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>nmien_raw_reg(7 downto 6),enable=>'1',reset_n=>reset_n,data_out=>nmien_delayed_reg(7 downto 6));
+		
+	nmi_next <= not((dli_nmi_reg and nmien_delayed_reg(7)) or (vbi_nmi_reg and nmien_delayed_reg(6)));
+	
+	process(nmist_reg, vbi_nmi_reg, dli_nmi_reg, vbi_nmi_next, dli_nmi_next, nmist_reset)
+	begin	
+		nmist_next(5) <= '0';
+		nmist_next(6) <= ((nmist_reg(6) and not(nmist_reset)) or vbi_nmi_reg or vbi_nmi_next) and not(dli_nmi_reg or dli_nmi_next); -- auto clear vbi flat on dli!
+		nmist_next(7) <= ((nmist_reg(7) and not(nmist_reset))or dli_nmi_reg or dli_nmi_next) and not(vbi_nmi_reg or vbi_nmi_next); -- auto clear dli flag on vbi!
+	end process;
+	
+	-- dma clock	
+	process(dma_speed_reg) -- XXX TODO - remove this process!
+	begin
+		slow_dma_s <= '0';
+		medium_dma_s <= '0';
+		fast_dma_s <= '0';
+		
+		case dma_speed_reg is
+			when no_dma =>
+				-- nothing
+			when slow_dma =>
+				slow_dma_s <= '1';
+			when medium_dma =>
+				medium_dma_s <= '1';
+			when fast_dma =>
+				fast_dma_s <= '1';
+		end case;
+	end process;
+	
+	antic_dma_clock1 : antic_dma_clock
+		port map (clk=>clk, reset_n=>reset_n,enable_dma=>enable_dma, playfield_start=>playfield_dma_start,playfield_end=>playfield_dma_end,vblank=>vblank_reg,slow_dma=>slow_dma_s,medium_dma=>medium_dma_s,fast_dma=>fast_dma_s,dma_clock_out_0=>dma_clock_character_name,dma_clock_out_1=>dma_clock_character_inc,dma_clock_out_2=>dma_clock_bitmap_data,dma_clock_out_3=>dma_clock_character_data);
+
+	-- line buffer
+	reg_file1 : reg_file
+		generic map (BYTES=>48, WIDTH=>6) -- TODO:reset after 63, not 64?
+		port map (clk=>clk,addr=>line_buffer_address_reg(5 downto 0),data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);		
+		--generic map (BYTES=>192, WIDTH=>8) -- TODO:reset after 63, not 64?
+		--port map (clk=>clk,addr=>line_buffer_address_reg,data_in=>line_buffer_data_in,wr_en=>line_buffer_write, data_out=>line_buffer_data_out);
+		
+	-- vertical scrolling
+	-- load row count from vscrol must be done at time of instruction load
+	-- vscrol adjustment to affect dli should be done by cycle 5 - i.e. dli 'last line'
+	-- vscrol adjustment to affect actual last line should be done by cycle 108 - because...
+	vscrol_delay : wide_delay_line
+		generic map (COUNT=>cycle_length,WIDTH=>4)
+		port map (clk=>clk,sync_reset=>'0',data_in=>vscrol_raw_reg(3 downto 0),enable=>'1',reset_n=>reset_n,data_out=>vscrol_delayed_reg(3 downto 0));		
+	
+	process(vblank_reg, vscrol_delayed_reg, vscrol_enabled_reg, vscrol_last_enabled_reg, first_line_of_instruction_reg, row_count_reg, instruction_final_row_reg, update_row_count)
+	begin								
+		load_row_count <= '0';
+		row_count_next <= (others=>'0');
+		increment_row_count <= '0';
+		
+		last_line_of_instruction_live <= '0';		
+		
+		if (update_row_count = '1') then							
+			if (vscrol_enabled_reg='1' and vscrol_last_enabled_reg='0') then -- vscrol - first line
+				row_count_next <= vscrol_delayed_reg;
+			end if;
+		
+			if (first_line_of_instruction_reg = '1') then
+				load_row_count <= '1';
+			else
+				increment_row_count <= '1';
+			end if;
+		end if;
+		
+		if (vscrol_enabled_reg='0' and vscrol_last_enabled_reg='1') then -- vscrol - last line
+			if (row_count_reg = vscrol_delayed_reg) then -- TODO, review
+				last_line_of_instruction_live <= '1';
+			end if;
+		else -- normal
+			if (row_count_reg = instruction_final_row_reg) then
+				last_line_of_instruction_live <= '1';
+			end if;
+		end if;
+		
+		if (vblank_reg = '1') then
+			last_line_of_instruction_live <= '1';
+		end if;
+						
+	end process;
+	
+	-- chbase 2 cycle delay
+	chbase_delay : wide_delay_line
+		generic map (COUNT=>cycle_length*2,WIDTH=>7)
+		port map (clk=>clk,sync_reset=>'0',data_in=>chbase_raw_reg(7 downto 1),enable=>'1',reset_n=>reset_n,data_out=>chbase_delayed_reg(7 downto 1));
+		
+	-- decode instruction	
+	process(instruction_reg)
+	begin
+		dma_speed_next <= no_dma;
+		instruction_type_next <= mode_blank;
+		shift_rate_next <= slow_shift;
+		shift_twobit_next <= '0';
+		twopixel_next <= '0';
+		single_colour_character_next <= '0';		
+		multi_colour_character_next <= '0';		
+		twoline_character_next <= '0';
+		map_background_next <= '0';
+		instruction_final_row_next <= (others=>'0');
+		two_part_instruction_next <= instruction_reg(6);
+		instruction_blank_next <= '0';
+		vscrol_enabled_next <= instruction_reg(5);
+		hscrol_enabled_next <= instruction_reg(4);
+		dli_enabled_next <= instruction_reg(7);
+		descenders_next <= '0';		
+		
+		case instruction_reg(3 downto 0) is 			
+			when X"0" =>
+				instruction_type_next <= mode_blank;
+				instruction_final_row_next <= '0'&instruction_reg(6 downto 4);
+				two_part_instruction_next <= '0';
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				
+			when X"1" =>
+				instruction_type_next <= mode_jump;
+				instruction_final_row_next <= (others=>'0');
+				instruction_blank_next <= '1';
+				vscrol_enabled_next <= '0';
+				hscrol_enabled_next <= '0';
+				two_part_instruction_next <= '1';
+				
+				if (instruction_reg(6) = '1') then
+					instruction_type_next <= mode_jvb;
+				end if;
+				
+			when X"2" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+			when X"3" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"9";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				descenders_next <= '1';
+				
+			when X"4" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				multi_colour_character_next <= '1';
+				
+			when X"5" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';	
+				twoline_character_next <= '1';		
+				multi_colour_character_next <= '1';
+				
+			when X"6" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				
+			when X"7" =>
+				instruction_type_next <= mode_character;
+				instruction_final_row_next <= X"F";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				single_colour_character_next <= '1';
+				twoline_character_next <= '1';
+				
+			when X"8" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"7";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= slow_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"9" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= slow_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"A" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"3";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= medium_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"B" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"C" =>					
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= medium_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '0';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"D" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"1";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"E" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '0';
+				map_background_next <= '1';
+				
+			when X"F" =>
+				instruction_type_next <= mode_bitmap;
+				instruction_final_row_next <= X"0";
+				
+				dma_speed_next <= fast_dma;
+				shift_rate_next <= fast_shift;
+				shift_twobit_next <= '1';
+				twopixel_next <= '1';
+				
+		end case;
+	end process;
+
+	-- dma fetching
+	process(dma_fetch_reg,dma_address_reg,dma_fetch_destination_reg,memory_ready_both,memory_data_in,dma_fetch_request,vblank_reg, instruction_type_reg, instruction_reg, display_list_address_reg, memory_scan_address_reg, enable_dma, display_list_address_low_temp_reg)
+	begin	
+		instruction_next <= instruction_reg;
+		dma_fetch_next <= dma_fetch_request or dma_fetch_reg;
+		
+		display_list_address_next_dma <= display_list_address_reg;
+		load_display_list_address_dma <= '0';
+		memory_scan_address_next <= memory_scan_address_reg;
+		load_memory_scan_address <= '0';
+		increment_display_list_address <= '0';
+		
+		load_display_shift_from_memory <= '0';
+		display_list_address_low_temp_next <= display_list_address_low_temp_reg;		
+		
+		line_buffer_data_in <= (others=>'0');
+		line_buffer_write <= '0';
+		
+		if (vblank_reg = '1' and instruction_type_reg = mode_jvb) then
+			instruction_next <= (others=>'0');
+		end if;
+	
+		if (dma_fetch_reg='1' and memory_ready_both='1') then
+			case dma_fetch_destination_reg is 
+				when dma_fetch_line_buffer =>
+					line_buffer_data_in <= memory_data_in;					
+					line_buffer_write <= '1';
+				when dma_fetch_shiftreg =>
+					load_display_shift_from_memory <= '1';
+				when dma_fetch_null =>
+					-- nothing (C/G/MTIA listens to bus)
+				when dma_fetch_instruction =>
+					instruction_next <= memory_data_in;
+					
+					increment_display_list_address <= '1';
+					
+				when dma_fetch_list_low =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						--display_list_address_next_dma(7 downto 0) <= memory_data_in; Changing this so soon messes up next dma cycle
+						display_list_address_low_temp_next <= memory_data_in;
+						increment_display_list_address <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(7 downto 0) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				when dma_fetch_list_high =>
+					if (instruction_type_reg = mode_jump or instruction_type_reg = mode_jvb) then
+						 display_list_address_next_dma <= memory_data_in&display_list_address_low_temp_reg;
+						 load_display_list_address_dma <= '1';
+					else
+						increment_display_list_address <= '1';
+						memory_scan_address_next(15 downto 8) <= memory_data_in;
+						load_memory_scan_address <= '1';
+					end if;
+				
+				when others =>
+					-- nothing
+				
+			end case;
+
+			dma_fetch_next <= '0';
+		end if;
+	end process;
+	
+	-- shift reg clock
+	playfield_reset <= hblank_reg;
+	
+	process(colour_clock_selected, shift_rate_reg, shiftclock_reg, playfield_reset, playfield_load)
+	begin
+		shiftclock_next <= shiftclock_reg;
+		enable_shift <= '0';
+	
+		if (colour_clock_selected = '1') then
+		
+			shiftclock_next <= shiftclock_reg(2 downto 0)&shiftclock_reg(3);
+			
+			if (playfield_load='1') then
+				shiftclock_next <= "1000";
+			end if;
+			
+			if (playfield_reset='1') then
+				shiftclock_next <= "0000";
+			end if;			
+			
+			--shiftclock_next(0) <= shiftclock_reg(1);
+			--shiftclock_next(1) <= shiftclock_reg(2);
+			--shiftclock_next(2) <= shiftclock_reg(3) nor playfield_load;
+			--shiftclock_next(3) <= shiftclock_reg(0) nor playfield_reset;						
+			case shift_rate_reg is
+				when slow_shift =>
+					enable_shift <= shiftclock_reg(0);
+				when medium_shift =>
+					enable_shift <= shiftclock_reg(2) or shiftclock_reg(0);
+				when fast_shift =>			
+					enable_shift <= (shiftclock_reg(3) or shiftclock_reg(2)) or (shiftclock_reg(1) or shiftclock_reg(0));
+				when others =>
+					-- nothing
+			end case;			
+		end if;
+	end process;
+
+	-- shift reg
+	process (enable_shift, shift_twobit_reg, display_shift_reg, load_display_shift_from_memory, load_display_shift_from_line_buffer, memory_data_in, line_buffer_data_out)
+	begin
+		display_shift_next <= display_shift_reg;
+		
+		if (enable_shift = '1') then
+			if (shift_twobit_reg = '1') then
+				display_shift_next <= display_shift_reg(5 downto 0)&"00";
+			else
+				display_shift_next <= display_shift_reg(6 downto 0)&"0";
+			end if;			
+		end if;
+		
+		if (load_display_shift_from_memory = '1') then
+			display_shift_next(7 downto 0) <= memory_data_in;
+		end if;
+
+		if (load_display_shift_from_line_buffer = '1') then
+			display_shift_next(7 downto 0) <= line_buffer_data_out;
+		end if;
+		
+	end process;
+	
+	-- delay shift reg output for n cycles, so we can match AN with antic output
+	process(colour_clock_selected, display_shift_reg, delay_display_shift_reg, displayed_character_reg)
+	begin
+		delay_display_shift_next <= delay_display_shift_reg;
+		
+		if (colour_clock_selected = '1') then
+			delay_display_shift_next <= displayed_character_reg(7 downto 5)&display_shift_reg(7 downto 6)&delay_display_shift_reg(24 downto 5);
+		end if;
+		
+	end process;
+	
+	-- ANO-2
+	-- XXX - clean up!	
+	-- first process - AN with no blanking	
+	process(data_live,delay_display_shift_reg, shift_twobit_reg, twopixel_reg, instruction_blank_reg, playfield_display_active_reg, single_colour_character_reg, multi_colour_character_reg, chactl_reg, instruction_type_reg, map_background_reg, descenders_reg, row_count_reg)
+	begin
+		an_current <= (others=>'0');
+		data_live <= (others=>'0');
+		if (shift_twobit_reg = '1') then				
+			an_current(0) <= delay_display_shift_reg(0);
+			an_current(1) <= delay_display_shift_reg(1);
+			an_current(2) <= '1';
+			
+			if (instruction_type_reg = mode_character) then							
+				data_live(0) <= delay_display_shift_reg(0);
+				data_live(1) <= delay_display_shift_reg(1);
+								
+				if (descenders_reg = '1') then					
+					if (delay_display_shift_reg(3 downto 2) = "11") then
+						if (unsigned(row_count_reg)<2) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					else
+						if (unsigned(row_count_reg)>=8) then
+							data_live(1 downto 0) <= "00";
+						end if;
+					end if;
+				end if;	
+			
+				if (delay_display_shift_reg(4)='1') then -- inverse/hidden
+					if (chactl_reg(1)='1') then
+						an_current(0) <= not(data_live(0) and not(chactl_reg(0)));
+						an_current(1) <= not(data_live(1) and not(chactl_reg(0)));
+					else
+						an_current(0) <= data_live(0) and not(chactl_reg(0));
+						an_current(1) <= data_live(1) and not(chactl_reg(0));					
+					end if;
+				else
+					an_current(0) <= data_live(0);
+					an_current(1) <= data_live(1);				
+				end if;
+			end if;		
+
+			if (multi_colour_character_reg = '1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "11"&delay_display_shift_reg(4);										
+				end case;				
+			end if;
+			
+			if (map_background_reg='1') then
+				case delay_display_shift_reg(1 downto 0) is
+					when "00" =>
+						an_current <= "000";
+					when "01" =>
+						an_current <= "100";			
+					when "10" =>
+						an_current <= "101";			
+					when "11" =>
+						an_current <= "110";										
+				end case;
+			end if;
+		else
+			if (single_colour_character_reg = '1') then
+				-- i.e. antic 6,7
+				if (delay_display_shift_reg(1) = '1') then
+					an_current(0) <= delay_display_shift_reg(3);
+					an_current(1) <= delay_display_shift_reg(4);
+					an_current(2) <= '1';					
+				else
+					an_current(0) <= '0';
+					an_current(1) <= '0';
+					an_current(2) <= '0';
+				end if;			
+			end if;
+			
+			if (map_background_reg='1') then
+				if (delay_display_shift_reg(1)='1') then
+					an_current <= "100";
+				else
+					an_current <= "000";										
+				end if;
+			end if;				
+		end if;		
+	end process;
+	
+	process(colour_clock_selected, an_current, an_prev_reg)
+	begin
+		an_prev_next <= an_prev_reg;
+		
+		if (colour_clock_selected = '1') then
+			an_prev_next <= an_current;
+		end if;
+	end process;
+	
+	process(colour_clock_selected, an_current, an_reg, an_prev_reg, hscrol_reg, hscrol_enabled_reg, vsync_reg, vblank_reg, hblank_reg, playfield_display_active_reg, instruction_blank_reg, twopixel_reg)
+	begin
+		an_next <= an_reg;
+	
+		if (colour_clock_selected = '1') then	
+			an_next <= an_current;
+			
+			if (hscrol_reg(0)='1' and hscrol_enabled_reg='1') then
+				an_next <= an_prev_reg;
+			end if;
+			
+			if ((not(playfield_display_active_reg) or instruction_blank_reg or vblank_reg) = '1') then
+				an_next <= "000";
+			end if;
+			
+			if (vblank_reg = '1' or hblank_reg = '1') then				
+				an_next(0) <= vsync_reg or twopixel_reg;
+				an_next(1) <= not(vsync_reg);
+				an_next(2) <= not(hblank_reg) and twopixel_reg;
+				
+				--an_next <= 
+						--(twopixel_reg and not(vsync_reg or hblank_reg))
+						--&((hblank_reg or vblank_reg) and not(vsync_reg))
+						--&(vsync_reg or twopixel_reg);
+			end if;			
+			
+			-- TODO this is too simplistic:
+			-- Antic should provide GTIA with the 'visible region using code 002 for vblank and hblank
+			-- + odd behaviour seen during high res bug
+
+		end if;
+		
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+
+	-- wsync write takes 1 cycle to assert rdy
+	-- TODO - revisit antic delays in terms of cpu cycles
+	wsync_delay : delay_line
+		generic map (COUNT=>cycle_length+cycle_length/2)
+		port map (clk=>clk,sync_reset=>'0',data_in=>wsync_write,enable=>'1',reset_n=>reset_n,data_out=>wsync_delayed_write);
+
+	-- dmactl takes 1 cycle to be applied - NO IT DOES NOT - TODO FIXME
+	--dmactl_delay : wide_delay_line
+	--	generic map (COUNT=>cycle_length,WIDTH=>6)
+	--	port map (clk=>clk,sync_reset=>'0',data_in=>dmactl_raw_reg(5 downto 0),enable=>'1',reset_n=>reset_n,data_out=>dmactl_delayed_reg(5 downto 0));
+	dmactl_delayed_reg <= dmactl_raw_next;
+	--dmactl_delayed_reg <= dmactl_raw_reg;
+		
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,nmien_raw_reg,dmactl_raw_reg,chactl_reg,hscrol_reg,display_list_address_reg,chbase_raw_reg,pmbase_reg,vscrol_raw_reg, wsync_reg, wsync_delayed_write, wsync_reset)
+	begin		
+		nmien_raw_next <= nmien_raw_reg;
+		dmactl_raw_next <= dmactl_raw_reg;
+		chactl_next <= chactl_reg;
+		hscrol_next <= hscrol_reg;
+		vscrol_raw_next <= vscrol_raw_reg;
+		chbase_raw_next <= chbase_raw_reg;
+		pmbase_next <= pmbase_reg;
+		wsync_next <= (wsync_delayed_write or wsync_reg) and not(wsync_reset);
+		nmist_reset <= '0';
+		wsync_write <= '0';
+		
+		load_display_list_address_cpu <= '0';
+		display_list_address_next_cpu <= display_list_address_reg;
+	
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				dmactl_raw_next <= cpu_data_in(6 downto 0);
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				chactl_next <= cpu_data_in(2 downto 0);
+			end if;	
+			
+			if(addr_decoded(2) = '1') then
+				display_list_address_next_cpu(7 downto 0) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;		
+			
+			if(addr_decoded(3) = '1') then
+				display_list_address_next_cpu(15 downto 8) <= cpu_data_in;
+				load_display_list_address_cpu <= '1';
+			end if;
+
+			if(addr_decoded(4) = '1') then
+				hscrol_next <= cpu_data_in(3 downto 0);
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				vscrol_raw_next <= cpu_data_in(3 downto 0);
+			end if;
+			
+			if(addr_decoded(7) = '1') then
+				pmbase_next <= cpu_data_in(7 downto 2);
+			end if;		
+			
+			if(addr_decoded(9) = '1') then
+				chbase_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+
+			if(addr_decoded(10) = '1') then
+				wsync_write <= '1';
+			end if;		
+	
+			if(addr_decoded(14) = '1') then
+				nmien_raw_next <= cpu_data_in(7 downto 6);
+			end if;
+		
+			if(addr_decoded(15) = '1') then
+				nmist_reset <= '1';
+			end if;		
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,hcount_reg,vcount_reg,nmist_reg,penv_reg,penh_reg)
+	begin
+		data_out <= X"FF";
+
+		if (addr_decoded(8) = '1') then -- HCOUNT :-)
+			data_out <= hcount_reg; -- bonus points for the one who spots this in code:-)
+		end if;
+		
+		if(addr_decoded(11) = '1') then --VCOUNT
+			data_out <= vcount_reg(8 downto 1);
+		end if;
+		
+		if (addr_decoded(12) = '1') then -- PENH
+			data_out <= penh_reg;
+		end if;
+		
+		if (addr_decoded(13) = '1') then -- PENV
+			data_out <= penv_reg;
+		end if;
+
+		if(addr_decoded(15) = '1') then --NMIST
+			data_out <= nmist_reg&"00000";
+		end if;
+		
+	end process;
+	
+	-- nmi delay
+	nmi_shiftreg_next <= nmi_reg&nmi_shiftreg_reg(15 downto 1);
+	
+	-- light pen
+	process(lightpen,hcount_reg,vcount_reg,penv_reg,penh_reg)
+	begin
+		penv_next <= penv_reg;
+		penh_next <= penh_reg;
+		
+		if (lightpen = '0') then
+			penv_next <= vcount_reg(8 downto 1);
+			penh_next <= hcount_reg;
+		end if;
+	end process;
+	
+	-- Use CPU data if virtual dma
+	MEMORY_READY_both <= MEMORY_READY_ANTIC when allow_real_dma_reg='1' else MEMORY_READY_CPU;
+	
+	-- output
+	nmi_n_out <= nmi_shiftreg_reg(0);
+	
+	dma_clock_out<=dma_clock_character_name;
+	
+	AN <= an_reg;
+	
+	antic_ready <= not(wsync_reg);
+	
+	dma_fetch_out <= refresh_fetch_reg or (allow_real_dma_reg and dma_fetch_reg);
+	dma_address_out <= dma_address_reg;
+	
+	refresh_out <= refresh_fetch_reg;
+	
+	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+	COLOUR_CLOCK_OUT <= colour_clock_selected;
+	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
+	
+END vhdl;
+
Index: unmerged/core/mist/atari800core.qpf
===================================================================
--- unmerged/core/mist/atari800core.qpf	(nonexistent)
+++ unmerged/core/mist/atari800core.qpf	(revision 1)
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:38  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "12.1"
+DATE = "13:58:38  April 11, 2013"
+
+# Revisions
+
+PROJECT_REVISION = "atari800core"
Index: unmerged/core/mist/atari800core.jdi
===================================================================
--- unmerged/core/mist/atari800core.jdi	(nonexistent)
+++ unmerged/core/mist/atari800core.jdi	(revision 1)
@@ -0,0 +1,62 @@
+<sld_project_info>
+  <project>
+    <hash md5_digest_80b="7d0f11bf891bc55d775e"/>
+  </project>
+  <file_info/>
+  <hub_info ir_width="8" node_count="1"/>
+  <node_info>
+    <node hpath="sld_signaltap:auto_signaltap_0" instance_id="0" mfg_id="110" node_id="0" sld_node_info="0x30006E00" version="6">
+      <parameters>
+        <parameter name="lpm_type" type="string" value="sld_signaltap"/>
+        <parameter name="sld_node_info" type="unknown" value="805334528"/>
+        <parameter name="SLD_IP_VERSION" type="dec" value="6"/>
+        <parameter name="SLD_IP_MINOR_VERSION" type="dec" value="0"/>
+        <parameter name="SLD_COMMON_IP_VERSION" type="dec" value="0"/>
+        <parameter name="sld_data_bits" type="unknown" value="119"/>
+        <parameter name="sld_trigger_bits" type="unknown" value="119"/>
+        <parameter name="SLD_NODE_CRC_BITS" type="dec" value="32"/>
+        <parameter name="sld_node_crc_hiword" type="unknown" value="37736"/>
+        <parameter name="sld_node_crc_loword" type="unknown" value="25945"/>
+        <parameter name="SLD_INCREMENTAL_ROUTING" type="dec" value="0"/>
+        <parameter name="sld_sample_depth" type="unknown" value="2048"/>
+        <parameter name="sld_segment_size" type="unknown" value="2048"/>
+        <parameter name="SLD_RAM_BLOCK_TYPE" type="string" value="AUTO"/>
+        <parameter name="sld_state_bits" type="unknown" value="11"/>
+        <parameter name="sld_buffer_full_stop" type="unknown" value="1"/>
+        <parameter name="SLD_MEM_ADDRESS_BITS" type="dec" value="7"/>
+        <parameter name="SLD_DATA_BIT_CNTR_BITS" type="dec" value="4"/>
+        <parameter name="sld_trigger_level" type="unknown" value="1"/>
+        <parameter name="sld_trigger_in_enabled" type="unknown" value="0"/>
+        <parameter name="sld_advanced_trigger_entity" type="unknown" value="basic,1,"/>
+        <parameter name="sld_trigger_level_pipeline" type="unknown" value="1"/>
+        <parameter name="sld_enable_advanced_trigger" type="unknown" value="0"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_1" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_2" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_3" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_4" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_5" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_6" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_7" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_8" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_9" type="string" value="NONE"/>
+        <parameter name="SLD_ADVANCED_TRIGGER_10" type="string" value="NONE"/>
+        <parameter name="sld_inversion_mask_length" type="unknown" value="382"/>
+        <parameter name="sld_inversion_mask" type="unknown" value="0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"/>
+        <parameter name="sld_power_up_trigger" type="unknown" value="0"/>
+        <parameter name="SLD_STATE_FLOW_MGR_ENTITY" type="string" value="state_flow_mgr_entity.vhd"/>
+        <parameter name="sld_state_flow_use_generated" type="unknown" value="0"/>
+        <parameter name="sld_current_resource_width" type="unknown" value="1"/>
+        <parameter name="sld_attribute_mem_mode" type="unknown" value="OFF"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_BITS" type="dec" value="1"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_GAP_RECORD" type="dec" value="0"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_MODE" type="string" value="OFF"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION" type="dec" value="0"/>
+        <parameter name="sld_storage_qualifier_inversion_mask_length" type="unknown" value="0"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY" type="string" value="basic"/>
+        <parameter name="SLD_STORAGE_QUALIFIER_PIPELINE" type="dec" value="0"/>
+      </parameters>
+      <inputs/>
+      <outputs/>
+    </node>
+  </node_info>
+</sld_project_info>
Index: unmerged/core/mist/antic_dma_clock.vhdl
===================================================================
--- unmerged/core/mist/antic_dma_clock.vhdl	(nonexistent)
+++ unmerged/core/mist/antic_dma_clock.vhdl	(revision 1)
@@ -0,0 +1,74 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY antic_dma_clock IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	enable_dma : IN STD_LOGIC;
+	
+	playfield_start : in std_logic;
+	playfield_end : in std_logic;
+	vblank : in std_logic;
+	
+	slow_dma : in std_logic;
+	medium_dma : in std_logic;
+	fast_dma : in std_logic;
+	
+	dma_clock_out_0 : out std_logic;
+	dma_clock_out_1 : out std_logic;
+	dma_clock_out_2 : out std_logic;
+	dma_clock_out_3 : out std_logic
+);
+END antic_dma_clock;
+
+ARCHITECTURE vhdl OF antic_dma_clock IS
+	signal dma_shiftreg_next : std_logic_vector(7 downto 0);
+	signal dma_shiftreg_reg : std_logic_vector(7 downto 0);
+	
+	signal tick : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			dma_shiftreg_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			dma_shiftreg_reg <= dma_shiftreg_next;
+		end if;
+	end process;
+
+	-- next state
+	tick <=(dma_shiftreg_reg(0) and slow_dma) or (dma_shiftreg_reg(4) and medium_dma) or (dma_shiftreg_reg(6) and fast_dma);
+	process(enable_dma, dma_shiftreg_reg, playfield_start, playfield_end, vblank, slow_dma, medium_dma, fast_dma, tick)
+	begin
+		dma_shiftreg_next <= dma_shiftreg_reg;
+
+		if (enable_dma = '1') then			
+			dma_shiftreg_next <= 
+				not((playfield_start nor tick)
+				or playfield_end or vblank)				
+				&dma_shiftreg_reg(7 downto 1);
+		end if;
+		
+		if (playfield_start = '1') then
+			dma_shiftreg_next(7) <= not((playfield_start nor tick) or playfield_end or vblank);
+		end if;
+	end process;
+	
+	-- output
+	dma_clock_out_0 <= dma_shiftreg_reg(6) and enable_dma;
+	dma_clock_out_1 <= dma_shiftreg_reg(5) and enable_dma;
+	dma_clock_out_2 <= dma_shiftreg_reg(4) and enable_dma;
+	dma_clock_out_3 <= dma_shiftreg_reg(3) and enable_dma;
+	
+END vhdl;
Index: unmerged/core/mist/atari800core.qsf.bak
===================================================================
--- unmerged/core/mist/atari800core.qsf.bak	(nonexistent)
+++ unmerged/core/mist/atari800core.qsf.bak	(revision 1)
@@ -0,0 +1,584 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone II"
+set_global_assignment -name DEVICE EP2C20F484C7
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_A15 -to GPIO_0[4]
+set_location_assignment PIN_B15 -to GPIO_0[5]
+set_location_assignment PIN_A16 -to GPIO_0[6]
+set_location_assignment PIN_B16 -to GPIO_0[7]
+set_location_assignment PIN_A17 -to GPIO_0[8]
+set_location_assignment PIN_B17 -to GPIO_0[9]
+set_location_assignment PIN_A18 -to GPIO_0[10]
+set_location_assignment PIN_B18 -to GPIO_0[11]
+set_location_assignment PIN_A19 -to GPIO_0[12]
+set_location_assignment PIN_B19 -to GPIO_0[13]
+set_location_assignment PIN_A20 -to GPIO_0[14]
+set_location_assignment PIN_B20 -to GPIO_0[15]
+set_location_assignment PIN_C21 -to GPIO_0[16]
+set_location_assignment PIN_C22 -to GPIO_0[17]
+set_location_assignment PIN_D21 -to GPIO_0[18]
+set_location_assignment PIN_D22 -to GPIO_0[19]
+set_location_assignment PIN_E21 -to GPIO_0[20]
+set_location_assignment PIN_E22 -to GPIO_0[21]
+set_location_assignment PIN_F21 -to GPIO_0[22]
+set_location_assignment PIN_F22 -to GPIO_0[23]
+set_location_assignment PIN_G21 -to GPIO_0[24]
+set_location_assignment PIN_G22 -to GPIO_0[25]
+set_location_assignment PIN_J21 -to GPIO_0[26]
+set_location_assignment PIN_J22 -to GPIO_0[27]
+set_location_assignment PIN_K21 -to GPIO_0[28]
+set_location_assignment PIN_K22 -to GPIO_0[29]
+set_location_assignment PIN_J19 -to GPIO_0[30]
+set_location_assignment PIN_J20 -to GPIO_0[31]
+set_location_assignment PIN_J18 -to GPIO_0[32]
+set_location_assignment PIN_K20 -to GPIO_0[33]
+set_location_assignment PIN_L19 -to GPIO_0[34]
+set_location_assignment PIN_L18 -to GPIO_0[35]
+set_location_assignment PIN_H12 -to GPIO_1[0]
+set_location_assignment PIN_H13 -to GPIO_1[1]
+set_location_assignment PIN_H14 -to GPIO_1[2]
+set_location_assignment PIN_G15 -to GPIO_1[3]
+set_location_assignment PIN_E14 -to GPIO_1[4]
+set_location_assignment PIN_E15 -to GPIO_1[5]
+set_location_assignment PIN_F15 -to GPIO_1[6]
+set_location_assignment PIN_G16 -to GPIO_1[7]
+set_location_assignment PIN_F12 -to GPIO_1[8]
+set_location_assignment PIN_F13 -to GPIO_1[9]
+set_location_assignment PIN_C14 -to GPIO_1[10]
+set_location_assignment PIN_D14 -to GPIO_1[11]
+set_location_assignment PIN_D15 -to GPIO_1[12]
+set_location_assignment PIN_D16 -to GPIO_1[13]
+set_location_assignment PIN_C17 -to GPIO_1[14]
+set_location_assignment PIN_C18 -to GPIO_1[15]
+set_location_assignment PIN_C19 -to GPIO_1[16]
+set_location_assignment PIN_C20 -to GPIO_1[17]
+set_location_assignment PIN_D19 -to GPIO_1[18]
+set_location_assignment PIN_D20 -to GPIO_1[19]
+set_location_assignment PIN_E20 -to GPIO_1[20]
+set_location_assignment PIN_F20 -to GPIO_1[21]
+set_location_assignment PIN_E19 -to GPIO_1[22]
+set_location_assignment PIN_E18 -to GPIO_1[23]
+set_location_assignment PIN_G20 -to GPIO_1[24]
+set_location_assignment PIN_G18 -to GPIO_1[25]
+set_location_assignment PIN_G17 -to GPIO_1[26]
+set_location_assignment PIN_H17 -to GPIO_1[27]
+set_location_assignment PIN_J15 -to GPIO_1[28]
+set_location_assignment PIN_H18 -to GPIO_1[29]
+set_location_assignment PIN_N22 -to GPIO_1[30]
+set_location_assignment PIN_N21 -to GPIO_1[31]
+set_location_assignment PIN_P15 -to GPIO_1[32]
+set_location_assignment PIN_N15 -to GPIO_1[33]
+set_location_assignment PIN_P17 -to GPIO_1[34]
+set_location_assignment PIN_P18 -to GPIO_1[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[25]
+set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to GPIO_0[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[28]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to GPIO_0[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_0[35]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[10]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[11]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[12]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[13]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[14]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[15]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[16]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[17]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[18]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[19]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[20]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[21]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[22]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[23]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[24]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[25]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[26]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[27]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[28]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[29]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[30]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[31]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[32]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[33]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[34]
+set_instance_assignment -name IO_STANDARD LVTTL -to GPIO_1[35]
+set_location_assignment PIN_L22 -to SW[0]
+set_location_assignment PIN_L21 -to SW[1]
+set_location_assignment PIN_M22 -to SW[2]
+set_location_assignment PIN_V12 -to SW[3]
+set_location_assignment PIN_W12 -to SW[4]
+set_location_assignment PIN_U12 -to SW[5]
+set_location_assignment PIN_U11 -to SW[6]
+set_location_assignment PIN_M2 -to SW[7]
+set_location_assignment PIN_M1 -to SW[8]
+set_location_assignment PIN_L2 -to SW[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to SW[9]
+set_location_assignment PIN_J2 -to HEX0[0]
+set_location_assignment PIN_J1 -to HEX0[1]
+set_location_assignment PIN_H2 -to HEX0[2]
+set_location_assignment PIN_H1 -to HEX0[3]
+set_location_assignment PIN_F2 -to HEX0[4]
+set_location_assignment PIN_F1 -to HEX0[5]
+set_location_assignment PIN_E2 -to HEX0[6]
+set_location_assignment PIN_E1 -to HEX1[0]
+set_location_assignment PIN_H6 -to HEX1[1]
+set_location_assignment PIN_H5 -to HEX1[2]
+set_location_assignment PIN_H4 -to HEX1[3]
+set_location_assignment PIN_G3 -to HEX1[4]
+set_location_assignment PIN_D2 -to HEX1[5]
+set_location_assignment PIN_D1 -to HEX1[6]
+set_location_assignment PIN_G5 -to HEX2[0]
+set_location_assignment PIN_G6 -to HEX2[1]
+set_location_assignment PIN_C2 -to HEX2[2]
+set_location_assignment PIN_C1 -to HEX2[3]
+set_location_assignment PIN_E3 -to HEX2[4]
+set_location_assignment PIN_E4 -to HEX2[5]
+set_location_assignment PIN_D3 -to HEX2[6]
+set_location_assignment PIN_F4 -to HEX3[0]
+set_location_assignment PIN_D5 -to HEX3[1]
+set_location_assignment PIN_D6 -to HEX3[2]
+set_location_assignment PIN_J4 -to HEX3[3]
+set_location_assignment PIN_L8 -to HEX3[4]
+set_location_assignment PIN_F3 -to HEX3[5]
+set_location_assignment PIN_D4 -to HEX3[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX0[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX1[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX2[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to HEX3[6]
+set_location_assignment PIN_R22 -to KEY[0]
+set_location_assignment PIN_R21 -to KEY[1]
+set_location_assignment PIN_T22 -to KEY[2]
+set_location_assignment PIN_T21 -to KEY[3]
+set_location_assignment PIN_R20 -to LEDR[0]
+set_location_assignment PIN_R19 -to LEDR[1]
+set_location_assignment PIN_U19 -to LEDR[2]
+set_location_assignment PIN_Y19 -to LEDR[3]
+set_location_assignment PIN_T18 -to LEDR[4]
+set_location_assignment PIN_V19 -to LEDR[5]
+set_location_assignment PIN_Y18 -to LEDR[6]
+set_location_assignment PIN_U18 -to LEDR[7]
+set_location_assignment PIN_R18 -to LEDR[8]
+set_location_assignment PIN_R17 -to LEDR[9]
+set_location_assignment PIN_U22 -to LEDG[0]
+set_location_assignment PIN_U21 -to LEDG[1]
+set_location_assignment PIN_V22 -to LEDG[2]
+set_location_assignment PIN_V21 -to LEDG[3]
+set_location_assignment PIN_W22 -to LEDG[4]
+set_location_assignment PIN_W21 -to LEDG[5]
+set_location_assignment PIN_Y22 -to LEDG[6]
+set_location_assignment PIN_Y21 -to LEDG[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to KEY[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[7]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[8]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDR[9]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[4]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[5]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[6]
+set_instance_assignment -name IO_STANDARD LVTTL -to LEDG[7]
+set_location_assignment PIN_D12 -to CLOCK_27[0]
+set_location_assignment PIN_E12 -to CLOCK_27[1]
+set_location_assignment PIN_B12 -to CLOCK_24[0]
+set_location_assignment PIN_A12 -to CLOCK_24[1]
+set_location_assignment PIN_L1 -to CLOCK_50
+set_location_assignment PIN_M21 -to EXT_CLOCK
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_27[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_24[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to CLOCK_50
+set_instance_assignment -name IO_STANDARD LVTTL -to EXT_CLOCK
+set_location_assignment PIN_H15 -to PS2_CLK
+set_location_assignment PIN_J14 -to PS2_DAT
+set_location_assignment PIN_F14 -to UART_RXD
+set_location_assignment PIN_G12 -to UART_TXD
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_CLK
+set_instance_assignment -name IO_STANDARD LVTTL -to PS2_DAT
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_RXD
+set_instance_assignment -name IO_STANDARD LVTTL -to UART_TXD
+set_location_assignment PIN_E8 -to TDI
+set_location_assignment PIN_D8 -to TCS
+set_location_assignment PIN_C7 -to TCK
+set_location_assignment PIN_D7 -to TDO
+set_instance_assignment -name IO_STANDARD LVTTL -to TDI
+set_instance_assignment -name IO_STANDARD LVTTL -to TCS
+set_instance_assignment -name IO_STANDARD LVTTL -to TCK
+set_instance_assignment -name IO_STANDARD LVTTL -to TDO
+set_location_assignment PIN_D9 -to VGA_R[0]
+set_location_assignment PIN_C9 -to VGA_R[1]
+set_location_assignment PIN_A7 -to VGA_R[2]
+set_location_assignment PIN_B7 -to VGA_R[3]
+set_location_assignment PIN_B8 -to VGA_G[0]
+set_location_assignment PIN_C10 -to VGA_G[1]
+set_location_assignment PIN_B9 -to VGA_G[2]
+set_location_assignment PIN_A8 -to VGA_G[3]
+set_location_assignment PIN_A9 -to VGA_B[0]
+set_location_assignment PIN_D11 -to VGA_B[1]
+set_location_assignment PIN_A10 -to VGA_B[2]
+set_location_assignment PIN_B10 -to VGA_B[3]
+set_location_assignment PIN_A11 -to VGA_HS
+set_location_assignment PIN_B11 -to VGA_VS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_R[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_G[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[0]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[1]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[2]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_B[3]
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_HS
+set_instance_assignment -name IO_STANDARD LVTTL -to VGA_VS
+set_location_assignment PIN_A3 -to I2C_SCLK
+set_location_assignment PIN_B3 -to I2C_SDAT
+set_location_assignment PIN_A6 -to AUD_ADCLRCK
+set_location_assignment PIN_B6 -to AUD_ADCDAT
+set_location_assignment PIN_A5 -to AUD_DACLRCK
+set_location_assignment PIN_B5 -to AUD_DACDAT
+set_location_assignment PIN_B4 -to AUD_XCK
+set_location_assignment PIN_A4 -to AUD_BCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SCLK
+set_instance_assignment -name IO_STANDARD LVTTL -to I2C_SDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_ADCDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACLRCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_DACDAT
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_XCK
+set_instance_assignment -name IO_STANDARD LVTTL -to AUD_BCLK
+set_location_assignment PIN_W4 -to DRAM_ADDR[0]
+set_location_assignment PIN_W5 -to DRAM_ADDR[1]
+set_location_assignment PIN_Y3 -to DRAM_ADDR[2]
+set_location_assignment PIN_Y4 -to DRAM_ADDR[3]
+set_location_assignment PIN_R6 -to DRAM_ADDR[4]
+set_location_assignment PIN_R5 -to DRAM_ADDR[5]
+set_location_assignment PIN_P6 -to DRAM_ADDR[6]
+set_location_assignment PIN_P5 -to DRAM_ADDR[7]
+set_location_assignment PIN_P3 -to DRAM_ADDR[8]
+set_location_assignment PIN_N4 -to DRAM_ADDR[9]
+set_location_assignment PIN_W3 -to DRAM_ADDR[10]
+set_location_assignment PIN_N6 -to DRAM_ADDR[11]
+set_location_assignment PIN_U3 -to DRAM_BA_0
+set_location_assignment PIN_V4 -to DRAM_BA_1
+set_location_assignment PIN_T3 -to DRAM_CAS_N
+set_location_assignment PIN_N3 -to DRAM_CKE
+set_location_assignment PIN_U4 -to DRAM_CLK
+set_location_assignment PIN_T6 -to DRAM_CS_N
+set_location_assignment PIN_U1 -to DRAM_DQ[0]
+set_location_assignment PIN_U2 -to DRAM_DQ[1]
+set_location_assignment PIN_V1 -to DRAM_DQ[2]
+set_location_assignment PIN_V2 -to DRAM_DQ[3]
+set_location_assignment PIN_W1 -to DRAM_DQ[4]
+set_location_assignment PIN_W2 -to DRAM_DQ[5]
+set_location_assignment PIN_Y1 -to DRAM_DQ[6]
+set_location_assignment PIN_Y2 -to DRAM_DQ[7]
+set_location_assignment PIN_N1 -to DRAM_DQ[8]
+set_location_assignment PIN_N2 -to DRAM_DQ[9]
+set_location_assignment PIN_P1 -to DRAM_DQ[10]
+set_location_assignment PIN_P2 -to DRAM_DQ[11]
+set_location_assignment PIN_R1 -to DRAM_DQ[12]
+set_location_assignment PIN_R2 -to DRAM_DQ[13]
+set_location_assignment PIN_T1 -to DRAM_DQ[14]
+set_location_assignment PIN_T2 -to DRAM_DQ[15]
+set_location_assignment PIN_R7 -to DRAM_LDQM
+set_location_assignment PIN_T5 -to DRAM_RAS_N
+set_location_assignment PIN_M5 -to DRAM_UDQM
+set_location_assignment PIN_R8 -to DRAM_WE_N
+set_location_assignment PIN_AB20 -to FL_ADDR[0]
+set_location_assignment PIN_AA14 -to FL_ADDR[1]
+set_location_assignment PIN_Y16 -to FL_ADDR[2]
+set_location_assignment PIN_R15 -to FL_ADDR[3]
+set_location_assignment PIN_T15 -to FL_ADDR[4]
+set_location_assignment PIN_U15 -to FL_ADDR[5]
+set_location_assignment PIN_V15 -to FL_ADDR[6]
+set_location_assignment PIN_W15 -to FL_ADDR[7]
+set_location_assignment PIN_R14 -to FL_ADDR[8]
+set_location_assignment PIN_Y13 -to FL_ADDR[9]
+set_location_assignment PIN_R12 -to FL_ADDR[10]
+set_location_assignment PIN_T12 -to FL_ADDR[11]
+set_location_assignment PIN_AB14 -to FL_ADDR[12]
+set_location_assignment PIN_AA13 -to FL_ADDR[13]
+set_location_assignment PIN_AB13 -to FL_ADDR[14]
+set_location_assignment PIN_AA12 -to FL_ADDR[15]
+set_location_assignment PIN_AB12 -to FL_ADDR[16]
+set_location_assignment PIN_AA20 -to FL_ADDR[17]
+set_location_assignment PIN_U14 -to FL_ADDR[18]
+set_location_assignment PIN_V14 -to FL_ADDR[19]
+set_location_assignment PIN_U13 -to FL_ADDR[20]
+set_location_assignment PIN_R13 -to FL_ADDR[21]
+set_location_assignment PIN_AB16 -to FL_DQ[0]
+set_location_assignment PIN_AA16 -to FL_DQ[1]
+set_location_assignment PIN_AB17 -to FL_DQ[2]
+set_location_assignment PIN_AA17 -to FL_DQ[3]
+set_location_assignment PIN_AB18 -to FL_DQ[4]
+set_location_assignment PIN_AA18 -to FL_DQ[5]
+set_location_assignment PIN_AB19 -to FL_DQ[6]
+set_location_assignment PIN_AA19 -to FL_DQ[7]
+set_location_assignment PIN_AA15 -to FL_OE_N
+set_location_assignment PIN_W14 -to FL_RST_N
+set_location_assignment PIN_Y14 -to FL_WE_N
+set_location_assignment PIN_AA3 -to SRAM_ADDR[0]
+set_location_assignment PIN_AB3 -to SRAM_ADDR[1]
+set_location_assignment PIN_AA4 -to SRAM_ADDR[2]
+set_location_assignment PIN_AB4 -to SRAM_ADDR[3]
+set_location_assignment PIN_AA5 -to SRAM_ADDR[4]
+set_location_assignment PIN_AB10 -to SRAM_ADDR[5]
+set_location_assignment PIN_AA11 -to SRAM_ADDR[6]
+set_location_assignment PIN_AB11 -to SRAM_ADDR[7]
+set_location_assignment PIN_V11 -to SRAM_ADDR[8]
+set_location_assignment PIN_W11 -to SRAM_ADDR[9]
+set_location_assignment PIN_R11 -to SRAM_ADDR[10]
+set_location_assignment PIN_T11 -to SRAM_ADDR[11]
+set_location_assignment PIN_Y10 -to SRAM_ADDR[12]
+set_location_assignment PIN_U10 -to SRAM_ADDR[13]
+set_location_assignment PIN_R10 -to SRAM_ADDR[14]
+set_location_assignment PIN_T7 -to SRAM_ADDR[15]
+set_location_assignment PIN_Y6 -to SRAM_ADDR[16]
+set_location_assignment PIN_Y5 -to SRAM_ADDR[17]
+set_location_assignment PIN_AB5 -to SRAM_CE_N
+set_location_assignment PIN_AA6 -to SRAM_DQ[0]
+set_location_assignment PIN_AB6 -to SRAM_DQ[1]
+set_location_assignment PIN_AA7 -to SRAM_DQ[2]
+set_location_assignment PIN_AB7 -to SRAM_DQ[3]
+set_location_assignment PIN_AA8 -to SRAM_DQ[4]
+set_location_assignment PIN_AB8 -to SRAM_DQ[5]
+set_location_assignment PIN_AA9 -to SRAM_DQ[6]
+set_location_assignment PIN_AB9 -to SRAM_DQ[7]
+set_location_assignment PIN_Y9 -to SRAM_DQ[8]
+set_location_assignment PIN_W9 -to SRAM_DQ[9]
+set_location_assignment PIN_V9 -to SRAM_DQ[10]
+set_location_assignment PIN_U9 -to SRAM_DQ[11]
+set_location_assignment PIN_R9 -to SRAM_DQ[12]
+set_location_assignment PIN_W8 -to SRAM_DQ[13]
+set_location_assignment PIN_V8 -to SRAM_DQ[14]
+set_location_assignment PIN_U8 -to SRAM_DQ[15]
+set_location_assignment PIN_Y7 -to SRAM_LB_N
+set_location_assignment PIN_T8 -to SRAM_OE_N
+set_location_assignment PIN_W7 -to SRAM_UB_N
+set_location_assignment PIN_AA10 -to SRAM_WE_N
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_V20 -to SD_CLK
+set_location_assignment PIN_Y20 -to SD_CMD
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_location_assignment PIN_W20 -to SD_DATA
+set_location_assignment PIN_U20 -to SD_THREE
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE i2s_intf.vhd
+set_global_assignment -name VHDL_FILE i2c_loader.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name VHDL_FILE ledsw.vhd
+set_global_assignment -name VHDL_FILE hexdecoder.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE dumprom.vhdl
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE i2sslave.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE nmigen.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE tvsync.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE flashrom.vhdl
+set_global_assignment -name VHDL_FILE sram.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE gpio.vhd
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_location_assignment PIN_A13 -to GPIO_0[0]
+set_location_assignment PIN_B13 -to GPIO_0[1]
+set_location_assignment PIN_A14 -to GPIO_0[2]
+set_location_assignment PIN_B14 -to GPIO_0[3]
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
Index: unmerged/core/mist/atari800core.sdc.bak
===================================================================
--- unmerged/core/mist/atari800core.sdc.bak	(nonexistent)
+++ unmerged/core/mist/atari800core.sdc.bak	(revision 1)
@@ -0,0 +1,2 @@
+create_clock -period 50MHz [get_ports CLOCK_50]
+derive_pll_clocks
\ No newline at end of file
Index: unmerged/core/mist/atari800core.sdc
===================================================================
--- unmerged/core/mist/atari800core.sdc	(nonexistent)
+++ unmerged/core/mist/atari800core.sdc	(revision 1)
@@ -0,0 +1,3 @@
+create_clock -period 27MHz [get_ports CLOCK_27[0]]
+derive_pll_clocks
+derive_clock_uncertainty
\ No newline at end of file
Index: unmerged/core/mist/atari800core_assignment_defaults.qdf
===================================================================
--- unmerged/core/mist/atari800core_assignment_defaults.qdf	(nonexistent)
+++ unmerged/core/mist/atari800core_assignment_defaults.qdf	(revision 1)
@@ -0,0 +1,796 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition
+# Date created = 09:08:15  February 16, 2014
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name SMART_RECOMPILE Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Cyclone
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family Stratix
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000B
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000AE
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family Cyclone
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX7000S
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix III"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family MAX3000A
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family Stratix
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000B
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "HardCopy II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000AE
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Cyclone
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX7000S
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Cyclone II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "HardCopy IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone III LS"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix III"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Arria GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family MAX3000A
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "Stratix II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family Stratix
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone IV GX"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Cyclone II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "HardCopy II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "HardCopy IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix III"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Night Fury"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Arria GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS Off -family "Stratix II"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Night Fury"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Cyclone
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "HardCopy III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "HardCopy IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone III LS"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix III"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Arria GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Stratix II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family Stratix
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "HardCopy IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III LS"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix III"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Night Fury"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Cyclone
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix II"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family Stratix
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name SYNTHESIS_SEED 1
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Cyclone II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family Cyclone
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "HardCopy II"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Arria GX"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "Use as regular IO" -family "Stratix II"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix III"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Night Fury"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Cyclone
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "Stratix II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family Stratix
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000B
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Night Fury"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000AE
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Cyclone
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "Stratix GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX7000S
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "HardCopy IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone III LS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix III"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family MAX3000A
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family Stratix
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING "Force All Tiles with Failing Timing Paths to High Speed"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAXII AUTO
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS Off
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIX AUTO
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION AUTO
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION AUTO
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Night Fury"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "HardCopy III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone III LS"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Stratix III"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Night Fury"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT LOW
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000B
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "HardCopy II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000AE
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Cyclone
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX7000S
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Cyclone II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "HardCopy IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone III LS"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix III"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Arria GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family MAX3000A
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "Stratix II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family Stratix
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
Index: unmerged/core/mist/basic.vhd
===================================================================
--- unmerged/core/mist/basic.vhd	(nonexistent)
+++ unmerged/core/mist/basic.vhd	(revision 1)
@@ -0,0 +1,169 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: basic.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY basic IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END basic;
+
+
+ARCHITECTURE SYN OF basic IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "ataribas.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 8192,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 13,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "ataribas.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "ataribas.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL basic.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL basic.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL basic.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL basic.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL basic_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/covox.vhd.bak
===================================================================
--- unmerged/core/mist/covox.vhd.bak	(nonexistent)
+++ unmerged/core/mist/covox.vhd.bak	(revision 1)
@@ -0,0 +1,85 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END reg_file;
+
+ARCHITECTURE vhdl OF reg_file IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+
+	type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
+
+	signal digit_next : reg_file_type;
+	signal digit_reg : reg_file_type;
+	
+	signal addr_decoded : std_logic_vector(2**width-1 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => WIDTH)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(digit_reg,addr_decoded,data_in,WR_EN)
+	begin
+		digit_next <= digit_reg;
+		
+		if (WR_EN = '1') then		
+			comp_gen:
+			for i in 0 to (BYTES-1) loop
+				if (addr_decoded(i) = '1') then				
+					digit_next(i) <= data_in;
+				end if;
+			end loop;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	-- output
+	process(addr_decoded,digit_reg)
+	begin
+		data_out <= X"FF";
+		comp_gen:
+		for i in 0 to (BYTES-1) loop
+			if (addr_decoded(i) = '1') then				
+				data_out <= digit_reg(i);
+			end if;
+		end loop;	
+	end process;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/cpu_65xx_a.vhd.bak
===================================================================
--- unmerged/core/mist/cpu_65xx_a.vhd.bak	(nonexistent)
+++ unmerged/core/mist/cpu_65xx_a.vhd.bak	(revision 1)
@@ -0,0 +1,1599 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processNmi : std_logic := '0';
+	signal processIrq : std_logic := '0';
+	signal processInt : std_logic := '0';
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal so_reg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAX  & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluInp, -- AB iLXA imm
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal Creg: std_logic; -- Carry
+	signal Zreg: std_logic; -- Zero flag
+	signal Ireg: std_logic; -- Interrupt flag
+	signal Dreg: std_logic; -- Decimal mode
+	signal Vreg: std_logic; -- Overflow
+	signal Nreg: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := Creg & aluInput;
+		when aluModeP =>
+			rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
+		when aluModeInc =>
+			rmwBits := Creg & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := Creg & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & Creg;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := Creg & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if Dreg = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if Dreg = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if Dreg = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if Dreg = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then -- and (halt = '0') then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+					
+					if theCpuCycle = cycleStack4 -- MWW
+					or reset = '1' then
+						nmiReg <= '1';
+					end if;					
+				if halt = '0' then
+					if theCpuCycle /= cycleBranchTaken then
+						-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+						-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+						processNmi <= not (nmiReg or opcInfo(opcIRQ));
+						processIrq <= not (irqReg or opcInfo(opcIRQ));
+					end if;
+				end if;
+			end if;
+			processInt <= processNmi or (processIrq and (not Ireg));
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, d, reset, processInt)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := d;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processInt = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processInt = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, halt, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if (enable = '1') and (halt = '0') then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= d;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= d;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= d;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					Creg <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Zreg <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					Ireg <= aluInput(2);
+				end if;
+			end if;
+			-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
+			if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
+				if (theOpcode = X"58") then
+					Ireg <= '0';
+				end if;
+				if (theOpcode = X"78") then
+					Ireg <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					Dreg <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					Vreg <= aluV;
+				end if;
+			end if;
+			if so_reg = '1' and so_n = '0' then
+				Vreg <= '1';
+			end if;
+			so_reg <= so_n;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					Nreg <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if (enable = '1') and (halt = '0') then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					q <= T; -- Read-modify-write write old value first.
+					doReg <= d; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	q <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+				if reset = '1' then
+					theWe <= '0';
+				end if;
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else
+							PC <= myAddr;
+						end if;
+					end if;
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when opcodeFetch =>
+			if processInt = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else
+				nextAddr <= nextAddrAbsIndexed;
+			end if;
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then
+				halt_dly <= halt;
+			end if;
+			if (enable = '1') and (halt = '0') then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
+--				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= d & T;
+				when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & d;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+			if (enable = '1') and (halt_dly = '0') then
+				case nextAddr is
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
+					else myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
+
+end architecture;
+
+
Index: unmerged/core/mist/data_io.vhdl.bak
===================================================================
--- unmerged/core/mist/data_io.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/data_io.vhdl.bak	(revision 1)
@@ -0,0 +1,91 @@
+module data_io(
+	   input      SPI_CLK,
+	   input      SPI_SS_IO,
+	   output     reg SPI_MISO,
+	   input      SPI_MOSI,
+	   input [7:0] CORE_TYPE,
+		output [5:0] JOY0,
+		output [5:0] JOY1,
+		output [127:0] KEYBOARD,		
+		output [1:0] BUTTONS,
+		output [1:0] SWITCHES
+	   );
+
+   reg [6:0]         sbuf;
+   reg [7:0]         cmd;
+   reg [7:0] 	      cnt;
+   reg [5:0]         joystick0;
+   reg [5:0]         joystick1;
+	reg [119:0]       keyboard;
+	reg [127:0]       keyboard_out;	
+   reg [3:0] 	      but_sw;
+
+	assign JOY0 = joystick0;
+	assign JOY1 = joystick1;
+	assign KEYBOARD = keyboard_out;
+	assign BUTTONS = but_sw[1:0];
+	assign SWITCHES = but_sw[3:2];
+   
+   always@(negedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+		   SPI_MISO <= 1'bZ;
+		end else begin
+	      if(cnt < 8) begin
+			  SPI_MISO <= CORE_TYPE[7-cnt];
+			end else begin
+		     SPI_MISO <= 1'bZ;
+			end
+	   end
+	end
+		
+   always@(posedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+        cnt <= 0;
+		end else begin
+			sbuf[6:1] <= sbuf[5:0];
+			sbuf[0] <= SPI_MOSI;
+
+			cnt <= cnt + 1;
+
+	      if(cnt == 7) begin
+			   cmd[7:1] <= sbuf; 
+				cmd[0] <= SPI_MOSI;
+		   end	
+
+	      if(cnt == 15) begin
+			   if(cmd == 1) begin
+					 but_sw[3:1] <= sbuf[2:0]; 
+					 but_sw[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 2) begin
+					 joystick0[5:1] <= sbuf[4:0]; 
+					 joystick0[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 3) begin
+					 joystick1[5:1] <= sbuf[4:0]; 
+					 joystick1[0] <= SPI_MOSI; 
+				end			
+			end	
+			
+			// 15,23,31,39,47,55,63,71
+			if (cnt[2:0]==7) begin
+			   if(cmd == 5) begin
+					if (!cnt[7]) begin
+					 keyboard[111:0] <= keyboard[119:8];
+					 keyboard[119:113] <= sbuf[6:0]; 
+					 keyboard[112] <= SPI_MOSI; 
+					end
+					if (cnt[7]) begin
+					 keyboard_out[119:0] <= keyboard[119:0];
+					 keyboard_out[127:121] <= sbuf[6:0]; 
+					 keyboard_out[120] <= SPI_MOSI; 					
+					end
+				end
+			end
+		end
+   end		
+//   always@(posedge clk2) begin
+//      LED <= ~LED;
+//   end
+   
+endmodule
Index: unmerged/core/mist/flashrom.vhdl
===================================================================
--- unmerged/core/mist/flashrom.vhdl	(nonexistent)
+++ unmerged/core/mist/flashrom.vhdl	(revision 1)
@@ -0,0 +1,63 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY flashrom IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+
+	ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+	
+	REQUEST : IN STD_LOGIC;
+
+	-- takes 90+ns, wait states handled here
+	
+	-- Flash interface
+	FLASH_D : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	FLASH_CE_N : OUT STD_LOGIC;
+	FLASH_OE_N : OUT STD_LOGIC;
+	FLASH_WE_N : OUT STD_LOGIC;
+	FLASH_RESET_N : OUT STD_LOGIC;
+	FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	COMPLETE : OUT STD_LOGIC
+);
+
+END flashrom;
+
+ARCHITECTURE vhdl OF flashrom IS
+	signal complete_next : std_logic_vector(4 downto 0); --56MHZ, 17ns per cycle.
+	signal complete_reg : std_logic_vector(4 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			complete_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			complete_reg <= complete_next;
+		end if;
+	end process;
+	
+	complete_next <= request&complete_reg(complete_reg'left downto 1);
+
+	FLASH_CE_N <= '0';
+	FLASH_OE_N <= '0';
+	FLASH_WE_N <= '1';
+	FLASH_RESET_N <= RESET_N;
+	FLASH_ADDRESS <= ADDRESS;
+	
+	DOUT <= FLASH_D;
+	COMPLETE <= complete_reg(0);
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/gtia.vhdl
===================================================================
--- unmerged/core/mist/gtia.vhdl	(nonexistent)
+++ unmerged/core/mist/gtia.vhdl	(revision 1)
@@ -0,0 +1,1556 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	CPU_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_MEMORY_READY : IN STD_LOGIC;
+	ANTIC_FETCH : IN STD_LOGIC;
+	
+	CPU_ENABLE_ORIGINAL : in std_logic;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	PAL : IN STD_LOGIC;
+	
+	-- ANTIC interface
+	COLOUR_CLOCK_ORIGINAL : in std_logic;
+	COLOUR_CLOCK : in std_logic;
+	COLOUR_CLOCK_HIGHRES : in std_logic;
+	AN : IN STD_LOGIC_VECTOR(2 downto 0);
+	
+	-- keyboard interface
+	CONSOL_START : IN STD_LOGIC;
+	CONSOL_SELECT : IN STD_LOGIC;
+	CONSOL_OPTION : IN STD_LOGIC;
+	
+	-- keyboard interface
+	TRIG0 : IN STD_LOGIC;
+	TRIG1 : IN STD_LOGIC;
+	TRIG2 : IN STD_LOGIC;
+	TRIG3 : IN STD_LOGIC;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	-- TO scandoubler...
+	COLOUR_out : out std_logic_vector(7 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic;
+	
+	-- To speaker
+	sound : out std_logic
+);
+END gtia;
+
+ARCHITECTURE vhdl OF gtia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component simple_counter IS
+	generic
+	(
+		COUNT_WIDTH : natural := 1
+	);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_n : IN STD_LOGIC;
+		increment : in std_logic;
+		load : IN STD_LOGIC;
+		load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+		current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	component wide_delay_line IS
+	generic(COUNT : natural := 1; WIDTH : natural :=1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+	);
+	END component;
+	
+	component gtia_player IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : in std_logic;
+		
+		COLOUR_ENABLE : IN STD_LOGIC;
+		LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+		PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+		SIZE : in std_logic_vector(1 downto 0);
+		bitmap : in std_logic_vector(7 downto 0);
+		
+		output : out std_logic
+	);
+	END component;
+	
+	component gtia_priority IS
+	PORT 
+	( 
+		CLK : in std_logic;
+		colour_enable : in std_logic;
+		PRIOR : in std_logic_vector(7 downto 0);
+		P0 : in std_logic;
+		P1 : in std_logic;
+		P2	: in std_logic;
+		P3 : in std_logic;
+		PF0 : in std_logic;
+		PF1 : in std_logic;
+		PF2 : in std_logic;
+		PF3 : in std_logic;
+		BK : in std_logic;
+		
+		P0_OUT : out std_logic;
+		P1_OUT : out std_logic;
+		P2_OUT : out std_logic;
+		P3_OUT : out std_logic;
+		PF0_OUT : out std_logic;
+		PF1_OUT : out std_logic;
+		PF2_OUT : out std_logic;
+		PF3_OUT : out std_logic;
+		BK_OUT : out std_logic
+	);
+	END component;	
+	
+	signal addr_decoded : std_logic_vector(31 downto 0);
+	
+	signal hposp0_raw_next : std_logic_vector(7 downto 0);
+	signal hposp0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp1_raw_next : std_logic_vector(7 downto 0);
+	signal hposp1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp2_raw_next : std_logic_vector(7 downto 0);
+	signal hposp2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp3_raw_next : std_logic_vector(7 downto 0);
+	signal hposp3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposp0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposp3_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal hposm0_raw_next : std_logic_vector(7 downto 0);
+	signal hposm0_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm1_raw_next : std_logic_vector(7 downto 0);
+	signal hposm1_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm2_raw_next : std_logic_vector(7 downto 0);
+	signal hposm2_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm3_raw_next : std_logic_vector(7 downto 0);
+	signal hposm3_raw_reg : std_logic_vector(7 downto 0);
+	signal hposm0_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm1_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm2_delayed_reg : std_logic_vector(7 downto 0);
+	signal hposm3_delayed_reg : std_logic_vector(7 downto 0);	
+	
+	signal sizep0_raw_next : std_logic_vector(1 downto 0);
+	signal sizep0_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep1_raw_next : std_logic_vector(1 downto 0);
+	signal sizep1_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep2_raw_next : std_logic_vector(1 downto 0);
+	signal sizep2_raw_reg : std_logic_vector(1 downto 0);
+	signal sizep3_raw_next : std_logic_vector(1 downto 0);
+	signal sizep3_raw_reg : std_logic_vector(1 downto 0);
+
+	signal sizem_raw_next : std_logic_vector(7 downto 0);
+	signal sizem_raw_reg : std_logic_vector(7 downto 0);
+
+	signal sizep0_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep1_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep2_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizep3_delayed_reg : std_logic_vector(1 downto 0);
+	signal sizem_delayed_reg : std_logic_vector(7 downto 0);
+	
+	signal grafp0_next : std_logic_vector(7 downto 0);
+	signal grafp0_reg : std_logic_vector(7 downto 0);
+	signal grafp1_next : std_logic_vector(7 downto 0);
+	signal grafp1_reg : std_logic_vector(7 downto 0);
+	signal grafp2_next : std_logic_vector(7 downto 0);
+	signal grafp2_reg : std_logic_vector(7 downto 0);
+	signal grafp3_next : std_logic_vector(7 downto 0);
+	signal grafp3_reg : std_logic_vector(7 downto 0);
+	
+	signal grafm_next : std_logic_vector(7 downto 0);
+	signal grafm_reg : std_logic_vector(7 downto 0);
+
+	signal colpm0_raw_next : std_logic_vector(7 downto 1);
+	signal colpm0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm1_raw_next : std_logic_vector(7 downto 1);
+	signal colpm1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm2_raw_next : std_logic_vector(7 downto 1);
+	signal colpm2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm3_raw_next : std_logic_vector(7 downto 1);
+	signal colpm3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpm0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpm3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colpf0_raw_next : std_logic_vector(7 downto 1);
+	signal colpf0_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf1_raw_next : std_logic_vector(7 downto 1);
+	signal colpf1_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf2_raw_next : std_logic_vector(7 downto 1);
+	signal colpf2_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf3_raw_next : std_logic_vector(7 downto 1);
+	signal colpf3_raw_reg : std_logic_vector(7 downto 1);
+	signal colpf0_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf1_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf2_delayed_reg : std_logic_vector(7 downto 1);
+	signal colpf3_delayed_reg : std_logic_vector(7 downto 1);
+	
+	signal colbk_raw_next : std_logic_vector(7 downto 1);
+	signal colbk_raw_reg : std_logic_vector(7 downto 1);
+	signal colbk_delayed_reg : std_logic_vector(7 downto 1);	
+	
+	signal prior_raw_next : std_logic_vector(7 downto 0);
+	signal prior_raw_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed_reg : std_logic_vector(7 downto 0);
+	signal prior_delayed2_reg : std_logic_vector(7 downto 6);
+	
+	signal vdelay_next : std_logic_vector(7 downto 0);
+	signal vdelay_reg : std_logic_vector(7 downto 0);
+
+	signal gractl_next : std_logic_vector(2 downto 0);
+	signal gractl_reg : std_logic_vector(2 downto 0);
+	
+	signal consol_output_next : std_logic_vector(3 downto 0);
+	signal consol_output_reg : std_logic_vector(3 downto 0);
+	
+	signal trig0_next : std_logic;
+	signal trig0_reg : std_logic;
+	signal trig1_next : std_logic;
+	signal trig1_reg : std_logic;
+	signal trig2_next : std_logic;
+	signal trig2_reg : std_logic;
+	signal trig3_next : std_logic;
+	signal trig3_reg : std_logic;
+	
+	-- collisions
+	signal hitclr_write : std_logic;
+	
+	signal m0pf_next : std_logic_vector(3 downto 0);
+	signal m0pf_reg : std_logic_vector(3 downto 0);
+	signal m1pf_next : std_logic_vector(3 downto 0);
+	signal m1pf_reg : std_logic_vector(3 downto 0);
+	signal m2pf_next : std_logic_vector(3 downto 0);
+	signal m2pf_reg : std_logic_vector(3 downto 0);
+	signal m3pf_next : std_logic_vector(3 downto 0);
+	signal m3pf_reg : std_logic_vector(3 downto 0);
+
+	signal m0pl_next : std_logic_vector(3 downto 0);
+	signal m0pl_reg : std_logic_vector(3 downto 0);
+	signal m1pl_next : std_logic_vector(3 downto 0);
+	signal m1pl_reg : std_logic_vector(3 downto 0);
+	signal m2pl_next : std_logic_vector(3 downto 0);
+	signal m2pl_reg : std_logic_vector(3 downto 0);
+	signal m3pl_next : std_logic_vector(3 downto 0);
+	signal m3pl_reg : std_logic_vector(3 downto 0);
+	
+	signal p0pf_next : std_logic_vector(3 downto 0);
+	signal p0pf_reg : std_logic_vector(3 downto 0);
+	signal p1pf_next : std_logic_vector(3 downto 0);
+	signal p1pf_reg : std_logic_vector(3 downto 0);
+	signal p2pf_next : std_logic_vector(3 downto 0);
+	signal p2pf_reg : std_logic_vector(3 downto 0);
+	signal p3pf_next : std_logic_vector(3 downto 0);
+	signal p3pf_reg : std_logic_vector(3 downto 0);	
+	
+	signal p0pl_next : std_logic_vector(3 downto 0);
+	signal p0pl_reg : std_logic_vector(3 downto 0);
+	signal p1pl_next : std_logic_vector(3 downto 0);
+	signal p1pl_reg : std_logic_vector(3 downto 0);
+	signal p2pl_next : std_logic_vector(3 downto 0);
+	signal p2pl_reg : std_logic_vector(3 downto 0);
+	signal p3pl_next : std_logic_vector(3 downto 0);
+	signal p3pl_reg : std_logic_vector(3 downto 0);		
+	
+	-- priority
+	signal set_p0 : std_logic;
+	signal set_p1 : std_logic;
+	signal set_p2 : std_logic;
+	signal set_p3 : std_logic;
+	signal set_pf0 : std_logic;
+	signal set_pf1 : std_logic;
+	signal set_pf2 : std_logic;
+	signal set_pf3 : std_logic;
+	signal set_bk : std_logic;	
+	
+	-- ouput/sync
+	signal COLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal COLOUR_REG : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_NEXT : std_logic_vector(7 downto 0);
+	signal HRCOLOUR_REG : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+	
+	signal hsync_start : std_logic;
+	signal hsync_end : std_logic;
+	
+	signal hblank_next : std_logic;
+	signal hblank_reg : std_logic;
+	
+	-- visible region (no collision detection outside this)
+	signal visible_live : std_logic;
+	
+	-- antic input decode
+	signal an_prev3_next : std_logic_vector(2 downto 0);
+	signal an_prev3_reg : std_logic_vector(2 downto 0);	
+	signal an_prev2_next : std_logic_vector(2 downto 0);
+	signal an_prev2_reg : std_logic_vector(2 downto 0);	
+	signal an_prev_next : std_logic_vector(2 downto 0);
+	signal an_prev_reg : std_logic_vector(2 downto 0);
+	
+	signal active_bk_modify_next : std_logic_vector(7 downto 0);
+	signal active_bk_modify_reg : std_logic_vector(7 downto 0);
+	signal active_bk_valid_next : std_logic_vector(7 downto 0);
+	signal active_bk_valid_reg : std_logic_vector(7 downto 0);
+	signal active_bk_live : std_logic;
+	signal active_pf0_live : std_logic;
+	signal active_pf1_live : std_logic;
+	signal active_pf2_live : std_logic;
+	signal active_pf2_collision_live : std_logic;
+	signal active_pf3_live : std_logic;
+	signal active_pf3_collision_live : std_logic;
+	signal active_pm0_live : std_logic;
+	signal active_pm1_live : std_logic;
+	signal active_pm2_live : std_logic;
+	signal active_pm3_live : std_logic;
+	
+	signal active_p0_live : std_logic;
+	signal active_p1_live : std_logic;
+	signal active_p2_live : std_logic;
+	signal active_p3_live : std_logic;
+	signal active_m0_live : std_logic;
+	signal active_m1_live : std_logic;
+	signal active_m2_live : std_logic;
+	signal active_m3_live : std_logic;
+	
+	signal active_hr_next : std_logic_vector(1 downto 0);
+	signal active_hr_reg : std_logic_vector(1 downto 0);
+	signal highres_next : std_logic;
+	signal highres_reg : std_logic;
+	
+	-- horizontal position counter
+	signal hpos_reg : std_logic_vector(7 downto 0);
+	signal reset_counter : std_logic;
+	signal counter_load_value : std_logic_vector(7 downto 0);
+	
+	-- sub colour clock highres mode	
+	signal trigger_secondhalf : std_logic;
+	
+	-- pmg dma
+	signal grafm_dma_load : std_logic;
+	signal grafm_dma_next : std_logic_vector(7 downto 0);
+	signal grafp0_dma_load : std_logic;
+	signal grafp0_dma_next : std_logic_vector(7 downto 0);
+	signal grafp1_dma_load : std_logic;
+	signal grafp1_dma_next : std_logic_vector(7 downto 0);
+	signal grafp2_dma_load : std_logic;
+	signal grafp2_dma_next : std_logic_vector(7 downto 0);
+	signal grafp3_dma_load : std_logic;
+	signal grafp3_dma_next : std_logic_vector(7 downto 0);
+	signal odd_scanline_next : std_logic;
+	signal odd_scanline_reg : std_logic;
+	
+	signal pmg_dma_state_next : std_logic_vector(2 downto 0);
+	signal pmg_dma_state_reg : std_logic_vector(2 downto 0);
+	constant pmg_dma_missile : std_logic_vector(2 downto 0) := "000";
+	constant pmg_dma_player0 : std_logic_vector(2 downto 0) := "001";
+	constant pmg_dma_player1 : std_logic_vector(2 downto 0) := "010";
+	constant pmg_dma_player2 : std_logic_vector(2 downto 0) := "011";
+	constant pmg_dma_player3 : std_logic_vector(2 downto 0) := "100";
+	constant pmg_dma_done    : std_logic_vector(2 downto 0) := "101";	
+	constant pmg_dma_instruction : std_logic_vector(2 downto 0) := "110";	
+	
+	signal memory_ready : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			hposp0_raw_reg <= (others=>'0');
+			hposp1_raw_reg <= (others=>'0');
+			hposp2_raw_reg <= (others=>'0');
+			hposp3_raw_reg <= (others=>'0');
+
+			hposm0_raw_reg <= (others=>'0');
+			hposm1_raw_reg <= (others=>'0');
+			hposm2_raw_reg <= (others=>'0');
+			hposm3_raw_reg <= (others=>'0');			
+
+			sizep0_raw_reg <= (others=>'0');
+			sizep1_raw_reg <= (others=>'0');
+			sizep2_raw_reg <= (others=>'0');
+			sizep3_raw_reg <= (others=>'0');
+
+			sizem_raw_reg <= (others=>'0');
+			
+			grafp0_reg <= (others=>'0');
+			grafp1_reg <= (others=>'0');
+			grafp2_reg <= (others=>'0');
+			grafp3_reg <= (others=>'0');
+
+			grafm_reg <= (others=>'0');
+			
+			colpm0_raw_reg <= (others=>'0');
+			colpm1_raw_reg <= (others=>'0');
+			colpm2_raw_reg <= (others=>'0');
+			colpm3_raw_reg <= (others=>'0');
+
+			colpf0_raw_reg <= (others=>'0');
+			colpf1_raw_reg <= (others=>'0');
+			colpf2_raw_reg <= (others=>'0');
+			colpf3_raw_reg <= (others=>'0');
+			
+			colbk_raw_reg <= (others=>'0');
+			
+			prior_raw_reg <= (others=>'0');
+			
+			vdelay_reg <= (others=>'0');
+			
+			gractl_reg <= (others=>'0');
+			
+			consol_output_reg <= (others=>'1');
+			
+			COLOUR_REG <= (OTHERS=>'0');
+			HRCOLOUR_REG <= (OTHERS=>'0');
+			
+			vsync_reg <= '0';
+			hsync_reg <= '0';
+			hblank_reg <= '0';
+			
+			an_prev_reg <= (others=>'0');
+			an_prev2_reg <= (others=>'0');
+			an_prev3_reg <= (others=>'0');
+			
+			highres_reg <= '0';
+			active_hr_reg <= (others=>'0');
+			
+			trig0_reg <= '0';
+			trig1_reg <= '0';
+			trig2_reg <= '0';
+			trig3_reg <= '0';
+			
+			odd_scanline_reg <= '0';
+			
+			pmg_dma_state_reg <= pmg_dma_done;
+			
+			m0pf_reg <= (others=>'0');
+			m1pf_reg <= (others=>'0');
+			m2pf_reg <= (others=>'0');
+			m3pf_reg <= (others=>'0');
+			m0pl_reg <= (others=>'0');
+			m1pl_reg <= (others=>'0');
+			m2pl_reg <= (others=>'0');
+			m3pl_reg <= (others=>'0');
+			
+			p0pf_reg <= (others=>'0');
+			p1pf_reg <= (others=>'0');
+			p2pf_reg <= (others=>'0');
+			p3pf_reg <= (others=>'0');
+			p0pl_reg <= (others=>'0');
+			p1pl_reg <= (others=>'0');
+			p2pl_reg <= (others=>'0');
+			p3pl_reg <= (others=>'0');	
+			
+			active_bk_modify_reg <= (others=>'0');
+			active_bk_valid_reg <= (others=>'0');
+			
+		elsif (clk'event and clk='1') then										
+			hposp0_raw_reg <= hposp0_raw_next;
+			hposp1_raw_reg <= hposp1_raw_next;
+			hposp2_raw_reg <= hposp2_raw_next;
+			hposp3_raw_reg <= hposp3_raw_next;
+
+			hposm0_raw_reg <= hposm0_raw_next;
+			hposm1_raw_reg <= hposm1_raw_next;
+			hposm2_raw_reg <= hposm2_raw_next;
+			hposm3_raw_reg <= hposm3_raw_next;			
+
+			sizep0_raw_reg <= sizep0_raw_next;
+			sizep1_raw_reg <= sizep1_raw_next;
+			sizep2_raw_reg <= sizep2_raw_next;
+			sizep3_raw_reg <= sizep3_raw_next;
+
+			sizem_raw_reg <= sizem_raw_next;
+			
+			grafp0_reg <= grafp0_next;
+			grafp1_reg <= grafp1_next;
+			grafp2_reg <= grafp2_next;
+			grafp3_reg <= grafp3_next;
+
+			grafm_reg <= grafm_next;
+			
+			colpm0_raw_reg <= colpm0_raw_next;
+			colpm1_raw_reg <= colpm1_raw_next;
+			colpm2_raw_reg <= colpm2_raw_next;
+			colpm3_raw_reg <= colpm3_raw_next;
+
+			colpf0_raw_reg <= colpf0_raw_next;
+			colpf1_raw_reg <= colpf1_raw_next;
+			colpf2_raw_reg <= colpf2_raw_next;
+			colpf3_raw_reg <= colpf3_raw_next;
+			
+			colbk_raw_reg <= colbk_raw_next;
+			
+			prior_raw_reg <= prior_raw_next;
+			
+			vdelay_reg <= vdelay_next;
+			
+			gractl_reg <= gractl_next;
+			
+			consol_output_reg <= consol_output_next;		
+
+			COLOUR_REG <= colour_next;
+			HRCOLOUR_REG <= hrcolour_next;
+			
+			vsync_reg <= vsync_next;
+			hsync_reg <= hsync_next;
+			hblank_reg <= hblank_next;
+			
+			an_prev_reg <= an_prev_next;
+			an_prev2_reg <= an_prev2_next;
+			an_prev3_reg <= an_prev3_next;
+	
+			highres_reg <= highres_next;
+			active_hr_reg <= active_hr_next;
+			
+			trig0_reg <= trig0_next;
+			trig1_reg <= trig1_next;
+			trig2_reg <= trig2_next;
+			trig3_reg <= trig3_next;
+			
+			odd_scanline_reg <= odd_scanline_next;
+			
+			pmg_dma_state_reg <= pmg_dma_state_next;
+			
+			m0pf_reg <= m0pf_next;
+			m1pf_reg <= m1pf_next;
+			m2pf_reg <= m2pf_next;
+			m3pf_reg <= m3pf_next;
+			m0pl_reg <= m0pl_next;
+			m1pl_reg <= m1pl_next;
+			m2pl_reg <= m2pl_next;
+			m3pl_reg <= m3pl_next;
+			
+			p0pf_reg <= p0pf_next;
+			p1pf_reg <= p1pf_next;
+			p2pf_reg <= p2pf_next;
+			p3pf_reg <= p3pf_next;
+			p0pl_reg <= p0pl_next;
+			p1pl_reg <= p1pl_next;
+			p2pl_reg <= p2pl_next;
+			p3pl_reg <= p3pl_next;
+			
+			active_bk_modify_reg <= active_bk_modify_next;
+			active_bk_valid_reg <= active_bk_valid_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>5)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+		
+	-- decode antic input
+	process (AN, COLOUR_CLOCK, COLOUR_CLOCK_ORIGINAL, an_prev_reg, an_prev2_reg, an_prev3_reg, hblank_reg, vsync_reg, highres_reg, odd_scanline_reg, prior_delayed_reg, prior_delayed2_reg, hpos_reg, active_p0_live, active_p1_live, active_p2_live, active_p3_live, active_m0_live, active_m1_live, active_m2_live, active_m3_live, active_pf3_collision_live, active_bk_modify_reg, active_bk_modify_next, active_bk_valid_reg, active_hr_reg, visible_live)
+	begin	
+		hblank_next <= hblank_reg;
+		reset_counter <= '0';
+		counter_load_value <= (others=>'0');
+		vsync_next <= vsync_reg;
+		
+		odd_scanline_next <= odd_scanline_reg;
+			
+		-- NB high res mode gives pf2 - which is or of the two pixels
+		highres_next <= highres_reg;
+		
+		-- for gtia modes
+		an_prev_next <= an_prev_reg;
+		an_prev2_next <= an_prev2_reg;
+		an_prev3_next <= an_prev3_reg;
+		
+		-- decoded AN
+		visible_live <= '0';
+		
+		active_hr_next <= active_hr_reg;
+		
+		active_bk_modify_next <= active_bk_modify_reg;
+		active_bk_valid_next <= active_bk_valid_reg;
+		active_bk_live <= '0';
+		active_pf0_live <= '0';
+		active_pf1_live <= '0';
+		active_pf2_live <= '0';
+		active_pf2_collision_live <= '0';
+		active_pf3_live <= '0';
+		active_pf3_collision_live <= '0';
+		active_pm0_live <= '0';
+		active_pm1_live <= '0';
+		active_pm2_live <= '0';
+		active_pm3_live <= '0';
+		
+		if (COLOUR_CLOCK = '1') then	
+			visible_live <= '1';
+			vsync_next <= '0';
+			hblank_next <= '0';
+			an_prev_next <= an;
+			an_prev2_next <= an_prev_reg;
+			an_prev3_next <= an_prev2_reg;
+			
+			active_pm0_live <= active_p0_live or (active_m0_live and not(prior_delayed_reg(4)));
+			active_pm1_live <= active_p1_live or (active_m1_live and not(prior_delayed_reg(4)));
+			active_pm2_live <= active_p2_live or (active_m2_live and not(prior_delayed_reg(4)));
+			active_pm3_live <= active_p3_live or (active_m3_live and not(prior_delayed_reg(4)));			
+			
+			active_bk_modify_next <= (others=>'0');
+			active_bk_valid_next <= (others=>'1');
+			
+			active_hr_next <= (others=>'0');
+		
+			-- 000 background colour
+			-- 001 vsync
+			-- 01X hsync (low bit is high res mode - i.e. 2 pixels per colour clock)
+			-- 1XX colour 0 to colour 3
+			
+			-- in gtia modes then we listen for 2 colour clocks to get one pixels
+			-- 1ZY (giving signal ZYXV for 4 bit colour reg/luminance - unfortunately we only have 9 colour regs!)
+			-- 1XV
+			
+			if (highres_reg = '1') then
+				if (an(2) = '1') then
+					active_hr_next <= AN(1 downto 0);				
+				end if;
+				
+				active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= an(2);
+				active_pf2_collision_live <= an(2) and (an(1) or an(0));
+				active_pf3_collision_live <= '0';				
+			else								
+				-- gtia modes										
+				case prior_delayed_reg(7 downto 6) is
+					when "00" => 
+						-- normal mode
+						active_bk_live <= not(an(2)) and not(an(1)) and not(an(0));
+						active_pf0_live <= an(2) and not(an(1)) and not(an(0));
+						active_pf1_live <= an(2) and not(an(1)) and an(0);
+						active_pf2_live <= an(2) and      an(1) and not(an(0));
+						active_pf2_collision_live <= an(2) and      an(1) and not(an(0));
+						active_pf3_collision_live <= an(2) and      an(1) and an(0);
+					when "01" =>
+						-- 1 colour/16 luminance
+						-- no playfield collisions
+						-- 5th player gets my luminance
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';						
+						active_bk_live <= '1';
+						
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(3 downto 0) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(3 downto 0) <= active_bk_modify_reg(3 downto 0);
+						end if;
+					when "10" => 
+						-- 9 colour
+						-- playfield collisions
+						-- no missile/player collisions from 'playfield' data though		
+						-- offset by 1 colour clock...
+						if (hpos_reg(0) = '1') then
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev_reg(1 downto 0)&an(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an(2);
+									active_pf2_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an(2);
+									active_bk_live <= not(an(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;
+						else
+							active_bk_live <= '0';
+							active_pf0_live <= '0';
+							active_pf1_live <= '0';
+							active_pf2_live <= '0';
+							active_pf2_collision_live <= '0';
+							active_pf3_collision_live <= '0';
+														
+							case an_prev2_reg(1 downto 0)&an_prev_reg(1 downto 0) is
+								when "0000" =>
+									active_pm0_live <= '1';
+								when "0001" =>
+									active_pm1_live <= '1';
+								when "0010" =>
+									active_pm2_live <= '1';
+								when "0011" =>								
+									active_pm3_live <= '1';
+								when "0100"|"1100" =>
+									active_pf0_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0101"|"1101" =>
+									active_pf1_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0110"|"1110" =>
+									active_pf2_live <= an_prev_reg(2);
+									active_pf2_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when "0111"|"1111" =>								
+									active_pf3_collision_live <= an_prev_reg(2);
+									active_bk_live <= not(an_prev_reg(2));
+								when others =>
+									active_bk_live <= '1';
+							end case;									
+						end if;
+						
+					when "11" =>
+						-- 16 colour/1 luminance
+						-- no playfield collisions
+						-- 5th player gets our luminance
+						active_bk_live <= '1';
+						active_pf0_live <= '0';
+						active_pf1_live <= '0';
+						active_pf2_live <= '0';
+						active_pf2_collision_live <= '0';
+						active_pf3_collision_live <= '0';	
+						if (hpos_reg(0) = '1') then
+							active_bk_modify_next(7 downto 4) <= an_prev_reg(1 downto 0)&an(1 downto 0);
+						else
+							active_bk_modify_next(7 downto 4) <= active_bk_modify_reg(7 downto 4);
+						end if;
+						
+						if (active_bk_modify_next(7 downto 4) = "0000") then
+							active_bk_valid_next(3 downto 0) <= "0000";
+						end if;
+				end case;
+			end if;
+			
+			if (prior_delayed_reg(4) = '1') then
+				active_pf3_live <= active_pf3_collision_live or active_m0_live or active_m1_live or active_m2_live or active_m3_live;
+			else
+				active_pf3_live <= active_pf3_collision_live;
+			end if;
+			
+			if (not (prior_delayed2_reg(7 downto 6) = "00")) then
+				-- force off flip flop when in gtia mode
+				highres_next <= '0';
+			end if;
+			
+			-- hblank
+			if (an_prev_reg(2 downto 1) = "01") then
+				hblank_next <= '1';
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				highres_next <= an_prev_reg(0);
+			
+				if (COLOUR_CLOCK_ORIGINAL='1') then				
+					if (hblank_reg = '0' and vsync_reg = '0') then
+						reset_counter <= '1';
+						counter_load_value <= X"E0"; -- 2 lower than antic
+						odd_scanline_next <= not(odd_scanline_reg);
+					end if;
+				end if;
+			end if;
+			if (an(2 downto 1) = "01") then
+				visible_live <= '0';
+			end if;			
+	
+			-- vsync
+			if (an_prev_reg = "001") then
+				active_bk_live <= '0';
+				active_pf0_live <= '0';
+				active_pf1_live <= '0';
+				active_pf2_live <= '0';
+				active_pf2_collision_live <= '0';
+				active_pf3_live <= '0';
+				active_pf3_collision_live <= '0';
+				
+				vsync_next <= '1';
+
+				odd_scanline_next <= '0';
+				
+				visible_live <= '0';
+			end if;
+			
+			-- during vblank we reset our own counter - since Antic does not clear hblank_reg
+			if (hpos_reg = X"E3" and COLOUR_CLOCK_ORIGINAL='1') then
+				reset_counter <= '1';
+				counter_load_value <= X"00";
+			end if;
+
+		end if;
+	end process;
+	
+	-- hpos
+	counter_hpos : simple_counter
+		generic map (COUNT_WIDTH=>8)
+		port map (clk=>clk, reset_n=>reset_n, increment=>COLOUR_CLOCK_ORIGINAL, load=>reset_counter, load_value=>counter_load_value, current_value=>hpos_reg);
+	
+	-- visible region
+--	process(hpos_reg,vpos_reg)
+--	begin		
+--		visible_live <= '1';
+--		
+----		if (unsigned(vpos_reg) < to_unsigned(8,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(vpos_reg) > to_unsigned(247,9)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) <= to_unsigned(34,8)) then
+----			visible_live <= '0';
+----		end if;
+----		
+----		if (unsigned(hpos_reg) > to_unsigned(221,8)) then
+----			visible_live <= '0';
+----		end if;		
+--	end process;
+	
+	-- generate hsync
+	process(hpos_reg, hsync_reg, hsync_end, vsync_reg, vsync_next)
+	begin
+		hsync_start <= '0';
+		hsync_next <= hsync_reg;
+
+		if (unsigned(hpos_reg) = X"D4" and vsync_reg = '1') then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+	
+		if (unsigned(hpos_reg) = X"0" and vsync_reg = '0' ) then
+			hsync_start <= '1';
+			hsync_next <= '1';
+		end if;
+			
+		if (hsync_end = '1') then
+			hsync_next <= '0';
+		end if;
+		
+		if (vsync_next = '0' and vsync_reg = '1') then
+			hsync_next <= '0';
+		end if;
+	end process;
+
+	hsync_delay : delay_line
+		generic map (COUNT=>15)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hsync_start,enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hsync_end);	
+
+	-- pmg dma
+	MEMORY_READY <= CPU_MEMORY_READY or ANTIC_MEMORY_READY; -- TODO, REVIEW timing vs CPU/ANTIC - simpler may be possible now
+	process(antic_fetch,CPU_ENABLE_ORIGINAL,memory_ready,memory_data_in,hsync_start,pmg_dma_state_reg,gractl_reg,odd_scanline_reg,vdelay_reg,grafm_reg, visible_live,hpos_reg, hblank_reg)
+	begin
+		pmg_dma_state_next <= pmg_dma_state_reg;
+		grafm_dma_load <= '0';
+		grafm_dma_next <= grafm_reg;		
+		grafp0_dma_load <= '0';
+		grafp0_dma_next <= (others=>'0');
+		grafp1_dma_load <= '0';
+		grafp1_dma_next <= (others=>'0');
+		grafp2_dma_load <= '0';
+		grafp2_dma_next <= (others=>'0');
+		grafp3_dma_load <= '0';
+		grafp3_dma_next <= (others=>'0');
+	
+		-- pull pmg data from bus
+		if (hpos_reg = X"E1") then
+			pmg_dma_state_next <= pmg_dma_missile;
+		end if;
+		
+		-- we start from the first antic refresh cycle
+		-- TODO - CPU enable does not identify next 'antic' cycle in turbo mode...
+		case pmg_dma_state_reg is
+			when pmg_dma_missile =>
+				if (antic_fetch = '1' and memory_ready = '1' and hblank_reg = '1' and visible_live = '0' and hpos_reg(7 downto 4) = "0000") then
+					-- here we have the missile0					
+					grafm_dma_load <= gractl_reg(0);
+				
+					if ((odd_scanline_reg or not(vdelay_reg(0))) = '1') then
+						grafm_dma_next(1 downto 0) <= memory_data_in(1 downto 0);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(1))) = '1') then
+						grafm_dma_next(3 downto 2) <= memory_data_in(3 downto 2);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(2))) = '1') then
+						grafm_dma_next(5 downto 4) <= memory_data_in(5 downto 4);
+					end if;
+					if ((odd_scanline_reg or not(vdelay_reg(3))) = '1') then
+						grafm_dma_next(7 downto 6) <= memory_data_in(7 downto 6);
+					end if;
+					
+					pmg_dma_state_next <= pmg_dma_instruction;
+				end if;
+			when pmg_dma_instruction =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					pmg_dma_state_next <= pmg_dma_player0;
+				end if;			
+			when pmg_dma_player0 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player0
+					grafp0_dma_next <= memory_data_in;				
+					grafp0_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(4)));
+					pmg_dma_state_next <= pmg_dma_player1;
+				end if;
+			when pmg_dma_player1 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp1_dma_next <= memory_data_in;
+					grafp1_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(5)));
+					pmg_dma_state_next <= pmg_dma_player2;
+				end if;
+			when pmg_dma_player2 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp2_dma_next <= memory_data_in;
+					grafp2_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(6)));
+					pmg_dma_state_next <= pmg_dma_player3;
+				end if;				
+			when pmg_dma_player3 =>
+				if (((CPU_ENABLE_ORIGINAL or antic_fetch) and memory_ready) = '1') then
+					-- here we have player1
+					grafp3_dma_next <= memory_data_in;				
+					grafp3_dma_load <= gractl_reg(1) and (odd_scanline_reg or not(vdelay_reg(7)));
+					pmg_dma_state_next <= pmg_dma_done;
+				end if;
+			when others =>
+				-- nop
+		end case;
+	end process;
+		
+	-- pmg display - same for all pmgs
+	-- TODO: priority
+	player0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp0_delayed_reg,size=>sizep0_delayed_reg(1 downto 0),bitmap=>grafp0_reg, output=>active_p0_live);	
+	player1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp1_delayed_reg,size=>sizep1_delayed_reg(1 downto 0),bitmap=>grafp1_reg, output=>active_p1_live);	
+	player2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp2_delayed_reg,size=>sizep2_delayed_reg(1 downto 0),bitmap=>grafp2_reg, output=>active_p2_live);	
+	player3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);				
+
+	missile0 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg(1 downto 0)&"000000", output=>active_m0_live);
+	missile1 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg(3 downto 2)&"000000", output=>active_m1_live);
+	missile2 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg(5 downto 4)&"000000", output=>active_m2_live);
+	missile3 : gtia_player
+		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg(7 downto 6)&"000000", output=>active_m3_live);
+		
+	-- calculate atari colour
+	priority_rules : gtia_priority
+		port map(clk=>clk, colour_enable=>colour_clock, prior=>prior_delayed_reg,p0=>active_pm0_live,p1=>active_pm1_live,p2=>active_pm2_live,p3=>active_pm3_live,pf0=>active_pf0_live,pf1=>active_pf1_live,pf2=>active_pf2_live,pf3=>active_pf3_live,bk=>active_bk_live,p0_out=>set_p0,p1_out=>set_p1,p2_out=>set_p2,p3_out=>set_p3,pf0_out=>set_pf0,pf1_out=>set_pf1,pf2_out=>set_pf2,pf3_out=>set_pf3,bk_out=>set_bk);	
+
+	trigger_secondhalf <= colour_clock_HIGHRES and not colour_clock;
+	process(set_p0,set_p1,set_p2,set_p3,set_pf0,set_pf1,set_pf2,set_pf3,set_bk,highres_reg, active_hr_reg, colbk_delayed_reg, colpf0_delayed_reg, colpf1_delayed_reg, colpf2_delayed_reg, colpf3_delayed_reg, colpm0_delayed_reg, colpm1_delayed_reg, colpm2_delayed_reg, colpm3_delayed_reg, trigger_secondhalf, colour_clock, COLOUR_REG, hrcolour_reg, visible_live, active_bk_modify_next, active_bk_valid_next)
+	begin
+		colour_next <= colour_reg;
+		hrcolour_next <= hrcolour_reg;
+		
+		if (trigger_secondhalf = '1') then
+			if (highres_reg = '1') then
+				colour_next <= hrcolour_reg;
+			end if;
+		end if;		
+		
+		if (colour_clock = '1') then 
+			colour_next <= 
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+			hrcolour_next <= -- SAME FIXME
+				(
+				((colbk_delayed_reg&'0' or active_bk_modify_next) and active_bk_valid_next and (set_bk &set_bk &set_bk &set_bk &set_bk &set_bk &set_bk& set_bk)) or
+				(colpf0_delayed_reg&'0' and (set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0&set_pf0) ) or
+				(colpf1_delayed_reg&'0' and (set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1&set_pf1) ) or
+				(colpf2_delayed_reg&'0' and (set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2&set_pf2) ) or
+				((colpf3_delayed_reg&'0' or active_bk_modify_next) and (set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3&set_pf3) ) or
+				(colpm0_delayed_reg&'0' and (set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0 &set_p0& set_p0)) or
+				(colpm1_delayed_reg&'0' and (set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1 &set_p1& set_p1)) or
+				(colpm2_delayed_reg&'0' and (set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2 &set_p2& set_p2)) or
+				(colpm3_delayed_reg&'0' and (set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3 &set_p3& set_p3))
+				);
+						
+			-- finally high-res mode overrides the luma
+			if (set_bk = '0' and highres_reg = '1') then
+			
+				if (active_hr_reg(1) = '1') then
+					colour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';						
+				end if;
+				
+				if (active_hr_reg(0) = '1') then						
+					hrcolour_next(3 downto 0) <= colpf1_delayed_reg(3 downto 1)&'0';
+				end if;
+			end if;				
+			
+			if (visible_live = '0') then
+				colour_next <= X"00";
+				hrcolour_next <= X"00";
+			end if;			
+		end if;
+	end process;
+
+	-- collision detection
+	process (colour_clock, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg,hitclr_write,active_pf0_live,active_pf1_live,active_pf2_collision_live,active_pf3_collision_live,active_p0_live,active_p1_live,active_p2_live,active_p3_live,active_m0_live,active_m1_live,active_m2_live,active_m3_live, visible_live)
+	begin
+		m0pf_next <= m0pf_reg;
+		m1pf_next <= m1pf_reg;
+		m2pf_next <= m2pf_reg;
+		m3pf_next <= m3pf_reg;
+		m0pl_next <= m0pl_reg;
+		m1pl_next <= m1pl_reg;
+		m2pl_next <= m2pl_reg;
+		m3pl_next <= m3pl_reg;
+		
+		p0pf_next <= p0pf_reg;
+		p1pf_next <= p1pf_reg;
+		p2pf_next <= p2pf_reg;
+		p3pf_next <= p3pf_reg;
+		p0pl_next <= p0pl_reg;
+		p1pl_next <= p1pl_reg;
+		p2pl_next <= p2pl_reg;
+		p3pl_next <= p3pl_reg;	
+		
+		if (hitclr_write = '1') then
+			m0pf_next <= (others=>'0');
+			m1pf_next <= (others=>'0');
+			m2pf_next <= (others=>'0');
+			m3pf_next <= (others=>'0');
+			m0pl_next <= (others=>'0');
+			m1pl_next <= (others=>'0');
+			m2pl_next <= (others=>'0');
+			m3pl_next <= (others=>'0');
+			
+			p0pf_next <= (others=>'0');
+			p1pf_next <= (others=>'0');
+			p2pf_next <= (others=>'0');
+			p3pf_next <= (others=>'0');
+			p0pl_next <= (others=>'0');
+			p1pl_next <= (others=>'0');
+			p2pl_next <= (others=>'0');
+			p3pl_next <= (others=>'0');
+		else
+			if (visible_live = '1' and colour_clock = '1') then
+				m0pl_next <= m0pl_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m1pl_next <= m1pl_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m2pl_next <= m2pl_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				m3pl_next <= m3pl_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+
+				m0pf_next <= m0pf_reg or (active_m0_live&active_m0_live&active_m0_live&active_m0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m1pf_next <= m1pf_reg or (active_m1_live&active_m1_live&active_m1_live&active_m1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m2pf_next <= m2pf_reg or (active_m2_live&active_m2_live&active_m2_live&active_m2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				m3pf_next <= m3pf_reg or (active_m3_live&active_m3_live&active_m3_live&active_m3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				
+				p0pl_next <= p0pl_reg or (active_p0_live&active_p0_live&active_p0_live&'0'        and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p1pl_next <= p1pl_reg or (active_p1_live&active_p1_live&'0'       &active_p1_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p2pl_next <= p2pl_reg or (active_p2_live&'0'       &active_p2_live&active_p2_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);
+				p3pl_next <= p3pl_reg or ('0'       &active_p3_live&active_p3_live&active_p3_live and active_p3_live&active_p2_live&active_p1_live&active_p0_live);	
+				
+				p0pf_next <= p0pf_reg or (active_p0_live&active_p0_live&active_p0_live&active_p0_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p1pf_next <= p1pf_reg or (active_p1_live&active_p1_live&active_p1_live&active_p1_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p2pf_next <= p2pf_reg or (active_p2_live&active_p2_live&active_p2_live&active_p2_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);
+				p3pf_next <= p3pf_reg or (active_p3_live&active_p3_live&active_p3_live&active_p3_live and active_pf3_collision_live&active_pf2_collision_live&active_pf1_live&active_pf0_live);			
+			end if;
+		end if;
+		
+	end process;
+
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded,hposp0_raw_reg,hposp1_raw_reg,hposp2_raw_reg,hposp3_raw_reg,hposm0_raw_reg,hposm1_raw_reg,hposm2_raw_reg,hposm3_raw_reg,sizep0_raw_reg,sizep1_raw_reg,sizep2_raw_reg,sizep3_raw_reg,sizem_raw_reg,grafp0_reg,grafp1_reg,grafp2_reg,grafp3_reg, grafm_reg, colpm0_raw_reg, colpm1_raw_reg, colpm2_raw_reg, colpm3_raw_reg, colpf0_raw_reg, colpf1_raw_reg,colpf2_raw_reg, colpf3_raw_reg, colbk_raw_reg, prior_raw_reg, vdelay_reg, gractl_reg, consol_output_reg, grafm_dma_load, grafm_dma_next, grafp0_dma_load, grafp0_dma_next, grafp1_dma_load, grafp1_dma_next, grafp2_dma_load, grafp2_dma_next, grafp3_dma_load, grafp3_dma_next)
+	begin
+		hposp0_raw_next <= hposp0_raw_reg;
+		hposp1_raw_next <= hposp1_raw_reg;
+		hposp2_raw_next <= hposp2_raw_reg;
+		hposp3_raw_next <= hposp3_raw_reg;
+
+		hposm0_raw_next <= hposm0_raw_reg;
+		hposm1_raw_next <= hposm1_raw_reg;
+		hposm2_raw_next <= hposm2_raw_reg;
+		hposm3_raw_next <= hposm3_raw_reg;			
+
+		sizep0_raw_next <= sizep0_raw_reg;
+		sizep1_raw_next <= sizep1_raw_reg;
+		sizep2_raw_next <= sizep2_raw_reg;
+		sizep3_raw_next <= sizep3_raw_reg;
+
+		sizem_raw_next <= sizem_raw_reg;
+		
+		grafp0_next <= grafp0_reg;
+		grafp1_next <= grafp1_reg;
+		grafp2_next <= grafp2_reg;
+		grafp3_next <= grafp3_reg;
+
+		grafm_next <= grafm_reg;
+		
+		colpm0_raw_next <= colpm0_raw_reg;
+		colpm1_raw_next <= colpm1_raw_reg;
+		colpm2_raw_next <= colpm2_raw_reg;
+		colpm3_raw_next <= colpm3_raw_reg;
+
+		colpf0_raw_next <= colpf0_raw_reg;
+		colpf1_raw_next <= colpf1_raw_reg;
+		colpf2_raw_next <= colpf2_raw_reg;
+		colpf3_raw_next <= colpf3_raw_reg;
+		
+		colbk_raw_next <= colbk_raw_reg;
+		
+		prior_raw_next <= prior_raw_reg;
+		
+		vdelay_next <= vdelay_reg;
+		
+		gractl_next <= gractl_reg;
+		
+		consol_output_next <= consol_output_reg;	
+		
+		hitclr_write <= '0';
+		
+		if (grafm_dma_load = '1') then
+			grafm_next <= grafm_dma_next;
+		end if;
+
+		if (grafp0_dma_load = '1') then
+			grafp0_next <= grafp0_dma_next;
+		end if;
+
+		if (grafp1_dma_load = '1') then
+			grafp1_next <= grafp1_dma_next;
+		end if;
+
+		if (grafp2_dma_load = '1') then
+			grafp2_next <= grafp2_dma_next;
+		end if;
+
+		if (grafp3_dma_load = '1') then
+			grafp3_next <= grafp3_dma_next;
+		end if;
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				hposp0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(1) = '1') then
+				hposp1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(2) = '1') then
+				hposp2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				hposp3_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(4) = '1') then
+				hposm0_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(5) = '1') then
+				hposm1_raw_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(6) = '1') then
+				hposm2_raw_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(7) = '1') then
+				hposm3_raw_next <= cpu_data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				sizep0_raw_next <= cpu_data_in(1 downto 0);
+			end if;	
+
+			if(addr_decoded(9) = '1') then
+				sizep1_raw_next <= cpu_data_in(1 downto 0);
+			end if;		
+			
+			if(addr_decoded(10) = '1') then
+				sizep2_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+
+			if(addr_decoded(11) = '1') then
+				sizep3_raw_next <= cpu_data_in(1 downto 0);
+			end if;
+			
+			if(addr_decoded(12) = '1') then
+				sizem_raw_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(13) = '1') then
+				grafp0_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(14) = '1') then
+				grafp1_next <= cpu_data_in;
+			end if;
+
+			if(addr_decoded(15) = '1') then
+				grafp2_next <= cpu_data_in;
+			end if;			
+			
+			if(addr_decoded(16) = '1') then
+				grafp3_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(17) = '1') then
+				grafm_next <= cpu_data_in;
+			end if;		
+			
+			if(addr_decoded(18) = '1') then
+				colpm0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(19) = '1') then
+				colpm1_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(20) = '1') then
+				colpm2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(21) = '1') then
+				colpm3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(22) = '1') then
+				colpf0_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(23) = '1') then
+				colpf1_raw_next <= cpu_data_in(7 downto 1);
+			end if;									
+
+			if(addr_decoded(24) = '1') then
+				colpf2_raw_next <= cpu_data_in(7 downto 1);
+			end if;	
+
+			if(addr_decoded(25) = '1') then
+				colpf3_raw_next <= cpu_data_in(7 downto 1);
+			end if;		
+			
+			if(addr_decoded(26) = '1') then
+				colbk_raw_next <= cpu_data_in(7 downto 1);
+			end if;
+
+			if(addr_decoded(27) = '1') then
+				prior_raw_next <= cpu_data_in;
+			end if;	
+			
+			if(addr_decoded(28) = '1') then
+				vdelay_next <= cpu_data_in;
+			end if;	
+
+			if(addr_decoded(29) = '1') then
+				gractl_next <= cpu_data_in(2 downto 0);
+			end if;		
+			
+			if(addr_decoded(30) = '1') then
+				-- clear the collision regs
+				hitclr_write <= '1';
+			end if;
+
+			if(addr_decoded(31) = '1') then
+				consol_output_next <= cpu_data_in(3 downto 0);
+			end if;				
+			
+		end if;
+	end process;
+	
+	-- delays...
+		-- TODO - needs more attention ... 
+		-- The prior behaviour here in real hardware is all over the place...
+		-- THESE CAN TAKE MUCH LESS SPACE - only need to store per CPU cycle, not per colour clock original
+	prior_short_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>6)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(5 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(5 downto 0));
+
+	prior_long_delay : wide_delay_line
+		generic map (COUNT=>3, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed_reg(7 downto 6));
+
+	prior_longer_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>prior_raw_reg(7 downto 6),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>prior_delayed2_reg(7 downto 6));		
+		
+	colbk_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colbk_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colbk_delayed_reg(7 downto 1));	
+
+	colpm0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm0_delayed_reg(7 downto 1));		
+	colpm1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm1_delayed_reg(7 downto 1));		
+	colpm2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm2_delayed_reg(7 downto 1));		
+	colpm3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpm3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpm3_delayed_reg(7 downto 1));		
+
+	colpf0_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf0_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf0_delayed_reg(7 downto 1));		
+	colpf1_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf1_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf1_delayed_reg(7 downto 1));		
+	colpf2_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf2_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf2_delayed_reg(7 downto 1));		
+	colpf3_delay : wide_delay_line
+		generic map (COUNT=>2, WIDTH=>7)
+		port map(clk=>clk,sync_reset=>'0',data_in=>colpf3_raw_reg(7 downto 1),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>colpf3_delayed_reg(7 downto 1));				
+
+	hposp0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp0_delayed_reg(7 downto 0));		
+	hposp1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp1_delayed_reg(7 downto 0));		
+	hposp2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp2_delayed_reg(7 downto 0));		
+	hposp3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposp3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposp3_delayed_reg(7 downto 0));				
+
+	hposm0_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm0_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm0_delayed_reg(7 downto 0));		
+	hposm1_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm1_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm1_delayed_reg(7 downto 0));		
+	hposm2_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm2_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm2_delayed_reg(7 downto 0));		
+	hposm3_delay : wide_delay_line
+		generic map (COUNT=>5, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>hposm3_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>hposm3_delayed_reg(7 downto 0));				
+		
+	sizep0_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep0_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep0_delayed_reg(1 downto 0));		
+	sizep1_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep1_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep1_delayed_reg(1 downto 0));		
+	sizep2_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep2_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep2_delayed_reg(1 downto 0));		
+	sizep3_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>2)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizep3_raw_reg(1 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizep3_delayed_reg(1 downto 0));		
+	sizem_delay : wide_delay_line
+		generic map (COUNT=>4, WIDTH=>8)
+		port map(clk=>clk,sync_reset=>'0',data_in=>sizem_raw_reg(7 downto 0),enable=>COLOUR_CLOCK_ORIGINAL,reset_n=>reset_n,data_out=>sizem_delayed_reg(7 downto 0));				
+		
+	-- joystick
+	process(trig0_reg, trig1_reg, trig2_reg, trig3_reg, trig0, trig1, trig2, trig3, gractl_reg)
+	begin	
+		trig0_next <= trig0;
+		trig1_next <= trig1;
+		trig2_next <= trig2;
+		trig3_next <= trig3;
+		
+		if (gractl_reg(2) = '1') then
+			trig0_next <= trig0_reg and trig0;
+			trig1_next <= trig1_reg and trig1;
+			trig2_next <= trig2_reg and trig2;
+			trig3_next <= trig3_reg and trig3;
+		end if;
+	end process;
+	
+	-- Read from registers		
+	process(addr_decoded, CONSOL_OPTION, CONSOL_SELECT, CONSOL_START, consol_output_reg, trig0_reg, trig1_reg, trig2_reg, trig3_reg, m0pf_reg,m1pf_reg,m2pf_reg,m3pf_reg,m0pl_reg,m1pl_reg,m2pl_reg,m3pl_reg,p0pf_reg,p1pf_reg,p2pf_reg,p3pf_reg,p0pl_reg,p1pl_reg,p2pl_reg,p3pl_reg, pal)
+	begin
+		data_out <= X"0F";
+
+		if (addr_decoded(0) = '1') then
+			data_out <= "0000"&m0pf_reg;
+		end if;
+
+		if (addr_decoded(1) = '1') then
+			data_out <= "0000"&m1pf_reg;
+		end if;
+		
+		if (addr_decoded(2) = '1') then
+			data_out <= "0000"&m2pf_reg;
+		end if;
+
+		if (addr_decoded(3) = '1') then
+			data_out <= "0000"&m3pf_reg;
+		end if;
+
+		if (addr_decoded(4) = '1') then
+			data_out <= "0000"&p0pf_reg;
+		end if;
+
+		if (addr_decoded(5) = '1') then
+			data_out <= "0000"&p1pf_reg;
+		end if;
+		
+		if (addr_decoded(6) = '1') then
+			data_out <= "0000"&p2pf_reg;
+		end if;
+
+		if (addr_decoded(7) = '1') then
+			data_out <= "0000"&p3pf_reg;
+		end if;
+		
+		if (addr_decoded(8) = '1') then
+			data_out <= "0000"&m0pl_reg;
+		end if;
+
+		if (addr_decoded(9) = '1') then
+			data_out <= "0000"&m1pl_reg;
+		end if;
+		
+		if (addr_decoded(10) = '1') then
+			data_out <= "0000"&m2pl_reg;
+		end if;
+
+		if (addr_decoded(11) = '1') then
+			data_out <= "0000"&m3pl_reg;
+		end if;		
+
+		if (addr_decoded(12) = '1') then
+			data_out <= "0000"&p0pl_reg;
+		end if;
+
+		if (addr_decoded(13) = '1') then
+			data_out <= "0000"&p1pl_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then
+			data_out <= "0000"&p2pl_reg;
+		end if;
+
+		if (addr_decoded(15) = '1') then
+			data_out <= "0000"&p3pl_reg;
+		end if;		
+		
+		if (addr_decoded(16) = '1') then
+			data_out <= "0000000"&trig0_reg;
+		end if;
+
+		if (addr_decoded(17) = '1') then
+			data_out <= "0000000"&trig1_reg;
+		end if;
+
+		if (addr_decoded(18) = '1') then
+			data_out <= "0000000"&trig2_reg;
+		end if;
+		
+		if (addr_decoded(19) = '1') then
+			data_out <= "0000000"&trig3_reg;
+		end if;
+		
+		if (addr_decoded(20) = '1') then
+			data_out <= "00000"&not(pal&pal&pal);
+		end if;
+
+		if (addr_decoded(31) = '1') then
+			data_out <= "0000"&('0'&not(CONSOL_OPTION)&not(CONSOL_SELECT)&not(CONSOL_START) and (not consol_output_reg));
+		end if;
+		
+	end process;
+	
+	-- output	
+	colour_out <= colour_reg;
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+	
+	sound <= consol_output_reg(3);
+
+end vhdl;
+
+
Index: unmerged/core/mist/hexdecoder.vhd
===================================================================
--- unmerged/core/mist/hexdecoder.vhd	(nonexistent)
+++ unmerged/core/mist/hexdecoder.vhd	(revision 1)
@@ -0,0 +1,75 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY hexdecoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+);
+END hexdecoder;
+
+ARCHITECTURE vhdl OF hexdecoder IS
+	signal numinv : STD_LOGIC_VECTOR(3 downto 0);
+	signal digit_next : std_logic_vector(6 downto 0);
+	signal digit_reg : STD_LOGIC_VECTOR(6 DOWNTO 0);
+BEGIN
+	--numinv <= not(NUMBER);
+	numinv <= NUMBER;
+	process(numinv)
+	begin
+		case numinv is
+			when "0000" =>
+				digit_next <= "1111111";
+			when "0001" =>
+				digit_next <= "1111001";
+			when "0010" =>
+				digit_next <= "0100100";
+			when "0011" =>
+				digit_next <= "0110000";
+			when "0100" =>
+				digit_next <= "0011001";
+			when "0101" =>
+				digit_next <= "0010010";
+			when "0110" =>
+				digit_next <= "0000010";
+			when "0111" =>
+				digit_next <= "1111000";
+			when "1000" =>
+				digit_next <= "0000000";
+			when "1001" =>
+				digit_next <= "0011000";
+			when "1010" =>
+				digit_next <= "0001000";
+			when "1011" =>
+				digit_next <= "0000011";
+			when "1100" =>
+				digit_next <= "1000110";
+			when "1101" =>
+				digit_next <= "0100001";
+			when "1110" =>
+				digit_next <= "0000110";
+			when "1111" =>
+				digit_next <= "0001110";
+			when others =>
+				digit_next <= "1111111";
+		end case;
+	end process;
+	
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	digit<=digit_reg;
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/i2sslave.vhdl
===================================================================
--- unmerged/core/mist/i2sslave.vhdl	(nonexistent)
+++ unmerged/core/mist/i2sslave.vhdl	(revision 1)
@@ -0,0 +1,86 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY i2sslave IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	BCLK : IN STD_LOGIC;
+	DACLRC : IN STD_LOGIC;
+	
+	LEFT_IN : in std_logic_vector(15 downto 0);
+	RIGHT_IN : in std_logic_vector(15 downto 0);
+	
+	MCLK_2 : OUT STD_LOGIC;
+	DACDAT : OUT STD_LOGIC
+);
+END i2sslave;
+
+ARCHITECTURE vhdl OF i2sslave IS
+	signal bclk_reg : std_logic;
+	signal bclk_last_reg : std_logic;
+	signal daclrc_reg : std_logic;
+	signal daclrc_last_reg : std_logic;
+	
+	signal shiftreg_reg : std_logic_vector(15 downto 0);
+	signal shiftreg_next : std_logic_vector(15 downto 0);
+	
+	signal CLK_FAKE : std_logic;
+BEGIN
+	MCLK_2 <= CLK_FAKE; -- bad practice, but pll out of...
+	
+	-- Data read on bclk low->high transition
+	-- daclrc is set on bclk high->low transition
+	
+	-- register inputs
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			CLK_FAKE <= not(CLK_FAKE);
+		end if;
+	end process;
+	
+	process(CLK_FAKE)
+	begin	
+		if (CLK_FAKE'event and CLK_FAKE='1') then
+			bclk_reg <= bclk;
+			bclk_last_reg <= bclk_reg;
+			daclrc_reg <= daclrc;
+			daclrc_last_reg <= daclrc_reg;
+			shiftreg_reg <= shiftreg_next;
+		end if;
+	end process;
+	
+	-- sample on change to daclrc, shift out bit if required
+	process(daclrc_reg,daclrc_last_reg,bclk_reg,shiftreg_reg,left_in,right_in,bclk_last_reg)
+		variable reload : std_logic;
+	begin
+		reload := '0';
+		shiftreg_next <= shiftreg_reg;
+		
+		if (daclrc_reg = '1' and daclrc_last_reg = '0') then
+			shiftreg_next <= right_in;
+			reload := '1';
+		end if;
+		
+		if (daclrc_reg = '0' and daclrc_last_reg = '1') then
+			shiftreg_next <= left_in;
+			reload := '1';
+		end if;
+		
+		if (bclk_reg = '0' and bclk_last_reg = '1' and reload='0') then
+				shiftreg_next <= shiftreg_reg(14 downto 0)&'0';
+		end if;
+			
+	end process;
+	
+	DACDAT <= shiftreg_reg(15);
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/atari800core.qws
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/core/mist/atari800core.qws
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/core/mist/atari800core.vhd.bak
===================================================================
--- unmerged/core/mist/atari800core.vhd.bak	(nonexistent)
+++ unmerged/core/mist/atari800core.vhd.bak	(revision 1)
@@ -0,0 +1,1395 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLOCK_50 :  IN  STD_LOGIC;
+		AUD_BCLK :  IN  STD_LOGIC;
+		AUD_DACLRCK :  IN  STD_LOGIC;
+		PS2_CLK :  IN  STD_LOGIC;
+		PS2_DAT :  IN  STD_LOGIC;
+		UART_RXD :  IN  STD_LOGIC;
+		SD_DATA :  IN  STD_LOGIC;
+		I2C_SCLK :  INOUT  STD_LOGIC;
+		I2C_SDAT :  INOUT  STD_LOGIC;
+		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		AUD_XCK :  OUT  STD_LOGIC;
+		AUD_DACDAT :  OUT  STD_LOGIC;
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		FL_OE_N :  OUT  STD_LOGIC;
+		FL_WE_N :  OUT  STD_LOGIC;
+		FL_RST_N :  OUT  STD_LOGIC;
+		SRAM_CE_N :  OUT  STD_LOGIC;
+		SRAM_OE_N :  OUT  STD_LOGIC;
+		SRAM_WE_N :  OUT  STD_LOGIC;
+		SRAM_LB_N :  OUT  STD_LOGIC;
+		SRAM_UB_N :  OUT  STD_LOGIC;
+		UART_TXD :  OUT  STD_LOGIC;
+		DRAM_BA_0 :  OUT  STD_LOGIC;
+		DRAM_BA_1 :  OUT  STD_LOGIC;
+		DRAM_CS_N :  OUT  STD_LOGIC;
+		DRAM_RAS_N :  OUT  STD_LOGIC;
+		DRAM_CAS_N :  OUT  STD_LOGIC;
+		DRAM_WE_N :  OUT  STD_LOGIC;
+		DRAM_LDQM :  OUT  STD_LOGIC;
+		DRAM_UDQM :  OUT  STD_LOGIC;
+		DRAM_CLK :  OUT  STD_LOGIC;
+		DRAM_CKE :  OUT  STD_LOGIC;
+		SD_CLK :  OUT  STD_LOGIC;
+		SD_CMD :  OUT  STD_LOGIC;
+		SD_THREE :  OUT  STD_LOGIC;
+		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT hexdecoder
+	PORT(CLK : IN STD_LOGIC;
+		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sram
+	PORT(WREN : IN STD_LOGIC;
+		 clk : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 request : IN STD_LOGIC;
+		 width_16bit : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_CE_N : OUT STD_LOGIC;
+		 SRAM_OE_N : OUT STD_LOGIC;
+		 SRAM_WE_N : OUT STD_LOGIC;
+		 SRAM_LB_N : OUT STD_LOGIC;
+		 SRAM_UB_N : OUT STD_LOGIC;
+		 complete : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT gpio
+	PORT(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+	);
+END COMPONENT;
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REPLY : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 REPLY : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 TURBO : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT i2c_loader
+GENERIC (device_address : INTEGER;
+			log2_divider : INTEGER;
+			num_retries : INTEGER
+			);
+	PORT(CLK : IN STD_LOGIC;
+		 nRESET : IN STD_LOGIC;
+		 I2C_SCL : INOUT STD_LOGIC;
+		 I2C_SDA : INOUT STD_LOGIC;
+		 IS_DONE : OUT STD_LOGIC;
+		 IS_ERROR : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT flashrom
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_CE_N : OUT STD_LOGIC;
+		 FLASH_OE_N : OUT STD_LOGIC;
+		 FLASH_WE_N : OUT STD_LOGIC;
+		 FLASH_RESET_N : OUT STD_LOGIC;
+		 COMPLETE : OUT STD_LOGIC;
+		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT i2sslave
+	PORT(CLK : IN STD_LOGIC;
+		 BCLK : IN STD_LOGIC;
+		 DACLRC : IN STD_LOGIC;
+		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 MCLK_2 : OUT STD_LOGIC;
+		 DACDAT : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+SIGNAL	CART_CCTL_N :  STD_LOGIC;
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	TURBO :  STD_LOGIC;
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+
+BEGIN 
+
+
+
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+
+b2v_hex0_inst : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(3 DOWNTO 0),
+		 DIGIT => HEX0);
+
+
+b2v_hex0_inst2 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(7 DOWNTO 4),
+		 DIGIT => HEX1);
+
+
+b2v_hex0_inst3 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(11 DOWNTO 8),
+		 DIGIT => HEX2);
+
+
+b2v_hex0_inst4 : hexdecoder
+PORT MAP(CLK => CLK,
+		 NUMBER => ZPU_HEX(15 DOWNTO 12),
+		 DIGIT => HEX3);
+
+
+b2v_inst : sram
+PORT MAP(WREN => RAM_WRITE_ENABLE,
+		 clk => CLK,
+		 reset_n => RESET_N,
+		 request => RAM_REQUEST,
+		 width_16bit => WIDTH_16BIT_ACCESS,
+		 ADDRESS => RAM_ADDR,
+		 DIN => WRITE_DATA(15 DOWNTO 0),
+		 SRAM_DQ => SRAM_DQ,
+		 SRAM_CE_N => SRAM_CE_N,
+		 SRAM_OE_N => SRAM_OE_N,
+		 SRAM_WE_N => SRAM_WE_N,
+		 SRAM_LB_N => SRAM_LB_N,
+		 SRAM_UB_N => SRAM_UB_N,
+		 complete => RAM_REQUEST_COMPLETE,
+		 DOUT => RAM_DO,
+		 SRAM_ADDR => SRAM_ADDR);
+
+
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+
+b2v_inst10 : ledsw
+PORT MAP(CLK => CLK,
+		 KEY => KEY,
+		 SW => SW,
+		 SYNC_KEYS => SYNC_KEYS,
+		 SYNC_SWITCHES => SYNC_SWITCHES);
+
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2_CLK,
+		 PS2_DAT => PS2_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+b2v_inst18 : pokey_ps2_decoder
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_CODE => SYNTHESIZED_WIRE_11,
+		 KEY_HELD => KEY_HELD,
+		 SHIFT_PRESSED => SHIFT_PRESSED,
+		 BREAK_PRESSED => BREAK_PRESSED,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+		 KBCODE => KBCODE,
+		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
+
+gpio0_gen:
+   for I in 0 to 35 generate
+		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+   end generate gpio0_gen;
+
+gpio1_gen:
+   for I in 0 to 35 generate
+		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+   end generate gpio1_gen;
+	
+b2v_inst19 : gpio
+PORT MAP(clk => CLK,
+		 gpio_enable => GPIO_ENABLE,
+		 pot_reset => POT_RESET,
+		 virtual_keyheld => KEY_HELD,
+		 virtual_shift_pressed => SHIFT_PRESSED,
+		 virtual_control_pressed => KBCODE(7),
+		 virtual_break_pressed => BREAK_PRESSED,
+		 pbi_write_enable => PBI_WRITE_ENABLE,
+		 cart_request => CART_REQUEST,
+		 s4_n => CART_S4_n,
+		 s5_n => CART_S5_N,
+		 cctl_n => CART_CCTL_N,
+		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+		 GPIO_0_IN => GPIO_0,
+		 GPIO_0_OUT => GPIO_0_OUT,
+		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+		 GPIO_1_IN => GPIO_1,
+		 GPIO_1_OUT => GPIO_1_OUT,
+		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+		 keyboard_scan => KEYBOARD_SCAN,
+		 pbi_addr_out => PBI_ADDR,
+		 porta_out => PORTA_OUT,
+		 porta_output => PORTA_DIR_OUT,
+		 virtual_keycode => KBCODE(5 DOWNTO 0),
+		 virtual_stick_in => VIRTUAL_STICKS,
+		 virtual_trig_in => VIRTUAL_TRIGGERS,
+		 lightpen => LIGHTPEN,
+		 cart_complete => CART_REQUEST_COMPLETE,
+		 rd4 => CART_RD4,
+		 rd5 => CART_RD5,
+		 cart_data_read => CART_ROM_DO,
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 porta_in => GPIO_PORTA_IN,
+		 pot_in => POT_IN,
+		 trig_in => TRIGGERS,
+		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_OUT => CA2_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_OUT => CB2_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 SIO_IN => GPIO_SIO_IN,
+		 SIO_OUT => GPIO_SIO_OUT
+		 );
+
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REPLY => SDRAM_REPLY,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT,
+		 ROM_DATA => ROM_DO,
+		 rom_select => ROM_SELECT,
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA);
+
+
+b2v_inst20 : sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => DRAM_DQ,
+		 REPLY => SDRAM_REPLY,
+		 SDRAM_BA0 => DRAM_BA_0,
+		 SDRAM_BA1 => DRAM_BA_1,
+		 SDRAM_CKE => DRAM_CKE,
+		 SDRAM_CS_N => DRAM_CS_N,
+		 SDRAM_RAS_N => DRAM_RAS_N,
+		 SDRAM_CAS_N => DRAM_CAS_N,
+		 SDRAM_WE_N => DRAM_WE_N,
+		 SDRAM_ldqm => DRAM_LDQM,
+		 SDRAM_udqm => DRAM_UDQM,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => DRAM_ADDR);
+
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B,
+		 G => VGA_G,
+		 R => VGA_R);
+
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DATA,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_THREE,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG,
+		 LEDR => LEDR,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX);
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst3 : i2c_loader
+GENERIC MAP(device_address => 26,
+			log2_divider => 6,
+			num_retries => 0
+			)
+PORT MAP(CLK => CLK,
+		 nRESET => RESET_N,
+		 I2C_SCL => I2C_SCLK,
+		 I2C_SDA => I2C_SDAT);
+
+
+b2v_inst4 : flashrom
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 REQUEST => ROM_REQUEST,
+		 ADDRESS => ROM_ADDR,
+		 FLASH_D => FL_DQ,
+		 FLASH_OE_N => FL_OE_N,
+		 FLASH_WE_N => FL_WE_N,
+		 FLASH_RESET_N => FL_RST_N,
+		 COMPLETE => ROM_REQUEST_COMPLETE,
+		 DOUT => ROM_DO,
+		 FLASH_ADDRESS => FL_ADDR);
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => CLOCK_50,
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => DRAM_CLK,
+		 locked => PLL_LOCKED);
+
+
+b2v_inst6 : i2sslave
+PORT MAP(CLK => CLK,
+		 BCLK => AUD_BCLK,
+		 DACLRC => AUD_DACLRCK,
+		 LEFT_IN => AUDIO_LEFT,
+		 RIGHT_IN => AUDIO_RIGHT,
+		 MCLK_2 => AUD_XCK,
+		 DACDAT => AUD_DACDAT);
+
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => UART_RXD,
+		 SIO_IN2 => GPIO_SIO_IN,
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => TRIGGERS(0),
+		 TRIG1 => TRIGGERS(1),
+		 TRIG2 => TRIGGERS(2),
+		 TRIG3 => TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+
+END bdf_type;
\ No newline at end of file
Index: unmerged/core/mist/basic.qip
===================================================================
--- unmerged/core/mist/basic.qip	(nonexistent)
+++ unmerged/core/mist/basic.qip	(revision 1)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "basic.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "basic.cmp"]
Index: unmerged/core/mist/covox.vhd
===================================================================
--- unmerged/core/mist/covox.vhd	(nonexistent)
+++ unmerged/core/mist/covox.vhd	(revision 1)
@@ -0,0 +1,92 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY covox IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	covox_channel0 : out std_logic_vector(7 downto 0);
+	covox_channel1 : out std_logic_vector(7 downto 0);
+	covox_channel2 : out std_logic_vector(7 downto 0);
+	covox_channel3 : out std_logic_vector(7 downto 0)
+);
+END covox;
+
+ARCHITECTURE vhdl OF covox IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	signal channel0_next : std_logic_vector(7 downto 0);
+	signal channel1_next : std_logic_vector(7 downto 0);
+	signal channel2_next : std_logic_vector(7 downto 0);
+	signal channel3_next : std_logic_vector(7 downto 0);
+	signal channel0_reg : std_logic_vector(7 downto 0);
+	signal channel1_reg : std_logic_vector(7 downto 0);
+	signal channel2_reg : std_logic_vector(7 downto 0);
+	signal channel3_reg : std_logic_vector(7 downto 0);
+	
+	signal addr_decoded : std_logic_vector(3 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => 2)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(channel0_reg,channel1_reg,channel2_reg,channel3_reg,addr_decoded,data_in,WR_EN)
+	begin
+		channel0_next <= channel0_reg;
+		channel1_next <= channel1_reg;
+		channel2_next <= channel2_reg;
+		channel3_next <= channel3_reg;
+		
+		if (WR_EN = '1') then		
+			if (addr_decoded(0) = '1') then				
+				channel0_next <= data_in;
+			end if;
+			if (addr_decoded(1) = '1') then				
+				channel1_next <= data_in;
+			end if;
+			if (addr_decoded(2) = '1') then				
+				channel2_next <= data_in;
+			end if;
+			if (addr_decoded(3) = '1') then				
+				channel3_next <= data_in;
+			end if;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			channel0_reg <= channel0_next;
+			channel1_reg <= channel1_next;
+			channel2_reg <= channel2_next;
+			channel3_reg <= channel3_next;
+		end if;
+	end process;
+	
+	-- output
+	covox_channel0 <= channel0_reg;
+	covox_channel1 <= channel1_reg;
+	covox_channel2 <= channel2_reg;
+	covox_channel3 <= channel3_reg;
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/cpu_65xx_a.vhd
===================================================================
--- unmerged/core/mist/cpu_65xx_a.vhd	(nonexistent)
+++ unmerged/core/mist/cpu_65xx_a.vhd	(revision 1)
@@ -0,0 +1,1599 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2011 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processNmi : std_logic := '0';
+	signal processIrq : std_logic := '0';
+	signal processInt : std_logic := '0';
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal so_reg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAX  & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluAnd, -- AB iLXA imm - MWW:change for Atari800 CPU
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal halt_dly : std_logic := '0'; -- !!! TODO: high address correction on boundary crossing continues on BA=0. Temp register to remember that incr is done.
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal Creg: std_logic; -- Carry
+	signal Zreg: std_logic; -- Zero flag
+	signal Ireg: std_logic; -- Interrupt flag
+	signal Dreg: std_logic; -- Decimal mode
+	signal Vreg: std_logic; -- Overflow
+	signal Nreg: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, Nreg, Vreg, Dreg, Ireg, Zreg, Creg)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := Creg & aluInput;
+		when aluModeP =>
+			rmwBits := Creg & Nreg & Vreg & '1' & (not irqActive) & Dreg & Ireg & Zreg & Creg;
+		when aluModeInc =>
+			rmwBits := Creg & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := Creg & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & Creg;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & Creg & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := Creg & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if Dreg = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if Dreg = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if Dreg = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if Dreg = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then -- and (halt = '0') then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+					
+					if theCpuCycle = cycleStack4 -- MWW
+					or reset = '1' then
+						nmiReg <= '1';
+					end if;					
+				if halt = '0' then
+					if theCpuCycle /= cycleBranchTaken then
+						-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+						-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+						processNmi <= not (nmiReg or opcInfo(opcIRQ));
+						processIrq <= not (irqReg or opcInfo(opcIRQ));
+					end if;
+				end if;
+			end if;
+			processInt <= processNmi or (processIrq and (not Ireg));
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, d, reset, processInt)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := d;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processInt = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processInt = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, halt, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if (enable = '1') and (halt = '0') then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, Nreg, Vreg, Creg, Zreg)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (Nreg = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (Vreg = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (Creg = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Zreg = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= d;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= d;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= d;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					Creg <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Zreg <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					Ireg <= aluInput(2);
+				end if;
+			end if;
+			-- Hack to bypass 1 clock delay when CLI is interrupted by RDY/HALT.
+			if enable = '1' and (theCpuCycle = cycle2) and (halt = '1') then
+				if (theOpcode = X"58") then
+					Ireg <= '0';
+				end if;
+				if (theOpcode = X"78") then
+					Ireg <= '1';
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					Dreg <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					Vreg <= aluV;
+				end if;
+			end if;
+			if so_reg = '1' and so_n = '0' then
+				Vreg <= '1';
+			end if;
+			so_reg <= so_n;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					Nreg <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if (enable = '1') and (halt = '0') then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					q <= T; -- Read-modify-write write old value first.
+					doReg <= d; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	q <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+				if reset = '1' then
+					theWe <= '0';
+				end if;
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') and (halt = '0') then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else
+							PC <= myAddr;
+						end if;
+					end if;
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when opcodeFetch =>
+			if processInt = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else
+				nextAddr <= nextAddrAbsIndexed;
+			end if;
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if (enable = '1') then
+				halt_dly <= halt;
+			end if;
+			if (enable = '1') and (halt = '0') then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+-- !!! TODO fix properly. Real CPU updates address even if BA=0. Using halt_dly to emulate behavior until proper fix.
+--				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= d & T;
+				when nextAddrAbsIndexed => myAddr <= d & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & d;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+			if (enable = '1') and (halt_dly = '0') then
+				case nextAddr is
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= (aluRmwOut and (myAddr(15 downto 8) + 1)) when (opcInfo(opcInH) and (opcInfo(opcInY) or opcInfo(opcInX))) = '1'
+					else myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	debug_flags <= Nreg & Vreg & "10" & Dreg & Ireg & Zreg & Creg;
+
+end architecture;
+
+
Index: unmerged/core/mist/data_io.vhdl
===================================================================
--- unmerged/core/mist/data_io.vhdl	(nonexistent)
+++ unmerged/core/mist/data_io.vhdl	(revision 1)
@@ -0,0 +1,204 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY data_io IS 
+	PORT
+	(
+		CLK : in std_logic;
+		RESET_n : in std_logic;
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO: out std_logic;
+	   SPI_MOSI : in std_logic;
+		
+		-- Sector access request
+		request : in std_logic;
+		sector : in std_logic_vector(23 downto 0);
+		ready : out std_logic;
+		
+		-- DMA to RAM
+		ADDR: out std_logic_vector(8 downto 0);
+		DATA_OUT : out std_logic_vector(7 downto 0);
+		DATA_IN : in std_logic_vector(7 downto 0);
+		WR_EN : out std_logic
+	 );
+end data_io;
+
+architecture vhdl of data_io is
+
+
+   signal sbuf_next : std_logic_vector(6 downto 0);
+	signal sbuf_reg : std_logic_vector(6 downto 0);
+	
+   signal cmd_next : std_logic_vector(7 downto 0);
+	signal cmd_reg : std_logic_vector(7 downto 0);
+	
+	signal cnt_next : std_logic_vector(15 downto 0);
+	signal cnt_reg : std_logic_vector(15 downto 0);
+
+	signal data_out_next : std_logic_vector(7 downto 0);
+	signal data_out_reg : std_logic_vector(7 downto 0);
+
+	signal addr_next : std_logic_vector(8 downto 0);
+	signal addr_reg : std_logic_vector(8 downto 0);
+
+	signal wren_next : std_logic;
+	signal wren_reg : std_logic;
+
+	signal ready_next : std_logic;
+	signal ready_reg : std_logic;
+	
+	signal transmit_next : std_logic_vector(7 downto 0);
+	signal transmit_reg : std_logic_vector(7 downto 0);
+	
+	signal sector_next : std_logic_vector(23 downto 0);
+	signal sector_reg : std_logic_vector(23 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+begin	 
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			cnt_reg <= (others=>'0');
+			cmd_reg <= (others=>'0');
+			sbuf_reg <= (others=>'0');
+			
+			addr_reg <= (others => '0');
+			data_out_reg <= (others => '0');
+			wren_reg <= '0';			
+			
+			ready_reg <= '0';
+			
+			transmit_reg <= (others=>'0');
+			
+			request_reg <= '0';
+			sector_reg <=(others=>'0');
+		elsif (clk'event and clk='1') then
+			cnt_reg <= cnt_next;
+			cmd_reg <= cmd_next;
+			sbuf_reg <= sbuf_next;			
+			
+			addr_reg <= addr_next;
+			data_out_reg <= data_out_next;
+			wren_reg <= wren_next;
+			
+			ready_reg <= ready_next;
+		
+			transmit_reg <= transmit_next;
+
+			request_reg <= request_next;
+			sector_reg <= sector_next;			
+		end if;
+	end process;	
+	
+--	clk_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_clk, sync=>spi_clk_next);
+--spi_clk_next <= spi_clk;
+
+--	input_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_mosi, sync=>spi_mosi_next);
+
+--	select_sync : synchronizer
+--	PORT MAP ( CLK => clk, raw => spi_ss_io, sync=>spi_ss_next);
+
+	process(spi_ss_io,cnt_reg, sbuf_reg, transmit_reg, spi_mosi, addr_reg, cmd_reg, sector_reg, request_reg, ready_reg,request,sector)
+	begin
+		cnt_next <= cnt_reg;
+		sbuf_next <= sbuf_reg;
+		cmd_next <= cmd_reg;
+		ready_next <= ready_reg and request; -- stay ready until request cleared (received by other end)
+		
+		transmit_next <= transmit_reg;
+		
+		wren_next <= '0';
+		data_out_next <= (others=>'0');		
+		addr_next <= addr_reg;
+		
+		sector_next <= sector_reg;
+		request_next <= request_reg;		
+		
+--- It polls get_status 10 times a second
+--- it uses SPI_SS2 for this
+--- it sends command code 0x50
+--- reads 4 bytes afterwards
+
+--- it reports whenever the returned value is different then the one from previous get_status
+
+--- if the lowest byte of the status (the last transmitted of the four) is 0xa5:
+--- a sector is read from sd card with the sector no being the upper/first three bytes transmitted
+--- if the sector could be read
+--- SPI_SS2 is activated
+--- command byte 0x51 is sent
+--- all 512 sector bytes are sent
+		
+		--if (spi_clk_reg = '1' and spi_clk_next = '0') then
+		transmit_next(7 downto 1) <= transmit_reg(6 downto 0);
+		transmit_next(0) <= '0';
+
+		cnt_next <= std_logic_vector(unsigned(cnt_reg) + 1);		
+		
+		sbuf_next(6 downto 1) <= sbuf_reg(5 downto 0);
+		sbuf_next(0) <= SPI_MOSI;
+			
+		if (cnt_reg = X"0007") then
+			cmd_next(7 downto 1) <= sbuf_reg;
+			cmd_next(0) <= SPI_MOSI;
+			addr_next <= (others=>'1');
+			
+			sector_next <= sector;
+			request_next <= request;		
+		end if;
+			
+		--end if;
+		
+		if (spi_ss_io = '1') then
+			cnt_next <= (others=>'0');
+			cmd_next <= (others=>'0');
+		end if;	
+		
+		case cmd_reg is
+		when X"50" => --get status
+			case cnt_reg is 
+			when X"0008" =>
+				transmit_next <= sector_reg(23 downto 16);
+			when X"0010" =>
+				transmit_next <= sector_reg(15 downto 8);
+			when X"0018" =>
+				transmit_next <= sector_reg(7 downto 0);				
+			when X"0020" =>
+				transmit_next <= "1010010"&request_reg; --read request
+			when others =>
+				-- nothing
+			end case;
+		when X"51" => --sector read from sd, write it...
+			if (cnt_reg(2 downto 0) = "111") then
+				addr_next <= std_logic_vector(unsigned(addr_reg) + 1);
+				data_out_next(7 downto 1) <= sbuf_reg;
+				data_out_next(0) <= SPI_MOSI;
+				wren_next <= request;
+				
+				if (cnt_reg(12) = '1')then
+					ready_next <= '1';
+				end if;
+			end if;
+		when others =>
+			-- nop
+		end case;
+	end process;
+
+	-- outputs
+	addr <= addr_reg;
+	data_out <= data_out_reg;
+	wr_en <= wren_reg;
+	
+	ready <= ready_reg;
+
+	spi_miso <= transmit_next(7);
+end vhdl;
Index: unmerged/core/mist/enable_divider.vhdl
===================================================================
--- unmerged/core/mist/enable_divider.vhdl	(nonexistent)
+++ unmerged/core/mist/enable_divider.vhdl	(revision 1)
@@ -0,0 +1,76 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY enable_divider IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END enable_divider;
+
+ARCHITECTURE vhdl OF enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: unmerged/core/mist/gpio.vhd
===================================================================
--- unmerged/core/mist/gpio.vhd	(nonexistent)
+++ unmerged/core/mist/gpio.vhd	(revision 1)
@@ -0,0 +1,413 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity gpio is
+port
+(
+	clk : in std_logic;
+	
+	gpio_enable : in std_logic;
+
+	-- pia
+	porta_in : out std_logic_vector(7 downto 0);
+	virtual_stick_in : in std_logic_vector(7 downto 0);
+	porta_out : in std_logic_vector(7 downto 0);
+	porta_output : in std_logic_vector(7 downto 0);
+	CA2_DIR_OUT : IN std_logic;
+	CA2_OUT : IN std_logic;
+	CA2_IN : OUT STD_LOGIC;
+	CB2_DIR_OUT : IN std_logic;
+	CB2_OUT : IN std_logic;
+	CB2_IN : OUT STD_LOGIC;
+	
+	-- gtia
+	virtual_trig_in : in std_logic_vector(3 downto 0);
+	trig_in : out std_logic_vector(3 downto 0);
+	
+	-- antic
+	lightpen : out std_logic;
+	
+	-- pokey
+	pot_reset : in std_logic;
+	pot_in : out std_logic_vector(7 downto 0);
+	keyboard_scan : in std_logic_vector(5 downto 0);
+	keyboard_response : out std_logic_vector(1 downto 0);
+	virtual_keycode : in std_logic_vector(5 downto 0);
+	virtual_keyheld : in std_logic;
+	virtual_shift_pressed : in std_logic;
+	virtual_control_pressed : in std_logic;
+	virtual_break_pressed : in std_logic;
+	SIO_IN : OUT STD_LOGIC;
+	SIO_OUT : IN STD_LOGIC;
+	
+	-- cartridge
+	pbi_addr_out : in std_logic_vector(15 downto 0);
+	pbi_write_enable : in std_logic;
+	cart_data_read : out std_logic_vector(7 downto 0);
+	cart_request : in std_logic;
+	cart_complete : out std_logic;
+	cart_data_write : in std_logic_vector(7 downto 0);
+	rd4 : out std_logic;
+	rd5 : out std_logic;
+	s4_n : in std_logic;
+	s5_n : in std_logic;
+	cctl_n : in std_logic;
+	
+	monitor : in std_logic;
+	
+	-- gpio connections
+	GPIO_0_IN : in std_logic_vector(35 downto 0);
+	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_IN : in std_logic_vector(35 downto 0);
+	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+);
+end gpio;
+
+architecture vhdl of gpio is
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+	
+	signal pot_in_async : std_logic_vector(7 downto 0);
+	signal porta_in_async : std_logic_vector(7 downto 0);
+	signal trig_in_async : std_logic_vector(3 downto 0);
+	signal trig_in_sync : std_logic_vector(3 downto 0);
+	
+	signal read_write_n : std_logic;	
+	signal cart_data_read_async : std_logic_vector(7 downto 0);
+	signal rd4_async : std_logic;
+	signal rd5_async : std_logic;	
+	
+	signal keyboard_response_async : std_logic_vector(1 downto 0);
+	signal keyboard_response_gpio : std_logic_vector(1 downto 0);
+	
+	signal porta_in_gpio : std_logic_vector(7 downto 0);
+begin	
+-- OUTPUTS TO GPIO
+	-- unused
+	GPIO_1_DIR_OUT(18 downto 8) <= (others=>'0');
+	GPIO_1_OUT(18 downto 8) <= (others=>'0');
+	
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0');
+	GPIO_0_OUT(7 downto 5) <= (others=>'0');
+	
+	-- sio
+	GPIO_0_DIR_OUT(0) <= CA2_dir_out;
+	GPIO_0_OUT(0) <= CA2_out;
+	GPIO_0_DIR_OUT(1) <= CB2_dir_out;
+	GPIO_0_OUT(1) <= CB2_out;
+	GPIO_0_DIR_OUT(2) <= '1';
+	GPIO_0_OUT(2) <= SIO_OUT;
+	GPIO_0_DIR_OUT(3) <= '0';
+	GPIO_0_OUT(3) <= '0';
+	
+	GPIO_0_DIR_OUT(4) <= '1';
+	GPIO_0_OUT(4) <= MONITOR; -- zpu output for logic analyzer
+	
+	CA2_in <= GPIO_0_IN(0);
+	CB2_in <= GPIO_0_IN(1);
+	SIO_IN <= GPIO_0_IN(3);
+	
+	-- sticks
+	GPIO_1_OUT(35 downto 19) <= (others=>'0');
+	GPIO_1_DIR_OUT(35) <= '0'; -- trig 0
+	GPIO_1_DIR_OUT(34) <= gpio_enable and porta_output(0) and not(porta_out(0)); -- stick 0
+	GPIO_1_DIR_OUT(33) <= '0';
+	GPIO_1_DIR_OUT(32) <= gpio_enable and porta_output(1) and not(porta_out(1)); -- stick 0
+	GPIO_1_DIR_OUT(31) <= '0';
+	GPIO_1_DIR_OUT(30) <= gpio_enable and porta_output(2) and not(porta_out(2)); -- stick 0
+	GPIO_1_DIR_OUT(29) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(28) <= gpio_enable and porta_output(3) and not(porta_out(3)); -- stick 0
+	GPIO_1_DIR_OUT(27) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(26) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(25) <= '0'; -- trig 1
+	GPIO_1_DIR_OUT(24) <= gpio_enable and porta_output(4) and not(porta_out(4)); -- stick 1
+	GPIO_1_DIR_OUT(23) <= gpio_enable and porta_output(7) and not(porta_out(7)); -- stick 1
+	GPIO_1_DIR_OUT(22) <= gpio_enable and porta_output(5) and not(porta_out(5)); -- stick 1
+	GPIO_1_DIR_OUT(21) <= gpio_enable and pot_reset;
+	GPIO_1_DIR_OUT(20) <= gpio_enable and porta_output(6) and not(porta_out(6)); -- stick 1
+	GPIO_1_DIR_OUT(19 downto 8) <= (others=>'0');
+	
+	-- keyboard
+	GPIO_1_OUT(7 downto 0) <= (others=>'0');
+	GPIO_1_DIR_OUT(7) <= '0'; -- keyboard response 2
+	GPIO_1_DIR_OUT(6) <= '0'; -- keyboard response 1
+	GPIO_1_DIR_OUT(5) <= gpio_enable and not(keyboard_scan(5)); -- keyboard scan 5
+	GPIO_1_DIR_OUT(4) <= gpio_enable and not(keyboard_scan(4)); -- keyboard scan 4
+	GPIO_1_DIR_OUT(3) <= gpio_enable and not(keyboard_scan(3)); -- keyboard scan 3
+	GPIO_1_DIR_OUT(2) <= gpio_enable and not(keyboard_scan(2)); -- keyboard scan 2
+	GPIO_1_DIR_OUT(1) <= gpio_enable and not(keyboard_scan(1)); -- keyboard scan 1
+	GPIO_1_DIR_OUT(0) <= gpio_enable and not(keyboard_scan(0)); -- keyboard scan 0
+	
+	-- cart
+	GPIO_0_DIR_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_OUT(35) <= '0'; -- clock - TODO
+	GPIO_0_DIR_OUT(34) <= gpio_enable; 
+	GPIO_0_OUT(34) <= read_write_n; 
+	GPIO_0_DIR_OUT(33) <= gpio_enable;
+	GPIO_0_OUT(33) <= pbi_addr_out(10);
+	GPIO_0_DIR_OUT(32) <= gpio_enable;
+	GPIO_0_OUT(32) <= pbi_addr_out(11);
+	GPIO_0_DIR_OUT(31) <= gpio_enable and pbi_write_enable; -- d7
+	GPIO_0_OUT(31) <= cart_data_write(7); -- d7
+	GPIO_0_DIR_OUT(30) <= gpio_enable and pbi_write_enable; -- d3
+	GPIO_0_OUT(30) <= cart_data_write(3); -- d3
+	GPIO_0_DIR_OUT(29) <= gpio_enable;
+	GPIO_0_OUT(29) <= pbi_addr_out(12);
+	GPIO_0_DIR_OUT(28) <= gpio_enable;
+	GPIO_0_OUT(28) <= pbi_addr_out(9);
+	GPIO_0_DIR_OUT(27) <= gpio_enable;
+	GPIO_0_OUT(27) <= pbi_addr_out(8);
+	GPIO_0_DIR_OUT(26) <= gpio_enable;
+	GPIO_0_OUT(26) <= pbi_addr_out(7);
+	GPIO_0_DIR_OUT(25) <= gpio_enable;
+	GPIO_0_OUT(25) <= pbi_addr_out(6);
+	GPIO_0_DIR_OUT(24) <= gpio_enable;
+	GPIO_0_OUT(24) <= pbi_addr_out(5);
+	GPIO_0_DIR_OUT(23) <= gpio_enable;
+	GPIO_0_OUT(23) <= pbi_addr_out(4);
+	GPIO_0_DIR_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_OUT(22) <= '0'; -- RD4 rom present
+	GPIO_0_DIR_OUT(21) <= gpio_enable;
+	GPIO_0_OUT(21) <= S4_n;
+	GPIO_0_DIR_OUT(20) <= gpio_enable;
+	GPIO_0_OUT(20) <= pbi_addr_out(3);
+	GPIO_0_DIR_OUT(19) <= gpio_enable;
+	GPIO_0_OUT(19) <= pbi_addr_out(2);
+	GPIO_0_DIR_OUT(18) <= gpio_enable;
+	GPIO_0_OUT(18) <= pbi_addr_out(1);
+	GPIO_0_DIR_OUT(17) <= gpio_enable;
+	GPIO_0_OUT(17) <= pbi_addr_out(0);
+	GPIO_0_DIR_OUT(16) <= gpio_enable and pbi_write_enable; -- d4
+	GPIO_0_OUT(16) <= cart_data_write(4); -- d4
+	GPIO_0_DIR_OUT(15) <= gpio_enable and pbi_write_enable; -- d5
+	GPIO_0_OUT(15) <= cart_data_write(5); -- d5
+	GPIO_0_DIR_OUT(14) <= gpio_enable and pbi_write_enable; -- d2
+	GPIO_0_OUT(14) <= cart_data_write(2); -- d2
+	GPIO_0_DIR_OUT(13) <= gpio_enable and pbi_write_enable; -- d1
+	GPIO_0_OUT(13) <= cart_data_write(1); -- d1
+	GPIO_0_DIR_OUT(12) <= gpio_enable and pbi_write_enable; -- d0
+	GPIO_0_OUT(12) <= cart_data_write(0); -- d0
+	GPIO_0_DIR_OUT(11) <= gpio_enable and pbi_write_enable; -- d6
+	GPIO_0_OUT(11) <= cart_data_write(6); -- d6
+	GPIO_0_DIR_OUT(10) <= gpio_enable;
+	GPIO_0_OUT(10) <= S5_n;
+	GPIO_0_DIR_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_OUT(9) <= '0'; -- RD5 rom present
+	GPIO_0_DIR_OUT(8) <= gpio_enable; -- cart control
+	GPIO_0_OUT(8) <= CCTL_n; -- cart control
+	GPIO_0_DIR_OUT(7 downto 5) <= (others=>'0'); -- unused
+	GPIO_0_OUT(7 downto 5) <= (others=>'0'); -- unused	
+	
+-- INPUTS FROM GPIO	
+	-- sticks
+	pot_in_async <= 
+					gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable and 
+					("0000"&
+					GPIO_1_IN(27)&GPIO_1_IN(21)& -- 32/24
+					GPIO_1_IN(26)&GPIO_1_IN(29)); -- 31/34
+	pot_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(0), sync=>pot_in(0));						
+	pot_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(1), sync=>pot_in(1));						
+	pot_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(2), sync=>pot_in(2));						
+	pot_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(3), sync=>pot_in(3));							
+	pot_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(4), sync=>pot_in(4));						
+	pot_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(5), sync=>pot_in(5));						
+	pot_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(6), sync=>pot_in(6));						
+	pot_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>pot_in_async(7), sync=>pot_in(7));								
+		
+--	porta_in_async <= 
+--					not(gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable&gpio_enable) or 
+--					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+--					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33
+	porta_in_async <= 
+					GPIO_1_IN(23)&GPIO_1_IN(20)&GPIO_1_IN(22)&GPIO_1_IN(24)& -- 27/25/23/26
+					GPIO_1_IN(28)&GPIO_1_IN(30)&GPIO_1_IN(32)&GPIO_1_IN(34); -- 39/37/35/33					
+	porta_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(0), sync=>porta_in_gpio(0));						
+	porta_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(1), sync=>porta_in_gpio(1));						
+	porta_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(2), sync=>porta_in_gpio(2));						
+	porta_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(3), sync=>porta_in_gpio(3));						
+	porta_in4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(4), sync=>porta_in_gpio(4));						
+	porta_in5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(5), sync=>porta_in_gpio(5));						
+	porta_in6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(6), sync=>porta_in_gpio(6));						
+	porta_in7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>porta_in_async(7), sync=>porta_in_gpio(7));
+		
+	porta_in(7 downto 4) <= porta_in_gpio(7 downto 4) when virtual_stick_in(7 downto 4) = "1111" else virtual_stick_in(7 downto 4);
+	porta_in(3 downto 0) <= porta_in_gpio(3 downto 0) when virtual_stick_in(3 downto 0) = "1111" else virtual_stick_in(3 downto 0);
+		
+	--trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&gpio_enable&gpio_enable) or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in_async <= virtual_trig_in and (not(gpio_enable&gpio_enable&"11") or (rd5_async&"1"&GPIO_1_IN(25)&GPIO_1_IN(35)));	-- 28/40
+	trig_in0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(0), sync=>trig_in_sync(0));							
+	trig_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(1), sync=>trig_in_sync(1));							
+	trig_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(2), sync=>trig_in_sync(2));							
+	trig_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>trig_in_async(3), sync=>trig_in_sync(3));		
+
+	trig_in <= trig_in_sync;
+		
+	lightpen <= trig_in_sync(0) and trig_in_sync(1); -- either joystick button				
+	
+	-- keyboard
+	keyboard_response_async <= GPIO_1_IN(7)& GPIO_1_IN(6);
+	keyboard_response1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(0), sync=>keyboard_response_gpio(0));						
+	keyboard_response2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>keyboard_response_async(1), sync=>keyboard_response_gpio(1));			
+		
+	process(gpio_enable, keyboard_scan, keyboard_response_gpio, virtual_keycode, virtual_keyheld, virtual_shift_pressed, virtual_control_pressed, virtual_break_pressed, virtual_stick_in, virtual_trig_in)
+	begin	
+		keyboard_response <= keyboard_response_gpio;
+		
+		if (gpio_enable = '0') then
+			keyboard_response <= (others=>'1');
+		end if;
+		
+		if (virtual_keyheld='1' and virtual_keycode = not(keyboard_scan)) then
+			keyboard_response(0) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and virtual_break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and virtual_shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and virtual_control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+	end process;	
+	
+	-- cartridge
+--	 1(21). S4' Chip Select--$8000 to $9FFF  A(22). RD4 ROM present--$8000 to $9FFF
+-- 2(20). A3 CPU Address bus line          B(GND). GND Ground
+-- 3(19). A2 CPU Address bus line          C(23). A4 CPU Address bus line
+-- 4(18). A1 CPU Address bus line          D(24). A5 CPU Address bus line
+-- 5(17). A0 CPU Address bus line          E(25). A6 CPU Address bus line
+-- 6(16). D4 CPU Data bus line             F(26). A7 CPU Address bus line
+-- 7(15). D5 CPU Data bus line             H(27). A8 CPU Address bus line
+-- 8(14). D2 CPU Data bus line             J(28). A9 CPU Address bus line
+-- 9(13). D1 CPU Data bus line             K(29). A12 CPU Address bus line
+--10(12). D0 CPU Data bus line             L(30). D3 CPU Data bus line
+--11(11). D6 CPU Data bus line             M(31). D7 CPU Data bus line
+--12(10). S5' Chip Select--$A000 to $BFFF  N(32). A11 CPU Address bus line
+--13(5V). +5V                              P(33). A10 CPU Address bus line
+--14(9). RD5 ROM present--$A000 to $BFFF  R(34). R/W' CPU read/write
+--15(8). CCTL' Cartridge control select   S(35). B02,Phi2 CPU Phase 2 clock
+
+	-- S4'/S5' - chip select
+	-- CTTL' - control select
+	-- R/W'
+	-- clock (not needed for rom?)
+	-- RD5 ROM present (in)
+	-- RD4 ROM present (in)
+	
+	read_write_n <= not(pbi_write_enable);
+	
+	cart_complete <= cart_request; -- TODO!
+	
+	rd4_async <= gpio_enable and GPIO_0_IN(22);
+	cart_rd4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd4_async, sync=>rd4);							
+	rd5_async <= gpio_enable and GPIO_0_IN(9);
+	cart_rd5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>rd5_async, sync=>rd5);							
+	
+	cart_data_read_async <= GPIO_0_IN(31)&GPIO_0_IN(11)&GPIO_0_IN(15)&GPIO_0_IN(16)&GPIO_0_IN(30)&GPIO_0_IN(14)&GPIO_0_IN(13)&GPIO_0_IN(12);	
+	cart_data0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(0), sync=>cart_data_read(0));							
+	cart_data1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(1), sync=>cart_data_read(1));							
+	cart_data2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(2), sync=>cart_data_read(2));							
+	cart_data3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(3), sync=>cart_data_read(3));	
+	cart_data4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(4), sync=>cart_data_read(4));							
+	cart_data5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(5), sync=>cart_data_read(5));							
+	cart_data6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(6), sync=>cart_data_read(6));							
+	cart_data7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>cart_data_read_async(7), sync=>cart_data_read(7));
+		
+	--GPIO_1(25) <= GPIO_1(29);
+	
+--40	35
+--39	34
+--38	33
+--37	32
+--36	31
+--35	30
+--34	29
+--33	28
+--32	27
+--31	26
+--30	GND
+--29	3.3V
+--28	25
+--27	24
+--26	23
+--25	22
+--24	21
+--23	20
+--22	19
+--21	18
+--20	17
+--19	16
+--18	15
+--17	14
+--16	13
+--15	12
+--14	11
+--13	10
+--12	GND
+--11	5V
+--10	9
+--9	8
+--8	7
+--7	6
+--6	5
+--5	4
+--4	3
+--3	2
+--2	1
+--1	0
+
+end vhdl;
+
+
Index: unmerged/core/mist/atari800core.qsf~
===================================================================
--- unmerged/core/mist/atari800core.qsf~	(nonexistent)
+++ unmerged/core/mist/atari800core.qsf~	(revision 1)
@@ -0,0 +1,688 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2012 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 12.1 Build 243 01/31/2013 Service Pack 1 SJ Web Edition
+# Date created = 13:58:39  April 11, 2013
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		atari800core_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C16E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY atari800core
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "12.1 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:58:39  APRIL 11, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION "12.1 SP1.33"
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_134 -to VGA_R[1]
+set_location_assignment PIN_133 -to VGA_R[2]
+set_location_assignment PIN_132 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_G[0]
+set_location_assignment PIN_142 -to VGA_G[1]
+set_location_assignment PIN_143 -to VGA_G[2]
+set_location_assignment PIN_144 -to VGA_G[3]
+set_location_assignment PIN_4 -to VGA_B[0]
+set_location_assignment PIN_7 -to VGA_B[1]
+set_location_assignment PIN_10 -to VGA_B[2]
+set_location_assignment PIN_11 -to VGA_B[3]
+set_location_assignment PIN_136 -to VGA_HS
+set_location_assignment PIN_137 -to VGA_VS
+set_global_assignment -name ENABLE_SIGNALTAP ON
+set_location_assignment PIN_44 -to SD_CLK
+set_location_assignment PIN_46 -to SD_CMD
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name BLOCK_DESIGN_NAMING AUTO
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp
+set_location_assignment PIN_28 -to AUDIO_L
+set_location_assignment PIN_30 -to AUDIO_R
+set_location_assignment PIN_53 -to CPU_RESET_n
+set_location_assignment PIN_55 -to FPGA_CLK
+set_location_assignment PIN_127 -to JOY1_n[0]
+set_location_assignment PIN_91 -to JOY1_n[1]
+set_location_assignment PIN_90 -to JOY1_n[2]
+set_location_assignment PIN_88 -to JOY1_n[3]
+set_location_assignment PIN_89 -to JOY1_n[4]
+set_location_assignment PIN_126 -to JOY1_n[5]
+set_location_assignment PIN_128 -to JOY2_n[0]
+set_location_assignment PIN_25 -to JOY2_n[1]
+set_location_assignment PIN_24 -to JOY2_n[2]
+set_location_assignment PIN_22 -to JOY2_n[3]
+set_location_assignment PIN_23 -to JOY2_n[4]
+set_location_assignment PIN_129 -to JOY2_n[5]
+set_location_assignment PIN_33 -to PS2K_DAT
+set_location_assignment PIN_39 -to PS2K_CLK
+set_location_assignment PIN_32 -to PS2M_DAT
+set_location_assignment PIN_31 -to PS2M_CLK
+set_location_assignment PIN_52 -to SD_DAT0
+set_location_assignment PIN_49 -to SD_DAT3
+set_location_assignment PIN_42 -to USB_P
+set_location_assignment PIN_43 -to USB_N
+set_location_assignment PIN_50 -to USB2_P
+set_location_assignment PIN_51 -to USB2_N
+set_location_assignment PIN_112 -to SDRAM_CLK
+set_location_assignment PIN_61 -to SDRAM_A[0]
+set_location_assignment PIN_60 -to SDRAM_A[1]
+set_location_assignment PIN_59 -to SDRAM_A[2]
+set_location_assignment PIN_58 -to SDRAM_A[3]
+set_location_assignment PIN_125 -to SDRAM_A[4]
+set_location_assignment PIN_121 -to SDRAM_A[5]
+set_location_assignment PIN_120 -to SDRAM_A[6]
+set_location_assignment PIN_119 -to SDRAM_A[7]
+set_location_assignment PIN_115 -to SDRAM_A[8]
+set_location_assignment PIN_114 -to SDRAM_A[9]
+set_location_assignment PIN_64 -to SDRAM_A[10]
+set_location_assignment PIN_113 -to SDRAM_A[11]
+set_location_assignment PIN_111 -to SDRAM_A[12]
+set_location_assignment PIN_66 -to SDRAM_BA[0]
+set_location_assignment PIN_65 -to SDRAM_BA[1]
+set_location_assignment PIN_87 -to SDRAM_DQ[0]
+set_location_assignment PIN_86 -to SDRAM_DQ[1]
+set_location_assignment PIN_85 -to SDRAM_DQ[2]
+set_location_assignment PIN_83 -to SDRAM_DQ[3]
+set_location_assignment PIN_80 -to SDRAM_DQ[4]
+set_location_assignment PIN_79 -to SDRAM_DQ[5]
+set_location_assignment PIN_77 -to SDRAM_DQ[6]
+set_location_assignment PIN_76 -to SDRAM_DQ[7]
+set_location_assignment PIN_106 -to SDRAM_DQ[8]
+set_location_assignment PIN_105 -to SDRAM_DQ[9]
+set_location_assignment PIN_104 -to SDRAM_DQ[10]
+set_location_assignment PIN_103 -to SDRAM_DQ[11]
+set_location_assignment PIN_101 -to SDRAM_DQ[12]
+set_location_assignment PIN_100 -to SDRAM_DQ[13]
+set_location_assignment PIN_99 -to SDRAM_DQ[14]
+set_location_assignment PIN_98 -to SDRAM_DQ[15]
+set_location_assignment PIN_67 -to SDRAM_CS_n
+set_location_assignment PIN_68 -to SDRAM_RAS_n
+set_location_assignment PIN_69 -to SDRAM_CAS_n
+set_location_assignment PIN_71 -to SDRAM_WE_n
+set_location_assignment PIN_6 -to CFG_DOUT
+set_location_assignment PIN_8 -to CFG_CS_n
+set_location_assignment PIN_12 -to CFG_CLK
+set_location_assignment PIN_13 -to CFG_DIN
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_location_assignment PIN_72 -to SDRAM_DQM_n[0]
+set_location_assignment PIN_110 -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[1]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SDRAM_DQM_n[0]
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name VERILOG_FILE sdram_ctrl_4_ports.v
+set_global_assignment -name VHDL_FILE romlo.vhd
+set_global_assignment -name VHDL_FILE romhi.vhd
+set_global_assignment -name VHDL_FILE ramint.vhd
+set_global_assignment -name VHDL_FILE atari800core.vhd
+set_global_assignment -name VHDL_FILE spi_master.vhd
+set_global_assignment -name VHDL_FILE zpu_config_regs.vhdl
+set_global_assignment -name VHDL_FILE zpu_rom.vhd
+set_global_assignment -name SOURCE_FILE zpu_rom.cmp
+set_global_assignment -name VHDL_FILE zpu_core.vhd
+set_global_assignment -name VHDL_FILE zpupkg.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine.vhdl
+set_global_assignment -name VHDL_FILE cpu_65xx_e.vhd
+set_global_assignment -name VHDL_FILE cpu_65xx_a.vhd
+set_global_assignment -name VHDL_FILE cpu.vhd
+set_global_assignment -name QIP_FILE pll.qip
+set_global_assignment -name SDC_FILE atari800core.sdc
+set_global_assignment -name VHDL_FILE reg_file.vhdl
+set_global_assignment -name VHDL_FILE address_decoder.vhdl
+set_global_assignment -name VHDL_FILE pokey.vhdl
+set_global_assignment -name VHDL_FILE enable_divider.vhdl
+set_global_assignment -name VHDL_FILE poly_17_9.vhdl
+set_global_assignment -name VHDL_FILE poly_5.vhdl
+set_global_assignment -name VHDL_FILE poly_4.vhdl
+set_global_assignment -name VHDL_FILE delay_line.vhdl
+set_global_assignment -name VHDL_FILE countdown_timer.vhdl
+set_global_assignment -name VHDL_FILE pokey_mixer.vhdl
+set_global_assignment -name VHDL_FILE pokey_noise_filter.vhdl
+set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl
+set_global_assignment -name VHDL_FILE ps2_keyboard.vhdl
+set_global_assignment -name VHDL_FILE pokey_ps2_decoder.vhdl
+set_global_assignment -name VHDL_FILE antic.vhdl
+set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl
+set_global_assignment -name VHDL_FILE antic_counter.vhdl
+set_global_assignment -name VHDL_FILE simple_counter.vhdl
+set_global_assignment -name VHDL_FILE gtia.vhdl
+set_global_assignment -name VHDL_FILE gtia_palette.vhdl
+set_global_assignment -name VHDL_FILE pia.vhdl
+set_global_assignment -name VHDL_FILE shared_enable.vhdl
+set_global_assignment -name VHDL_FILE gtia_player.vhdl
+set_global_assignment -name VHDL_FILE gtia_priority.vhdl
+set_global_assignment -name VHDL_FILE synchronizer.vhdl
+set_global_assignment -name VHDL_FILE scandoubler.vhdl
+set_global_assignment -name VHDL_FILE scandouble_ram_infer.vhdl
+set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd
+set_global_assignment -name VHDL_FILE wide_delay_line.vhdl
+set_global_assignment -name VHDL_FILE irq_glue.vhdl
+set_global_assignment -name VHDL_FILE pokey_keyboard_scanner.vhdl
+set_global_assignment -name VHDL_FILE zpu_glue.vhdl
+set_global_assignment -name QIP_FILE zpu_ram.qip
+set_global_assignment -name QIP_FILE zpu_rom.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
+set_global_assignment -name VHDL_FILE internalromram.vhd
+set_global_assignment -name VHDL_FILE sdram_statemachine_mcc.vhdl
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "sdram_statemachine_mcc:b2v_inst20|CLK_SDRAM" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "address_decoder:b2v_inst2|SDRAM_REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "address_decoder:b2v_inst2|SDRAM_REQUEST_COMPLETE" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "address_decoder:b2v_inst2|ZPU_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "address_decoder:b2v_inst2|ZPU_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "address_decoder:b2v_inst2|ZPU_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "address_decoder:b2v_inst2|ZPU_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "address_decoder:b2v_inst2|ZPU_ADDR[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "address_decoder:b2v_inst2|ZPU_ADDR[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "address_decoder:b2v_inst2|ZPU_ADDR[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "address_decoder:b2v_inst2|ZPU_ADDR[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "address_decoder:b2v_inst2|ZPU_ADDR[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "address_decoder:b2v_inst2|ZPU_ADDR[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "address_decoder:b2v_inst2|ZPU_ADDR[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "address_decoder:b2v_inst2|ZPU_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "address_decoder:b2v_inst2|ZPU_ADDR[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "address_decoder:b2v_inst2|ZPU_ADDR[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "address_decoder:b2v_inst2|ZPU_ADDR[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "address_decoder:b2v_inst2|ZPU_ADDR[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "address_decoder:b2v_inst2|ZPU_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "address_decoder:b2v_inst2|ZPU_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "address_decoder:b2v_inst2|ZPU_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "address_decoder:b2v_inst2|ZPU_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "address_decoder:b2v_inst2|ZPU_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "address_decoder:b2v_inst2|ZPU_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "address_decoder:b2v_inst2|ZPU_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "address_decoder:b2v_inst2|ZPU_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "address_decoder:b2v_inst2|ZPU_FETCH" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "address_decoder:b2v_inst2|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "address_decoder:b2v_inst2|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram_statemachine_mcc:b2v_inst20|ADDRESS_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram_statemachine_mcc:b2v_inst20|BYTE_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "sdram_statemachine_mcc:b2v_inst20|DATA_IN[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[23]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[24]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[25]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[26]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[27]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[28]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[29]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[30]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[31]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "sdram_statemachine_mcc:b2v_inst20|DATA_OUT[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "sdram_statemachine_mcc:b2v_inst20|LONGWORD_ACCESS" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "sdram_statemachine_mcc:b2v_inst20|READ_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "sdram_statemachine_mcc:b2v_inst20|REPLY" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "sdram_statemachine_mcc:b2v_inst20|REQUEST" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ADDR[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_BA1" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_CS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_DQ[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_RAS_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_WE_N" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_ldqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "sdram_statemachine_mcc:b2v_inst20|SDRAM_udqm" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "sdram_statemachine_mcc:b2v_inst20|WRITE_EN" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[16]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[17]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[18]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[19]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[20]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[21]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[22]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|addr_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|bena_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|fetch_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|rden_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|valid_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[10]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[11]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[12]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[13]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[14]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[15]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[2]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[3]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[4]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[5]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[6]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[7]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[8]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wdata_b0[9]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "sdram_statemachine_mcc:b2v_inst20|sdram_ctrl:sdram_mcc|wren_b0" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[0]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[1]" -section_id auto_signaltap_0
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "sdram_statemachine_mcc:b2v_inst20|state_reg[2]" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=221" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=221" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=686" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=45961" -section_id auto_signaltap_0
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=45082" -section_id auto_signaltap_0
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
Index: unmerged/core/mist/atari800core.vhd
===================================================================
--- unmerged/core/mist/atari800core.vhd	(nonexistent)
+++ unmerged/core/mist/atari800core.vhd	(revision 1)
@@ -0,0 +1,1846 @@
+-- Copyright (C) 1991-2012 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- PROGRAM		"Quartus II 64-Bit"
+-- VERSION		"Version 12.1 Build 243 01/31/2013 Service Pack 1.33 SJ Web Edition"
+-- CREATED		"Tue Dec 31 22:21:48 2013"
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all; 
+use ieee.numeric_std.all;
+
+LIBRARY work;
+
+ENTITY atari800core IS 
+	PORT
+	(
+		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
+--		PS2K_CLK :  IN  STD_LOGIC;
+--		PS2K_DAT :  IN  STD_LOGIC;
+--		PS2M_CLK :  IN  STD_LOGIC;
+--		PS2M_DAT :  IN  STD_LOGIC;		
+
+		VGA_VS :  OUT  STD_LOGIC;
+		VGA_HS :  OUT  STD_LOGIC;
+		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+--		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+--		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+		
+		AUDIO_L : OUT std_logic;
+		AUDIO_R : OUT std_logic;
+
+		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+		SDRAM_nCS :  OUT  STD_LOGIC;
+		SDRAM_nRAS :  OUT  STD_LOGIC;
+		SDRAM_nCAS :  OUT  STD_LOGIC;
+		SDRAM_nWE :  OUT  STD_LOGIC;
+		SDRAM_DQMH :  OUT  STD_LOGIC;
+		SDRAM_DQML :  OUT  STD_LOGIC;
+		SDRAM_CLK :  OUT  STD_LOGIC;
+		SDRAM_CKE :  OUT  STD_LOGIC;
+		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+
+--		SD_DAT0 :  IN  STD_LOGIC;
+--		SD_CLK :  OUT  STD_LOGIC;
+--		SD_CMD :  OUT  STD_LOGIC;
+--		SD_DAT3 :  OUT  STD_LOGIC
+
+		LED : OUT std_logic;
+		
+		UART_TX :  OUT  STD_LOGIC;
+		UART_RX :  IN  STD_LOGIC;
+		
+		SPI_DO :  INOUT  STD_LOGIC;
+		SPI_DI :  IN  STD_LOGIC;
+		SPI_SCK :  IN  STD_LOGIC;
+		SPI_SS2 :  IN  STD_LOGIC;		
+		SPI_SS3 :  IN  STD_LOGIC;		
+		SPI_SS4 :  IN  STD_LOGIC;
+		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
+	);
+END atari800core;
+
+ARCHITECTURE bdf_type OF atari800core IS 
+--
+--component generic_ram_infer IS
+--	generic
+--	(
+--		ADDRESS_WIDTH : natural := 9;
+--		SPACE : natural := 512;
+--		DATA_WIDTH : natural := 8
+--	);
+--   PORT
+--   (
+--      clock: IN   std_logic;
+--      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+--      address:  IN   std_logic_vector(address_width-1 downto 0);
+--      we:    IN   std_logic;
+--      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+--   );
+--END component;
+
+component mist_sector_buffer IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END component;
+
+component synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END component;
+
+component data_io IS 
+	PORT
+	(
+		CLK : in std_logic;
+		RESET_n : in std_logic;
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO: out std_logic;
+	   SPI_MOSI : in std_logic;
+		
+		-- Sector access request
+		request : in std_logic;
+		sector : in std_logic_vector(23 downto 0);
+		ready : out std_logic;
+		
+		-- DMA to RAM
+		ADDR: out std_logic_vector(8 downto 0);
+		DATA_OUT : out std_logic_vector(7 downto 0);
+		DATA_IN : in std_logic_vector(7 downto 0);
+		WR_EN : out std_logic
+	 );
+end component;
+
+component user_io
+	PORT(
+	   SPI_CLK : in std_logic;
+	   SPI_SS_IO : in std_logic;
+	   SPI_MISO : out std_logic;
+	   SPI_MOSI : in std_logic;
+	   CORE_TYPE : in std_logic_vector(7 downto 0);
+		JOY0 : out std_logic_vector(5 downto 0);
+		JOY1 : out std_logic_vector(5 downto 0);
+		KEYBOARD : out std_logic_vector(127 downto 0);
+		BUTTONS : out std_logic_vector(1 downto 0);
+		SWITCHES : out std_logic_vector(1 downto 0)
+	  );
+end component;
+
+COMPONENT complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);			
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END component;
+
+COMPONENT cpu
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 ENABLE : IN STD_LOGIC;
+		 IRQ_n : IN STD_LOGIC;
+		 NMI_n : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 THROTTLE : IN STD_LOGIC;
+		 RDY : IN STD_LOGIC;
+		 DI : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 R_W_n : OUT STD_LOGIC;
+		 CPU_FETCH : OUT STD_LOGIC;
+		 A : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 DO : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+component hq_dac
+port (
+  reset :in std_logic;
+  clk :in std_logic;
+  clk_ena : in std_logic;
+  pcm_in : in std_logic_vector(19 downto 0);
+  dac_out : out std_logic
+);
+end component;
+
+component internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+	
+END component;
+
+COMPONENT antic
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 ANTIC_ENABLE_179 : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 lightpen : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 NMI_N_OUT : OUT STD_LOGIC;
+		 ANTIC_READY : OUT STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL_OUT : OUT STD_LOGIC;
+		 COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 HIGHRES_COLOUR_CLOCK_OUT : OUT STD_LOGIC;
+		 dma_fetch_out : OUT STD_LOGIC;
+		 refresh_out : OUT STD_LOGIC;
+		 dma_clock_out : OUT STD_LOGIC;
+		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ledsw
+	PORT(CLK : IN STD_LOGIC;
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey_mixer
+	PORT(CLK : IN STD_LOGIC;
+		 GTIA_SOUND : IN STD_LOGIC;
+		 CHANNEL_0 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT ps2_keyboard
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PS2_CLK : IN STD_LOGIC;
+		 PS2_DAT : IN STD_LOGIC;
+		 KEY_EVENT : OUT STD_LOGIC;
+		 KEY_EXTENDED : OUT STD_LOGIC;
+		 KEY_UP : OUT STD_LOGIC;
+		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_glue
+	PORT(CLK : IN STD_LOGIC;
+		 RESET : IN STD_LOGIC;
+		 PAUSE : IN STD_LOGIC;
+		 MEMORY_READY : IN STD_LOGIC;
+		 ZPU_CONFIG_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_FETCH : OUT STD_LOGIC;
+		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : OUT STD_LOGIC;
+		 ZPU_CONFIG_WRITE : OUT STD_LOGIC;
+		 ZPU_ADDR_FETCH : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_ADDR_ROM_RAM : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_DO : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_STACK_WRITE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pokey
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 SIO_IN1 : IN STD_LOGIC;
+		 SIO_IN2 : IN STD_LOGIC;
+		 SIO_IN3 : IN STD_LOGIC;
+		 SIO_CLOCK : INOUT STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_response : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+		 POT_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 IRQ_N_OUT : OUT STD_LOGIC;
+		 SIO_OUT1 : OUT STD_LOGIC;
+		 SIO_OUT2 : OUT STD_LOGIC;
+		 SIO_OUT3 : OUT STD_LOGIC;
+		 POT_RESET : OUT STD_LOGIC;
+		 CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 keyboard_scan : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT pia
+	PORT(	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;		
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	-- pull up - i.e. 0 driven only
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); 
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC	);
+END COMPONENT;
+
+COMPONENT shared_enable
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 MEMORY_READY_CPU : IN STD_LOGIC;
+		 MEMORY_READY_ANTIC : IN STD_LOGIC;
+		 PAUSE_6502 : IN STD_LOGIC;
+		 THROTTLE_COUNT_6502 : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 POKEY_ENABLE_179 : OUT STD_LOGIC;
+		 ANTIC_ENABLE_179 : OUT STD_LOGIC;
+		 oldcpu_enable : OUT STD_LOGIC;
+		 CPU_ENABLE_OUT : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC;
+		 SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT pokey_ps2_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 KEY_EVENT : IN STD_LOGIC;
+		 KEY_EXTENDED : IN STD_LOGIC;
+		 KEY_UP : IN STD_LOGIC;
+		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 KEY_HELD : OUT STD_LOGIC;
+		 SHIFT_PRESSED : OUT STD_LOGIC;
+		 BREAK_PRESSED : OUT STD_LOGIC;
+		 KEY_INTERRUPT : OUT STD_LOGIC;
+		 CONSOL_START : OUT STD_LOGIC;
+		 CONSOL_SELECT : OUT STD_LOGIC;
+		 CONSOL_OPTION : OUT STD_LOGIC;
+		 SYSTEM_RESET : OUT STD_LOGIC;
+		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+	);
+END COMPONENT;
+
+
+COMPONENT address_decoder
+	PORT(CLK : IN STD_LOGIC;
+		 CPU_FETCH : IN STD_LOGIC;
+		 CPU_WRITE_N : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 antic_refresh : IN STD_LOGIC;
+		 ZPU_FETCH : IN STD_LOGIC;
+		 ZPU_READ_ENABLE : IN STD_LOGIC;
+		 ZPU_32BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_16BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 ZPU_8BIT_WRITE_ENABLE : IN STD_LOGIC;
+		 RAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ROM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 CART_REQUEST_COMPLETE : IN STD_LOGIC;
+		 reset_n : IN STD_LOGIC;
+		 CART_RD4 : IN STD_LOGIC;
+		 CART_RD5 : IN STD_LOGIC;
+		 use_sdram : IN STD_LOGIC;
+		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+		 ANTIC_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_ANTIC_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CART_ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CPU_ADDR : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 CPU_WRITE_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_GTIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PIA_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY2_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 rom_select : in std_logic_vector(5 downto 0);
+		 cart_select : in std_logic_vector(6 downto 0);
+		 cart_activate : in std_logic;
+		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 MEMORY_READY_ANTIC : OUT STD_LOGIC;
+		 MEMORY_READY_ZPU : OUT STD_LOGIC;
+		 MEMORY_READY_CPU : OUT STD_LOGIC;
+		 GTIA_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY_WR_ENABLE : OUT STD_LOGIC;
+		 POKEY2_WR_ENABLE : OUT STD_LOGIC;
+		 ANTIC_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_WR_ENABLE : OUT STD_LOGIC;
+		 PIA_RD_ENABLE : OUT STD_LOGIC;
+		 RAM_WR_ENABLE : OUT STD_LOGIC;
+		 PBI_WR_ENABLE : OUT STD_LOGIC;
+		 RAM_REQUEST : OUT STD_LOGIC;
+		 ROM_REQUEST : OUT STD_LOGIC;
+		 CART_REQUEST : OUT STD_LOGIC;
+		 CART_S4_n : OUT STD_LOGIC;
+		 CART_S5_n : OUT STD_LOGIC;
+		 CART_CCTL_n : OUT STD_LOGIC;
+		 WIDTH_8bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_16bit_ACCESS : OUT STD_LOGIC;
+		 WIDTH_32bit_ACCESS : OUT STD_LOGIC;
+		 SDRAM_READ_EN : OUT STD_LOGIC;
+		 SDRAM_WRITE_EN : OUT STD_LOGIC;
+		 SDRAM_REQUEST : OUT STD_LOGIC;
+		 SDRAM_REFRESH : OUT STD_LOGIC;
+		 MEMORY_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 PBI_ADDR : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 D6_WR_ENABLE : out std_logic
+	);
+END COMPONENT;
+
+COMPONENT sdram_statemachine
+GENERIC (ADDRESS_WIDTH : INTEGER;
+			AP_BIT : INTEGER;
+			COLUMN_WIDTH : INTEGER;
+			ROW_WIDTH : INTEGER
+			);
+	PORT(CLK_SYSTEM : IN STD_LOGIC;
+		 CLK_SDRAM : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 READ_EN : IN STD_LOGIC;
+		 WRITE_EN : IN STD_LOGIC;
+		 REQUEST : IN STD_LOGIC;
+		 BYTE_ACCESS : IN STD_LOGIC;
+		 WORD_ACCESS : IN STD_LOGIC;
+		 LONGWORD_ACCESS : IN STD_LOGIC;
+		 REFRESH : IN STD_LOGIC;
+		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 COMPLETE : OUT STD_LOGIC;
+		 SDRAM_BA0 : OUT STD_LOGIC;
+		 SDRAM_BA1 : OUT STD_LOGIC;
+		 SDRAM_CKE : OUT STD_LOGIC;
+		 SDRAM_CS_N : OUT STD_LOGIC;
+		 SDRAM_RAS_N : OUT STD_LOGIC;
+		 SDRAM_CAS_N : OUT STD_LOGIC;
+		 SDRAM_WE_N : OUT STD_LOGIC;
+		 SDRAM_ldqm : OUT STD_LOGIC;
+		 SDRAM_udqm : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+	);
+END COMPONENT;
+
+component sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END component;
+
+COMPONENT zpu_rom
+	PORT(clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT scandoubler
+	PORT(CLK : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 VGA : IN STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+		 colour_enable : IN STD_LOGIC;
+		 doubled_enable : IN STD_LOGIC;
+		 vsync_in : IN STD_LOGIC;
+		 hsync_in : IN STD_LOGIC;
+		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_ram
+	PORT(wren : IN STD_LOGIC;
+		 clock : IN STD_LOGIC;
+		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT zpu_config_regs
+	PORT(CLK : IN STD_LOGIC;
+		 ENABLE_179 : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 SDCARD_DAT : IN STD_LOGIC;
+		 SIO_COMMAND_OUT : IN STD_LOGIC;
+		 SIO_DATA_OUT : IN STD_LOGIC;
+		 PLL_LOCKED : IN STD_LOGIC;
+		 REQUEST_RESET_ZPU : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 SWITCH : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 SDCARD_CLK : OUT STD_LOGIC;
+		 SDCARD_CMD : OUT STD_LOGIC;
+		 SDCARD_DAT3 : OUT STD_LOGIC;
+		 SIO_DATA_IN : OUT STD_LOGIC;
+		 PAUSE_ZPU : OUT STD_LOGIC;
+		 PAL : OUT STD_LOGIC;
+		 USE_SDRAM : OUT STD_LOGIC;
+		 VGA : OUT STD_LOGIC;
+		 COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+		 GPIO_ENABLE : OUT STD_LOGIC;
+		 RESET_6502 : OUT STD_LOGIC;
+		 RESET_ZPU : OUT STD_LOGIC;
+		 RESET_N : OUT STD_LOGIC;
+		 PAUSE_6502 : OUT STD_LOGIC;
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+		 RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		 sector : out std_logic_vector(31 downto 0);
+		 sector_request : out std_logic;
+		 sector_ready : in std_logic
+	);
+END COMPONENT;
+
+COMPONENT pll
+	PORT(inclk0 : IN STD_LOGIC;
+		 c0 : OUT STD_LOGIC;
+		 c1 : OUT STD_LOGIC;
+		 c2 : OUT STD_LOGIC;
+		 locked : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+COMPONENT gtia
+	PORT(CLK : IN STD_LOGIC;
+		 WR_EN : IN STD_LOGIC;
+		 CPU_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_MEMORY_READY : IN STD_LOGIC;
+		 ANTIC_FETCH : IN STD_LOGIC;
+		 CPU_ENABLE_ORIGINAL : IN STD_LOGIC;
+		 RESET_N : IN STD_LOGIC;
+		 PAL : IN STD_LOGIC;
+		 COLOUR_CLOCK_ORIGINAL : IN STD_LOGIC;
+		 COLOUR_CLOCK : IN STD_LOGIC;
+		 COLOUR_CLOCK_HIGHRES : IN STD_LOGIC;
+		 CONSOL_START : IN STD_LOGIC;
+		 CONSOL_SELECT : IN STD_LOGIC;
+		 CONSOL_OPTION : IN STD_LOGIC;
+		 TRIG0 : IN STD_LOGIC;
+		 TRIG1 : IN STD_LOGIC;
+		 TRIG2 : IN STD_LOGIC;
+		 TRIG3 : IN STD_LOGIC;
+		 ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+		 AN : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+		 CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 VSYNC : OUT STD_LOGIC;
+		 HSYNC : OUT STD_LOGIC;
+		 sound : OUT STD_LOGIC;
+		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+	);
+END COMPONENT;
+
+COMPONENT irq_glue
+	PORT(pokey_irq : IN STD_LOGIC;
+		 pia_irqa : IN STD_LOGIC;
+		 pia_irqb : IN STD_LOGIC;
+		 combined_irq : OUT STD_LOGIC
+	);
+END COMPONENT;
+
+component reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END component;
+
+component covox IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	covox_channel0 : out std_logic_vector(7 downto 0);
+	covox_channel1 : out std_logic_vector(7 downto 0);
+	covox_channel2 : out std_logic_vector(7 downto 0);
+	covox_channel3 : out std_logic_vector(7 downto 0)
+);
+END component;
+
+SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_ANTIC_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ANTIC_ENABLE_179 :  STD_LOGIC;
+SIGNAL	ANTIC_FETCH :  STD_LOGIC;
+SIGNAL	ANTIC_HIGHRES_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_ORIGINAL_COLOUR_CLOCK_OUT :  STD_LOGIC;
+SIGNAL	ANTIC_RDY :  STD_LOGIC;
+SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+
+SIGNAL	CART_RD4 :  STD_LOGIC;
+SIGNAL	CART_RD5 :  STD_LOGIC;
+SIGNAL	CART_REQUEST :  STD_LOGIC;
+SIGNAL	CART_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	CART_ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CART_S4_n :  STD_LOGIC;
+SIGNAL	CART_S5_N :  STD_LOGIC;
+signal CART_CCTL_N : std_logic;
+SIGNAL	CA2_OUT :  STD_LOGIC;
+SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CB2_OUT :  STD_LOGIC;
+SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+SIGNAL	CLK :  STD_LOGIC;
+SIGNAL	CLK_SDRAM :  STD_LOGIC;
+SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+SIGNAL	CONSOL_START :  STD_LOGIC;
+SIGNAL	CPU_6502_RESET :  STD_LOGIC;
+SIGNAL	CPU_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	CPU_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CPU_FETCH :  STD_LOGIC;
+SIGNAL	CPU_SHARED_ENABLE :  STD_LOGIC;
+SIGNAL	ENABLE_179_MEMWAIT :  STD_LOGIC;
+SIGNAL   GPIO_0_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_0_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_IN : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL   GPIO_1_DIR_OUT : STD_LOGIC_VECTOR(35 downto 0);
+SIGNAL	GPIO_CA2_IN:  STD_LOGIC;
+SIGNAL	GPIO_CB2_IN:  STD_LOGIC;
+SIGNAL	GPIO_ENABLE :  STD_LOGIC;
+SIGNAL	GPIO_PORTA_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GPIO_PORTB_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL   GPIO_SIO_IN : STD_LOGIC;
+SIGNAL   GPIO_SIO_OUT : STD_LOGIC;
+SIGNAL	GREEN_LEDS :  STD_LOGIC_VECTOR(1 TO 1);
+SIGNAL	GREREN_LEDS :  STD_LOGIC_VECTOR(0 TO 0);
+SIGNAL	GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_GTIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	GTIA_SOUND :  STD_LOGIC;
+SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	IRQ_n :  STD_LOGIC;
+SIGNAL	KBCODE_DUMMY :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	KEY_HELD :  STD_LOGIC;
+SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+SIGNAL	KEYBOARD_SCAN :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	LIGHTPEN :  STD_LOGIC;
+SIGNAL	MEMORY_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	MEMORY_READY_ANTIC :  STD_LOGIC;
+SIGNAL	MEMORY_READY_CPU :  STD_LOGIC;
+SIGNAL	MEMORY_READY_ZPU :  STD_LOGIC;
+SIGNAL	NMI_n :  STD_LOGIC;
+SIGNAL	PAL :  STD_LOGIC;
+SIGNAL	PAUSE_6502 :  STD_LOGIC;
+SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PIA_IRQA :  STD_LOGIC;
+SIGNAL	PIA_IRQB :  STD_LOGIC;
+SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PLL_LOCKED :  STD_LOGIC;
+SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	CACHE_POKEY_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POKEY_ENABLE_179 :  STD_LOGIC;
+SIGNAL	POKEY_IRQ :  STD_LOGIC;
+SIGNAL	POKEY_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	PORTA_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTA_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	PORTB_DIR_OUT :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_IN :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	POT_RESET :  STD_LOGIC;
+SIGNAL	R_W_N :  STD_LOGIC;
+SIGNAL	RAM_ADDR :  STD_LOGIC_VECTOR(18 DOWNTO 0);
+SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	RAM_REQUEST :  STD_LOGIC;
+SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	RESET_N :  STD_LOGIC;
+SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	ROM_REQUEST :  STD_LOGIC;
+SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+--SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+SIGNAL	SIO_DATA_OUT :  STD_LOGIC;
+SIGNAL	SYNC_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNC_SWITCHES :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	SYSTEM_RESET_REQUEST :  STD_LOGIC;
+SIGNAL	THROTTLE_COUNT_6502 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+SIGNAL	TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	USE_SDRAM :  STD_LOGIC;
+SIGNAL	VGA :  STD_LOGIC;
+SIGNAL	VIRTUAL_STICKS :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	VIRTUAL_TRIGGERS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	WIDTH_16BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_32BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WIDTH_8BIT_ACCESS :  STD_LOGIC;
+SIGNAL	WRITE_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_16BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_32BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_8BIT_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_ADDR_FETCH :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_ADDR_ROM_RAM :  STD_LOGIC_VECTOR(23 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_CONFIG_WRITE_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_FETCH :  STD_LOGIC;
+SIGNAL	ZPU_HEX :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+SIGNAL	ZPU_PAUSE :  STD_LOGIC;
+SIGNAL	ZPU_RAM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+SIGNAL	ZPU_RESET :  STD_LOGIC;
+SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+
+SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+signal UART_TXD_dummy : std_logic;
+
+-- STUB OUT FOR NOW
+SIGNAL		PS2K_CLK :  STD_LOGIC;
+SIGNAL		PS2K_DAT :  STD_LOGIC;
+signal		JOY1_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal		JOY2_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+
+
+SIGNAL		SD_DAT0 :  STD_LOGIC;
+SIGNAL		SD_CLK :  STD_LOGIC;
+SIGNAL		SD_CMD :  STD_LOGIC;
+SIGNAL		SD_DAT3 :  STD_LOGIC;
+
+signal mist_buttons : std_logic_vector(1 downto 0);
+signal mist_switches : std_logic_vector(1 downto 0);
+
+signal keyboard : std_logic_vector(127 downto 0);
+signal atari_keyboard : std_logic_vector(63 downto 0);
+
+SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
+SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
+SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
+
+SIGNAL	CONSOL_OPTION_DUMMY :  STD_LOGIC;
+SIGNAL	CONSOL_SELECT_DUMMY :  STD_LOGIC;
+SIGNAL	CONSOL_START_DUMMY :  STD_LOGIC;
+
+signal capslock_pressed : std_logic;
+signal capsheld_next : std_logic;
+signal capsheld_reg : std_logic;
+
+signal mist_sector_ready : std_logic;
+signal mist_sector_ready_sync : std_logic;
+signal mist_sector_request : std_logic;
+signal mist_sector_request_sync : std_logic;
+signal mist_sector : std_logic_vector(31 downto 0);
+signal mist_sector_sync : std_logic_vector(31 downto 0);
+
+		
+signal mist_addr : std_logic_vector(8 downto 0);
+signal mist_do : std_logic_vector(7 downto 0);
+signal mist_di : std_logic_vector(7 downto 0);
+signal mist_wren : std_logic;
+
+signal spi_miso_data : std_logic;
+signal spi_miso_io : std_logic;
+
+signal covox_write_enable : std_logic;
+signal covox_channel0 : std_logic_vector(7 downto 0);
+signal covox_channel1 : std_logic_vector(7 downto 0);
+signal covox_channel2 : std_logic_vector(7 downto 0);
+signal covox_channel3 : std_logic_vector(7 downto 0);
+
+BEGIN 
+
+	
+-- mist spi io
+mist_spi_interface : data_io 
+	PORT map
+	(
+		CLK =>spi_sck,
+		RESET_n =>reset_n,
+		
+		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+		SPI_CLK =>spi_sck,
+		SPI_SS_IO => spi_ss2,
+		SPI_MISO => spi_miso_data,
+		SPI_MOSI => spi_di,
+		
+		-- Sector access request
+		request => mist_sector_request_sync,
+		sector => mist_sector_sync(23 downto 0),
+		ready => mist_sector_ready,
+		
+		-- DMA to RAM
+		ADDR => mist_addr,
+		DATA_OUT => mist_do,
+		DATA_IN => mist_di,
+		WR_EN => mist_wren
+	 );
+ 
+	select_sync : synchronizer
+	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
+
+	select_sync2 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
+
+	sector_sync0 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
+
+	sector_sync1 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
+
+	sector_sync2 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
+
+	sector_sync3 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
+
+	sector_sync4 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
+
+	sector_sync5 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
+
+	sector_sync6 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
+
+	sector_sync7 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
+
+	sector_sync8 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
+
+	sector_sync9 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
+
+	sector_sync10 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
+
+	sector_sync11 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
+
+	sector_sync12 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
+
+	sector_sync13 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
+
+	sector_sync14 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
+
+	sector_sync15 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
+
+	sector_sync16 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
+
+	sector_sync17 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
+
+	sector_sync18 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
+
+	sector_sync19 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
+
+	sector_sync20 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
+
+	sector_sync21 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
+
+	sector_sync22 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
+
+	sector_sync23 : synchronizer
+	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
+	
+	
+	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
+
+	-- TODO, dual port, dual clock! 
+--	mist_sector_buffer : generic_ram_infer
+--	generic map
+--	(
+--		ADDRESS_WIDTH => 9,
+--		SPACE => 512,
+--		DATA_WIDTH => 8
+--	)
+--   PORT map
+--   (
+--      clock => spi_sck,
+--      data => mist_do,
+--      address => mist_addr,
+--      we => mist_wren,
+--      q => mist_di
+--   );
+
+mist_sector_buffer1 : mist_sector_buffer
+	PORT map
+	(
+		address_a		=> mist_addr,
+		address_b		=> ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
+		clock_a		=> spi_sck,
+		clock_b		=> clk,
+		data_a		=> mist_do,
+		data_b		=> zpu_do,
+		wren_a		=> mist_wren,
+		wren_b		=> '0',
+		q_a		=> mist_di,
+		q_b		=> zpu_sector_data
+	);
+	
+my_user_io : user_io
+	PORT map(
+	   SPI_CLK => SPI_SCK,
+	   SPI_SS_IO => CONF_DATA0,
+	   SPI_MISO => SPI_miso_io,
+	   SPI_MOSI => SPI_DI,
+	   CORE_TYPE => x"A4",
+		JOY0 => joy1,
+		JOY1 => joy2,
+		KEYBOARD => keyboard,
+		BUTTONS => mist_buttons,
+		SWITCHES => mist_switches
+	  );
+	  
+	 joy1_n <= not(joy1);
+	 joy2_n <= not(joy2);
+	 
+	process(clk,reset_n)
+	begin
+		if (reset_n='0') then
+			capsheld_reg <= '0';
+		elsif (clk'event and clk='1') then
+			capsheld_reg <= capsheld_next;
+		end if;
+	end process;
+
+	process(keyboard,capsheld_reg)
+	begin
+		capsheld_next <= capsheld_reg;
+		capslock_pressed <= '0';
+		
+		if ((keyboard(58) xor capsheld_reg)='1') then
+			capsheld_next <= keyboard(58);
+			
+			-- assert something for 10 frames
+			capslock_pressed <= '1';
+		end if;
+	end process;
+	
+atari_keyboard(63) <= keyboard(30);
+atari_keyboard(62) <= keyboard(31);
+atari_keyboard(61) <= keyboard(34);
+atari_keyboard(60) <= '0';
+atari_keyboard(58) <= keyboard(32);
+atari_keyboard(57) <= keyboard(35);
+atari_keyboard(56) <= keyboard(33);
+atari_keyboard(55) <= keyboard(13);
+atari_keyboard(54) <= keyboard(12);
+atari_keyboard(53) <= keyboard(9);
+atari_keyboard(52) <= keyboard(14);
+atari_keyboard(51) <= keyboard(8);
+atari_keyboard(50) <= keyboard(11);
+atari_keyboard(48) <= keyboard(10);
+atari_keyboard(47) <= keyboard(16);
+atari_keyboard(46) <= keyboard(17);
+atari_keyboard(45) <= keyboard(20);
+atari_keyboard(44) <= keyboard(15);
+atari_keyboard(43) <= keyboard(21);
+atari_keyboard(42) <= keyboard(18);
+atari_keyboard(40) <= keyboard(19);
+atari_keyboard(39) <= keyboard(56);
+atari_keyboard(38) <= keyboard(53);
+atari_keyboard(37) <= keyboard(50);
+atari_keyboard(35) <= keyboard(49);
+atari_keyboard(34) <= keyboard(52);
+atari_keyboard(33) <= keyboard(57);
+atari_keyboard(32) <= keyboard(51);
+atari_keyboard(31) <= keyboard(2);
+atari_keyboard(30) <= keyboard(3);
+atari_keyboard(29) <= keyboard(6);
+atari_keyboard(28) <= keyboard(1);
+atari_keyboard(27) <= keyboard(7);
+atari_keyboard(26) <= keyboard(4);
+atari_keyboard(24) <= keyboard(5);
+atari_keyboard(23) <= keyboard(44);
+atari_keyboard(22) <= keyboard(45);
+atari_keyboard(21) <= keyboard(48);
+atari_keyboard(18) <= keyboard(46);
+atari_keyboard(17) <= keyboard(59);
+atari_keyboard(16) <= keyboard(47);
+atari_keyboard(15) <= keyboard(27);
+atari_keyboard(14) <= keyboard(26);
+atari_keyboard(13) <= keyboard(23);
+atari_keyboard(12) <= keyboard(28);
+atari_keyboard(11) <= keyboard(22);
+atari_keyboard(10) <= keyboard(25);
+atari_keyboard(8) <= keyboard(24);
+atari_keyboard(7) <= keyboard(41);
+atari_keyboard(6) <= keyboard(40);
+atari_keyboard(5) <= keyboard(37);
+atari_keyboard(2) <= keyboard(39);
+atari_keyboard(1) <= keyboard(36);
+atari_keyboard(0) <= keyboard(38);
+
+	  
+shift_pressed <= keyboard(54) or keyboard(42);
+control_pressed <= keyboard(29);
+break_pressed <= keyboard(96); -- TODO - not on st keyboard
+
+consol_start <= keyboard(60); --F2
+consol_select <= keyboard(61); --F3
+consol_option <= keyboard(62); -- F4
+		
+--f5 <= keyboard(63);
+--f6 <= keyboard(64);
+--f7 <= keyboard(65);
+--f8 <= keyboard(66);
+--f9 <= keyboard(67);
+--f10 <= keyboard(68);
+
+virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
+SYSTEM_RESET_REQUEST <= keyboard(63);
+
+process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
+	begin	
+		keyboard_response <= (others=>'1');		
+		
+		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
+			keyboard_response(0) <= '0';
+		end if;
+		
+--		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+--			keyboard_response(0) <= '0';
+--		end if;
+		
+		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+		
+		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+
+		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
+			keyboard_response(1) <= '0';
+		end if;
+end process;		 
+		  
+	-- decode address
+--decode_addr1 : complete_address_decoder
+--	generic map(width=>6)
+--	port map (addr_in=>keyboard_scan, addr_decoded=>keyboard_scan_decoded);
+	  
+b2v_a_6502 : cpu
+PORT MAP(CLK => CLK,
+		 RESET => CPU_6502_RESET,
+		 ENABLE => RESET_N,
+		 IRQ_n => IRQ_n,
+		 NMI_n => NMI_n,
+		 MEMORY_READY => MEMORY_READY_CPU,
+		 THROTTLE => CPU_SHARED_ENABLE,
+		 RDY => ANTIC_RDY,
+		 DI => MEMORY_DATA(7 DOWNTO 0),
+		 R_W_n => R_W_N,
+		 CPU_FETCH => CPU_FETCH,
+		 A => CPU_ADDR,
+		 DO => CPU_DO);
+
+LIGHTPEN <= '1';
+b2v_inst1 : antic
+PORT MAP(CLK => CLK,
+		 WR_EN => ANTIC_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 PAL => PAL,
+		 lightpen => LIGHTPEN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 NMI_N_OUT => NMI_n,
+		 ANTIC_READY => ANTIC_RDY,
+		 COLOUR_CLOCK_ORIGINAL_OUT => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 dma_fetch_out => ANTIC_FETCH,
+		 refresh_out => ANTIC_REFRESH,
+		 AN => ANTIC_AN,
+		 DATA_OUT => ANTIC_DO,
+		 dma_address_out => ANTIC_ADDR);
+
+b2v_inst11 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+		 COVOX_CHANNEL_0 => covox_channel0,
+		 COVOX_CHANNEL_1 => covox_channel1,
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_LEFT);
+		 
+dac_left : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_left&"0000",
+  dac_out => audio_l
+);
+
+dac_right : hq_dac
+port map
+(
+  reset => not(reset_n),
+  clk => clk,
+  clk_ena => '1',
+  pcm_in => audio_right&"0000",
+  dac_out => audio_r
+);
+
+
+b2v_inst12 : ps2_keyboard
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 PS2_CLK => PS2K_CLK,
+		 PS2_DAT => PS2K_DAT,
+		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+		 KEY_UP => SYNTHESIZED_WIRE_10,
+		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+
+
+b2v_inst13 : zpu_glue
+PORT MAP(CLK => CLK,
+		 RESET => ZPU_RESET,
+		 PAUSE => ZPU_PAUSE,
+		 MEMORY_READY => MEMORY_READY_ZPU,
+		 ZPU_CONFIG_DI => ZPU_CONFIG_DO,
+		 ZPU_DI => MEMORY_DATA,
+		 ZPU_RAM_DI => ZPU_RAM_DATA,
+		 ZPU_ROM_DI => ZPU_ROM_DATA,
+		 ZPU_SECTOR_DI => zpu_sector_data,
+		 MEMORY_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 ZPU_CONFIG_WRITE => ZPU_CONFIG_WRITE_ENABLE,
+		 ZPU_ADDR_FETCH => ZPU_ADDR_FETCH,
+		 ZPU_ADDR_ROM_RAM => ZPU_ADDR_ROM_RAM,
+		 ZPU_DO => ZPU_DO,
+		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+
+
+b2v_inst14 : pokey_mixer
+PORT MAP(CLK => CLK,
+		 GTIA_SOUND => GTIA_SOUND,
+		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+		 COVOX_CHANNEL_0 => covox_channel2,
+		 COVOX_CHANNEL_1 => covox_channel3, 
+		 CHANNEL_ENABLE => "1111",
+		 VOLUME_OUT => AUDIO_RIGHT);
+
+
+b2v_inst15 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY2_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+		 DATA_OUT => POKEY2_DO,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => '1',
+		 keyboard_response => "00",
+		 pot_in=>"00000000");
+
+
+-- PIA
+--GPIO_0[0] <= CA2_OUT when CA2_DIR_OUT='1' else 'Z';
+--CA2_IN <= GPIO_0[0];
+
+--GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+--CB2_IN <= GPIO_O[1];
+SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
+-- TODO - sioto gpio!
+GPIO_PORTB_IN <= PORTB_OUT;
+GPIO_CA2_IN <= CA2_OUT;
+GPIO_CB2_IN <= CB2_OUT;
+GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
+
+b2v_inst16 : pia
+PORT MAP(CLK => CLK,
+		 EN => PIA_READ_ENABLE,
+		 WR_EN => PIA_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 CA1 => '1', --todo - high/low?
+		 CB1 => '1',
+		 CA2_DIR_OUT => CA2_DIR_OUT,
+		 CA2_IN => GPIO_CA2_IN,
+		 CA2_OUT => CA2_OUT,
+		 CB2_DIR_OUT => CB2_DIR_OUT,
+		 CB2_IN => GPIO_CB2_IN,
+		 CB2_OUT => CB2_OUT,
+		 ADDR => PBI_ADDR(1 DOWNTO 0),
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 IRQA_N => PIA_IRQA,
+		 IRQB_N => PIA_IRQB,
+		 DATA_OUT => PIA_DO,
+		 PORTA_IN => GPIO_PORTA_IN,
+		 PORTA_DIR_OUT => PORTA_DIR_OUT,
+		 PORTA_OUT => PORTA_OUT,
+		 PORTB_IN => GPIO_PORTB_IN,
+		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+		 PORTB_OUT => PORTB_OUT);
+
+b2v_inst17 : shared_enable
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 PAUSE_6502 => PAUSE_6502,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+		 oldcpu_enable => ENABLE_179_MEMWAIT,
+		 CPU_ENABLE_OUT => CPU_SHARED_ENABLE,
+		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+
+
+virtual_sticks <= (others=>'1');
+virtual_triggers <= "0011";
+--b2v_inst18 : pokey_ps2_decoder
+--PORT MAP(CLK => CLK,
+--		 RESET_N => RESET_N,
+--		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+--		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+--		 KEY_UP => SYNTHESIZED_WIRE_10,
+--		 KEY_CODE => SYNTHESIZED_WIRE_11,
+--		 KEY_HELD => KEY_HELD,
+--		 SHIFT_PRESSED => SHIFT_PRESSED_DUMMY,
+--		 BREAK_PRESSED => BREAK_PRESSED_DUMMY,
+--		 CONSOL_START => CONSOL_START_DUMMY,
+--		 CONSOL_SELECT => CONSOL_SELECT_DUMMY,
+--		 CONSOL_OPTION => CONSOL_OPTION_DUMMY,
+--		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+--		 KBCODE => KBCODE_dummy,
+--		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+--		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+--		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+
+-- no cart!
+CART_RD4 <= '0';
+CART_RD5 <= '0';
+CART_REQUEST_COMPLETE <= '0';
+CART_ROM_DO <= (others=>'0');
+
+b2v_inst2 : address_decoder
+PORT MAP(CLK => CLK,
+		 CPU_FETCH => CPU_FETCH,
+		 CPU_WRITE_N => R_W_N,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 antic_refresh => ANTIC_REFRESH,
+		 ZPU_FETCH => ZPU_FETCH,
+		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+		 ZPU_16BIT_WRITE_ENABLE => ZPU_16BIT_WRITE_ENABLE,
+		 ZPU_8BIT_WRITE_ENABLE => ZPU_8BIT_WRITE_ENABLE,
+		 RAM_REQUEST_COMPLETE => RAM_REQUEST_COMPLETE,
+		 ROM_REQUEST_COMPLETE => ROM_REQUEST_COMPLETE,
+		 CART_REQUEST_COMPLETE => CART_REQUEST_COMPLETE,
+		 reset_n => RESET_N,
+		 CART_RD4 => CART_RD4,
+		 CART_RD5 => CART_RD5,
+		 use_sdram => USE_SDRAM,
+		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 ANTIC_ADDR => ANTIC_ADDR,
+		 ANTIC_DATA => ANTIC_DO,
+		 CACHE_ANTIC_DATA => CACHE_ANTIC_DO,
+		 CART_ROM_DATA => CART_ROM_DO,
+		 CPU_ADDR => CPU_ADDR,
+		 CPU_WRITE_DATA => CPU_DO,
+		 GTIA_DATA => GTIA_DO,
+		 CACHE_GTIA_DATA => CACHE_GTIA_DO,
+		 PIA_DATA => PIA_DO,
+		 POKEY2_DATA => POKEY2_DO,
+		 CACHE_POKEY2_DATA => CACHE_POKEY2_DO,
+		 POKEY_DATA => POKEY_DO,
+		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+		 PORTB => PORTB_OUT,
+		 RAM_DATA => RAM_DO,
+		 ram_select => RAM_SELECT(2 downto 0),
+		 ROM_DATA => ROM_DO,
+		 rom_select => "00"&ROM_SELECT, -- TODO
+		 SDRAM_DATA => SDRAM_DO,
+		 ZPU_ADDR => ZPU_ADDR_FETCH,
+		 ZPU_WRITE_DATA => ZPU_DO,
+		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+		 MEMORY_READY_ZPU => MEMORY_READY_ZPU,
+		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+		 GTIA_WR_ENABLE => GTIA_WRITE_ENABLE,
+		 POKEY_WR_ENABLE => POKEY_WRITE_ENABLE,
+		 POKEY2_WR_ENABLE => POKEY2_WRITE_ENABLE,
+		 ANTIC_WR_ENABLE => ANTIC_WRITE_ENABLE,
+		 PIA_WR_ENABLE => PIA_WRITE_ENABLE,
+		 PIA_RD_ENABLE => PIA_READ_ENABLE,
+		 RAM_WR_ENABLE => RAM_WRITE_ENABLE,
+		 PBI_WR_ENABLE => PBI_WRITE_ENABLE,
+		 RAM_REQUEST => RAM_REQUEST,
+		 ROM_REQUEST => ROM_REQUEST,
+		 CART_REQUEST => CART_REQUEST,
+		 CART_S4_n => CART_S4_n,
+		 CART_S5_n => CART_S5_N,
+		 CART_CCTL_n => CART_CCTL_N,
+		 WIDTH_8bit_ACCESS => WIDTH_8BIT_ACCESS,
+		 WIDTH_16bit_ACCESS => WIDTH_16BIT_ACCESS,
+		 WIDTH_32bit_ACCESS => WIDTH_32BIT_ACCESS,
+		 SDRAM_READ_EN => SDRAM_READ_ENABLE,
+		 SDRAM_WRITE_EN => SDRAM_WRITE_ENABLE,
+		 SDRAM_REQUEST => SDRAM_REQUEST,
+		 SDRAM_REFRESH => SDRAM_REFRESH,
+		 MEMORY_DATA => MEMORY_DATA,
+		 PBI_ADDR => PBI_ADDR,
+		 RAM_ADDR => RAM_ADDR,
+		 ROM_ADDR => ROM_ADDR,
+		 SDRAM_ADDR => SDRAM_ADDR,
+		 WRITE_DATA => WRITE_DATA,
+		 d6_wr_enable => covox_write_enable,
+		 cart_select => "0000000",
+		 cart_activate => '0');
+
+b2v_inst21 : zpu_rom
+PORT MAP(clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+		 q => ZPU_ROM_DATA);
+
+
+b2v_inst22 : scandoubler
+PORT MAP(CLK => CLK,
+		 RESET_N => RESET_N,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+		 vsync_in => SYNTHESIZED_WIRE_12,
+		 hsync_in => SYNTHESIZED_WIRE_13,
+		 colour_in => SYNTHESIZED_WIRE_14,
+		 VSYNC => VGA_VS,
+		 HSYNC => VGA_HS,
+		 B => VGA_B(5 downto 2),
+		 G => VGA_G(5 downto 2),
+		 R => VGA_R(5 downto 2));
+
+b2v_inst23 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(2),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(23 DOWNTO 16),
+		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+
+SYNC_KEYS <= (others=> '0');
+SYNC_SWITCHES <= (others=> '1');
+b2v_inst24 : zpu_config_regs
+PORT MAP(CLK => CLK,
+		 ENABLE_179 => POKEY_ENABLE_179,
+		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+		 SDCARD_DAT => SD_DAT0,
+		 SIO_COMMAND_OUT => SIO_COMMAND_OUT,
+		 SIO_DATA_OUT => SIO_DATA_OUT,
+		 PLL_LOCKED => PLL_LOCKED,
+		 REQUEST_RESET_ZPU => SYSTEM_RESET_REQUEST,
+		 ADDR => ZPU_ADDR_ROM_RAM(6 DOWNTO 2),
+		 CPU_DATA_IN => ZPU_DO,
+		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+		 SWITCH => SYNC_SWITCHES,
+		 SDCARD_CLK => SD_CLK,
+		 SDCARD_CMD => SD_CMD,
+		 SDCARD_DAT3 => SD_DAT3,
+		 SIO_DATA_IN => SIO_DATA_IN,
+		 PAUSE_ZPU => ZPU_PAUSE,
+		 PAL => PAL,
+		 USE_SDRAM => USE_SDRAM,
+		 VGA => VGA,
+		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+		 GPIO_ENABLE => GPIO_ENABLE,
+		 RESET_6502 => CPU_6502_RESET,
+		 RESET_ZPU => ZPU_RESET,
+		 RESET_N => RESET_N,
+		 PAUSE_6502 => PAUSE_6502,
+		 DATA_OUT => ZPU_CONFIG_DO,
+		 LEDG => LEDG_dummy,
+		 LEDR => LEDR_dummy,
+		 RAM_SELECT => RAM_SELECT,
+		 ROM_SELECT => ROM_SELECT,
+		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+		 ZPU_HEX => ZPU_HEX,
+		 sector_request => mist_sector_request,
+		 sector => mist_sector,
+		 sector_ready => mist_sector_ready_sync
+		 );
+
+
+b2v_inst25 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(3),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(31 DOWNTO 24),
+		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+
+
+b2v_inst26 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(0),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(7 DOWNTO 0),
+		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+
+
+b2v_inst27 : zpu_ram
+PORT MAP(wren => ZPU_STACK_WRITE(1),
+		 clock => CLK,
+		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+		 data => ZPU_DO(15 DOWNTO 8),
+		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+
+
+b2v_inst5 : pll
+PORT MAP(inclk0 => CLOCK_27(0),
+		 c0 => CLK_SDRAM,
+		 c1 => CLK,
+		 c2 => SDRAM_CLK,
+		 locked => PLL_LOCKED);
+
+b2v_inst7 : pokey
+PORT MAP(CLK => CLK,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 WR_EN => POKEY_WRITE_ENABLE,
+		 RESET_N => RESET_N,
+		 SIO_IN1 => '1',
+		 SIO_IN2 => '1',
+		 SIO_IN3 => SIO_DATA_IN,
+		 ADDR => PBI_ADDR(3 DOWNTO 0),
+		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 keyboard_response => KEYBOARD_RESPONSE,
+		 POT_IN => POT_IN,
+		 IRQ_N_OUT => POKEY_IRQ,
+		 SIO_OUT1 => UART_TXD_dummy,
+		 SIO_OUT2 => GPIO_SIO_OUT,
+		 SIO_OUT3 => SIO_DATA_OUT,
+		 POT_RESET => POT_RESET,
+		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+		 DATA_OUT => POKEY_DO,
+		 keyboard_scan => KEYBOARD_SCAN);
+
+--	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+--	begin	
+--		keyboard_response <= (others=>'1');
+--		
+--		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+--			keyboard_response(0) <= '0';
+--		end if;
+--		
+--		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+--			keyboard_response(1) <= '0';
+--		end if;
+--		
+--		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+--			keyboard_response(1) <= '0';
+--		end if;
+--
+--		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
+--			keyboard_response(1) <= '0';
+--		end if;
+--	end process;		 
+--		 	 
+b2v_inst8 : gtia
+PORT MAP(CLK => CLK,
+		 WR_EN => GTIA_WRITE_ENABLE,
+		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+		 ANTIC_FETCH => ANTIC_FETCH,
+		 CPU_ENABLE_ORIGINAL => ENABLE_179_MEMWAIT,
+		 RESET_N => RESET_N,
+		 PAL => PAL,
+		 COLOUR_CLOCK_ORIGINAL => ANTIC_ORIGINAL_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK => ANTIC_COLOUR_CLOCK_OUT,
+		 COLOUR_CLOCK_HIGHRES => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+		 CONSOL_START => CONSOL_START,
+		 CONSOL_SELECT => CONSOL_SELECT,
+		 CONSOL_OPTION => CONSOL_OPTION,
+		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+		 TRIG2 => VIRTUAL_TRIGGERS(2),
+		 TRIG3 => VIRTUAL_TRIGGERS(3),
+		 ADDR => PBI_ADDR(4 DOWNTO 0),
+		 AN => ANTIC_AN,
+		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+		 VSYNC => SYNTHESIZED_WIRE_12,
+		 HSYNC => SYNTHESIZED_WIRE_13,
+		 sound => GTIA_SOUND,
+		 COLOUR_out => SYNTHESIZED_WIRE_14,
+		 DATA_OUT => GTIA_DO);
+
+
+b2v_inst9 : irq_glue
+PORT MAP(pokey_irq => POKEY_IRQ,
+		 pia_irqa => PIA_IRQA,
+		 pia_irqb => PIA_IRQB,
+		 combined_irq => IRQ_n);
+		 
+pokey1_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY_DO
+);	 
+
+pokey2_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => POKEY2_WRITE_ENABLE,
+	DATA_OUT => CACHE_POKEY2_DO
+);	 		 
+
+gtia_mirror : reg_file
+generic map(BYTES=>32,WIDTH=>5)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(4 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => GTIA_WRITE_ENABLE,
+	DATA_OUT => CACHE_GTIA_DO
+);	
+
+antic_mirror : reg_file
+generic map(BYTES=>16,WIDTH=>4)
+port map(
+	CLK => CLK,
+	ADDR => PBI_ADDR(3 downto 0),
+	DATA_IN => WRITE_DATA(7 downto 0),
+	WR_EN => ANTIC_WRITE_ENABLE,
+	DATA_OUT => CACHE_ANTIC_DO
+);	
+
+irr : internalromram
+  PORT map(
+    clock => clk,
+    reset_n => reset_n,
+
+	ROM_ADDR =>rom_addr,
+	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
+	ROM_REQUEST => rom_REQUEST,
+	ROM_DATA => rom_DO,
+	
+	RAM_ADDR => ram_addr,
+	RAM_WR_ENABLE => ram_WRITE_ENABLE,
+	RAM_DATA_IN => wriTE_DATA(7 downto 0),
+	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
+	RAM_REQUEST => ram_REQUEST,
+	RAM_DATA => ram_do(7 downto 0)
+	);
+
+b2v_inst20 : sdram_statemachine
+GENERIC MAP(ADDRESS_WIDTH => 22,
+			AP_BIT => 10,
+			COLUMN_WIDTH => 8,
+			ROW_WIDTH => 12
+			)
+PORT MAP(CLK_SYSTEM => CLK,
+		 CLK_SDRAM => CLK_SDRAM,
+		 RESET_N => RESET_N,
+		 READ_EN => SDRAM_READ_ENABLE,
+		 WRITE_EN => SDRAM_WRITE_ENABLE,
+		 REQUEST => SDRAM_REQUEST,
+		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+		 REFRESH => SDRAM_REFRESH,
+		 ADDRESS_IN => SDRAM_ADDR,
+		 DATA_IN => WRITE_DATA,
+		 SDRAM_DQ => SDRAM_DQ,
+		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+		 SDRAM_BA0 => SDRAM_BA(0),
+		 SDRAM_BA1 => SDRAM_BA(1),
+		 SDRAM_CKE => SDRAM_CKE,
+		 SDRAM_CS_N => SDRAM_nCS,
+		 SDRAM_RAS_N => SDRAM_nRAS,
+		 SDRAM_CAS_N => SDRAM_nCAS,
+		 SDRAM_WE_N => SDRAM_nWE,
+		 SDRAM_ldqm => SDRAM_DQML,
+		 SDRAM_udqm => SDRAM_DQMH,
+		 DATA_OUT => SDRAM_DO,
+		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+		 
+SDRAM_A(12) <= '0';
+
+--b2v_inst20 : sdram_statemachine_mcc
+--GENERIC MAP(ADDRESS_WIDTH => 22,
+--			AP_BIT => 10,
+--			COLUMN_WIDTH => 8,
+--			ROW_WIDTH => 12
+--			)
+--PORT MAP(CLK_SYSTEM => CLK,
+--		 CLK_SDRAM => CLK_SDRAM,
+--		 RESET_N => RESET_N,
+--		 READ_EN => SDRAM_READ_ENABLE,
+--		 WRITE_EN => SDRAM_WRITE_ENABLE,
+--		 REQUEST => SDRAM_REQUEST,
+--		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+--		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+--		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+--		 REFRESH => SDRAM_REFRESH,
+--		 ADDRESS_IN => SDRAM_ADDR,
+--		 DATA_IN => WRITE_DATA,
+--		 SDRAM_DQ => SDRAM_DQ,
+--		 REPLY => SDRAM_REQUEST_COMPLETE,
+--		 SDRAM_BA0 => SDRAM_BA(0),
+--		 SDRAM_BA1 => SDRAM_BA(1),
+--		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+--		 SDRAM_CS_N => SDRAM_nCS,
+--		 SDRAM_RAS_N => SDRAM_nRAS,
+--		 SDRAM_CAS_N => SDRAM_nCAS,
+--		 SDRAM_WE_N => SDRAM_nWE,
+--		 SDRAM_ldqm => SDRAM_DQML,
+--		 SDRAM_udqm => SDRAM_DQMH,
+--		 DATA_OUT => SDRAM_DO,
+--		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
+
+--SDRAM_CKE <= '1';		 
+LED <= '0';
+VGA_R(1 downto 0) <= "00";
+VGA_G(1 downto 0) <= "00";
+VGA_B(1 downto 0) <= "00";
+
+covox1 : covox
+	PORT map
+	( 
+		clk => clk,
+		addr => pbi_addr(1 downto 0),
+		data_in => WRITE_DATA(7 DOWNTO 0),
+		wr_en => covox_write_enable,
+		covox_channel0 => covox_channel0,
+		covox_channel1 => covox_channel1,
+		covox_channel2 => covox_channel2,
+		covox_channel3 => covox_channel3
+	);
+		
+END bdf_type;
\ No newline at end of file
Index: unmerged/core/mist/basic.cmp
===================================================================
--- unmerged/core/mist/basic.cmp	(nonexistent)
+++ unmerged/core/mist/basic.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component basic
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/countdown_timer.vhdl
===================================================================
--- unmerged/core/mist/countdown_timer.vhdl	(nonexistent)
+++ unmerged/core/mist/countdown_timer.vhdl	(revision 1)
@@ -0,0 +1,102 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_countdown_timer IS
+generic(UNDERFLOW_DELAY : natural := 3);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	ENABLE_UNDERFLOW : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	WR_EN : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+	DATA_OUT : OUT STD_LOGIC
+);
+END pokey_countdown_timer;
+
+ARCHITECTURE vhdl OF pokey_countdown_timer IS
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	signal count_reg : std_logic_vector(7 downto 0);
+	signal count_next: std_logic_vector(7 downto 0);
+	
+	signal underflow : std_logic;
+	
+	signal count_command : std_logic_vector(1 downto 0);	
+	signal underflow_command: std_logic_vector(1 downto 0);	
+BEGIN
+	-- Instantiate delay (provides output)
+	underflow0_delay : delay_line
+		generic map (COUNT=>UNDERFLOW_DELAY)
+		port map(clk=>clk,sync_reset=>wr_en,data_in=>underflow,enable=>ENABLE_UNDERFLOW,reset_n=>reset_n,data_out=>data_out);
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+		end if;
+	end process;
+
+	-- count down on enable
+	process(count_reg,enable,wr_en,count_command,data_in)
+	begin	
+		count_command <= enable&wr_en;
+		case count_command is
+			when "10" =>
+				count_next <= std_logic_vector(unsigned(count_reg) -1);
+			when "01"|"11" =>
+				count_next <= data_in;
+			when others =>
+				count_next <= count_reg;
+		end case;
+	end process;
+		
+	-- underflow
+	process(count_reg,enable,underflow_command)
+	begin
+		underflow_command <= enable & To_Std_Logic(count_reg = X"00");
+		case underflow_command is
+			when "11" =>
+				underflow <= '1';
+			when others =>
+				underflow <= '0';
+		end case;
+	end process;
+		
+END vhdl;
Index: unmerged/core/mist/cpu_6510.vhd
===================================================================
--- unmerged/core/mist/cpu_6510.vhd	(nonexistent)
+++ unmerged/core/mist/cpu_6510.vhd	(revision 1)
@@ -0,0 +1,201 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- 6510 wrapper for 65xx core
+-- Adds 8 bit I/O port mapped at addresses $0000 to $0001
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_6510 is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean;
+		emulate_bitfade : boolean
+	);
+	port (
+		clk : in std_logic;
+		ena_1khz : in std_logic := '0';
+		enable : in std_logic;
+		halt : in std_logic;
+		reset : in std_logic;
+		nmi_n : in std_logic;
+		irq_n : in std_logic;
+
+		we : out std_logic;
+		a : out unsigned(15 downto 0);
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+
+		diIO : in unsigned(7 downto 0);
+		doIO : out unsigned(7 downto 0);
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0);
+		debug_io : out unsigned(7 downto 0)
+	);
+end cpu_6510;
+
+-- -----------------------------------------------------------------------
+
+architecture rtl of cpu_6510 is
+	signal localA : unsigned(15 downto 0);
+	signal localD : unsigned(7 downto 0);
+	signal localQ : unsigned(7 downto 0);
+	signal localWe : std_logic;
+
+	signal currentIO : unsigned(7 downto 0);
+	signal ioDir : unsigned(7 downto 0);
+	signal ioData : unsigned(7 downto 0);
+	
+	signal accessIO : std_logic;
+	signal ioFade : unsigned(7 downto 0) := (others => '0');
+begin
+	cpuInstance: entity work.cpu_65xx
+		generic map (
+			pipelineOpcode => pipelineOpcode,
+			pipelineAluMux => pipelineAluMux,
+			pipelineAluOut => pipelineAluOut
+		)
+		port map (
+			clk => clk,
+			enable => enable,
+			halt => halt,
+			reset => reset,
+			nmi_n => nmi_n,
+			irq_n => irq_n,
+
+			d => localD,
+			q => localQ,
+			addr => localA,
+			we => localWe,
+
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugY,
+			debugS => debugS,
+			debug_flags => debug_flags
+		);
+	
+	MyBitfade: if emulate_bitfade generate
+		bitfade7 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(7),
+				d => ioData(7),
+				q => ioFade(7)
+			);
+		bitfade6 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(6),
+				d => ioData(6),
+				q => ioFade(6)
+			);
+		bitfade3 : entity work.chameleon_bitfade
+			generic map (
+				max_fade_timer => 100
+			)
+			port map (
+				clk => clk,
+				ena_1khz => ena_1khz,
+				
+				dir => ioDir(3),
+				d => ioData(3),
+				q => ioFade(3)
+			);
+	end generate;
+	
+	process(localA)
+	begin
+		accessIO <= '0';
+		if localA(15 downto 1) = 0 then
+			accessIO <= '1';
+		end if;
+	end process;
+	
+	process(d, localA, ioDir, currentIO, accessIO)
+	begin
+		localD <= d;
+		if accessIO = '1' then
+			if localA(0) = '0' then
+				localD <= ioDir;
+			else
+				localD <= currentIO;
+			end if;
+		end if;
+	end process;
+	
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if accessIO = '1' then
+				if localWe = '1'
+				and enable = '1' then
+					if localA(0) = '0' then
+						ioDir <= localQ;
+					else
+						ioData <= localQ;
+					end if;
+				end if;
+			end if;
+			if reset = '1' then
+				ioDir <= (others => '0');
+			end if;
+		end if;
+	end process;
+	
+	process(ioDir, ioData, diIO)
+	begin
+		for i in 0 to 7 loop
+			if ioDir(i) = '0' then
+				currentIO(i) <= diIO(i);
+			else
+				currentIO(i) <= ioData(i);
+			end if;
+		end loop;
+		if emulate_bitfade then
+			currentIO(7) <= ioFade(7);
+			currentIO(6) <= ioFade(6);
+			currentIO(3) <= ioFade(3);
+		end if;
+	end process;
+	
+	-- Cunnect zee wires
+	a <= localA;
+	q <= localQ;
+	we <= localWe;
+	doIO <= currentIO;
+	debug_io <= "00" & (ioData(5 downto 0) or (not ioDir(5 downto 0)));
+end architecture;
Index: unmerged/core/mist/custom_io.vhd
===================================================================
--- unmerged/core/mist/custom_io.vhd	(nonexistent)
+++ unmerged/core/mist/custom_io.vhd	(revision 1)
@@ -0,0 +1,25 @@
+library ieee;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library work;
+use work.target_pkg.all;
+use work.platform_pkg.all;
+use work.project_pkg.all;
+
+entity custom_io is
+  port
+  (
+    project_i         : out from_PROJECT_IO_t;
+    project_o         : in to_PROJECT_IO_t;
+    platform_i        : out from_PLATFORM_IO_t;
+    platform_o        : in to_PLATFORM_IO_t;
+    target_i          : out from_TARGET_IO_t;
+    target_o          : in to_TARGET_IO_t
+  );
+end entity custom_io;
+
+architecture SYN of custom_io is
+
+begin
+end architecture SYN;
Index: unmerged/core/mist/delay_line.vhdl
===================================================================
--- unmerged/core/mist/delay_line.vhdl	(nonexistent)
+++ unmerged/core/mist/delay_line.vhdl	(revision 1)
@@ -0,0 +1,57 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY delay_line IS
+generic(COUNT : natural := 1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC
+);
+END delay_line;
+
+ARCHITECTURE vhdl OF delay_line IS
+	signal shift_reg : std_logic_vector(COUNT-1 downto 0);
+	signal shift_next : std_logic_vector(COUNT-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>'0');
+		end if;		
+	end process;
+	
+	-- output
+	data_out <= shift_reg(0) and enable;
+		
+END vhdl;
Index: unmerged/core/mist/generic_ram_infer.vhdl.bak
===================================================================
--- unmerged/core/mist/generic_ram_infer.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/generic_ram_infer.vhdl.bak	(revision 1)
@@ -0,0 +1,40 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY generic_ram_infer IS
+	generic
+	(
+		ADDRESS_WIDTH : natural := 9;
+		SPACE : natural := 512;
+		DATA_WIDTH : natural := 8;
+	);
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+      address:  IN   std_logic_vector(address_width-1 downto 0);
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+   );
+END generic_ram_infer;
+
+ARCHITECTURE rtl OF generic_ram_infer IS
+   TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(to_integer(unsigned(address))) <= data;
+         END IF;
+         q <= ram_block(to_integer(unsigned(address)));
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: unmerged/core/mist/gtia_player.vhdl
===================================================================
--- unmerged/core/mist/gtia_player.vhdl	(nonexistent)
+++ unmerged/core/mist/gtia_player.vhdl	(revision 1)
@@ -0,0 +1,108 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_player IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : in std_logic;
+	
+	COLOUR_ENABLE : IN STD_LOGIC;
+	LIVE_POSITION : in std_logic_vector(7 downto 0);   -- counter ticks as display is drawn
+	PLAYER_POSITION : in std_logic_vector(7 downto 0); -- requested position
+	SIZE : in std_logic_vector(1 downto 0);
+	bitmap : in std_logic_vector(7 downto 0);
+	
+	output : out std_logic
+);
+END gtia_player;
+
+ARCHITECTURE vhdl OF gtia_player IS
+
+	-- pmgs
+	signal shift_next : std_logic_vector(7 downto 0);
+	signal shift_reg : std_logic_vector(7 downto 0);
+	signal count_next : std_logic_vector(1 downto 0);
+	signal count_reg : std_logic_vector(1 downto 0);
+begin
+		-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= (others=>'0');
+			count_reg <= (others=>'0');		
+		elsif (clk'event and clk='1') then										
+			shift_reg <= shift_next;
+			count_reg <= count_next;
+		end if;
+	end process;
+	
+	
+	process(shift_next,COLOUR_ENABLE, live_position, player_position, size, bitmap, shift_reg, count_reg)
+	begin
+		-- size is 2 bits (00 normal, 01 twice, 10 normal(bugged), 11 four times)
+		-- grafp0 is 8 bits of data (2 bits for missiles)
+		-- hposp0_reg is position - 0x30 is left side of normal playfield, 0xd0 is right size of normal playfield
+		
+		-- 'or' into shift register, so if not empty we get extra pixels
+		
+		-- counter before we shift	
+		
+		shift_next <= shift_reg;
+		count_next <= count_reg;
+		
+		output <= shift_next(7);
+		
+		if (COLOUR_ENABLE = '1') then								
+			case size is 
+				when "00" => -- normal size
+					count_next <= "00";
+					shift_next <= shift_reg(6 downto 0) &'0';
+				when "10" => -- normal size (with bug)
+					case count_reg is
+						when "00"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "01"|"10" =>
+							count_next <= "10";						
+					end case;					
+				when "01" =>					
+					case count_reg is
+						when "01"|"11" =>
+							count_next <= "00";
+							shift_next <= shift_reg(6 downto 0) &'0';
+						when "00"|"10" =>
+							count_next <= "01";							
+					end case;					
+
+				when "11" =>
+					case count_reg is
+						when "00" =>
+							count_next <= "01";
+						when "01" =>
+							count_next <= "10";						
+						when "10" =>
+							count_next <= "11";
+						when "11" =>
+							shift_next <= shift_reg(6 downto 0) &'0';
+							count_next <= "00";
+					end case;
+			end case;	
+
+			if (live_position = player_position) then
+				shift_next <= shift_reg(6 downto 0) &'0' or bitmap;
+				count_next <= (others=>'0');
+			end if;			
+		end if;
+		
+	end process;
+	
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/i2c_loader.vhd
===================================================================
--- unmerged/core/mist/i2c_loader.vhd	(nonexistent)
+++ unmerged/core/mist/i2c_loader.vhd	(revision 1)
@@ -0,0 +1,302 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+use IEEE.STD_LOGIC_MISC.ALL; -- for AND_REDUCE
+use IEEE.NUMERIC_STD.ALL;
+
+entity i2c_loader is
+generic (
+	-- Address of slave to be loaded
+	device_address : integer := 16#1a#;
+	-- Number of retries to allow before stopping
+	num_retries : integer := 0;
+	-- Length of clock divider in bits.  Resulting bus frequency is
+	-- CLK/2^(log2_divider + 2)
+	log2_divider : integer := 7
+);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	I2C_SCL		:	inout	std_logic;
+	I2C_SDA		:	inout	std_logic;
+	
+	IS_DONE		:	out std_logic;
+	IS_ERROR	:	out	std_logic
+	);
+end i2c_loader;
+
+architecture i2c_loader_arch of i2c_loader is
+type regs is array(0 to 19) of std_logic_vector(7 downto 0);
+constant init_regs : regs := (
+	-- Left line in, 0dB, mute
+	X"00", X"97",
+	-- Right line in, 0dB, mute
+	X"02", X"97",
+	-- Left headphone out, -29dB, zero cross disabled
+	--X"04", X"58",
+	X"04", X"78",
+	-- Right headphone out, -29dB, zero cross disabled
+	--X"06", X"58",
+	X"06", X"78",
+	-- Audio path, DAC enabled, Line in, Bypass off, mic muted
+	X"08", X"12",
+	-- Digital path, Unmute, HP filter enabled
+	X"0A", X"00",
+	-- Power down mic, clkout and xtal osc, line in and adc
+	X"0C", X"67",
+	-- Format 16-bit I2S, no bit inversion or phase changes, MASTER
+	X"0E", X"42",
+	-- Sampling control, Normal mode, mclk/2 used, We should provide 12.288MHz but will provide 12.25MHz - making 96KHz notional, 97.656KHz actual 
+	X"10", X"DC",
+	-- Activate
+	X"12", X"01"
+	);
+-- Number of bursts (i.e. total number of registers)
+constant burst_length : positive := 2;
+-- Number of bytes to transfer per burst
+constant num_bursts : positive := (init_regs'length / burst_length);
+	
+type state_t is (Idle, Start, Data, Ack, Stop, Pause, Done);
+signal state : state_t;
+signal phase : std_logic_vector(1 downto 0);
+subtype nbit_t is integer range 0 to 7;
+signal nbit : nbit_t;
+subtype nbyte_t is integer range 0 to burst_length; -- +1 for address byte
+signal nbyte : nbyte_t;
+subtype thisbyte_t is integer range 0 to init_regs'length; -- +1 for "done"
+signal thisbyte : thisbyte_t;
+subtype retries_t is integer range 0 to num_retries;
+signal retries : retries_t;
+
+signal clken : std_logic;
+signal divider : std_logic_vector(log2_divider-1 downto 0);
+signal shiftreg : std_logic_vector(7 downto 0);
+signal scl_out : std_logic;
+signal sda_out : std_logic;
+signal nak : std_logic;
+begin
+	-- Create open-drain outputs for I2C bus
+	I2C_SCL <= '0' when scl_out = '0' else 'Z';
+	I2C_SDA <= '0' when sda_out = '0' else 'Z';
+	-- Status outputs are driven both ways
+	IS_DONE <= '1' when state = Done else '0';
+	IS_ERROR <= nak;
+	
+	-- Generate clock enable for desired bus speed
+	clken <= AND_REDUCE(divider);
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			divider <= (others => '0');
+		elsif falling_edge(CLK) then
+			divider <= divider + '1';
+		end if;
+	end process;
+
+	-- The I2C loader process
+	process(nRESET,CLK,clken)
+	begin
+		if nRESET = '0' then
+			scl_out <= '1';
+			sda_out <= '1';
+			state <= Idle;
+			phase <= "00";
+			nbit <= 0;
+			nbyte <= 0;
+			thisbyte <= 0;
+			shiftreg <= (others => '0');
+			nak <= '0'; -- No error
+			retries <= num_retries;
+		elsif rising_edge(CLK) and clken = '1' then
+  			-- Next phase by default
+			phase <= phase + 1;
+
+			-- STATE: IDLE
+			if state = Idle then
+				-- Start loading the device registers straight away
+				-- A 'GO' bit could be polled here if required
+				state <= Start;
+				phase <= "00";
+				scl_out <= '1';
+				sda_out <= '1';
+				
+			-- STATE: START
+			elsif state = Start then
+				-- Generate START condition
+				case phase is
+				when "00" =>
+					-- Drop SDA first
+					sda_out <= '0';
+				when "10" =>
+					-- Then drop SCL
+					scl_out <= '0';
+				when "11" =>
+					-- Advance to next state
+					-- Shift register loaded with device slave address
+					state <= Data;
+					nbit <= 7;
+					shiftreg <= std_logic_vector(to_unsigned(device_address,7)) & '0'; -- writing
+					nbyte <= burst_length;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: DATA
+			elsif state = Data then
+				-- Generate data
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Output data and shift (MSb first)
+					sda_out <= shiftreg(7);
+					shiftreg <= shiftreg(6 downto 0) & '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Next bit or advance to next state when done
+					if nbit = 0 then
+						state <= Ack;
+					else
+						nbit <= nbit - 1;
+					end if;
+				when others =>
+				  null;
+				end case;
+				
+			-- STATE: ACK
+			elsif state = Ack then
+				-- Generate ACK clock and check for error condition
+				case phase is
+				when "00" =>
+					-- Drop SCL
+					scl_out <= '0';
+				when "01" =>
+					-- Float data
+					sda_out <= '1';
+				when "10" =>
+					-- Sample ack bit
+					nak <= I2C_SDA;
+					if I2C_SDA = '1' then
+						-- Error
+						nbyte <= 0; -- Close this burst and skip remaining registers
+						thisbyte <= init_regs'length;
+					else
+						-- Hold ACK to avoid spurious stops - this seems to fix a
+						-- problem with the Wolfson codec which releases the ACK
+						-- right on the falling edge of the clock pulse.  It looks like
+						-- the device interprets this is a STOP condition and then fails
+						-- to acknowledge the next byte.  We can avoid this by holding the
+						-- ACK condition for a little longer.
+						sda_out <= '0';
+					end if;
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					-- Advance to next state
+					if nbyte = 0 then
+						-- No more bytes in this burst - generate a STOP
+						state <= Stop;
+					else
+						-- Generate next byte
+						state <= Data;
+						nbit <= 7;
+						shiftreg <= init_regs(thisbyte);
+						nbyte <= nbyte - 1;
+						thisbyte <= thisbyte + 1;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: STOP
+			elsif state = Stop then
+				-- Generate STOP condition
+				case phase is
+				when "00" =>
+					-- Drop SCL first
+					scl_out <= '0';
+				when "01" =>
+					-- Drop SDA
+					sda_out <= '0';
+				when "10" =>
+					-- Raise SCL
+					scl_out <= '1';
+				when "11" =>
+					if thisbyte = init_regs'length then
+						-- All registers done, advance to finished state.  This will
+						-- bring SDA high while SCL is still high, completing the STOP
+						-- condition
+						state <= Done;
+					else
+						-- Load the next register after a short delay
+						state <= Pause;
+					end if;
+				when others =>
+					null;
+				end case;
+				
+			-- STATE: PAUSE
+			elsif state = Pause then
+				-- Delay for one cycle of 'phase' then start the next burst
+				scl_out <= '1';
+				sda_out <= '1';
+				if phase = "11" then
+					state <= Start;
+				end if;
+				
+			-- STATE: DONE
+			else
+				-- Finished
+				scl_out <= '1';
+				sda_out <= '1';
+				
+				if nak = '1' and retries > 0 then
+					-- We can retry in the event of a NAK in case the
+					-- slave got out of sync for some reason
+					retries <= retries - 1;
+					state <= Idle;
+				end if;
+			end if;
+		end if;
+	end process;
+end i2c_loader_arch;
+
Index: unmerged/core/mist/internalromram.vhd.bak
===================================================================
--- unmerged/core/mist/internalromram.vhd.bak	(nonexistent)
+++ unmerged/core/mist/internalromram.vhd.bak	(revision 1)
@@ -0,0 +1,19 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+	 
+END internalromram;
+
+
+	IROM_DATA <= IROMLO_DATA when addr(15 downto 12)=X"D" else IROMHI_DATA;		
+		if (int_ram = '1') then
+		
+			if (not(addr(15 downto 13) = "000")) then
+				USE_RAM_DATA <= X"FF";
+				RAM_WR_ENABLE <= '0'; -- ban writes over 8k when using int ram - HACK
\ No newline at end of file
Index: unmerged/core/mist/ataribas.mif
===================================================================
--- unmerged/core/mist/ataribas.mif	(nonexistent)
+++ unmerged/core/mist/ataribas.mif	(revision 1)
@@ -0,0 +1,8203 @@
+DEPTH = 8192; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 8; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : a5;
+0001 : ca;
+0002 : d0;
+0003 : 04;
+0004 : a5;
+0005 : 08;
+0006 : d0;
+0007 : 45;
+0008 : a2;
+0009 : ff;
+000a : 9a;
+000b : d8;
+000c : ae;
+000d : e7;
+000e : 02;
+000f : ac;
+0010 : e8;
+0011 : 02;
+0012 : 86;
+0013 : 80;
+0014 : 84;
+0015 : 81;
+0016 : a9;
+0017 : 00;
+0018 : 85;
+0019 : 92;
+001a : 85;
+001b : ca;
+001c : c8;
+001d : 8a;
+001e : a2;
+001f : 82;
+0020 : 95;
+0021 : 00;
+0022 : e8;
+0023 : 94;
+0024 : 00;
+0025 : e8;
+0026 : e0;
+0027 : 92;
+0028 : 90;
+0029 : f6;
+002a : a2;
+002b : 86;
+002c : a0;
+002d : 01;
+002e : 20;
+002f : 7a;
+0030 : a8;
+0031 : a2;
+0032 : 8c;
+0033 : a0;
+0034 : 03;
+0035 : 20;
+0036 : 7a;
+0037 : a8;
+0038 : a9;
+0039 : 00;
+003a : a8;
+003b : 91;
+003c : 84;
+003d : 91;
+003e : 8a;
+003f : c8;
+0040 : a9;
+0041 : 80;
+0042 : 91;
+0043 : 8a;
+0044 : c8;
+0045 : a9;
+0046 : 03;
+0047 : 91;
+0048 : 8a;
+0049 : a9;
+004a : 0a;
+004b : 85;
+004c : c9;
+004d : 20;
+004e : f1;
+004f : b8;
+0050 : 20;
+0051 : 45;
+0052 : bd;
+0053 : 20;
+0054 : 5b;
+0055 : bd;
+0056 : a5;
+0057 : 92;
+0058 : f0;
+0059 : 03;
+005a : 20;
+005b : 9d;
+005c : bd;
+005d : 20;
+005e : 62;
+005f : bd;
+0060 : a5;
+0061 : ca;
+0062 : d0;
+0063 : 9c;
+0064 : a2;
+0065 : ff;
+0066 : 9a;
+0067 : 20;
+0068 : 51;
+0069 : da;
+006a : a9;
+006b : 5d;
+006c : 85;
+006d : c2;
+006e : 20;
+006f : ed;
+0070 : bd;
+0071 : 20;
+0072 : f2;
+0073 : a9;
+0074 : f0;
+0075 : ea;
+0076 : a9;
+0077 : 00;
+0078 : 85;
+0079 : f2;
+007a : 85;
+007b : 9f;
+007c : 85;
+007d : 94;
+007e : 85;
+007f : a6;
+0080 : 85;
+0081 : b3;
+0082 : 85;
+0083 : b0;
+0084 : 85;
+0085 : b1;
+0086 : a5;
+0087 : 84;
+0088 : 85;
+0089 : ad;
+008a : a5;
+008b : 85;
+008c : 85;
+008d : ae;
+008e : 20;
+008f : a1;
+0090 : db;
+0091 : 20;
+0092 : 9a;
+0093 : a1;
+0094 : 20;
+0095 : c4;
+0096 : a2;
+0097 : a5;
+0098 : d5;
+0099 : 10;
+009a : 02;
+009b : 85;
+009c : a6;
+009d : 20;
+009e : a1;
+009f : db;
+00a0 : a4;
+00a1 : f2;
+00a2 : 84;
+00a3 : a8;
+00a4 : b1;
+00a5 : f3;
+00a6 : c9;
+00a7 : 9b;
+00a8 : d0;
+00a9 : 07;
+00aa : 24;
+00ab : a6;
+00ac : 30;
+00ad : b2;
+00ae : 4c;
+00af : 86;
+00b0 : a1;
+00b1 : a5;
+00b2 : 94;
+00b3 : 85;
+00b4 : a7;
+00b5 : 20;
+00b6 : c4;
+00b7 : a2;
+00b8 : 20;
+00b9 : a1;
+00ba : db;
+00bb : a9;
+00bc : a4;
+00bd : a0;
+00be : 9f;
+00bf : a2;
+00c0 : 02;
+00c1 : 20;
+00c2 : 54;
+00c3 : a4;
+00c4 : 86;
+00c5 : f2;
+00c6 : a5;
+00c7 : af;
+00c8 : 20;
+00c9 : c4;
+00ca : a2;
+00cb : 20;
+00cc : a1;
+00cd : db;
+00ce : 20;
+00cf : be;
+00d0 : a1;
+00d1 : 90;
+00d2 : 35;
+00d3 : a4;
+00d4 : 9f;
+00d5 : b1;
+00d6 : f3;
+00d7 : c9;
+00d8 : 9b;
+00d9 : d0;
+00da : 06;
+00db : c8;
+00dc : 91;
+00dd : f3;
+00de : 88;
+00df : a9;
+00e0 : 20;
+00e1 : 09;
+00e2 : 80;
+00e3 : 91;
+00e4 : f3;
+00e5 : a9;
+00e6 : 40;
+00e7 : 05;
+00e8 : a6;
+00e9 : 85;
+00ea : a6;
+00eb : a4;
+00ec : a8;
+00ed : 84;
+00ee : f2;
+00ef : a2;
+00f0 : 03;
+00f1 : 86;
+00f2 : a7;
+00f3 : e8;
+00f4 : 86;
+00f5 : 94;
+00f6 : a9;
+00f7 : 37;
+00f8 : 20;
+00f9 : c4;
+00fa : a2;
+00fb : a4;
+00fc : f2;
+00fd : b1;
+00fe : f3;
+00ff : e6;
+0100 : f2;
+0101 : c9;
+0102 : 9b;
+0103 : d0;
+0104 : f3;
+0105 : 20;
+0106 : c4;
+0107 : a2;
+0108 : a5;
+0109 : 94;
+010a : a4;
+010b : a7;
+010c : 91;
+010d : 80;
+010e : a4;
+010f : f2;
+0110 : 88;
+0111 : b1;
+0112 : f3;
+0113 : c9;
+0114 : 9b;
+0115 : d0;
+0116 : 9a;
+0117 : a0;
+0118 : 02;
+0119 : a5;
+011a : 94;
+011b : 91;
+011c : 80;
+011d : 20;
+011e : a2;
+011f : a9;
+0120 : a9;
+0121 : 00;
+0122 : b0;
+0123 : 03;
+0124 : 20;
+0125 : dc;
+0126 : a9;
+0127 : 38;
+0128 : e5;
+0129 : 94;
+012a : f0;
+012b : 1e;
+012c : b0;
+012d : 13;
+012e : 49;
+012f : ff;
+0130 : a8;
+0131 : c8;
+0132 : a2;
+0133 : 8a;
+0134 : 20;
+0135 : 7a;
+0136 : a8;
+0137 : a5;
+0138 : 97;
+0139 : 85;
+013a : 8a;
+013b : a5;
+013c : 98;
+013d : 85;
+013e : 8b;
+013f : d0;
+0140 : 09;
+0141 : a8;
+0142 : 20;
+0143 : d0;
+0144 : a9;
+0145 : a2;
+0146 : 8a;
+0147 : 20;
+0148 : f8;
+0149 : a8;
+014a : a4;
+014b : 94;
+014c : 88;
+014d : b1;
+014e : 80;
+014f : 91;
+0150 : 8a;
+0151 : 98;
+0152 : d0;
+0153 : f8;
+0154 : 24;
+0155 : a6;
+0156 : 50;
+0157 : 29;
+0158 : a5;
+0159 : b1;
+015a : 0a;
+015b : 0a;
+015c : 0a;
+015d : a2;
+015e : 88;
+015f : 20;
+0160 : f7;
+0161 : a8;
+0162 : 38;
+0163 : a5;
+0164 : 84;
+0165 : e5;
+0166 : ad;
+0167 : a8;
+0168 : a5;
+0169 : 85;
+016a : e5;
+016b : ae;
+016c : a2;
+016d : 84;
+016e : 20;
+016f : fa;
+0170 : a8;
+0171 : 24;
+0172 : a6;
+0173 : 10;
+0174 : 06;
+0175 : 20;
+0176 : aa;
+0177 : b5;
+0178 : 4c;
+0179 : 60;
+017a : a0;
+017b : 20;
+017c : 8e;
+017d : b5;
+017e : 4c;
+017f : 60;
+0180 : a0;
+0181 : 10;
+0182 : fb;
+0183 : 4c;
+0184 : 5e;
+0185 : a9;
+0186 : 20;
+0187 : a2;
+0188 : a9;
+0189 : b0;
+018a : f3;
+018b : 20;
+018c : dc;
+018d : a9;
+018e : a8;
+018f : 20;
+0190 : d0;
+0191 : a9;
+0192 : a2;
+0193 : 8a;
+0194 : 20;
+0195 : f8;
+0196 : a8;
+0197 : 4c;
+0198 : 60;
+0199 : a0;
+019a : 20;
+019b : 00;
+019c : d8;
+019d : 90;
+019e : 08;
+019f : a9;
+01a0 : 00;
+01a1 : 85;
+01a2 : f2;
+01a3 : a0;
+01a4 : 80;
+01a5 : 30;
+01a6 : 09;
+01a7 : 20;
+01a8 : 41;
+01a9 : ad;
+01aa : a4;
+01ab : d5;
+01ac : 30;
+01ad : f1;
+01ae : a5;
+01af : d4;
+01b0 : 84;
+01b1 : a1;
+01b2 : 85;
+01b3 : a0;
+01b4 : 20;
+01b5 : c4;
+01b6 : a2;
+01b7 : a5;
+01b8 : a1;
+01b9 : 85;
+01ba : d5;
+01bb : 4c;
+01bc : c4;
+01bd : a2;
+01be : a0;
+01bf : 01;
+01c0 : b1;
+01c1 : 95;
+01c2 : 85;
+01c3 : 9e;
+01c4 : 8d;
+01c5 : 83;
+01c6 : 04;
+01c7 : 88;
+01c8 : b1;
+01c9 : 95;
+01ca : 85;
+01cb : 9d;
+01cc : 8d;
+01cd : 82;
+01ce : 04;
+01cf : 84;
+01d0 : a9;
+01d1 : a5;
+01d2 : 94;
+01d3 : 8d;
+01d4 : 81;
+01d5 : 04;
+01d6 : a5;
+01d7 : f2;
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+1dfc : ab;
+1dfd : 20;
+1dfe : 26;
+1dff : ad;
+1e00 : 4c;
+1e01 : b2;
+1e02 : ab;
+1e03 : 38;
+1e04 : 60;
+1e05 : a9;
+1e06 : 04;
+1e07 : 24;
+1e08 : d4;
+1e09 : 10;
+1e0a : 06;
+1e0b : a9;
+1e0c : 02;
+1e0d : d0;
+1e0e : 02;
+1e0f : a9;
+1e10 : 01;
+1e11 : 85;
+1e12 : f0;
+1e13 : a5;
+1e14 : d4;
+1e15 : 29;
+1e16 : 7f;
+1e17 : 85;
+1e18 : d4;
+1e19 : a9;
+1e1a : bd;
+1e1b : 18;
+1e1c : 65;
+1e1d : fb;
+1e1e : aa;
+1e1f : a0;
+1e20 : be;
+1e21 : 20;
+1e22 : 98;
+1e23 : dd;
+1e24 : 20;
+1e25 : 28;
+1e26 : db;
+1e27 : 90;
+1e28 : 01;
+1e29 : 60;
+1e2a : a5;
+1e2b : d4;
+1e2c : 29;
+1e2d : 7f;
+1e2e : 38;
+1e2f : e9;
+1e30 : 40;
+1e31 : 30;
+1e32 : 2b;
+1e33 : c9;
+1e34 : 04;
+1e35 : 10;
+1e36 : cc;
+1e37 : aa;
+1e38 : b5;
+1e39 : d5;
+1e3a : 85;
+1e3b : f1;
+1e3c : 29;
+1e3d : 10;
+1e3e : f0;
+1e3f : 02;
+1e40 : a9;
+1e41 : 02;
+1e42 : 18;
+1e43 : 65;
+1e44 : f1;
+1e45 : 29;
+1e46 : 03;
+1e47 : 65;
+1e48 : f0;
+1e49 : 85;
+1e4a : f0;
+1e4b : 86;
+1e4c : f1;
+1e4d : 20;
+1e4e : b6;
+1e4f : dd;
+1e50 : a6;
+1e51 : f1;
+1e52 : a9;
+1e53 : 00;
+1e54 : 95;
+1e55 : e2;
+1e56 : e8;
+1e57 : e0;
+1e58 : 03;
+1e59 : 90;
+1e5a : f9;
+1e5b : 20;
+1e5c : 60;
+1e5d : da;
+1e5e : 46;
+1e5f : f0;
+1e60 : 90;
+1e61 : 0d;
+1e62 : 20;
+1e63 : b6;
+1e64 : dd;
+1e65 : a2;
+1e66 : cf;
+1e67 : a0;
+1e68 : be;
+1e69 : 20;
+1e6a : 89;
+1e6b : dd;
+1e6c : 20;
+1e6d : 60;
+1e6e : da;
+1e6f : a2;
+1e70 : e6;
+1e71 : a0;
+1e72 : 05;
+1e73 : 20;
+1e74 : a7;
+1e75 : dd;
+1e76 : 20;
+1e77 : b6;
+1e78 : dd;
+1e79 : 20;
+1e7a : db;
+1e7b : da;
+1e7c : b0;
+1e7d : 85;
+1e7e : a9;
+1e7f : 06;
+1e80 : a2;
+1e81 : 9f;
+1e82 : a0;
+1e83 : be;
+1e84 : 20;
+1e85 : 40;
+1e86 : dd;
+1e87 : a2;
+1e88 : e6;
+1e89 : a0;
+1e8a : 05;
+1e8b : 20;
+1e8c : 98;
+1e8d : dd;
+1e8e : 20;
+1e8f : db;
+1e90 : da;
+1e91 : 46;
+1e92 : f0;
+1e93 : 90;
+1e94 : 09;
+1e95 : 18;
+1e96 : a5;
+1e97 : d4;
+1e98 : f0;
+1e99 : 04;
+1e9a : 49;
+1e9b : 80;
+1e9c : 85;
+1e9d : d4;
+1e9e : 60;
+1e9f : bd;
+1ea0 : 03;
+1ea1 : 55;
+1ea2 : 14;
+1ea3 : 99;
+1ea4 : 39;
+1ea5 : 3e;
+1ea6 : 01;
+1ea7 : 60;
+1ea8 : 44;
+1ea9 : 27;
+1eaa : 52;
+1eab : be;
+1eac : 46;
+1ead : 81;
+1eae : 75;
+1eaf : 43;
+1eb0 : 55;
+1eb1 : 3f;
+1eb2 : 07;
+1eb3 : 96;
+1eb4 : 92;
+1eb5 : 62;
+1eb6 : 39;
+1eb7 : bf;
+1eb8 : 64;
+1eb9 : 59;
+1eba : 64;
+1ebb : 08;
+1ebc : 67;
+1ebd : 40;
+1ebe : 01;
+1ebf : 57;
+1ec0 : 07;
+1ec1 : 96;
+1ec2 : 32;
+1ec3 : 40;
+1ec4 : 90;
+1ec5 : 00;
+1ec6 : 00;
+1ec7 : 00;
+1ec8 : 00;
+1ec9 : 3f;
+1eca : 01;
+1ecb : 74;
+1ecc : 53;
+1ecd : 29;
+1ece : 25;
+1ecf : 40;
+1ed0 : 01;
+1ed1 : 00;
+1ed2 : 00;
+1ed3 : 00;
+1ed4 : 00;
+1ed5 : a9;
+1ed6 : 00;
+1ed7 : 85;
+1ed8 : f0;
+1ed9 : 85;
+1eda : f1;
+1edb : a5;
+1edc : d4;
+1edd : 29;
+1ede : 7f;
+1edf : c9;
+1ee0 : 40;
+1ee1 : 30;
+1ee2 : 15;
+1ee3 : a5;
+1ee4 : d4;
+1ee5 : 29;
+1ee6 : 80;
+1ee7 : 85;
+1ee8 : f0;
+1ee9 : e6;
+1eea : f1;
+1eeb : a9;
+1eec : 7f;
+1eed : 25;
+1eee : d4;
+1eef : 85;
+1ef0 : d4;
+1ef1 : a2;
+1ef2 : ea;
+1ef3 : a0;
+1ef4 : df;
+1ef5 : 20;
+1ef6 : 95;
+1ef7 : de;
+1ef8 : a2;
+1ef9 : e6;
+1efa : a0;
+1efb : 05;
+1efc : 20;
+1efd : a7;
+1efe : dd;
+1eff : 20;
+1f00 : b6;
+1f01 : dd;
+1f02 : 20;
+1f03 : db;
+1f04 : da;
+1f05 : b0;
+1f06 : 39;
+1f07 : a9;
+1f08 : 0b;
+1f09 : a2;
+1f0a : ae;
+1f0b : a0;
+1f0c : df;
+1f0d : 20;
+1f0e : 40;
+1f0f : dd;
+1f10 : b0;
+1f11 : 2e;
+1f12 : a2;
+1f13 : e6;
+1f14 : a0;
+1f15 : 05;
+1f16 : 20;
+1f17 : 98;
+1f18 : dd;
+1f19 : 20;
+1f1a : db;
+1f1b : da;
+1f1c : b0;
+1f1d : 22;
+1f1e : a5;
+1f1f : f1;
+1f20 : f0;
+1f21 : 10;
+1f22 : a2;
+1f23 : f0;
+1f24 : a0;
+1f25 : df;
+1f26 : 20;
+1f27 : 98;
+1f28 : dd;
+1f29 : 20;
+1f2a : 66;
+1f2b : da;
+1f2c : a5;
+1f2d : f0;
+1f2e : 05;
+1f2f : d4;
+1f30 : 85;
+1f31 : d4;
+1f32 : a5;
+1f33 : fb;
+1f34 : f0;
+1f35 : 0a;
+1f36 : a2;
+1f37 : c9;
+1f38 : a0;
+1f39 : be;
+1f3a : 20;
+1f3b : 98;
+1f3c : dd;
+1f3d : 20;
+1f3e : 28;
+1f3f : db;
+1f40 : 60;
+1f41 : 38;
+1f42 : 60;
+1f43 : a9;
+1f44 : 00;
+1f45 : 85;
+1f46 : f1;
+1f47 : a5;
+1f48 : d4;
+1f49 : 30;
+1f4a : f6;
+1f4b : c9;
+1f4c : 3f;
+1f4d : f0;
+1f4e : 17;
+1f4f : 18;
+1f50 : 69;
+1f51 : 01;
+1f52 : 85;
+1f53 : f1;
+1f54 : 85;
+1f55 : e0;
+1f56 : a9;
+1f57 : 01;
+1f58 : 85;
+1f59 : e1;
+1f5a : a2;
+1f5b : 04;
+1f5c : a9;
+1f5d : 00;
+1f5e : 95;
+1f5f : e2;
+1f60 : ca;
+1f61 : 10;
+1f62 : fb;
+1f63 : 20;
+1f64 : 28;
+1f65 : db;
+1f66 : a9;
+1f67 : 06;
+1f68 : 85;
+1f69 : ef;
+1f6a : a2;
+1f6b : e6;
+1f6c : a0;
+1f6d : 05;
+1f6e : 20;
+1f6f : a7;
+1f70 : dd;
+1f71 : 20;
+1f72 : b6;
+1f73 : dd;
+1f74 : a2;
+1f75 : f1;
+1f76 : a0;
+1f77 : ba;
+1f78 : 20;
+1f79 : 89;
+1f7a : dd;
+1f7b : 20;
+1f7c : 60;
+1f7d : da;
+1f7e : a2;
+1f7f : e6;
+1f80 : a0;
+1f81 : 05;
+1f82 : 20;
+1f83 : 98;
+1f84 : dd;
+1f85 : 20;
+1f86 : db;
+1f87 : da;
+1f88 : a2;
+1f89 : ec;
+1f8a : a0;
+1f8b : 05;
+1f8c : 20;
+1f8d : a7;
+1f8e : dd;
+1f8f : 20;
+1f90 : b6;
+1f91 : dd;
+1f92 : a2;
+1f93 : e6;
+1f94 : a0;
+1f95 : 05;
+1f96 : 20;
+1f97 : 89;
+1f98 : dd;
+1f99 : 20;
+1f9a : 28;
+1f9b : db;
+1f9c : a2;
+1f9d : ec;
+1f9e : a0;
+1f9f : 05;
+1fa0 : 20;
+1fa1 : 98;
+1fa2 : dd;
+1fa3 : 20;
+1fa4 : 60;
+1fa5 : da;
+1fa6 : a2;
+1fa7 : 6c;
+1fa8 : a0;
+1fa9 : df;
+1faa : 20;
+1fab : 98;
+1fac : dd;
+1fad : 20;
+1fae : db;
+1faf : da;
+1fb0 : a5;
+1fb1 : d4;
+1fb2 : f0;
+1fb3 : 0e;
+1fb4 : a2;
+1fb5 : ec;
+1fb6 : a0;
+1fb7 : 05;
+1fb8 : 20;
+1fb9 : 98;
+1fba : dd;
+1fbb : 20;
+1fbc : 66;
+1fbd : da;
+1fbe : c6;
+1fbf : ef;
+1fc0 : 10;
+1fc1 : c6;
+1fc2 : a2;
+1fc3 : ec;
+1fc4 : a0;
+1fc5 : 05;
+1fc6 : 20;
+1fc7 : 89;
+1fc8 : dd;
+1fc9 : a5;
+1fca : f1;
+1fcb : f0;
+1fcc : 23;
+1fcd : 38;
+1fce : e9;
+1fcf : 40;
+1fd0 : 18;
+1fd1 : 6a;
+1fd2 : 18;
+1fd3 : 69;
+1fd4 : 40;
+1fd5 : 29;
+1fd6 : 7f;
+1fd7 : 85;
+1fd8 : e0;
+1fd9 : a5;
+1fda : f1;
+1fdb : 6a;
+1fdc : a9;
+1fdd : 01;
+1fde : 90;
+1fdf : 02;
+1fe0 : a9;
+1fe1 : 10;
+1fe2 : 85;
+1fe3 : e1;
+1fe4 : a2;
+1fe5 : 04;
+1fe6 : a9;
+1fe7 : 00;
+1fe8 : 95;
+1fe9 : e2;
+1fea : ca;
+1feb : 10;
+1fec : fb;
+1fed : 20;
+1fee : db;
+1fef : da;
+1ff0 : 60;
+1ff1 : 00;
+1ff2 : 00;
+1ff3 : 00;
+1ff4 : 00;
+1ff5 : 00;
+1ff6 : 00;
+1ff7 : 00;
+1ff8 : 00;
+1ff9 : 00;
+1ffa : 00;
+1ffb : a0;
+1ffc : 00;
+1ffd : 05;
+1ffe : f0;
+1fff : bf;
+END; 
Index: unmerged/core/mist/complete_address_decoder.vhdl
===================================================================
--- unmerged/core/mist/complete_address_decoder.vhdl	(nonexistent)
+++ unmerged/core/mist/complete_address_decoder.vhdl	(revision 1)
@@ -0,0 +1,52 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY complete_address_decoder IS
+generic (width : natural := 1);
+PORT 
+( 
+	addr_in : in std_logic_vector(width-1 downto 0);	
+	
+	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+);
+END complete_address_decoder;
+
+--ARCHITECTURE vhdl OF complete_address_decoder IS
+--BEGIN
+--	comp_gen:
+--	for i in 0 to ((2**width)-1) generate
+--		addr_decoded(i) <= '1' when i=to_integer(unsigned(addr_in)) else '0';
+--	end generate;
+--end vhdl;
+
+architecture tree of complete_address_decoder is
+	constant STAGE : natural:=width;
+	type std_logic_2d is array (natural range <>,natural range <>) of std_logic;
+	signal p: std_logic_2d(stage downto 0,2**stage-1 downto 0);
+	signal a: std_logic_vector(width-1 downto 0) ;
+begin
+	a<=addr_in;
+	process(a,p)
+	begin
+		p(stage,0) <= '1';
+		
+		for s in stage downto 1 loop
+			for r in 0 to (2**(stage-s)-1) loop
+				p(s-1,2*r) <= (not a(s-1)) and p(s,r);
+				p(s-1,2*r+1) <= a(s-1) and p(s,r);
+			end loop;
+		end loop;
+		
+		for i in  0 to (2**stage-1) loop
+			addr_decoded(i) <= p(0,i);
+		end loop;
+	end process;
+end tree;
\ No newline at end of file
Index: unmerged/core/mist/cpu.vhd
===================================================================
--- unmerged/core/mist/cpu.vhd	(nonexistent)
+++ unmerged/core/mist/cpu.vhd	(revision 1)
@@ -0,0 +1,142 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+ENTITY cpu IS
+PORT 
+(
+	CLK,RESET,ENABLE : IN STD_logic;
+	DI : IN std_logic_vector(7 downto 0);
+	IRQ_n   : in  std_logic;
+	NMI_n   : in  std_logic;
+	MEMORY_READY : in std_logic;
+	THROTTLE : in std_logic;
+	RDY : in std_logic;
+	DO : OUT std_logic_vector(7 downto 0);
+	A : OUT std_logic_vector(15 downto 0);
+	R_W_n : OUT std_logic;
+	CPU_FETCH : out std_logic
+);
+END cpu;
+
+architecture vhdl of cpu is
+component cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end component;
+
+	signal CPU_ENABLE: std_logic; -- Apply Antic HALT and throttle
+		
+	-- Support for Peter's core (NMI patch applied)
+	signal debugOpcode : unsigned(7 downto 0);
+	signal debugPc : unsigned(15 downto 0);
+	signal debugA : unsigned(7 downto 0);
+	signal debugX : unsigned(7 downto 0);
+	signal debugY : unsigned(7 downto 0);
+	signal debugS : unsigned(7 downto 0);
+	signal di_unsigned : unsigned(7 downto 0);
+   signal do_unsigned : unsigned(7 downto 0);
+	signal addr_unsigned : unsigned(15 downto 0);
+	signal CPU_ENABLE_RDY : std_logic; -- it has not RDY line
+	signal WE : std_logic;
+	signal nmi_pending_next : std_logic; -- NMI during RDY
+	signal nmi_pending_reg : std_logic;
+	signal nmi_n_adjusted : std_logic;
+	signal nmi_n_reg : std_logic;
+	signal nmi_edge : std_logic;
+	
+	signal CPU_ENABLE_RESET : std_logic;
+	signal not_rdy : std_logic;	
+	
+BEGIN
+	CPU_ENABLE <= ENABLE and memory_ready and THROTTLE;
+	
+	-- CPU designed by Peter W - as used in Chameleon
+	di_unsigned <= unsigned(di);
+	cpu_6502_peter:cpu_65xx
+		generic map
+		(
+			pipelineOpcode => false,
+			pipelineAluMux => false,
+			pipelineAluOut => false
+		)
+		port map (
+			clk => clk,
+			enable => CPU_ENABLE_RDY,
+			halt => '0',
+			reset=>reset,
+			nmi_n=>nmi_n_adjusted,
+			irq_n=>irq_n,
+			d=>di_unsigned,
+			q=>do_unsigned,
+			addr=>addr_unsigned,
+			WE=>WE,
+			debugOpcode => debugOpcode,
+			debugPc => debugPc,
+			debugA => debugA,
+			debugX => debugX,
+			debugY => debugOpcode,
+			debugS => debugS
+		);
+		CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
+		
+		CPU_ENABLE_RESET <= CPU_ENABLE or reset;
+		not_rdy <= not(rdy);
+		
+		nmi_edge <= not(nmi_n) and nmi_n_reg;
+		nmi_pending_next <= (nmi_edge and not(rdy or we)) or (nmi_pending_reg and not(rdy)) or (nmi_pending_reg and rdy and not(cpu_enable));
+		nmi_n_adjusted <= not(nmi_pending_reg) and nmi_n;
+		
+	-- register
+	process(clk,reset)
+	begin
+		if (RESET = '1') then
+			nmi_pending_reg <= '0';
+			nmi_n_reg <= '1';
+		elsif (clk'event and clk='1') then						
+			nmi_pending_reg <= nmi_pending_next;		
+			nmi_n_reg <= nmi_n;
+		end if;
+	end process;	
+
+	-- outputs
+	r_w_n <= not(we);
+	do <= std_logic_vector(do_unsigned);
+	a <= std_logic_vector(addr_unsigned);
+		
+	CPU_FETCH <= ENABLE and THROTTLE;
+
+END vhdl;
Index: unmerged/core/mist/cpu_65xx_e.vhd
===================================================================
--- unmerged/core/mist/cpu_65xx_e.vhd	(nonexistent)
+++ unmerged/core/mist/cpu_65xx_e.vhd	(revision 1)
@@ -0,0 +1,52 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- All Rights Reserved.
+--
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Interface to 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu_65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		halt : in std_logic := '0';
+		reset : in std_logic;
+		nmi_n : in std_logic := '1';
+		irq_n : in std_logic := '1';
+		so_n : in std_logic := '1';
+
+		d : in unsigned(7 downto 0);
+		q : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0);
+		debug_flags : out unsigned(7 downto 0)
+	);
+end entity;
Index: unmerged/core/mist/data_io.v~
===================================================================
--- unmerged/core/mist/data_io.v~	(nonexistent)
+++ unmerged/core/mist/data_io.v~	(revision 1)
@@ -0,0 +1,91 @@
+module user_io(
+	   input      SPI_CLK,
+	   input      SPI_SS_IO,
+	   output     reg SPI_MISO,
+	   input      SPI_MOSI,
+	   input [7:0] CORE_TYPE,
+		output [5:0] JOY0,
+		output [5:0] JOY1,
+		output [127:0] KEYBOARD,		
+		output [1:0] BUTTONS,
+		output [1:0] SWITCHES
+	   );
+
+   reg [6:0]         sbuf;
+   reg [7:0]         cmd;
+   reg [7:0] 	      cnt;
+   reg [5:0]         joystick0;
+   reg [5:0]         joystick1;
+	reg [119:0]       keyboard;
+	reg [127:0]       keyboard_out;	
+   reg [3:0] 	      but_sw;
+
+	assign JOY0 = joystick0;
+	assign JOY1 = joystick1;
+	assign KEYBOARD = keyboard_out;
+	assign BUTTONS = but_sw[1:0];
+	assign SWITCHES = but_sw[3:2];
+   
+   always@(negedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+		   SPI_MISO <= 1'bZ;
+		end else begin
+	      if(cnt < 8) begin
+			  SPI_MISO <= CORE_TYPE[7-cnt];
+			end else begin
+		     SPI_MISO <= 1'bZ;
+			end
+	   end
+	end
+		
+   always@(posedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+        cnt <= 0;
+		end else begin
+			sbuf[6:1] <= sbuf[5:0];
+			sbuf[0] <= SPI_MOSI;
+
+			cnt <= cnt + 1;
+
+	      if(cnt == 7) begin
+			   cmd[7:1] <= sbuf; 
+				cmd[0] <= SPI_MOSI;
+		   end	
+
+	      if(cnt == 15) begin
+			   if(cmd == 1) begin
+					 but_sw[3:1] <= sbuf[2:0]; 
+					 but_sw[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 2) begin
+					 joystick0[5:1] <= sbuf[4:0]; 
+					 joystick0[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 3) begin
+					 joystick1[5:1] <= sbuf[4:0]; 
+					 joystick1[0] <= SPI_MOSI; 
+				end			
+			end	
+			
+			// 15,23,31,39,47,55,63,71
+			if (cnt[2:0]==7) begin
+			   if(cmd == 5) begin
+					if (!cnt[7]) begin
+					 keyboard[111:0] <= keyboard[119:8];
+					 keyboard[119:113] <= sbuf[6:0]; 
+					 keyboard[112] <= SPI_MOSI; 
+					end
+					if (cnt[7]) begin
+					 keyboard_out[119:0] <= keyboard[119:0];
+					 keyboard_out[127:121] <= sbuf[6:0]; 
+					 keyboard_out[120] <= SPI_MOSI; 					
+					end
+				end
+			end
+		end
+   end		
+//   always@(posedge clk2) begin
+//      LED <= ~LED;
+//   end
+   
+endmodule
Index: unmerged/core/mist/generic_ram_infer.vhdl
===================================================================
--- unmerged/core/mist/generic_ram_infer.vhdl	(nonexistent)
+++ unmerged/core/mist/generic_ram_infer.vhdl	(revision 1)
@@ -0,0 +1,42 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+use ieee.numeric_std.all;
+
+ENTITY generic_ram_infer IS
+	generic
+	(
+		ADDRESS_WIDTH : natural := 9;
+		SPACE : natural := 512;
+		DATA_WIDTH : natural := 8
+	);
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+      address:  IN   std_logic_vector(address_width-1 downto 0);
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+   );
+END generic_ram_infer;
+
+ARCHITECTURE rtl OF generic_ram_infer IS
+   TYPE mem IS ARRAY(0 TO space-1) OF std_logic_vector(data_width-1 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(to_integer(unsigned(address))) <= data;
+         END IF;
+         q <= ram_block(to_integer(unsigned(address)));
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: unmerged/core/mist/gtia_palette.vhdl
===================================================================
--- unmerged/core/mist/gtia_palette.vhdl	(nonexistent)
+++ unmerged/core/mist/gtia_palette.vhdl	(revision 1)
@@ -0,0 +1,2092 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_palette IS
+PORT 
+( 
+	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+);
+END gtia_palette;
+
+ARCHITECTURE altirra OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+				when X"00" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"01" =>
+					R_next <= X"11";
+					G_next <= X"11";
+					B_next <= X"11";
+				when X"02" =>
+					R_next <= X"22";
+					G_next <= X"22";
+					B_next <= X"22";
+				when X"03" =>
+					R_next <= X"33";
+					G_next <= X"33";
+					B_next <= X"33";
+				when X"04" =>
+					R_next <= X"44";
+					G_next <= X"44";
+					B_next <= X"44";
+				when X"05" =>
+					R_next <= X"55";
+					G_next <= X"55";
+					B_next <= X"55";
+				when X"06" =>
+					R_next <= X"66";
+					G_next <= X"66";
+					B_next <= X"66";
+				when X"07" =>
+					R_next <= X"77";
+					G_next <= X"77";
+					B_next <= X"77";
+				when X"08" =>
+					R_next <= X"88";
+					G_next <= X"88";
+					B_next <= X"88";
+				when X"09" =>
+					R_next <= X"99";
+					G_next <= X"99";
+					B_next <= X"99";
+				when X"0a" =>
+					R_next <= X"aa";
+					G_next <= X"aa";
+					B_next <= X"aa";
+				when X"0b" =>
+					R_next <= X"bb";
+					G_next <= X"bb";
+					B_next <= X"bb";
+				when X"0c" =>
+					R_next <= X"cc";
+					G_next <= X"cc";
+					B_next <= X"cc";
+				when X"0d" =>
+					R_next <= X"dd";
+					G_next <= X"dd";
+					B_next <= X"dd";
+				when X"0e" =>
+					R_next <= X"ee";
+					G_next <= X"ee";
+					B_next <= X"ee";
+				when X"0f" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"10" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"11" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"12" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"13" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"14" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"15" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"16" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"17" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"18" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"19" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"1a" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"1b" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"1c" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"1d" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"1e" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"1f" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+				when X"20" =>
+					R_next <= X"50";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"21" =>
+					R_next <= X"61";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"22" =>
+					R_next <= X"72";
+					G_next <= X"03";
+					B_next <= X"00";
+				when X"23" =>
+					R_next <= X"83";
+					G_next <= X"14";
+					B_next <= X"03";
+				when X"24" =>
+					R_next <= X"94";
+					G_next <= X"25";
+					B_next <= X"14";
+				when X"25" =>
+					R_next <= X"a5";
+					G_next <= X"36";
+					B_next <= X"25";
+				when X"26" =>
+					R_next <= X"b6";
+					G_next <= X"47";
+					B_next <= X"36";
+				when X"27" =>
+					R_next <= X"c7";
+					G_next <= X"58";
+					B_next <= X"47";
+				when X"28" =>
+					R_next <= X"d8";
+					G_next <= X"69";
+					B_next <= X"58";
+				when X"29" =>
+					R_next <= X"e9";
+					G_next <= X"7a";
+					B_next <= X"69";
+				when X"2a" =>
+					R_next <= X"fa";
+					G_next <= X"8b";
+					B_next <= X"7a";
+				when X"2b" =>
+					R_next <= X"ff";
+					G_next <= X"9c";
+					B_next <= X"8b";
+				when X"2c" =>
+					R_next <= X"ff";
+					G_next <= X"ad";
+					B_next <= X"9c";
+				when X"2d" =>
+					R_next <= X"ff";
+					G_next <= X"be";
+					B_next <= X"ad";
+				when X"2e" =>
+					R_next <= X"ff";
+					G_next <= X"cf";
+					B_next <= X"be";
+				when X"2f" =>
+					R_next <= X"ff";
+					G_next <= X"e0";
+					B_next <= X"cf";
+				when X"30" =>
+					R_next <= X"54";
+					G_next <= X"00";
+					B_next <= X"03";
+				when X"31" =>
+					R_next <= X"65";
+					G_next <= X"00";
+					B_next <= X"14";
+				when X"32" =>
+					R_next <= X"76";
+					G_next <= X"00";
+					B_next <= X"25";
+				when X"33" =>
+					R_next <= X"87";
+					G_next <= X"08";
+					B_next <= X"36";
+				when X"34" =>
+					R_next <= X"98";
+					G_next <= X"19";
+					B_next <= X"47";
+				when X"35" =>
+					R_next <= X"a9";
+					G_next <= X"2a";
+					B_next <= X"58";
+				when X"36" =>
+					R_next <= X"ba";
+					G_next <= X"3b";
+					B_next <= X"69";
+				when X"37" =>
+					R_next <= X"cb";
+					G_next <= X"4c";
+					B_next <= X"7a";
+				when X"38" =>
+					R_next <= X"dc";
+					G_next <= X"5d";
+					B_next <= X"8b";
+				when X"39" =>
+					R_next <= X"ed";
+					G_next <= X"6e";
+					B_next <= X"9c";
+				when X"3a" =>
+					R_next <= X"fe";
+					G_next <= X"7f";
+					B_next <= X"ad";
+				when X"3b" =>
+					R_next <= X"ff";
+					G_next <= X"90";
+					B_next <= X"be";
+				when X"3c" =>
+					R_next <= X"ff";
+					G_next <= X"a1";
+					B_next <= X"cf";
+				when X"3d" =>
+					R_next <= X"ff";
+					G_next <= X"b2";
+					B_next <= X"e0";
+				when X"3e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"f1";
+				when X"3f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"40" =>
+					R_next <= X"4f";
+					G_next <= X"00";
+					B_next <= X"35";
+				when X"41" =>
+					R_next <= X"60";
+					G_next <= X"00";
+					B_next <= X"46";
+				when X"42" =>
+					R_next <= X"71";
+					G_next <= X"00";
+					B_next <= X"57";
+				when X"43" =>
+					R_next <= X"82";
+					G_next <= X"01";
+					B_next <= X"68";
+				when X"44" =>
+					R_next <= X"93";
+					G_next <= X"12";
+					B_next <= X"79";
+				when X"45" =>
+					R_next <= X"a4";
+					G_next <= X"23";
+					B_next <= X"8a";
+				when X"46" =>
+					R_next <= X"b5";
+					G_next <= X"34";
+					B_next <= X"9b";
+				when X"47" =>
+					R_next <= X"c6";
+					G_next <= X"45";
+					B_next <= X"ac";
+				when X"48" =>
+					R_next <= X"d7";
+					G_next <= X"56";
+					B_next <= X"bd";
+				when X"49" =>
+					R_next <= X"e8";
+					G_next <= X"67";
+					B_next <= X"ce";
+				when X"4a" =>
+					R_next <= X"f9";
+					G_next <= X"78";
+					B_next <= X"df";
+				when X"4b" =>
+					R_next <= X"ff";
+					G_next <= X"89";
+					B_next <= X"f0";
+				when X"4c" =>
+					R_next <= X"ff";
+					G_next <= X"9a";
+					B_next <= X"ff";
+				when X"4d" =>
+					R_next <= X"ff";
+					G_next <= X"ab";
+					B_next <= X"ff";
+				when X"4e" =>
+					R_next <= X"ff";
+					G_next <= X"bc";
+					B_next <= X"ff";
+				when X"4f" =>
+					R_next <= X"ff";
+					G_next <= X"cd";
+					B_next <= X"ff";
+				when X"50" =>
+					R_next <= X"3d";
+					G_next <= X"00";
+					B_next <= X"68";
+				when X"51" =>
+					R_next <= X"4e";
+					G_next <= X"00";
+					B_next <= X"79";
+				when X"52" =>
+					R_next <= X"5f";
+					G_next <= X"00";
+					B_next <= X"8a";
+				when X"53" =>
+					R_next <= X"70";
+					G_next <= X"00";
+					B_next <= X"9b";
+				when X"54" =>
+					R_next <= X"81";
+					G_next <= X"11";
+					B_next <= X"ac";
+				when X"55" =>
+					R_next <= X"92";
+					G_next <= X"22";
+					B_next <= X"bd";
+				when X"56" =>
+					R_next <= X"a3";
+					G_next <= X"33";
+					B_next <= X"ce";
+				when X"57" =>
+					R_next <= X"b4";
+					G_next <= X"44";
+					B_next <= X"df";
+				when X"58" =>
+					R_next <= X"c5";
+					G_next <= X"55";
+					B_next <= X"f0";
+				when X"59" =>
+					R_next <= X"d6";
+					G_next <= X"66";
+					B_next <= X"ff";
+				when X"5a" =>
+					R_next <= X"e7";
+					G_next <= X"77";
+					B_next <= X"ff";
+				when X"5b" =>
+					R_next <= X"f8";
+					G_next <= X"88";
+					B_next <= X"ff";
+				when X"5c" =>
+					R_next <= X"ff";
+					G_next <= X"99";
+					B_next <= X"ff";
+				when X"5d" =>
+					R_next <= X"ff";
+					G_next <= X"aa";
+					B_next <= X"ff";
+				when X"5e" =>
+					R_next <= X"ff";
+					G_next <= X"bb";
+					B_next <= X"ff";
+				when X"5f" =>
+					R_next <= X"ff";
+					G_next <= X"cc";
+					B_next <= X"ff";
+				when X"60" =>
+					R_next <= X"20";
+					G_next <= X"00";
+					B_next <= X"8b";
+				when X"61" =>
+					R_next <= X"31";
+					G_next <= X"00";
+					B_next <= X"9c";
+				when X"62" =>
+					R_next <= X"42";
+					G_next <= X"00";
+					B_next <= X"ad";
+				when X"63" =>
+					R_next <= X"53";
+					G_next <= X"08";
+					B_next <= X"be";
+				when X"64" =>
+					R_next <= X"64";
+					G_next <= X"19";
+					B_next <= X"cf";
+				when X"65" =>
+					R_next <= X"75";
+					G_next <= X"2a";
+					B_next <= X"e0";
+				when X"66" =>
+					R_next <= X"86";
+					G_next <= X"3b";
+					B_next <= X"f1";
+				when X"67" =>
+					R_next <= X"97";
+					G_next <= X"4c";
+					B_next <= X"ff";
+				when X"68" =>
+					R_next <= X"a8";
+					G_next <= X"5d";
+					B_next <= X"ff";
+				when X"69" =>
+					R_next <= X"b9";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"6a" =>
+					R_next <= X"ca";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"6b" =>
+					R_next <= X"db";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"6c" =>
+					R_next <= X"ec";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"6d" =>
+					R_next <= X"fd";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"6e" =>
+					R_next <= X"ff";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"6f" =>
+					R_next <= X"ff";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"70" =>
+					R_next <= X"00";
+					G_next <= X"00";
+					B_next <= X"89";
+				when X"71" =>
+					R_next <= X"00";
+					G_next <= X"08";
+					B_next <= X"9a";
+				when X"72" =>
+					R_next <= X"00";
+					G_next <= X"19";
+					B_next <= X"ab";
+				when X"73" =>
+					R_next <= X"10";
+					G_next <= X"2a";
+					B_next <= X"bc";
+				when X"74" =>
+					R_next <= X"21";
+					G_next <= X"3b";
+					B_next <= X"cd";
+				when X"75" =>
+					R_next <= X"32";
+					G_next <= X"4c";
+					B_next <= X"de";
+				when X"76" =>
+					R_next <= X"43";
+					G_next <= X"5d";
+					B_next <= X"ef";
+				when X"77" =>
+					R_next <= X"54";
+					G_next <= X"6e";
+					B_next <= X"ff";
+				when X"78" =>
+					R_next <= X"65";
+					G_next <= X"7f";
+					B_next <= X"ff";
+				when X"79" =>
+					R_next <= X"76";
+					G_next <= X"90";
+					B_next <= X"ff";
+				when X"7a" =>
+					R_next <= X"87";
+					G_next <= X"a1";
+					B_next <= X"ff";
+				when X"7b" =>
+					R_next <= X"98";
+					G_next <= X"b2";
+					B_next <= X"ff";
+				when X"7c" =>
+					R_next <= X"a9";
+					G_next <= X"c3";
+					B_next <= X"ff";
+				when X"7d" =>
+					R_next <= X"ba";
+					G_next <= X"d4";
+					B_next <= X"ff";
+				when X"7e" =>
+					R_next <= X"cb";
+					G_next <= X"e5";
+					B_next <= X"ff";
+				when X"7f" =>
+					R_next <= X"dc";
+					G_next <= X"f6";
+					B_next <= X"ff";
+				when X"80" =>
+					R_next <= X"00";
+					G_next <= X"0c";
+					B_next <= X"65";
+				when X"81" =>
+					R_next <= X"00";
+					G_next <= X"1d";
+					B_next <= X"76";
+				when X"82" =>
+					R_next <= X"00";
+					G_next <= X"2e";
+					B_next <= X"87";
+				when X"83" =>
+					R_next <= X"00";
+					G_next <= X"3f";
+					B_next <= X"98";
+				when X"84" =>
+					R_next <= X"05";
+					G_next <= X"50";
+					B_next <= X"a9";
+				when X"85" =>
+					R_next <= X"16";
+					G_next <= X"61";
+					B_next <= X"ba";
+				when X"86" =>
+					R_next <= X"27";
+					G_next <= X"72";
+					B_next <= X"cb";
+				when X"87" =>
+					R_next <= X"38";
+					G_next <= X"83";
+					B_next <= X"dc";
+				when X"88" =>
+					R_next <= X"49";
+					G_next <= X"94";
+					B_next <= X"ed";
+				when X"89" =>
+					R_next <= X"5a";
+					G_next <= X"a5";
+					B_next <= X"fe";
+				when X"8a" =>
+					R_next <= X"6b";
+					G_next <= X"b6";
+					B_next <= X"ff";
+				when X"8b" =>
+					R_next <= X"7c";
+					G_next <= X"c7";
+					B_next <= X"ff";
+				when X"8c" =>
+					R_next <= X"8d";
+					G_next <= X"d8";
+					B_next <= X"ff";
+				when X"8d" =>
+					R_next <= X"9e";
+					G_next <= X"e9";
+					B_next <= X"ff";
+				when X"8e" =>
+					R_next <= X"af";
+					G_next <= X"fa";
+					B_next <= X"ff";
+				when X"8f" =>
+					R_next <= X"c0";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"90" =>
+					R_next <= X"00";
+					G_next <= X"1f";
+					B_next <= X"30";
+				when X"91" =>
+					R_next <= X"00";
+					G_next <= X"30";
+					B_next <= X"41";
+				when X"92" =>
+					R_next <= X"00";
+					G_next <= X"41";
+					B_next <= X"52";
+				when X"93" =>
+					R_next <= X"00";
+					G_next <= X"52";
+					B_next <= X"63";
+				when X"94" =>
+					R_next <= X"00";
+					G_next <= X"63";
+					B_next <= X"74";
+				when X"95" =>
+					R_next <= X"05";
+					G_next <= X"74";
+					B_next <= X"85";
+				when X"96" =>
+					R_next <= X"16";
+					G_next <= X"85";
+					B_next <= X"96";
+				when X"97" =>
+					R_next <= X"27";
+					G_next <= X"96";
+					B_next <= X"a7";
+				when X"98" =>
+					R_next <= X"38";
+					G_next <= X"a7";
+					B_next <= X"b8";
+				when X"99" =>
+					R_next <= X"49";
+					G_next <= X"b8";
+					B_next <= X"c9";
+				when X"9a" =>
+					R_next <= X"5a";
+					G_next <= X"c9";
+					B_next <= X"da";
+				when X"9b" =>
+					R_next <= X"6b";
+					G_next <= X"da";
+					B_next <= X"eb";
+				when X"9c" =>
+					R_next <= X"7c";
+					G_next <= X"eb";
+					B_next <= X"fc";
+				when X"9d" =>
+					R_next <= X"8d";
+					G_next <= X"fc";
+					B_next <= X"ff";
+				when X"9e" =>
+					R_next <= X"9e";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"9f" =>
+					R_next <= X"af";
+					G_next <= X"ff";
+					B_next <= X"ff";
+				when X"a0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"a1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"0e";
+				when X"a2" =>
+					R_next <= X"00";
+					G_next <= X"4d";
+					B_next <= X"1f";
+				when X"a3" =>
+					R_next <= X"00";
+					G_next <= X"5e";
+					B_next <= X"30";
+				when X"a4" =>
+					R_next <= X"00";
+					G_next <= X"6f";
+					B_next <= X"41";
+				when X"a5" =>
+					R_next <= X"01";
+					G_next <= X"80";
+					B_next <= X"52";
+				when X"a6" =>
+					R_next <= X"12";
+					G_next <= X"91";
+					B_next <= X"63";
+				when X"a7" =>
+					R_next <= X"23";
+					G_next <= X"a2";
+					B_next <= X"74";
+				when X"a8" =>
+					R_next <= X"34";
+					G_next <= X"b3";
+					B_next <= X"85";
+				when X"a9" =>
+					R_next <= X"45";
+					G_next <= X"c4";
+					B_next <= X"96";
+				when X"aa" =>
+					R_next <= X"56";
+					G_next <= X"d5";
+					B_next <= X"a7";
+				when X"ab" =>
+					R_next <= X"67";
+					G_next <= X"e6";
+					B_next <= X"b8";
+				when X"ac" =>
+					R_next <= X"78";
+					G_next <= X"f7";
+					B_next <= X"c9";
+				when X"ad" =>
+					R_next <= X"89";
+					G_next <= X"ff";
+					B_next <= X"da";
+				when X"ae" =>
+					R_next <= X"9a";
+					G_next <= X"ff";
+					B_next <= X"eb";
+				when X"af" =>
+					R_next <= X"ab";
+					G_next <= X"ff";
+					B_next <= X"fc";
+				when X"b0" =>
+					R_next <= X"00";
+					G_next <= X"33";
+					B_next <= X"00";
+				when X"b1" =>
+					R_next <= X"00";
+					G_next <= X"44";
+					B_next <= X"00";
+				when X"b2" =>
+					R_next <= X"00";
+					G_next <= X"55";
+					B_next <= X"00";
+				when X"b3" =>
+					R_next <= X"00";
+					G_next <= X"66";
+					B_next <= X"00";
+				when X"b4" =>
+					R_next <= X"07";
+					G_next <= X"77";
+					B_next <= X"00";
+				when X"b5" =>
+					R_next <= X"18";
+					G_next <= X"88";
+					B_next <= X"00";
+				when X"b6" =>
+					R_next <= X"29";
+					G_next <= X"99";
+					B_next <= X"00";
+				when X"b7" =>
+					R_next <= X"3a";
+					G_next <= X"aa";
+					B_next <= X"0f";
+				when X"b8" =>
+					R_next <= X"4b";
+					G_next <= X"bb";
+					B_next <= X"20";
+				when X"b9" =>
+					R_next <= X"5c";
+					G_next <= X"cc";
+					B_next <= X"31";
+				when X"ba" =>
+					R_next <= X"6d";
+					G_next <= X"dd";
+					B_next <= X"42";
+				when X"bb" =>
+					R_next <= X"7e";
+					G_next <= X"ee";
+					B_next <= X"53";
+				when X"bc" =>
+					R_next <= X"8f";
+					G_next <= X"ff";
+					B_next <= X"64";
+				when X"bd" =>
+					R_next <= X"a0";
+					G_next <= X"ff";
+					B_next <= X"75";
+				when X"be" =>
+					R_next <= X"b1";
+					G_next <= X"ff";
+					B_next <= X"86";
+				when X"bf" =>
+					R_next <= X"c2";
+					G_next <= X"ff";
+					B_next <= X"97";
+				when X"c0" =>
+					R_next <= X"00";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"c1" =>
+					R_next <= X"00";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"c2" =>
+					R_next <= X"02";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"c3" =>
+					R_next <= X"13";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"c4" =>
+					R_next <= X"24";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"c5" =>
+					R_next <= X"35";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"c6" =>
+					R_next <= X"46";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"c7" =>
+					R_next <= X"57";
+					G_next <= X"a2";
+					B_next <= X"00";
+				when X"c8" =>
+					R_next <= X"68";
+					G_next <= X"b3";
+					B_next <= X"00";
+				when X"c9" =>
+					R_next <= X"79";
+					G_next <= X"c4";
+					B_next <= X"0e";
+				when X"ca" =>
+					R_next <= X"8a";
+					G_next <= X"d5";
+					B_next <= X"1f";
+				when X"cb" =>
+					R_next <= X"9b";
+					G_next <= X"e6";
+					B_next <= X"30";
+				when X"cc" =>
+					R_next <= X"ac";
+					G_next <= X"f7";
+					B_next <= X"41";
+				when X"cd" =>
+					R_next <= X"bd";
+					G_next <= X"ff";
+					B_next <= X"52";
+				when X"ce" =>
+					R_next <= X"ce";
+					G_next <= X"ff";
+					B_next <= X"63";
+				when X"cf" =>
+					R_next <= X"df";
+					G_next <= X"ff";
+					B_next <= X"74";
+				when X"d0" =>
+					R_next <= X"01";
+					G_next <= X"1c";
+					B_next <= X"00";
+				when X"d1" =>
+					R_next <= X"12";
+					G_next <= X"2d";
+					B_next <= X"00";
+				when X"d2" =>
+					R_next <= X"23";
+					G_next <= X"3e";
+					B_next <= X"00";
+				when X"d3" =>
+					R_next <= X"34";
+					G_next <= X"4f";
+					B_next <= X"00";
+				when X"d4" =>
+					R_next <= X"45";
+					G_next <= X"60";
+					B_next <= X"00";
+				when X"d5" =>
+					R_next <= X"56";
+					G_next <= X"71";
+					B_next <= X"00";
+				when X"d6" =>
+					R_next <= X"67";
+					G_next <= X"82";
+					B_next <= X"00";
+				when X"d7" =>
+					R_next <= X"78";
+					G_next <= X"93";
+					B_next <= X"00";
+				when X"d8" =>
+					R_next <= X"89";
+					G_next <= X"a4";
+					B_next <= X"00";
+				when X"d9" =>
+					R_next <= X"9a";
+					G_next <= X"b5";
+					B_next <= X"03";
+				when X"da" =>
+					R_next <= X"ab";
+					G_next <= X"c6";
+					B_next <= X"14";
+				when X"db" =>
+					R_next <= X"bc";
+					G_next <= X"d7";
+					B_next <= X"25";
+				when X"dc" =>
+					R_next <= X"cd";
+					G_next <= X"e8";
+					B_next <= X"36";
+				when X"dd" =>
+					R_next <= X"de";
+					G_next <= X"f9";
+					B_next <= X"47";
+				when X"de" =>
+					R_next <= X"ef";
+					G_next <= X"ff";
+					B_next <= X"58";
+				when X"df" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"69";
+				when X"e0" =>
+					R_next <= X"23";
+					G_next <= X"09";
+					B_next <= X"00";
+				when X"e1" =>
+					R_next <= X"34";
+					G_next <= X"1a";
+					B_next <= X"00";
+				when X"e2" =>
+					R_next <= X"45";
+					G_next <= X"2b";
+					B_next <= X"00";
+				when X"e3" =>
+					R_next <= X"56";
+					G_next <= X"3c";
+					B_next <= X"00";
+				when X"e4" =>
+					R_next <= X"67";
+					G_next <= X"4d";
+					B_next <= X"00";
+				when X"e5" =>
+					R_next <= X"78";
+					G_next <= X"5e";
+					B_next <= X"00";
+				when X"e6" =>
+					R_next <= X"89";
+					G_next <= X"6f";
+					B_next <= X"00";
+				when X"e7" =>
+					R_next <= X"9a";
+					G_next <= X"80";
+					B_next <= X"00";
+				when X"e8" =>
+					R_next <= X"ab";
+					G_next <= X"91";
+					B_next <= X"00";
+				when X"e9" =>
+					R_next <= X"bc";
+					G_next <= X"a2";
+					B_next <= X"10";
+				when X"ea" =>
+					R_next <= X"cd";
+					G_next <= X"b3";
+					B_next <= X"21";
+				when X"eb" =>
+					R_next <= X"de";
+					G_next <= X"c4";
+					B_next <= X"32";
+				when X"ec" =>
+					R_next <= X"ef";
+					G_next <= X"d5";
+					B_next <= X"43";
+				when X"ed" =>
+					R_next <= X"ff";
+					G_next <= X"e6";
+					B_next <= X"54";
+				when X"ee" =>
+					R_next <= X"ff";
+					G_next <= X"f7";
+					B_next <= X"65";
+				when X"ef" =>
+					R_next <= X"ff";
+					G_next <= X"ff";
+					B_next <= X"76";
+				when X"f0" =>
+					R_next <= X"3f";
+					G_next <= X"00";
+					B_next <= X"00";
+				when X"f1" =>
+					R_next <= X"50";
+					G_next <= X"05";
+					B_next <= X"00";
+				when X"f2" =>
+					R_next <= X"61";
+					G_next <= X"16";
+					B_next <= X"00";
+				when X"f3" =>
+					R_next <= X"72";
+					G_next <= X"27";
+					B_next <= X"00";
+				when X"f4" =>
+					R_next <= X"83";
+					G_next <= X"38";
+					B_next <= X"00";
+				when X"f5" =>
+					R_next <= X"94";
+					G_next <= X"49";
+					B_next <= X"00";
+				when X"f6" =>
+					R_next <= X"a5";
+					G_next <= X"5a";
+					B_next <= X"01";
+				when X"f7" =>
+					R_next <= X"b6";
+					G_next <= X"6b";
+					B_next <= X"12";
+				when X"f8" =>
+					R_next <= X"c7";
+					G_next <= X"7c";
+					B_next <= X"23";
+				when X"f9" =>
+					R_next <= X"d8";
+					G_next <= X"8d";
+					B_next <= X"34";
+				when X"fa" =>
+					R_next <= X"e9";
+					G_next <= X"9e";
+					B_next <= X"45";
+				when X"fb" =>
+					R_next <= X"fa";
+					G_next <= X"af";
+					B_next <= X"56";
+				when X"fc" =>
+					R_next <= X"ff";
+					G_next <= X"c0";
+					B_next <= X"67";
+				when X"fd" =>
+					R_next <= X"ff";
+					G_next <= X"d1";
+					B_next <= X"78";
+				when X"fe" =>
+					R_next <= X"ff";
+					G_next <= X"e2";
+					B_next <= X"89";
+				when X"ff" =>
+					R_next <= X"ff";
+					G_next <= X"f3";
+					B_next <= X"9a";
+			end case;
+			
+		end process;
+		
+end altirra;
+
+
+ARCHITECTURE laoo OF gtia_palette IS
+begin
+		process(atari_colour)
+		begin
+			case atari_colour is
+					when X"00" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"01" =>
+						R_next <= X"0e";
+						G_next <= X"0d";
+						B_next <= X"0e";
+					when X"02" =>
+						R_next <= X"1d";
+						G_next <= X"1d";
+						B_next <= X"1d";
+					when X"03" =>
+						R_next <= X"2e";
+						G_next <= X"2d";
+						B_next <= X"2e";
+					when X"04" =>
+						R_next <= X"3e";
+						G_next <= X"3d";
+						B_next <= X"3e";
+					when X"05" =>
+						R_next <= X"4f";
+						G_next <= X"4e";
+						B_next <= X"4f";
+					when X"06" =>
+						R_next <= X"5f";
+						G_next <= X"5e";
+						B_next <= X"5f";
+					when X"07" =>
+						R_next <= X"70";
+						G_next <= X"6f";
+						B_next <= X"6f";
+					when X"08" =>
+						R_next <= X"7a";
+						G_next <= X"7a";
+						B_next <= X"79";
+					when X"09" =>
+						R_next <= X"8b";
+						G_next <= X"8a";
+						B_next <= X"8b";
+					when X"0a" =>
+						R_next <= X"9c";
+						G_next <= X"9b";
+						B_next <= X"9b";
+					when X"0b" =>
+						R_next <= X"ad";
+						G_next <= X"ac";
+						B_next <= X"ac";
+					when X"0c" =>
+						R_next <= X"bc";
+						G_next <= X"bb";
+						B_next <= X"bb";
+					when X"0d" =>
+						R_next <= X"cd";
+						G_next <= X"cc";
+						B_next <= X"cd";
+					when X"0e" =>
+						R_next <= X"dc";
+						G_next <= X"db";
+						B_next <= X"dc";
+					when X"0f" =>
+						R_next <= X"ec";
+						G_next <= X"ec";
+						B_next <= X"ec";
+					when X"10" =>
+						R_next <= X"35";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"11" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"12" =>
+						R_next <= X"4f";
+						G_next <= X"14";
+						B_next <= X"00";
+					when X"13" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"14" =>
+						R_next <= X"6e";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"15" =>
+						R_next <= X"7f";
+						G_next <= X"45";
+						B_next <= X"03";
+					when X"16" =>
+						R_next <= X"8e";
+						G_next <= X"55";
+						B_next <= X"13";
+					when X"17" =>
+						R_next <= X"9f";
+						G_next <= X"66";
+						B_next <= X"23";
+					when X"18" =>
+						R_next <= X"a9";
+						G_next <= X"71";
+						B_next <= X"2d";
+					when X"19" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"1a" =>
+						R_next <= X"ca";
+						G_next <= X"92";
+						B_next <= X"50";
+					when X"1b" =>
+						R_next <= X"db";
+						G_next <= X"a3";
+						B_next <= X"61";
+					when X"1c" =>
+						R_next <= X"ea";
+						G_next <= X"b2";
+						B_next <= X"70";
+					when X"1d" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"1e" =>
+						R_next <= X"fe";
+						G_next <= X"d2";
+						B_next <= X"91";
+					when X"1f" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+					when X"20" =>
+						R_next <= X"3f";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"21" =>
+						R_next <= X"4b";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"22" =>
+						R_next <= X"59";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"23" =>
+						R_next <= X"69";
+						G_next <= X"19";
+						B_next <= X"03";
+					when X"24" =>
+						R_next <= X"78";
+						G_next <= X"29";
+						B_next <= X"12";
+					when X"25" =>
+						R_next <= X"88";
+						G_next <= X"3a";
+						B_next <= X"23";
+					when X"26" =>
+						R_next <= X"98";
+						G_next <= X"4a";
+						B_next <= X"34";
+					when X"27" =>
+						R_next <= X"a9";
+						G_next <= X"5b";
+						B_next <= X"45";
+					when X"28" =>
+						R_next <= X"b3";
+						G_next <= X"65";
+						B_next <= X"4f";
+					when X"29" =>
+						R_next <= X"c4";
+						G_next <= X"76";
+						B_next <= X"61";
+					when X"2a" =>
+						R_next <= X"d4";
+						G_next <= X"87";
+						B_next <= X"72";
+					when X"2b" =>
+						R_next <= X"e5";
+						G_next <= X"98";
+						B_next <= X"83";
+					when X"2c" =>
+						R_next <= X"f4";
+						G_next <= X"a7";
+						B_next <= X"92";
+					when X"2d" =>
+						R_next <= X"fd";
+						G_next <= X"b8";
+						B_next <= X"a3";
+					when X"2e" =>
+						R_next <= X"ff";
+						G_next <= X"c7";
+						B_next <= X"b3";
+					when X"2f" =>
+						R_next <= X"ff";
+						G_next <= X"d7";
+						B_next <= X"c2";
+					when X"30" =>
+						R_next <= X"3d";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"31" =>
+						R_next <= X"49";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"32" =>
+						R_next <= X"57";
+						G_next <= X"05";
+						B_next <= X"0b";
+					when X"33" =>
+						R_next <= X"68";
+						G_next <= X"15";
+						B_next <= X"1b";
+					when X"34" =>
+						R_next <= X"77";
+						G_next <= X"25";
+						B_next <= X"2a";
+					when X"35" =>
+						R_next <= X"88";
+						G_next <= X"36";
+						B_next <= X"3c";
+					when X"36" =>
+						R_next <= X"98";
+						G_next <= X"46";
+						B_next <= X"4c";
+					when X"37" =>
+						R_next <= X"a8";
+						G_next <= X"57";
+						B_next <= X"5d";
+					when X"38" =>
+						R_next <= X"b2";
+						G_next <= X"61";
+						B_next <= X"67";
+					when X"39" =>
+						R_next <= X"c3";
+						G_next <= X"72";
+						B_next <= X"79";
+					when X"3a" =>
+						R_next <= X"d3";
+						G_next <= X"83";
+						B_next <= X"89";
+					when X"3b" =>
+						R_next <= X"e4";
+						G_next <= X"94";
+						B_next <= X"9a";
+					when X"3c" =>
+						R_next <= X"f3";
+						G_next <= X"a3";
+						B_next <= X"a9";
+					when X"3d" =>
+						R_next <= X"fd";
+						G_next <= X"b4";
+						B_next <= X"ba";
+					when X"3e" =>
+						R_next <= X"ff";
+						G_next <= X"c4";
+						B_next <= X"ca";
+					when X"3f" =>
+						R_next <= X"ff";
+						G_next <= X"d4";
+						B_next <= X"d9";
+					when X"40" =>
+						R_next <= X"38";
+						G_next <= X"00";
+						B_next <= X"27";
+					when X"41" =>
+						R_next <= X"42";
+						G_next <= X"00";
+						B_next <= X"32";
+					when X"42" =>
+						R_next <= X"51";
+						G_next <= X"01";
+						B_next <= X"40";
+					when X"43" =>
+						R_next <= X"61";
+						G_next <= X"0e";
+						B_next <= X"50";
+					when X"44" =>
+						R_next <= X"70";
+						G_next <= X"1e";
+						B_next <= X"5f";
+					when X"45" =>
+						R_next <= X"81";
+						G_next <= X"2f";
+						B_next <= X"70";
+					when X"46" =>
+						R_next <= X"90";
+						G_next <= X"3f";
+						B_next <= X"81";
+					when X"47" =>
+						R_next <= X"a0";
+						G_next <= X"51";
+						B_next <= X"90";
+					when X"48" =>
+						R_next <= X"ab";
+						G_next <= X"5b";
+						B_next <= X"9a";
+					when X"49" =>
+						R_next <= X"bc";
+						G_next <= X"6c";
+						B_next <= X"ac";
+					when X"4a" =>
+						R_next <= X"cc";
+						G_next <= X"7c";
+						B_next <= X"bc";
+					when X"4b" =>
+						R_next <= X"dc";
+						G_next <= X"8d";
+						B_next <= X"cd";
+					when X"4c" =>
+						R_next <= X"ec";
+						G_next <= X"9d";
+						B_next <= X"dc";
+					when X"4d" =>
+						R_next <= X"fa";
+						G_next <= X"ae";
+						B_next <= X"ed";
+					when X"4e" =>
+						R_next <= X"fe";
+						G_next <= X"bd";
+						B_next <= X"fa";
+					when X"4f" =>
+						R_next <= X"ff";
+						G_next <= X"cd";
+						B_next <= X"fe";
+					when X"50" =>
+						R_next <= X"2c";
+						G_next <= X"00";
+						B_next <= X"46";
+					when X"51" =>
+						R_next <= X"37";
+						G_next <= X"00";
+						B_next <= X"50";
+					when X"52" =>
+						R_next <= X"46";
+						G_next <= X"01";
+						B_next <= X"5f";
+					when X"53" =>
+						R_next <= X"55";
+						G_next <= X"0e";
+						B_next <= X"6e";
+					when X"54" =>
+						R_next <= X"65";
+						G_next <= X"1e";
+						B_next <= X"7d";
+					when X"55" =>
+						R_next <= X"75";
+						G_next <= X"2f";
+						B_next <= X"8e";
+					when X"56" =>
+						R_next <= X"85";
+						G_next <= X"3f";
+						B_next <= X"9f";
+					when X"57" =>
+						R_next <= X"95";
+						G_next <= X"50";
+						B_next <= X"ae";
+					when X"58" =>
+						R_next <= X"a0";
+						G_next <= X"5b";
+						B_next <= X"b8";
+					when X"59" =>
+						R_next <= X"b1";
+						G_next <= X"6c";
+						B_next <= X"ca";
+					when X"5a" =>
+						R_next <= X"c1";
+						G_next <= X"7c";
+						B_next <= X"da";
+					when X"5b" =>
+						R_next <= X"d2";
+						G_next <= X"8d";
+						B_next <= X"eb";
+					when X"5c" =>
+						R_next <= X"e1";
+						G_next <= X"9d";
+						B_next <= X"f8";
+					when X"5d" =>
+						R_next <= X"f2";
+						G_next <= X"ae";
+						B_next <= X"fe";
+					when X"5e" =>
+						R_next <= X"fc";
+						G_next <= X"bd";
+						B_next <= X"ff";
+					when X"5f" =>
+						R_next <= X"fe";
+						G_next <= X"cd";
+						B_next <= X"ff";
+					when X"60" =>
+						R_next <= X"19";
+						G_next <= X"00";
+						B_next <= X"5e";
+					when X"61" =>
+						R_next <= X"24";
+						G_next <= X"00";
+						B_next <= X"67";
+					when X"62" =>
+						R_next <= X"34";
+						G_next <= X"03";
+						B_next <= X"76";
+					when X"63" =>
+						R_next <= X"44";
+						G_next <= X"13";
+						B_next <= X"85";
+					when X"64" =>
+						R_next <= X"53";
+						G_next <= X"22";
+						B_next <= X"94";
+					when X"65" =>
+						R_next <= X"64";
+						G_next <= X"33";
+						B_next <= X"a5";
+					when X"66" =>
+						R_next <= X"74";
+						G_next <= X"43";
+						B_next <= X"b5";
+					when X"67" =>
+						R_next <= X"85";
+						G_next <= X"55";
+						B_next <= X"c4";
+					when X"68" =>
+						R_next <= X"8f";
+						G_next <= X"5f";
+						B_next <= X"ce";
+					when X"69" =>
+						R_next <= X"a0";
+						G_next <= X"70";
+						B_next <= X"e0";
+					when X"6a" =>
+						R_next <= X"b0";
+						G_next <= X"81";
+						B_next <= X"f0";
+					when X"6b" =>
+						R_next <= X"c1";
+						G_next <= X"92";
+						B_next <= X"fc";
+					when X"6c" =>
+						R_next <= X"d0";
+						G_next <= X"a1";
+						B_next <= X"fe";
+					when X"6d" =>
+						R_next <= X"e1";
+						G_next <= X"b2";
+						B_next <= X"ff";
+					when X"6e" =>
+						R_next <= X"f0";
+						G_next <= X"c2";
+						B_next <= X"ff";
+					when X"6f" =>
+						R_next <= X"fc";
+						G_next <= X"d2";
+						B_next <= X"ff";
+					when X"70" =>
+						R_next <= X"00";
+						G_next <= X"00";
+						B_next <= X"5c";
+					when X"71" =>
+						R_next <= X"00";
+						G_next <= X"09";
+						B_next <= X"66";
+					when X"72" =>
+						R_next <= X"09";
+						G_next <= X"18";
+						B_next <= X"75";
+					when X"73" =>
+						R_next <= X"1a";
+						G_next <= X"29";
+						B_next <= X"84";
+					when X"74" =>
+						R_next <= X"29";
+						G_next <= X"38";
+						B_next <= X"93";
+					when X"75" =>
+						R_next <= X"3a";
+						G_next <= X"49";
+						B_next <= X"a4";
+					when X"76" =>
+						R_next <= X"4a";
+						G_next <= X"59";
+						B_next <= X"b4";
+					when X"77" =>
+						R_next <= X"5c";
+						G_next <= X"6a";
+						B_next <= X"c3";
+					when X"78" =>
+						R_next <= X"66";
+						G_next <= X"74";
+						B_next <= X"cd";
+					when X"79" =>
+						R_next <= X"77";
+						G_next <= X"85";
+						B_next <= X"df";
+					when X"7a" =>
+						R_next <= X"87";
+						G_next <= X"96";
+						B_next <= X"ef";
+					when X"7b" =>
+						R_next <= X"98";
+						G_next <= X"a7";
+						B_next <= X"fc";
+					when X"7c" =>
+						R_next <= X"a8";
+						G_next <= X"b6";
+						B_next <= X"fe";
+					when X"7d" =>
+						R_next <= X"b9";
+						G_next <= X"c7";
+						B_next <= X"ff";
+					when X"7e" =>
+						R_next <= X"c8";
+						G_next <= X"d6";
+						B_next <= X"ff";
+					when X"7f" =>
+						R_next <= X"d8";
+						G_next <= X"e7";
+						B_next <= X"ff";
+					when X"80" =>
+						R_next <= X"00";
+						G_next <= X"0b";
+						B_next <= X"45";
+					when X"81" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"4f";
+					when X"82" =>
+						R_next <= X"00";
+						G_next <= X"25";
+						B_next <= X"5d";
+					when X"83" =>
+						R_next <= X"09";
+						G_next <= X"36";
+						B_next <= X"6d";
+					when X"84" =>
+						R_next <= X"18";
+						G_next <= X"45";
+						B_next <= X"7c";
+					when X"85" =>
+						R_next <= X"29";
+						G_next <= X"56";
+						B_next <= X"8d";
+					when X"86" =>
+						R_next <= X"39";
+						G_next <= X"66";
+						B_next <= X"9d";
+					when X"87" =>
+						R_next <= X"4b";
+						G_next <= X"77";
+						B_next <= X"ac";
+					when X"88" =>
+						R_next <= X"56";
+						G_next <= X"81";
+						B_next <= X"b6";
+					when X"89" =>
+						R_next <= X"67";
+						G_next <= X"92";
+						B_next <= X"c8";
+					when X"8a" =>
+						R_next <= X"77";
+						G_next <= X"a2";
+						B_next <= X"d9";
+					when X"8b" =>
+						R_next <= X"88";
+						G_next <= X"b3";
+						B_next <= X"e9";
+					when X"8c" =>
+						R_next <= X"98";
+						G_next <= X"c3";
+						B_next <= X"f7";
+					when X"8d" =>
+						R_next <= X"a9";
+						G_next <= X"d3";
+						B_next <= X"fe";
+					when X"8e" =>
+						R_next <= X"b8";
+						G_next <= X"e3";
+						B_next <= X"ff";
+					when X"8f" =>
+						R_next <= X"c8";
+						G_next <= X"f3";
+						B_next <= X"ff";
+					when X"90" =>
+						R_next <= X"00";
+						G_next <= X"16";
+						B_next <= X"25";
+					when X"91" =>
+						R_next <= X"00";
+						G_next <= X"22";
+						B_next <= X"30";
+					when X"92" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"3f";
+					when X"93" =>
+						R_next <= X"01";
+						G_next <= X"42";
+						B_next <= X"4f";
+					when X"94" =>
+						R_next <= X"0c";
+						G_next <= X"51";
+						B_next <= X"5e";
+					when X"95" =>
+						R_next <= X"1e";
+						G_next <= X"62";
+						B_next <= X"6f";
+					when X"96" =>
+						R_next <= X"2e";
+						G_next <= X"72";
+						B_next <= X"80";
+					when X"97" =>
+						R_next <= X"40";
+						G_next <= X"82";
+						B_next <= X"8f";
+					when X"98" =>
+						R_next <= X"4a";
+						G_next <= X"8d";
+						B_next <= X"99";
+					when X"99" =>
+						R_next <= X"5c";
+						G_next <= X"9d";
+						B_next <= X"ab";
+					when X"9a" =>
+						R_next <= X"6c";
+						G_next <= X"ae";
+						B_next <= X"bc";
+					when X"9b" =>
+						R_next <= X"7e";
+						G_next <= X"be";
+						B_next <= X"cc";
+					when X"9c" =>
+						R_next <= X"8d";
+						G_next <= X"ce";
+						B_next <= X"db";
+					when X"9d" =>
+						R_next <= X"9e";
+						G_next <= X"de";
+						B_next <= X"ed";
+					when X"9e" =>
+						R_next <= X"ad";
+						G_next <= X"ee";
+						B_next <= X"fa";
+					when X"9f" =>
+						R_next <= X"bd";
+						G_next <= X"fc";
+						B_next <= X"fe";
+					when X"a0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"a1" =>
+						R_next <= X"00";
+						G_next <= X"2f";
+						B_next <= X"00";
+					when X"a2" =>
+						R_next <= X"00";
+						G_next <= X"3e";
+						B_next <= X"0a";
+					when X"a3" =>
+						R_next <= X"00";
+						G_next <= X"4f";
+						B_next <= X"1a";
+					when X"a4" =>
+						R_next <= X"08";
+						G_next <= X"5e";
+						B_next <= X"29";
+					when X"a5" =>
+						R_next <= X"18";
+						G_next <= X"6f";
+						B_next <= X"3b";
+					when X"a6" =>
+						R_next <= X"28";
+						G_next <= X"7f";
+						B_next <= X"4b";
+					when X"a7" =>
+						R_next <= X"3a";
+						G_next <= X"8f";
+						B_next <= X"5c";
+					when X"a8" =>
+						R_next <= X"44";
+						G_next <= X"9a";
+						B_next <= X"65";
+					when X"a9" =>
+						R_next <= X"55";
+						G_next <= X"ab";
+						B_next <= X"78";
+					when X"aa" =>
+						R_next <= X"65";
+						G_next <= X"bb";
+						B_next <= X"88";
+					when X"ab" =>
+						R_next <= X"77";
+						G_next <= X"cc";
+						B_next <= X"99";
+					when X"ac" =>
+						R_next <= X"86";
+						G_next <= X"db";
+						B_next <= X"a8";
+					when X"ad" =>
+						R_next <= X"97";
+						G_next <= X"ec";
+						B_next <= X"ba";
+					when X"ae" =>
+						R_next <= X"a6";
+						G_next <= X"fa";
+						B_next <= X"c9";
+					when X"af" =>
+						R_next <= X"b7";
+						G_next <= X"fe";
+						B_next <= X"d9";
+					when X"b0" =>
+						R_next <= X"00";
+						G_next <= X"2a";
+						B_next <= X"00";
+					when X"b1" =>
+						R_next <= X"00";
+						G_next <= X"37";
+						B_next <= X"00";
+					when X"b2" =>
+						R_next <= X"00";
+						G_next <= X"46";
+						B_next <= X"00";
+					when X"b3" =>
+						R_next <= X"01";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"b4" =>
+						R_next <= X"0f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"b5" =>
+						R_next <= X"20";
+						G_next <= X"76";
+						B_next <= X"03";
+					when X"b6" =>
+						R_next <= X"31";
+						G_next <= X"85";
+						B_next <= X"13";
+					when X"b7" =>
+						R_next <= X"42";
+						G_next <= X"96";
+						B_next <= X"24";
+					when X"b8" =>
+						R_next <= X"4c";
+						G_next <= X"a1";
+						B_next <= X"2d";
+					when X"b9" =>
+						R_next <= X"5d";
+						G_next <= X"b1";
+						B_next <= X"40";
+					when X"ba" =>
+						R_next <= X"6d";
+						G_next <= X"c1";
+						B_next <= X"51";
+					when X"bb" =>
+						R_next <= X"7f";
+						G_next <= X"d2";
+						B_next <= X"62";
+					when X"bc" =>
+						R_next <= X"8e";
+						G_next <= X"e2";
+						B_next <= X"71";
+					when X"bd" =>
+						R_next <= X"9f";
+						G_next <= X"f2";
+						B_next <= X"82";
+					when X"be" =>
+						R_next <= X"af";
+						G_next <= X"fd";
+						B_next <= X"92";
+					when X"bf" =>
+						R_next <= X"bf";
+						G_next <= X"ff";
+						B_next <= X"a1";
+					when X"c0" =>
+						R_next <= X"00";
+						G_next <= X"24";
+						B_next <= X"00";
+					when X"c1" =>
+						R_next <= X"00";
+						G_next <= X"31";
+						B_next <= X"00";
+					when X"c2" =>
+						R_next <= X"05";
+						G_next <= X"40";
+						B_next <= X"00";
+					when X"c3" =>
+						R_next <= X"16";
+						G_next <= X"50";
+						B_next <= X"00";
+					when X"c4" =>
+						R_next <= X"26";
+						G_next <= X"5f";
+						B_next <= X"00";
+					when X"c5" =>
+						R_next <= X"36";
+						G_next <= X"70";
+						B_next <= X"00";
+					when X"c6" =>
+						R_next <= X"47";
+						G_next <= X"80";
+						B_next <= X"00";
+					when X"c7" =>
+						R_next <= X"58";
+						G_next <= X"90";
+						B_next <= X"08";
+					when X"c8" =>
+						R_next <= X"62";
+						G_next <= X"9b";
+						B_next <= X"12";
+					when X"c9" =>
+						R_next <= X"73";
+						G_next <= X"ac";
+						B_next <= X"24";
+					when X"ca" =>
+						R_next <= X"84";
+						G_next <= X"bc";
+						B_next <= X"35";
+					when X"cb" =>
+						R_next <= X"95";
+						G_next <= X"cd";
+						B_next <= X"46";
+					when X"cc" =>
+						R_next <= X"a4";
+						G_next <= X"dc";
+						B_next <= X"55";
+					when X"cd" =>
+						R_next <= X"b5";
+						G_next <= X"ed";
+						B_next <= X"67";
+					when X"ce" =>
+						R_next <= X"c5";
+						G_next <= X"fb";
+						B_next <= X"77";
+					when X"cf" =>
+						R_next <= X"d5";
+						G_next <= X"ff";
+						B_next <= X"86";
+					when X"d0" =>
+						R_next <= X"02";
+						G_next <= X"18";
+						B_next <= X"00";
+					when X"d1" =>
+						R_next <= X"0f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"d2" =>
+						R_next <= X"1f";
+						G_next <= X"34";
+						B_next <= X"00";
+					when X"d3" =>
+						R_next <= X"2f";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"d4" =>
+						R_next <= X"3f";
+						G_next <= X"54";
+						B_next <= X"00";
+					when X"d5" =>
+						R_next <= X"4f";
+						G_next <= X"65";
+						B_next <= X"00";
+					when X"d6" =>
+						R_next <= X"60";
+						G_next <= X"75";
+						B_next <= X"00";
+					when X"d7" =>
+						R_next <= X"70";
+						G_next <= X"86";
+						B_next <= X"01";
+					when X"d8" =>
+						R_next <= X"7b";
+						G_next <= X"90";
+						B_next <= X"0a";
+					when X"d9" =>
+						R_next <= X"8c";
+						G_next <= X"a1";
+						B_next <= X"1c";
+					when X"da" =>
+						R_next <= X"9c";
+						G_next <= X"b1";
+						B_next <= X"2c";
+					when X"db" =>
+						R_next <= X"ad";
+						G_next <= X"c2";
+						B_next <= X"3e";
+					when X"dc" =>
+						R_next <= X"bd";
+						G_next <= X"d1";
+						B_next <= X"4d";
+					when X"dd" =>
+						R_next <= X"cd";
+						G_next <= X"e2";
+						B_next <= X"5e";
+					when X"de" =>
+						R_next <= X"dd";
+						G_next <= X"f1";
+						B_next <= X"6e";
+					when X"df" =>
+						R_next <= X"ed";
+						G_next <= X"fd";
+						B_next <= X"7e";
+					when X"e0" =>
+						R_next <= X"1e";
+						G_next <= X"09";
+						B_next <= X"00";
+					when X"e1" =>
+						R_next <= X"2a";
+						G_next <= X"16";
+						B_next <= X"00";
+					when X"e2" =>
+						R_next <= X"39";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"e3" =>
+						R_next <= X"49";
+						G_next <= X"36";
+						B_next <= X"00";
+					when X"e4" =>
+						R_next <= X"58";
+						G_next <= X"45";
+						B_next <= X"00";
+					when X"e5" =>
+						R_next <= X"69";
+						G_next <= X"56";
+						B_next <= X"00";
+					when X"e6" =>
+						R_next <= X"79";
+						G_next <= X"66";
+						B_next <= X"00";
+					when X"e7" =>
+						R_next <= X"8a";
+						G_next <= X"77";
+						B_next <= X"08";
+					when X"e8" =>
+						R_next <= X"94";
+						G_next <= X"81";
+						B_next <= X"12";
+					when X"e9" =>
+						R_next <= X"a5";
+						G_next <= X"92";
+						B_next <= X"24";
+					when X"ea" =>
+						R_next <= X"b5";
+						G_next <= X"a3";
+						B_next <= X"35";
+					when X"eb" =>
+						R_next <= X"c6";
+						G_next <= X"b3";
+						B_next <= X"46";
+					when X"ec" =>
+						R_next <= X"d6";
+						G_next <= X"c3";
+						B_next <= X"55";
+					when X"ed" =>
+						R_next <= X"e6";
+						G_next <= X"d4";
+						B_next <= X"66";
+					when X"ee" =>
+						R_next <= X"f6";
+						G_next <= X"e3";
+						B_next <= X"76";
+					when X"ef" =>
+						R_next <= X"fe";
+						G_next <= X"f3";
+						B_next <= X"86";
+					when X"f0" =>
+						R_next <= X"34";
+						G_next <= X"00";
+						B_next <= X"00";
+					when X"f1" =>
+						R_next <= X"40";
+						G_next <= X"05";
+						B_next <= X"00";
+					when X"f2" =>
+						R_next <= X"4f";
+						G_next <= X"15";
+						B_next <= X"00";
+					when X"f3" =>
+						R_next <= X"5f";
+						G_next <= X"25";
+						B_next <= X"00";
+					when X"f4" =>
+						R_next <= X"6e";
+						G_next <= X"35";
+						B_next <= X"00";
+					when X"f5" =>
+						R_next <= X"7f";
+						G_next <= X"46";
+						B_next <= X"03";
+					when X"f6" =>
+						R_next <= X"8f";
+						G_next <= X"56";
+						B_next <= X"13";
+					when X"f7" =>
+						R_next <= X"9f";
+						G_next <= X"67";
+						B_next <= X"23";
+					when X"f8" =>
+						R_next <= X"aa";
+						G_next <= X"71";
+						B_next <= X"2e";
+					when X"f9" =>
+						R_next <= X"ba";
+						G_next <= X"82";
+						B_next <= X"40";
+					when X"fa" =>
+						R_next <= X"cb";
+						G_next <= X"92";
+						B_next <= X"51";
+					when X"fb" =>
+						R_next <= X"dc";
+						G_next <= X"a3";
+						B_next <= X"62";
+					when X"fc" =>
+						R_next <= X"eb";
+						G_next <= X"b3";
+						B_next <= X"71";
+					when X"fd" =>
+						R_next <= X"fa";
+						G_next <= X"c3";
+						B_next <= X"82";
+					when X"fe" =>
+						R_next <= X"fe";
+						G_next <= X"d3";
+						B_next <= X"92";
+					when X"ff" =>
+						R_next <= X"ff";
+						G_next <= X"e3";
+						B_next <= X"a1";
+			end case;
+			
+		end process;
+		
+end laoo;
Index: unmerged/core/mist/hq_dac.v
===================================================================
--- unmerged/core/mist/hq_dac.v	(nonexistent)
+++ unmerged/core/mist/hq_dac.v	(revision 1)
@@ -0,0 +1,100 @@
+`timescale 1ns / 1ps
+
+// This module is a third order delta/sigma modulator
+// It uses no multiply only shifts by 1, 2 or 13
+// There are only 7 adders used, it takes around 110 LUTs
+module hq_dac
+(
+  input         reset,
+  input         clk,
+  input         clk_ena,
+  input  [19:0] pcm_in,
+  output reg    dac_out
+);
+
+// ======================================
+// ============== Stage #1 ==============
+// ======================================
+wire [23:0] w_data_in_p0;
+wire [23:0] w_data_err_p0;
+wire [23:0] w_data_int_p0;
+reg  [23:0] r_data_fwd_p1;
+
+// PCM input extended to 24 bits
+assign w_data_in_p0  = { {4{pcm_in[19]}}, pcm_in };
+
+// Error between the input and the quantizer output
+assign w_data_err_p0 = w_data_in_p0 - w_data_qt_p2;
+
+// First integrator adder
+assign w_data_int_p0 = { {3{w_data_err_p0[23]}}, w_data_err_p0[22:2] } // Divide by 4
+                     + r_data_fwd_p1;
+
+// First integrator forward delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_fwd_p1 <= 24'd0;
+  else if (clk_ena)
+    r_data_fwd_p1 <= w_data_int_p0;
+
+// ======================================
+// ============== Stage #2 ==============
+// ======================================
+wire [23:0] w_data_fb1_p1;
+wire [23:0] w_data_fb2_p1;
+wire [23:0] w_data_lpf_p1;
+reg  [23:0] r_data_lpf_p2;
+
+// Feedback from the quantizer output
+assign w_data_fb1_p1 = { {3{r_data_fwd_p1[23]}}, r_data_fwd_p1[22:2] } // Divide by 4
+                     - { {3{w_data_qt_p2[23]}},  w_data_qt_p2[22:2] }; // Divide by 4
+
+// Feedback from the third stage
+assign w_data_fb2_p1 = w_data_fb1_p1
+                     - { {14{r_data_fwd_p2[23]}}, r_data_fwd_p2[22:13] }; // Divide by 8192
+
+// Low pass filter
+assign w_data_lpf_p1 = w_data_fb2_p1 + r_data_lpf_p2;
+
+// Low pass filter feedback delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_lpf_p2 <= 24'd0;
+  else if (clk_ena)
+    r_data_lpf_p2 <= w_data_lpf_p1;
+
+// ======================================
+// ============== Stage #3 ==============
+// ======================================
+wire [23:0] w_data_fb3_p1;
+wire [23:0] w_data_int_p1;
+reg  [23:0] r_data_fwd_p2;
+
+// Feedback from the quantizer output
+assign w_data_fb3_p1 = { {2{w_data_lpf_p1[23]}}, w_data_lpf_p1[22:1] } // Divide by 2
+                     - { {2{w_data_qt_p2[23]}},  w_data_qt_p2[22:1] }; // Divide by 2
+
+// Second integrator adder
+assign w_data_int_p1 = w_data_fb3_p1 + r_data_fwd_p2;
+
+// Second integrator forward delay
+always @(posedge reset or posedge clk)
+  if (reset)
+    r_data_fwd_p2 <= 24'd0;
+  else if (clk_ena)
+    r_data_fwd_p2 <= w_data_int_p1;
+
+// =====================================
+// ========== 1-bit quantizer ==========
+// =====================================
+wire [23:0] w_data_qt_p2;
+
+assign w_data_qt_p2 = (r_data_fwd_p2[23]) ? 24'hF00000 : 24'h100000;
+
+always @(posedge reset or posedge clk)
+  if (reset)
+    dac_out <= 1'b0;
+  else if (clk_ena)
+    dac_out <= ~r_data_fwd_p2[23];
+
+endmodule
Index: unmerged/core/mist/ledsw.vhd
===================================================================
--- unmerged/core/mist/ledsw.vhd	(nonexistent)
+++ unmerged/core/mist/ledsw.vhd	(revision 1)
@@ -0,0 +1,70 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+-- Simple module that connects the SW switches to the LEDR lights
+ENTITY ledsw IS
+PORT ( 
+	CLK : IN STD_LOGIC;
+
+	SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+	KEY : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	SYNC_KEYS : out std_logic_vector(3 downto 0);
+	SYNC_SWITCHES : out std_logic_vector(9 downto 0)
+); 
+END ledsw;
+
+ARCHITECTURE Behavior OF ledsw IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+		
+	signal sw_reg : std_logic_vector(9 downto 0);
+	signal key_reg : std_logic_vector(3 downto 0);
+	
+BEGIN
+	sw9_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(9), sync=>sw_reg(9));	
+	sw8_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(8), sync=>sw_reg(8));	
+	sw7_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(7), sync=>sw_reg(7));	
+	sw6_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(6), sync=>sw_reg(6));	
+	sw5_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(5), sync=>sw_reg(5));			
+	sw4_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(4), sync=>sw_reg(4));	
+	sw3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(3), sync=>sw_reg(3));	
+	sw2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(2), sync=>sw_reg(2));	
+	sw1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(1), sync=>sw_reg(1));	
+	sw0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sw(0), sync=>sw_reg(0));			
+
+	key3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(3)), sync=>key_reg(3));	
+	key2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(2)), sync=>key_reg(2));	
+	key1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(1)), sync=>key_reg(1));	
+	key0_synchronizer : synchronizer
+		port map (clk=>clk, raw=>not(key(0)), sync=>key_reg(0));			
+	
+	-- outputs
+	SYNC_KEYS <= key_reg(3)&key_reg(2)&key_reg(1)&key_reg(0);
+	SYNC_SWITCHES <= sw_reg(9)&sw_reg(8)&sw_reg(7)&sw_reg(6)&sw_reg(5)&sw_reg(4)&sw_reg(3)&sw_reg(2)&sw_reg(1)&sw_reg(0);
+END Behavior;
Index: unmerged/core/mist/mist_sector_buffer.qip
===================================================================
--- unmerged/core/mist/mist_sector_buffer.qip	(nonexistent)
+++ unmerged/core/mist/mist_sector_buffer.qip	(revision 1)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 2-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "mist_sector_buffer.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mist_sector_buffer.cmp"]
Index: unmerged/core/mist/pia.vhdl
===================================================================
--- unmerged/core/mist/pia.vhdl	(nonexistent)
+++ unmerged/core/mist/pia.vhdl	(revision 1)
@@ -0,0 +1,402 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pia IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	EN : IN STD_LOGIC;
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	CA1 : IN STD_LOGIC;
+	CB1 : IN STD_LOGIC;	
+	
+	CA2_DIR_OUT : OUT std_logic;
+	CA2_OUT : OUT std_logic;
+	CA2_IN : IN STD_LOGIC;
+
+	CB2_DIR_OUT : OUT std_logic;
+	CB2_OUT : OUT std_logic;
+	CB2_IN : IN STD_LOGIC;
+	
+	-- remember these two are different if connecting to gpio (push pull vs pull up - check 6520 data sheet...)
+	PORTA_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- pull up - i.e. 0 driven only
+	PORTA_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- set bit to 1 to enable output mode
+	PORTA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	PORTB_DIR_OUT : OUT STD_LOGIC_VECTOR(7 downto 0);
+	PORTB_OUT : OUT STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	PORTB_IN : IN STD_LOGIC_VECTOR(7 downto 0); -- push pull
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+	IRQA_N : OUT STD_LOGIC;
+	IRQB_N : OUT STD_LOGIC
+);
+END pia;
+
+ARCHITECTURE vhdl OF pia IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	signal addr_decoded : std_logic_vector(3 downto 0);
+	
+	signal porta_output_next : std_logic_vector(7 downto 0);
+	signal porta_output_reg : std_logic_vector(7 downto 0);
+	signal porta_input_reg : std_logic_vector(7 downto 0);
+	signal porta_input_next : std_logic_vector(7 downto 0);
+
+	signal porta_direction_next : std_logic_vector(7 downto 0);
+	signal porta_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal porta_control_next : std_logic_vector(5 downto 0);
+	signal porta_control_reg : std_logic_vector(5 downto 0);
+	
+	signal portb_output_next : std_logic_vector(7 downto 0);
+	signal portb_output_reg : std_logic_vector(7 downto 0);
+	signal portb_input_reg : std_logic_vector(7 downto 0);
+	signal portb_input_next : std_logic_vector(7 downto 0);	
+
+	signal portb_direction_next : std_logic_vector(7 downto 0);
+	signal portb_direction_reg : std_logic_vector(7 downto 0);
+	
+	signal portb_control_next : std_logic_vector(5 downto 0);
+	signal portb_control_reg : std_logic_vector(5 downto 0);
+	
+	signal irqa_next : std_logic_vector(1 downto 0);
+	signal irqa_reg : std_logic_vector(1 downto 0);
+	signal irqb_next : std_logic_vector(1 downto 0);
+	signal irqb_reg : std_logic_vector(1 downto 0);
+	
+	signal CA1_reg : std_logic;
+	signal CA2_reg : std_logic;
+	signal CB1_reg : std_logic;
+	signal CB2_reg : std_logic;
+
+	signal CA2_output_next : std_logic;
+	signal CA2_output_reg : std_logic;
+	signal CB2_output_next : std_logic;
+	signal CB2_output_reg : std_logic;
+	
+	signal read_ora : std_logic;
+	signal read_orb : std_logic;
+	
+	signal write_ora : std_logic;
+	signal write_orb : std_logic;
+
+	signal ca1_edge_next : std_logic;
+	signal ca1_edge_reg : std_logic;	
+	signal ca2_edge_next : std_logic;
+	signal ca2_edge_reg : std_logic;
+	
+	signal cb1_edge_next : std_logic;
+	signal cb1_edge_reg : std_logic;	
+	signal cb2_edge_next : std_logic;
+	signal cb2_edge_reg : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			porta_output_reg <= (others=>'0');
+			porta_input_reg <= (others=>'0');
+			porta_direction_reg <= (others=>'0'); -- default to input
+			porta_control_reg <= (others=>'0');
+			
+			portb_output_reg <= X"FF"; -- all high to ensure we have OS Rom enabled
+			portb_input_reg <= (others=>'0');
+			portb_direction_reg <= (others=>'1'); -- default to ouput
+			portb_control_reg <= (others=>'0');
+			
+			irqa_reg <= (others=>'0');
+			irqb_reg <= (others=>'0');
+			
+			CA1_reg	<= '0';
+			CA2_reg	<= '0';
+			CB1_reg	<= '0';
+			CB2_reg	<= '0';
+			
+			CA2_output_reg <= '0';
+			CB2_output_reg <= '0';
+			
+			ca1_edge_reg <= '0';
+			ca2_edge_reg <= '0';
+			
+			cb1_edge_reg <= '0';
+			cb2_edge_reg <= '0';
+			
+		elsif (clk'event and clk='1') then						
+			porta_output_reg <= porta_output_next;
+			porta_input_reg <= porta_input_next;
+			porta_direction_reg <= porta_direction_next;
+			porta_control_reg <= porta_control_next;
+			
+			portb_output_reg <= portb_output_next;
+			portb_input_reg <= PORTB_input_next;
+			portb_direction_reg <= portb_direction_next;
+			portb_control_reg <= portb_control_next;	
+	
+			irqa_reg <= irqa_next;
+			irqb_reg <= irqb_next;
+	
+			CA1_reg	<= CA1;
+			CA2_reg	<= CA2_in;
+			CB1_reg	<= CB1;
+			CB2_reg	<= CB2_in;
+			
+			CA2_output_reg <= CA2_output_next;
+			CB2_output_reg <= CB2_output_next;
+
+			ca1_edge_reg <= ca1_edge_next;			
+			ca2_edge_reg <= ca2_edge_next;
+			
+			cb1_edge_reg <= cb1_edge_next;			
+			cb2_edge_reg <= cb2_edge_next;			
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>2)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr_decoded, porta_output_reg, portb_output_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg)
+	begin
+		porta_output_next <= porta_output_reg;
+		portb_output_next <= portb_output_reg;
+		porta_direction_next <= porta_direction_reg;
+		portb_direction_next <= portb_direction_reg;
+		porta_control_next(5 downto 0) <= porta_control_reg(5 downto 0);
+		portb_control_next(5 downto 0) <= portb_control_reg(5 downto 0);
+		
+		write_ora <= '0';
+		write_orb <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					porta_output_next <= cpu_data_in;
+					write_ora <= '1';
+				else
+					porta_direction_next <= cpu_data_in;
+				end if;
+			end if;	
+
+			if(addr_decoded(1) = '1') then				
+				if (portb_control_reg(2) = '1') then
+					portb_output_next <= cpu_data_in;
+					write_orb <= '1';
+				else
+					portb_direction_next <= cpu_data_in;
+				end if;			
+			end if;						
+
+			if(addr_decoded(2) = '1') then	
+				porta_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;						
+			
+			if(addr_decoded(3) = '1') then		
+				portb_control_next(5 downto 0) <= cpu_data_in(5 downto 0);
+			end if;															
+
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded, en, porta_input_reg, portb_input_reg, porta_direction_reg, portb_direction_reg, porta_control_reg, portb_control_reg, irqa_reg, irqb_reg)
+	begin
+		data_out <= X"FF";
+		read_ora <= '0';
+		read_orb <= '0';
+
+		if (EN = '1') then -- since reads have an effect here...
+			if (addr_decoded(0) = '1') then
+				if (porta_control_reg(2) = '1') then
+					data_out <= porta_input_reg;
+					read_ora <= '1';
+				else
+					data_out <= porta_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(1) = '1') then
+				if (portb_control_reg(2) = '1') then
+					data_out <= portb_input_reg;
+					read_orb <= '1';
+				else
+					data_out <= portb_direction_reg; -- can this be read?
+				end if;
+			end if;
+
+			if (addr_decoded(2) = '1') then			
+				data_out <= irqa_reg(1)&(irqa_reg(0)and not(porta_control_reg(5)))&porta_control_reg;
+			end if;
+
+			if (addr_decoded(3) = '1') then			
+				data_out <= irqb_reg(1)&(irqb_reg(0)and not(portb_control_reg(5)))&portb_control_reg;
+			end if;
+		end if;
+		
+	end process;
+	
+	-- irq handing
+	-- TODO REVIEW, this stuff is complicated! I think Atari does not need it anyway...
+	process (irqa_reg, porta_control_next, porta_control_reg, read_ora, write_ora, ca2_output_reg, CA1, CA1_reg, ca2_in, ca2_reg, ca1_edge_reg, ca2_edge_reg)
+	begin
+		irqa_next(1) <= irqa_reg(1) and not(read_ora);
+		irqa_next(0) <= irqa_reg(0) and not(read_ora);
+				
+		ca2_output_next <= ca2_output_reg;
+
+		if (CA1 = '1' and CA1_reg = '0') then
+			irqa_next(1) <= ca1_edge_reg;
+		end if;
+		if (CA1 = '0' and CA1_reg = '1') then
+			irqa_next(1) <= not(ca1_edge_reg);
+		end if;
+		
+		if (CA2_in = '1' and CA2_reg = '0') then
+			irqa_next(0) <= ca2_edge_reg;
+		end if;
+		
+		if (CA2_in = '0' and CA2_reg = '1') then
+			irqa_next(0) <= not(ca2_edge_reg);
+		end if;	
+		
+		ca1_edge_next <= porta_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		ca2_edge_next <= porta_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (porta_control_next(5) = '0') then -- CA2 is an input					
+		else -- CA2 is an output
+			--irqa_next(0) <= '0';
+			
+			case porta_control_next(4 downto 3) is
+				when "10" =>
+					ca2_output_next <= '0'; -- direct control
+				when "11" =>
+					ca2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					else						
+						-- clock restore
+						ca2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (read_ora = '1') then
+						ca2_output_next <= '0';
+					elsif (irqa_reg(1) = '1') then
+						-- ca1 restore
+						ca2_output_next <= '1';	
+					end if;				
+			end case;					
+		end if;
+
+	end process;
+
+	process (irqb_reg, portb_control_next, portb_control_reg, read_orb, write_orb, cb2_output_reg, CB1, CB1_reg, cb2_in, cb2_reg, cb1_edge_reg, cb2_edge_reg)
+	begin
+		irqb_next(1) <= irqb_reg(1) and not(read_orb);
+		irqb_next(0) <= irqb_reg(0) and not(read_orb);
+				
+		cb2_output_next <= cb2_output_reg;
+
+		if (CB1 = '1' and CB1_reg = '0') then
+			irqb_next(1) <= cb1_edge_reg;
+		end if;
+		if (CB1 = '0' and CB1_reg = '1') then
+			irqb_next(1) <= not(cb1_edge_reg);
+		end if;
+		
+		if (CB2_in = '1' and CB2_reg = '0') then
+			irqb_next(0) <= cb2_edge_reg;
+		end if;
+		
+		if (CB2_in = '0' and CB2_reg = '1') then
+			irqb_next(0) <= not(cb2_edge_reg);
+		end if;	
+		
+		cb1_edge_next <= portb_control_next(0); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		cb2_edge_next <= portb_control_next(4); -- delay 1 cycle, so I am still set to detect falling edge on the rising edge
+		
+		if (portb_control_next(5) = '0') then -- CB2 is an input					
+		else -- CB2 is an output
+			--irqb_next(0) <= '0';
+			
+			case portb_control_next(4 downto 3) is
+				when "10" =>
+					cb2_output_next <= '0'; -- direct control
+				when "11" =>
+					cb2_output_next <= '1'; -- direct control
+				when "01" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					else						
+						-- clock restore
+						cb2_output_next <= '1';
+					end if;
+				when "00" =>
+					if (write_orb = '1') then
+						cb2_output_next <= '0';
+					elsif (irqb_reg(1) = '1') then
+						-- cb1 restore
+						cb2_output_next <= '1';	
+					end if;				
+			end case;					
+		end if;
+
+	end process;
+	
+	-- output
+		-- TODO - review if ca2 and cb2 are push pull or pull up...
+	--ca2 <= CA2_output_reg when porta_control_reg(5) = '1' else 'Z';
+	--cb2 <= CB2_output_reg when portb_control_reg(5) = '1' else 'Z';
+	ca2_out <= CA2_output_reg;
+	ca2_dir_out <= porta_control_reg(5);
+	cb2_out <= CB2_output_reg;
+	cb2_dir_out <= portb_control_reg(5);
+	
+	porta_out <= porta_output_reg;
+	porta_dir_out <= porta_direction_reg;
+	porta_input_next <= porta_in;
+
+	--portb_out <= portb_output_reg;
+	-- forced to 1 when in input mode - star raiders relies on this
+	portb_out(0) <= portb_output_reg(0) when portb_direction_reg(0)='1' else '1';
+	portb_out(1) <= portb_output_reg(1) when portb_direction_reg(1)='1' else '1';
+	portb_out(2) <= portb_output_reg(2) when portb_direction_reg(2)='1' else '1';
+	portb_out(3) <= portb_output_reg(3) when portb_direction_reg(3)='1' else '1';	
+	portb_out(4) <= portb_output_reg(4) when portb_direction_reg(4)='1' else '1';
+	portb_out(5) <= portb_output_reg(5) when portb_direction_reg(5)='1' else '1';
+	portb_out(6) <= portb_output_reg(6) when portb_direction_reg(6)='1' else '1';
+	portb_out(7) <= portb_output_reg(7) when portb_direction_reg(7)='1' else '1';		
+	portb_dir_out <= portb_direction_reg;
+	portb_input_next <= portb_in;
+	
+	irqa_n <= not(((irqa_reg(1) and porta_control_reg(0)) or (irqa_reg(0) and porta_control_reg(3))) and not(porta_control_reg(5)));
+	irqb_n <= not(((irqb_reg(1) and portb_control_reg(0)) or (irqb_reg(0) and portb_control_reg(3))) and not(portb_control_reg(5)));
+	
+end vhdl;
+
+
Index: unmerged/core/mist/pll.qip
===================================================================
--- unmerged/core/mist/pll.qip	(nonexistent)
+++ unmerged/core/mist/pll.qip	(revision 1)
@@ -0,0 +1,6 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.cmp"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
Index: unmerged/core/mist/pokey_keyboard_scanner.vhdl
===================================================================
--- unmerged/core/mist/pokey_keyboard_scanner.vhdl	(nonexistent)
+++ unmerged/core/mist/pokey_keyboard_scanner.vhdl	(revision 1)
@@ -0,0 +1,179 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity pokey_keyboard_scanner is
+port
+(
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	enable : in std_logic; -- typically hsync or equiv timing
+	keyboard_response : in std_logic_vector(1 downto 0);
+	debounce_disable : in std_logic;
+	scan_enable : in std_logic;
+	
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	
+	shift_pressed : out std_logic;
+	control_pressed : out std_logic;
+	break_pressed : out std_logic;
+	key_held : out std_logic;
+	keycode : out std_logic_vector(5 downto 0);
+	other_key_irq : out std_logic
+);
+end pokey_keyboard_scanner;
+
+architecture vhdl of pokey_keyboard_scanner is
+	signal bincnt_next : std_logic_vector(5 downto 0);
+	signal bincnt_reg : std_logic_vector(5 downto 0);
+
+	signal break_pressed_next : std_logic;
+	signal break_pressed_reg : std_logic;
+
+	signal shift_pressed_next : std_logic;
+	signal shift_pressed_reg : std_logic;
+	
+	signal control_pressed_next : std_logic;
+	signal control_pressed_reg : std_logic;	
+	
+	signal compare_latch_next : std_logic_vector(5 downto 0);
+	signal compare_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal keycode_latch_next : std_logic_vector(5 downto 0);
+	signal keycode_latch_reg : std_logic_vector(5 downto 0);
+	
+	signal irq_next : std_logic;
+	signal irq_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal my_key : std_logic;
+	
+	signal state_next : std_logic_vector(1 downto 0);
+	signal state_reg : std_logic_vector(1 downto 0);
+	constant state_wait_key : std_logic_vector(1 downto 0) := "00";
+	constant state_key_bounce : std_logic_vector(1 downto 0) := "01";
+	constant state_valid_key : std_logic_vector(1 downto 0) := "10";
+	constant state_key_debounce : std_logic_vector(1 downto 0) := "11";
+begin
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			bincnt_reg <= (others=>'0');
+			break_pressed_reg <= '0';
+			shift_pressed_reg <= '0';
+			control_pressed_reg <= '0';
+			compare_latch_reg <= (others=>'0');
+			keycode_latch_reg <= (others=>'1');
+			key_held_reg <= '0';
+			state_reg <= state_wait_key;
+			irq_reg <= '0';
+		elsif (clk'event and clk = '1') then
+			bincnt_reg <= bincnt_next;
+			state_reg <= state_next;
+			break_pressed_reg <= break_pressed_next;
+			shift_pressed_reg <= shift_pressed_next;
+			control_pressed_reg <= control_pressed_next;
+			compare_latch_reg <= compare_latch_next;
+			keycode_latch_reg <= keycode_latch_next;
+			key_held_reg <= key_held_next;
+			state_reg <= state_next;
+			irq_reg <= irq_next;
+		end if;
+	end process;
+
+	process (enable, keyboard_response, scan_enable, key_held_reg, my_key, state_reg,bincnt_reg, compare_latch_reg, break_pressed_reg, shift_pressed_reg, control_pressed_reg, keycode_latch_reg, debounce_disable)
+	begin
+		bincnt_next <= bincnt_reg;
+		state_next <= state_reg;
+		compare_latch_next <= compare_latch_reg;
+		irq_next <= '0';
+		break_pressed_next <= break_pressed_reg;
+		shift_pressed_next <= shift_pressed_reg;
+		control_pressed_next <= control_pressed_reg;
+		keycode_latch_next <= keycode_latch_reg;
+		key_held_next <= key_held_reg;
+		
+		my_key <= '0';
+		if (bincnt_reg = compare_latch_reg or debounce_disable='1') then
+			my_key <= '1';
+		end if;
+		
+		if (enable = '1' and scan_enable='1') then			
+			bincnt_next <= std_logic_vector(unsigned(bincnt_reg) + 1); -- check another key
+		
+			key_held_next<= '0';
+		
+			case state_reg is
+			when state_wait_key =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					state_next <= state_key_bounce;
+					compare_latch_next <= bincnt_reg;
+				end if;
+				
+			when state_key_bounce =>
+				if (keyboard_response(0) = '0') then -- detected key press
+					if (my_key = '1') then -- same key
+						keycode_latch_next <= compare_latch_reg;
+						irq_next <= '1';
+						key_held_next<= '1';
+						state_next <= state_valid_key;
+					else -- different key (multiple keys pressed)
+						state_next <= state_wait_key;
+					end if;
+				else -- key not pressed
+					if (my_key = '1') then -- same key, no longer pressed
+						state_next <= state_wait_key;
+					end if;
+				end if;
+			
+			when state_valid_key =>
+				key_held_next<= '1';
+				if (my_key = '1') then -- only response to my key
+					if (keyboard_response(0) = '1') then -- no longer pressed
+						state_next <= state_key_debounce;
+					end if;					
+				end if;
+				
+			when state_key_debounce =>
+				if (my_key = '1') then
+					state_next <= state_wait_key;
+				end if;
+			end case;
+
+			if (bincnt_reg(3 downto 0)  = "0000") then
+				case bincnt_reg(5 downto 4) is
+				when "11" =>
+					break_pressed_next <= not(keyboard_response(1)); --0x30
+				when "01" =>
+					shift_pressed_next <= not(keyboard_response(1)); --0x10
+				when "00" =>
+					control_pressed_next <= not(keyboard_response(1)); -- 0x00
+				when others =>
+					--
+				end case;
+			end if;
+		end if;
+	end process;
+	
+	-- outputs
+	keyboard_scan <= not(bincnt_reg);
+	
+	key_held <= key_held_reg;	
+	keycode <= keycode_latch_reg;
+	break_pressed <= break_pressed_reg;
+	shift_pressed <= shift_pressed_reg;
+	control_pressed <= control_pressed_reg;
+	other_key_irq <= irq_reg;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/pokey_ps2_decoder.vhdl
===================================================================
--- unmerged/core/mist/pokey_ps2_decoder.vhdl	(nonexistent)
+++ unmerged/core/mist/pokey_ps2_decoder.vhdl	(revision 1)
@@ -0,0 +1,468 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_ps2_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : std_logic;
+	-- ENABLE : IN STD_LOGIC; TODO Pokey debounce and scanning can be disabled
+	
+	-- ps2 keyboard input
+	KEY_EVENT : IN STD_LOGIC;
+	KEY_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
+	KEY_EXTENDED : IN STD_LOGIC;
+	KEY_UP : IN STD_LOGIC;
+	
+	-- pokey output
+	KBCODE : OUT STD_LOGIC_VECTOR(7 downto 0);
+	KEY_HELD : OUT STD_LOGIC;
+	SHIFT_PRESSED : OUT STD_LOGIC;
+	BREAK_PRESSED : OUT STD_LOGIC;
+	KEY_INTERRUPT : OUT STD_LOGIC;
+	
+	-- other output
+	CONSOL_START : OUT STD_LOGIC;
+	CONSOL_SELECT : OUT STD_LOGIC;
+	CONSOL_OPTION : OUT STD_LOGIC;
+	
+	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+	
+	SYSTEM_RESET : out std_logic;
+	
+	VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+);
+END pokey_ps2_decoder;
+
+ARCHITECTURE vhdl OF pokey_ps2_decoder IS
+	signal left_shift_pressed_reg : std_logic;
+	signal left_shift_pressed_next : std_logic;
+	signal right_shift_pressed_reg : std_logic;
+	signal right_shift_pressed_next : std_logic;	
+	
+	signal left_control_pressed_reg : std_logic;
+	signal left_control_pressed_next : std_logic;	
+	signal right_control_pressed_reg : std_logic;
+	signal right_control_pressed_next : std_logic;	
+	
+	signal kbcode_next : std_logic_vector(7 downto 0);
+	signal kbcode_reg : std_logic_vector(7 downto 0); -- XXX remove unused upper bits
+	
+	signal interrupt_next : std_logic;
+	signal interrupt_reg : std_logic;
+	
+	signal break_next : std_logic;
+	signal break_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal start_next : std_logic;
+	signal start_reg : std_logic;
+	signal select_next : std_logic;
+	signal select_reg : std_logic;	
+	signal option_next : std_logic;
+	signal option_reg : std_logic;
+	
+	signal virtual_up_next : std_logic;
+	signal virtual_up_reg : std_logic;
+	signal virtual_down_next : std_logic;
+	signal virtual_down_reg : std_logic;
+	signal virtual_left_next : std_logic;
+	signal virtual_left_reg : std_logic;
+	signal virtual_right_next : std_logic;
+	signal virtual_right_reg : std_logic;
+	signal virtual_stick_pressed_next : std_logic;
+	signal virtual_stick_pressed_reg : std_logic;
+	
+	signal system_reset_next : std_logic;
+	signal system_reset_reg : std_logic;	
+
+	signal virtual_keys_next : std_logic_vector(3 downto 0);
+	signal virtual_keys_reg : std_logic_vector(3 downto 0);	
+	
+	signal no_kbcode_update : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			left_shift_pressed_reg <= '0';
+			right_shift_pressed_reg <= '0';
+			
+			left_control_pressed_reg <= '0';
+			right_control_pressed_reg <= '0';
+			
+			kbcode_reg <= X"3F";
+			
+			interrupt_reg <= '0';
+			
+			break_reg <= '0';
+			
+			key_held_reg <= '0';
+			
+			start_reg <= '0';
+			select_reg <= '0';
+			option_reg <= '0';
+			
+			virtual_up_reg <= '0';
+			virtual_down_reg <= '0';
+			virtual_left_reg <= '0';
+			virtual_right_reg <= '0';
+			virtual_stick_pressed_reg <= '0';
+			
+			system_reset_reg <= '0';
+			
+			virtual_keys_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			left_shift_pressed_reg <= left_shift_pressed_next;
+			right_shift_pressed_reg <= right_shift_pressed_next;
+			
+			left_control_pressed_reg <= left_control_pressed_next;
+			right_control_pressed_reg <= right_control_pressed_next;			
+			
+			kbcode_reg <= kbcode_next;
+			
+			interrupt_reg <= interrupt_next;
+			
+			break_reg <= break_next;
+			
+			key_held_reg <= key_held_next;
+			
+			start_reg <= start_next;
+			select_reg <= select_next;
+			option_reg <= option_next;
+			
+			virtual_up_reg <= virtual_up_next;
+			virtual_down_reg <= virtual_down_next;
+			virtual_left_reg <= virtual_left_next;
+			virtual_right_reg <= virtual_right_next;
+			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+			
+			system_reset_reg <= system_reset_next;
+			virtual_keys_reg <= virtual_keys_next;
+		end if;
+	end process;
+	
+	-- update key pressed
+	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg, virtual_keys_reg)
+	begin
+		left_shift_pressed_next <= left_shift_pressed_reg;
+		right_shift_pressed_next <= right_shift_pressed_reg;
+		
+		left_control_pressed_next <= left_control_pressed_reg;
+		right_control_pressed_next <= right_control_pressed_reg;		
+	
+		kbcode_next <= kbcode_reg;
+		interrupt_next <= '0';
+		
+		break_next <= break_reg;
+	
+		start_next <= start_reg;
+		select_next <= select_reg;
+		option_next <= option_reg;
+		
+		virtual_up_next <= virtual_up_reg;
+		virtual_down_next <= virtual_down_reg;
+		virtual_left_next <= virtual_left_reg;
+		virtual_right_next <= virtual_right_reg;				
+		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+		
+		system_reset_next <= system_reset_reg;
+		virtual_keys_next <= virtual_keys_reg;
+		
+		key_held_next <= key_held_reg;
+		
+		no_kbcode_update <= '0';
+	
+		-- Core functionality exactly as the Atari layout
+		if (key_event = '1') then
+			interrupt_next <= not(key_up);			
+			key_held_next <= not(key_up);
+			
+			case key_extended&key_code is 
+			
+				-- Basic mapping - should allow all keys on Atari, just fiddly
+				when 
+					'0'&X"AA"|'1'&X"AA"|  -- BAT SUCCESSFUL
+					'0'&X"FC"|'1'&X"FC"   -- BAT FAIL
+					=>
+					no_kbcode_update <= '1';
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"4B" => --L
+					kbcode_next <= X"00";
+				when '0'&X"3B" => --J
+					kbcode_next <= X"01";					
+				when '0'&X"4C" => --;
+					kbcode_next <= X"02";										
+				when '0'&X"42" => --K
+					kbcode_next <= X"05";				
+				when '0'&X"79" => --+
+					kbcode_next <= X"06";
+				when '0'&X"7C" => --*
+					kbcode_next <= X"07";
+				when '0'&X"44" => --O
+					kbcode_next <= X"08";
+				when '0'&X"4D" => --P
+					kbcode_next <= X"0A";
+				when '0'&X"3C" => --U
+					kbcode_next <= X"0B";
+				when '0'&X"5A" => --Enter
+					kbcode_next <= X"0C";
+				when '0'&X"43" => --I
+					kbcode_next <= X"0D";
+				when '0'&X"4E" => -- -
+					kbcode_next <= X"0E";
+				when '0'&X"55" => -- =
+					kbcode_next <= X"0F";
+
+				when '0'&X"2A" => --V
+					kbcode_next <= X"10";
+				when '0'&X"05" => --Help (Using F1)
+					kbcode_next <= X"11";					
+				when '0'&X"21" => --C
+					kbcode_next <= X"12";										
+				when '0'&X"32" => --B
+					kbcode_next <= X"15";				
+				when '0'&X"22" => --X
+					kbcode_next <= X"16";
+				when '0'&X"1A" => --Z
+					kbcode_next <= X"17";
+				when '0'&X"25" => --4
+					kbcode_next <= X"18";
+				when '0'&X"26" => --3
+					kbcode_next <= X"1A";
+				when '0'&X"36" => --6
+					kbcode_next <= X"1B";
+				when '0'&X"76" => --Esc
+					kbcode_next <= X"1C";
+				when '0'&X"2E" => --5
+					kbcode_next <= X"1D";
+				when '0'&X"1E" => --2
+					kbcode_next <= X"1E";
+				when '0'&X"16" => --1
+					kbcode_next <= X"1F";
+
+				when '0'&X"41" => --,
+					kbcode_next <= X"20";
+				when '0'&X"29" => --Spc
+					kbcode_next <= X"21";					
+				when '0'&X"49" => --.
+					kbcode_next <= X"22";										
+				when '0'&X"31" => --N
+					kbcode_next <= X"23";
+				when '0'&X"3A" => --M
+					kbcode_next <= X"25";				
+				when '0'&X"4A" => --/
+					kbcode_next <= X"26";
+				when '1'&X"11" => --Inv
+					kbcode_next <= X"27";
+				when '0'&X"2D" => --R
+					kbcode_next <= X"28";
+				when '0'&X"24" => --E
+					kbcode_next <= X"2A";
+				when '0'&X"35" => --Y
+					kbcode_next <= X"2B";
+				when '0'&X"0D" => --Tab
+					kbcode_next <= X"2C";
+				when '0'&X"2C" => --T
+					kbcode_next <= X"2D";
+				when '0'&X"1D" => --W
+					kbcode_next <= X"2E";
+				when '0'&X"15" => --Q
+					kbcode_next <= X"2F";					
+					
+				when '0'&X"46" => --9
+					kbcode_next <= X"30";				
+				when '0'&X"45" => --0
+					kbcode_next <= X"32";										
+				when '0'&X"3D" => --7
+					kbcode_next <= X"33";
+				when '0'&X"66" => --Backspace
+					kbcode_next <= X"34";						
+				when '0'&X"3E" => --8
+					kbcode_next <= X"35";				
+				when '0'&X"54" => --< (using [)
+					kbcode_next <= X"36";
+				when '0'&X"5B" => --> (using ])
+					kbcode_next <= X"37";
+				when '0'&X"2B" => --F
+					kbcode_next <= X"38";
+				when '0'&X"33" => --H
+					kbcode_next <= X"39";					
+				when '0'&X"23" => --D
+					kbcode_next <= X"3A";
+				when '0'&X"58" => --Caps
+					kbcode_next <= X"3C";
+				when '0'&X"34" => --G
+					kbcode_next <= X"3D";
+				when '0'&X"1B" => --S
+					kbcode_next <= X"3E";
+				when '0'&X"1C" => --A
+					kbcode_next <= X"3F";
+
+				when '0'&X"77" => --Break - XXX BUG, also presses 14, since E1 ext code...
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+				when '1'&X"77" => --Break
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+					
+				-- XXX BUGS
+				-- i) press shift when already holding key - does not update kbcode
+				-- ii) press key, then press another, then release second key. Should go back to first...
+				when '0'&X"12" => --Left shift
+					no_kbcode_update <= '1';
+					left_shift_pressed_next <= not(key_UP);					
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"59" => --Right shift
+					no_kbcode_update <= '1';
+					right_shift_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+					
+				when '0'&X"14" => --Left control
+					no_kbcode_update <= '1';
+					left_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '1'&X"14" => --Right control
+					no_kbcode_update <= '1';
+					right_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';			
+					key_held_next <= '0';
+					
+				when '0'&X"06" => --Start (F2)
+					no_kbcode_update <= '1';
+					start_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"04" => --Select (F3)
+					no_kbcode_update <= '1';
+					select_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"0C" => --Option (F4)
+					no_kbcode_update <= '1';
+					option_next <= not(key_UP);
+					interrupt_next <= '0';					
+					key_held_next <= '0';
+
+				-- TODO will also be useful to cursor control...
+				when '1'&X"75" => -- up
+					no_kbcode_update <= '1';
+					virtual_up_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"72" => -- down
+					no_kbcode_update <= '1';
+					virtual_down_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"6b" => -- left
+					no_kbcode_update <= '1';
+					virtual_left_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"74" => -- right
+					no_kbcode_update <= '1';
+					virtual_right_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';
+				when '1'&X"27" => -- right windows key -> fire button
+					no_kbcode_update <= '1';
+					virtual_stick_pressed_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"0a" => -- f8 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(0) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"01" => -- f9 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(1) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';						
+					
+				when '0'&X"09" => -- f10 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(2) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';						
+					
+				when '0'&X"78" => -- f11 => system reset
+					no_kbcode_update <= '1';
+					virtual_keys_next(3) <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';	
+					
+				when '0'&X"07" => -- f12 => system reset
+					no_kbcode_update <= '1';
+					system_reset_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';										
+					
+				when others =>
+					no_kbcode_update <= '1';
+					-- nop
+				-- Idea: Use Windows key and Alt for atari shift/control. Then use keyboard ones for 'nice' mapping as displayed on keyboard?
+			end case;
+			
+			if (key_up = '1' or no_kbcode_update = '1') then
+				kbcode_next <= kbcode_reg;				
+			else
+				kbcode_next(7 downto 6) <= (left_control_pressed_reg or right_control_pressed_reg)&(left_shift_pressed_reg or right_shift_pressed_reg);
+			end if;
+		end if;
+		
+		-- Then override a few for convenience
+		-- e.g. if we press '#' on the keyboard we want to see '#' on the atari, even though on the atari its shift a different key.
+
+--http://atariwiki.de/wiki/Wiki.jsp?page=KBCODE
+-- 			$00	$01	$02	$03	$04	$05	$06	$07	$08	$09	$0A	$0B	$0C	$0D	$0E	$0F
+--		$00	L		J		;		F1		F2		K		+		*		O	 			P		U		CR		I		-		=
+--		$10	V		Help	C		F3		F4		B		X		Z		4	 			3		6		Esc	5		2		1
+--		$20	,		Spc	.		N	 			M		/		Inv	R	 			E		Y		Tab	T		W		Q
+--		$30	9	 			0		7		BS		8		<		>		F		H		D	 			Caps	G		S		A
+--together with Shift Key: add +$40
+--together with Control key: add +$80
+
+-- Would be great to have option of using real Atari keyboard, but probably not worthwhile yet.
+
+	end process;
+			
+	-- output
+	kbcode <= kbcode_reg;
+	KEY_HELD <= key_held_reg;
+	shift_pressed <= left_shift_pressed_reg or right_shift_pressed_reg;
+	break_pressed <= break_reg;
+	
+	key_interrupt <= interrupt_reg;
+	
+	consol_start <= start_reg;
+	consol_select <= select_reg;
+	consol_option <= option_reg;
+	
+	VIRTUAL_STICKS <= not(virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg&virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg);
+	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+	
+	system_reset <= system_reset_reg;
+	virtual_keys <= virtual_keys_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/poly_5.vhdl
===================================================================
--- unmerged/core/mist/poly_5.vhdl	(nonexistent)
+++ unmerged/core/mist/poly_5.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_5 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_5;
+
+ARCHITECTURE vhdl OF poly_5 IS
+	signal shift_reg: std_logic_vector(4 downto 0);
+	signal shift_next: std_logic_vector(4 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(2) xnor shift_reg(0)) and not(init))&shift_reg(4 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: unmerged/core/mist/ramint.qip
===================================================================
--- unmerged/core/mist/ramint.qip	(nonexistent)
+++ unmerged/core/mist/ramint.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "ramint.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ramint.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "ramint.cmp"]
Index: unmerged/core/mist/rom16.qip
===================================================================
--- unmerged/core/mist/rom16.qip	(nonexistent)
+++ unmerged/core/mist/rom16.qip	(revision 1)
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom16.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "rom16.cmp"]
Index: unmerged/core/mist/gtia_priority.vhdl
===================================================================
--- unmerged/core/mist/gtia_priority.vhdl	(nonexistent)
+++ unmerged/core/mist/gtia_priority.vhdl	(revision 1)
@@ -0,0 +1,175 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY gtia_priority IS
+PORT 
+( 
+	CLK : in std_logic;
+	colour_enable : in std_logic;
+
+	PRIOR : in std_logic_vector(7 downto 0);
+	P0 : in std_logic;
+	P1 : in std_logic;
+	P2	: in std_logic;
+	P3 : in std_logic;
+	PF0 : in std_logic;
+	PF1 : in std_logic;
+	PF2 : in std_logic;
+	PF3 : in std_logic;
+	BK : in std_logic;
+	
+	P0_OUT : out std_logic;
+	P1_OUT : out std_logic;
+	P2_OUT : out std_logic;
+	P3_OUT : out std_logic;
+	PF0_OUT : out std_logic;
+	PF1_OUT : out std_logic;
+	PF2_OUT : out std_logic;
+	PF3_OUT : out std_logic;
+	BK_OUT : out std_logic
+);
+END gtia_priority;
+
+ARCHITECTURE vhdl OF gtia_priority IS
+	signal P01 : std_logic;
+	signal P23 : std_logic;
+	
+	signal PF01 : std_logic;
+	signal PF23 : std_logic;
+	
+	signal PRI01 : std_logic;
+	signal PRI12 : std_logic;
+	signal PRI23 : std_logic;
+	signal PRI03 : std_logic;
+	
+	signal PRI0 : std_logic;
+	signal PRI1 : std_logic;
+	signal PRI2 : std_logic;
+	signal PRI3 : std_logic;
+	signal MULTI : std_logic;
+	
+	signal SP0 : std_logic;
+	signal SP1 : std_logic;
+	signal SP2 : std_logic;
+	signal SP3 : std_logic;	
+	signal SF0 : std_logic;
+	signal SF1 : std_logic;
+	signal SF2 : std_logic;
+	signal SF3 : std_logic;	
+	signal SB : std_logic;
+	
+	signal SP0_next : std_logic;
+	signal SP1_next : std_logic;
+	signal SP2_next : std_logic;
+	signal SP3_next : std_logic;	
+	signal SF0_next : std_logic;
+	signal SF1_next : std_logic;
+	signal SF2_next : std_logic;
+	signal SF3_next : std_logic;	
+	signal SB_next : std_logic;
+
+	signal SP0_reg : std_logic;
+	signal SP1_reg : std_logic;
+	signal SP2_reg : std_logic;
+	signal SP3_reg : std_logic;	
+	signal SF0_reg : std_logic;
+	signal SF1_reg : std_logic;
+	signal SF2_reg : std_logic;
+	signal SF3_reg : std_logic;	
+	signal SB_reg : std_logic;
+begin
+	-- Use actual GTIA logic...
+	P01 <= P0 or P1;
+	P23 <= P2 or P3;
+
+	PF01 <= PF0 or PF1;
+	PF23 <= PF2 or PF3;
+	
+	PRI0 <= prior(0);
+	PRI1 <= prior(1);
+	PRI2 <= prior(2);
+	PRI3 <= prior(3);
+	MULTI <= prior(5);
+	
+	PRI01 <= PRI0  or  PRI1;
+	PRI12 <= PRI1  or  PRI2;
+	PRI23 <= PRI2  or  PRI3;
+	PRI03 <= PRI0  or  PRI3;
+	
+	SP0 <= P0  and   not (PF01 and PRI23)  and   not (PRI2 and PF23);
+	SP1 <= P1  and   not (PF01 and PRI23)  and   not (PRI2 and PF23)  and  ( not P0  or  MULTI);
+	SP2 <= P2  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0);
+	SP3 <= P3  and   not P01  and   not (PF23 and PRI12)  and   not (PF01 and  not PRI0)  and  ( not P2  or  MULTI);
+	SF0 <= PF0  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF1 <= PF1  and   not (P23 and PRI0)  and   not (P01 and PRI01)  and   not SF3;
+	SF2 <= PF2  and   not (P23 and PRI03)  and   not (P01 and  not PRI2)  and   not SF3;
+	SF3 <= PF3  and   not (P23 and PRI03)  and   not (P01 and  not PRI2);
+	SB <=  not P01  and   not P23  and   not PF01  and   not PF23;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+		SP0_reg <= SP0_next;
+		SP1_reg <= SP1_next;
+		SP2_reg <= SP2_next;
+		SP3_reg <= SP3_next;
+		
+		SF0_reg <= SF0_next;
+		SF1_reg <= SF1_next;
+		SF2_reg <= SF2_next;
+		SF3_reg <= SF3_next;
+		
+		SB_reg <= SB_next;
+		end if;
+	end process;
+	
+	-- need to register this to get same position as GTIA modes - i.e. two colour clocks after AN data received
+	process(colour_enable,SP0_reg,SP1_reg,SP2_reg,SP3_reg,SF0_reg,SF1_reg,SF2_reg,SF3_reg,SB_reg,SP0,SP1,SP2,SP3,SF0,SF1,SF2,SF3,SB)
+	begin
+		SP0_next <= SP0_reg;
+		SP1_next <= SP1_reg;
+		SP2_next <= SP2_reg;
+		SP3_next <= SP3_reg;
+		
+		SF0_next <= SF0_reg;
+		SF1_next <= SF1_reg;
+		SF2_next <= SF2_reg;
+		SF3_next <= SF3_reg;
+		
+		SB_next <= SB_reg;
+		
+		if (colour_enable = '1') then	
+			SP0_next <= SP0;
+			SP1_next <= SP1;
+			SP2_next <= SP2;
+			SP3_next <= SP3;
+			
+			SF0_next <= SF0;
+			SF1_next <= SF1;
+			SF2_next <= SF2;
+			SF3_next <= SF3;
+			
+			SB_next <= SB;	
+		end if;
+	end process;
+		
+	-- output
+	P0_OUT <= SP0_reg;
+	P1_OUT <= SP1_reg;
+	P2_OUT <= SP2_reg;
+	P3_OUT <= SP3_reg;
+	PF0_OUT <= SF0_reg;
+	PF1_OUT <= SF1_reg;
+	PF2_OUT <= SF2_reg;
+	PF3_OUT <= SF3_reg;
+	BK_OUT <= SB_reg;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/i2s_intf.vhd
===================================================================
--- unmerged/core/mist/i2s_intf.vhd	(nonexistent)
+++ unmerged/core/mist/i2s_intf.vhd	(revision 1)
@@ -0,0 +1,183 @@
+-- ZX Spectrum for Altera DE1
+--
+-- Copyright (c) 2009-2010 Mike Stirling
+-- Modified by Mark Watson for the Atari800
+--
+-- All rights reserved
+--
+-- Redistribution and use in source and synthezised forms, with or without
+-- modification, are permitted provided that the following conditions are met:
+--
+-- * Redistributions of source code must retain the above copyright notice,
+--   this list of conditions and the following disclaimer.
+--
+-- * Redistributions in synthesized form must reproduce the above copyright
+--   notice, this list of conditions and the following disclaimer in the
+--   documentation and/or other materials provided with the distribution.
+--
+-- * Neither the name of the author nor the names of other contributors may
+--   be used to endorse or promote products derived from this software without
+--   specific prior written permission.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
+-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
+-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+-- POSSIBILITY OF SUCH DAMAGE.
+--
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+entity i2s_intf is
+generic(
+   inclk_rate : positive := 25000000;
+	sample_rate : positive := 8000;
+	preamble : positive := 1; -- I2S
+	word_length : positive := 16
+	);
+
+port (
+	CLK			:	in	std_logic;
+	nRESET		:	in	std_logic;
+	
+	-- Parallel IO
+	PCM_INL		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_INR		:	out	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTL	:	in	std_logic_vector(word_length - 1 downto 0);
+	PCM_OUTR	:	in	std_logic_vector(word_length - 1 downto 0);
+	
+	-- Codec interface (right justified mode)
+	-- LRCLK is equal to the sample rate and is synchronous to
+	-- MCLK.  It must be related to MCLK by the oversampling ratio
+	-- given in the codec datasheet.
+	I2S_LRCLK	:	out	std_logic;
+	
+	-- Data is shifted out on the falling edge of BCLK, sampled
+	-- on the rising edge.  The bit rate is determined such that
+	-- it is fast enough to fit preamble + word_length bits into
+	-- each LRCLK half cycle.  The last cycle of each word may be 
+	-- stretched to fit to LRCLK.  This is OK at least for the 
+	-- WM8731 codec.
+	-- The first falling edge of each timeslot is always synchronised
+	-- with the LRCLK edge.
+	I2S_BCLK	:	out	std_logic;
+	-- Output bitstream
+	I2S_DOUT	:	out	std_logic;
+	-- Input bitstream
+	I2S_DIN		:	in	std_logic
+	);
+end i2s_intf;
+
+architecture i2s_intf_arch of i2s_intf is
+constant ratio_mclk_fs : positive := (inclk_rate / sample_rate);
+constant lrdivider_top : positive := (ratio_mclk_fs / 2) - 1;
+constant bdivider_top : positive := (ratio_mclk_fs / 8 / (preamble + word_length) * 2) - 1;
+constant nbits : positive := preamble + word_length;
+
+subtype lrdivider_t is integer range 0 to lrdivider_top;
+subtype bdivider_t is integer range 0 to bdivider_top;
+subtype bitcount_t is integer range 0 to nbits;
+
+signal lrdivider : lrdivider_t; 
+signal bdivider : bdivider_t;
+signal bitcount : bitcount_t;
+
+signal lrclk_r : std_logic;
+signal bclk_r : std_logic;
+
+-- Shift register is long enough for the number of data bits
+-- plus the preamble, plus an extra bit on the right to register
+-- the incoming data
+signal shiftreg : std_logic_vector(nbits downto 0);
+begin
+	I2S_LRCLK <= lrclk_r;
+	I2S_BCLK <= bclk_r;
+	I2S_DOUT <= shiftreg(nbits); -- data goes out MSb first
+
+	process(nRESET,CLK)
+	begin
+		if nRESET = '0' then
+			PCM_INL <= (others => '0');
+			PCM_INR <= (others => '0');
+						
+			-- Preload down-counters for clock generation
+			lrdivider <= lrdivider_top;
+			bdivider <= bdivider_top;
+			bitcount <= nbits;
+			
+			lrclk_r <= '0';
+			bclk_r <= '0';
+			shiftreg <= (others => '0');
+		elsif rising_edge(CLK) then		
+			-- Generate LRCLK at rate specified by codec configuration
+			if lrdivider = 0 then
+				-- LRCLK divider has reached 0 - start again from the top
+				lrdivider <= lrdivider_top;
+				
+				-- Generate LRCLK edge and sync the BCLK counter
+				lrclk_r <= not lrclk_r;
+				bclk_r <= '0';
+				bitcount <= nbits; -- 1 extra required for setup
+				bdivider <= bdivider_top;
+				
+				-- Load shift register with output data padding preamble
+				-- with 0s.  Load output buses with input word from the 
+				-- previous timeslot.
+				shiftreg(nbits downto nbits - preamble + 1) <= (others => '0');
+				if lrclk_r = '0' then
+					-- Previous channel input is LEFT.  This is available in the
+					-- shift register at the end of a cycle, right justified
+					PCM_INL <= shiftreg(word_length - 1 downto 0);
+					-- Next channel to output is RIGHT.  Load this into the
+					-- shift register at the start of a cycle, left justified
+					shiftreg(word_length downto 1) <= PCM_OUTR;
+				else
+					-- Previous channel input is RIGHT
+					PCM_INR <= shiftreg(word_length - 1 downto 0);
+					-- Next channel is LEFT
+					shiftreg(word_length downto 1) <= PCM_OUTL;
+				end if;
+			else
+				-- Decrement the LRCLK counter
+				lrdivider <= lrdivider - 1;
+				
+				-- Generate BCLK at a suitable rate to fit the required number
+				-- of bits into each timeslot.  Data is changed on the falling edge,
+				-- sampled on the rising edge
+				if bdivider = 0 then
+					-- If all bits have been output for this phase then
+					-- stop and wait to sync back up with LRCLK
+					if bitcount > 0 then
+						-- Reset
+						bdivider <= bdivider_top;
+						
+						-- Toggle BCLK
+						bclk_r <= not bclk_r;
+						if bclk_r = '0' then
+							-- Rising edge - shift in current bit and decrement bit counter
+							bitcount <= bitcount - 1;
+							shiftreg(0) <= I2S_DIN;
+						else
+							-- Falling edge - shift out next bit
+							shiftreg(nbits downto 1) <= shiftreg(nbits - 1 downto 0);
+						end if;
+					end if;
+				else
+					-- Decrement the BCLK counter
+					bdivider <= bdivider - 1;
+				end if;
+			end if;
+			
+		end if;
+	end process;
+end i2s_intf_arch;
+
Index: unmerged/core/mist/irq_glue.vhdl
===================================================================
--- unmerged/core/mist/irq_glue.vhdl	(nonexistent)
+++ unmerged/core/mist/irq_glue.vhdl	(revision 1)
@@ -0,0 +1,26 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY irq_glue IS
+PORT 
+( 
+	pokey_irq : in std_logic;
+	pia_irqa : in std_logic;
+	pia_irqb : in std_logic;
+	
+	combined_irq : out std_logic
+);
+end irq_glue;
+
+architecture vhdl of irq_glue is
+begin
+	combined_irq <= pokey_irq and pia_irqa and pia_irqb;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/mist_sector_buffer.vhd
===================================================================
--- unmerged/core/mist/mist_sector_buffer.vhd	(nonexistent)
+++ unmerged/core/mist/mist_sector_buffer.vhd	(revision 1)
@@ -0,0 +1,270 @@
+-- megafunction wizard: %RAM: 2-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: mist_sector_buffer.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY mist_sector_buffer IS
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END mist_sector_buffer;
+
+
+ARCHITECTURE SYN OF mist_sector_buffer IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_reg_b		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_input_b		: STRING;
+		clock_enable_output_a		: STRING;
+		clock_enable_output_b		: STRING;
+		indata_reg_b		: STRING;
+		intended_device_family		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		numwords_b		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_aclr_b		: STRING;
+		outdata_reg_a		: STRING;
+		outdata_reg_b		: STRING;
+		power_up_uninitialized		: STRING;
+		read_during_write_mode_port_a		: STRING;
+		read_during_write_mode_port_b		: STRING;
+		widthad_a		: NATURAL;
+		widthad_b		: NATURAL;
+		width_a		: NATURAL;
+		width_b		: NATURAL;
+		width_byteena_a		: NATURAL;
+		width_byteena_b		: NATURAL;
+		wrcontrol_wraddress_reg_b		: STRING
+	);
+	PORT (
+			clock0	: IN STD_LOGIC ;
+			wren_a	: IN STD_LOGIC ;
+			address_b	: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+			clock1	: IN STD_LOGIC ;
+			data_b	: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_b	: IN STD_LOGIC ;
+			address_a	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			q_b	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q_a    <= sub_wire0(7 DOWNTO 0);
+	q_b    <= sub_wire1(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_reg_b => "CLOCK1",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_input_b => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		clock_enable_output_b => "BYPASS",
+		indata_reg_b => "CLOCK1",
+		intended_device_family => "Cyclone III",
+		lpm_type => "altsyncram",
+		numwords_a => 512,
+		numwords_b => 128,
+		operation_mode => "BIDIR_DUAL_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_aclr_b => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		outdata_reg_b => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		read_during_write_mode_port_a => "NEW_DATA_NO_NBE_READ",
+		read_during_write_mode_port_b => "NEW_DATA_NO_NBE_READ",
+		widthad_a => 9,
+		widthad_b => 7,
+		width_a => 8,
+		width_b => 32,
+		width_byteena_a => 1,
+		width_byteena_b => 1,
+		wrcontrol_wraddress_reg_b => "CLOCK1"
+	)
+	PORT MAP (
+		clock0 => clock_a,
+		wren_a => wren_a,
+		address_b => address_b,
+		clock1 => clock_b,
+		data_b => data_b,
+		wren_b => wren_b,
+		address_a => address_a,
+		data_a => data_a,
+		q_a => sub_wire0,
+		q_b => sub_wire1
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRdata NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRq NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
+-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock NUMERIC "5"
+-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "4096"
+-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
+-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
+-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
+-- Retrieval info: PRIVATE: REGq NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
+-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
+-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
+-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
+-- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: VarWidth NUMERIC "1"
+-- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "32"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "8"
+-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "32"
+-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
+-- Retrieval info: PRIVATE: enable NUMERIC "0"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
+-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "512"
+-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "128"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "9"
+-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "7"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
+-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
+-- Retrieval info: USED_PORT: address_a 0 0 9 0 INPUT NODEFVAL "address_a[8..0]"
+-- Retrieval info: USED_PORT: address_b 0 0 7 0 INPUT NODEFVAL "address_b[6..0]"
+-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a"
+-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b"
+-- Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]"
+-- Retrieval info: USED_PORT: data_b 0 0 32 0 INPUT NODEFVAL "data_b[31..0]"
+-- Retrieval info: USED_PORT: q_a 0 0 8 0 OUTPUT NODEFVAL "q_a[7..0]"
+-- Retrieval info: USED_PORT: q_b 0 0 32 0 OUTPUT NODEFVAL "q_b[31..0]"
+-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a"
+-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b"
+-- Retrieval info: CONNECT: @address_a 0 0 9 0 address_a 0 0 9 0
+-- Retrieval info: CONNECT: @address_b 0 0 7 0 address_b 0 0 7 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
+-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0
+-- Retrieval info: CONNECT: @data_b 0 0 32 0 data_b 0 0 32 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
+-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
+-- Retrieval info: CONNECT: q_a 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: CONNECT: q_b 0 0 32 0 @q_b 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL mist_sector_buffer_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/pll.bsf
===================================================================
--- unmerged/core/mist/pll.bsf	(nonexistent)
+++ unmerged/core/mist/pll.bsf	(revision 1)
@@ -0,0 +1,100 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 256 184)
+	(text "pll" (rect 122 0 137 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(port
+		(pt 0 64)
+		(input)
+		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 50 29 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 40 64))
+	)
+	(port
+		(pt 256 64)
+		(output)
+		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 240 50 250 63)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 80)
+		(output)
+		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 240 66 248 79)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 96)
+		(output)
+		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 240 82 250 95)(font "Arial" (font_size 8)))
+	)
+	(port
+		(pt 256 112)
+		(output)
+		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 221 98 250 111)(font "Arial" (font_size 8)))
+	)
+	(drawing
+		(text "Cyclone III" (rect 194 168 433 347)(font "Arial" ))
+		(text "inclk0 frequency: 27.000 MHz" (rect 50 59 223 129)(font "Arial" ))
+		(text "Operation Mode: Normal" (rect 50 72 199 155)(font "Arial" ))
+		(text "Clk " (rect 51 93 116 197)(font "Arial" ))
+		(text "Ratio" (rect 72 93 164 197)(font "Arial" ))
+		(text "Ph (dg)" (rect 99 93 227 197)(font "Arial" ))
+		(text "DC (%)" (rect 133 93 296 197)(font "Arial" ))
+		(text "c0" (rect 54 107 116 225)(font "Arial" ))
+		(text "69/16" (rect 72 107 165 225)(font "Arial" ))
+		(text "0.00" (rect 105 107 226 225)(font "Arial" ))
+		(text "50.00" (rect 137 107 295 225)(font "Arial" ))
+		(text "c1" (rect 54 121 115 253)(font "Arial" ))
+		(text "69/32" (rect 72 121 165 253)(font "Arial" ))
+		(text "0.00" (rect 105 121 226 253)(font "Arial" ))
+		(text "50.00" (rect 137 121 295 253)(font "Arial" ))
+		(text "c2" (rect 54 135 116 281)(font "Arial" ))
+		(text "69/16" (rect 72 135 165 281)(font "Arial" ))
+		(text "-67.06" (rect 101 135 226 281)(font "Arial" ))
+		(text "50.00" (rect 137 135 295 281)(font "Arial" ))
+		(line (pt 0 0)(pt 257 0))
+		(line (pt 257 0)(pt 257 185))
+		(line (pt 0 185)(pt 257 185))
+		(line (pt 0 0)(pt 0 185))
+		(line (pt 48 91)(pt 165 91))
+		(line (pt 48 104)(pt 165 104))
+		(line (pt 48 118)(pt 165 118))
+		(line (pt 48 132)(pt 165 132))
+		(line (pt 48 146)(pt 165 146))
+		(line (pt 48 91)(pt 48 146))
+		(line (pt 69 91)(pt 69 146)(line_width 3))
+		(line (pt 96 91)(pt 96 146)(line_width 3))
+		(line (pt 130 91)(pt 130 146)(line_width 3))
+		(line (pt 164 91)(pt 164 146))
+		(line (pt 40 48)(pt 207 48))
+		(line (pt 207 48)(pt 207 167))
+		(line (pt 40 167)(pt 207 167))
+		(line (pt 40 48)(pt 40 167))
+		(line (pt 255 64)(pt 207 64))
+		(line (pt 255 80)(pt 207 80))
+		(line (pt 255 96)(pt 207 96))
+		(line (pt 255 112)(pt 207 112))
+	)
+)
Index: unmerged/core/mist/pll.vhd
===================================================================
--- unmerged/core/mist/pll.vhd	(nonexistent)
+++ unmerged/core/mist/pll.vhd	(revision 1)
@@ -0,0 +1,424 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 16,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 69,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 32,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 69,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 16,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 69,
+		clk2_phase_shift => "-1600",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "16"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "32"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "16"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "116.437500"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "58.218750"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "116.437500"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "69"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "69"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "57.40000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "57.50000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.60000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "32"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "16"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "69"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1600"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: unmerged/core/mist/pokey_mixer.vhdl
===================================================================
--- unmerged/core/mist/pokey_mixer.vhdl	(nonexistent)
+++ unmerged/core/mist/pokey_mixer.vhdl	(revision 1)
@@ -0,0 +1,249 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_mixer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
+		
+	CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	GTIA_SOUND : IN STD_LOGIC;
+
+	COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+	COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+	
+	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+);
+END pokey_mixer;
+
+ARCHITECTURE vhdl OF pokey_mixer IS
+	signal volume_reg : std_logic_vector(15 downto 0);
+	signal volume_next : std_logic_vector(15 downto 0);
+	signal volume_next_real : std_logic_vector(15 downto 0);	
+	
+	signal volume_sum : std_logic_vector(5 downto 0);
+	
+	signal channel_0_en : std_logic_vector(3 downto 0);
+	signal channel_1_en : std_logic_vector(3 downto 0);
+	signal channel_2_en : std_logic_vector(3 downto 0);
+	signal channel_3_en : std_logic_vector(3 downto 0);
+	
+	signal gtia_en : std_logic_vector(15 downto 0);
+BEGIN
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			volume_reg <= volume_next_real;
+		end if;
+	end process;
+	
+	-- next state
+	process(channel_enable,channel_0,channel_1,channel_2,channel_3)
+	begin
+		channel_0_en <= channel_0;
+		channel_1_en <= channel_1;
+		channel_2_en <= channel_2;
+		channel_3_en <= channel_3;
+	
+--		if (channel_enable(3)='0') then
+--			channel_0_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(2)='0') then
+--			channel_1_en <= X"0";
+--		end if;
+--
+--		if (channel_enable(1)='0') then
+--			channel_2_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(0)='0') then
+--			channel_3_en <= X"0";
+--		end if;
+	end process;
+	
+	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_en)
+	begin
+		volume_sum <= 
+			std_logic_vector
+			(
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_0_en)
+						+ unsigned('0'&CHANNEL_1_en)
+					)) 
+					+ 
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_2_en) + 
+						unsigned('0'&CHANNEL_3_en)
+					))
+			);
+	end process;
+	
+	gtia_en(15 downto 13) <= (others=>'0');
+	gtia_en(12) <= gtia_sound;
+	gtia_en(11 downto 0) <= (others=>'0');
+ 	process (volume_sum, volume_next, gtia_en, covOX_CHANNEL_0,covOX_CHANNEL_1)
+	begin
+		case volume_sum is 
+			when "000000" =>
+				volume_next <= X"0000";
+			when "000001" =>
+				volume_next <= X"05e4";
+			when "000010" =>
+				volume_next <= X"0b90";
+			when "000011" =>
+				volume_next <= X"1107";
+			when "000100" =>
+				volume_next <= X"1649";
+			when "000101" =>
+				volume_next <= X"1b57";
+			when "000110" =>
+				volume_next <= X"2032";
+			when "000111" =>
+				volume_next <= X"24db";
+			when "001000" =>
+				volume_next <= X"2954";
+			when "001001" =>
+				volume_next <= X"2d9d";
+			when "001010" =>
+				volume_next <= X"31b8";
+			when "001011" =>
+				volume_next <= X"35a6";
+			when "001100" =>
+				volume_next <= X"3968";
+			when "001101" =>
+				volume_next <= X"3cff";
+			when "001110" =>
+				volume_next <= X"406b";
+			when "001111" =>
+				volume_next <= X"43af";
+			when "010000" =>
+				volume_next <= X"46cc";
+			when "010001" =>
+				volume_next <= X"49c2";
+			when "010010" =>
+				volume_next <= X"4c92";
+			when "010011" =>
+				volume_next <= X"4f3e";
+			when "010100" =>
+				volume_next <= X"51c7";
+			when "010101" =>
+				volume_next <= X"542d";
+			when "010110" =>
+				volume_next <= X"5673";
+			when "010111" =>
+				volume_next <= X"5898";
+			when "011000" =>
+				volume_next <= X"5a9f";
+			when "011001" =>
+				volume_next <= X"5c88";
+			when "011010" =>
+				volume_next <= X"5e55";
+			when "011011" =>
+				volume_next <= X"6006";
+			when "011100" =>
+				volume_next <= X"619d";
+			when "011101" =>
+				volume_next <= X"631a";
+			when "011110" =>
+				volume_next <= X"647f";
+			when "011111" =>
+				volume_next <= X"65ce";
+			when "100000" =>
+				volume_next <= X"6706";
+			when "100001" =>
+				volume_next <= X"682a";
+			when "100010" =>
+				volume_next <= X"6939";
+			when "100011" =>
+				volume_next <= X"6a37";
+			when "100100" =>
+				volume_next <= X"6b22";
+			when "100101" =>
+				volume_next <= X"6bfe";
+			when "100110" =>
+				volume_next <= X"6cca";
+			when "100111" =>
+				volume_next <= X"6d88";
+			when "101000" =>
+				volume_next <= X"6e38";
+			when "101001" =>
+				volume_next <= X"6edd";
+			when "101010" =>
+				volume_next <= X"6f77";
+			when "101011" =>
+				volume_next <= X"7008";
+			when "101100" =>
+				volume_next <= X"708f";
+			when "101101" =>
+				volume_next <= X"710f";
+			when "101110" =>
+				volume_next <= X"7189";
+			when "101111" =>
+				volume_next <= X"71fe";
+			when "110000" =>
+				volume_next <= X"726e";
+			when "110001" =>
+				volume_next <= X"72db";
+			when "110010" =>
+				volume_next <= X"7347";
+			when "110011" =>
+				volume_next <= X"73b1";
+			when "110100" =>
+				volume_next <= X"741c";
+			when "110101" =>
+				volume_next <= X"7488";
+			when "110110" =>
+				volume_next <= X"74f6";
+			when "110111" =>
+				volume_next <= X"7568";
+			when "111000" =>
+				volume_next <= X"75df";
+			when "111001" =>
+				volume_next <= X"765c";
+			when "111010" =>
+				volume_next <= X"76df";
+			when "111011" =>
+				volume_next <= X"776b";
+			when "111100" =>
+				volume_next <= X"7800";				
+			when others =>
+				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+		end case;
+		
+--		volume_next_real <= std_LOGIC_vector(
+--			(unsigned('0'&volume_next(15 downto 1)) 
+--			+ unsigned(gtia_en)) 
+--			+ (unsigned("00"&covox_CHANNEL_0) 
+--			+ unsigned("00"&covox_CHANNEL_1)));
+		
+		--volume_next_real <= '0'&volume_next(15 downto 1);
+		
+		volume_next_real <= std_LOGIC_vector(
+			(unsigned("00"&volume_next(15 downto 2)) 
+			+ unsigned(gtia_en)) 		
+			+ (unsigned("000"&covox_CHANNEL_0&"00000") 
+			+ unsigned("000"&covox_CHANNEL_1&"00000")));
+		
+	end process;
+			
+	-- output
+	-- TODO
+	volume_out <= volume_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/pokey_ps2_decoder.vhdl.bak
===================================================================
--- unmerged/core/mist/pokey_ps2_decoder.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/pokey_ps2_decoder.vhdl.bak	(revision 1)
@@ -0,0 +1,434 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_ps2_decoder IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : std_logic;
+	-- ENABLE : IN STD_LOGIC; TODO Pokey debounce and scanning can be disabled
+	
+	-- ps2 keyboard input
+	KEY_EVENT : IN STD_LOGIC;
+	KEY_CODE : IN STD_LOGIC_VECTOR(7 downto 0);
+	KEY_EXTENDED : IN STD_LOGIC;
+	KEY_UP : IN STD_LOGIC;
+	
+	-- pokey output
+	KBCODE : OUT STD_LOGIC_VECTOR(7 downto 0);
+	KEY_HELD : OUT STD_LOGIC;
+	SHIFT_PRESSED : OUT STD_LOGIC;
+	BREAK_PRESSED : OUT STD_LOGIC;
+	KEY_INTERRUPT : OUT STD_LOGIC;
+	
+	-- other output
+	CONSOL_START : OUT STD_LOGIC;
+	CONSOL_SELECT : OUT STD_LOGIC;
+	CONSOL_OPTION : OUT STD_LOGIC;
+	
+	VIRTUAL_STICKS : out std_logic_vector(7 downto 0);
+	VIRTUAL_TRIGGER : out std_logic_vector(3 downto 0);
+	
+	SYSTEM_RESET : out std_logic
+);
+END pokey_ps2_decoder;
+
+ARCHITECTURE vhdl OF pokey_ps2_decoder IS
+	signal left_shift_pressed_reg : std_logic;
+	signal left_shift_pressed_next : std_logic;
+	signal right_shift_pressed_reg : std_logic;
+	signal right_shift_pressed_next : std_logic;	
+	
+	signal left_control_pressed_reg : std_logic;
+	signal left_control_pressed_next : std_logic;	
+	signal right_control_pressed_reg : std_logic;
+	signal right_control_pressed_next : std_logic;	
+	
+	signal kbcode_next : std_logic_vector(7 downto 0);
+	signal kbcode_reg : std_logic_vector(7 downto 0); -- XXX remove unused upper bits
+	
+	signal interrupt_next : std_logic;
+	signal interrupt_reg : std_logic;
+	
+	signal break_next : std_logic;
+	signal break_reg : std_logic;
+	
+	signal key_held_next : std_logic;
+	signal key_held_reg : std_logic;
+	
+	signal start_next : std_logic;
+	signal start_reg : std_logic;
+	signal select_next : std_logic;
+	signal select_reg : std_logic;	
+	signal option_next : std_logic;
+	signal option_reg : std_logic;
+	
+	signal virtual_up_next : std_logic;
+	signal virtual_up_reg : std_logic;
+	signal virtual_down_next : std_logic;
+	signal virtual_down_reg : std_logic;
+	signal virtual_left_next : std_logic;
+	signal virtual_left_reg : std_logic;
+	signal virtual_right_next : std_logic;
+	signal virtual_right_reg : std_logic;
+	signal virtual_stick_pressed_next : std_logic;
+	signal virtual_stick_pressed_reg : std_logic;
+	
+	signal system_reset_next : std_logic;
+	signal system_reset_reg : std_logic;	
+	
+	signal no_kbcode_update : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			left_shift_pressed_reg <= '0';
+			right_shift_pressed_reg <= '0';
+			
+			left_control_pressed_reg <= '0';
+			right_control_pressed_reg <= '0';
+			
+			kbcode_reg <= X"3F";
+			
+			interrupt_reg <= '0';
+			
+			break_reg <= '0';
+			
+			key_held_reg <= '0';
+			
+			start_reg <= '0';
+			select_reg <= '0';
+			option_reg <= '0';
+			
+			virtual_up_reg <= '0';
+			virtual_down_reg <= '0';
+			virtual_left_reg <= '0';
+			virtual_right_reg <= '0';
+			virtual_stick_pressed_reg <= '0';
+			
+			system_reset_reg <= '0';
+		elsif (clk'event and clk='1') then
+			left_shift_pressed_reg <= left_shift_pressed_next;
+			right_shift_pressed_reg <= right_shift_pressed_next;
+			
+			left_control_pressed_reg <= left_control_pressed_next;
+			right_control_pressed_reg <= right_control_pressed_next;			
+			
+			kbcode_reg <= kbcode_next;
+			
+			interrupt_reg <= interrupt_next;
+			
+			break_reg <= break_next;
+			
+			key_held_reg <= key_held_next;
+			
+			start_reg <= start_next;
+			select_reg <= select_next;
+			option_reg <= option_next;
+			
+			virtual_up_reg <= virtual_up_next;
+			virtual_down_reg <= virtual_down_next;
+			virtual_left_reg <= virtual_left_next;
+			virtual_right_reg <= virtual_right_next;
+			virtual_stick_pressed_reg <= virtual_stick_pressed_next;
+			
+			system_reset_reg <= system_reset_next;
+		end if;
+	end process;
+	
+	-- update key pressed
+	process(key_event, key_up, key_code, key_extended, left_shift_pressed_reg, right_shift_pressed_reg, left_control_pressed_reg, right_control_pressed_reg, kbcode_reg, break_reg, start_reg, select_reg, option_reg, key_held_reg, no_kbcode_update, virtual_up_reg, virtual_down_reg, virtual_left_reg, virtual_right_reg, virtual_stick_pressed_reg, system_reset_reg)
+	begin
+		left_shift_pressed_next <= left_shift_pressed_reg;
+		right_shift_pressed_next <= right_shift_pressed_reg;
+		
+		left_control_pressed_next <= left_control_pressed_reg;
+		right_control_pressed_next <= right_control_pressed_reg;		
+	
+		kbcode_next <= kbcode_reg;
+		interrupt_next <= '0';
+		
+		break_next <= break_reg;
+	
+		start_next <= start_reg;
+		select_next <= select_reg;
+		option_next <= option_reg;
+		
+		virtual_up_next <= virtual_up_reg;
+		virtual_down_next <= virtual_down_reg;
+		virtual_left_next <= virtual_left_reg;
+		virtual_right_next <= virtual_right_reg;				
+		virtual_stick_pressed_next <= virtual_stick_pressed_reg;
+		
+		system_reset_next <= system_reset_reg;
+		
+		key_held_next <= key_held_reg;
+		
+		no_kbcode_update <= '0';
+	
+		-- Core functionality exactly as the Atari layout
+		if (key_event = '1') then
+			interrupt_next <= not(key_up);			
+			key_held_next <= not(key_up);
+			
+			case key_extended&key_code is 
+			
+				-- Basic mapping - should allow all keys on Atari, just fiddly
+				when 
+					'0'&X"AA"|'1'&X"AA"|  -- BAT SUCCESSFUL
+					'0'&X"FC"|'1'&X"FC"   -- BAT FAIL
+					=>
+					no_kbcode_update <= '1';
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"4B" => --L
+					kbcode_next <= X"00";
+				when '0'&X"3B" => --J
+					kbcode_next <= X"01";					
+				when '0'&X"4C" => --;
+					kbcode_next <= X"02";										
+				when '0'&X"42" => --K
+					kbcode_next <= X"05";				
+				when '0'&X"79" => --+
+					kbcode_next <= X"06";
+				when '0'&X"7C" => --*
+					kbcode_next <= X"07";
+				when '0'&X"44" => --O
+					kbcode_next <= X"08";
+				when '0'&X"4D" => --P
+					kbcode_next <= X"0A";
+				when '0'&X"3C" => --U
+					kbcode_next <= X"0B";
+				when '0'&X"5A" => --Enter
+					kbcode_next <= X"0C";
+				when '0'&X"43" => --I
+					kbcode_next <= X"0D";
+				when '0'&X"4E" => -- -
+					kbcode_next <= X"0E";
+				when '0'&X"55" => -- =
+					kbcode_next <= X"0F";
+
+				when '0'&X"2A" => --V
+					kbcode_next <= X"10";
+				when '0'&X"05" => --Help (Using F1)
+					kbcode_next <= X"11";					
+				when '0'&X"21" => --C
+					kbcode_next <= X"12";										
+				when '0'&X"32" => --B
+					kbcode_next <= X"15";				
+				when '0'&X"22" => --X
+					kbcode_next <= X"16";
+				when '0'&X"1A" => --Z
+					kbcode_next <= X"17";
+				when '0'&X"25" => --4
+					kbcode_next <= X"18";
+				when '0'&X"26" => --3
+					kbcode_next <= X"1A";
+				when '0'&X"36" => --6
+					kbcode_next <= X"1B";
+				when '0'&X"76" => --Esc
+					kbcode_next <= X"1C";
+				when '0'&X"2E" => --5
+					kbcode_next <= X"1D";
+				when '0'&X"1E" => --2
+					kbcode_next <= X"1E";
+				when '0'&X"16" => --1
+					kbcode_next <= X"1F";
+
+				when '0'&X"41" => --,
+					kbcode_next <= X"20";
+				when '0'&X"29" => --Spc
+					kbcode_next <= X"21";					
+				when '0'&X"49" => --.
+					kbcode_next <= X"22";										
+				when '0'&X"31" => --N
+					kbcode_next <= X"23";
+				when '0'&X"3A" => --M
+					kbcode_next <= X"25";				
+				when '0'&X"4A" => --/
+					kbcode_next <= X"26";
+				when '1'&X"11" => --Inv
+					kbcode_next <= X"27";
+				when '0'&X"2D" => --R
+					kbcode_next <= X"28";
+				when '0'&X"24" => --E
+					kbcode_next <= X"2A";
+				when '0'&X"35" => --Y
+					kbcode_next <= X"2B";
+				when '0'&X"0D" => --Tab
+					kbcode_next <= X"2C";
+				when '0'&X"2C" => --T
+					kbcode_next <= X"2D";
+				when '0'&X"1D" => --W
+					kbcode_next <= X"2E";
+				when '0'&X"15" => --Q
+					kbcode_next <= X"2F";					
+					
+				when '0'&X"46" => --9
+					kbcode_next <= X"30";				
+				when '0'&X"45" => --0
+					kbcode_next <= X"32";										
+				when '0'&X"3D" => --7
+					kbcode_next <= X"33";
+				when '0'&X"66" => --Backspace
+					kbcode_next <= X"34";						
+				when '0'&X"3E" => --8
+					kbcode_next <= X"35";				
+				when '0'&X"54" => --< (using [)
+					kbcode_next <= X"36";
+				when '0'&X"5B" => --> (using ])
+					kbcode_next <= X"37";
+				when '0'&X"2B" => --F
+					kbcode_next <= X"38";
+				when '0'&X"33" => --H
+					kbcode_next <= X"39";					
+				when '0'&X"23" => --D
+					kbcode_next <= X"3A";
+				when '0'&X"58" => --Caps
+					kbcode_next <= X"3C";
+				when '0'&X"34" => --G
+					kbcode_next <= X"3D";
+				when '0'&X"1B" => --S
+					kbcode_next <= X"3E";
+				when '0'&X"1C" => --A
+					kbcode_next <= X"3F";
+
+				when '0'&X"77" => --Break - XXX BUG, also presses 14, since E1 ext code...
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+				when '1'&X"77" => --Break
+					no_kbcode_update <= '1';
+					break_next <= not(key_up);
+					key_held_next <= '0';
+					
+				-- XXX BUGS
+				-- i) press shift when already holding key - does not update kbcode
+				-- ii) press key, then press another, then release second key. Should go back to first...
+				when '0'&X"12" => --Left shift
+					no_kbcode_update <= '1';
+					left_shift_pressed_next <= not(key_UP);					
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"59" => --Right shift
+					no_kbcode_update <= '1';
+					right_shift_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+					
+				when '0'&X"14" => --Left control
+					no_kbcode_update <= '1';
+					left_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '1'&X"14" => --Right control
+					no_kbcode_update <= '1';
+					right_control_pressed_next <= not(key_UP);
+					interrupt_next <= '0';			
+					key_held_next <= '0';
+					
+				when '0'&X"06" => --Start (F2)
+					no_kbcode_update <= '1';
+					start_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"04" => --Select (F3)
+					no_kbcode_update <= '1';
+					select_next <= not(key_UP);				
+					interrupt_next <= '0';
+					key_held_next <= '0';
+				when '0'&X"0C" => --Option (F4)
+					no_kbcode_update <= '1';
+					option_next <= not(key_UP);
+					interrupt_next <= '0';					
+					key_held_next <= '0';
+
+				-- TODO will also be useful to cursor control...
+				when '1'&X"75" => -- up
+					no_kbcode_update <= '1';
+					virtual_up_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"72" => -- down
+					no_kbcode_update <= '1';
+					virtual_down_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"6b" => -- left
+					no_kbcode_update <= '1';
+					virtual_left_next <= not(key_UP);
+					interrupt_next <= '0';									
+					key_held_next <= '0';
+				when '1'&X"74" => -- right
+					no_kbcode_update <= '1';
+					virtual_right_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';
+				when '1'&X"27" => -- right windows key -> fire button
+					no_kbcode_update <= '1';
+					virtual_stick_pressed_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';					
+					
+				when '0'&X"07" => -- f12 => system reset
+					no_kbcode_update <= '1';
+					system_reset_next <= not(key_UP);
+					interrupt_next <= '0';	
+					key_held_next <= '0';										
+					
+				when others =>
+					no_kbcode_update <= '1';
+					-- nop
+				-- Idea: Use Windows key and Alt for atari shift/control. Then use keyboard ones for 'nice' mapping as displayed on keyboard?
+			end case;
+			
+			if (key_up = '1' or no_kbcode_update = '1') then
+				kbcode_next <= kbcode_reg;				
+			else
+				kbcode_next(7 downto 6) <= (left_control_pressed_reg or right_control_pressed_reg)&(left_shift_pressed_reg or right_shift_pressed_reg);
+			end if;
+		end if;
+		
+		-- Then override a few for convenience
+		-- e.g. if we press '#' on the keyboard we want to see '#' on the atari, even though on the atari its shift a different key.
+
+--http://atariwiki.de/wiki/Wiki.jsp?page=KBCODE
+-- 			$00	$01	$02	$03	$04	$05	$06	$07	$08	$09	$0A	$0B	$0C	$0D	$0E	$0F
+--		$00	L		J		;		F1		F2		K		+		*		O	 			P		U		CR		I		-		=
+--		$10	V		Help	C		F3		F4		B		X		Z		4	 			3		6		Esc	5		2		1
+--		$20	,		Spc	.		N	 			M		/		Inv	R	 			E		Y		Tab	T		W		Q
+--		$30	9	 			0		7		BS		8		<		>		F		H		D	 			Caps	G		S		A
+--together with Shift Key: add +$40
+--together with Control key: add +$80
+
+-- Would be great to have option of using real Atari keyboard, but probably not worthwhile yet.
+
+	end process;
+			
+	-- output
+	kbcode <= kbcode_reg;
+	KEY_HELD <= key_held_reg;
+	shift_pressed <= left_shift_pressed_reg or right_shift_pressed_reg;
+	break_pressed <= break_reg;
+	
+	key_interrupt <= interrupt_reg;
+	
+	consol_start <= start_reg;
+	consol_select <= select_reg;
+	consol_option <= option_reg;
+	
+	VIRTUAL_STICKS <= not(virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg&virtual_right_reg&virtual_left_reg&virtual_down_reg&virtual_up_reg);
+	VIRTUAL_TRIGGER <= "00"&not(virtual_stick_pressed_reg)&not(virtual_stick_pressed_reg);
+	
+	system_reset <= system_reset_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/ps2_keyboard.vhdl
===================================================================
--- unmerged/core/mist/ps2_keyboard.vhdl	(nonexistent)
+++ unmerged/core/mist/ps2_keyboard.vhdl	(revision 1)
@@ -0,0 +1,266 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+--	KEY_OUT : OUT STD_LOGIC_vector(7 downto 0); -- Pokey scan code
+	
+--	KEY_PRESSED : OUT STD_LOGIC; -- high for 1 cycle on new key pressed
+--	SHIFT_PRESSED : OUT STD_LOGIC; -- high while shift held
+--	CONTROL_PRESSED : OUT STD_LOGIC; -- high while control held
+--	BREAK_PRESSED : OUT STD_LOGIC -- high for 1 cycle on break key pressed (pause - no need for modifiers)
+
+ENTITY ps2_keyboard IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	PS2_CLK : IN STD_LOGIC;
+	PS2_DAT : IN STD_LOGIC;
+	
+	KEY_EVENT : OUT STD_LOGIC; -- high for 1 cycle on new key pressed(or repeated)/released
+	KEY_VALUE : OUT STD_LOGIC_VECTOR(7 downto 0); -- valid on event, raw scan code
+	KEY_EXTENDED : OUT STD_LOGIC;           -- valid on event, if scan code extended
+	KEY_UP : OUT STD_LOGIC                 -- value on event, if key released
+);
+END ps2_keyboard;
+
+ARCHITECTURE vhdl OF ps2_keyboard IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	function To_Std_Logic(L: BOOLEAN) return std_ulogic is
+	begin
+		if L then
+			return('1');
+		else
+			return('0');
+		end if;
+	end function To_Std_Logic;
+	
+	-- PS2 keyboard sends on its own clock high->low transition
+	-- start, 8 data bits, parity, stop
+	
+	-- Codes are either 1 bytes or 2 bytes (extended) on press
+	-- XX
+	-- EX YY
+	-- Codes are eighter 2 bytes or 3 bytes (extended) on release
+	-- F0 XX
+	-- EX F0 YY
+	
+	-- Some keys have multiple codes. e.g. break sends E1,14 and 77. It also sends release immediately E1 F0 14,F0 77
+	
+	-- LSB first
+	-- Start bit 0
+	-- Stop bit 1
+	-- Parity = not(data(0) xor data(1) xor data(2) xor data(3) xor data(4) xor data(5) xor data(6) xor data(7))
+	-- e.g. 
+	-- '0 1100 0010 0 1'
+	-- not(1 xor 1 xor 0 xor 0 xor 0 xor 0 xor 1 xor 0) = not(1) = 0
+	
+
+	-- Receive raw data from ps2 serial interface
+	signal ps2_shiftreg_next : std_logic_vector(10 downto 0);
+	signal ps2_shiftreg_reg : std_logic_vector(10 downto 0);
+	
+	signal idle_next : std_logic_vector(3 downto 0);
+	signal idle_reg : std_logic_vector(3 downto 0);	
+
+	signal bitcount_next : std_logic_vector(3 downto 0);
+	signal bitcount_reg : std_logic_vector(3 downto 0);	
+	
+	signal enable_ps2 : std_logic;
+	
+	signal last_ps2_clk_next : std_logic;
+	signal last_ps2_clk_reg : std_logic;
+	
+	signal ps2_clk_reg : std_logic;
+	signal ps2_dat_reg : std_logic;
+	
+	signal parity : std_logic;
+	
+	-- Once we have whole parity checked bytes
+	signal byte_next : std_logic_vector(7 downto 0);
+	signal byte_reg : std_logic_vector(7 downto 0);
+	
+	signal byte_received_next : std_logic;
+	signal byte_received_reg : std_logic;	
+	
+	-- Decode if they are press(or repeat)/release or extended
+	signal pending_extended_next : std_logic;
+	signal pending_extended_reg : std_logic;
+	
+	signal pending_keyup_next : std_logic;
+	signal pending_keyup_reg : std_logic;
+	
+	-- To eventually get the code itself
+	signal key_event_next : std_logic;
+	signal key_event_reg : std_logic;
+	
+	signal key_value_next : std_logic_vector(9 downto 0);
+	signal key_value_reg : std_logic_vector(9 downto 0);
+	
+	-- Store the last value, so I can filter repeat. I want repeat handled by Atari OS, not PS2 keyboard
+	signal key_value_last_next : std_logic_vector(9 downto 0);
+	signal key_value_last_reg : std_logic_vector(9 downto 0);
+	
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			ps2_clk_reg <= '0';
+			ps2_dat_reg <= '0';
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= '0';
+			
+			ps2_shiftreg_reg<= (others=>'0');		
+			idle_reg <= (others=>'0');
+			bitcount_reg <= (others=>'0');
+			
+			byte_received_reg <= '0';
+			byte_reg <= (others=>'0');
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= '0';
+			pending_keyup_reg <= '0';			
+
+			-- Output registers
+			key_event_reg <= '0';
+			key_value_reg <= (others=>'0');
+			
+			key_value_last_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then
+			-- Raw interface
+			-- async - do we need some form of synchronizer?
+			ps2_clk_reg <= ps2_clk;
+			ps2_dat_reg <= ps2_dat;
+			
+			-- Convert to bytes/verify
+			last_ps2_clk_reg <= last_ps2_clk_next;
+			
+			ps2_shiftreg_reg<= ps2_shiftreg_next;		
+			idle_reg <= idle_next;
+			bitcount_reg <= bitcount_next;
+			
+			byte_received_reg <= byte_received_next;
+			byte_reg <= byte_next;
+			
+			-- Handle simple byte strings (extended,byte extended,release,byte byte release,byte)
+			pending_extended_reg <= pending_extended_next;
+			pending_keyup_reg <= pending_keyup_next;			
+
+			-- Output registers
+			key_event_reg <= key_event_next;
+			key_value_reg <= key_value_next;
+			
+			key_value_last_reg <= key_value_last_next;
+			
+		end if;
+	end process;
+
+	-- Divide clock by 256 to get approx 4*ps2 clock
+	enable_div : enable_divider
+		generic map (COUNT=>256)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_ps2);
+	
+	-- capture bytes from ps2
+	parity<= not(ps2_shiftreg_reg(8) xor ps2_shiftreg_reg(7) xor ps2_shiftreg_reg(6) xor ps2_shiftreg_reg(5) xor  ps2_shiftreg_reg(4) xor ps2_shiftreg_reg(3) xor ps2_shiftreg_reg(2) xor ps2_shiftreg_reg(1));
+	process(last_ps2_clk_reg,ps2_clk_reg, ps2_dat_reg, ps2_shiftreg_reg,idle_reg,enable_ps2,bitcount_reg,parity)
+	begin	
+		ps2_shiftreg_next <= ps2_shiftreg_reg;
+		last_ps2_clk_next <= last_ps2_clk_reg;
+		
+		bitcount_next <= bitcount_reg;
+		
+		idle_next <= idle_reg;
+		
+		byte_received_next <= '0';
+		byte_next <= (others=>'0');
+		
+		if (enable_ps2 = '1') then		
+			last_ps2_clk_next <= ps2_clk_reg;
+			
+			-- sample on falling edge
+			if (ps2_clk_reg = '0' and last_ps2_clk_reg = '1') then
+				ps2_shiftreg_next <= ps2_dat_reg&ps2_shiftreg_reg(10 downto 1);
+				bitcount_next <= std_logic_vector(unsigned(bitcount_reg)+1);
+			end if;
+			
+			-- output to next stage when done
+			if (bitcount_reg = X"B") then
+				byte_received_next <= (parity xnor ps2_shiftreg_reg(9)) and not(ps2_shiftreg_reg(0)) and ps2_shiftreg_reg(10);
+				byte_next <= ps2_shiftreg_reg(8 downto 1);
+				bitcount_next <= (others=>'0');
+			end if;
+			
+			-- reset if both high for a time period
+			idle_next <= std_logic_vector(unsigned(idle_reg) +1);
+			if (idle_reg = X"F") then
+				ps2_shiftreg_next <= (others=>'0');
+				bitcount_next <= (others=>'0');
+			end if;
+			if (ps2_clk_reg = '0' or ps2_dat_reg = '0') then
+				idle_next <= X"0";
+			end if;		
+		end if;
+	end process;
+	
+	-- process bytes
+	process(byte_reg,byte_received_reg, pending_extended_reg, pending_keyup_reg, key_value_last_reg)
+	begin
+		pending_extended_next <=  pending_extended_reg;
+		pending_keyup_next <=  pending_keyup_reg;
+		
+		key_event_next <= '0';
+		key_value_next <= (others =>'0');
+		
+		key_value_last_next <= key_value_last_reg;
+		
+		if (byte_received_reg = '1') then		
+			case byte_reg is 
+				when X"E0" =>
+					pending_extended_next <= '1';					
+				when X"E1" =>
+					pending_extended_next <= '1';
+				when X"F0" =>
+					pending_keyup_next <= '1';
+				when others => 
+					pending_extended_next <= '0';
+					pending_keyup_next <= '0';	
+					
+					if (not(key_value_last_reg = pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0))) then
+						key_event_next <= '1';
+						key_value_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+						
+						key_value_last_next <= pending_keyup_reg&pending_extended_reg&byte_reg(7 downto 0);
+					end if;
+			end case;
+		end if;
+	end process;
+			
+	-- Output
+	key_event <= key_event_reg;
+	key_value <= key_value_reg(7 downto 0);
+	key_extended <= key_value_reg(8);
+	key_up <= key_value_reg(9);
+		
+END vhdl;
Index: unmerged/core/mist/ramint.vhd
===================================================================
--- unmerged/core/mist/ramint.vhd	(nonexistent)
+++ unmerged/core/mist/ramint.vhd	(revision 1)
@@ -0,0 +1,181 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: ramint.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY ramint IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END ramint;
+
+
+ARCHITECTURE SYN OF ramint IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 8192,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 13,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		data_a => data,
+		wren_a => wren,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL ramint_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/rom16.vhd
===================================================================
--- unmerged/core/mist/rom16.vhd	(nonexistent)
+++ unmerged/core/mist/rom16.vhd	(revision 1)
@@ -0,0 +1,169 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom16.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY rom16 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END rom16;
+
+
+ARCHITECTURE SYN OF rom16 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		address_aclr_a		: STRING;
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "os16.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 16384,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 14,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "os16.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "os16.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom16.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom16.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom16.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom16.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom16_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/romhi.qip
===================================================================
--- unmerged/core/mist/romhi.qip	(nonexistent)
+++ unmerged/core/mist/romhi.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "romhi.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romhi.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romhi.cmp"]
Index: unmerged/core/mist/romlo.qip
===================================================================
--- unmerged/core/mist/romlo.qip	(nonexistent)
+++ unmerged/core/mist/romlo.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "romlo.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romlo.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "romlo.cmp"]
Index: unmerged/core/mist/sdram_ctrl_4_ports.v
===================================================================
--- unmerged/core/mist/sdram_ctrl_4_ports.v	(nonexistent)
+++ unmerged/core/mist/sdram_ctrl_4_ports.v	(revision 1)
@@ -0,0 +1,561 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    	 
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b1000;
+            r_ram_ph  <= 4'b1000;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+					 //r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+                r_ref_ena <= r_ram_ph[1]; // r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            //r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+            //          | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b0_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: unmerged/core/mist/internalromram.vhd
===================================================================
--- unmerged/core/mist/internalromram.vhd	(nonexistent)
+++ unmerged/core/mist/internalromram.vhd	(revision 1)
@@ -0,0 +1,115 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY internalromram IS
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+
+	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+	ROM_REQUEST : in std_logic;
+	ROM_DATA : out std_logic_vector(7 downto 0);
+	
+	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+	RAM_WR_ENABLE : in std_logic;
+	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+	RAM_REQUEST : in std_logic;
+	RAM_DATA : out std_logic_vector(7 downto 0)
+	);
+END internalromram;
+
+architecture vhdl of internalromram is
+component ramint IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+component rom16 IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+component basic IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END component;
+
+	signal rom_request_reg : std_logic;
+	signal ram_request_reg : std_logic;
+	
+	signal ROM16_DATA : std_logic_vector(7 downto 0);
+	signal BASIC_DATA : std_logic_vector(7 downto 0);	
+	
+	signal RAM_WR_ENABLE_REAL : std_logic;
+	signal IRAM_DATA : std_logic_vector(7 downto 0);
+
+begin
+	process(clock,reset_n)
+	begin
+		if (reset_n ='0') then
+			rom_request_reg <= '0';
+			ram_request_reg <= '0';
+		elsif (clock'event and clock='1') then
+			rom_request_reg <= rom_request;
+			ram_request_reg <= ram_request;
+		end if;
+	end process;
+
+	rom_request_complete <= rom_request_reg;
+	--C000 = basic. 
+	--0000-07FF = low
+	--0800-27ff high
+	
+	process(rom16_data,basic_data, rom_addr(15 downto 0))
+	begin
+		ROM_DATA <= ROM16_DATA;
+		if (rom_addr(15)='1') then
+			ROM_DATA <= BASIC_DATA;
+		end if;
+	end process;
+	
+	
+	--ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
+	--ROM_DATA <= ROMHI_DATA;
+--	basic1 : basic
+--	PORT MAP(clock => clock,
+--			 address => rom_addr(12 downto 0),
+--			 q => BASIC_data
+--			 );			 
+--			 
+--	rom16a : rom16
+--	PORT MAP(clock => clock,
+--			 address => rom_addr(13 downto 0),
+--			 q => ROM16_data
+--			 );
+--	
+--	ramint1 : ramint
+--	PORT MAP(clock => clock,
+--			 address => ram_addr(12 downto 0),
+--			 data => ram_data_in(7 downto 0),
+--			 wren => RAM_WR_ENABLE_REAL,
+--			 q => iram_data
+--			 );	
+	ram_request_complete <= ram_request_reg;
+	
+	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
+	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/mist_sector_buffer.cmp
===================================================================
--- unmerged/core/mist/mist_sector_buffer.cmp	(nonexistent)
+++ unmerged/core/mist/mist_sector_buffer.cmp	(revision 1)
@@ -0,0 +1,30 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component mist_sector_buffer
+	PORT
+	(
+		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+		clock_a		: IN STD_LOGIC  := '1';
+		clock_b		: IN STD_LOGIC ;
+		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+		wren_a		: IN STD_LOGIC  := '0';
+		wren_b		: IN STD_LOGIC  := '0';
+		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/romhi.vhd
===================================================================
--- unmerged/core/mist/romhi.vhd	(nonexistent)
+++ unmerged/core/mist/romhi.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: romhi.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY romhi IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END romhi;
+
+
+ARCHITECTURE SYN OF romhi IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_8k.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 8192,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 13,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_8k.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "13"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_8k.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "8192"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "13"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 13 0 INPUT NODEFVAL "address[12..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 13 0 address 0 0 13 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romhi_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/romlo.vhd
===================================================================
--- unmerged/core/mist/romlo.vhd	(nonexistent)
+++ unmerged/core/mist/romlo.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: romlo.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY romlo IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END romlo;
+
+
+ARCHITECTURE SYN OF romlo IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_2k.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 2048,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 11,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_2k.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "11"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "C:/Users/Mark/Desktop/FPGA/hipatch-1.30/ossmall_2k.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 11 0 INPUT NODEFVAL "address[10..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 11 0 address 0 0 11 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL romlo_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/sdram_statemachine_mcc.vhdl
===================================================================
--- unmerged/core/mist/sdram_statemachine_mcc.vhdl	(nonexistent)
+++ unmerged/core/mist/sdram_statemachine_mcc.vhdl	(revision 1)
@@ -0,0 +1,480 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine_mcc IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine_mcc;
+
+ARCHITECTURE vhdl OF sdram_statemachine_mcc IS
+component sdram_ctrl
+port
+(
+--    //-----------------------------
+--    // Clock and reset
+--    //-----------------------------
+--    input         rst,             // Global reset
+--    input         clk,             // Master clock (72 MHz)
+--    
+--    output        ram_rdy_n,       // SDRAM ready
+--    output        ram_ref,         // SDRAM refresh
+--    output  [3:0] ram_cyc,         // SDRAM cycles
+--    output  [3:0] ram_ph,          // SDRAM phases
+--    output  [8:0] ram_ph_ctr,      // Phase counter
+    rst : in std_logic;
+	 clk : in std_logic;
+	 
+	 ram_rdy_n : out std_logic;
+	 ram_ref : out std_logic;
+	 ram_cyc : out std_logic_vector(3 downto 0);
+	 ram_ph : out std_logic_vector(3 downto 0);
+	 ram_ph_ctr : out std_logic_vector(8 downto 0);
+	
+	rden_b0 : in std_logic;
+	wren_b0 : in std_logic;
+	addr_b0 : in std_logic_vector(22 downto 2);
+	valid_b0 : out std_logic;
+	fetch_b0 : out std_logic;
+	rdata_b0 : out std_logic_vector(15 downto 0);
+	wdata_b0 : in std_logic_vector(15 downto 0);
+	bena_b0 : in std_logic_vector(1 downto 0);
+
+	rden_b1 : in std_logic;
+	wren_b1 : in std_logic;
+	addr_b1 : in std_logic_vector(22 downto 2);
+	valid_b1 : out std_logic;
+	fetch_b1 : out std_logic;
+	rdata_b1 : out std_logic_vector(15 downto 0);
+	wdata_b1 : in std_logic_vector(15 downto 0);
+	bena_b1 : in std_logic_vector(1 downto 0);
+
+	rden_b2 : in std_logic;
+	wren_b2 : in std_logic;
+	addr_b2 : in std_logic_vector(22 downto 2);
+	valid_b2 : out std_logic;
+	fetch_b2 : out std_logic;
+	rdata_b2 : out std_logic_vector(15 downto 0);
+	wdata_b2 : in std_logic_vector(15 downto 0);
+	bena_b2 : in std_logic_vector(1 downto 0);
+
+	rden_b3 : in std_logic;
+	wren_b3 : in std_logic;
+	addr_b3 : in std_logic_vector(22 downto 2);
+	valid_b3 : out std_logic;
+	fetch_b3 : out std_logic;
+	rdata_b3 : out std_logic_vector(15 downto 0);
+	wdata_b3 : in std_logic_vector(15 downto 0);
+	bena_b3 : in std_logic_vector(1 downto 0);
+	
+--    //-----------------------------
+--    // Access bank #0
+--    //-----------------------------
+--    input         rden_b0,         // Read enable
+--    input         wren_b0,         // Write enable
+--    input  [22:2] addr_b0,         // Address (up to 8 MB)
+--    output        valid_b0,        // Read data valid
+--    output        fetch_b0,        // Write data fetch
+--    output [15:0] rdata_b0,        // Read data
+--    input  [15:0] wdata_b0,        // Write data
+--    input   [1:0] bena_b0,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #1
+--    //-----------------------------
+--    input         rden_b1,         // Read enable
+--    input         wren_b1,         // Write enable
+--    input  [22:2] addr_b1,         // Address (up to 8 MB)
+--    output        valid_b1,        // Read data valid
+--    output        fetch_b1,        // Write data fetch
+--    output [15:0] rdata_b1,        // Read data
+--    input  [15:0] wdata_b1,        // Write data
+--    input   [1:0] bena_b1,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #2
+--    //-----------------------------
+--    input         rden_b2,         // Read enable
+--    input         wren_b2,         // Write enable
+--    input  [22:2] addr_b2,         // Address (up to 8 MB)
+--    output        valid_b2,        // Read data valid
+--    output        fetch_b2,        // Write data fetch
+--    output [15:0] rdata_b2,        // Read data
+--    input  [15:0] wdata_b2,        // Write data
+--    input   [1:0] bena_b2,         // Byte enable
+--    
+--    //-----------------------------
+--    // Access bank #3
+--    //-----------------------------
+--    input         rden_b3,         // Read enable
+--    input         wren_b3,         // Write enable
+--    input  [22:2] addr_b3,         // Address (up to 8 MB)
+--    output        valid_b3,        // Read data valid
+--    output        fetch_b3,        // Write data fetch
+--    output [15:0] rdata_b3,        // Read data
+--    input  [15:0] wdata_b3,        // Write data
+--    input   [1:0] bena_b3,         // Byte enable
+    
+--    //-----------------------------
+--    // SDRAM memory signals
+--    //-----------------------------
+--    output            sdram_cs_n,  // SDRAM chip select
+--    output reg        sdram_ras_n, // SDRAM row address strobe
+--    output reg        sdram_cas_n, // SDRAM column address strobe
+--    output reg        sdram_we_n,  // SDRAM write enable
+--    //
+--    output reg  [1:0] sdram_ba,    // SDRAM bank address
+--    output reg [12:0] sdram_addr,  // SDRAM address
+--    //
+--    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+--    output reg        sdram_dq_oe, // SDRAM data output enable
+--    output reg [31:0] sdram_dq_o,  // SDRAM data output
+--    input      [31:0] sdram_dq_i   // SDRAM data input
+
+	sdram_cs_n : out std_logic;
+	sdram_ras_n : out std_logic;
+	sdram_cas_n : out std_logic;
+	sdram_we_n : out std_logic;
+	sdram_ba : out std_logic_vector(1 downto 0);
+	sdram_addr : out std_logic_vector(12 downto 0);
+	sdram_dqm_n : out std_logic_vector(3 downto 0);
+	sdram_dq_oe : out std_logic;
+	sdram_dq_o : out std_logic_vector(31 downto 0);
+	sdram_dq_i : in std_logic_vector(31 downto 0)
+);
+end component;
+
+signal SDRAM_CKE_dummy : std_logic;
+
+signal sdram_valid_b0_dummy : std_logic;
+signal sdram_valid_b1_dummy : std_logic;
+signal sdram_valid_b2_dummy : std_logic;
+signal sdram_valid_b3_dummy : std_logic;
+
+signal sdram_fetch_b0_dummy : std_logic;
+signal sdram_fetch_b1_dummy : std_logic;
+signal sdram_fetch_b2_dummy : std_logic;
+signal sdram_fetch_b3_dummy : std_logic;
+
+signal sdram_read_b0_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b1_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b2_dummy : std_logic_vector(15 downto 0);
+signal sdram_read_b3_dummy : std_logic_vector(15 downto 0);
+
+signal reset : std_logic;
+
+signal sdram_ctl_rdy_dummy : std_logic;
+signal sdram_ctl_ref_dummy : std_logic;
+signal sdram_ctl_cyc_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_dummy : std_logic_vector(3 downto 0);
+signal sdram_ctl_ph_ctr_dummy : std_logic_vector(8 downto 0);
+
+signal SDRAM_VALID : std_logic;
+signal SDRAM_FETCH : std_logic;
+
+signal SDRAM_dq_oe : std_logic;
+signal sdram_dq_o : std_logic_vector(31 downto 0);
+signal sdram_dq_i : std_logic_vector(31 downto 0);
+signal sdram_dqm_N_temp : std_logic_vector(3 downto 0);
+
+signal sdram_ba : std_logic_vector(1 downto 0);
+
+signal sdram_enable_byte : std_logic_vector(1 downto 0);
+
+signal sdram_reply_reg : std_logic;
+signal state_reg : std_logic_vector(2 downto 0);
+signal store_data_in_reg : std_logic_vector(47 downto 0);
+signal data_out_reg : std_logic_vector(31 downto 0);
+signal sdram_reply_next : std_logic;
+signal state_next : std_logic_vector(2 downto 0);
+signal store_data_in_next : std_logic_vector(47 downto 0);
+signal data_out_next : std_logic_vector(31 downto 0);
+
+constant state_idle : std_logic_vector(2 downto 0) := "000";
+constant state_write_wait_1 : std_logic_vector(2 downto 0) := "001";
+constant state_write_wait_2 : std_logic_vector(2 downto 0) := "010";
+constant state_write_wait_3 : std_logic_vector(2 downto 0) := "111";
+constant state_read_wait_1 : std_logic_vector(2 downto 0) := "011";
+constant state_read_wait_2 : std_logic_vector(2 downto 0) := "100";
+constant state_read_wait_3 : std_logic_vector(2 downto 0) := "101";
+constant state_read_wait_4 : std_logic_vector(2 downto 0) := "110";
+
+
+signal internal_data_in : std_logic_vector(15 downto 0);
+signal internal_data_out : std_logic_vector(15 downto 0);
+
+signal write_en_next : std_logic;
+signal write_en_reg : std_logic;
+
+signal read_en_next : std_logic;
+signal read_en_reg : std_logic;
+
+signal SDRAM_ADDR_temp : std_logic_vector(12 downto 0);
+
+begin
+
+
+reset <= not(reset_n);
+
+process(clk_system, reset_n)
+begin
+	if (reset_n = '0') then
+		sdram_reply_reg <= '0';
+		state_reg <= state_idle;
+		store_data_in_reg <= (others=>'0');
+		data_out_reg <= (others=>'0');
+		write_en_reg <= '0';
+		read_en_reg <= '0';
+	elsif (clk_system'event and clk_system = '1') then
+		sdram_reply_reg <= sdram_reply_next;
+		state_reg <= state_next;
+		store_data_in_reg <= store_data_in_next;
+		data_out_reg <= data_out_next;
+		write_en_reg <= write_en_next;
+		read_en_reg <= read_en_next;		
+	end if;
+end process;	
+
+data_out <= data_out_reg;
+reply <= sdram_reply_reg;
+
+process(read_en_reg, write_en_reg, state_reg, request, write_en, store_data_in_reg, internal_data_in, data_in, sdram_reply_reg, byte_access, longword_access, address_in, sdram_valid, sdram_fetch)
+begin
+	sdram_reply_next <= sdram_reply_reg;
+	state_next <= state_reg;
+	store_data_in_next <= store_data_in_reg;
+	data_out_next <= (others=>'0');
+	
+	read_en_next <= read_en_reg;
+	write_en_next <= write_en_reg;
+	
+	internal_data_out <= (others=>'0');
+	sdram_enable_byte <= "11";
+
+	case state_reg is
+	when state_idle => 
+		sdram_reply_next <= '0';
+		if (request = '1') then
+			if (write_en = '1') then
+				-- 4 byte write
+				state_next <= state_write_wait_1;
+				write_en_next <= '1';
+			else
+				-- 8 byte read
+				state_next <= state_read_wait_1;
+				read_en_next <= '1';
+				-- TODO - read from cached?
+			end if;
+		end if;
+	when state_write_wait_1 =>
+		if (sdram_fetch = '1') then
+			state_next <= state_write_wait_2;
+		end if;
+		internal_data_out <= data_in(31 downto 16);
+	when state_write_wait_2 =>
+		state_next <= state_write_wait_3;
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "01";
+			when "01" =>	
+				sdram_enable_byte <= "10";				
+			when "10" =>
+				sdram_enable_byte <= "00";								
+			when "11" =>	
+				sdram_enable_byte <= "00";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(15 downto 0);
+		end if;
+		sdram_reply_next <= '1';	
+	when state_write_wait_3 =>
+		state_next <= state_idle;
+		write_en_next <= '0';		
+		if (byte_access = '1') then			
+			internal_data_out <= data_in(7 downto 0)&data_in(7 downto 0);
+			case address_in(1 downto 0) is
+			when "00" =>
+				sdram_enable_byte <= "00";
+			when "01" =>	
+				sdram_enable_byte <= "00";				
+			when "10" =>
+				sdram_enable_byte <= "01";								
+			when "11" =>	
+				sdram_enable_byte <= "10";												
+			end case;	
+		elsif (longword_access = '1') then
+			internal_data_out <= data_in(31 downto 16);
+		end if;
+		sdram_reply_next <= '0';
+	when state_read_wait_1 =>
+		if (sdram_valid = '1') then
+			state_next <= state_read_wait_2;
+			store_data_in_next(15 downto 0) <= internal_data_in;
+		end if;
+	when state_read_wait_2 =>
+		state_next <= state_read_wait_3;
+		store_data_in_next(31 downto 16) <= internal_data_in;
+	when state_read_wait_3 =>
+		state_next <= state_read_wait_4;
+		store_data_in_next(47 downto 32) <= internal_data_in;
+	when state_read_wait_4 =>
+		read_en_next <= '0';
+		state_next <= state_idle;
+		--store_data_in_next(63 downto 48) <= internal_data_in;
+		sdram_reply_next <= '1';
+		if (byte_access = '1') then
+			case address_in(2 downto 0) is
+			when "000" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(7 downto 0);
+			when "001" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(15 downto 8);
+			when "010" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(23 downto 16);
+			when "011" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(31 downto 24);
+			when "100" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(39 downto 32);
+			when "101" =>
+				data_out_next(7 downto 0) <= store_data_in_reg(47 downto 40);
+			when "110" =>
+				data_out_next(7 downto 0) <= internal_data_in(7 downto 0);
+			when "111" =>
+				data_out_next(7 downto 0) <= internal_data_in(15 downto 8);
+			end case;
+		elsif (longword_access = '1') then
+			case address_in(2 downto 0) is -- aligned only!
+			when "000" =>
+				data_out_next <= store_data_in_reg(31 downto 0);
+			when "100" =>
+				data_out_next <= internal_data_in&store_data_in_reg(47 downto 32);
+			when others =>
+				-- NOP
+			end case;		
+		end if;
+	end case;	
+end process;
+
+
+sdram_mcc : sdram_ctrl 
+	PORT map
+	(
+		rst => reset,
+		clk => clk_SYSTEM,
+		
+		ram_rdy_n => sdram_ctl_rdy_dummy,
+		ram_ref => sdram_ctl_ref_dummy,
+		ram_cyc => sdram_ctl_cyc_dummy,
+		ram_ph => sdram_ctl_ph_dummy,
+		ram_ph_ctr => sdram_ctl_ph_ctr_dummy,
+
+		 --BYTE_ACCESS : IN STD_LOGIC;
+		 --WORD_ACCESS : IN STD_LOGIC;
+		 --LONGWORD_ACCESS : IN STD_LOGIC;		
+		 
+		rden_b0 => READ_EN_reg,
+		wren_b0 => WRITE_EN_reg,
+		addr_b0 => ADDRESS_IN(22 downto 2),
+		valid_b0 => SDRAM_VALID,
+		fetch_b0 => SDRAM_FETCH,
+		rdata_b0 => INTERNAL_DATA_IN(15 downto 0),
+		wdata_b0 => INTERNAL_DATA_OUT(15 downto 0),
+		bena_b0 => sdram_enable_byte,
+
+		rden_b1 => '0',
+		wren_b1 => '0',
+		addr_b1 => (others=>'0'),
+		valid_b1 => sdram_valid_b1_dummy,
+		fetch_b1 => sdram_fetch_b1_dummy,
+		rdata_b1 => sdram_read_b1_dummy,
+		wdata_b1 => (others=>'0'),
+		bena_b1 => "00",
+
+		rden_b2 => '0',
+		wren_b2 => '0',
+		addr_b2 => (others=>'0'),
+		valid_b2 => sdram_valid_b2_dummy,
+		fetch_b2 => sdram_fetch_b2_dummy,
+		rdata_b2 => sdram_read_b2_dummy,
+		wdata_b2 => (others=>'0'),
+		bena_b2 => "00",
+
+		rden_b3 => '0',
+		wren_b3 => '0',
+		addr_b3 => (others=>'0'),
+		valid_b3 => sdram_valid_b3_dummy,
+		fetch_b3 => sdram_fetch_b3_dummy,		
+		rdata_b3 => sdram_read_b3_dummy,
+		wdata_b3 => (others=>'0'),
+		bena_b3 => "00",	
+		
+		sdram_cs_n => SDRAM_CS_N,
+		sdram_ras_n => SDRAM_RAS_N,
+		sdram_cas_n => SDRAM_CAS_N,
+		sdram_we_n => SDRAM_WE_N,
+		sdram_ba => SDRAM_BA,
+		sdram_addr => SDRAM_ADDR_temp,
+		sdram_dqm_n => sdram_dqm_N_temp,
+		sdram_dq_oe => sdram_dq_oe,
+		sdram_dq_o => sdram_dq_o,
+		sdram_dq_i => sdram_dq_i
+);
+sdram_dq <= sdram_dq_o(15 downto 0) when sdram_dq_oe='1' else (others=>'Z');
+sdram_dq_i(15 downto 0) <= sdram_dq;
+sdram_dq_i(31 downto 16) <= (others=>'0');
+SDRAM_LDQM<= sdram_dqm_N_temp(0);
+SDRAM_UDQM<= sdram_dqm_N_temp(1);
+SDRAM_BA0 <= sdram_ba(0);
+SDRAM_BA1 <= sdram_ba(1);
+
+SDRAM_ADDR(12) <= '1';
+SDRAM_ADDR(11 downto 0) <= SDRAM_ADDR_temp(11 downto 0);
+
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/spi_master.vhd
===================================================================
--- unmerged/core/mist/spi_master.vhd	(nonexistent)
+++ unmerged/core/mist/spi_master.vhd	(revision 1)
@@ -0,0 +1,172 @@
+--------------------------------------------------------------------------------
+--
+--   FileName:         spi_master.vhd
+--   Dependencies:     none
+--   Design Software:  Quartus II Version 9.0 Build 132 SJ Full Version
+--
+--   HDL CODE IS PROVIDED "AS IS."  DIGI-KEY EXPRESSLY DISCLAIMS ANY
+--   WARRANTY OF ANY KIND, WHETHER EXPRESS OR IMPLIED, INCLUDING BUT NOT
+--   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A
+--   PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL DIGI-KEY
+--   BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT OR CONSEQUENTIAL
+--   DAMAGES, LOST PROFITS OR LOST DATA, HARM TO YOUR EQUIPMENT, COST OF
+--   PROCUREMENT OF SUBSTITUTE GOODS, TECHNOLOGY OR SERVICES, ANY CLAIMS
+--   BY THIRD PARTIES (INCLUDING BUT NOT LIMITED TO ANY DEFENSE THEREOF),
+--   ANY CLAIMS FOR INDEMNITY OR CONTRIBUTION, OR OTHER SIMILAR COSTS.
+--
+--   Version History
+--   Version 1.0 7/23/2010 Scott Larson
+--     Initial Public Release
+--   Version 1.1 4/11/2013 Scott Larson
+--     Corrected ModelSim simulation error (explicitly reset clk_toggles signal)
+--    
+--------------------------------------------------------------------------------
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+USE ieee.std_logic_arith.all;
+USE ieee.std_logic_unsigned.all;
+
+ENTITY spi_master IS
+  GENERIC(
+    slaves  : INTEGER := 4;  --number of spi slaves
+    d_width : INTEGER := 2); --data bus width
+  PORT(
+    clock   : IN     STD_LOGIC;                             --system clock
+    reset_n : IN     STD_LOGIC;                             --asynchronous reset
+    enable  : IN     STD_LOGIC;                             --initiate transaction
+    cpol    : IN     STD_LOGIC;                             --spi clock polarity
+    cpha    : IN     STD_LOGIC;                             --spi clock phase
+    cont    : IN     STD_LOGIC;                             --continuous mode command
+    clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+    addr    : IN     INTEGER;                               --address of slave
+    tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+    miso    : IN     STD_LOGIC;                             --master in, slave out
+    sclk    : BUFFER STD_LOGIC;                             --spi clock
+    ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+    mosi    : OUT    STD_LOGIC;                             --master out, slave in
+    busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+    rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+END spi_master;
+
+ARCHITECTURE logic OF spi_master IS
+  TYPE machine IS(ready, execute);                           --state machine data type
+  SIGNAL state       : machine;                              --current state
+  SIGNAL slave       : INTEGER;                              --slave selected for current transaction
+  SIGNAL clk_ratio   : INTEGER;                              --current clk_div
+  SIGNAL count       : INTEGER;                              --counter to trigger sclk from system clock
+  SIGNAL clk_toggles : INTEGER RANGE 0 TO d_width*2 + 1;     --count spi clock toggles
+  SIGNAL assert_data : STD_LOGIC;                            --'1' is tx sclk toggle, '0' is rx sclk toggle
+  SIGNAL continue    : STD_LOGIC;                            --flag to continue transaction
+  SIGNAL rx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --receive data buffer
+  SIGNAL tx_buffer   : STD_LOGIC_VECTOR(d_width-1 DOWNTO 0); --transmit data buffer
+  SIGNAL last_bit_rx : INTEGER RANGE 0 TO d_width*2;         --last rx data bit location
+BEGIN
+  PROCESS(clock, reset_n)
+  BEGIN
+
+    IF(reset_n = '0') THEN        --reset system
+      busy <= '1';                --set busy signal
+      ss_n <= (OTHERS => '1');    --deassert all slave select lines
+      mosi <= 'Z';                --set master out to high impedance
+      rx_data <= (OTHERS => '0'); --clear receive data port
+      state <= ready;             --go to ready state when reset is exited
+
+    ELSIF(clock'EVENT AND clock = '1') THEN
+      CASE state IS               --state machine
+
+        WHEN ready =>
+          busy <= '0';             --clock out not busy signal
+          ss_n <= (OTHERS => '1'); --set all slave select outputs high
+          mosi <= 'Z';             --set mosi output high impedance
+          continue <= '0';         --clear continue flag
+
+          --user input to initiate transaction
+          IF(enable = '1') THEN       
+            busy <= '1';             --set busy signal
+            IF(addr < slaves) THEN   --check for valid slave address
+              slave <= addr;         --clock in current slave selection if valid
+            ELSE
+              slave <= 0;            --set to first slave if not valid
+            END IF;
+            IF(clk_div = 0) THEN     --check for valid spi speed
+              clk_ratio <= 1;        --set to maximum speed if zero
+              count <= 1;            --initiate system-to-spi clock counter
+            ELSE
+              clk_ratio <= clk_div;  --set to input selection if valid
+              count <= clk_div;      --initiate system-to-spi clock counter
+            END IF;
+            sclk <= cpol;            --set spi clock polarity
+            assert_data <= NOT cpha; --set spi clock phase
+            tx_buffer <= tx_data;    --clock in data for transmit into buffer
+            clk_toggles <= 0;        --initiate clock toggle counter
+            last_bit_rx <= d_width*2 + conv_integer(cpha) - 1; --set last rx data bit
+            state <= execute;        --proceed to execute state
+          ELSE
+            state <= ready;          --remain in ready state
+          END IF;
+
+        WHEN execute =>
+          busy <= '1';        --set busy signal
+          ss_n(slave) <= '0'; --set proper slave select output
+          
+          --system clock to sclk ratio is met
+          IF(count = clk_ratio) THEN        
+            count <= 1;                     --reset system-to-spi clock counter
+            assert_data <= NOT assert_data; --switch transmit/receive indicator
+            IF(clk_toggles = d_width*2 + 1) THEN
+              clk_toggles <= 0;               --reset spi clock toggles counter
+            ELSE
+              clk_toggles <= clk_toggles + 1; --increment spi clock toggles counter
+            END IF;
+            
+            --spi clock toggle needed
+            IF(clk_toggles <= d_width*2 AND ss_n(slave) = '0') THEN 
+              sclk <= NOT sclk; --toggle spi clock
+            END IF;
+            
+            --receive spi clock toggle
+            IF(assert_data = '0' AND clk_toggles < last_bit_rx + 1 AND ss_n(slave) = '0') THEN 
+              rx_buffer <= rx_buffer(d_width-2 DOWNTO 0) & miso; --shift in received bit
+            END IF;
+            
+            --transmit spi clock toggle
+            IF(assert_data = '1' AND clk_toggles < last_bit_rx) THEN 
+              mosi <= tx_buffer(d_width-1);                     --clock out data bit
+              tx_buffer <= tx_buffer(d_width-2 DOWNTO 0) & '0'; --shift data transmit buffer
+            END IF;
+            
+            --last data receive, but continue
+            IF(clk_toggles = last_bit_rx AND cont = '1') THEN 
+              tx_buffer <= tx_data;                       --reload transmit buffer
+              clk_toggles <= last_bit_rx - d_width*2 + 1; --reset spi clock toggle counter
+              continue <= '1';                            --set continue flag
+            END IF;
+            
+            --normal end of transaction, but continue
+            IF(continue = '1') THEN  
+              continue <= '0';      --clear continue flag
+              busy <= '0';          --clock out signal that first receive data is ready
+              rx_data <= rx_buffer; --clock out received data to output port    
+            END IF;
+            
+            --end of transaction
+            IF((clk_toggles = d_width*2 + 1) AND cont = '0') THEN   
+              busy <= '0';             --clock out not busy signal
+              ss_n <= (OTHERS => '1'); --set all slave selects high
+              mosi <= 'Z';             --set mosi output high impedance
+              rx_data <= rx_buffer;    --clock out received data to output port
+              state <= ready;          --return to ready state
+            ELSE                       --not end of transaction
+              state <= execute;        --remain in execute state
+            END IF;
+          
+          ELSE        --system clock to sclk ratio not met
+            count <= count + 1; --increment counter
+            state <= execute;   --remain in execute state
+          END IF;
+
+      END CASE;
+    END IF;
+  END PROCESS; 
+END logic;
Index: unmerged/core/mist/syncreset_enable_divider.vhd
===================================================================
--- unmerged/core/mist/syncreset_enable_divider.vhd	(nonexistent)
+++ unmerged/core/mist/syncreset_enable_divider.vhd	(revision 1)
@@ -0,0 +1,81 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY syncreset_enable_divider IS
+generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNCRESET : in std_logic;
+	RESET_N : IN STD_LOGIC;
+	ENABLE_IN : IN STD_LOGIC;
+	
+	ENABLE_OUT : OUT STD_LOGIC
+);
+END syncreset_enable_divider;
+
+ARCHITECTURE vhdl OF syncreset_enable_divider IS
+	function log2c(n : integer) return integer is
+		variable m,p : integer;
+	begin
+		m := 0;
+		p := 1;
+		while p<n loop
+			m:=m+1;
+			p:=p*2;
+		end loop;
+		return m;
+	end log2c;
+
+	constant WIDTH : natural := log2c(COUNT);
+	signal count_reg : std_logic_vector(WIDTH-1 downto 0); -- width should depend on count
+	signal count_next : std_logic_vector(WIDTH-1 downto 0);
+	
+	signal enabled_out_next : std_logic;
+	signal enabled_out_reg : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			count_reg <= (others=>'0');
+			enabled_out_reg <= '0';
+		elsif (clk'event and clk='1') then
+			count_reg <= count_next;
+			enabled_out_reg <= enabled_out_next;
+		end if;
+	end process;
+
+	-- Maintain a count in order to calculate a clock circa 1.79 (in this case 25/14) -> 64KHz -> /28
+	process(count_reg,enable_in,enabled_out_reg,syncreset)
+	begin
+		count_next <= count_reg;
+		enabled_out_next <= enabled_out_reg;
+		
+		if (enable_in = '1') then
+			count_next <= std_logic_vector(unsigned(count_reg) + 1);
+			enabled_out_next <= '0';
+		
+			if (unsigned(count_reg) = to_unsigned(COUNT-1,WIDTH)) then
+				count_next <= std_logic_vector(to_unsigned(0,WIDTH));
+				enabled_out_next <= '1';
+			end if;
+		end if;
+		
+		if (syncreset='1') then
+			count_next <= std_logic_vector(to_unsigned(resetcount,width));
+		end if;
+	end process;
+	
+	-- output
+	enable_out <= enabled_out_reg and enable_in;
+		
+END vhdl;
Index: unmerged/core/mist/sdram_ctrl_4_ports.v.bak
===================================================================
--- unmerged/core/mist/sdram_ctrl_4_ports.v.bak	(nonexistent)
+++ unmerged/core/mist/sdram_ctrl_4_ports.v.bak	(revision 1)
@@ -0,0 +1,558 @@
+`timescale 1 ns / 1 ps
+
+module sdram_ctrl /* verilator tracing_off */
+(
+    //-----------------------------
+    // Clock and reset
+    //-----------------------------
+    input         rst,             // Global reset
+    input         clk,             // Master clock (72 MHz)
+    
+    output        ram_rdy_n,       // SDRAM ready
+    output        ram_ref,         // SDRAM refresh
+    output  [3:0] ram_cyc,         // SDRAM cycles
+    output  [3:0] ram_ph,          // SDRAM phases
+    output  [8:0] ram_ph_ctr,      // Phase counter
+    
+    //-----------------------------
+    // Access bank #0
+    //-----------------------------
+    input         rden_b0,         // Read enable
+    input         wren_b0,         // Write enable
+    input  [22:2] addr_b0,         // Address (up to 8 MB)
+    output        valid_b0,        // Read data valid
+    output        fetch_b0,        // Write data fetch
+    output [15:0] rdata_b0,        // Read data
+    input  [15:0] wdata_b0,        // Write data
+    input   [1:0] bena_b0,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #1
+    //-----------------------------
+    input         rden_b1,         // Read enable
+    input         wren_b1,         // Write enable
+    input  [22:2] addr_b1,         // Address (up to 8 MB)
+    output        valid_b1,        // Read data valid
+    output        fetch_b1,        // Write data fetch
+    output [15:0] rdata_b1,        // Read data
+    input  [15:0] wdata_b1,        // Write data
+    input   [1:0] bena_b1,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #2
+    //-----------------------------
+    input         rden_b2,         // Read enable
+    input         wren_b2,         // Write enable
+    input  [22:2] addr_b2,         // Address (up to 8 MB)
+    output        valid_b2,        // Read data valid
+    output        fetch_b2,        // Write data fetch
+    output [15:0] rdata_b2,        // Read data
+    input  [15:0] wdata_b2,        // Write data
+    input   [1:0] bena_b2,         // Byte enable
+    
+    //-----------------------------
+    // Access bank #3
+    //-----------------------------
+    input         rden_b3,         // Read enable
+    input         wren_b3,         // Write enable
+    input  [22:2] addr_b3,         // Address (up to 8 MB)
+    output        valid_b3,        // Read data valid
+    output        fetch_b3,        // Write data fetch
+    output [15:0] rdata_b3,        // Read data
+    input  [15:0] wdata_b3,        // Write data
+    input   [1:0] bena_b3,         // Byte enable
+    
+    //-----------------------------
+    // SDRAM memory signals
+    //-----------------------------
+    output            sdram_cs_n,  // SDRAM chip select
+    output reg        sdram_ras_n, // SDRAM row address strobe
+    output reg        sdram_cas_n, // SDRAM column address strobe
+    output reg        sdram_we_n,  // SDRAM write enable
+    //
+    output reg  [1:0] sdram_ba,    // SDRAM bank address
+    output reg [12:0] sdram_addr,  // SDRAM address
+    //
+    output reg  [3:0] sdram_dqm_n, // SDRAM DQ masks
+    output reg        sdram_dq_oe, // SDRAM data output enable
+    output reg [31:0] sdram_dq_o,  // SDRAM data output
+    input      [31:0] sdram_dq_i   // SDRAM data input
+);
+    // SDRAM memory size (16 or 32 MB)
+    parameter SDRAM_SIZE  = 16;
+    // SDRAM memory width (16 or 32 bits)
+    parameter SDRAM_WIDTH = 16;
+    // Clock-to-output delay (for simulation)
+    parameter Tco_dly = 4.5;
+    // SDRAM commands
+    localparam [2:0]
+        CMD_LMR = 3'b000,
+        CMD_REF = 3'b001,
+        CMD_PRE = 3'b010,
+        CMD_ACT = 3'b011,
+        CMD_WR  = 3'b100,
+        CMD_RD  = 3'b101,
+        CMD_BST = 3'b110,
+        CMD_NOP = 3'b111;
+        
+    // ======================================================
+    // SDRAM sequencer control
+    // ======================================================
+    
+    reg [3:0] r_ram_cyc;
+    reg [3:0] r_ram_ph;
+    reg [1:0] r_ba0_ctr;
+    reg [1:0] r_ba1_ctr;
+    reg [8:0] r_ph_ctr;
+    reg [2:0] r_ini_ctr;
+    reg       r_ref_ena;
+    wire      w_bus_eol;
+    
+    assign w_bus_eol = r_ph_ctr[8] & r_ph_ctr[5] & r_ram_ph[3]; // 288
+    
+    always@(posedge rst or posedge clk) begin : SEQUENCER_CTRL
+        
+        if (rst) begin
+            r_ram_cyc <= 4'b0001;
+            r_ram_ph  <= 4'b0001;
+            r_ba0_ctr <= 2'd0;
+            r_ba1_ctr <= 2'd3;
+            r_ph_ctr  <= 9'd3;
+            r_ini_ctr <= 3'd0;
+            r_ref_ena <= 1'b0;
+        end
+        else begin
+            r_ram_cyc <= { r_ram_cyc[2:0], r_ram_cyc[3] };
+            if (r_ram_cyc[3]) begin
+                r_ram_ph  <= { r_ram_ph[2:0], r_ram_ph[3] };
+                r_ba0_ctr <= r_ba0_ctr + 2'd1;
+                r_ba1_ctr <= r_ba1_ctr + 2'd1;
+                // Phase counter : 3 - 288
+                if (r_ram_ph[3]) begin
+                    r_ph_ctr <= (w_bus_eol) ? 9'd3 : r_ph_ctr + 9'd1;
+                end
+                // Initialization done after 4 scanlines
+                if (w_bus_eol & r_ram_ph[3] & ~r_ini_ctr[2])
+                    r_ini_ctr <= r_ini_ctr + 3'd1;
+                // Refreshes are enabled during phase 284 - 288
+                r_ref_ena <= r_ph_ctr[8] & (r_ph_ctr[5] | &r_ph_ctr[4:2]);
+            end
+        end
+    end
+    
+    assign ram_ref    = r_ref_ena;
+    assign ram_cyc    = r_ram_cyc;
+    assign ram_ph     = r_ram_ph;
+    assign ram_ph_ctr = r_ph_ctr;
+    assign ram_rdy_n  = ~r_ini_ctr[2];
+    
+    // ======================================================
+    // SDRAM phase generation
+    // ======================================================
+    
+    reg [3:0] r_rd_act;
+    reg [3:0] r_wr_act;
+    
+    reg       r_act_ph; // Activate phase
+    reg       r_rd_ph;  // Burst read phase
+    reg       r_wr_ph;  // Burst write phase
+    reg       r_ref_ph; // Auto-refresh phase
+    reg [3:0] r_ini_ph; // Initialization phases
+    reg       r_pre_ph; // Precharge phase
+    reg       r_lmr_ph; // Load mode register phase
+    
+    always@(posedge rst or posedge clk) begin : PHASE_GEN
+    
+        if (rst) begin
+            r_rd_act <= 4'b0000;
+            r_wr_act <= 4'b0000;
+            
+            r_act_ph <= 1'b0;
+            r_rd_ph  <= 1'b0;
+            r_wr_ph  <= 1'b0;
+            r_ref_ph <= 1'b0;
+            r_ini_ph <= 4'b0000;
+            r_pre_ph <= 1'b0;
+            r_lmr_ph <= 1'b0;
+        end
+        else begin
+            if (r_ram_cyc[0]) begin
+                // Access port #0 read/write
+                if (r_ram_ph[0]) begin
+                    r_rd_act[0] <= rden_b0 & ~r_ref_ena;
+                    r_wr_act[0] <= wren_b0 & ~r_ref_ena & ~rden_b0;
+                end
+                else if (r_ram_ph[2]) begin
+                    r_rd_act[0] <= 1'b0;
+                    r_wr_act[0] <= 1'b0;
+                end
+                // Access port #1 read/write
+                if (r_ram_ph[1]) begin
+                    r_rd_act[1] <= rden_b1 & ~r_ref_ena;
+                    r_wr_act[1] <= wren_b1 & ~r_ref_ena & ~rden_b1;
+                end
+                else if (r_ram_ph[3]) begin
+                    r_rd_act[1] <= 1'b0;
+                    r_wr_act[1] <= 1'b0;
+                end
+                // Access port #2 read/write
+                if (r_ram_ph[2]) begin
+                    r_rd_act[2] <= rden_b2 & ~r_ref_ena;
+                    r_wr_act[2] <= wren_b2 & ~r_ref_ena & ~rden_b2;
+                end
+                else if (r_ram_ph[0]) begin
+                    r_rd_act[2] <= 1'b0;
+                    r_wr_act[2] <= 1'b0;
+                end
+                // Access port #3 read/write
+                if (r_ram_ph[3]) begin
+                    r_rd_act[3] <= rden_b3 & ~r_ref_ena;
+                    r_wr_act[3] <= wren_b3 & ~r_ref_ena & ~rden_b3;
+                end
+                else if (r_ram_ph[1]) begin
+                    r_rd_act[3] <= 1'b0;
+                    r_wr_act[3] <= 1'b0;
+                end
+            end
+            
+            if (r_ram_cyc[0] & r_ini_ctr[2]) begin
+                // Activate phase
+                r_act_ph <= (r_ram_ph[0] & (rden_b0 | wren_b0) & ~r_ref_ena)
+                          | (r_ram_ph[1] & (rden_b1 | wren_b1) & ~r_ref_ena)
+                          | (r_ram_ph[2] & (rden_b2 | wren_b2) & ~r_ref_ena)
+                          | (r_ram_ph[3] & (rden_b3 | wren_b3) & ~r_ref_ena);
+            end
+            
+            if (r_ram_cyc[3] & r_ini_ctr[2]) begin
+                // Read phase
+                r_rd_ph  <= (r_ram_ph[0] & r_rd_act[0])
+                          | (r_ram_ph[1] & r_rd_act[1])
+                          | (r_ram_ph[2] & r_rd_act[2])
+                          | (r_ram_ph[3] & r_rd_act[3]);
+                // Write phase
+                r_wr_ph  <= (r_ram_ph[0] & r_wr_act[0])
+                          | (r_ram_ph[1] & r_wr_act[1])
+                          | (r_ram_ph[2] & r_wr_act[2])
+                          | (r_ram_ph[3] & r_wr_act[3]);
+            end
+
+            // Initialization phases (0:PRE, 1:REF, 2:REF, 3:LMR)
+            if (r_ram_cyc[3] & r_ram_ph[2]) begin
+                if (r_ref_ena & r_ini_ctr[0] & r_ini_ctr[1]) begin
+                    r_ini_ph <= { r_ini_ph[2:0], ~|r_ini_ph };
+                end
+                else begin
+                    r_ini_ph <= 4'b0000;
+                end
+            end
+            
+            // Precharge phase
+            r_pre_ph <= r_ini_ph[0] & r_ram_ph[0];
+            
+            // Refresh phase
+            r_ref_ph <= r_ref_ena & r_ini_ctr[2] & (r_ram_ph[0] | r_ram_ph[2]) & r_ph_ctr[8] // Normal
+                      | (r_ini_ph[1] | r_ini_ph[2]) & r_ram_ph[0];                           // Init
+            
+            // Load mode register phase
+            r_lmr_ph <= r_ini_ph[3] & r_ram_ph[0];
+            
+        end
+    end
+    
+    // ======================================================
+    // SDRAM address generation
+    // ======================================================
+    
+    reg  [22:2] r_addr_mux;
+    reg  [10:2] r_addr_col;
+    reg  [12:0] r_addr_sdr;
+    reg   [1:0] r_ba_sdr;
+
+    always@(posedge rst or posedge clk) begin : ADDRESS_GEN
+    
+        if (rst) begin
+            r_addr_mux <= 21'd0;
+            r_addr_col <= 9'd0;
+            r_addr_sdr <= 13'd0;
+            r_ba_sdr   <= 2'b00;
+        end
+        else begin
+            // Port address multiplexer
+            if (r_ram_cyc[0]) begin
+                r_addr_mux <= addr_b0 & {21{r_ram_ph[0] & (rden_b0 | wren_b0) }}
+                            | addr_b1 & {21{r_ram_ph[1] & (rden_b1 | wren_b1) }}
+                            | addr_b2 & {21{r_ram_ph[2] & (rden_b2 | wren_b2) }}
+                            | addr_b3 & {21{r_ram_ph[3] & (rden_b3 | wren_b3) }};
+            end
+
+            // Column address (for read/write op.)
+            if (r_ram_cyc[3]) begin
+                r_addr_col <= r_addr_mux[10:2];
+            end
+            
+            // Memories layouts :
+            // ------------------
+            // SDRAM  4M x 32b (128 Mb) : 4 banks x 4096 rows x 256 cols x 32 bits
+            // SDRAM  8M x 32b (256 Mb) : 4 banks x 4096 rows x 512 cols x 32 bits
+            // SDRAM  8M x 16b (128 Mb) : 4 banks x 4096 rows x 512 cols x 16 bits
+            // SDRAM 16M x 16b (256 Mb) : 4 banks x 8192 rows x 512 cols x 16 bits
+    
+            // Row / col address
+            if (SDRAM_WIDTH == 32) begin
+                // 32-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000,  r_addr_col[10: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,     r_addr_mux[22:11]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010,  r_addr_col[10: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010,  r_addr_col[10: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 5'b00000, r_addr_col[ 9: 3], 1'b0 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  256 cols
+                                | { 1'b0,     r_addr_mux[21:10]       } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 5'b00100, r_addr_col[ 9: 3], 1'b1 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  256 cols
+                                | { 5'b00100, r_addr_col[ 9: 2]       } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  256 cols
+                                | { 3'b001,             10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,        10'b1_00_010_0_000 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=1, CAS=2)
+                end
+            end
+            else begin
+                // 16-bit bus
+                if (SDRAM_SIZE == 32) begin
+                    // 32 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                |            r_addr_mux[22:10]        & {13{r_act_ph & r_ram_cyc[1]}}  // 8192 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+                else begin
+                    // 16 MB
+                    r_addr_sdr <= { 4'b0000, r_addr_col[9:3], 2'b00 } & {13{r_rd_ph  & r_ram_cyc[0]}}  //  512 cols
+                                | { 1'b0,    r_addr_mux[21:10]      } & {13{r_act_ph & r_ram_cyc[1]}}  // 4096 rows
+                                | { 4'b0010, r_addr_col[9:3], 2'b10 } & {13{r_rd_ph  & r_ram_cyc[2]}}  //  512 cols
+                                | { 4'b0010, r_addr_col[9:2],  1'b0 } & {13{r_wr_ph  & r_ram_cyc[3]}}  //  512 cols
+                                | { 3'b001,           10'b000000000 } & {13{r_ini_ph[0]            }}  // Init : precharge all
+                                | { 3'b000,      10'b1_00_010_0_001 } & {13{r_ini_ph[3]            }}; // Init : load mode register (BL=2, CAS=2)
+                end
+            end
+            
+            // Bank address
+            r_ba_sdr   <= r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[0]}}  // 32-bit read
+                        | r_ba0_ctr & {2{r_act_ph & r_ram_cyc[1]}}  // Activate
+                        | r_ba1_ctr & {2{r_rd_ph  & r_ram_cyc[2]}}  // 32-bit read with auto-precharge
+                        | r_ba1_ctr & {2{r_wr_ph  & r_ram_cyc[3]}}; // 32-bit write with auto-precharge
+        end
+    end
+    
+    // ======================================================
+    // SDRAM command generation
+    // ======================================================
+    
+    reg  [2:0] r_cmd_sdr;
+        
+    always@(posedge rst or posedge clk) begin : COMMAND_GEN
+        reg [2:0] v_cmd_0;
+        reg [2:0] v_cmd_1;
+        reg [2:0] v_cmd_2;
+        reg [2:0] v_cmd_3;
+        reg [2:0] v_cmd_4;
+        reg [2:0] v_cmd_5;
+        reg [2:0] v_cmd_6;
+    
+        if (rst) begin
+            r_cmd_sdr <= CMD_NOP;
+        end
+        else begin
+            v_cmd_0 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_1 = CMD_ACT | {3{~r_act_ph}};
+            v_cmd_2 = CMD_RD  | {3{~r_rd_ph }};
+            v_cmd_3 = CMD_WR  | {3{~r_wr_ph }};
+            v_cmd_4 = CMD_PRE | {3{~r_pre_ph}};
+            v_cmd_5 = CMD_REF | {3{~r_ref_ph}};
+            v_cmd_6 = CMD_LMR | {3{~r_lmr_ph}};
+            
+            r_cmd_sdr <= (v_cmd_0 | {3{~r_ram_cyc[0]}})
+                       & (v_cmd_1 | {3{~r_ram_cyc[1]}})
+                       & (v_cmd_2 | {3{~r_ram_cyc[2]}})
+                       & (v_cmd_3 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_4 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_5 | {3{~r_ram_cyc[3]}})
+                       & (v_cmd_6 | {3{~r_ram_cyc[3]}});
+        end
+    end
+    
+    assign sdram_cs_n  = 1'b0;
+    
+    // Command and address
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_ras_n = #Tco_dly r_cmd_sdr[2];
+    always@(*) sdram_cas_n = #Tco_dly r_cmd_sdr[1];
+    always@(*) sdram_we_n  = #Tco_dly r_cmd_sdr[0];
+    always@(*) sdram_ba    = #Tco_dly r_ba_sdr;
+    always@(*) sdram_addr  = #Tco_dly r_addr_sdr;
+    /* verilator lint_on STMTDLY */
+    
+    // ======================================================
+    // Data being read
+    // ======================================================
+    
+    reg   [3:0] r_data_vld;
+    reg         r_data_sel;
+    
+    reg  [15:0] r_lrdata_p0;
+    reg  [15:0] r_hrdata_p0;
+    reg  [15:0] r_hrdata_p1;
+    wire [15:0] w_rdata_p0;
+    
+    always@(posedge rst or posedge clk) begin : DATA_READ
+        if (rst) begin
+            r_data_vld  <= 4'b0000;
+            r_data_sel  <= 1'b0;
+            r_lrdata_p0 <= 16'h0000;
+            r_hrdata_p0 <= 16'h0000;
+            r_hrdata_p1 <= 16'h0000;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_vld[0] <= r_rd_act[0] & r_ram_ph[1];
+                r_data_vld[1] <= r_rd_act[1] & r_ram_ph[2];
+                r_data_vld[2] <= r_rd_act[2] & r_ram_ph[3];
+                r_data_vld[3] <= r_rd_act[3] & r_ram_ph[0];
+            end
+            r_data_sel  <= r_ram_cyc[1] | r_ram_cyc[3];
+            r_lrdata_p0 <= sdram_dq_i[15:0];
+            r_hrdata_p0 <= sdram_dq_i[31:16];
+            r_hrdata_p1 <= r_hrdata_p0;
+        end
+    end
+    
+    // 32-bit to 16-bit multiplexer
+    assign w_rdata_p0 = (r_data_sel) ? r_hrdata_p1 : r_lrdata_p0;
+    
+    // Access Port #0
+    assign rdata_b0 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b0 = r_data_vld[0];
+    
+    // Access Port #1
+    assign rdata_b1 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b1 = r_data_vld[1];
+    
+    // Access Port #2
+    assign rdata_b2 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b2 = r_data_vld[2];
+    
+    // Access Port #3
+    assign rdata_b3 = (SDRAM_WIDTH == 32) ? w_rdata_p0 : r_lrdata_p0;
+    assign valid_b3 = r_data_vld[3];
+    
+    // ======================================================
+    // Data being written
+    // ======================================================
+    
+    reg   [3:0] r_data_fe_p0;
+    reg   [3:0] r_data_fe_p1;
+    reg         r_data_oe;
+    
+    reg  [15:0] r_wdata_p2a;
+    reg  [15:0] r_wdata_p2b;
+    reg  [31:0] r_wdata_p3;
+    
+    reg   [1:0] r_bena_p2a;
+    reg   [1:0] r_bena_p2b;
+    reg   [3:0] r_bena_p3;
+    
+    always@(posedge rst or posedge clk) begin : DATA_WRITE
+        if (rst) begin
+            r_data_fe_p0 <= 4'b0000;
+            r_data_fe_p1 <= 4'b0000;
+            r_data_oe    <= 1'b0;
+            r_wdata_p2a  <= 16'h0000;
+            r_wdata_p2b  <= 16'h0000;
+            r_wdata_p3   <= 32'h0000_0000;
+            r_bena_p2a   <= 2'b00;
+            r_bena_p2b   <= 2'b00;
+            r_bena_p3    <= 4'b00_00;
+        end
+        else begin
+            if (r_ram_cyc[3]) begin
+                r_data_fe_p0 <= r_wr_act & r_ram_ph;
+                r_data_oe    <= r_wr_ph;
+            end
+            else if (r_ram_cyc[1]) begin
+                r_data_fe_p0 <= 4'b0000;
+                r_data_oe    <= 1'b0;
+            end
+            r_data_fe_p1 <= r_data_fe_p0;
+            
+            if (SDRAM_WIDTH == 32) begin
+                // 16-bit -> 32-bit bus
+                if (r_data_sel) begin
+                    r_wdata_p2b <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2b  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                else begin
+                    r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                                 | wdata_b1 & {16{r_data_fe_p1[1]}}
+                                 | wdata_b2 & {16{r_data_fe_p1[2]}}
+                                 | wdata_b3 & {16{r_data_fe_p1[3]}};
+                    r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                                 | bena_b1 & {2{r_data_fe_p1[1]}}
+                                 | bena_b2 & {2{r_data_fe_p1[2]}}
+                                 | bena_b3 & {2{r_data_fe_p1[3]}}
+                                 | {2{~|r_data_fe_p1}};
+                end
+                r_wdata_p3  <= { r_wdata_p2b, r_wdata_p2a };
+                r_bena_p3   <= { r_bena_p2b, r_bena_p2a };
+            end
+            else begin
+                // 16-bit bus
+                r_wdata_p2a <= wdata_b0 & {16{r_data_fe_p1[0]}}
+                             | wdata_b1 & {16{r_data_fe_p1[1]}}
+                             | wdata_b2 & {16{r_data_fe_p1[2]}}
+                             | wdata_b3 & {16{r_data_fe_p1[3]}};
+                r_wdata_p2b <= r_wdata_p2a;
+                r_wdata_p3  <= { 16'h0000, r_wdata_p2b };
+                
+                r_bena_p2a  <= bena_b0 & {2{r_data_fe_p1[0]}}
+                             | bena_b1 & {2{r_data_fe_p1[1]}}
+                             | bena_b2 & {2{r_data_fe_p1[2]}}
+                             | bena_b3 & {2{r_data_fe_p1[3]}}
+                             | {2{~|r_data_fe_p1}};
+                r_bena_p2b  <= r_bena_p2a;
+                r_bena_p3   <= { 2'b00, r_bena_p2b };
+            end
+        end
+    end
+    
+    // Output mask, data & enable
+    /* verilator lint_off STMTDLY */
+    always@(*) sdram_dqm_n = #Tco_dly ~r_bena_p3;
+    always@(*) sdram_dq_o  = #Tco_dly r_wdata_p3;
+    always@(*) sdram_dq_oe = #Tco_dly r_data_oe;
+    /* verilator lint_on STMTDLY */
+    
+    // Access Port #0
+    assign fetch_b0 = r_data_fe_p0[0];
+    
+    // Access Port #1
+    assign fetch_b1 = r_data_fe_p0[1];
+    
+    // Access Port #2
+    assign fetch_b2 = r_data_fe_p0[2];
+    
+    // Access Port #3
+    assign fetch_b3 = r_data_fe_p0[3];
+    
+endmodule /* verilator tracing_on */
Index: unmerged/core/mist/sdram_statemachine_mcc.vhdl.bak
===================================================================
Index: unmerged/core/mist/os16.mif
===================================================================
--- unmerged/core/mist/os16.mif	(nonexistent)
+++ unmerged/core/mist/os16.mif	(revision 1)
@@ -0,0 +1,16395 @@
+DEPTH = 16384; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 8; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 11;
+0001 : 92;
+0002 : 10;
+0003 : 05;
+0004 : 83;
+0005 : 00;
+0006 : 42;
+0007 : 42;
+0008 : 00;
+0009 : 00;
+000a : 01;
+000b : 02;
+000c : a9;
+000d : 40;
+000e : 8d;
+000f : 0e;
+0010 : d4;
+0011 : ad;
+0012 : 13;
+0013 : d0;
+0014 : 8d;
+0015 : fa;
+0016 : 03;
+0017 : 60;
+0018 : 2c;
+0019 : 0f;
+001a : d4;
+001b : 10;
+001c : 03;
+001d : 6c;
+001e : 00;
+001f : 02;
+0020 : d8;
+0021 : 48;
+0022 : 8a;
+0023 : 48;
+0024 : 98;
+0025 : 48;
+0026 : 8d;
+0027 : 0f;
+0028 : d4;
+0029 : 6c;
+002a : 22;
+002b : 02;
+002c : d8;
+002d : 6c;
+002e : 16;
+002f : 02;
+0030 : 48;
+0031 : ad;
+0032 : 0e;
+0033 : d2;
+0034 : 29;
+0035 : 20;
+0036 : d0;
+0037 : 0d;
+0038 : a9;
+0039 : df;
+003a : 8d;
+003b : 0e;
+003c : d2;
+003d : a5;
+003e : 10;
+003f : 8d;
+0040 : 0e;
+0041 : d2;
+0042 : 6c;
+0043 : 0a;
+0044 : 02;
+0045 : 8a;
+0046 : 48;
+0047 : ad;
+0048 : ff;
+0049 : d1;
+004a : 2d;
+004b : 49;
+004c : 02;
+004d : f0;
+004e : 03;
+004f : 6c;
+0050 : 38;
+0051 : 02;
+0052 : a2;
+0053 : 06;
+0054 : bd;
+0055 : cf;
+0056 : c0;
+0057 : e0;
+0058 : 05;
+0059 : d0;
+005a : 04;
+005b : 25;
+005c : 10;
+005d : f0;
+005e : 05;
+005f : 2c;
+0060 : 0e;
+0061 : d2;
+0062 : f0;
+0063 : 06;
+0064 : ca;
+0065 : 10;
+0066 : ed;
+0067 : 4c;
+0068 : a0;
+0069 : c0;
+006a : 49;
+006b : ff;
+006c : 8d;
+006d : 0e;
+006e : d2;
+006f : a5;
+0070 : 10;
+0071 : 8d;
+0072 : 0e;
+0073 : d2;
+0074 : e0;
+0075 : 00;
+0076 : d0;
+0077 : 05;
+0078 : ad;
+0079 : 6d;
+007a : 02;
+007b : d0;
+007c : 23;
+007d : bd;
+007e : d7;
+007f : c0;
+0080 : aa;
+0081 : bd;
+0082 : 00;
+0083 : 02;
+0084 : 8d;
+0085 : 8c;
+0086 : 02;
+0087 : bd;
+0088 : 01;
+0089 : 02;
+008a : 8d;
+008b : 8d;
+008c : 02;
+008d : 68;
+008e : aa;
+008f : 6c;
+0090 : 8c;
+0091 : 02;
+0092 : a9;
+0093 : 00;
+0094 : 85;
+0095 : 11;
+0096 : 8d;
+0097 : ff;
+0098 : 02;
+0099 : 8d;
+009a : f0;
+009b : 02;
+009c : 85;
+009d : 4d;
+009e : 68;
+009f : 40;
+00a0 : 68;
+00a1 : aa;
+00a2 : 2c;
+00a3 : 02;
+00a4 : d3;
+00a5 : 10;
+00a6 : 06;
+00a7 : ad;
+00a8 : 00;
+00a9 : d3;
+00aa : 6c;
+00ab : 02;
+00ac : 02;
+00ad : 2c;
+00ae : 03;
+00af : d3;
+00b0 : 10;
+00b1 : 06;
+00b2 : ad;
+00b3 : 01;
+00b4 : d3;
+00b5 : 6c;
+00b6 : 04;
+00b7 : 02;
+00b8 : 68;
+00b9 : 8d;
+00ba : 8c;
+00bb : 02;
+00bc : 68;
+00bd : 48;
+00be : 29;
+00bf : 10;
+00c0 : f0;
+00c1 : 07;
+00c2 : ad;
+00c3 : 8c;
+00c4 : 02;
+00c5 : 48;
+00c6 : 6c;
+00c7 : 06;
+00c8 : 02;
+00c9 : ad;
+00ca : 8c;
+00cb : 02;
+00cc : 48;
+00cd : 68;
+00ce : 40;
+00cf : 80;
+00d0 : 40;
+00d1 : 04;
+00d2 : 02;
+00d3 : 01;
+00d4 : 08;
+00d5 : 10;
+00d6 : 20;
+00d7 : 36;
+00d8 : 08;
+00d9 : 14;
+00da : 12;
+00db : 10;
+00dc : 0e;
+00dd : 0c;
+00de : 0a;
+00df : 4c;
+00e0 : df;
+00e1 : c0;
+00e2 : e6;
+00e3 : 14;
+00e4 : d0;
+00e5 : 08;
+00e6 : e6;
+00e7 : 4d;
+00e8 : e6;
+00e9 : 13;
+00ea : d0;
+00eb : 02;
+00ec : e6;
+00ed : 12;
+00ee : a9;
+00ef : fe;
+00f0 : a2;
+00f1 : 00;
+00f2 : a4;
+00f3 : 4d;
+00f4 : 10;
+00f5 : 06;
+00f6 : 85;
+00f7 : 4d;
+00f8 : a6;
+00f9 : 13;
+00fa : a9;
+00fb : f6;
+00fc : 85;
+00fd : 4e;
+00fe : 86;
+00ff : 4f;
+0100 : ad;
+0101 : c5;
+0102 : 02;
+0103 : 45;
+0104 : 4f;
+0105 : 25;
+0106 : 4e;
+0107 : 8d;
+0108 : 17;
+0109 : d0;
+010a : a2;
+010b : 00;
+010c : 20;
+010d : 55;
+010e : c2;
+010f : d0;
+0110 : 03;
+0111 : 20;
+0112 : 4f;
+0113 : c2;
+0114 : a5;
+0115 : 42;
+0116 : d0;
+0117 : 08;
+0118 : ba;
+0119 : bd;
+011a : 04;
+011b : 01;
+011c : 29;
+011d : 04;
+011e : f0;
+011f : 03;
+0120 : 4c;
+0121 : 8a;
+0122 : c2;
+0123 : ad;
+0124 : 13;
+0125 : d0;
+0126 : cd;
+0127 : fa;
+0128 : 03;
+0129 : d0;
+012a : b4;
+012b : ad;
+012c : 0d;
+012d : d4;
+012e : 8d;
+012f : 35;
+0130 : 02;
+0131 : ad;
+0132 : 0c;
+0133 : d4;
+0134 : 8d;
+0135 : 34;
+0136 : 02;
+0137 : ad;
+0138 : 31;
+0139 : 02;
+013a : 8d;
+013b : 03;
+013c : d4;
+013d : ad;
+013e : 30;
+013f : 02;
+0140 : 8d;
+0141 : 02;
+0142 : d4;
+0143 : ad;
+0144 : 2f;
+0145 : 02;
+0146 : 8d;
+0147 : 00;
+0148 : d4;
+0149 : ad;
+014a : 6f;
+014b : 02;
+014c : 8d;
+014d : 1b;
+014e : d0;
+014f : ad;
+0150 : 6c;
+0151 : 02;
+0152 : f0;
+0153 : 0e;
+0154 : ce;
+0155 : 6c;
+0156 : 02;
+0157 : a9;
+0158 : 08;
+0159 : 38;
+015a : ed;
+015b : 6c;
+015c : 02;
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+3db4 : a6;
+3db5 : 3d;
+3db6 : 9d;
+3db7 : 00;
+3db8 : 04;
+3db9 : e6;
+3dba : 3d;
+3dbb : a0;
+3dbc : 01;
+3dbd : e0;
+3dbe : 7f;
+3dbf : f0;
+3dc0 : 01;
+3dc1 : 60;
+3dc2 : a9;
+3dc3 : fc;
+3dc4 : 20;
+3dc5 : 7c;
+3dc6 : fe;
+3dc7 : a9;
+3dc8 : 00;
+3dc9 : 85;
+3dca : 3d;
+3dcb : 60;
+3dcc : a0;
+3dcd : 01;
+3dce : 60;
+3dcf : ad;
+3dd0 : 89;
+3dd1 : 02;
+3dd2 : 30;
+3dd3 : 08;
+3dd4 : a0;
+3dd5 : 01;
+3dd6 : a9;
+3dd7 : 3c;
+3dd8 : 8d;
+3dd9 : 02;
+3dda : d3;
+3ddb : 60;
+3ddc : a6;
+3ddd : 3d;
+3dde : f0;
+3ddf : 0a;
+3de0 : 8e;
+3de1 : 7f;
+3de2 : 04;
+3de3 : a9;
+3de4 : fa;
+3de5 : 20;
+3de6 : 7c;
+3de7 : fe;
+3de8 : 30;
+3de9 : ec;
+3dea : a2;
+3deb : 7f;
+3dec : a9;
+3ded : 00;
+3dee : 9d;
+3def : 00;
+3df0 : 04;
+3df1 : ca;
+3df2 : 10;
+3df3 : fa;
+3df4 : a9;
+3df5 : fe;
+3df6 : 20;
+3df7 : 7c;
+3df8 : fe;
+3df9 : 4c;
+3dfa : d6;
+3dfb : fd;
+3dfc : 85;
+3dfd : 40;
+3dfe : a5;
+3dff : 14;
+3e00 : 18;
+3e01 : a6;
+3e02 : 62;
+3e03 : 7d;
+3e04 : 95;
+3e05 : fe;
+3e06 : aa;
+3e07 : a9;
+3e08 : ff;
+3e09 : 8d;
+3e0a : 1f;
+3e0b : d0;
+3e0c : a9;
+3e0d : 00;
+3e0e : a0;
+3e0f : f0;
+3e10 : 88;
+3e11 : d0;
+3e12 : fd;
+3e13 : 8d;
+3e14 : 1f;
+3e15 : d0;
+3e16 : a0;
+3e17 : f0;
+3e18 : 88;
+3e19 : d0;
+3e1a : fd;
+3e1b : e4;
+3e1c : 14;
+3e1d : d0;
+3e1e : e8;
+3e1f : c6;
+3e20 : 40;
+3e21 : f0;
+3e22 : 0e;
+3e23 : 8a;
+3e24 : 18;
+3e25 : a6;
+3e26 : 62;
+3e27 : 7d;
+3e28 : 97;
+3e29 : fe;
+3e2a : aa;
+3e2b : e4;
+3e2c : 14;
+3e2d : d0;
+3e2e : fc;
+3e2f : f0;
+3e30 : cd;
+3e31 : 20;
+3e32 : 36;
+3e33 : fe;
+3e34 : 98;
+3e35 : 60;
+3e36 : ad;
+3e37 : 25;
+3e38 : e4;
+3e39 : 48;
+3e3a : ad;
+3e3b : 24;
+3e3c : e4;
+3e3d : 48;
+3e3e : 60;
+3e3f : 8d;
+3e40 : 02;
+3e41 : 03;
+3e42 : a9;
+3e43 : 00;
+3e44 : 8d;
+3e45 : 09;
+3e46 : 03;
+3e47 : a9;
+3e48 : 83;
+3e49 : 8d;
+3e4a : 08;
+3e4b : 03;
+3e4c : a9;
+3e4d : 03;
+3e4e : 8d;
+3e4f : 05;
+3e50 : 03;
+3e51 : a9;
+3e52 : fd;
+3e53 : 8d;
+3e54 : 04;
+3e55 : 03;
+3e56 : a9;
+3e57 : 60;
+3e58 : 8d;
+3e59 : 00;
+3e5a : 03;
+3e5b : a9;
+3e5c : 00;
+3e5d : 8d;
+3e5e : 01;
+3e5f : 03;
+3e60 : a9;
+3e61 : 23;
+3e62 : 8d;
+3e63 : 06;
+3e64 : 03;
+3e65 : ad;
+3e66 : 02;
+3e67 : 03;
+3e68 : a0;
+3e69 : 40;
+3e6a : c9;
+3e6b : 52;
+3e6c : f0;
+3e6d : 02;
+3e6e : a0;
+3e6f : 80;
+3e70 : 8c;
+3e71 : 03;
+3e72 : 03;
+3e73 : a5;
+3e74 : 3e;
+3e75 : 8d;
+3e76 : 0b;
+3e77 : 03;
+3e78 : 20;
+3e79 : 59;
+3e7a : e4;
+3e7b : 60;
+3e7c : 8d;
+3e7d : ff;
+3e7e : 03;
+3e7f : a9;
+3e80 : 55;
+3e81 : 8d;
+3e82 : fd;
+3e83 : 03;
+3e84 : 8d;
+3e85 : fe;
+3e86 : 03;
+3e87 : a9;
+3e88 : 57;
+3e89 : 20;
+3e8a : 3f;
+3e8b : fe;
+3e8c : 60;
+3e8d : 04;
+3e8e : 03;
+3e8f : 80;
+3e90 : c0;
+3e91 : 02;
+3e92 : 01;
+3e93 : 40;
+3e94 : e0;
+3e95 : 1e;
+3e96 : 19;
+3e97 : 0a;
+3e98 : 08;
+3e99 : a9;
+3e9a : 1e;
+3e9b : 8d;
+3e9c : 14;
+3e9d : 03;
+3e9e : 60;
+3e9f : ea;
+3ea0 : 02;
+3ea1 : c0;
+3ea2 : 03;
+3ea3 : a9;
+3ea4 : 04;
+3ea5 : 8d;
+3ea6 : df;
+3ea7 : 02;
+3ea8 : ae;
+3ea9 : 9f;
+3eaa : fe;
+3eab : ac;
+3eac : a0;
+3ead : fe;
+3eae : a9;
+3eaf : 53;
+3eb0 : 8d;
+3eb1 : 02;
+3eb2 : 03;
+3eb3 : 8d;
+3eb4 : 0a;
+3eb5 : 03;
+3eb6 : 20;
+3eb7 : 14;
+3eb8 : ff;
+3eb9 : 20;
+3eba : 59;
+3ebb : e4;
+3ebc : 30;
+3ebd : 03;
+3ebe : 20;
+3ebf : 44;
+3ec0 : ff;
+3ec1 : 60;
+3ec2 : 20;
+3ec3 : a3;
+3ec4 : fe;
+3ec5 : a9;
+3ec6 : 00;
+3ec7 : 8d;
+3ec8 : de;
+3ec9 : 02;
+3eca : 60;
+3ecb : 48;
+3ecc : bd;
+3ecd : 41;
+3ece : 03;
+3ecf : 85;
+3ed0 : 21;
+3ed1 : 20;
+3ed2 : 4b;
+3ed3 : ff;
+3ed4 : ae;
+3ed5 : de;
+3ed6 : 02;
+3ed7 : 68;
+3ed8 : 9d;
+3ed9 : c0;
+3eda : 03;
+3edb : e8;
+3edc : ec;
+3edd : df;
+3ede : 02;
+3edf : f0;
+3ee0 : 15;
+3ee1 : 8e;
+3ee2 : de;
+3ee3 : 02;
+3ee4 : c9;
+3ee5 : 9b;
+3ee6 : f0;
+3ee7 : 03;
+3ee8 : a0;
+3ee9 : 01;
+3eea : 60;
+3eeb : a9;
+3eec : 20;
+3eed : 9d;
+3eee : c0;
+3eef : 03;
+3ef0 : e8;
+3ef1 : ec;
+3ef2 : df;
+3ef3 : 02;
+3ef4 : d0;
+3ef5 : f7;
+3ef6 : a9;
+3ef7 : 00;
+3ef8 : 8d;
+3ef9 : de;
+3efa : 02;
+3efb : ae;
+3efc : a1;
+3efd : fe;
+3efe : ac;
+3eff : a2;
+3f00 : fe;
+3f01 : 20;
+3f02 : 14;
+3f03 : ff;
+3f04 : 4c;
+3f05 : 59;
+3f06 : e4;
+3f07 : 20;
+3f08 : 4b;
+3f09 : ff;
+3f0a : a9;
+3f0b : 9b;
+3f0c : ae;
+3f0d : de;
+3f0e : 02;
+3f0f : d0;
+3f10 : dc;
+3f11 : a0;
+3f12 : 01;
+3f13 : 60;
+3f14 : 8e;
+3f15 : 04;
+3f16 : 03;
+3f17 : 8c;
+3f18 : 05;
+3f19 : 03;
+3f1a : a9;
+3f1b : 40;
+3f1c : 8d;
+3f1d : 00;
+3f1e : 03;
+3f1f : a5;
+3f20 : 21;
+3f21 : 8d;
+3f22 : 01;
+3f23 : 03;
+3f24 : a9;
+3f25 : 80;
+3f26 : ae;
+3f27 : 02;
+3f28 : 03;
+3f29 : e0;
+3f2a : 53;
+3f2b : d0;
+3f2c : 02;
+3f2d : a9;
+3f2e : 40;
+3f2f : 8d;
+3f30 : 03;
+3f31 : 03;
+3f32 : ad;
+3f33 : df;
+3f34 : 02;
+3f35 : 8d;
+3f36 : 08;
+3f37 : 03;
+3f38 : a9;
+3f39 : 00;
+3f3a : 8d;
+3f3b : 09;
+3f3c : 03;
+3f3d : ad;
+3f3e : 14;
+3f3f : 03;
+3f40 : 8d;
+3f41 : 06;
+3f42 : 03;
+3f43 : 60;
+3f44 : ad;
+3f45 : ec;
+3f46 : 02;
+3f47 : 8d;
+3f48 : 14;
+3f49 : 03;
+3f4a : 60;
+3f4b : a0;
+3f4c : 57;
+3f4d : a5;
+3f4e : 2b;
+3f4f : c9;
+3f50 : 4e;
+3f51 : d0;
+3f52 : 04;
+3f53 : a2;
+3f54 : 28;
+3f55 : d0;
+3f56 : 0e;
+3f57 : c9;
+3f58 : 44;
+3f59 : d0;
+3f5a : 04;
+3f5b : a2;
+3f5c : 14;
+3f5d : d0;
+3f5e : 06;
+3f5f : c9;
+3f60 : 53;
+3f61 : d0;
+3f62 : 0c;
+3f63 : a2;
+3f64 : 1d;
+3f65 : 8e;
+3f66 : df;
+3f67 : 02;
+3f68 : 8c;
+3f69 : 02;
+3f6a : 03;
+3f6b : 8d;
+3f6c : 0a;
+3f6d : 03;
+3f6e : 60;
+3f6f : a9;
+3f70 : 4e;
+3f71 : d0;
+3f72 : dc;
+3f73 : a2;
+3f74 : 00;
+3f75 : 86;
+3f76 : 8b;
+3f77 : 86;
+3f78 : 8c;
+3f79 : 20;
+3f7a : a9;
+3f7b : ff;
+3f7c : e0;
+3f7d : 0c;
+3f7e : d0;
+3f7f : f9;
+3f80 : ad;
+3f81 : 00;
+3f82 : c0;
+3f83 : ae;
+3f84 : 01;
+3f85 : c0;
+3f86 : c5;
+3f87 : 8b;
+3f88 : d0;
+3f89 : 06;
+3f8a : e4;
+3f8b : 8c;
+3f8c : d0;
+3f8d : 02;
+3f8e : 18;
+3f8f : 60;
+3f90 : 38;
+3f91 : 60;
+3f92 : a2;
+3f93 : 00;
+3f94 : 86;
+3f95 : 8b;
+3f96 : 86;
+3f97 : 8c;
+3f98 : a2;
+3f99 : 0c;
+3f9a : 20;
+3f9b : a9;
+3f9c : ff;
+3f9d : 20;
+3f9e : a9;
+3f9f : ff;
+3fa0 : ad;
+3fa1 : f8;
+3fa2 : ff;
+3fa3 : ae;
+3fa4 : f9;
+3fa5 : ff;
+3fa6 : 4c;
+3fa7 : 86;
+3fa8 : ff;
+3fa9 : a0;
+3faa : 00;
+3fab : bd;
+3fac : d7;
+3fad : ff;
+3fae : 99;
+3faf : 9e;
+3fb0 : 00;
+3fb1 : e8;
+3fb2 : c8;
+3fb3 : c0;
+3fb4 : 04;
+3fb5 : d0;
+3fb6 : f4;
+3fb7 : a0;
+3fb8 : 00;
+3fb9 : 18;
+3fba : b1;
+3fbb : 9e;
+3fbc : 65;
+3fbd : 8b;
+3fbe : 85;
+3fbf : 8b;
+3fc0 : 90;
+3fc1 : 02;
+3fc2 : e6;
+3fc3 : 8c;
+3fc4 : e6;
+3fc5 : 9e;
+3fc6 : d0;
+3fc7 : 02;
+3fc8 : e6;
+3fc9 : 9f;
+3fca : a5;
+3fcb : 9e;
+3fcc : c5;
+3fcd : a0;
+3fce : d0;
+3fcf : e9;
+3fd0 : a5;
+3fd1 : 9f;
+3fd2 : c5;
+3fd3 : a1;
+3fd4 : d0;
+3fd5 : e3;
+3fd6 : 60;
+3fd7 : 02;
+3fd8 : c0;
+3fd9 : 00;
+3fda : d0;
+3fdb : 00;
+3fdc : 50;
+3fdd : 00;
+3fde : 58;
+3fdf : 00;
+3fe0 : d8;
+3fe1 : 00;
+3fe2 : e0;
+3fe3 : 00;
+3fe4 : e0;
+3fe5 : f8;
+3fe6 : ff;
+3fe7 : fa;
+3fe8 : ff;
+3fe9 : 00;
+3fea : 00;
+3feb : 00;
+3fec : 00;
+3fed : 00;
+3fee : 10;
+3fef : 05;
+3ff0 : 83;
+3ff1 : 02;
+3ff2 : 42;
+3ff3 : 42;
+3ff4 : 00;
+3ff5 : 00;
+3ff6 : 01;
+3ff7 : 02;
+3ff8 : 8c;
+3ff9 : 6c;
+3ffa : 18;
+3ffb : c0;
+3ffc : aa;
+3ffd : c2;
+3ffe : 2c;
+3fff : c0;
+END; 
Index: unmerged/core/mist/sram.vhdl
===================================================================
--- unmerged/core/mist/sram.vhdl	(nonexistent)
+++ unmerged/core/mist/sram.vhdl	(revision 1)
@@ -0,0 +1,143 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY sram IS
+PORT 
+( 
+	ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+	DIN : IN STD_LOGIC_vector(15 downto 0);
+	WREN : IN STD_LOGIC;
+	
+	clk : in std_logic;
+	reset_n : in std_logic;
+	
+	request : in std_logic;
+	
+	width_16bit : in std_logic;
+	
+	-- SRAM interface
+	SRAM_ADDR: OUT STD_LOGIC_VECTOR(17 downto 0);
+	SRAM_CE_N: OUT STD_LOGIC;
+	SRAM_OE_N: OUT STD_LOGIC;
+	SRAM_WE_N: OUT STD_LOGIC;
+
+	SRAM_LB_N: OUT STD_LOGIC;
+	SRAM_UB_N: OUT STD_LOGIC;
+	
+	SRAM_DQ: INOUT STD_LOGIC_VECTOR(15 downto 0);
+	
+	-- Provide data to system
+	DOUT : OUT STD_LOGIC_VECTOR(15 downto 0);
+	complete : out std_logic
+);
+
+END sram;
+
+-- TODO, implement 32-bit accesses in two cycles
+
+-- first cycle, capture inputs
+-- second cycle, sram access
+ARCHITECTURE slow OF sram IS
+	signal oe_n_next : std_logic;
+	signal oe_n_reg : std_logic;
+	
+	signal we_n_next : std_logic;
+	signal we_n_reg : std_logic;	
+	
+	signal data_next : std_logic_vector(15 downto 0);
+	signal data_reg : std_logic_vector(15 downto 0);
+	
+	signal request_next : std_logic;
+	signal request_reg : std_logic;
+	
+	signal low_byte : std_logic_vector(7 downto 0);
+BEGIN
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			oe_n_reg <= '1';
+			we_n_reg <= '1';
+			data_reg <= (others=>'0');
+			request_reg <= '0';
+		elsif (clk'event and clk='1') then
+			oe_n_reg <= oe_n_next;
+			we_n_reg <= we_n_next;
+			data_reg <= data_next;
+			request_reg <= request_next;
+		end if;
+	end process;
+
+	-- next state
+	process(din,wren,request,request_reg,width_16bit)
+	begin		
+		data_next <= din;
+		request_next <= '0';
+		
+		oe_n_next <= '0';
+		we_n_next <= '1';
+		
+		if (width_16bit = '0') then
+			data_next <= din(7 downto 0)&din(7 downto 0);
+		end if;
+		
+		if (request = '1') then
+			-- on second cycle do write - address/data stable by now guaranteed (normal timequest...)
+			oe_n_next <= wren;
+			we_n_next <= not(wren);		
+			request_next <= '1';
+		end if;
+	end process;
+	
+	LOW_BYTE <= SRAM_DQ(7 downto 0) when address(0)='0' else SRAM_DQ(15 downto 8);
+	
+	-- output
+	SRAM_ADDR <= address(18 downto 1);
+	SRAM_CE_N <= '0';
+	SRAM_OE_N <= oe_n_reg;
+	SRAM_WE_N <= we_n_reg;
+	SRAM_LB_N <= not(width_16bit) and address(0);
+	SRAM_UB_N <= not(width_16bit) and NOT(address(0));
+	SRAM_DQ <= data_reg when we_n_reg = '0' else (others=>'Z');
+
+	DOUT <= SRAM_DQ(15 downto 8)&LOW_BYTE;
+			
+	complete <= request_reg;		
+		
+	--GPIO <= (others=>'0');
+END slow;
+
+--ARCHITECTURE fast OF sram IS
+--	signal we_n : std_logic;
+--	signal dq : std_logic_vector(7 downto 0);
+--	
+--BEGIN
+--	we_n <= not(clk) nand WREN;
+--	dq <= SRAM_DQ(7 downto 0) when address(0)='0' else
+--		SRAM_DQ(15 downto 8);
+--		
+--	-- output
+--	SRAM_ADDR <= ADDRESS(18 downto 1);
+--	--SRAM_ADDR <= ADDRESS(17 downto 0);
+--	SRAM_CE_N <= '0';
+--	SRAM_OE_N <= WREN;
+--	SRAM_WE_N <= we_n;
+--	
+--	SRAM_LB_N <= ADDRESS(0);
+--	SRAM_UB_N <= NOT(ADDRESS(0));
+--	--SRAM_LB_N <= '0';
+--	--SRAM_UB_N <= '0';
+--		
+--	DOUT <= dq;		
+--	SRAM_DQ <= DIN&DIN when wren='1' else (others=>'Z');
+--	
+--	-- immediate completion
+--	complete <= request;
+--END fast;
\ No newline at end of file
Index: unmerged/core/mist/user_io.v
===================================================================
--- unmerged/core/mist/user_io.v	(nonexistent)
+++ unmerged/core/mist/user_io.v	(revision 1)
@@ -0,0 +1,91 @@
+module user_io(
+	   input      SPI_CLK,
+	   input      SPI_SS_IO,
+	   output     reg SPI_MISO,
+	   input      SPI_MOSI,
+	   input [7:0] CORE_TYPE,
+		output [5:0] JOY0,
+		output [5:0] JOY1,
+		output [127:0] KEYBOARD,		
+		output [1:0] BUTTONS,
+		output [1:0] SWITCHES
+	   );
+
+   reg [6:0]         sbuf;
+   reg [7:0]         cmd;
+   reg [7:0] 	      cnt;
+   reg [5:0]         joystick0;
+   reg [5:0]         joystick1;
+	reg [119:0]       keyboard;
+	reg [127:0]       keyboard_out;	
+   reg [3:0] 	      but_sw;
+
+	assign JOY0 = joystick0;
+	assign JOY1 = joystick1;
+	assign KEYBOARD = keyboard_out;
+	assign BUTTONS = but_sw[1:0];
+	assign SWITCHES = but_sw[3:2];
+   
+   always@(negedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+		   SPI_MISO <= 1'bZ;
+		end else begin
+	      if(cnt < 8) begin
+			  SPI_MISO <= CORE_TYPE[7-cnt];
+			end else begin
+		     SPI_MISO <= 1'bZ;
+			end
+	   end
+	end
+		
+   always@(posedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+        cnt <= 0;
+		end else begin
+			sbuf[6:1] <= sbuf[5:0];
+			sbuf[0] <= SPI_MOSI;
+
+			cnt <= cnt + 1;
+
+	      if(cnt == 7) begin
+			   cmd[7:1] <= sbuf; 
+				cmd[0] <= SPI_MOSI;
+		   end	
+
+	      if(cnt == 15) begin
+			   if(cmd == 1) begin
+					 but_sw[3:1] <= sbuf[2:0]; 
+					 but_sw[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 2) begin
+					 joystick0[5:1] <= sbuf[4:0]; 
+					 joystick0[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 3) begin
+					 joystick1[5:1] <= sbuf[4:0]; 
+					 joystick1[0] <= SPI_MOSI; 
+				end			
+			end	
+			
+			// 15,23,31,39,47,55,63,71
+			if (cnt[2:0]==7) begin
+			   if(cmd == 5) begin
+					if (!cnt[7]) begin
+					 keyboard[111:0] <= keyboard[119:8];
+					 keyboard[119:113] <= sbuf[6:0]; 
+					 keyboard[112] <= SPI_MOSI; 
+					end
+					if (cnt[7]) begin
+					 keyboard_out[119:0] <= keyboard[119:0];
+					 keyboard_out[127:121] <= sbuf[6:0]; 
+					 keyboard_out[120] <= SPI_MOSI; 					
+					end
+				end
+			end
+		end
+   end		
+//   always@(posedge clk2) begin
+//      LED <= ~LED;
+//   end
+   
+endmodule
Index: unmerged/core/mist/zpu/Makefile
===================================================================
--- unmerged/core/mist/zpu/Makefile	(nonexistent)
+++ unmerged/core/mist/zpu/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c mmc.c    spi.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/core/mist/zpu/diskio.h
===================================================================
--- unmerged/core/mist/zpu/diskio.h	(nonexistent)
+++ unmerged/core/mist/zpu/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/core/mist/zpu/main.c
===================================================================
--- unmerged/core/mist/zpu/main.c	(nonexistent)
+++ unmerged/core/mist/zpu/main.c	(revision 1)
@@ -0,0 +1,1166 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (reset_n == 1)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<7;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (pause == 0)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<6;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+
+	if ((1&*zpu_key) == 1)
+	{
+		// stop 6502
+		pause_6502(1);
+
+		// write a display list in page 6 (TODO, backup first...)
+		*((volatile unsigned char *)(0x600 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x601 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x602 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x603 + 0x10000)) = 0x42;
+		*((volatile unsigned char *)(0x604 + 0x10000)) = 0x40;
+		*((volatile unsigned char *)(0x605 + 0x10000)) = 0x06;
+		*((volatile unsigned char *)(0x606 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x607 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x608 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x609 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60a + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60b + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60c + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60d + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60e + 0x10000)) = 0x41;
+		*((volatile unsigned char *)(0x60f + 0x10000)) = 0x00;
+		*((volatile unsigned char *)(0x610 + 0x10000)) = 0x06;
+
+		*((volatile unsigned char *)(0x640 + 0x10000)) = 'H';
+		*((volatile unsigned char *)(0x641 + 0x10000)) = 'E';
+		*((volatile unsigned char *)(0x642 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x643 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x644 + 0x10000)) = 'O';
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+
+		// wait 10 seconds
+		for (i=0; i!=10000; ++i)
+		{
+			*atari_colbk = *atari_random;
+			wait_us(1000);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		int fileno;
+		int skip;
+		int plotted = 0;
+		unsigned char volatile * mem;
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		for (;;)
+		{
+			int i = 0;
+			int go = 0;
+			fileno = 0;
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			if (FR_OK != pf_opendir(&dir,"/"))
+			{
+				debug("opendir failed\n");
+				while(1);
+			}
+
+			plotted = 0;
+			skip = 0;
+			if (selfileno>20)
+			{
+				skip = selfileno-20;
+				skip&=0xfffffffe;
+			}
+			if (selfileno<0)
+			{
+				selfileno = 0;
+			}
+			while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+			{
+				if (filinfo.fattrib & AM_SYS)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_HID)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_DIR)
+				{
+					debug("DIR ");
+				}
+				if (selfileno == fileno)
+				{
+					for (i=0;i!=256;++i)
+					{
+						atari_sector_buffer[i] = filinfo.fname[i];
+						if (0==filinfo.fname[i]) break;
+						filinfo.fname[i]+=128;
+					}
+				}
+				if (--skip<0)
+				{
+					debug(filinfo.fname);
+					++plotted;
+					if (plotted&1)
+					{
+						setxpos(20);
+					}
+					else
+					{
+						debug("\n");
+					}
+					if (plotted==40)
+					{
+						break;
+					}
+				}
+				fileno++;
+			}
+			debug("\n");
+			setypos(21);
+			openfile(atari_sector_buffer);
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					selfileno+=2;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					selfileno-=2;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					selfileno|=1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					selfileno&=0xfffffffe;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+			if (go == 1)
+			{
+				debug("Booting...");
+				wait_us(500000);
+
+				// reset process
+				reset_6502(0);
+				*atari_nmien = 0x00;
+				clear_64k_ram();
+				reset_6502(1);
+				break;
+			}
+			wait_us(80000);
+		}
+		initdebug(debugmode);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	speed = speedslow;
+	if (2==(2&(*zpu_switches)))
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+
+		wait_us(2000000);
+	}
+
+	if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	do
+	{
+		mmcInit();
+	}
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	openfile("BOOT.ATR");
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId == 0x31)
+ 	 	{
+			int sent = 0;
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/core/mist/zpu/mycrt0.s
===================================================================
--- unmerged/core/mist/zpu/mycrt0.s	(nonexistent)
+++ unmerged/core/mist/zpu/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/core/mist/zpu/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/core/mist/zpu/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/core/mist/zpu/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,3853 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b80ef;
+00a2 : 98738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
+00a9 : ff040000;
+00aa : 00000000;
+00ab : 00000000;
+00ac : 00000000;
+00ad : 00000000;
+00ae : 00000000;
+00af : 00000000;
+00b0 : 0b0b0b88;
+00b1 : d8040000;
+00b2 : 00000000;
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+0dda : 54087170;
+0ddb : 8405530c;
+0ddc : f0125271;
+0ddd : 8f26c938;
+0dde : 83722795;
+0ddf : 38727084;
+0de0 : 05540871;
+0de1 : 70840553;
+0de2 : 0cfc1252;
+0de3 : 718326ed;
+0de4 : 387054ff;
+0de5 : 81390000;
+0de6 : 00ffffff;
+0de7 : ff00ffff;
+0de8 : ffff00ff;
+0de9 : ffffff00;
+0dea : 70707042;
+0deb : 409c0202;
+0dec : 02020202;
+0ded : 02020202;
+0dee : 02020202;
+0def : 02020202;
+0df0 : 02020202;
+0df1 : 02704100;
+0df2 : 9c000000;
+0df3 : 0000175d;
+0df4 : 00001754;
+0df5 : 0000174b;
+0df6 : 00001742;
+0df7 : 00001739;
+0df8 : 00001730;
+0df9 : 00001727;
+0dfa : 000011b0;
+0dfb : 2f000000;
+0dfc : 4f70656e;
+0dfd : 696e673a;
+0dfe : 00000000;
+0dff : 6661696c;
+0e00 : 0a000000;
+0e01 : 6f6b0a00;
+0e02 : 436f756c;
+0e03 : 64206e6f;
+0e04 : 74207265;
+0e05 : 61642068;
+0e06 : 65616465;
+0e07 : 720a0000;
+0e08 : 556e6b6e;
+0e09 : 6f776e20;
+0e0a : 66696c65;
+0e0b : 20747970;
+0e0c : 65000000;
+0e0d : 41545220;
+0e0e : 00000000;
+0e0f : 58442000;
+0e10 : 300a0000;
+0e11 : 58464420;
+0e12 : 00000000;
+0e13 : 42414420;
+0e14 : 73656374;
+0e15 : 6f722073;
+0e16 : 697a6500;
+0e17 : 4d442000;
+0e18 : 58455820;
+0e19 : 00000000;
+0e1a : 53442000;
+0e1b : 44442000;
+0e1c : 44495220;
+0e1d : 00000000;
+0e1e : 6f70656e;
+0e1f : 64697220;
+0e20 : 6661696c;
+0e21 : 65640a00;
+0e22 : 426f6f74;
+0e23 : 696e672e;
+0e24 : 2e2e0000;
+0e25 : 53797374;
+0e26 : 656d2073;
+0e27 : 65747469;
+0e28 : 6e67730a;
+0e29 : 00000000;
+0e2a : 2d2d2d2d;
+0e2b : 2d2d2d2d;
+0e2c : 2d2d2d2d;
+0e2d : 2d2d2d0a;
+0e2e : 00000000;
+0e2f : 4d656d6f;
+0e30 : 72793a00;
+0e31 : 344d4221;
+0e32 : 00000000;
+0e33 : 524f4d20;
+0e34 : 62616e6b;
+0e35 : 3a000000;
+0e36 : 556e6b6e;
+0e37 : 6f776e00;
+0e38 : 53706565;
+0e39 : 643a0000;
+0e3a : 204b487a;
+0e3b : 0a44313a;
+0e3c : 00000000;
+0e3d : 0a44323a;
+0e3e : 00000000;
+0e3f : 0a44333a;
+0e40 : 00000000;
+0e41 : 0a44343a;
+0e42 : 00000000;
+0e43 : 0a526562;
+0e44 : 6f6f7400;
+0e45 : 0a457869;
+0e46 : 74000000;
+0e47 : 34202864;
+0e48 : 65666175;
+0e49 : 6c743a4f;
+0e4a : 53204220;
+0e4b : 2b206869;
+0e4c : 20737065;
+0e4d : 65642900;
+0e4e : 32202864;
+0e4f : 65666175;
+0e50 : 6c743a58;
+0e51 : 4c202b20;
+0e52 : 68692073;
+0e53 : 70656564;
+0e54 : 29000000;
+0e55 : 31202864;
+0e56 : 65666175;
+0e57 : 6c743a58;
+0e58 : 4c290000;
+0e59 : 33202864;
+0e5a : 65666175;
+0e5b : 6c743a55;
+0e5c : 6c74696d;
+0e5d : 6f6e2900;
+0e5e : 31303838;
+0e5f : 4b694220;
+0e60 : 52616d62;
+0e61 : 6f000000;
+0e62 : 3537364b;
+0e63 : 69422052;
+0e64 : 616d626f;
+0e65 : 00000000;
+0e66 : 3537364b;
+0e67 : 69422043;
+0e68 : 6f6d7079;
+0e69 : 2053686f;
+0e6a : 70000000;
+0e6b : 3332304b;
+0e6c : 69422052;
+0e6d : 616d626f;
+0e6e : 00000000;
+0e6f : 3332304b;
+0e70 : 69422043;
+0e71 : 6f6d7079;
+0e72 : 2053686f;
+0e73 : 70000000;
+0e74 : 3132384b;
+0e75 : 69420000;
+0e76 : 36344b69;
+0e77 : 42000000;
+0e78 : 636d643a;
+0e79 : 00000000;
+0e7a : 45525220;
+0e7b : 00000000;
+0e7c : 53504453;
+0e7d : 00000000;
+0e7e : 53504446;
+0e7f : 00000000;
+0e80 : 2873656e;
+0e81 : 643a0000;
+0e82 : 3a63686b;
+0e83 : 3a000000;
+0e84 : 73646361;
+0e85 : 72640a00;
+0e86 : 6469736b;
+0e87 : 5f696e69;
+0e88 : 743a0000;
+0e89 : 6d6f756e;
+0e8a : 743a0000;
+0e8b : 6f70656e;
+0e8c : 6469723a;
+0e8d : 00000000;
+0e8e : 424f4f54;
+0e8f : 2e415452;
+0e90 : 00000000;
+0e91 : 61746172;
+0e92 : 69726f6d;
+0e93 : 2e62696e;
+0e94 : 00000000;
+0e95 : 53746174;
+0e96 : 3a000000;
+0e97 : 3a646f6e;
+0e98 : 650a0000;
+0e99 : 53656374;
+0e9a : 6f723a00;
+0e9b : 20726563;
+0e9c : 65697665;
+0e9d : 3a000000;
+0e9e : 2073656e;
+0e9f : 64696e67;
+0ea0 : 0a000000;
+0ea1 : 64617461;
+0ea2 : 20000000;
+0ea3 : 626f6f74;
+0ea4 : 20000000;
+0ea5 : 6e616d65;
+0ea6 : 20000000;
+0ea7 : 6e756d74;
+0ea8 : 6f627566;
+0ea9 : 66657220;
+0eaa : 00000000;
+0eab : 00000000;
+0eac : 00000000;
+0ead : 72025f07;
+0eae : f807a900;
+0eaf : 8d04038d;
+0eb0 : 4402a907;
+0eb1 : 8d0503a9;
+0eb2 : 708d0a03;
+0eb3 : a9018d0b;
+0eb4 : 03850960;
+0eb5 : 7d8a4820;
+0eb6 : 53e488d0;
+0eb7 : fa68aa8c;
+0eb8 : 8e07ad7d;
+0eb9 : 07ee8e07;
+0eba : 60a9938d;
+0ebb : e202a907;
+0ebc : 8de302a2;
+0ebd : 0220da07;
+0ebe : 954320da;
+0ebf : 07954435;
+0ec0 : 43c9fff0;
+0ec1 : f0caca10;
+0ec2 : ec3006e6;
+0ec3 : 45d002e6;
+0ec4 : 4620da07;
+0ec5 : a2018144;
+0ec6 : b545d543;
+0ec7 : d0edca10;
+0ec8 : f720d207;
+0ec9 : 4c9407a9;
+0eca : 038d0fd2;
+0ecb : 6ce202ad;
+0ecc : 8e07cd7f;
+0ecd : 07d0abee;
+0ece : 0a03d003;
+0ecf : ee0b03ad;
+0ed0 : 7d070d7e;
+0ed1 : 07d08e20;
+0ed2 : d2076ce0;
+0ed3 : 0220da07;
+0ed4 : 8de00220;
+0ed5 : da078de1;
+0ed6 : 022de002;
+0ed7 : c9fff0ed;
+0ed8 : a9008d8e;
+0ed9 : 07f08200;
+0eda : 0001d20f;
+0edb : 0001d400;
+0edc : 0001d401;
+0edd : 0001d409;
+0ede : 0001d010;
+0edf : 0001d301;
+0ee0 : 0001d300;
+0ee1 : 0001d20a;
+0ee2 : 0001d01b;
+0ee3 : 0001d018;
+0ee4 : 0001d017;
+0ee5 : 0001d01a;
+0ee6 : 0001d403;
+0ee7 : 0001d402;
+0ee8 : 0001d40e;
+0ee9 : 0004007c;
+0eea : 00040078;
+0eeb : 00040074;
+0eec : 00040068;
+0eed : 00040060;
+0eee : 0004005c;
+0eef : 00040058;
+0ef0 : 00040054;
+0ef1 : 00040050;
+0ef2 : 0004004c;
+0ef3 : 00040048;
+0ef4 : 00040044;
+0ef5 : 00040040;
+0ef6 : 0004002c;
+0ef7 : 00040028;
+0ef8 : 00040024;
+0ef9 : 00040020;
+0efa : 0004001c;
+0efb : 00040018;
+0efc : 00040014;
+0efd : 00040010;
+0efe : 0004000c;
+0eff : 00040008;
+0f00 : 00040004;
+0f01 : 00040000;
+END; 
Index: unmerged/core/mist/zpu/debug.h
===================================================================
--- unmerged/core/mist/zpu/debug.h	(nonexistent)
+++ unmerged/core/mist/zpu/debug.h	(revision 1)
@@ -0,0 +1,19 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/core/mist/zpu/led.h
===================================================================
--- unmerged/core/mist/zpu/led.h	(nonexistent)
+++ unmerged/core/mist/zpu/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/core/mist/zpu/mmcconf.h
===================================================================
--- unmerged/core/mist/zpu/mmcconf.h	(nonexistent)
+++ unmerged/core/mist/zpu/mmcconf.h	(revision 1)
@@ -0,0 +1,33 @@
+/*! \file mmcconf.h \brief MultiMedia and SD Flash Card Interface Configuration. */
+//*****************************************************************************
+//
+// File Name	: 'mmcconf.h'
+// Title		: MultiMedia and SD Flash Card Interface Configuration
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef MMCCONF_H
+#define MMCCONF_H
+
+#endif
Index: unmerged/core/mist/zpu/regs.c
===================================================================
--- unmerged/core/mist/zpu/regs.c	(nonexistent)
+++ unmerged/core/mist/zpu/regs.c	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+
+#endif // regs_h
Index: unmerged/core/mist/output_file.rbf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/core/mist/output_file.rbf
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/core/mist/pll.ppf
===================================================================
--- unmerged/core/mist/pll.ppf	(nonexistent)
+++ unmerged/core/mist/pll.ppf	(revision 1)
@@ -0,0 +1,12 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="c2" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
Index: unmerged/core/mist/pokey.vhdl
===================================================================
--- unmerged/core/mist/pokey.vhdl	(nonexistent)
+++ unmerged/core/mist/pokey.vhdl	(revision 1)
@@ -0,0 +1,1229 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Problem - UART on the DE1 does not have all pins connected. Need to use...
+
+ENTITY pokey IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	--ENABLE_179 :in std_logic;
+	CPU_MEMORY_READY :in std_logic;
+	ANTIC_MEMORY_READY :in std_logic;
+	ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	RESET_N : IN STD_LOGIC;
+	
+	-- keyboard interface
+--	KBCODE : IN STD_LOGIC_VECTOR(7 downto 0);
+--	KEY_HELD : IN STD_LOGIC;
+--	SHIFT_PRESSED : IN STD_LOGIC;
+--	BREAK_PRESSED : IN STD_LOGIC;
+--	KEY_INTERRUPT : IN STD_LOGIC;
+	keyboard_scan : out std_logic_vector(5 downto 0);
+	keyboard_response : in std_logic_vector(1 downto 0);
+	
+	-- pots - go high as capacitor charges
+	POT_IN : in std_logic_vector(7 downto 0);
+	
+	-- sio interface
+	SIO_IN1 : IN std_logic;
+	SIO_IN2 : IN std_logic;
+	SIO_IN3 : IN std_logic;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+	
+	CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	
+	IRQ_N_OUT : OUT std_logic;
+	
+	SIO_OUT1 : OUT std_logic;
+	SIO_OUT2 : OUT std_logic;
+	SIO_OUT3 : OUT std_logic;
+	
+	SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+	
+	POT_RESET : out std_logic
+);
+END pokey;
+
+ARCHITECTURE vhdl OF pokey IS
+	component synchronizer IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RAW : IN STD_LOGIC;
+		SYNC : OUT STD_LOGIC
+	);
+	END component;
+
+	component syncreset_enable_divider IS
+	generic(COUNT : natural := 1; RESETCOUNT : natural := 0);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		syncreset : in std_logic;
+		reset_n : in std_logic;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_17_9 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC;
+		
+		RAND_OUT : OUT std_logic_vector(7 downto 0)
+	);
+	END component;
+	
+	component poly_5 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component poly_4 IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		INIT : IN STD_LOGIC;
+		
+		BIT_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_countdown_timer IS
+	generic(UNDERFLOW_DELAY : natural := 3);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		ENABLE_UNDERFLOW : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		WR_EN : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC_VECTOR(7 downto 0);
+
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_noise_filter IS
+	PORT 
+	( 
+		NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+			
+		PULSE_IN : IN STD_LOGIC;
+
+		NOISE_4 : IN STD_LOGIC;
+		NOISE_5 : IN STD_LOGIC;
+		NOISE_LARGE : IN STD_LOGIC;
+		
+		PULSE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component pokey_keyboard_scanner is
+	port
+	(
+		clk : in std_logic;
+		reset_n : in std_logic;
+		
+		enable : in std_logic; -- typically hsync or equiv timing
+		keyboard_response : in std_logic_vector(1 downto 0);
+		debounce_disable : in std_logic;
+		scan_enable : in std_logic;
+		
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		
+		shift_pressed : out std_logic;
+		control_pressed : out std_logic;
+		break_pressed : out std_logic;
+		key_held : out std_logic;
+		keycode : out std_logic_vector(5 downto 0);
+		other_key_irq : out std_logic
+	);
+	end component;
+	
+	--signal enable_179 : std_logic;
+	signal enable_64 : std_logic;
+	signal enable_15 : std_logic;
+
+	signal audf0_reg : std_logic_vector(7 downto 0);
+	signal audc0_reg : std_logic_vector(7 downto 0);
+	signal audf1_reg : std_logic_vector(7 downto 0);
+	signal audc1_reg : std_logic_vector(7 downto 0);
+	signal audf2_reg : std_logic_vector(7 downto 0);
+	signal audc2_reg : std_logic_vector(7 downto 0);
+	signal audf3_reg : std_logic_vector(7 downto 0);
+	signal audc3_reg : std_logic_vector(7 downto 0);
+	signal audctl_reg : std_logic_vector(7 downto 0);	
+	signal audf0_next : std_logic_vector(7 downto 0);
+	signal audc0_next : std_logic_vector(7 downto 0);
+	signal audf1_next : std_logic_vector(7 downto 0);
+	signal audc1_next : std_logic_vector(7 downto 0);
+	signal audf2_next : std_logic_vector(7 downto 0);
+	signal audc2_next : std_logic_vector(7 downto 0);
+	signal audf3_next : std_logic_vector(7 downto 0);
+	signal audc3_next : std_logic_vector(7 downto 0);
+	signal audctl_next : std_logic_vector(7 downto 0);
+
+	signal audf0_pulse : std_logic;
+	signal audf1_pulse : std_logic;
+	signal audf2_pulse : std_logic;
+	signal audf3_pulse : std_logic;
+	
+	signal audf0_reload : std_logic;
+	signal audf1_reload : std_logic;
+	signal audf2_reload : std_logic;
+	signal audf3_reload : std_logic;
+	
+	signal stimer_write : std_logic;
+	signal stimer_write_delayed : std_logic;
+	
+	signal audf0_pulse_noise : std_logic;
+	signal audf1_pulse_noise : std_logic;
+	signal audf2_pulse_noise : std_logic;
+	signal audf3_pulse_noise : std_logic;
+	
+	signal audf0_enable : std_logic;
+	signal audf1_enable : std_logic;
+	signal audf2_enable : std_logic;
+	signal audf3_enable : std_logic;
+	
+	signal chan0_output_next : std_logic;
+	signal chan1_output_next : std_logic;
+	signal chan2_output_next : std_logic;
+	signal chan3_output_next : std_logic;
+	signal chan0_output_reg : std_logic;
+	signal chan1_output_reg : std_logic;
+	signal chan2_output_reg : std_logic;
+	signal chan3_output_reg : std_logic;
+	
+	signal highpass0_next : std_logic;
+	signal highpass1_next : std_logic;	
+	signal highpass0_reg : std_logic;
+	signal highpass1_reg : std_logic;
+	
+	signal volume_channel_0_next : std_logic_vector(3 downto 0);
+	signal volume_channel_1_next : std_logic_vector(3 downto 0);
+	signal volume_channel_2_next : std_logic_vector(3 downto 0);
+	signal volume_channel_3_next : std_logic_vector(3 downto 0);
+	signal volume_channel_0_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_1_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_2_reg : std_logic_vector(3 downto 0);
+	signal volume_channel_3_reg : std_logic_vector(3 downto 0);
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);
+	
+	signal noise_4 : std_logic;
+	signal noise_5 : std_logic;
+	signal noise_large : std_logic;
+	signal rand_out : std_logic_vector(7 downto 0); -- snoop part of the shift reg
+	
+	signal initmode : std_logic;
+	
+	signal irqen_next : std_logic_vector(7 downto 0);
+	signal irqen_reg : std_logic_vector(7 downto 0);
+
+	signal irqst_next : std_logic_vector(7 downto 0);
+	signal irqst_reg : std_logic_vector(7 downto 0);
+	
+	signal irq_n_next : std_logic;
+	signal irq_n_reg : std_logic; -- for output
+	
+	-- serial ports!
+	signal serial_ip_ready_interrupt : std_logic;
+	signal serial_ip_framing_next : std_logic;
+	signal serial_ip_framing_reg : std_logic;
+	signal serial_ip_overrun_next : std_logic;
+	signal serial_ip_overrun_reg : std_logic;
+	signal serial_op_needed_interrupt : std_logic;
+	
+	signal skctl_next : std_logic_vector(7 downto 0);
+	signal skctl_reg : std_logic_vector(7 downto 0);
+	
+	signal serin_shift_next : std_logic_vector(9 downto 0);
+	signal serin_shift_reg : std_logic_vector(9 downto 0);
+	signal serin_next : std_logic_vector(7 downto 0);
+	signal serin_reg : std_logic_vector(7 downto 0);
+	signal serin_bitcount_next : std_logic_vector(3 downto 0);
+	signal serin_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal sio_in1_reg : std_logic;
+	signal sio_in2_reg : std_logic;
+	signal sio_in3_reg : std_logic;
+	signal sio_in_next : std_logic;
+	signal sio_in_reg : std_logic;
+	
+	signal sio_out_next : std_logic;
+	signal sio_out_reg : std_logic;
+	signal serial_out_next : std_logic;
+	signal serial_out_reg : std_logic;
+	
+	signal serout_shift_next : std_logic_vector(9 downto 0);
+	signal serout_shift_reg : std_logic_vector(9 downto 0);
+	
+	signal serout_holding_full_next : std_logic;
+	signal serout_holding_full_reg : std_logic;
+	signal serout_holding_next : std_logic_vector(7 downto 0);
+	signal serout_holding_reg : std_logic_vector(7 downto 0);
+	signal serout_holding_load : std_logic;
+
+	signal serout_bitcount_next : std_logic_vector(3 downto 0);
+	signal serout_bitcount_reg : std_logic_vector(3 downto 0);
+	
+	signal serout_active_next : std_logic;
+	signal serout_active_reg : std_logic;
+	
+	signal serial_reset : std_logic;
+	signal skrest_write : std_logic;
+	
+	signal serout_enable : std_logic;
+	signal serout_enable_delayed : std_logic;
+	signal serin_enable : std_logic;
+	
+	signal async_serial_reset : std_logic;
+	signal waiting_for_start_bit : std_logic;
+	
+	signal serin_clock_next : std_logic;
+	signal serin_clock_reg : std_logic;
+	signal serin_clock_last_next : std_logic;
+	signal serin_clock_last_reg : std_logic;
+
+	signal serout_clock_next : std_logic;
+	signal serout_clock_reg : std_logic;
+	signal serout_clock_last_next : std_logic;
+	signal serout_clock_last_reg : std_logic;
+	
+	signal twotone_reset : std_logic;
+	signal twotone_next : std_logic;
+	signal twotone_reg : std_logic;
+	
+	signal clock_next : std_logic;
+	signal clock_reg : std_logic;
+	signal clock_sync_next : std_logic;
+	signal clock_sync_reg : std_logic;
+	signal clock_input : std_logic;
+	
+	-- keyboard
+	signal keyboard_overrun_next : std_logic;
+	signal keyboard_overrun_reg : std_logic;
+	
+	signal shift_pressed : std_logic;
+	signal control_pressed : std_logic;
+	signal break_pressed : std_logic;
+	signal key_held : std_logic;
+	signal other_key_irq : std_logic;
+	
+	signal kbcode : std_logic_vector(5 downto 0);
+	
+	-- pots
+	signal pot0_next : std_logic_vector(7 downto 0);
+	signal pot0_reg : std_logic_vector(7 downto 0);
+	signal pot1_next : std_logic_vector(7 downto 0);
+	signal pot1_reg : std_logic_vector(7 downto 0);
+	signal pot2_next : std_logic_vector(7 downto 0);
+	signal pot2_reg : std_logic_vector(7 downto 0);
+	signal pot3_next : std_logic_vector(7 downto 0);
+	signal pot3_reg : std_logic_vector(7 downto 0);
+	signal pot4_next : std_logic_vector(7 downto 0);
+	signal pot4_reg : std_logic_vector(7 downto 0);
+	signal pot5_next : std_logic_vector(7 downto 0);
+	signal pot5_reg : std_logic_vector(7 downto 0);	
+	signal pot6_next : std_logic_vector(7 downto 0);
+	signal pot6_reg : std_logic_vector(7 downto 0);
+	signal pot7_next : std_logic_vector(7 downto 0);
+	signal pot7_reg : std_logic_vector(7 downto 0);	
+	
+	signal pot_counter_next : std_logic_vector(7 downto 0);
+	signal pot_counter_reg : std_logic_vector(7 downto 0);
+	
+	signal potgo_write : std_logic;
+	
+	signal pot_reset_next : std_logic;
+	signal pot_reset_reg : std_logic;
+	
+	signal enable_179 : std_logic;
+BEGIN
+	--HACK FIXME TODO
+	enable_179 <= cpu_MEMORY_READY or antIC_MEMORY_READY;
+
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			-- FIXME - Pokey does not have RESET - instead this is caused by 'init' sequence
+			audf0_reg <= X"00";
+			audc0_reg <= X"00";
+			audf1_reg <= X"00";
+			audc1_reg <= X"00";
+			audf2_reg <= X"00";
+			audc2_reg <= X"00";
+			audf3_reg <= X"00";
+			audc3_reg <= X"00";
+			audctl_reg <= X"00";
+			
+			irqen_reg <= X"00";
+			irqst_reg <= X"FF";
+			irq_n_reg <= '1';
+			
+			skctl_reg <= X"00";
+			
+			highpass0_reg <= '0';
+			highpass1_reg <= '0';
+			
+			chan0_output_reg <= '0';
+			chan1_output_reg <= '0';
+			chan2_output_reg <= '0';
+			chan3_output_reg <= '0';
+			
+			volume_channel_0_reg <= (others=>'0');
+			volume_channel_1_reg <= (others=>'0');
+			volume_channel_2_reg <= (others=>'0');
+			volume_channel_3_reg <= (others=>'0');
+			
+			serin_reg <= (others=>'0');
+			serin_shift_reg <= (others=>'0');
+			serin_bitcount_reg <= (others=>'0');
+			serout_shift_reg <= (others=>'0');
+			serout_holding_reg <= (others=>'0');
+			serout_holding_full_reg <= '0';
+			serout_active_reg <= '0';		
+			sio_out_reg <= '1';
+			serial_out_reg <= '1';
+			
+			serial_ip_framing_reg <= '0';
+			serial_ip_overrun_reg <= '0';
+			
+			clock_reg <= '0';
+			clock_sync_reg <= '0';
+	
+			keyboard_overrun_reg <= '0';
+			
+			serin_clock_reg <= '0';
+			serin_clock_last_reg <= '0';
+			serout_clock_reg <= '0';
+			serout_clock_last_reg <= '0';
+			
+			twotone_reg <= '0';
+			
+			sio_in_reg <= '0';
+			
+			pot0_reg <= (others=>'0');
+			pot1_reg <= (others=>'0');
+			pot2_reg <= (others=>'0');
+			pot3_reg <= (others=>'0');
+			pot4_reg <= (others=>'0');
+			pot5_reg <= (others=>'0');
+			pot6_reg <= (others=>'0');
+			pot7_reg <= (others=>'0');
+			
+			pot_counter_reg <= (others=>'0');
+			
+			pot_reset_reg <= '1';
+			
+		elsif (clk'event and clk='1') then			
+			audf0_reg <= audf0_next;
+			audc0_reg <= audc0_next;
+			audf1_reg <= audf1_next;
+			audc1_reg <= audc1_next;
+			audf2_reg <= audf2_next;
+			audc2_reg <= audc2_next;
+			audf3_reg <= audf3_next;
+			audc3_reg <= audc3_next;
+			audctl_reg <= audctl_next;
+			
+			irqen_reg <= irqen_next;
+			irqst_reg <= irqst_next;
+			irq_n_reg <= irq_n_next;
+			
+			skctl_reg <= skctl_next;
+			
+			highpass0_reg <= highpass0_next;
+			highpass1_reg <= highpass1_next;
+			
+			chan0_output_reg <= chan0_output_next;
+			chan1_output_reg <= chan1_output_next;
+			chan2_output_reg <= chan2_output_next;
+			chan3_output_reg <= chan3_output_next;
+			
+			volume_channel_0_reg<= volume_channel_0_next;
+			volume_channel_1_reg<= volume_channel_1_next;
+			volume_channel_2_reg<= volume_channel_2_next;
+			volume_channel_3_reg<= volume_channel_3_next;
+			
+			serin_reg <= serin_next;
+			serin_shift_reg <= serin_shift_next;
+			serin_bitcount_reg <= serin_bitcount_next;
+			serout_shift_reg <= serout_shift_next;
+			serout_bitcount_reg <= serout_bitcount_next;
+			
+			serout_holding_reg<=serout_holding_next;
+			serout_holding_full_reg<=serout_holding_full_next;
+			serout_active_reg <= serout_active_next;
+			
+			sio_out_reg <= sio_out_next;
+			serial_out_reg <= serial_out_next;
+			
+			serial_ip_framing_reg <= serial_ip_framing_next;
+			serial_ip_overrun_reg <= serial_ip_overrun_next;
+			
+			clock_reg <= clock_next;
+			clock_sync_reg <= clock_sync_next;
+			
+			keyboard_overrun_reg <= keyboard_overrun_next;
+			
+			serin_clock_reg <= serin_clock_next;
+			serin_clock_last_reg <= serin_clock_last_next;
+			serout_clock_reg <= serout_clock_next;
+			serout_clock_last_reg <= serout_clock_last_next;
+			
+			twotone_reg <= twotone_next;
+			
+			sio_in_reg <= sio_in_next;
+			
+			pot0_reg <= pot0_next;
+			pot1_reg <= pot1_next;
+			pot2_reg <= pot2_next;
+			pot3_reg <= pot3_next;
+			pot4_reg <= pot4_next;
+			pot5_reg <= pot5_next;
+			pot6_reg <= pot6_next;
+			pot7_reg <= pot7_next;
+			
+			pot_counter_reg <= pot_counter_next;
+			
+			pot_reset_reg <= pot_reset_next;
+		end if;
+	end process;
+	
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr, addr_decoded=>addr_decoded);
+	
+	-- clock selection
+	process(enable_64,enable_15,enable_179,audctl_reg,audf0_pulse,audf2_pulse)
+	begin
+		audf0_enable <= enable_64;
+		audf1_enable <= enable_64;
+		audf2_enable <= enable_64;
+		audf3_enable <= enable_64;		
+		
+		if (audctl_reg(0) = '1') then
+			audf0_enable <= enable_15;
+			audf1_enable <= enable_15;
+			audf2_enable <= enable_15;
+			audf3_enable <= enable_15;
+		end if;
+
+		if (audctl_reg(6) = '1') then
+			audf0_enable <= enable_179;
+		end if;
+		
+		if (audctl_reg(5) = '1') then
+			audf2_enable <= enable_179;
+		end if;
+		
+		if(audctl_reg(4) = '1') then
+			audf1_enable <= audf0_pulse;
+		end if;
+		
+		if(audctl_reg(3) = '1') then
+			audf3_enable <= audf2_pulse;
+		end if;
+	end process;
+	
+	-- Instantiate timers
+	timer0 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf0_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf0_reload,data_in=>audf0_next,DATA_OUT=>audf0_pulse);
+	timer1 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf1_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf1_reload,data_in=>audf1_next,DATA_OUT=>audf1_pulse);
+	timer2 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf2_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf2_reload,data_in=>audf2_next,DATA_OUT=>audf2_pulse);
+	timer3 : pokey_countdown_timer
+		generic map (UNDERFLOW_DELAY=>3)
+		port map(clk=>clk,enable=>audf3_enable,enable_underflow=>enable_179,reset_n=>reset_n,wr_en=>audf3_reload,data_in=>audf3_next,DATA_OUT=>audf3_pulse);		
+		
+	-- Timer reloading
+	process (audctl_reg, audf0_pulse, audf1_pulse, audf2_pulse, audf3_pulse, stimer_write_delayed, async_serial_reset, twotone_reset)
+	begin
+		audf0_reload <= ((not(audctl_reg(4)) and audf0_pulse)) or (audctl_reg(4) and audf1_pulse) or stimer_write_delayed or twotone_reset;
+		audf1_reload <= audf1_pulse or stimer_write_delayed or twotone_reset;
+		audf2_reload <= ((not(audctl_reg(3)) and audf2_pulse)) or (audctl_reg(3) and audf3_pulse) or stimer_write_delayed or async_serial_reset;
+		audf3_reload <= audf3_pulse or stimer_write_delayed or async_serial_reset;
+	end process;
+	
+	-- Writes to registers
+	process(data_in,wr_en,addr_decoded,audf0_reg,audc0_reg,audf1_reg,audc1_reg,audf2_reg,audc2_reg,audf3_reg,audc3_reg,audf0_enable,audf1_enable,audf2_enable,audf3_enable,audctl_reg, irqen_reg, skctl_reg, serout_holding_reg)
+	begin
+		audf0_next <= audf0_reg;
+		audc0_next <= audc0_reg;
+		audf1_next <= audf1_reg;
+		audc1_next <= audc1_reg;
+		audf2_next <= audf2_reg;
+		audc2_next <= audc2_reg;
+		audf3_next <= audf3_reg;
+		audc3_next <= audc3_reg;
+		audctl_next <= audctl_reg;		
+		
+		irqen_next <= irqen_reg;
+		skctl_next <= skctl_reg;
+		
+		stimer_write <= '0';
+		
+		serout_holding_load <= '0';
+		serout_holding_next <= serout_holding_reg;
+		
+		serial_reset <= '0';
+		skrest_write <= '0';
+		potgo_write <= '0';
+		
+		if (wr_en = '1') then
+			if(addr_decoded(0) = '1') then
+				audf0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(1) = '1') then
+				audc0_next <= data_in;
+			end if;
+			
+			if(addr_decoded(2) = '1') then
+				audf1_next <= data_in;
+			end if;
+
+			if(addr_decoded(3) = '1') then
+				audc1_next <= data_in;
+			end if;
+			
+			if(addr_decoded(4) = '1') then
+				audf2_next <= data_in;
+			end if;
+
+			if(addr_decoded(5) = '1') then
+				audc2_next <= data_in;
+			end if;
+			
+			if(addr_decoded(6) = '1') then
+				audf3_next <= data_in;
+			end if;		
+
+			if(addr_decoded(7) = '1') then
+				audc3_next <= data_in;
+			end if;
+			
+			if(addr_decoded(8) = '1') then
+				audctl_next <= data_in;
+			end if;
+			
+			if (addr_decoded(9) = '1') then --STIMER
+				stimer_write <= '1';
+			end if;
+			
+			if (addr_decoded(10) = '1') then -- skrest - resets the serial input problems - overflow etc
+				skrest_write <= '1';
+			end if;
+
+			if (addr_decoded(11) = '1') then -- POTGO - start POT scan
+				potgo_write <= '1';
+			end if;
+			
+			if (addr_decoded(13) = '1') then --SEROUT								
+				serout_holding_next <= data_in;
+				serout_holding_load <= '1';
+			end if;
+			
+			if (addr_decoded(14) = '1') then --IRQEN
+				irqen_next <= data_in;
+			end if;
+
+			if (addr_decoded(15) = '1') then --SKCTL
+				skctl_next <= data_in;
+				
+				if (data_in(6 downto 4)="000") then
+					serial_reset <= '1';
+				end if;
+			end if;	
+	
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr_decoded,kbcode,control_pressed,RAND_OUT,IRQST_REG,KEY_HELD,SHIFT_PRESSED,sio_in_reg,serin_reg,keyboard_overrun_reg, serial_ip_framing_reg, serial_ip_overrun_reg, waiting_for_start_bit, pot_in, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin
+		data_out <= X"FF";
+
+		if(addr_decoded(0) = '1') then --POT0
+			data_out <= pot0_reg;
+		end if;
+
+		if(addr_decoded(1) = '1') then --POT1
+			data_out <= pot1_reg;
+		end if;
+
+		if(addr_decoded(2) = '1') then --POT2
+			data_out <= pot2_reg;
+		end if;
+
+		if(addr_decoded(3) = '1') then --POT3
+			data_out <= pot3_reg;
+		end if;
+		
+		if(addr_decoded(4) = '1') then --POT4
+			data_out <= pot4_reg;
+		end if;
+
+		if(addr_decoded(5) = '1') then --POT5
+			data_out <= pot5_reg;
+		end if;
+
+		if(addr_decoded(6) = '1') then --POT6
+			data_out <= pot6_reg;
+		end if;
+
+		if(addr_decoded(7) = '1') then --POT7
+			data_out <= pot7_reg;
+		end if;
+
+		if(addr_decoded(8) = '1') then --ALLPOT
+			data_out <= not(pot_in);
+		end if;
+		
+		if(addr_decoded(9) = '1') then --KBCODE
+			data_out <= control_pressed&shift_pressed&kbcode;
+		end if;
+		
+		if(addr_decoded(10) = '1') then -- RANDOM
+			data_out <= RAND_OUT;
+		end if;
+
+		if (addr_decoded(13) = '1') then --SERIN			
+			data_out <= serin_reg;
+		end if;
+		
+		if (addr_decoded(14) = '1') then --IRQST - bits set to low when irq
+			data_out <= IRQST_REG;
+			--break_irq_n & other_key_irq_n & serial_ip_irq_n & serial_op_irq_n & serial_trans_irq_n & timer3_irq_n & timer_1_irq_n & timer_0_irq_n
+		end if;		
+
+		if (addr_decoded(15) = '1') then --SKSTAT
+			data_out <= not(serial_ip_framing_reg)&not(serial_ip_overrun_reg)&not(keyboard_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
+		end if;		
+		
+	end process;
+	
+	-- Fire interrupts
+	process (irqen_reg, irqst_reg, audf0_pulse, audf1_pulse, audf3_pulse, other_key_irq, serial_ip_ready_interrupt, serout_active_reg, serial_op_needed_interrupt, break_pressed)
+	begin
+		-- clear interrupts
+		irqst_next <= irqst_reg or not(irqen_reg);
+				
+		irq_n_next <= '0';
+
+		if ((irqst_reg or "0000"&not(irqen_reg(3))&"000") = X"FF") then
+			irq_n_next <= '1';
+		end if;
+	
+		-- set interrupts
+		if (audf0_pulse = '1') then
+			irqst_next(0) <= not(irqen_reg(0));
+		end if;
+
+		if (audf1_pulse = '1') then
+			irqst_next(1) <= not(irqen_reg(1));
+		end if;
+
+		if (audf3_pulse = '1') then
+			irqst_next(2) <= not(irqen_reg(2));
+		end if;
+		
+		if (other_key_irq = '1') then
+			irqst_next(6) <= not(irqen_reg(6));			
+		end if;
+		
+		if (break_pressed = '1') then
+			irqst_next(7) <= not(irqen_reg(7));			
+		end if;		
+	
+		if (serial_ip_ready_interrupt = '1') then
+			irqst_next(5) <= not(irqen_reg(5));
+		end if;
+		
+		irqst_next(3) <= serout_active_reg;
+		
+		if (serial_op_needed_interrupt = '1') then
+			irqst_next(4) <= not(irqen_reg(4));
+		end if;
+		
+	end process;
+	
+	-- Instantiate delay for stimer reload_request
+	stimer_delay : delay_line
+		generic map (count=>3)
+		port map (clk=>clk, sync_reset=>'0',data_in=>stimer_write, enable=>enable_179, reset_n=>reset_n, data_out=>stimer_write_delayed);
+		
+	--stimer_write_delayed <= stimer_write;
+	
+	-- Instantiate audio noise filters
+	pokey_noise_filter0 : pokey_noise_filter
+		port map(noise_select=>audc0_reg(7 downto 5),pulse_in=>audf0_pulse,pulse_out=>audf0_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter1 : pokey_noise_filter
+		port map(noise_select=>audc1_reg(7 downto 5),pulse_in=>audf1_pulse,pulse_out=>audf1_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter2 : pokey_noise_filter
+		port map(noise_select=>audc2_reg(7 downto 5),pulse_in=>audf2_pulse,pulse_out=>audf2_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	pokey_noise_filter3 : pokey_noise_filter
+		port map(noise_select=>audc3_reg(7 downto 5),pulse_in=>audf3_pulse,pulse_out=>audf3_pulse_noise,noise_4=>noise_4,noise_5=>noise_5,noise_large=>noise_large);
+	
+	-- Audio output stage
+	process(audf0_pulse_noise, audf1_pulse_noise, audf2_pulse_noise, audf3_pulse_noise, chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg)
+	begin
+		chan0_output_next <= chan0_output_reg;
+		chan1_output_next <= chan1_output_reg;
+		chan2_output_next <= chan2_output_reg;
+		chan3_output_next <= chan3_output_reg;
+		
+		if (audf0_pulse_noise = '1') then
+			chan0_output_next <= not(chan0_output_reg);
+		end if;
+		
+		if (audf1_pulse_noise = '1') then
+			chan1_output_next <= not(chan1_output_reg);
+		end if;
+		
+		if (audf2_pulse_noise = '1') then
+			chan2_output_next <= not(chan2_output_reg);
+		end if;
+		
+		if (audf3_pulse_noise = '1') then
+			chan3_output_next <= not(chan3_output_reg);
+		end if;
+	end process;
+	
+	-- High pass filters
+	process(audctl_reg,audf2_pulse,audf3_pulse,chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, highpass0_reg, highpass1_reg)
+	begin
+		highpass0_next <= highpass0_reg;
+		highpass1_next <= highpass1_reg;
+		
+		if (audctl_reg(2) = '1') then
+			if (audf2_pulse = '1') then
+				highpass0_next <= chan0_output_reg;
+			end if;
+		else
+			highpass0_next <= '1';
+		end if;
+		
+		if (audctl_reg(1) = '1') then
+			if (audf3_pulse = '1') then
+				highpass1_next <= chan1_output_reg;
+			end if;
+		else
+			highpass1_next <= '1';
+		end if;
+		
+	end process;
+	
+	-- Instantiate key pokey clocks
+	-- ~1.79MHz - from 25MHz/14
+	-- ~64KHz - from 1.79MHz/28
+	-- ~15KHz - from 1.79MHz/114
+	--enable_179_div : enable_divider
+	--	generic map (COUNT=>14)
+	--	port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);		
+		
+	-- resetcount 6/33
+	enable_64_div : syncreset_enable_divider
+		generic map (COUNT=>28,RESETCOUNT=>6) -- 28-22
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_64);
+		
+	enable_15_div : syncreset_enable_divider
+		generic map (COUNT=>114,RESETCOUNT=>33) -- 114-81
+		port map(clk=>clk,syncreset=>initmode,reset_n=>reset_n,enable_in=>enable_179,enable_out=>enable_15);
+		
+	-- Instantiate pokey noise circuits (lfsr)
+	initmode <= skctl_next(1) nor skctl_next(0);
+	poly_17_19_lfsr : poly_17_9
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,select_9_17=>audctl_reg(7),bit_out=>noise_large,rand_out=>rand_out);
+		
+	poly_5_lfsr : poly_5
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_5);
+		
+	poly_4_lfsr : poly_4
+		port map(clk=>clk,reset_n=>reset_n,init=>initmode,enable=>enable_179,bit_out=>noise_4);
+	
+	--AUDIO_LEFT <= "000"&count_reg(15 downto 3);
+	process(chan0_output_reg, chan1_output_reg, chan2_output_reg, chan3_output_reg, audc0_reg, audc1_reg, audc2_reg, audc3_reg, highpass0_reg, highpass1_reg)
+	begin
+		volume_channel_0_next <= "0000";
+		volume_channel_1_next <= "0000";
+		volume_channel_2_next <= "0000";
+		volume_channel_3_next <= "0000";
+			
+		if (((chan0_output_reg xor highpass0_reg) or audc0_reg(4)) = '1') then
+			volume_channel_0_next <= audc0_reg(3 downto 0);
+		end if;
+		
+		if (((chan1_output_reg xor highpass1_reg) or audc1_reg(4)) = '1') then
+			volume_channel_1_next <= audc1_reg(3 downto 0);
+		end if;
+		
+		if ((chan2_output_reg or audc2_reg(4)) = '1') then
+			volume_channel_2_next <= audc2_reg(3 downto 0);
+		end if;
+		
+		if ((chan3_output_reg or audc3_reg(4)) = '1') then
+			volume_channel_3_next <= audc3_reg(3 downto 0);
+		end if;
+		
+	end process;
+	
+	-- serial port output	
+	-- urghhh
+	serout_clock_delay : delay_line
+		generic map (count=>2)
+		port map (clk=>clk, sync_reset=>serial_reset or stimer_write_delayed,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+		
+	
+	process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
+	begin
+		serout_clock_next <= serout_clock_reg;
+		serout_clock_last_next <= serout_clock_reg;
+	
+		serout_shift_next <= serout_shift_reg;
+		serout_bitcount_next <= serout_bitcount_reg;
+		serout_holding_full_next <= serout_holding_full_reg;
+		serout_active_next <= serout_active_reg;
+		
+		serial_out_next <= serial_out_reg; -- output from shift reg (if unchanged)
+		sio_out_next <= serial_out_reg;		
+	
+		-- two tone output
+		twotone_next <= twotone_reg;
+		twotone_reset <= '0';
+		
+		if ((audf1_pulse or (audf0_pulse and serial_out_reg)) = '1') then
+			twotone_next <= not(twotone_reg);
+			twotone_reset <= skctl_reg(3);
+		end if;
+		
+		if (skctl_reg(3) = '1') then
+			sio_out_next <= twotone_reg;
+		end if;
+	
+		-- force break
+		if (skctl_reg(7) = '1') then
+			sio_out_next <= '0';
+		end if;
+		
+		serial_op_needed_interrupt <= '0';		
+		
+		-- generate clock from enable signals
+		if (serout_enable_delayed = '1') then
+			serout_clock_next <= not(serout_clock_reg);
+		end if;
+		
+		-- output bits over sio
+		if (serout_clock_last_reg = '0' and serout_clock_reg = '1') then			
+			serout_shift_next <= '0'&serout_shift_reg(9 downto 1); -- next
+			serial_out_next <= serout_shift_reg(1) or not(serout_active_reg); -- i.e. next serout_shift_reg(0)
+				
+			-- reload			
+			if (serout_bitcount_reg = X"0") then
+				if (serout_holding_full_reg='1') then -- unless, more to send in holding reg?
+					serout_bitcount_next <= X"9"; -- 10 bits to send, 9 more after this
+					serout_shift_next <= '1'&serout_holding_reg&'0';
+					serial_out_next <= '0'; -- start bit (serout_shift_reg(0) after this cycle)
+					serout_holding_full_next <= '0';					
+					serial_op_needed_interrupt <= '1'; -- more data please!
+					serout_active_next <= '1';
+				else
+					serout_active_next <= '0';
+					serial_out_next <= '1'; -- remove blip! 
+				end if;
+			else
+				serout_bitcount_next <= std_logic_vector(unsigned(serout_bitcount_reg)-1);
+			end if;
+		end if;
+		
+		-- register to load has been written too, update our state to reflect that it is full
+		if (serout_holding_load = '1') then
+			serout_holding_full_next <= '1';
+		end if;
+		
+		if (serial_reset = '1') then
+			twotone_next <= '0';
+			serout_bitcount_next <= (others=>'0');
+			serout_shift_next <= (others=>'0');
+			serout_holding_full_next <= '0';
+			serout_clock_next <= '0';
+			serout_clock_last_next <= '0';
+			serout_active_next <= '0';
+		end if;
+	end process;
+	
+	-- serial port input
+	sio_in1_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in1, sync=>sio_in1_reg);	
+	sio_in2_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in2, sync=>sio_in2_reg);	
+	sio_in3_synchronizer : synchronizer
+		port map (clk=>clk, raw=>sio_in3, sync=>sio_in3_reg);	
+	sio_in_next <= sio_in1_reg and sio_in2_reg and sio_in3_reg;
+		
+	waiting_for_start_bit <= '1' when serin_bitcount_reg = X"9" else '0';
+	process(serin_enable,serin_clock_last_reg,serin_clock_reg, sio_in_reg, serin_reg,serin_shift_reg, serin_bitcount_reg, serial_ip_overrun_reg, serial_ip_framing_reg, skrest_write, irqst_reg, skctl_reg, waiting_for_start_bit, serial_reset)
+	begin
+		serin_clock_next <= serin_clock_reg;
+		serin_clock_last_next <= serin_clock_reg;
+	
+		serin_shift_next <= serin_shift_reg;
+		serin_bitcount_next <= serin_bitcount_reg;
+		serin_next <= serin_reg;
+		
+		serial_ip_overrun_next <= serial_ip_overrun_reg;
+		serial_ip_framing_next <= serial_ip_framing_reg;
+		serial_ip_ready_interrupt <= '0';
+		
+		async_serial_reset <= '0';
+		
+		-- generate clock from enable signals
+		if (serin_enable = '1') then
+			serin_clock_next <= not(serin_clock_reg);
+		end if;
+		
+		-- resync clock on receipt of start bit
+		if ((skctl_reg(4) and sio_in_reg and waiting_for_start_bit)= '1') then
+			async_serial_reset <= '1';
+			serin_clock_next <= '1';
+		end if;
+		
+		-- receive bits into shift reg		
+		if (serin_clock_last_reg='1' and serin_clock_reg='0') then -- failing edge					
+			if (((waiting_for_start_bit and not(sio_in_reg)) or not(waiting_for_start_bit))='1') then				
+				serin_shift_next <= sio_in_reg&serin_shift_reg(9 downto 1);
+			
+				if (serin_bitcount_reg = X"0") then -- full byte
+					serin_next <= serin_shift_reg(9 downto 2); -- not shifted yet
+					
+					serin_bitcount_next <= X"9"; -- next... no disable for serial input, always happening.
+					
+					-- irq to alert new data avilable
+					serial_ip_ready_interrupt <= '1';
+					
+					-- flag up overrun
+					if (irqst_reg(5) = '0') then -- if interrupt bit not cleared yet...
+						serial_ip_overrun_next <= '1';
+					end if;				
+					
+					-- flag up framing problem (stop bit is 1 - pull from sio since reg not yet shifted)
+					if (sio_in_reg='0') then
+						serial_ip_framing_next <= '1';
+					end if;
+				else			
+					serin_bitcount_next <= std_logic_vector(unsigned(serin_bitcount_reg)-1);
+				end if;
+			end if;
+		end if;
+		
+		if (skrest_write = '1') then
+			serial_ip_overrun_next <= '0';
+			serial_ip_framing_next <= '0';
+		end if;
+		
+		if (serial_reset = '1') then
+			serin_clock_next <= '0';
+			serin_bitcount_next <= X"9"; -- i.e. waiting for start bit
+			serin_shift_next <= (others=>'0');			
+		end if;		
+	end process;
+	
+	-- serial clocks
+	process(sio_clock,skctl_reg,clock_reg,clock_sync_reg,audf1_pulse,audf2_pulse,audf3_pulse)
+	begin
+		clock_next <= sio_clock;
+		clock_sync_next <= clock_reg;
+	
+		serout_enable <= '0';
+		serin_enable <= '0';
+		clock_input <= '1'; -- when output, outputs channel 4
+		
+		case skctl_reg(6 downto 4) is
+			when "000" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "001" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= not(clock_sync_reg) and clock_reg;
+			when "010" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+				clock_input <= '0';
+			when "011" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "100" =>
+				serin_enable <= not(clock_sync_reg) and clock_reg;
+				serout_enable <= audf3_pulse;
+			when "101" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf3_pulse;
+			when "110" =>
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+				clock_input <= '0';
+			when "111" =>			
+				serin_enable <= audf3_pulse;
+				serout_enable <= audf1_pulse;
+		end case;
+	end process;
+	
+	-- keyboard overrun (i.e. second key pressed before interrupt cleared)
+	process(other_key_irq,keyboard_overrun_reg,skrest_write,irqst_reg)
+	begin
+		keyboard_overrun_next <= keyboard_overrun_reg;
+		
+		if (other_key_irq='1' and irqst_reg(6)='0') then
+			keyboard_overrun_next <= '1';
+		end if;
+		
+		if (skrest_write = '1') then
+			keyboard_overrun_next <= '0';
+		end if;
+	end process;
+	
+	-- keyboard scan
+	pokey_keyboard_scanner1 : pokey_keyboard_scanner
+		port map (clk=>clk, reset_n=>reset_n, enable=>enable_15, keyboard_response=>keyboard_response, debounce_disable=>not(skctl_reg(0)), scan_enable=>skctl_reg(1), keyboard_scan=>keyboard_scan, shift_pressed=>shift_pressed, control_pressed=>control_pressed, break_pressed=>break_pressed, key_held=>key_held, keycode=>kbcode, other_key_irq=>other_key_irq);	
+	
+	-- POT scan
+	process(potgo_write, pot_reset_reg, pot_counter_reg, pot_in, enable_15, enable_179, skctl_reg, pot0_reg, pot1_reg, pot2_reg, pot3_reg, pot4_reg, pot5_reg, pot6_reg, pot7_reg)
+	begin	
+		pot0_next <= pot0_reg;
+		pot1_next <= pot1_reg;
+		pot2_next <= pot2_reg;
+		pot3_next <= pot3_reg;
+		pot4_next <= pot4_reg;
+		pot5_next <= pot5_reg;
+		pot6_next <= pot6_reg;
+		pot7_next <= pot7_reg;
+		
+		pot_reset_next <= pot_reset_reg;
+		
+		pot_counter_next <= pot_counter_reg;
+		
+		if (((enable_15 and not(skctl_reg(2))) or (enable_179 and skctl_reg(2))) = '1') then
+			pot_counter_next <= std_logic_vector(unsigned(pot_counter_reg) + 1);
+			if (pot_counter_reg = X"E4") then
+				pot_reset_next <= '1'; -- turn on pot dump transistors
+			end if;
+			
+			if (pot_reset_reg = '0') then
+				if (pot_in(0) = '0') then -- pot now high, latch
+					pot0_next <= pot_counter_reg;
+				end if;
+				if (pot_in(1) = '0') then -- pot now high, latch
+					pot1_next <= pot_counter_reg;
+				end if;				
+				if (pot_in(2) = '0') then -- pot now high, latch
+					pot2_next <= pot_counter_reg;
+				end if;
+				if (pot_in(3) = '0') then -- pot now high, latch
+					pot3_next <= pot_counter_reg;
+				end if;
+				if (pot_in(4) = '0') then -- pot now high, latch
+					pot4_next <= pot_counter_reg;
+				end if;
+				if (pot_in(5) = '0') then -- pot now high, latch
+					pot5_next <= pot_counter_reg;
+				end if;
+				if (pot_in(6) = '0') then -- pot now high, latch
+					pot6_next <= pot_counter_reg;
+				end if;
+				if (pot_in(7) = '0') then -- pot now high, latch
+					pot7_next <= pot_counter_reg;
+				end if;
+			end if;			
+		end if;
+			
+		if (potgo_write = '1') then
+			pot_counter_next <= (others=>'0');
+			pot_reset_next <= '0'; -- turn off pot dump transistors, so they start to get charged
+		end if;		
+	end process;
+	
+	-- Outputs
+	irq_n_out <= irq_n_reg;	
+	
+	CHANNEL_0_OUT <= volume_channel_0_reg;
+	CHANNEL_1_OUT <= volume_channel_1_reg;
+	CHANNEL_2_OUT <= volume_channel_2_reg;
+	CHANNEL_3_OUT <= volume_channel_3_reg;
+	
+	sio_out1 <= sio_out_reg;	
+	sio_out2 <= sio_out_reg;	
+	sio_out3 <= sio_out_reg;	
+	
+	sio_clock <= audf3_pulse when clock_input='0' else 'Z';
+	
+	pot_reset <= pot_reset_reg;
+		
+END vhdl;
+
+
Index: unmerged/core/mist/pokey_noise_filter.vhdl
===================================================================
--- unmerged/core/mist/pokey_noise_filter.vhdl	(nonexistent)
+++ unmerged/core/mist/pokey_noise_filter.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+	
+ENTITY pokey_noise_filter IS
+PORT 
+( 
+	NOISE_SELECT : IN STD_LOGIC_VECTOR(2 downto 0);
+		
+	PULSE_IN : IN STD_LOGIC;
+
+	NOISE_4 : IN STD_LOGIC;
+	NOISE_5 : IN STD_LOGIC;
+	NOISE_LARGE : IN STD_LOGIC;
+	
+	PULSE_OUT : OUT STD_LOGIC
+);
+END pokey_noise_filter;
+
+ARCHITECTURE vhdl OF pokey_noise_filter IS
+	signal pulse_noise_a : std_logic;
+	signal pulse_noise_b : std_logic;
+BEGIN
+	process(pulse_in, noise_4, noise_5, noise_large, pulse_noise_a, pulse_noise_b, noise_select)
+	begin
+		pulse_noise_a <= noise_large;
+		pulse_noise_b <= noise_5 and pulse_in;
+	
+		if (NOISE_SELECT(1) = '1') then
+			pulse_noise_a <= noise_4;
+		end if;
+	
+		if (NOISE_SELECT(2) = '1') then
+			pulse_noise_b <= pulse_in;
+		end if;
+		
+		PULSE_OUT <= pulse_noise_a and pulse_noise_b;
+
+		if (NOISE_SELECT(0) = '1') then
+			PULSE_OUT <= pulse_noise_b;
+		end if;		
+	end process;
+end vhdl;
\ No newline at end of file
Index: unmerged/core/mist/poly_4.vhdl
===================================================================
--- unmerged/core/mist/poly_4.vhdl	(nonexistent)
+++ unmerged/core/mist/poly_4.vhdl	(revision 1)
@@ -0,0 +1,50 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_4 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	INIT : IN STD_LOGIC;	
+	
+	BIT_OUT : OUT STD_LOGIC
+);
+END poly_4;
+
+ARCHITECTURE vhdl OF poly_4 IS
+	signal shift_reg: std_logic_vector(3 downto 0);
+	signal shift_next: std_logic_vector(3 downto 0);
+BEGIN
+	-- register
+	process(clk, reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "1010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(shift_reg,enable,init)
+	begin
+		shift_next <= shift_reg;
+		if (enable = '1') then
+			shift_next <= ((shift_reg(1) xnor shift_reg(0)) and not(init))&shift_reg(3 downto 1);
+		end if;
+	end process;
+	
+	-- output
+	bit_out <= not(shift_reg(0));
+		
+END vhdl;
Index: unmerged/core/mist/ramint.cmp
===================================================================
--- unmerged/core/mist/ramint.cmp	(nonexistent)
+++ unmerged/core/mist/ramint.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component ramint
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/rom16.cmp
===================================================================
--- unmerged/core/mist/rom16.cmp	(nonexistent)
+++ unmerged/core/mist/rom16.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component rom16
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/romhi.cmp
===================================================================
--- unmerged/core/mist/romhi.cmp	(nonexistent)
+++ unmerged/core/mist/romhi.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component romhi
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/romlo.cmp
===================================================================
--- unmerged/core/mist/romlo.cmp	(nonexistent)
+++ unmerged/core/mist/romlo.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component romlo
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/scandoubler.vhdl
===================================================================
--- unmerged/core/mist/scandoubler.vhdl	(nonexistent)
+++ unmerged/core/mist/scandoubler.vhdl	(revision 1)
@@ -0,0 +1,301 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY scandoubler IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	
+	VGA : IN STD_LOGIC;
+	COMPOSITE_ON_HSYNC : in std_logic;
+
+	colour_enable : in std_logic;
+	doubled_enable : in std_logic;
+	
+	-- GTIA interface
+	colour_in : in std_logic_vector(7 downto 0);
+	vsync_in : in std_logic;
+	hsync_in : in std_logic;
+	
+	-- TO TV...
+	R : OUT STD_LOGIC_vector(3 downto 0);
+	G : OUT STD_LOGIC_vector(3 downto 0);
+	B : OUT STD_LOGIC_vector(3 downto 0);
+	
+	VSYNC : out std_logic;
+	HSYNC : out std_logic
+);
+END scandoubler;
+
+ARCHITECTURE vhdl OF scandoubler IS
+
+	COMPONENT gtia_palette IS
+	PORT 
+	( 
+		ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+		
+		R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+		B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+	);
+	END component;
+	
+--	component reg_file IS
+--	generic
+--	(
+--		BYTES : natural := 1;
+--		WIDTH : natural := 1
+--	);
+--	PORT 
+--	( 
+--		CLK : IN STD_LOGIC;
+--		ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+--		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+--		WR_EN : IN STD_LOGIC;
+--		
+--		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+--	);
+--	END component;
+	
+	component scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		SYNC_RESET : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;	
+	
+	signal colour_next : std_logic_vector(7 downto 0);
+	signal colour_reg : std_logic_vector(7 downto 0);
+	
+	signal vsync_next : std_logic;
+	signal vsync_reg : std_logic;
+	
+	signal hsync_next : std_logic;
+	signal hsync_reg : std_logic;
+
+	signal r_next : std_logic_vector(7 downto 0);
+	signal g_next : std_logic_vector(7 downto 0);
+	signal b_next : std_logic_vector(7 downto 0);	
+	signal r_reg : std_logic_vector(7 downto 0);
+	signal g_reg : std_logic_vector(7 downto 0);
+	signal b_reg : std_logic_vector(7 downto 0);
+	
+	signal linea_address : std_logic_vector(10 downto 0);
+	signal linea_write_enable : std_logic;
+	signal linea_out : std_logic_vector(7 downto 0);
+
+	signal lineb_address : std_logic_vector(10 downto 0);
+	signal lineb_write_enable : std_logic;
+	signal lineb_out : std_logic_vector(7 downto 0);
+	
+	signal input_address_next : std_logic_vector(10 downto 0);
+	signal input_address_reg : std_logic_vector(10 downto 0);
+
+	signal output_address_next : std_logic_vector(10 downto 0);
+	signal output_address_reg : std_logic_vector(10 downto 0);
+	
+	signal buffer_select_next : std_logic;
+	signal buffer_select_reg : std_logic;
+	
+	signal hsync_in_reg : std_logic;
+	
+	signal vga_hsync_next : std_logic;
+	signal vga_hsync_reg : std_logic;
+	signal vga_hsync_start : std_logic;
+	signal vga_hsync_end : std_logic;
+	
+begin
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			r_reg <= (others=>'0');
+			g_reg <= (others=>'0');
+			b_reg <= (others=>'0');			
+			colour_reg <= (others=>'0');
+			hsync_reg <= '0';
+			vsync_reg <= '0';
+			
+			input_address_reg <= (others=>'0');
+			output_address_reg <= (others=>'0');
+			
+			buffer_select_reg <= '0';
+			
+			vga_hsync_reg <= '0';
+		elsif (clk'event and clk='1') then										
+			r_reg <= r_next;
+			g_reg <= g_next;
+			b_reg <= b_next;
+			colour_reg <= colour_next;
+			hsync_reg <= hsync_next;
+			vsync_reg <= vsync_next;
+		
+			input_address_reg <= input_address_next;
+			output_address_reg <= output_address_next;
+			
+			buffer_select_reg <= buffer_select_next;
+			
+			hsync_in_reg <= hsync_in;
+			
+			vga_hsync_reg <= vga_hsync_next;
+		end if;
+	end process;
+	
+	-- TODO - these should use FPGA RAM - at present about 50% of FPGA is taken by these!!!
+	--	linea : reg_file
+		--generic map (BYTES=>456,WIDTH=>9)
+		--port map (clk=>clk,addr=>linea_address,wr_en=>linea_write_enable,data_in=>colour_in,data_out=>linea_out);
+
+	--lineb : reg_file
+	--	generic map (BYTES=>456,WIDTH=>9)
+	--	port map (clk=>clk,addr=>lineb_address,wr_en=>lineb_write_enable,data_in=>colour_in,data_out=>lineb_out);	
+	
+	linea : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(linea_address)),we=>linea_write_enable,data=>colour_in,q=>linea_out);
+
+	lineb : scandouble_ram_infer
+	port map (clock=>clk,address=>to_integer(unsigned(lineb_address)),we=>lineb_write_enable,data=>colour_in,q=>lineb_out);	
+	
+	-- capture
+	process(input_address_reg,colour_enable,hsync_in,hsync_in_reg,buffer_select_reg)
+	begin
+		input_address_next <= input_address_reg;
+		buffer_select_next <= buffer_select_reg;
+		
+		linea_write_enable <= '0';
+		lineb_write_enable <= '0';
+		
+		if (colour_enable = '1') then
+			input_address_next <= std_logic_vector(unsigned(input_address_reg)+1);
+			linea_write_enable <= buffer_select_reg;
+			lineb_write_enable <= not(buffer_select_reg);
+		end if;		
+		
+		if (hsync_in = '1' and hsync_in_reg = '0') then
+				input_address_next <= (others=>'0');
+				buffer_select_next <= not(buffer_select_reg);
+		end if;		
+	end process;
+	
+	-- output
+	process(vga_hsync_reg,vga_hsync_end,output_address_reg,doubled_enable)
+	begin
+		output_address_next <= output_address_reg;
+		vga_hsync_start<='0';
+		vga_hsync_next <= vga_hsync_reg;
+		
+		if (doubled_enable = '1') then
+			output_address_next <= std_logic_vector(unsigned(output_address_reg)+1);
+			
+			if (output_address_reg = "111"&X"1F") then
+				output_address_next <= (others=>'0');
+				vga_hsync_start <= '1';
+				vga_hsync_next <= '1';
+			end if;
+		end if;
+		
+		if (vga_hsync_end = '1') then
+			vga_hsync_next <= '0';
+		end if;
+	end process;
+	
+	linea_address <= input_address_reg when buffer_select_reg='1' else output_address_reg;
+	lineb_address <= input_address_reg when buffer_select_reg='0' else output_address_reg;
+	
+	hsync_delay : delay_line
+		generic map (COUNT=>128)
+		port map(clk=>clk,sync_reset=>'0',data_in=>vga_hsync_start,enable=>doubled_enable,reset_n=>reset_n,data_out=>vga_hsync_end);			
+	
+	-- display
+	process(colour_reg,vsync_reg,vga_hsync_reg,hsync_reg,colour_in,vsync_in,hsync_in,colour_enable,doubled_enable,vga,composite_on_hsync,buffer_select_reg,linea_out,lineb_out)
+	begin	
+		colour_next <= colour_reg;
+		vsync_next <= vsync_reg;
+		hsync_next <= hsync_reg;
+		
+		if (vga = '0') then
+			-- non-vga mode - pass through
+			colour_next <= colour_in;
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(hsync_in or vsync_in);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(hsync_in xor vsync_in);
+			else
+				hsync_next <= not(hsync_in);			
+			end if;
+		else
+			-- vga mode, store all inputs - then play back!			
+			if (buffer_select_reg = '0') then
+				colour_next <= linea_out; -- todo, smoothly increase/decrease...
+			else
+				colour_next <= lineb_out;
+			end if;
+			
+			vsync_next <= not(vsync_in);
+			--hsync_next <= not(vga_hsync_reg);
+			if (composite_on_hsync = '1') then
+				hsync_next <= not(vga_hsync_reg xor vsync_in);
+			else
+				hsync_next <= not(vga_hsync_reg);			
+			end if;
+		end if;
+	end process;
+
+	-- colour palette
+--	Color             Value         Color             Value
+--Black           0,      0	Medium blue     8,    128
+--Rust            1,     16       Dark blue       9,    144
+--Red-orange      2,     32       Blue-grey      10,    160
+--Dark orange     3,     48       Olive green    11,    176
+--Red             4,     64       Medium green   12,    192
+--Dk lavender     5,     80       Dark green     13,    208
+--Cobalt blue     6,     96       Orange-green   14,    224
+--Ultramarine     7,    112       Orange         15,    240
+
+-- from altirra	
+	palette1 : entity work.gtia_palette(altirra)
+		port map (ATARI_COLOUR=>colour_reg, R_next=>R_next, G_next=>G_next, B_next=>B_next);
+		
+-- from lao
+--	palette2 : entity work.gtia_palette(laoo)
+--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
+	
+	-- output	
+		-- TODO - for DE2, output full 8 bits
+	R <= R_reg(7 downto 4);
+	G <= G_reg(7 downto 4);
+	B <= B_reg(7 downto 4);
+	
+	vsync<=vsync_reg;
+	hsync<=hsync_reg;
+
+end vhdl;
+
+
Index: unmerged/core/mist/sdram_statemachine.vhdl.bak
===================================================================
--- unmerged/core/mist/sdram_statemachine.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/sdram_statemachine.vhdl.bak	(revision 1)
@@ -0,0 +1,515 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- Toggle this to issue a new request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	REPLY : out std_logic; -- This matches the request once complete
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CKE : out std_logic;
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine;
+
+ARCHITECTURE vhdl OF sdram_statemachine IS
+	function repeat(N: natural; B: std_logic) 
+	return std_logic_vector
+	is
+	variable result: std_logic_vector(1 to N);
+	begin
+	for i in 1 to N loop
+	result(i) := B;
+	end loop;
+	return result;
+	end;
+
+	-- bits are: CS_n, RAS_n, CAS_n,WE_n
+	constant sdram_command_inhibit                  : std_logic_vector(3 downto 0) := "1000";
+	constant sdram_command_no_operation             : std_logic_vector(3 downto 0) := "0111";
+	constant sdram_command_device_burst_stop        : std_logic_vector(3 downto 0) := "0110";
+	constant sdram_command_read                     : std_logic_vector(3 downto 0) := "0101";
+	constant sdram_command_write                    : std_logic_vector(3 downto 0) := "0100";
+	constant sdram_command_bank_activate            : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
+	constant sdram_command_precharge                : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
+	constant sdram_command_mode_register            : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
+	constant sdram_command_refresh                  : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
+	
+	signal command_next : std_logic_vector(3 downto 0);
+	
+--	constant bank_state_idle                 : std_logic_vector(3 downto 0) := "0000";
+--	constant bank_state_row_active           : std_logic_vector(3 downto 0) := "0001";
+--	constant bank_state_read                 : std_logic_vector(3 downto 0) := "0010";
+--	constant bank_state_write                : std_logic_vector(3 downto 0) := "0011";
+--	constant bank_state_read_pre             : std_logic_vector(3 downto 0) := "0100";
+--	constant bank_state_write_pre            : std_logic_vector(3 downto 0) := "0101";
+--	constant bank_state_precharging          : std_logic_vector(3 downto 0) := "0111";
+--	constant bank_state_row_activating       : std_logic_vector(3 downto 0) := "1000";
+--	constant bank_state_write_recovering     : std_logic_vector(3 downto 0) := "1001";
+--	constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
+--	constant bank_state_refresh              : std_logic_vector(3 downto 0) := "1011";
+--	constant bank_state_mode_access          : std_logic_vector(3 downto 0) := "1100"; 
+--	constant bank_state_init                 : std_logic_vector(3 downto 0) := "1101"; 
+-- Banks each have their own state, but since read/write lines are shared they are not truly independent
+-- Also for auto-refresh all banks must be in idle state
+
+	constant sdram_state_powerup        : std_logic_vector(2 downto 0) := "000"; -- requires standard init
+	constant sdram_state_init           : std_logic_vector(2 downto 0) := "001"; -- requires standard init
+	constant sdram_state_idle           : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
+	constant sdram_state_refresh        : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
+	constant sdram_state_read           : std_logic_vector(2 downto 0) := "100"; -- processing a read request
+	constant sdram_state_write          : std_logic_vector(2 downto 0) := "101"; -- processing a write request
+	constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
+	
+	signal sdram_state_next : std_logic_vector(2 downto 0);
+	signal sdram_state_reg : std_logic_vector(2 downto 0);
+	
+	signal delay_next : std_logic_vector(13 downto 0);
+	signal delay_reg : std_logic_vector(13 downto 0);
+	
+	signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
+	signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
+	
+	signal refresh_pending_next : std_logic_vector(11 downto 0);
+	signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
+	
+	signal suggest_refresh : std_logic; -- i.e. do we have any pending?
+	signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
+	signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time	
+	signal refreshing_now : std_logic;
+	
+	signal idle_priority : std_logic_vector(3 downto 0);
+
+	signal data_out_next : std_logic_vector(31 downto 0);
+	signal data_out_reg : std_logic_vector(31 downto 0);
+	
+	signal reply_next : std_logic;
+	signal reply_reg : std_logic;
+	
+	-- track the active bank
+	-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
+	-- CAS,NOP,NOP,DATA
+	-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
+	--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	
+	-- capture inputs
+	signal DATA_IN_snext      : std_logic_vector(31 downto 0);
+	signal DATA_IN_sreg       : std_logic_vector(31 downto 0);
+	signal ADDRESS_IN_snext   : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal ADDRESS_IN_sreg    : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal READ_EN_snext      : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal READ_EN_sreg       : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal WRITE_EN_snext     : std_logic;
+	signal WRITE_EN_sreg      : std_logic;	
+	signal dqm_mask_snext     : std_logic_vector(3 downto 0);
+	signal dqm_mask_sreg      : std_logic_vector(3 downto 0);
+	signal request_snext      : std_logic;
+	signal request_sreg       : std_logic;
+	signal refresh_snext      : std_logic;
+	signal refresh_sreg       : std_logic;
+	
+	-- slow clock output regs
+	signal DATA_OUT_snext     : std_logic_vector(31 downto 0);
+	signal DATA_OUT_sreg      : std_logic_vector(31 downto 0);
+	
+	signal reply_snext : std_logic;
+	signal reply_sreg  : std_logic;
+	
+	-- sdram output registers 
+	signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_next : std_logic_vector(15 downto 0);
+	signal dq_output_next : std_logic;
+	signal dq_in_next  : std_logic_vector(15 downto 0);	
+	signal ba_next : std_logic_vector(1 downto 0);
+	signal cs_n_next : std_logic;
+	signal ras_n_next : std_logic;
+	signal cas_n_next : std_logic;
+	signal we_n_next : std_logic;
+	signal ldqm_next : std_logic;
+	signal udqm_next : std_logic;
+	signal cke_next : std_logic;
+	
+	signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_reg : std_logic_vector(15 downto 0);
+	signal dq_output_reg : std_logic;
+	signal ba_reg : std_logic_vector(1 downto 0);
+	signal cs_n_reg : std_logic;
+	signal ras_n_reg : std_logic;
+	signal cas_n_reg : std_logic;
+	signal we_n_reg : std_logic;
+	signal ldqm_reg : std_logic;
+	signal udqm_reg : std_logic;
+	signal cke_reg : std_logic;
+	
+BEGIN
+	-- register
+	process(CLK_SDRAM,reset_n)
+	begin
+		if (reset_N = '0') then
+			sdram_state_reg <= sdram_state_init;
+			delay_reg <= (others=>'0');
+			refresh_pending_reg <= (others=>'0');
+			cycles_since_refresh_reg <= (others=>'0');
+			data_out_reg <= (others=>'0');
+			reply_reg <= '0';
+			
+			addr_reg <= (others => '0');
+			dq_out_reg <= (others=> '0');
+			dq_output_reg <= '0';
+			ba_reg <= (others=>'0');
+			cs_n_reg <= '0';
+			ras_n_reg <= '0';
+			cas_n_reg <= '0';
+			we_n_reg <= '0';
+			ldqm_reg <= '1';
+			udqm_reg <= '1';
+			cke_reg <= '0';
+			
+			--bank_row_reg <= (others=>(others=>'0'));
+		elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
+			sdram_state_reg <= sdram_state_next;
+			delay_reg <= delay_next;
+			refresh_pending_reg <= refresh_pending_next;
+			cycles_since_refresh_reg <= cycles_since_refresh_next;
+			data_out_reg <= data_out_next;
+			reply_reg <= reply_next;
+			
+			addr_reg <= addr_next;
+			dq_out_reg <= dq_out_next;
+			dq_output_reg <= dq_output_next;
+			ba_reg <= ba_next;
+			cs_n_reg <= cs_n_next;
+			ras_n_reg <= ras_n_next;
+			cas_n_reg <= cas_n_next;
+			we_n_reg <= we_n_next;
+			ldqm_reg <=ldqm_next;
+			udqm_reg <= udqm_next;
+			cke_reg <= cke_next;
+			
+			--bank_row_reg <= bank_row_next;
+		end if;
+	end process;
+
+	-- register request	
+	process(CLK_SYSTEM,reset_n)
+	begin
+		if (reset_N = '0') then
+			data_in_sreg <= (others=>'0');
+			address_in_sreg <= (others=>'0');
+			read_en_sreg <= '0';
+			write_en_sreg <= '0';
+			request_sreg <= '0';
+			dqm_mask_sreg <= (others=>'1');
+			refresh_sreg <= '0';
+			
+			data_out_sreg <= (others=>'0');
+			reply_sreg <= '0';
+		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+			data_in_sreg <= data_in_snext;
+			address_in_sreg <= address_in_snext;
+			read_en_sreg <= read_en_snext;
+			write_en_sreg <= write_en_snext;
+			request_sreg <= request_snext;
+			dqm_mask_sreg <= dqm_mask_snext;
+			refresh_sreg <= refresh_snext;
+			
+			data_out_sreg <= data_out_snext;
+			reply_sreg <= reply_snext;
+		end if;
+	end process;
+
+	-- Inputs - NB, clocked at a smaller multiple
+	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, request, byte_access, word_access, longword_access, refresh)
+	begin
+		data_in_snext <= data_in_sreg;
+		address_in_snext <= address_in_sreg;
+		read_en_snext <= read_en_sreg;
+		write_en_snext <= write_en_sreg;
+		request_snext <= request_sreg;
+		dqm_mask_snext <= dqm_mask_sreg;
+		
+		refresh_snext <= refresh; -- independent of memory requests
+	
+		-- only snap inputs on new request
+		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+		if ((request xor request_sreg) = '1') then
+			data_in_snext <= data_in;
+			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+			read_en_snext <= read_en;
+			write_en_snext <= write_en;
+			request_snext <= request;
+			
+			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+			dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
+			dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
+		end if;
+	end process;
+	
+	-- refresh counters
+	process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
+	begin
+		cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
+		refresh_pending_next <= refresh_pending_reg;
+		suggest_refresh <= '0';
+		force_refresh <= '0';
+		
+		if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
+			suggest_refresh <= '1';
+		end if;
+		
+		if (refresh_pending_reg = X"FFF") then
+			force_refresh <= '1';
+		end if;
+		
+		require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
+		
+		if (refreshing_now = '1') then
+			-- refreshing right now
+			cycles_since_refresh_next <= (others=>'0');
+			
+			-- This is one of our pending refreshes (if we have any)			
+			if (suggest_refresh = '1') then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
+			end if;
+		else
+			if (cycles_since_refresh_reg = "11111111111") then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
+				cycles_since_refresh_next <= (others=>'0');
+			end if;
+		end if;
+
+	end process;
+	
+	--
+	process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
+	begin
+		idle_priority <= (others=>'0');
+		refreshing_now <= '0';
+	
+		sdram_state_next <= sdram_state_reg;
+		
+		command_next <= sdram_command_no_operation;
+		
+		delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
+		
+		data_out_next <= data_out_reg;
+		reply_next <= reply_reg;
+		
+		-- Set some default for when we're sending NOP
+		dq_out_next <= (others=>'0');
+		dq_output_next <= '0';
+		cke_next <= '1';
+		ldqm_next <= '1';
+		udqm_next <= '1';
+		ba_next <= (others=>'0');
+		addr_next <= (others=>'1');
+
+		-- TODO - use bank states!!
+		-- TODO - MUCH MORE SMART STUFF!
+		-- Lets do them once we have Hello World running...
+		case sdram_state_reg is
+		when sdram_state_powerup =>			
+			-- wait 100us (min)
+			if (delay_reg(13) = '1') then
+				sdram_state_next <= sdram_state_init_precharge;
+				delay_next <= (others=>'0');
+			end if;			
+		when sdram_state_init =>			
+			case delay_reg(5 downto 3)&delay_reg(0) is
+			when "0001" =>
+				command_next <= sdram_command_precharge;
+				addr_next(AP_BIT) <= '1'; --all banks
+			when "0010" =>
+				command_next <= sdram_command_refresh;				
+				-- cke still high, so auto refresh
+			when "0100" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+			when "1000" =>
+				command_next <= sdram_command_mode_register;
+				--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
+				addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
+				addr_next(3) <= '0'; -- sequential
+				addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
+				addr_next(8 downto 7) <= "00"; -- standard operation
+				addr_next(9) <= '0'; -- programmed burst access - of single cycle!
+				addr_next(11 downto 10) <= "00"; -- reserved
+			when "1010" =>
+				sdram_state_next <= sdram_state_idle;
+				delay_next <= (others=>'0');
+			when others =>
+				-- nop
+			end case;
+		when sdram_state_idle =>
+			delay_next <= (others=>'0');						
+			
+			idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
+			case idle_priority is -- priority encoder...
+			when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
+				sdram_state_next <= sdram_state_refresh;
+			when "1010"|"1011" =>				
+				sdram_state_next <= sdram_state_write;
+			when "1001" =>
+				sdram_state_next <= sdram_state_read;
+			when others =>
+				-- stay here
+			end case;
+		when sdram_state_read =>
+			-- TODO - if same bank we can save some time... ?
+			-- Only do precharge on switching bank?
+				
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_read;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+			when X"4" =>  -- command actually sent now
+				ldqm_next <= dqm_mask_sreg(0);  -- for first read
+				udqm_next <= dqm_mask_sreg(1);
+			
+			when X"5" =>  -- dqm for 1st read is sent
+				ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
+				udqm_next <= dqm_mask_sreg(3);				
+			when X"7" => 
+				data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				data_out_next(15 downto 8) <= dq_in_next(15 downto 8);				
+			when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
+				data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
+				data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
+				
+				reply_next <= request_sreg;
+				sdram_state_next <= sdram_state_idle;
+				-- after 3 cycles we can do the next ACT (21 ns psc)
+				-- TODO - directly switch to next action so as not to waste a cycle
+			when others =>
+			end case;				
+		when sdram_state_write =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_write; 
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
+				dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
+				ldqm_next <= dqm_mask_sreg(0);
+				udqm_next <= dqm_mask_sreg(1);
+			when X"4" =>
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
+				ldqm_next <= dqm_mask_sreg(2);
+				udqm_next <= dqm_mask_sreg(3);
+
+				reply_next <= request_sreg;				
+			when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
+				sdram_state_next <= sdram_state_idle;		
+				-- TODO - directly switch to next action to match read
+			when others =>
+			end case;				
+		when sdram_state_refresh =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+				refreshing_now <= '1';
+			when X"8" =>
+				sdram_state_next <= sdram_state_idle;
+			when others =>
+			end case;
+		when others =>
+			sdram_state_next <= sdram_state_init;			
+		end case;
+	end process;
+	
+	-- command_next directly translates to lines to send
+	-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
+	process(command_next)
+	begin
+		cs_n_next <= command_next(3);
+		ras_n_next <= command_next(2);
+		cas_n_next <= command_next(1);
+		we_n_next <= command_next(0);
+	end process;
+	
+	-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
+	SDRAM_ADDR <= addr_reg;
+	SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
+	SDRAM_BA0 <= ba_reg(0);
+	SDRAM_BA1 <= ba_reg(1);
+	SDRAM_CS_N <= cs_n_reg;
+	SDRAM_RAS_N <= ras_n_reg;
+	SDRAM_CAS_N <= cas_n_reg;
+	SDRAM_WE_N <= we_n_reg;
+	SDRAM_ldqm <= ldqm_reg;
+	SDRAM_udqm <= udqm_reg;
+	SDRAM_CKE <= cke_reg;
+	
+	-- inputs from SDRAM
+	dq_in_next <= SDRAM_DQ;
+	
+	-- back to slower clock
+	reply_snext <= reply_reg;
+	data_out_snext <= data_out_reg;
+	
+	-- outputs to rest of system
+	REPLY <= reply_sreg;
+	DATA_OUT <= DATA_OUT_sreg;
+		
+END vhdl;
Index: unmerged/core/mist/simple_counter.vhdl
===================================================================
--- unmerged/core/mist/simple_counter.vhdl	(nonexistent)
+++ unmerged/core/mist/simple_counter.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+-- Counter where only some bits are incremented - done in antic to save using larger adders I guess
+ENTITY simple_counter IS
+generic
+(
+	COUNT_WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_n : IN STD_LOGIC;
+	increment : in std_logic;
+	load : IN STD_LOGIC;
+	load_value : in std_logic_vector(COUNT_WIDTH-1 downto 0);
+
+	current_value : out std_logic_vector(COUNT_WIDTH-1 downto 0)
+);
+END simple_counter;
+
+ARCHITECTURE vhdl OF simple_counter IS
+	signal value_next : std_logic_vector(COUNT_WIDTH-1 downto 0);
+	signal value_reg : std_logic_vector(COUNT_WIDTH-1 downto 0);
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			value_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then			
+			value_reg <= value_next;
+		end if;
+	end process;
+
+	-- next state
+	process(increment, value_reg, load, load_value)
+	begin
+		value_next <= value_reg;
+
+		if (increment = '1') then
+			value_next <= std_logic_vector(unsigned(value_reg(COUNT_WIDTH-1 downto 0)) + 1);
+		end if;
+		
+		if (load = '1') then
+			value_next <= load_value;
+		end if;
+	end process;
+	
+	-- output
+	current_value <= value_reg;
+	
+END vhdl;
Index: unmerged/core/mist/synchronizer.vhdl
===================================================================
--- unmerged/core/mist/synchronizer.vhdl	(nonexistent)
+++ unmerged/core/mist/synchronizer.vhdl	(revision 1)
@@ -0,0 +1,39 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY synchronizer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RAW : IN STD_LOGIC;
+	SYNC : OUT STD_LOGIC
+);
+END synchronizer;
+
+ARCHITECTURE vhdl OF synchronizer IS
+	signal ff_next : std_logic_vector(2 downto 0);
+	signal ff_reg : std_logic_vector(2 downto 0);
+begin
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then						
+			ff_reg <= ff_next;	
+		end if;
+	end process;
+	
+	ff_next <= RAW&ff_reg(2 downto 1);
+	
+	SYNC <= ff_reg(0);
+
+end vhdl;
+
+
Index: unmerged/core/mist/wide_delay_line.vhdl
===================================================================
--- unmerged/core/mist/wide_delay_line.vhdl	(nonexistent)
+++ unmerged/core/mist/wide_delay_line.vhdl	(revision 1)
@@ -0,0 +1,61 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY wide_delay_line IS
+generic(COUNT : natural := 1; WIDTH : natural :=1);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	SYNC_RESET : IN STD_LOGIC;
+	DATA_IN : IN STD_LOGIC_VECTOR(WIDTH-1 downto 0);
+	ENABLE : IN STD_LOGIC; -- i.e. shift on this clock
+	RESET_N : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(WIDTH-1 downto 0)
+);
+END wide_delay_line;
+
+ARCHITECTURE vhdl OF wide_delay_line IS
+	type shift_reg_type is array(COUNT-1 downto 0) of std_logic_vector(WIDTH-1 downto 0);
+	signal shift_reg : shift_reg_type;
+	signal shift_next : shift_reg_type;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_N = '0') then
+			shift_reg <= (others=>(others=>'0'));
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+
+	-- shift on enable
+	process(shift_reg,enable,data_in,sync_reset)
+	begin
+		shift_next <= shift_reg;
+				
+		if (enable = '1') then
+			shift_next <= data_in&shift_reg(COUNT-1 downto 1);
+		end if;		
+		
+		if (sync_reset = '1') then
+			shift_next <= (others=>(others=>'0'));
+		end if;		
+	end process;
+	
+	-- output
+	gen_output:
+	for index in 0 to WIDTH-1 generate
+		data_out(index) <= shift_reg(0)(index);
+	end generate;
+		
+END vhdl;
Index: unmerged/core/mist/zpu/debug.c
===================================================================
--- unmerged/core/mist/zpu/debug.c	(nonexistent)
+++ unmerged/core/mist/zpu/debug.c	(revision 1)
@@ -0,0 +1,170 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/core/mist/zpu/led.c
===================================================================
--- unmerged/core/mist/zpu/led.c	(nonexistent)
+++ unmerged/core/mist/zpu/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/core/mist/zpu/mmc.h
===================================================================
--- unmerged/core/mist/zpu/mmc.h	(nonexistent)
+++ unmerged/core/mist/zpu/mmc.h	(revision 1)
@@ -0,0 +1,145 @@
+/*! \file mmc.h \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.h'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+///	\ingroup driver_hw
+/// \defgroup mmc MultiMedia and SD Flash Card Interface (mmc.c)
+/// \code #include "mmc.h" \endcode
+/// \par Description
+///		This library offers some simple functions which can be used
+///		to read and write data on a MultiMedia or SecureDigital (SD) Flash
+///		Card.  Although MM and SD Cards are designed to operate with their own
+///		special bus wiring and protocols, both types of cards also provide a
+///		simple SPI-like interface mode which is exceptionally useful when 
+///		attempting to use the cards in embedded systems.
+///
+/// \par Wiring
+///		To work with this library, the card must be wired to the SPI port of
+///		the Atmel microcontroller as described below.  Typical cards can
+///		operate at up to 25MHz maximum SPI clock rate (thus faster than most
+///		AVR's maximum SPI clock rate).
+/// <pre>
+///	      _________________
+///	     /  1 2 3 4 5 6 78 |	<- view of MMC/SD card looking at contacts
+///	    / 9                |	Pins 8 and 9 are present only on SD cards
+///	    |    MMC/SD Card   |
+///	    |                  |
+///	    --------------------
+///	    1 - CS   (chip select)          - wire to any available I/O pin(*)
+///	    2 - DIN  (data in, card<-host)  - wire to SPI MOSI pin
+///	    3 - VSS  (ground)               - wire to ground
+///	    4 - VDD  (power, 3.3V only?)    - wire to power (MIGHT BE 3.3V ONLY!)
+///	    5 - SCLK (data clock)           - wire to SPI SCK pin
+///	    6 - VSS  (ground)               - wire to ground
+///	    7 - DOUT (data out, card->host) - wire to SPI MISO pin
+///
+///	    (*) you must define this chip select I/O pin in mmcconf.h
+/// </pre>
+/// \note This code is currently below version 1.0, and therefore is considered
+/// to be lacking in some functionality or documentation, or may not be fully
+/// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "types.h"
+
+// constants/macros/typdefs
+// MMC commands (taken from sandisk MMC reference)
+#define MMC_GO_IDLE_STATE			0		///< initialize card to SPI-type access
+#define MMC_SEND_OP_COND			1		///< set card operational mode
+#define MMC_SEND_CSD				9		///< get card's CSD
+#define MMC_SEND_CID				10		///< get card's CID
+#define MMC_SEND_STATUS				13
+#define MMC_SET_BLOCKLEN			16		///< Set number of bytes to transfer per block
+#define MMC_READ_SINGLE_BLOCK		17		///< read a block
+#define MMC_WRITE_BLOCK				24		///< write a block
+#define MMC_PROGRAM_CSD				27
+#define MMC_SET_WRITE_PROT			28
+#define MMC_CLR_WRITE_PROT			29
+#define MMC_SEND_WRITE_PROT			30
+#define MMC_TAG_SECTOR_START		32
+#define MMC_TAG_SECTOR_END			33
+#define MMC_UNTAG_SECTOR			34
+#define MMC_TAG_ERASE_GROUP_START 	35		///< Sets beginning of erase group (mass erase)
+#define MMC_TAG_ERARE_GROUP_END		36		///< Sets end of erase group (mass erase)
+#define MMC_UNTAG_ERASE_GROUP		37		///< Untag (unset) erase group (mass erase)
+#define MMC_ERASE					38		///< Perform block/mass erase
+#define MMC_CRC_ON_OFF				59		///< Turns CRC check on/off
+// R1 Response bit-defines
+#define MMC_R1_BUSY					0x80	///< R1 response: bit indicates card is busy
+#define MMC_R1_PARAMETER			0x40
+#define MMC_R1_ADDRESS				0x20
+#define MMC_R1_ERASE_SEQ			0x10
+#define MMC_R1_COM_CRC				0x08
+#define MMC_R1_ILLEGAL_COM			0x04
+#define MMC_R1_ERASE_RESET			0x02
+#define MMC_R1_IDLE_STATE			0x01
+// Data Start tokens
+#define MMC_STARTBLOCK_READ			0xFE	///< when received from card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_WRITE		0xFE	///< when sent to card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_MWRITE		0xFC
+// Data Stop tokens
+#define MMC_STOPTRAN_WRITE			0xFD
+// Data Error Token values
+#define MMC_DE_MASK					0x1F
+#define MMC_DE_ERROR				0x01
+#define MMC_DE_CC_ERROR				0x02
+#define MMC_DE_ECC_FAIL				0x04
+#define MMC_DE_OUT_OF_RANGE			0x04
+#define MMC_DE_CARD_LOCKED			0x04
+// Data Response Token values
+#define MMC_DR_MASK					0x1F
+#define MMC_DR_ACCEPT				0x05
+#define MMC_DR_REJECT_CRC			0x0B
+#define MMC_DR_REJECT_WRITE_ERROR	0x0D
+
+// functions
+
+//! Initialize AVR<->MMC hardware interface.
+/// Prepares hardware for MMC access.
+void mmcInit(void);
+
+//! Initialize the card and prepare it for use.
+/// Returns zero if successful.
+u08 mmcReset(void);
+
+//! Send card an MMC command.
+/// Returns R1 result code.
+u08 mmcSendCommand(u08 cmd, u32 arg);
+
+//! Read 512-byte sector from card to buffer
+/// Returns zero if successful.
+u08 mmcRead(u32 sector);
+
+//! Write 512-byte sector from buffer to card
+/// Returns zero if successful.
+u08 mmcWrite(u32 sector);
+
+//! Internal command function.
+/// Issues a generic MMC command as specified by cmd and arg.
+u08 mmcCommand(u08 cmd, u32 arg);
+
+#endif
Index: unmerged/core/mist/zpu/pff.c
===================================================================
--- unmerged/core/mist/zpu/pff.c	(nonexistent)
+++ unmerged/core/mist/zpu/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/core/mist/zpu/rom_epilogue.vhd
===================================================================
--- unmerged/core/mist/zpu/rom_epilogue.vhd	(nonexistent)
+++ unmerged/core/mist/zpu/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/core/mist/pll.cmp
===================================================================
--- unmerged/core/mist/pll.cmp	(nonexistent)
+++ unmerged/core/mist/pll.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component pll
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+end component;
Index: unmerged/core/mist/pll.vhd.bak
===================================================================
--- unmerged/core/mist/pll.vhd.bak	(nonexistent)
+++ unmerged/core/mist/pll.vhd.bak	(revision 1)
@@ -0,0 +1,424 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll IS
+	PORT
+	(
+		inclk0		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		c2		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
+	);
+END pll;
+
+
+ARCHITECTURE SYN OF pll IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		clk2_divide_by		: NATURAL;
+		clk2_duty_cycle		: NATURAL;
+		clk2_multiply_by		: NATURAL;
+		clk2_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL
+	);
+	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire7_bv(0 DOWNTO 0) <= "0";
+	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
+	sub_wire4    <= sub_wire0(2);
+	sub_wire3    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	locked    <= sub_wire2;
+	c0    <= sub_wire3;
+	c2    <= sub_wire4;
+	sub_wire5    <= inclk0;
+	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 1,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 23,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 2,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 23,
+		clk1_phase_shift => "0",
+		clk2_divide_by => 1,
+		clk2_duty_cycle => 50,
+		clk2_multiply_by => 23,
+		clk2_phase_shift => "-1280",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 200000,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_UNUSED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_UNUSED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_UNUSED",
+		port_scanclkena => "PORT_UNUSED",
+		port_scandata => "PORT_UNUSED",
+		port_scandataout => "PORT_UNUSED",
+		port_scandone => "PORT_UNUSED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_USED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "OFF",
+		width_clock => 5
+	)
+	PORT MAP (
+		inclk => sub_wire6,
+		clk => sub_wire0,
+		locked => sub_wire2
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "10"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "20"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "10"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "115.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "57.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "115.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "1"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "5.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "230"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "230"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "28.70000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1.28000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1"
+-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "23"
+-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1280"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "200000"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
Index: unmerged/core/mist/pokey_mixer.vhdl.bak
===================================================================
--- unmerged/core/mist/pokey_mixer.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/pokey_mixer.vhdl.bak	(revision 1)
@@ -0,0 +1,231 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY pokey_mixer IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 downto 0);
+		
+	CHANNEL_0 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_1 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_2 : IN STD_LOGIC_VECTOR(3 downto 0);
+	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+	
+	GTIA_SOUND : IN STD_LOGIC;
+	
+	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+);
+END pokey_mixer;
+
+ARCHITECTURE vhdl OF pokey_mixer IS
+	signal volume_reg : std_logic_vector(15 downto 0);
+	signal volume_next : std_logic_vector(15 downto 0);
+	
+	signal volume_sum : std_logic_vector(5 downto 0);
+	
+	signal channel_0_en : std_logic_vector(3 downto 0);
+	signal channel_1_en : std_logic_vector(3 downto 0);
+	signal channel_2_en : std_logic_vector(3 downto 0);
+	signal channel_3_en : std_logic_vector(3 downto 0);
+	
+	signal gtia_en : std_logic_vector(5 downto 0);
+BEGIN
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			volume_reg <= volume_next;
+		end if;
+	end process;
+	
+	-- next state
+	process(channel_enable,channel_0,channel_1,channel_2,channel_3)
+	begin
+		channel_0_en <= channel_0;
+		channel_1_en <= channel_1;
+		channel_2_en <= channel_2;
+		channel_3_en <= channel_3;
+	
+--		if (channel_enable(3)='0') then
+--			channel_0_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(2)='0') then
+--			channel_1_en <= X"0";
+--		end if;
+--
+--		if (channel_enable(1)='0') then
+--			channel_2_en <= X"0";
+--		end if;
+--		
+--		if (channel_enable(0)='0') then
+--			channel_3_en <= X"0";
+--		end if;
+	end process;
+	
+	gtia_en <= "0000"&gtia_sound&gtia_sound;  -- only room for 3 more! TODO, regenerate...
+	
+	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
+	begin
+		volume_sum <= 
+			std_logic_vector
+			(
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_0_en)
+						+ unsigned('0'&CHANNEL_1_en)
+					)) 
+					+ 
+					unsigned('0'&(
+						unsigned('0'&CHANNEL_2_en) + 
+						unsigned('0'&CHANNEL_3_en)
+					))
+					+ 
+					unsigned(gtia_en)
+			);
+	end process;
+	
+	process (volume_sum)
+	begin
+		case volume_sum is 
+			when "000000" =>
+				volume_next <= X"0000";
+			when "000001" =>
+				volume_next <= X"05e4";
+			when "000010" =>
+				volume_next <= X"0b90";
+			when "000011" =>
+				volume_next <= X"1107";
+			when "000100" =>
+				volume_next <= X"1649";
+			when "000101" =>
+				volume_next <= X"1b57";
+			when "000110" =>
+				volume_next <= X"2032";
+			when "000111" =>
+				volume_next <= X"24db";
+			when "001000" =>
+				volume_next <= X"2954";
+			when "001001" =>
+				volume_next <= X"2d9d";
+			when "001010" =>
+				volume_next <= X"31b8";
+			when "001011" =>
+				volume_next <= X"35a6";
+			when "001100" =>
+				volume_next <= X"3968";
+			when "001101" =>
+				volume_next <= X"3cff";
+			when "001110" =>
+				volume_next <= X"406b";
+			when "001111" =>
+				volume_next <= X"43af";
+			when "010000" =>
+				volume_next <= X"46cc";
+			when "010001" =>
+				volume_next <= X"49c2";
+			when "010010" =>
+				volume_next <= X"4c92";
+			when "010011" =>
+				volume_next <= X"4f3e";
+			when "010100" =>
+				volume_next <= X"51c7";
+			when "010101" =>
+				volume_next <= X"542d";
+			when "010110" =>
+				volume_next <= X"5673";
+			when "010111" =>
+				volume_next <= X"5898";
+			when "011000" =>
+				volume_next <= X"5a9f";
+			when "011001" =>
+				volume_next <= X"5c88";
+			when "011010" =>
+				volume_next <= X"5e55";
+			when "011011" =>
+				volume_next <= X"6006";
+			when "011100" =>
+				volume_next <= X"619d";
+			when "011101" =>
+				volume_next <= X"631a";
+			when "011110" =>
+				volume_next <= X"647f";
+			when "011111" =>
+				volume_next <= X"65ce";
+			when "100000" =>
+				volume_next <= X"6706";
+			when "100001" =>
+				volume_next <= X"682a";
+			when "100010" =>
+				volume_next <= X"6939";
+			when "100011" =>
+				volume_next <= X"6a37";
+			when "100100" =>
+				volume_next <= X"6b22";
+			when "100101" =>
+				volume_next <= X"6bfe";
+			when "100110" =>
+				volume_next <= X"6cca";
+			when "100111" =>
+				volume_next <= X"6d88";
+			when "101000" =>
+				volume_next <= X"6e38";
+			when "101001" =>
+				volume_next <= X"6edd";
+			when "101010" =>
+				volume_next <= X"6f77";
+			when "101011" =>
+				volume_next <= X"7008";
+			when "101100" =>
+				volume_next <= X"708f";
+			when "101101" =>
+				volume_next <= X"710f";
+			when "101110" =>
+				volume_next <= X"7189";
+			when "101111" =>
+				volume_next <= X"71fe";
+			when "110000" =>
+				volume_next <= X"726e";
+			when "110001" =>
+				volume_next <= X"72db";
+			when "110010" =>
+				volume_next <= X"7347";
+			when "110011" =>
+				volume_next <= X"73b1";
+			when "110100" =>
+				volume_next <= X"741c";
+			when "110101" =>
+				volume_next <= X"7488";
+			when "110110" =>
+				volume_next <= X"74f6";
+			when "110111" =>
+				volume_next <= X"7568";
+			when "111000" =>
+				volume_next <= X"75df";
+			when "111001" =>
+				volume_next <= X"765c";
+			when "111010" =>
+				volume_next <= X"76df";
+			when "111011" =>
+				volume_next <= X"776b";
+			when "111100" =>
+				volume_next <= X"7800";				
+			when others =>
+				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+		end case;
+		
+	end process;
+			
+	-- output
+	volume_out <= volume_reg;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/poly_17_9.vhdl
===================================================================
--- unmerged/core/mist/poly_17_9.vhdl	(nonexistent)
+++ unmerged/core/mist/poly_17_9.vhdl	(revision 1)
@@ -0,0 +1,62 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY poly_17_9 IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	RESET_N : IN STD_LOGIC;
+	ENABLE : IN STD_LOGIC;
+	SELECT_9_17 : IN STD_LOGIC; -- 9 high, 17 low
+	INIT : IN STD_LOGIC;
+	
+	BIT_OUT : OUT STD_LOGIC;
+	
+	RAND_OUT : OUT std_logic_vector(7 downto 0)
+);
+END poly_17_9;
+
+ARCHITECTURE vhdl OF poly_17_9 IS
+	signal shift_reg: std_logic_vector(16 downto 0);
+	signal shift_next: std_logic_vector(16 downto 0);
+	
+	signal feedback : std_logic;
+BEGIN
+	-- register
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			shift_reg <= "01010101010101010";
+		elsif (clk'event and clk='1') then
+			shift_reg <= shift_next;
+		end if;
+	end process;
+	
+	-- next state (as pokey decap)
+	feedback <= shift_reg(13) xnor shift_reg(8);
+	process(enable,shift_reg,feedback,select_9_17,init)
+	begin
+		shift_next <= shift_reg;
+		
+		if (enable = '1') then	
+			shift_next(15 downto 8) <= shift_reg(16 downto 9);	
+			shift_next(7) <= feedback;
+			shift_next(6 downto 0) <= shift_reg(7 downto 1);
+
+			shift_next(16) <= ((feedback and select_9_17) or (shift_reg(0) and not(select_9_17))) and not(init);
+		end if;
+	end process;
+	
+		-- output
+	bit_out <= shift_reg(9);
+	RAND_OUT(7 downto 0) <= not(shift_reg(15 downto 8));
+		
+END vhdl;
Index: unmerged/core/mist/ramint.bsf
===================================================================
--- unmerged/core/mist/ramint.bsf	(nonexistent)
+++ unmerged/core/mist/ramint.bsf	(revision 1)
@@ -0,0 +1,105 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "ramint" (rect 90 0 132 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
+		(text "data[7..0]" (rect 4 18 47 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 48)
+		(input)
+		(text "wren" (rect 0 0 30 14)(font "Arial" (font_size 8)))
+		(text "wren" (rect 4 34 28 47)(font "Arial" (font_size 8)))
+		(line (pt 0 48)(pt 88 48))
+	)
+	(port
+		(pt 0 64)
+		(input)
+		(text "address[12..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
+		(text "address[12..0]" (rect 4 50 72 63)(font "Arial" (font_size 8)))
+		(line (pt 0 64)(pt 88 64)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 80 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 136 32)(line_width 3))
+	)
+	(drawing
+		(text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical))
+		(text "8192 words" (rect 120 12 214 177)(font "Arial" )(vertical))
+		(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 88 43)(pt 96 43))
+		(line (pt 96 43)(pt 96 55))
+		(line (pt 96 55)(pt 88 55))
+		(line (pt 88 55)(pt 88 43))
+		(line (pt 88 50)(pt 90 52))
+		(line (pt 90 52)(pt 88 54))
+		(line (pt 80 52)(pt 88 52))
+		(line (pt 96 48)(pt 104 48))
+		(line (pt 88 59)(pt 96 59))
+		(line (pt 96 59)(pt 96 71))
+		(line (pt 96 71)(pt 88 71))
+		(line (pt 88 71)(pt 88 59))
+		(line (pt 88 66)(pt 90 68))
+		(line (pt 90 68)(pt 88 70))
+		(line (pt 80 68)(pt 88 68))
+		(line (pt 96 64)(pt 104 64)(line_width 3))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
Index: unmerged/core/mist/reg_file.vhdl
===================================================================
--- unmerged/core/mist/reg_file.vhdl	(nonexistent)
+++ unmerged/core/mist/reg_file.vhdl	(revision 1)
@@ -0,0 +1,85 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY reg_file IS
+generic
+(
+	BYTES : natural := 1;
+	WIDTH : natural := 1
+);
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	ADDR : IN STD_LOGIC_VECTOR(width-1 DOWNTO 0);
+	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+);
+END reg_file;
+
+ARCHITECTURE vhdl OF reg_file IS
+	component complete_address_decoder IS
+	generic (width : natural := 1);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);	
+		
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+
+	type reg_file_type is array(bytes-1 downto 0) of std_LOGIC_VECTOR(7 downto 0);
+
+	signal digit_next : reg_file_type;
+	signal digit_reg : reg_file_type;
+	
+	signal addr_decoded : std_logic_vector(2**width-1 downto 0);
+BEGIN
+	complete_address_decoder1 : complete_address_decoder
+		generic map (width => WIDTH)
+		port map (addr_in => addr, addr_decoded => addr_decoded);
+
+	-- next state logic
+	process(digit_reg,addr_decoded,data_in,WR_EN)
+	begin
+		digit_next <= digit_reg;
+		
+		if (WR_EN = '1') then		
+			comp_gen:
+			for i in 0 to (BYTES-1) loop
+				if (addr_decoded(i) = '1') then				
+					digit_next(i) <= data_in;
+				end if;
+			end loop;		
+		end if;
+	end process;
+	
+	-- register
+	process(clk)
+	begin
+		if (clk'event and clk='1') then
+			digit_reg <= digit_next;
+		end if;
+	end process;
+	
+	-- output
+	process(addr_decoded,digit_reg)
+	begin
+		data_out <= X"FF";
+		comp_gen:
+		for i in 0 to (BYTES-1) loop
+			if (addr_decoded(i) = '1') then				
+				data_out <= digit_reg(i);
+			end if;
+		end loop;	
+	end process;
+		
+END vhdl;
\ No newline at end of file
Index: unmerged/core/mist/romhi.bsf
===================================================================
--- unmerged/core/mist/romhi.bsf	(nonexistent)
+++ unmerged/core/mist/romhi.bsf	(revision 1)
@@ -0,0 +1,75 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "romhi" (rect 92 0 129 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "address[12..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
+		(text "address[12..0]" (rect 4 18 72 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 80 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 136 32)(line_width 3))
+	)
+	(drawing
+		(text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical))
+		(text "8192 words" (rect 120 12 214 177)(font "Arial" )(vertical))
+		(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
Index: unmerged/core/mist/romlo.bsf
===================================================================
--- unmerged/core/mist/romlo.bsf	(nonexistent)
+++ unmerged/core/mist/romlo.bsf	(revision 1)
@@ -0,0 +1,75 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2012 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.2"))
+(symbol
+	(rect 0 0 216 128)
+	(text "romlo" (rect 92 0 129 16)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 112 25 124)(font "Arial" ))
+	(port
+		(pt 0 32)
+		(input)
+		(text "address[10..0]" (rect 0 0 82 14)(font "Arial" (font_size 8)))
+		(text "address[10..0]" (rect 4 18 72 31)(font "Arial" (font_size 8)))
+		(line (pt 0 32)(pt 88 32)(line_width 3))
+	)
+	(port
+		(pt 0 112)
+		(input)
+		(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
+		(text "clock" (rect 4 98 27 111)(font "Arial" (font_size 8)))
+		(line (pt 0 112)(pt 80 112))
+	)
+	(port
+		(pt 216 32)
+		(output)
+		(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
+		(text "q[7..0]" (rect 183 18 211 31)(font "Arial" (font_size 8)))
+		(line (pt 216 32)(pt 136 32)(line_width 3))
+	)
+	(drawing
+		(text "8 bits" (rect 109 23 191 153)(font "Arial" )(vertical))
+		(text "2048 words" (rect 120 12 214 177)(font "Arial" )(vertical))
+		(text "Block type: AUTO" (rect 48 114 170 239)(font "Arial" ))
+		(line (pt 104 24)(pt 136 24))
+		(line (pt 136 24)(pt 136 96))
+		(line (pt 136 96)(pt 104 96))
+		(line (pt 104 96)(pt 104 24))
+		(line (pt 118 58)(pt 123 63))
+		(line (pt 118 62)(pt 123 57))
+		(line (pt 88 27)(pt 96 27))
+		(line (pt 96 27)(pt 96 39))
+		(line (pt 96 39)(pt 88 39))
+		(line (pt 88 39)(pt 88 27))
+		(line (pt 88 34)(pt 90 36))
+		(line (pt 90 36)(pt 88 38))
+		(line (pt 80 36)(pt 88 36))
+		(line (pt 96 32)(pt 104 32)(line_width 3))
+		(line (pt 80 112)(pt 80 36))
+		(line (pt 0 0)(pt 217 0))
+		(line (pt 217 0)(pt 217 130))
+		(line (pt 0 130)(pt 217 130))
+		(line (pt 0 0)(pt 0 130))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+		(line (pt 0 0)(pt 0 0))
+	)
+)
Index: unmerged/core/mist/scandouble_ram_infer.vhdl
===================================================================
--- unmerged/core/mist/scandouble_ram_infer.vhdl	(nonexistent)
+++ unmerged/core/mist/scandouble_ram_infer.vhdl	(revision 1)
@@ -0,0 +1,34 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ENTITY scandouble_ram_infer IS
+   PORT
+   (
+      clock: IN   std_logic;
+      data:  IN   std_logic_vector (7 DOWNTO 0);
+      address:  IN   integer RANGE 0 to 1824;
+      we:    IN   std_logic;
+      q:     OUT  std_logic_vector (7 DOWNTO 0)
+   );
+END scandouble_ram_infer;
+
+ARCHITECTURE rtl OF scandouble_ram_infer IS
+   TYPE mem IS ARRAY(0 TO 1824) OF std_logic_vector(7 DOWNTO 0); -- TODO need 455 but this leads to glitches in the hblank
+   SIGNAL ram_block : mem;
+BEGIN
+   PROCESS (clock)
+   BEGIN
+      IF (clock'event AND clock = '1') THEN
+         IF (we = '1') THEN
+            ram_block(address) <= data;
+         END IF;
+         q <= ram_block(address);
+      END IF;
+   END PROCESS;
+END rtl;
\ No newline at end of file
Index: unmerged/core/mist/sdram_statemachine.vhdl
===================================================================
--- unmerged/core/mist/sdram_statemachine.vhdl	(nonexistent)
+++ unmerged/core/mist/sdram_statemachine.vhdl	(revision 1)
@@ -0,0 +1,526 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY sdram_statemachine IS
+generic
+(
+	ADDRESS_WIDTH : natural := 22;
+	ROW_WIDTH : natural := 12;
+	AP_BIT : natural := 10;
+	COLUMN_WIDTH : natural := 8
+);
+PORT 
+( 
+	CLK_SYSTEM : IN STD_LOGIC;
+	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+	RESET_N : in STD_LOGIC;
+	
+	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+	DATA_IN : in std_logic_vector(31 downto 0);
+	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+	WRITE_EN : in std_logic;
+	REQUEST : in std_logic; -- set true to request
+	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+	REFRESH : in std_logic;
+
+	COMPLETE : out std_logic;
+	DATA_OUT : out std_logic_vector(31 downto 0);
+
+	-- sdram itself
+	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH-1 downto 0);
+	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+	SDRAM_BA0 : out std_logic;
+	SDRAM_BA1 : out std_logic;
+	
+	SDRAM_CKE : out std_logic;
+	SDRAM_CS_N : out std_logic;
+	SDRAM_RAS_N : out std_logic;
+	SDRAM_CAS_N : out std_logic;
+	SDRAM_WE_N : out std_logic;
+	
+	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+	SDRAM_udqm : out std_logic
+);
+END sdram_statemachine;
+
+ARCHITECTURE vhdl OF sdram_statemachine IS
+	function repeat(N: natural; B: std_logic) 
+	return std_logic_vector
+	is
+	variable result: std_logic_vector(1 to N);
+	begin
+	for i in 1 to N loop
+	result(i) := B;
+	end loop;
+	return result;
+	end;
+
+	-- bits are: CS_n, RAS_n, CAS_n,WE_n
+	constant sdram_command_inhibit                  : std_logic_vector(3 downto 0) := "1000";
+	constant sdram_command_no_operation             : std_logic_vector(3 downto 0) := "0111";
+	constant sdram_command_device_burst_stop        : std_logic_vector(3 downto 0) := "0110";
+	constant sdram_command_read                     : std_logic_vector(3 downto 0) := "0101";
+	constant sdram_command_write                    : std_logic_vector(3 downto 0) := "0100";
+	constant sdram_command_bank_activate            : std_logic_vector(3 downto 0) := "0011"; -- activate copies cells to buffer for reading/writing
+	constant sdram_command_precharge                : std_logic_vector(3 downto 0) := "0010"; -- precharge copies cells from buffer back to dram
+	constant sdram_command_mode_register            : std_logic_vector(3 downto 0) := "0000"; -- e.g. burst length etc
+	constant sdram_command_refresh                  : std_logic_vector(3 downto 0) := "0001"; -- must be in idle state - call 4096 times in 64ms
+	
+	signal command_next : std_logic_vector(3 downto 0);
+	
+--	constant bank_state_idle                 : std_logic_vector(3 downto 0) := "0000";
+--	constant bank_state_row_active           : std_logic_vector(3 downto 0) := "0001";
+--	constant bank_state_read                 : std_logic_vector(3 downto 0) := "0010";
+--	constant bank_state_write                : std_logic_vector(3 downto 0) := "0011";
+--	constant bank_state_read_pre             : std_logic_vector(3 downto 0) := "0100";
+--	constant bank_state_write_pre            : std_logic_vector(3 downto 0) := "0101";
+--	constant bank_state_precharging          : std_logic_vector(3 downto 0) := "0111";
+--	constant bank_state_row_activating       : std_logic_vector(3 downto 0) := "1000";
+--	constant bank_state_write_recovering     : std_logic_vector(3 downto 0) := "1001";
+--	constant bank_state_write_recovering_pre : std_logic_vector(3 downto 0) := "1010";
+--	constant bank_state_refresh              : std_logic_vector(3 downto 0) := "1011";
+--	constant bank_state_mode_access          : std_logic_vector(3 downto 0) := "1100"; 
+--	constant bank_state_init                 : std_logic_vector(3 downto 0) := "1101"; 
+-- Banks each have their own state, but since read/write lines are shared they are not truly independent
+-- Also for auto-refresh all banks must be in idle state
+
+	constant sdram_state_powerup        : std_logic_vector(2 downto 0) := "000"; -- requires standard init
+	constant sdram_state_init           : std_logic_vector(2 downto 0) := "001"; -- requires standard init
+	constant sdram_state_idle           : std_logic_vector(2 downto 0) := "010"; -- ready to start a new request
+	constant sdram_state_refresh        : std_logic_vector(2 downto 0) := "011"; -- processing a refresh
+	constant sdram_state_read           : std_logic_vector(2 downto 0) := "100"; -- processing a read request
+	constant sdram_state_write          : std_logic_vector(2 downto 0) := "101"; -- processing a write request
+	constant sdram_state_init_precharge : std_logic_vector(2 downto 0) := "110";
+	
+	signal sdram_state_next : std_logic_vector(2 downto 0);
+	signal sdram_state_reg : std_logic_vector(2 downto 0);
+	
+	signal delay_next : std_logic_vector(13 downto 0);
+	signal delay_reg : std_logic_vector(13 downto 0);
+	
+	signal cycles_since_refresh_next : std_logic_vector(10 downto 0);
+	signal cycles_since_refresh_reg : std_logic_vector(10 downto 0); -- we expect a refresh about every 2000 cycles (approx 8ns each) - if this overflows we store the pending refresh below
+	
+	signal refresh_pending_next : std_logic_vector(11 downto 0);
+	signal refresh_pending_reg : std_logic_vector(11 downto 0); -- valid to do all 4096 once per 64ms
+	
+	signal suggest_refresh : std_logic; -- i.e. do we have any pending?
+	signal force_refresh : std_logic; -- i.e. do we NEED to refresh - up to 64ms...
+	signal require_refresh : std_logic; -- i.e. we NEED to refresh or we have some pending and the client says it is a good time	
+	signal refreshing_now : std_logic;
+	
+	signal idle_priority : std_logic_vector(3 downto 0);
+
+	signal data_out_next : std_logic_vector(31 downto 0);
+	signal data_out_reg : std_logic_vector(31 downto 0);
+	
+	signal reply_next : std_logic;
+	signal reply_reg : std_logic;
+	
+	-- track the active bank
+	-- Since we're often processing the same 512 bytes can keep the bank active and just read/write within it?
+	-- CAS,NOP,NOP,DATA
+	-- Perhaps if we're smart this can be access in one system clk cycle (4x slower than our one)
+	--signal bank_row_next : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	--signal bank_row_reg : array( downto 0) of std_logic_vector(ROW_WIDTH-1 downto 0);
+	
+	-- capture inputs
+	signal DATA_IN_snext      : std_logic_vector(31 downto 0);
+	signal DATA_IN_sreg       : std_logic_vector(31 downto 0);
+	signal ADDRESS_IN_snext   : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal ADDRESS_IN_sreg    : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
+	signal READ_EN_snext      : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal READ_EN_sreg       : std_logic; -- if no reads pending may be a good time to do a refresh
+	signal WRITE_EN_snext     : std_logic;
+	signal WRITE_EN_sreg      : std_logic;	
+	signal dqm_mask_snext     : std_logic_vector(3 downto 0);
+	signal dqm_mask_sreg      : std_logic_vector(3 downto 0);
+	signal request_snext      : std_logic;
+	signal request_sreg       : std_logic;
+	signal refresh_snext      : std_logic;
+	signal refresh_sreg       : std_logic;
+	
+	-- slow clock output regs
+	signal DATA_OUT_snext     : std_logic_vector(31 downto 0);
+	signal DATA_OUT_sreg      : std_logic_vector(31 downto 0);
+	
+	signal reply_snext : std_logic;
+	signal reply_sreg  : std_logic;
+	
+	-- sdram output registers 
+	signal addr_next : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_next : std_logic_vector(15 downto 0);
+	signal dq_output_next : std_logic;
+	signal dq_in_next  : std_logic_vector(15 downto 0);	
+	signal ba_next : std_logic_vector(1 downto 0);
+	signal cs_n_next : std_logic;
+	signal ras_n_next : std_logic;
+	signal cas_n_next : std_logic;
+	signal we_n_next : std_logic;
+	signal ldqm_next : std_logic;
+	signal udqm_next : std_logic;
+	signal cke_next : std_logic;
+	
+	signal addr_reg : std_logic_vector(ROW_WIDTH-1 downto 0);
+	signal dq_out_reg : std_logic_vector(15 downto 0);
+	signal dq_output_reg : std_logic;
+	signal ba_reg : std_logic_vector(1 downto 0);
+	signal cs_n_reg : std_logic;
+	signal ras_n_reg : std_logic;
+	signal cas_n_reg : std_logic;
+	signal we_n_reg : std_logic;
+	signal ldqm_reg : std_logic;
+	signal udqm_reg : std_logic;
+	signal cke_reg : std_logic;
+	
+	signal sdram_request_reg : std_logic;
+	signal sdram_request_next : std_logic;
+	
+BEGIN
+	-- register
+	process(CLK_SDRAM,reset_n)
+	begin
+		if (reset_N = '0') then
+			sdram_state_reg <= sdram_state_init;
+			delay_reg <= (others=>'0');
+			refresh_pending_reg <= (others=>'0');
+			cycles_since_refresh_reg <= (others=>'0');
+			data_out_reg <= (others=>'0');
+			reply_reg <= '0';
+			
+			addr_reg <= (others => '0');
+			dq_out_reg <= (others=> '0');
+			dq_output_reg <= '0';
+			ba_reg <= (others=>'0');
+			cs_n_reg <= '0';
+			ras_n_reg <= '0';
+			cas_n_reg <= '0';
+			we_n_reg <= '0';
+			ldqm_reg <= '0';
+			udqm_reg <= '0';
+			cke_reg <= '0';
+			
+			--bank_row_reg <= (others=>(others=>'0'));
+		elsif (CLK_SDRAM'event and CLK_SDRAM='1') then
+			sdram_state_reg <= sdram_state_next;
+			delay_reg <= delay_next;
+			refresh_pending_reg <= refresh_pending_next;
+			cycles_since_refresh_reg <= cycles_since_refresh_next;
+			data_out_reg <= data_out_next;
+			reply_reg <= reply_next;
+			
+			addr_reg <= addr_next;
+			dq_out_reg <= dq_out_next;
+			dq_output_reg <= dq_output_next;
+			ba_reg <= ba_next;
+			cs_n_reg <= cs_n_next;
+			ras_n_reg <= ras_n_next;
+			cas_n_reg <= cas_n_next;
+			we_n_reg <= we_n_next;
+			ldqm_reg <=ldqm_next;
+			udqm_reg <= udqm_next;
+			cke_reg <= cke_next;
+			
+			--bank_row_reg <= bank_row_next;
+		end if;
+	end process;
+
+	-- register request	
+	process(CLK_SYSTEM,reset_n)
+	begin
+		if (reset_N = '0') then
+			data_in_sreg <= (others=>'0');
+			address_in_sreg <= (others=>'0');
+			read_en_sreg <= '0';
+			write_en_sreg <= '0';
+			request_sreg <= '0';
+			dqm_mask_sreg <= (others=>'1');
+			refresh_sreg <= '0';
+			
+			data_out_sreg <= (others=>'0');
+			reply_sreg <= '0';
+			
+			sdram_request_reg <= '0';
+		elsif (CLK_SYSTEM'event and CLK_SYSTEM='1') then
+			data_in_sreg <= data_in_snext;
+			address_in_sreg <= address_in_snext;
+			read_en_sreg <= read_en_snext;
+			write_en_sreg <= write_en_snext;
+			request_sreg <= request_snext;
+			dqm_mask_sreg <= dqm_mask_snext;
+			refresh_sreg <= refresh_snext;
+			
+			data_out_sreg <= data_out_snext;
+			reply_sreg <= reply_snext;
+			
+			sdram_request_reg <= sdram_request_next;
+		end if;
+	end process;
+
+	-- Inputs - NB, clocked at a smaller multiple
+	process(data_in_sreg, address_in_sreg, read_en_sreg, write_en_sreg, request_sreg, dqm_mask_sreg, refresh_sreg, data_in, address_in, read_en, write_en, sdram_request_next, byte_access, word_access, longword_access, refresh)
+	begin
+		data_in_snext <= data_in_sreg;
+		address_in_snext <= address_in_sreg;
+		read_en_snext <= read_en_sreg;
+		write_en_snext <= write_en_sreg;
+		request_snext <= request_sreg;
+		dqm_mask_snext <= dqm_mask_sreg;
+		
+		refresh_snext <= refresh; -- independent of memory requests
+	
+		-- only snap inputs on new request
+		-- in theory I could keep the requests in a fifo so I can handle several without waiting - processed in order
+		if ((sdram_request_next xor request_sreg) = '1') then
+			data_in_snext <= data_in;
+			address_in_snext <= address_in(ADDRESS_WIDTH downto 1);
+			read_en_snext <= read_en;
+			write_en_snext <= write_en;
+			request_snext <= sdram_request_next;
+			
+			dqm_mask_snext(0) <= (byte_access or word_access) and address_in(0); -- masked on misaligned byte or word
+			dqm_mask_snext(1) <= (byte_access) and not(address_in(0)); -- masked on aligned byte only
+			dqm_mask_snext(2) <= byte_access or (word_access and not(address_in(0))); -- masked on aligned word or byte
+			dqm_mask_snext(3) <= not(longword_access); -- masked for everything except long word access
+		end if;
+	end process;
+	
+	-- refresh counters
+	process(cycles_since_refresh_reg, refresh_pending_reg, refresh_sreg, refreshing_now, force_refresh, suggest_refresh)
+	begin
+		cycles_since_refresh_next <= std_logic_vector(unsigned(cycles_since_refresh_reg)+1);
+		refresh_pending_next <= refresh_pending_reg;
+		suggest_refresh <= '0';
+		force_refresh <= '0';
+		
+		if (refresh_pending_reg > X"000") then -- refresh_pending updates before refresh completes
+			suggest_refresh <= '1';
+		end if;
+		
+		if (refresh_pending_reg = X"FFF") then
+			force_refresh <= '1';
+		end if;
+		
+		require_refresh <= force_refresh or (suggest_refresh and refresh_sreg);
+		
+		if (refreshing_now = '1') then
+			-- refreshing right now
+			cycles_since_refresh_next <= (others=>'0');
+			
+			-- This is one of our pending refreshes (if we have any)			
+			if (suggest_refresh = '1') then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) -1);
+			end if;
+		else
+			if (cycles_since_refresh_reg = "11111111111") then
+				refresh_pending_next <= std_logic_vector(unsigned(refresh_pending_reg) +1);
+				cycles_since_refresh_next <= (others=>'0');
+			end if;
+		end if;
+
+	end process;
+	
+	--
+	process(sdram_state_reg,delay_reg, idle_priority, data_out_reg, read_en_sreg, write_en_sreg, address_in_sreg, data_in_sreg, reply_reg, require_refresh, dq_in_next, dqm_mask_sreg, request_sreg)
+	begin
+		idle_priority <= (others=>'0');
+		refreshing_now <= '0';
+	
+		sdram_state_next <= sdram_state_reg;
+		
+		command_next <= sdram_command_no_operation;
+		
+		delay_next <= std_logic_vector(unsigned(delay_reg) + 1);
+		
+		data_out_next <= data_out_reg;
+		reply_next <= reply_reg;
+		
+		-- Set some default for when we're sending NOP
+		dq_out_next <= (others=>'0');
+		dq_output_next <= '0';
+		cke_next <= '1';
+		ldqm_next <= '1';
+		udqm_next <= '1';
+		ba_next <= (others=>'0');
+		addr_next <= (others=>'1');
+
+		-- TODO - use bank states!!
+		-- TODO - MUCH MORE SMART STUFF!
+		-- Lets do them once we have Hello World running...
+		case sdram_state_reg is
+		when sdram_state_powerup =>			
+			-- wait 100us (min)
+			if (delay_reg(13) = '1') then
+				sdram_state_next <= sdram_state_init_precharge;
+				delay_next <= (others=>'0');
+			end if;			
+		when sdram_state_init =>			
+			case delay_reg(5 downto 3)&delay_reg(0) is
+			when "0001" =>
+				command_next <= sdram_command_precharge;
+				addr_next(AP_BIT) <= '1'; --all banks
+			when "0010" =>
+				command_next <= sdram_command_refresh;				
+				-- cke still high, so auto refresh
+			when "0100" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+			when "1000" =>
+				command_next <= sdram_command_mode_register;
+				--addr_next(2 downto 0) <= (others=>'0'); -- burst single cycle for now
+				addr_next(2 downto 0) <= "001"; -- two cycle burst to fetch word-aligned 32-bit, misaligned 16-bit, misaligned 8-bit
+				addr_next(3) <= '0'; -- sequential
+				addr_next(6 downto 4) <= "011"; -- cas latency 3 cycles
+				addr_next(8 downto 7) <= "00"; -- standard operation
+				addr_next(9) <= '0'; -- programmed burst access - of single cycle!
+				addr_next(11 downto 10) <= "00"; -- reserved
+			when "1010" =>
+				sdram_state_next <= sdram_state_idle;
+				delay_next <= (others=>'0');
+			when others =>
+				-- nop
+			end case;
+		when sdram_state_idle =>
+			delay_next <= (others=>'0');						
+			
+			idle_priority <= (request_sreg xor reply_reg)&require_refresh&write_en_sreg&read_en_sreg;
+			case idle_priority is -- priority encoder...
+			when "0100"|"0101"|"0110"|"0111"|"1100"|"1101"|"1110"|"1111" =>
+				sdram_state_next <= sdram_state_refresh;
+			when "1010"|"1011" =>				
+				sdram_state_next <= sdram_state_write;
+			when "1001" =>
+				sdram_state_next <= sdram_state_read;
+			when others =>
+				-- stay here
+			end case;
+		when sdram_state_read =>
+			-- TODO - if same bank we can save some time... ?
+			-- Only do precharge on switching bank?
+				
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - beware of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_read;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+			when X"4" =>  -- command actually sent now
+				ldqm_next <= dqm_mask_sreg(0);  -- for first read
+				udqm_next <= dqm_mask_sreg(1);
+			
+			when X"5" =>  -- dqm for 1st read is sent
+				ldqm_next <= dqm_mask_sreg(2); -- for 2nd read
+				udqm_next <= dqm_mask_sreg(3);				
+			when X"7" => 
+				data_out_next(7 downto 0) <= (dq_in_next(7 downto 0) and not(repeat(8,dqm_mask_sreg(0)))) or (dq_in_next(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				data_out_next(15 downto 8) <= dq_in_next(15 downto 8);				
+			when X"8" => -- auto-precharge starts here after cas cycles (at this speed issi can do 2, psc can do 3 -> use slowest)
+				data_out_next(15 downto 8) <= (dq_in_next(7 downto 0) and repeat(8,dqm_mask_sreg(0))) or (data_out_reg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0))));
+				data_out_next(31 downto 16) <= dq_in_next(15 downto 0);
+				
+				reply_next <= request_sreg;
+				sdram_state_next <= sdram_state_idle;
+				-- after 3 cycles we can do the next ACT (21 ns psc)
+				-- TODO - directly switch to next action so as not to waste a cycle
+			when others =>
+			end case;				
+		when sdram_state_write =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_bank_activate;
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next <= address_in_sreg(ADDRESS_WIDTH-3 downto ADDRESS_WIDTH-3-ROW_WIDTH+1);
+			when X"3" => -- after t_rcd (18ns issi, 21ns psc) i.e. 3 cycles - before of t_ras (6 cycles before auto-precharge)
+				command_next <= sdram_command_write; 
+				ba_next <= address_in_sreg(ADDRESS_WIDTH-1 downto ADDRESS_WIDTH-2);
+				addr_next(COLUMN_WIDTH-1 downto 0) <= address_in_sreg(ADDRESS_WIDTH-3-ROW_WIDTH downto 0);
+				addr_next(AP_BIT) <= '1'; -- auto-precharge
+				
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= data_in_sreg(7 downto 0);
+				dq_out_next(15 downto 8) <= (data_in_sreg(15 downto 8) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(7 downto 0) and repeat(8,dqm_mask_sreg(0)));
+				ldqm_next <= dqm_mask_sreg(0);
+				udqm_next <= dqm_mask_sreg(1);
+			when X"4" =>
+				dq_output_next <= '1';
+				dq_out_next(7 downto 0) <= (data_in_sreg(23 downto 16) and not(repeat(8,dqm_mask_sreg(0)))) or (data_in_sreg(15 downto 8) and repeat(8,dqm_mask_sreg(0)));
+				dq_out_next(15 downto 8) <= data_in_sreg(31 downto 24);
+				ldqm_next <= dqm_mask_sreg(2);
+				udqm_next <= dqm_mask_sreg(3);
+
+				reply_next <= request_sreg;				
+			when X"6" => -- after 3 cycles we can do the next ACT (21 ns psc)
+				sdram_state_next <= sdram_state_idle;		
+				-- TODO - directly switch to next action to match read
+			when others =>
+			end case;				
+		when sdram_state_refresh =>
+			case delay_reg(3 downto 0) is
+			when X"0" =>
+				command_next <= sdram_command_refresh;
+				-- cke still high, so auto refresh
+				refreshing_now <= '1';
+			when X"8" =>
+				sdram_state_next <= sdram_state_idle;
+			when others =>
+			end case;
+		when others =>
+			sdram_state_next <= sdram_state_init;			
+		end case;
+	end process;
+	
+	-- command_next directly translates to lines to send
+	-- NB command_next is send ON NEXT CLOCK - so we get a clean clk->q with no combinational logic
+	process(command_next)
+	begin
+		cs_n_next <= command_next(3);
+		ras_n_next <= command_next(2);
+		cas_n_next <= command_next(1);
+		we_n_next <= command_next(0);
+	end process;
+	
+	-- outputs to SDRAM - because timing is tight these SHOULD ALL BE DIRECT FROM REGISTERS
+	SDRAM_ADDR <= addr_reg;
+	SDRAM_DQ <= dq_out_reg when dq_output_reg='1' else (others=>'Z');
+	SDRAM_BA0 <= ba_reg(0);
+	SDRAM_BA1 <= ba_reg(1);
+	SDRAM_CS_N <= cs_n_reg;
+	SDRAM_RAS_N <= ras_n_reg;
+	SDRAM_CAS_N <= cas_n_reg;
+	SDRAM_WE_N <= we_n_reg;
+	SDRAM_ldqm <= ldqm_reg;
+	SDRAM_udqm <= udqm_reg;
+	SDRAM_CKE <= cke_reg;
+	
+	-- inputs from SDRAM
+	dq_in_next <= SDRAM_DQ;
+	
+	-- back to slower clock
+	reply_snext <= reply_reg;
+	data_out_snext <= data_out_reg;
+	
+	-- outputs to rest of system
+	--REPLY <= reply_sreg;
+	DATA_OUT <= DATA_OUT_sreg;
+
+	-- a little sdram glue - move to sdram wrapper?
+	COMPLETE <= (reply_sreg xnor sdram_request_reg) and not(request);
+	sdram_request_next <= sdram_request_reg xor request;
+	
+END vhdl;
Index: unmerged/core/mist/shared_enable.vhdl
===================================================================
--- unmerged/core/mist/shared_enable.vhdl	(nonexistent)
+++ unmerged/core/mist/shared_enable.vhdl	(revision 1)
@@ -0,0 +1,163 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY shared_enable IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;	
+	RESET_N : IN STD_LOGIC;
+	MEMORY_READY_CPU : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	MEMORY_READY_ANTIC : IN STD_LOGIC;          -- during memory wait states keep CPU awake
+	PAUSE_6502 : in std_logic;
+	THROTTLE_COUNT_6502 : in std_logic_vector(5 downto 0);
+
+	POKEY_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same
+	ANTIC_ENABLE_179 : OUT STD_LOGIC;  -- always about 1.79MHz to keep sound the same - 1 cycle early
+	oldcpu_enable : OUT STD_LOGIC;     -- always about 1.79MHz to keep sound the same - expanded to next ready
+	CPU_ENABLE_OUT : OUT STD_LOGIC;    -- for compatibility run at 1.79MHz, for speed run as fast as we can
+	
+	SCANDOUBLER_ENABLE_LOW : OUT STD_LOGIC; -- double antic's rate - due to high-res mode
+	SCANDOUBLER_ENABLE_HIGH : OUT STD_LOGIC -- four times antic's rate - due to high-res mode
+	
+	-- antic DMA runs 1 cycle after 'enable', so ANTIC_ENABLE is delayed by 31 cycles vs CPU_ENABLE (when in 1.79MHz mode)
+	-- XXX watch out on clock speed change from 56MHz!
+);
+END shared_enable;
+
+ARCHITECTURE vhdl OF shared_enable IS
+	component enable_divider IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		ENABLE_IN : IN STD_LOGIC;
+		
+		ENABLE_OUT : OUT STD_LOGIC
+	);
+	END component;
+	
+	component delay_line IS
+	generic(COUNT : natural := 1);
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		DATA_IN : IN STD_LOGIC;
+		ENABLE : IN STD_LOGIC;
+		RESET_N : IN STD_LOGIC;
+		
+		DATA_OUT : OUT STD_LOGIC
+	);
+	END component;		
+	
+	signal enable_179 : std_logic;
+	signal enable_179_early : std_logic;
+	signal enable_179_late : std_logic;
+	signal cpu_enable : std_logic;
+	
+	signal cpu_extra_enable_next : std_logic;
+	signal cpu_extra_enable_reg : std_logic;
+	
+	signal turbo_next : std_logic;
+	signal turbo_reg : std_logic;	
+
+	signal throttle_count_next : std_logic_vector(5 downto 0);
+	signal throttle_count_reg : std_logic_vector(5 downto 0);	
+	
+	-- TODO - clean up
+	signal oldcpu_extra_enable_next : std_logic;
+	signal oldcpu_extra_enable_reg : std_logic;
+	signal enable_179_expanded : std_logic;
+	
+	signal memory_ready : std_logic;
+begin
+	-- instantiate some clock calcs
+	SCANDOUBLER_ENABLE_HIGH <= '1';
+		
+	sl_enable_colour_clock_div : enable_divider
+		generic map (COUNT=>2)
+		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
+
+	enable_179_clock_div : enable_divider
+		--generic map (COUNT=>16)
+		generic map (COUNT=>32)
+		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
+		
+	process(THROTTLE_COUNT_6502, throttle_count_reg, enable_179)
+	begin
+		turbo_next <= '0';
+		throttle_count_next <= std_logic_vector(unsigned(throttle_count_reg) + 1);
+
+		--011111/31/1f = run every 32 cycles
+		
+		if (throttle_count_reg = THROTTLE_COUNT_6502) then
+			throttle_count_next <= (others=>'0');
+			turbo_next <= '1';
+		end if;
+		
+		if (enable_179 = '1') then -- synchronize
+			throttle_count_next <= "000001";
+		end if;
+		--0000000000111111111122222222223333
+		--0123456789012345678901234567890123
+		--X-------------------------------X
+		--
+		--000000000011111111112222222222333
+		--R12345678901234567890123456789012
+		---------------------------------NT
+		
+		--000000000011111100000000001111111
+		--R12345678901234501234567890123456
+		-----------------NT--------------NT
+	end process;
+
+	delay_line_phase : delay_line
+		--generic map (COUNT=>15)
+		generic map (COUNT=>31)
+		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+
+	delay_line_phase2 : delay_line
+		--generic map (COUNT=>15)
+		generic map (COUNT=>16)
+		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+	
+	-- registers
+	process(clk,reset_n)
+	begin
+		if (reset_n = '0') then
+			cpu_extra_enable_reg <= '0';
+			oldcpu_extra_enable_reg <= '0';
+			turbo_reg <= '0';
+			throttle_count_reg <= (others=>'0');
+		elsif (clk'event and clk='1') then										
+			cpu_extra_enable_reg <= cpu_extra_enable_next;
+			oldcpu_extra_enable_reg <= oldcpu_extra_enable_next;
+			turbo_reg <= turbo_next;
+			throttle_count_reg <= throttle_count_next;
+		end if;
+	end process;
+	
+	-- next state
+	memory_ready <= memORY_READY_CPU or memORY_READY_ANTIC;
+	cpu_enable <= (turbo_reg or cpu_extra_enable_reg or enable_179) and not(pause_6502);
+	cpu_extra_enable_next <= cpu_enable and not(memory_ready);
+	
+	oldcpu_extra_enable_next <= enable_179_expanded and not(memory_ready);
+	enable_179_expanded <= oldcpu_extra_enable_reg or enable_179;
+	
+	-- output
+	POKEY_ENABLE_179 <= enable_179_late; -- aka enable_179_late!  TODO!!!
+	oldcpu_enable <= enable_179_expanded;
+	ANTIC_ENABLE_179 <= enable_179_early;
+	
+	CPU_ENABLE_OUT <= cpu_enable; -- run at 25MHz
+
+end vhdl;
Index: unmerged/core/mist/zpu/setup
===================================================================
--- unmerged/core/mist/zpu/setup	(nonexistent)
+++ unmerged/core/mist/zpu/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/core/mist/zpu/pff.h
===================================================================
--- unmerged/core/mist/zpu/pff.h	(nonexistent)
+++ unmerged/core/mist/zpu/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/core/mist/zpu/rom_prologue.vhd
===================================================================
--- unmerged/core/mist/zpu/rom_prologue.vhd	(nonexistent)
+++ unmerged/core/mist/zpu/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/core/mist/zpu/types.h
===================================================================
--- unmerged/core/mist/zpu/types.h	(nonexistent)
+++ unmerged/core/mist/zpu/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/core/mist/zpu_config_regs.vhdl
===================================================================
--- unmerged/core/mist/zpu_config_regs.vhdl	(nonexistent)
+++ unmerged/core/mist/zpu_config_regs.vhdl	(revision 1)
@@ -0,0 +1,538 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(3 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(3 downto 0);
+	
+	-- sector buffer
+	sector : out std_logic_vector(31 downto 0);
+	sector_request : out std_logic;
+	sector_ready : in std_logic;
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	signal ram_select_next : std_logic_vector(3 downto 0);
+	signal ram_select_reg : std_logic_vector(3 downto 0);
+	signal rom_select_next : std_logic_vector(3 downto 0);
+	signal rom_select_reg : std_logic_vector(3 downto 0);
+	signal gpio_enable_next : std_logic;
+	signal gpio_enable_reg : std_logic;
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+	
+	signal sector_next : std_logic_vector(31 downto 0);
+	signal sector_reg : std_logic_vector(31 downto 0);
+	signal sector_request_next : std_logic;
+	signal sector_request_reg : std_logic; -- cleared when ready asserted
+	
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				rom_select_reg <= "0010";
+				ram_select_reg <= "0010";
+				gpio_enable_reg <= '0';
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+				
+				sector_reg <= (others=>'0');
+				sector_request_reg <= '0';
+			else
+				config_6502_reg <= config_6502_next;
+				rom_select_reg <= rom_select_next;
+				ram_select_reg <= ram_select_next;
+				gpio_enable_reg <= gpio_enable_next;			
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+				
+				sector_reg <= sector_next;
+				sector_request_reg <= sector_request_next;				
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_ATARI: 
+	-- 	R/W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	--    R/W(8-11 bits) - XX 00=64k,01=128K,10=320K Compy,11=320K Rambo
+	--    R/W(12-15 bits) - XX 00=XL, 01=XL turbo, 10=OS B/debugger, 11=OS B turbo
+	--	   R/W(16-20 bits) - XXXG= G:0=GPIO_OFF,1=GPIO_ON(ISH!)
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	-- SECTOR
+	--   W(32 bits) - write here initiates a request_reset_zpu
+	--   R: 0=request_active
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, rom_select_reg, ram_select_reg, gpio_enable_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg, sector_request_reg, sector_ready, sector_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		rom_select_next <= rom_select_reg;
+		ram_select_next <= ram_select_reg;
+		gpio_enable_next <= gpio_enable_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		sector_next <= sector_reg;
+		sector_request_next <= sector_request_reg and not(sector_ready);
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+				ram_select_next <= cpu_DATA_IN(11 downto 8);
+				rom_select_next <= cpu_DATA_IN(15 downto 12);
+				gpio_enable_next <= cpu_DATA_IN(16);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+			if(addr_decoded(11) = '1') then
+				sector_next <= cpu_data_in;
+				sector_request_next <= '1';
+			end if;
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg, config_6502_reg, ram_select_reg, rom_select_reg, gpio_enable_reg, sector_request_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(0) = '1') then
+				data_out(7 downto 0) <= config_6502_reg;
+				data_out(11 downto 8) <= ram_select_reg;
+				data_out(15 downto 12) <= rom_select_reg;
+				data_out(16) <= gpio_enable_reg;
+			end if;
+			
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= (others=>'0'); -- TODO - enable SD.
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= key;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				--data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+			
+			if (addr_decoded(11) = '1') then
+				data_out(0) <= sector_request_reg;
+			end if;			
+			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1'; -- TODO
+	--USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	USE_SDRAM <= '1'; -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= ram_select_reg;
+	VGA <= '1';
+	COMPOSITE_ON_HSYNC <= '0';
+	GPIO_ENABLE <= '0'; -- enable gpio - FIXME - esp carts!
+	ROM_SELECT <= rom_select_reg;
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+	
+	sector <= sector_reg;
+	sector_request <= sector_request_reg;
+end vhdl;
+
+
Index: unmerged/core/mist/zpu_glue.vhdl.bak
===================================================================
--- unmerged/core/mist/zpu_glue.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/zpu_glue.vhdl.bak	(revision 1)
@@ -0,0 +1,332 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+library work;
+use work.zpupkg.all;
+
+ENTITY zpu_glue IS
+PORT 
+(
+	CLK : in std_logic;
+	RESET : in std_logic;
+	PAUSE : in std_logic;
+
+	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
+	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+	
+	ZPU_DO : out std_logic_vector(31 downto 0);
+	
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
+	
+	-- request
+	MEMORY_FETCH : out std_logic;
+	ZPU_READ_ENABLE : out std_logic;
+	ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
+	ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
+	
+	-- config
+	ZPU_CONFIG_WRITE : out std_logic;
+	
+	-- stack request
+	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+	
+	-- response
+	MEMORY_READY : in std_logic
+);
+END zpu_glue;
+
+architecture sticky of zpu_glue is
+component ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=24;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=16;  -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+	end component;	
+			
+	signal zpu_addr_unsigned : unsigned(23 downto 0);
+	signal zpu_do_unsigned : unsigned(31 downto 0);
+	signal ZPU_DI_unsigned : unsigned(31 downto 0);
+	signal zpu_break : std_logic;
+	signal zpu_debug : zpu_dbgo_t;
+	
+	signal zpu_mem_busy : std_logic;
+	
+	signal zpu_memory_fetch_pending_next : std_logic;
+	signal zpu_memory_fetch_pending_reg : std_logic;
+	
+	signal ZPU_32bit_READ_ENABLE_temp : std_logic;
+	signal ZPU_8bit_READ_ENABLE_temp : std_logic;	
+	signal ZPU_READ_temp : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;	
+	signal ZPU_WRITE_temp : std_logic;
+	
+	signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;	
+	signal ZPU_READ_next : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;	
+	signal ZPU_READ_reg : std_logic;
+	
+	signal block_mem : std_logic;
+	signal config_mem : std_logic;
+	
+	signal result_next : std_logic_vector(3 downto 0);
+	signal result_reg : std_logic_vector(3 downto 0);
+	constant result_external : std_logic_vector(3 downto 0) := "0000";
+	constant result_ram : std_logic_vector(3 downto 0) := "0001";
+	constant result_ram_8bit_0 : std_logic_vector(3 downto 0) := "0010";
+	constant result_ram_8bit_1 : std_logic_vector(3 downto 0) := "0011";
+	constant result_ram_8bit_2 : std_logic_vector(3 downto 0) := "0100";
+	constant result_ram_8bit_3 : std_logic_vector(3 downto 0) := "0101";
+	constant result_rom : std_logic_vector(3 downto 0) := "0110";
+	constant result_rom_8bit_0 : std_logic_vector(3 downto 0) := "0111";
+	constant result_rom_8bit_1 : std_logic_vector(3 downto 0) := "1000";
+	constant result_rom_8bit_2 : std_logic_vector(3 downto 0) := "1001";
+	constant result_rom_8bit_3 : std_logic_vector(3 downto 0) := "1010";	
+	constant result_config : std_logic_vector(3 downto 0) := "1011";	
+
+	signal request_type : std_logic_vector(4 downto 0);
+	
+	signal zpu_di_use : std_logic_vector(31 downto 0);
+	
+	signal memORY_ACCESS : std_logic;
+
+	-- 1 cycle delay on memory read - needed to allow running at higher clock
+	signal zpu_di_next : std_logic_vector(31 downto 0);
+	signal zpu_di_reg : std_logic_vector(31 downto 0);
+	
+	signal memory_ready_next : std_logic;
+	signal memory_ready_reg : std_logic;
+	
+	signal zpu_enable : std_logic;
+	
+	signal zpu_addr_next : std_logic_vector(23 downto 0);
+	signal zpu_addr_reg : std_logic_vector(23 downto 0);
+	
+begin
+		-- register
+	process(clk,reset)
+	begin
+		if (reset='1') then
+			zpu_memory_fetch_pending_reg <= '0';
+			result_reg <= result_rom;
+			zpu_di_reg <= (others=>'0');
+			memory_ready_reg <= '0';
+			zpu_addr_reg <= (others=>'0');
+			ZPU_32BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_16BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_8BIT_WRITE_ENABLE_reg <= '0';	
+			ZPU_READ_reg <= '0';
+		elsif (clk'event and clk='1') then
+			zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
+			result_reg <= result_next;
+			zpu_di_reg <= zpu_di_next;
+			memory_ready_reg <= memORY_READY_next;
+			zpu_addr_reg <=zpu_addr_next;
+			ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
+			ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
+			ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
+			ZPU_READ_reg <= ZPU_READ_next;
+		end if;
+	end process;
+
+-- a little glue
+	process(zpu_ADDR_unsigned)
+	begin
+		block_mem <= '0';
+		config_mem <= '0';
+		-- $00000-$0FFFF = Own ROM/RAM
+		-- $10000-$1FFFF = Atari
+		-- $20000-$2FFFF = Config area
+		if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
+			block_mem <= zpu_addr_unsigned(17) nor zpu_addr_unsigned(16);
+			config_mem <= zpu_addr_unsigned(17);
+		end if;	
+	end process;
+
+	ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
+	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp
+			  )
+	begin
+		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+		result_next <= result_reg;
+		memory_ready_next <= memory_ready;
+		zpu_stACK_WRITE <= (others=>'0');
+		ZPU_config_write <= '0';
+		zpu_addr_next <= zpu_addr_reg;
+	
+		ZPU_MEM_BUSY <= pause;
+		
+		MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
+		
+		memory_fetch <= zpu_memory_fetch_pending_reg;
+		
+		zpu_read_next <= zpu_read_reg;
+		zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
+		zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
+		zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;	
+		
+		request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
+		case request_type is
+			when "00010"|"00110" =>
+				zpu_memory_fetch_pending_next <= '1';
+				result_next <= result_external;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+				zpu_read_next <= zpu_read_temp;
+				zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
+				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+			when "01010" =>
+				if (zpu_8bit_read_enable_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_rom_8bit_3;										
+					when "01" =>
+						result_next <= result_rom_8bit_2;
+					when "10" =>
+						result_next <= result_rom_8bit_1;										
+					when "11" =>
+						result_next <= result_rom_8bit_0;
+					end case;
+				else
+					result_next <= result_rom;
+				end if;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "01110" =>
+				if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_ram_8bit_3;										
+						ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
+					when "01" =>
+						result_next <= result_ram_8bit_2;
+						ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
+					when "10" =>
+						result_next <= result_ram_8bit_1;					
+						ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;					
+					when "11" =>
+						result_next <= result_ram_8bit_0;
+						ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
+					end case;
+				else
+					result_next <= result_ram;
+					ZPU_STACK_WRITE <= (others=>zpu_write_temp);					
+				end if;
+				ZPU_MEM_BUSY <= '1';				
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "10110"|"10010" =>
+				result_next <= result_config;
+				ZPU_MEM_BUSY <= '1';
+				ZPU_config_write <= ZPU_WRITE_temp; 
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);				
+			when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
+				  "10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111" =>
+				ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
+				zpu_memory_fetch_pending_next <= not(memORY_READY);
+			when others =>
+				-- keep
+		end case;
+	end process;
+
+	zpu_di_next <= zpu_di;
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di)
+	begin
+		zpu_di_use <= (others=>'0');
+		case result_reg is 
+			when result_external =>
+				zpu_di_use <= zpu_di_reg;
+			when result_rom =>
+				zpu_di_use <= zpu_rom_DI;
+			when result_rom_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
+			when result_rom_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
+			when result_rom_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
+			when result_rom_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);				
+			when result_ram =>
+				zpu_di_use <= zpu_ram_DI;
+			when result_ram_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
+			when result_ram_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
+			when result_ram_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+			when result_ram_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
+			when result_config =>
+				zpu_di_use <= zpu_config_di;
+			when others =>
+				-- nothing
+		end case;
+	end process;
+
+-- zpu itself
+	--zpu_enable <= enable and not(pause);
+	zpu_enable <= '1'; -- does nothing useful...
+	
+myzpu: ZPUMediumCore
+	port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
+	data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
+	byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
+	
+	zpu_di_unsigned <= unsigned(zpu_di_use);
+	zpu_do <= std_logic_vector(zpu_do_unsigned);
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_FETCH <= zpu_addr_reg;
+		
+	zpu_read_enable <= zpu_read_reg;
+	zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
+	zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
+	zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
+
+end sticky;
Index: unmerged/core/mist/zpu_rom.cmp
===================================================================
--- unmerged/core/mist/zpu_rom.cmp	(nonexistent)
+++ unmerged/core/mist/zpu_rom.cmp	(revision 1)
@@ -0,0 +1,23 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component zpu_rom
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/zpu/standalone_simple.ld
===================================================================
--- unmerged/core/mist/zpu/standalone_simple.ld	(nonexistent)
+++ unmerged/core/mist/zpu/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/core/mist/zpu/zpuromgen.c
===================================================================
--- unmerged/core/mist/zpu/zpuromgen.c	(nonexistent)
+++ unmerged/core/mist/zpu/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/core/mist/zpu/spi.h
===================================================================
--- unmerged/core/mist/zpu/spi.h	(nonexistent)
+++ unmerged/core/mist/zpu/spi.h	(revision 1)
@@ -0,0 +1,65 @@
+/*! \file spi.h \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.h'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup driver_avr
+/// \defgroup spi SPI (Serial Peripheral Interface) Function Library (spi.c)
+/// \code #include "spi.h" \endcode
+/// \par Overview
+///		Provides basic byte and word transmitting and receiving via the AVR
+///	SPI interface.� Due to the nature of SPI, every SPI communication operation
+/// is both a transmit and simultaneous receive.
+///
+///	\note Currently, only MASTER mode is supported.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef SPI_H
+#define SPI_H
+
+#include "types.h"
+
+// function prototypes
+void mmcChipSelect(int select);
+
+
+// SPI interface initializer
+void spiInit(void);
+
+// spiTransferByte(u08 data) waits until the SPI interface is ready
+// and then sends a single byte over the SPI port.  The function also
+// returns the byte that was received during transmission.
+u08 spiTransferByte(u08 data);
+
+// spiTransferWord(u08 data) works just like spiTransferByte but
+// operates on a whole word (16-bits of data).
+u08 spiTransferFF();
+void spiTransferTwoFF();
+
+void spiDisplay(int i);
+
+#endif
Index: unmerged/core/mist/zpu/uart.h
===================================================================
--- unmerged/core/mist/zpu/uart.h	(nonexistent)
+++ unmerged/core/mist/zpu/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/core/mist/zpu_core.vhd
===================================================================
--- unmerged/core/mist/zpu_core.vhd	(nonexistent)
+++ unmerged/core/mist/zpu_core.vhd	(revision 1)
@@ -0,0 +1,961 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Medium                                                          ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the medium size version.  ----
+----  Supports external memories.                                         ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      ZPUMediumCore(Behave) (Entity and architecture)    ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+----                   zpu.zpupkg                                         ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+--
+-- write_en_o   - set to '1' for a single cycle to send off a write request.
+--                data_o is valid only while write_en_o='1'.
+-- read_en_o    - set to '1' for a single cycle to send off a read request.
+-- mem_busy_i   - It is illegal to send off a read/write request when
+--                mem_busy_i='1'.
+--                Set to '0' when data_i  is valid after a read request.
+--                If it goes to '1'(busy), it is on the cycle after read/
+--                write_en_o is '1'.
+-- addr_o       - address for read/write request
+-- data_i       - read data. Valid only on the cycle after mem_busy_i='0'
+--                after read_en_o='1' for a single cycle.
+-- data_o       - data to write
+-- break_o      - set to '1' when CPU hits break instruction
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+library zpu;
+use zpu.zpupkg.all;
+
+entity ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+end entity ZPUMediumCore;
+
+architecture Behave of ZPUMediumCore is
+   constant BYTE_BITS    : integer:=WORD_SIZE/16; -- # of bits in a word that addresses bytes
+   constant WORD_BYTES   : integer:=WORD_SIZE/OPCODE_W;
+   constant MAX_ADDR_BIT : integer:=ADDR_W-2;
+   -- Stack Pointer initial value: BRAM size-8
+   constant SP_START_1   : unsigned(ADDR_W-1 downto 0):=to_unsigned((2**MEM_W)-8,ADDR_W);
+   constant SP_START     : unsigned(ADDR_W-1 downto BYTE_BITS):=
+                           SP_START_1(ADDR_W-1 downto BYTE_BITS);
+
+   -- Update [SP+1]. We hold it in b_r, this writes the value to memory.
+   procedure FlushB(signal we     : out std_logic;
+                    signal addr   : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal inc_sp : in  unsigned(ADDR_W-1 downto BYTE_BITS);
+                    signal data   : out unsigned(WORD_SIZE-1 downto 0);
+                    signal b      : in  unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      we   <= '1';
+      addr <= inc_sp;
+      data <= b;
+   end procedure FlushB;
+
+   -- Do a simple stack push, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Push(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                  signal a      : in    unsigned(WORD_SIZE-1 downto 0);
+                  signal b      : out   unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      b  <= a;      -- Update cache [SP+1]=[SP]
+      sp <= sp-1;
+   end procedure Push;
+
+   -- Do a simple stack pop, it is performed in the internal cache registers,
+   -- not in the real memory.
+   procedure Pop(signal sp     : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                 signal a      : out   unsigned(WORD_SIZE-1 downto 0);
+                 signal b      : in    unsigned(WORD_SIZE-1 downto 0)) is
+   begin
+      a  <= b;      -- Update cache [SP]=[SP+1]
+      sp <= sp+1;
+   end procedure Pop;
+
+   -- Expand a PC value to WORD_SIZE
+   function ExpandPC(v : unsigned(ADDR_W-1 downto 0)) return unsigned is
+      variable nv : unsigned(WORD_SIZE-1 downto 0);
+   begin
+      nv:=(others => '0');
+      nv(ADDR_W-1 downto 0):=v;
+      return nv;
+   end function ExpandPC;
+
+   -- Program counter
+   signal pc_r          : unsigned(ADDR_W-1 downto 0):=(others => '0');
+   -- Stack pointer
+   signal sp_r          : unsigned(ADDR_W-1 downto BYTE_BITS):=SP_START;
+   -- SP+1, SP+2 and SP-1 are very used, these are shortcuts
+   signal inc_sp        : unsigned(ADDR_W-1 downto BYTE_BITS);
+   signal inc_inc_sp    : unsigned(ADDR_W-1 downto BYTE_BITS);
+   -- a_r is a cache for the top of the stack [SP]
+   -- Note: as this is a stack CPU this is a very important register.
+   signal a_r           : unsigned(WORD_SIZE-1 downto 0);
+   -- b_r is a cache for the next value in the stack [SP+1]
+   signal b_r           : unsigned(WORD_SIZE-1 downto 0);
+   signal bin_op_res1_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal bin_op_res2_r : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_res1_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res2_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_res3_r   : unsigned(WORD_SIZE-1 downto 0);
+   signal mult_a_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal mult_b_r      : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   signal idim_r        : std_logic;
+   signal write_en_r    : std_logic;
+	signal byte_read_r  : std_logic;
+	signal byte_write_r  : std_logic;
+	signal short_write_r : std_logic;
+   signal read_en_r     : std_logic;
+   signal addr_r        : unsigned(ADDR_W-1 downto BYTE_BITS):=(others => '0');
+	signal addrl_r        : unsigned(BYTE_BITS-1 downto 0):=(others => '0');
+   signal fetched_w_r   : unsigned(WORD_SIZE-1 downto 0);
+
+   type state_t is(st_load2, st_popped, st_load_sp2, st_load_sp3, st_add_sp2,
+                   st_fetch, st_execute, st_decode, st_decode2, st_resync,
+                   st_store_sp2, st_resync2, st_resync3, st_loadb2,
+                   st_mult2, st_mult3, st_mult5, st_mult4, st_binary_op_res2,
+                   st_binary_op_res, st_idle); 
+   signal state : state_t:=st_resync;
+
+   -- Go to st_fetch state or just do its work
+   procedure DoFetch(constant FAST   : boolean;
+                     signal state    : out state_t;
+                     signal addr     : out unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal pc       : in  unsigned(ADDR_W-1 downto 0);
+                     signal re       : out std_logic;
+                     signal busy     : in  std_logic) is
+   begin
+      if FAST then
+         -- Equivalent to st_fetch
+         if busy='0' then
+            addr  <= pc(ADDR_W-1 downto BYTE_BITS);
+            re    <= '1';
+            state <= st_decode;
+         end if;
+      else
+         state <= st_fetch;
+      end if;
+   end procedure DoFetch;
+
+   -- Perform a "binary operation" (2 operands)
+   procedure DoBinOp(result         : in    unsigned(WORD_SIZE-1 downto 0);
+                     signal state   : out   state_t;
+                     signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                     signal re      : out   std_logic;
+                     signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                     signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                     constant DEPTH :       natural) is
+   begin
+      if DEPTH=2 then
+         -- 2 clocks: st_binary_op_res+st_binary_op_res2
+         state  <= st_binary_op_res;
+         dest_p <= result;
+      elsif DEPTH=1 then
+         -- 1 clock: st_binary_op_res2
+         state  <= st_binary_op_res2;
+         dest_p <= result;
+      else -- 0 clocks
+         re    <= '1';
+         addr  <= sp+2;
+         sp    <= sp+1;
+         dest  <= result;
+         state <= st_popped;
+      end if;
+   end procedure DoBinOp;
+
+   -- Perform a boolean "binary operation" (2 operands)
+   procedure DoBinOpBool(result         : in    boolean;
+                         signal state   : out   state_t;
+                         signal sp      : inout unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal addr    : out   unsigned(ADDR_W-1 downto BYTE_BITS);
+                         signal re      : out   std_logic;
+                         signal dest    : out   unsigned(WORD_SIZE-1 downto 0);
+                         signal dest_p  : out   unsigned(WORD_SIZE-1 downto 0);
+                         constant DEPTH :       natural) is
+      variable res : unsigned(WORD_SIZE-1 downto 0):=(others => '0');
+   begin
+      if result then
+         res(0):='1';
+      end if;
+      DoBinOp(res,state,sp,addr,re,dest,dest_p,DEPTH);
+   end procedure DoBinOpBool;
+
+   type insn_t is (dec_add_top, dec_dup, dec_dup_stk_b, dec_pop, dec_add,
+                   dec_or, dec_and, dec_store, dec_add_sp, dec_shift, dec_nop,
+                   dec_im, dec_load_sp, dec_store_sp, dec_emulate, dec_load,
+                   dec_push_sp, dec_pop_pc, dec_pop_pc_rel, dec_not, dec_flip,
+                   dec_pop_sp, dec_neq_branch, dec_eq, dec_loadb, dec_mult,
+                   dec_less_than, dec_less_than_or_equal, dec_lshr,
+                   dec_u_less_than_or_equal, dec_u_less_than, dec_push_sp_add,
+                   dec_call, dec_call_pc_rel, dec_sub, dec_break, dec_storeb,
+                   dec_insn_fetch, dec_pop_down);
+   signal insn : insn_t;
+   type insn_array_t is array(0 to WORD_BYTES-1) of insn_t;
+   signal insns : insn_array_t;
+   type opcode_array_t is array(0 to WORD_BYTES-1) of unsigned(OPCODE_W-1 downto 0);
+   signal opcode_r : opcode_array_t;
+begin
+   -- the memory subsystem will tell us one cycle later whether or
+   -- not it is busy
+   write_en_o <= write_en_r;
+   read_en_o  <= read_en_r;
+	byte_read_o  <= byte_read_r;
+	byte_write_o  <= byte_write_r;
+	short_write_o  <= short_write_r;
+   addr_o(ADDR_W-1 downto BYTE_BITS) <= addr_r;
+   addr_o(BYTE_BITS-1 downto 0)      <= addrl_r;
+
+   -- SP+1 and +2
+   inc_sp     <= sp_r+1;
+   inc_inc_sp <= sp_r+2;
+
+   opcode_control:
+   process (clk_i)
+      variable topcode     : unsigned(OPCODE_W-1 downto 0);
+      variable ex_opcode   : unsigned(OPCODE_W-1 downto 0);
+      variable sp_offset   : unsigned(4 downto 0);
+      variable tsp_offset  : unsigned(4 downto 0);
+      variable next_pc     : unsigned(ADDR_W-1 downto 0);
+      variable tdecoded    : insn_t;
+      variable tinsns   : insn_array_t;
+      variable mult_res    : unsigned(WORD_SIZE*2-1 downto 0);
+      variable ipc_low     : integer range 0 to 3; -- Address inside a word (pc_r)
+      variable inpc_low    : integer range 0 to 3; -- Address inside a word (next_pc)
+      variable not_lshr    : std_logic:='1';
+   begin
+      if rising_edge(clk_i) then
+         break_o <= '0';
+         if reset_i='1' then
+            if ENA_IDLE then
+               state <= st_idle;
+            else
+               state <= st_resync;
+            end if;
+            sp_r         <= SP_START;
+            pc_r         <= (others => '0');
+            idim_r       <= '0';
+            write_en_r   <= '0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            read_en_r    <= '0';
+            mult_a_r     <= (others => '0');
+            mult_b_r     <= (others => '0');
+            dbg_o.b_inst <= '0';
+            -- Reseting add_r here makes XST fail to use BRAMs ?!
+         else -- reset_i='1'
+            if MULT_PIPE then
+               -- We must multiply unconditionally to get pipelined multiplication
+               mult_res:=mult_a_r*mult_b_r;
+               mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+               mult_res2_r <= mult_res1_r;
+               mult_res3_r <= mult_res2_r;
+               mult_a_r    <= (others => D_CARE_VAL);
+               mult_b_r    <= (others => D_CARE_VAL);
+            end if;
+
+            if BINOP_PIPE=2 then
+               bin_op_res2_r <= bin_op_res1_r; -- pipeline a bit.
+            end if;
+   
+            read_en_r  <='0';
+            write_en_r <='0';
+				byte_read_r <= '0';
+				byte_write_r <= '0';
+				short_write_r <= '0';
+            -- Allow synthesis tools to load bogus values when we don't
+            -- care about the address and output data.
+            addr_r     <= (others => D_CARE_VAL);
+            data_o     <= (others => D_CARE_VAL);
+				addrl_r    <= "00";
+   
+            if (write_en_r='1') and (read_en_r='1') then
+               report "read/write collision" severity failure;
+            end if;
+
+            ipc_low:=to_integer(pc_r(BYTE_BITS-1 downto 0));
+            sp_offset(4):=not opcode_r(ipc_low)(4);
+            sp_offset(3 downto 0):=opcode_r(ipc_low)(3 downto 0);
+            next_pc:=pc_r+1;
+   
+            -- Prepare trace snapshot
+            dbg_o.opcode <= opcode_r(ipc_low);
+            dbg_o.pc     <= resize(pc_r,32);
+            dbg_o.stk_a  <= resize(a_r,32);
+            dbg_o.stk_b  <= resize(b_r,32);
+            dbg_o.b_inst <= '0';
+            dbg_o.sp     <= (others => '0');
+            dbg_o.sp(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+   
+            case state is
+                 when st_idle =>
+                      if enable_i='1' then
+                         state <= st_resync;
+                      end if;
+                 -- Initial state of ZPU, fetch top of stack (A/B) + first instruction
+                 when st_resync =>
+                      if mem_busy_i='0' then
+                         addr_r    <= sp_r;
+                         read_en_r <= '1';
+                         state     <= st_resync2;
+                      end if;
+                 when st_resync2 =>
+                      if mem_busy_i='0' then
+                         a_r       <= data_i;
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_resync3;
+                      end if;
+                 when st_resync3 =>
+                      if mem_busy_i='0' then
+                         b_r       <= data_i;
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 when st_decode =>
+                      if mem_busy_i='0' then
+                         -- Here we latch the fetched word to give one full clock
+                         -- cycle to the instruction decoder. This could be removed
+                         -- if using BRAMs and the decoder delay isn't important.
+                         fetched_w_r <= data_i;
+                         state       <= st_decode2;
+                      end if;
+                 when st_decode2 =>
+                      -- decode 4 instructions in parallel
+                      for i in 0 to WORD_BYTES-1 loop
+                          topcode:=fetched_w_r((WORD_BYTES-1-i+1)*8-1 downto (WORD_BYTES-1-i)*8);
+
+                          tsp_offset(4):=not topcode(4);
+                          tsp_offset(3 downto 0):=topcode(3 downto 0);
+
+                          opcode_r(i) <= topcode;
+                          if topcode(7 downto 7)=OPCODE_IM then
+                             tdecoded:=dec_im;
+                          elsif topcode(7 downto 5)=OPCODE_STORESP then
+                             if tsp_offset=0 then
+                                -- Special case, we can avoid a write
+                                tdecoded:=dec_pop;
+                             elsif tsp_offset=1 then
+                                -- Special case, collision
+                                tdecoded:=dec_pop_down;
+                             else
+                                tdecoded:=dec_store_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_LOADSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_dup;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_dup_stk_b;
+                             else
+                                tdecoded:=dec_load_sp;
+                             end if;
+                          elsif topcode(7 downto 5)=OPCODE_EMULATE then
+                             tdecoded:=dec_emulate;
+                             if ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_NEQBRANCH then
+                                tdecoded:=dec_neq_branch;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_EQ then
+                                tdecoded:=dec_eq;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_LOADB then
+                                tdecoded:=dec_loadb;
+                             elsif ENA_LEVEL0 and topcode(5 downto 0)=OPCODE_PUSHSPADD then
+                                tdecoded:=dec_push_sp_add;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_LESSTHAN then
+                                tdecoded:=dec_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_ULESSTHAN then
+                                tdecoded:=dec_u_less_than;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_MULT then
+                                tdecoded:=dec_mult;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_STOREB then
+                                tdecoded:=dec_storeb;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_CALLPCREL then
+                                tdecoded:=dec_call_pc_rel;
+                             elsif ENA_LEVEL1 and topcode(5 downto 0)=OPCODE_SUB then
+                                tdecoded:=dec_sub;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_LESSTHANOREQUAL then
+                                tdecoded:=dec_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_ULESSTHANOREQUAL then
+                                tdecoded:=dec_u_less_than_or_equal;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_CALL then
+                                tdecoded:=dec_call;
+                             elsif ENA_LEVEL2 and topcode(5 downto 0)=OPCODE_POPPCREL then
+                                tdecoded:=dec_pop_pc_rel;
+                             elsif ENA_LSHR and topcode(5 downto 0)=OPCODE_LSHIFTRIGHT then
+                                tdecoded:=dec_lshr;
+                             end if;
+                          elsif topcode(7 downto 4)=OPCODE_ADDSP then
+                             if tsp_offset=0 then
+                                tdecoded:=dec_shift;
+                             elsif tsp_offset=1 then
+                                tdecoded:=dec_add_top;
+                             else
+                                tdecoded:=dec_add_sp;
+                             end if;
+                          else -- OPCODE_SHORT
+                             case topcode(3 downto 0) is
+                                  when OPCODE_BREAK =>
+                                       tdecoded:=dec_break;
+                                  when OPCODE_PUSHSP =>
+                                       tdecoded:=dec_push_sp;
+                                  when OPCODE_POPPC =>
+                                       tdecoded:=dec_pop_pc;
+                                  when OPCODE_ADD =>
+                                       tdecoded:=dec_add;
+                                  when OPCODE_OR =>
+                                       tdecoded:=dec_or;
+                                  when OPCODE_AND =>
+                                       tdecoded:=dec_and;
+                                  when OPCODE_LOAD =>
+                                       tdecoded:=dec_load;
+                                  when OPCODE_NOT =>
+                                       tdecoded:=dec_not;
+                                  when OPCODE_FLIP =>
+                                       tdecoded:=dec_flip;
+                                  when OPCODE_STORE =>
+                                       tdecoded:=dec_store;
+                                  when OPCODE_POPSP =>
+                                       tdecoded:=dec_pop_sp;
+                                  when others => -- OPCODE_NOP and others
+                                       tdecoded:=dec_nop;
+                             end case;
+                          end if;
+                          tinsns(i):=tdecoded;
+                      end loop;
+                      
+                      insn <= tinsns(ipc_low);
+                      -- once we wrap, we need to fetch
+                      tinsns(0):=dec_insn_fetch;
+                      insns <= tinsns;
+                      state <= st_execute;
+
+                      -- Each instruction must:
+                      --
+                      -- 1. increase pc_r if applicable
+                      -- 2. set next state if applicable
+                      -- 3. do it's operation
+                 when st_execute =>
+                      -- Some shortcut to make the code readable:
+                      inpc_low:=to_integer(next_pc(BYTE_BITS-1 downto 0));
+                      ex_opcode:=opcode_r(ipc_low);
+							 
+							 if (mem_busy_i = '0') then -- MWW, do not move on until mem is not busy!
+							 insn <= insns(inpc_low);
+							 
+                      -- Defaults used by most instructions
+                      if insn/=dec_insn_fetch and insn/=dec_im then
+                         dbg_o.b_inst <= '1';
+                         idim_r       <= '0';
+                      end if;
+							
+							case insn is
+                           when dec_insn_fetch =>
+                                -- Not a real instruction, fetch new instructions
+                                DoFetch(FAST_FETCH,state,addr_r,pc_r,read_en_r,mem_busy_i);
+                           when dec_im =>
+                                -- Push(immediate value), IDIM=1
+                                -- if IDIM=0 Push(signed(opcode & 0x7F)) else
+                                --           Push((Pop()<<7)|(opcode&0x7F))
+                                if mem_busy_i='0' then
+                                   dbg_o.b_inst <= '1';
+                                   idim_r       <= '1';
+                                   pc_r             <= pc_r+1;
+                                   if idim_r='1' then
+                                      -- We already started an IM sequence
+                                      -- Shift left 7 bits
+                                      a_r(WORD_SIZE-1 downto 7) <= a_r(WORD_SIZE-8 downto 0);
+                                      -- Put the new value
+                                      a_r(6 downto 0) <= ex_opcode(6 downto 0);
+                                   else
+                                      -- First IM, push the value sign extended
+                                      FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                      a_r <= unsigned(resize(signed(ex_opcode(6 downto 0)),WORD_SIZE));
+                                      Push(sp_r,a_r,b_r);
+                                   end if;
+                                end if;
+                           when dec_store_sp =>
+                                -- [SP+Offset]=Pop()
+                                if mem_busy_i='0' then
+                                   write_en_r <= '1';
+                                   addr_r     <= sp_r+sp_offset;
+                                   data_o     <= a_r;
+                                   Pop(sp_r,a_r,b_r);
+                                   -- We need to fetch B
+                                   state      <= st_store_sp2;
+                                end if;
+                           when dec_load_sp =>
+                                -- Push([SP+Offset])
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   Push(sp_r,a_r,b_r);
+                                   -- We are flushing B cache, so we need more time to
+                                   -- read the value.
+                                   state <= st_load_sp2;
+                                end if;
+                           when dec_emulate =>
+                                -- Push(PC+1), PC=Opcode[4:0]*32
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   Push(sp_r,a_r,b_r);
+                                   -- The emulate address is:
+                                   --        98 7654 3210
+                                   -- 0000 00aa aaa0 0000
+                                   pc_r             <= (others => '0');
+                                   pc_r(9 downto 5) <= ex_opcode(4 downto 0);
+                                end if;
+                           when dec_call_pc_rel =>
+                                -- t=Pop(), Push(PC+1), PC=PC+t
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= pc_r+a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_call =>
+                                -- t=Pop(), Push(PC+1), PC=t
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   state <= st_fetch;
+                                   a_r   <= ExpandPC(pc_r+1);
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                end if;
+                           when dec_add_sp =>
+                                -- Push(Pop()+[SP+Offset])
+                                if mem_busy_i='0' then
+                                   -- Read SP+Offset
+                                   state     <= st_add_sp2;
+                                   read_en_r <= '1';
+                                   addr_r    <= sp_r+sp_offset;
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_push_sp =>
+                                -- Push(SP)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <= sp_r;
+                                   Push(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_pc =>
+                                -- PC=Pop() (return)
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0);
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_pop_pc_rel =>
+                                -- PC=PC+Pop()
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   sp_r  <= inc_sp;
+                                end if;
+                           when dec_add =>
+                                -- Push(Pop()+Pop())  [A=A+B, SP++, update B]
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r+b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_sub =>
+                                -- a=Pop(), b=Pop(), Push(b-a)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOp(b_r-a_r,state,sp_r,addr_r,read_en_r,
+                                           a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_pop =>
+                                -- Pop()
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   Pop(sp_r,a_r,b_r);
+                                end if;
+                           when dec_pop_down =>
+                                -- t=Pop(), Pop(), Push(t)
+                                if mem_busy_i='0' then
+                                   -- PopDown leaves top of stack unchanged
+                                   state     <= st_popped;
+                                   addr_r    <= inc_inc_sp;
+                                   read_en_r <= '1';
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_or =>
+                                -- Push(Pop() or Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r or b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_and =>
+                                -- Push(Pop() and Pop())
+                                if mem_busy_i='0' then
+                                   state     <= st_popped;
+                                   a_r       <= a_r and b_r;
+                                   read_en_r <= '1';
+                                   addr_r    <= inc_inc_sp;
+                                   sp_r      <= inc_sp;
+                                end if;
+                           when dec_eq =>
+                                -- a=Pop(), b=Pop(), Push(a=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   DoBinOpBool(a_r=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than =>
+                                -- a=Pop(), b=Pop(), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(a_r<b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_u_less_than_or_equal =>
+                                -- a=Pop(), b=Pop(), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(a_r<=b_r,state,sp_r,addr_r,read_en_r,
+                                               a_r,bin_op_res1_r,BINOP_PIPE);
+                                end if;
+                           when dec_less_than =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   DoBinOpBool(signed(a_r)<signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_less_than_or_equal =>
+                                -- a=signed(Pop()), b=signed(Pop()), Push(a<=b ? 1 : 0)
+                                if mem_busy_i='0' and ENA_LEVEL2 then
+                                   DoBinOpBool(signed(a_r)<=signed(b_r),state,sp_r,
+                                               addr_r,read_en_r,a_r,bin_op_res1_r,
+                                               BINOP_PIPE);
+                                end if;
+                           when dec_load =>
+                                -- Push([Pop()])
+                                if mem_busy_i='0' then
+                                   state     <= st_load2;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   read_en_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_dup =>
+                                -- t=Pop(), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   -- A is dupped, no change
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_dup_stk_b =>
+                                -- Pop(), t=Pop(), Push(t), Push(t), Push(t)
+                                if mem_busy_i='0' then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= b_r;
+                                   -- B goes to A
+                                   Push(sp_r,a_r,b_r);
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                end if;
+                           when dec_store =>
+                                -- a=Pop(), b=Pop(), [a]=b
+                                if mem_busy_i='0' then
+                                   state      <= st_resync;
+                                   pc_r       <= pc_r+1;
+                                   addr_r     <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                   data_o     <= b_r;
+                                   write_en_r <= '1';
+                                   sp_r       <= inc_inc_sp;
+                                end if;
+                           when dec_pop_sp =>
+                                -- SP=Pop()
+                                if mem_busy_i='0' then
+                                   FlushB(write_en_r,addr_r,inc_sp,data_o,b_r);
+                                   state <= st_resync;
+                                   pc_r  <= pc_r+1;
+                                   sp_r  <= a_r(ADDR_W-1 downto BYTE_BITS);
+                                end if;
+                           when dec_nop =>
+                                pc_r <= pc_r+1;
+                           when dec_not =>
+                                -- Push(not(Pop()))
+                                pc_r <= pc_r+1;
+                                a_r  <= not a_r;
+                           when dec_flip =>
+                                -- Push(flip(Pop()))
+                                pc_r <= pc_r+1;
+                                for i in 0 to WORD_SIZE-1 loop
+                                    a_r(i) <= a_r(WORD_SIZE-1-i);
+                                end loop;
+                           when dec_add_top =>
+                                -- a=Pop(), b=Pop(), Push(b), Push(a+b)
+                                pc_r <= pc_r+1;
+                                a_r  <= a_r+b_r;
+                           when dec_shift =>
+                                -- Push(Pop()<<1) [equivalent to a=Pop(), Push(a+a)]
+                                pc_r <= pc_r+1;
+                                a_r(WORD_SIZE-1 downto 1) <= a_r(WORD_SIZE-2 downto 0);
+                                a_r(0) <= '0';
+                           when dec_push_sp_add =>
+                                -- Push(Pop()+SP)
+                                if ENA_LEVEL0 then
+                                   pc_r <= pc_r+1;
+                                   a_r  <= (others => '0');
+                                   a_r(ADDR_W-1 downto BYTE_BITS) <=
+                                      a_r(ADDR_W-1-BYTE_BITS downto 0)+sp_r;
+                                end if;
+                           when dec_neq_branch =>
+                                -- a=Pop(), b=Pop(), PC+=b==0 ? 1 : a
+                                -- Branches are almost always taken as they form loops
+                                if ENA_LEVEL0 then
+                                   sp_r  <= inc_inc_sp;
+                                   -- Need to fetch stack again.
+                                   state <= st_resync;
+                                   if b_r/=0 then
+                                      pc_r <= a_r(ADDR_W-1 downto 0)+pc_r;
+                                   else
+                                      pc_r <= pc_r+1;
+                                   end if;
+                                end if;
+                           when dec_mult =>
+                                -- Push(Pop()*Pop())
+                                if ENA_LEVEL1 then
+                                   if MULT_PIPE then
+                                      mult_a_r <= a_r;
+                                      mult_b_r <= b_r;
+                                      state    <= st_mult2;
+                                   else
+                                      mult_res:=a_r*b_r;
+                                      mult_res1_r <= mult_res(WORD_SIZE-1 downto 0);
+                                      state       <= st_mult5;
+                                   end if;
+                                end if;
+                           when dec_break =>
+                                -- Assert the break_o signal
+                                --report "Break instruction encountered" severity failure;
+                                break_o <= '1';
+                                pc_r    <= pc_r+1;
+                           when dec_loadb =>
+                                -- Push([Pop()] & 0xFF) (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL0 then
+                                   state     <= st_loadb2;                                   
+											  addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --read_en_r <= '1';
+											  byte_read_r <= '1';
+                                   pc_r      <= pc_r+1;
+                                end if;
+                           when dec_storeb =>
+                                -- [Pop()]=Pop() & 0xFF (byte address)
+                                if mem_busy_i='0' and ENA_LEVEL1 then
+                                   state     <= st_resync;
+											  sp_r       <= inc_inc_sp;
+                                   addr_r    <= a_r(ADDR_W-1 downto BYTE_BITS);
+											  addrl_r    <= a_r(BYTE_BITS-1 downto 0);
+                                   --write_en_r <= '1';
+											  byte_write_r <= '1';
+                                   pc_r      <= pc_r+1;
+											  --data_o(WORD_SIZE-1 downto 8) <= (others=>'0');
+											  --data_o(7 downto 0) <= b_r(7 downto 0);										  
+											  data_o(WORD_SIZE-1 downto 0) <= b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0)&b_r(7 downto 0);										  
+                                end if;
+                           when dec_lshr =>
+                                -- a=Pop(), b=Pop(), Push(b>>(a&0x3F))
+                                if ENA_LSHR then
+                                   -- This instruction takes more than one cycle.
+                                   -- We must avoid duplications in the trace log.
+                                   dbg_o.b_inst <= not_lshr;
+                                   not_lshr:='0';
+                                   if a_r(5 downto 0)=0 then -- Only 6 bits used
+                                      -- No more shifts
+                                      if mem_busy_i='0' then
+                                         state     <= st_popped;
+                                         a_r       <= b_r;
+                                         read_en_r <= '1';
+                                         addr_r    <= inc_inc_sp;
+                                         sp_r      <= inc_sp;
+                                         not_lshr:='1';
+                                      end if;
+                                   else -- More shifts needed
+                                      b_r <= "0"&b_r(WORD_SIZE-1 downto 1);
+                                      a_r(5 downto 0) <= a_r(5 downto 0)-1;
+                                      insn <= insn;
+                                   end if;
+                                end if;
+                           when others =>
+                                -- Undefined behavior, we shouldn't get here.
+                                -- It only helps synthesis tools.
+                                sp_r <= (others => D_CARE_VAL);
+                                report "Illegal decode instruction?!" severity failure;
+                                --break_o <= '1';
+                      end case;
+							 end if;
+                 -- The followup of operations that takes more than one execution clock
+                 when st_store_sp2 =>
+                      if mem_busy_i='0' then
+                         addr_r    <= inc_sp;
+                         read_en_r <= '1';
+                         state     <= st_popped;
+                      end if;
+                 when st_load_sp2 =>
+                      if mem_busy_i='0' then
+                         state     <= st_load_sp3;
+                         -- Now we can read SP+Offset (SP already decremented)
+                         read_en_r <= '1';
+                         addr_r    <= sp_r+sp_offset+1;
+                      end if;
+                 when st_load_sp3 =>
+                      if mem_busy_i='0' then
+                         -- Note: We can't increment PC in the decode stage
+                         -- because it will modify sp_offset.
+                         pc_r  <= pc_r+1;
+                         -- Finally we have the result in A
+                         state <= st_execute;
+                         a_r   <= data_i;
+                      end if;
+                 when st_add_sp2 =>
+                      if mem_busy_i='0' then
+                         state <= st_execute;
+                         a_r   <= a_r+data_i;
+                      end if;
+                 when st_load2 =>
+                      if mem_busy_i='0' then
+                         a_r   <= data_i;
+                         state <= st_execute;
+                      end if;
+                 when st_loadb2 =>
+                      if mem_busy_i='0' then
+                         a_r(WORD_SIZE-1 downto 8) <= (others => '0');								 
+								 a_r(7 downto 0) <= data_i(7 downto 0);
+                         state <= st_execute;
+                      end if;
+                 when st_fetch =>
+                      if mem_busy_i='0' then
+                         addr_r    <= pc_r(ADDR_W-1 downto BYTE_BITS);
+                         read_en_r <= '1';
+                         state     <= st_decode;
+                      end if;
+                 -- The following states can be used to leave cycles free for
+                 -- tools that can automagically decompose the multiplication
+                 -- in various stages. Xilinx tools can do it to increase the
+                 -- multipliers performance.
+                 when st_mult2 =>
+                      state <= st_mult3;
+                 when st_mult3 =>
+                      state <= st_mult4;
+                 when st_mult4 =>
+                      state <= st_mult5;
+                 when st_mult5 =>
+                      if mem_busy_i='0' then
+                         if MULT_PIPE then
+                            a_r <= mult_res3_r;
+                         else
+                            a_r <= mult_res1_r;
+                         end if;
+                         read_en_r <= '1';
+                         addr_r    <= inc_inc_sp;
+                         sp_r      <= inc_sp;
+                         state     <= st_popped;
+                      end if;
+               when st_binary_op_res =>
+                    -- BINOP_PIPE=2
+                    state <= st_binary_op_res2;
+               when st_binary_op_res2 =>
+                    -- BINOP_PIPE>=1
+                    read_en_r <= '1';
+                    addr_r    <= inc_inc_sp;
+                    sp_r      <= inc_sp;
+                    state     <= st_popped;
+                    if BINOP_PIPE=2 then
+                       a_r <= bin_op_res2_r;
+                    else -- 1
+                       a_r <= bin_op_res1_r;
+                    end if;
+               when st_popped =>
+                    if mem_busy_i='0' then
+                       -- Note: Moving this PC++ to the decoder seems to
+                       -- consume more LUTs.
+                       pc_r  <= pc_r+1;
+                       b_r   <= data_i;
+                       state <= st_execute;
+                    end if;
+               when others =>
+                    -- Undefined behavior, we shouldn't get here.
+                    -- It only helps synthesis tools.
+                    sp_r <= (others => D_CARE_VAL);
+                    report "Illegal state?!" severity failure;
+                    --break_o <= '1';
+            end case; -- state
+         end if; -- else reset_i='1'
+      end if; -- rising_edge(clk_i)
+   end process opcode_control;
+end architecture Behave; -- Entity: ZPUMediumCore
+
Index: unmerged/core/mist/zpu_ram.qip
===================================================================
--- unmerged/core/mist/zpu_ram.qip	(nonexistent)
+++ unmerged/core/mist/zpu_ram.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "RAM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_ram.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_ram.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_ram.cmp"]
Index: unmerged/core/mist/zpu_rom.vhd
===================================================================
--- unmerged/core/mist/zpu_rom.vhd	(nonexistent)
+++ unmerged/core/mist/zpu_rom.vhd	(revision 1)
@@ -0,0 +1,166 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: zpu_rom.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY zpu_rom IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+END zpu_rom;
+
+
+ARCHITECTURE SYN OF zpu_rom IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (31 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		init_file		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (11 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(31 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "./zpu/HelloTinyROM_ROM.mif",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 4096,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		widthad_a => 12,
+		width_a => 32,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "./zpu/HelloTinyROM_ROM.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "4096"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "12"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "32"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "./zpu/HelloTinyROM_ROM.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "4096"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "12"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "32"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 12 0 INPUT NODEFVAL "address[11..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL "q[31..0]"
+-- Retrieval info: CONNECT: @address_a 0 0 12 0 address 0 0 12 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 32 0 @q_a 0 0 32 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_rom_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/stp1.stp
===================================================================
--- unmerged/core/mist/stp1.stp	(nonexistent)
+++ unmerged/core/mist/stp1.stp	(revision 1)
@@ -0,0 +1,711 @@
+<session jtag_chain="USB-Blaster [USB-1]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="">
+  <display_tree gui_logging_enabled="0">
+    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
+  </display_tree>
+  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <signal_set global_temp="1" is_expanded="true" name="signal_set: 2014/03/08 18:45:04  #0">
+      <clock name="data_io:mist_spi_interface|SPI_CLK" polarity="posedge" tap_mode="classic"/>
+      <config ram_type="M4K" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="2048" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="CONF_DATA0" tap_mode="classic" type="input pin"/>
+          <wire name="SPI_DI" tap_mode="classic" type="input pin"/>
+          <wire name="SPI_DO" tap_mode="classic" type="output pin"/>
+          <wire name="SPI_SS2" tap_mode="classic" type="input pin"/>
+          <wire name="data_io:mist_spi_interface|ADDR[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|WR_EN" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[10]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[11]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[12]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[13]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[14]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[15]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[8]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[9]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|ready" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|request" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sector[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[10]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[11]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[12]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[13]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[14]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[15]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[16]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[17]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[18]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[19]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[20]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[21]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[22]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[23]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[9]" tap_mode="classic" type="combinatorial"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[10]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[11]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[12]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[13]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[14]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[15]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[16]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[17]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[18]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[19]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[20]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[21]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[22]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[23]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[24]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[25]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[26]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[27]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[28]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[29]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[30]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[31]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[9]" tap_mode="classic" type="combinatorial"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="CONF_DATA0" tap_mode="classic" type="input pin"/>
+          <wire name="SPI_DI" tap_mode="classic" type="input pin"/>
+          <wire name="SPI_DO" tap_mode="classic" type="output pin"/>
+          <wire name="SPI_SS2" tap_mode="classic" type="input pin"/>
+          <wire name="data_io:mist_spi_interface|ADDR[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|WR_EN" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[10]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[11]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[12]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[13]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[14]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[15]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[8]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[9]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|ready" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|request" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sector[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[10]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[11]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[12]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[13]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[14]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[15]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[16]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[17]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[18]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[19]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[20]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[21]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[22]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[23]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[9]" tap_mode="classic" type="combinatorial"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[10]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[11]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[12]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[13]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[14]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[15]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[16]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[17]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[18]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[19]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[20]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[21]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[22]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[23]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[24]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[25]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[26]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[27]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[28]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[29]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[30]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[31]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[9]" tap_mode="classic" type="combinatorial"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="CONF_DATA0" tap_mode="classic" type="input pin"/>
+          <wire name="SPI_DI" tap_mode="classic" type="input pin"/>
+          <wire name="SPI_DO" tap_mode="classic" type="output pin"/>
+          <wire name="SPI_SS2" tap_mode="classic" type="input pin"/>
+          <wire name="data_io:mist_spi_interface|ADDR[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|ADDR[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|DATA_OUT[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|WR_EN" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cmd_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[10]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[11]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[12]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[13]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[14]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[15]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[8]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|cnt_reg[9]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|ready" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|request" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sbuf_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="data_io:mist_spi_interface|sector[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[10]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[11]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[12]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[13]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[14]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[15]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[16]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[17]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[18]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[19]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[20]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[21]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[22]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[23]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="data_io:mist_spi_interface|sector[9]" tap_mode="classic" type="combinatorial"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[0]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[1]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[2]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[3]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[4]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[5]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[6]" tap_mode="classic" type="register"/>
+          <wire name="pia:b2v_inst16|portb_output_reg[7]" tap_mode="classic" type="register"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[0]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[10]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[11]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[12]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[13]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[14]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[15]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[16]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[17]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[18]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[19]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[1]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[20]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[21]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[22]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[23]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[24]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[25]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[26]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[27]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[28]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[29]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[2]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[30]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[31]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[3]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[4]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[5]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[6]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[7]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[8]" tap_mode="classic" type="combinatorial"/>
+          <wire name="zpu_config_regs:b2v_inst24|sector[9]" tap_mode="classic" type="combinatorial"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <data_view>
+          <net is_signal_inverted="no" name="SPI_DI"/>
+          <net is_signal_inverted="no" name="SPI_DO"/>
+          <net is_signal_inverted="no" name="SPI_SS2"/>
+          <net is_signal_inverted="no" name="CONF_DATA0"/>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|cmd_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|cnt_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[15]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[14]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[13]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[12]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[11]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[10]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[9]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[8]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|sbuf_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|ADDR" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[8]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|DATA_OUT" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[0]"/>
+          </bus>
+          <net is_signal_inverted="no" name="data_io:mist_spi_interface|WR_EN"/>
+          <net is_signal_inverted="no" name="data_io:mist_spi_interface|ready"/>
+          <bus is_signal_inverted="no" link="all" name="pia:b2v_inst16|portb_output_reg" order="msb_to_lsb" radix="hex" state="expand" type="register">
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[7]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[6]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[5]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[4]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[3]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[2]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[1]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="zpu_config_regs:b2v_inst24|sector" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[31]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[30]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[29]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[28]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[27]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[26]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[25]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[24]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[23]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[22]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[21]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[20]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[19]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[18]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[17]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[16]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[15]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[14]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[13]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[12]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[11]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[10]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[9]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[8]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[7]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[6]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[5]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[4]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[3]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[2]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[1]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|sector" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[23]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[22]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[21]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[20]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[19]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[18]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[17]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[16]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[15]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[14]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[13]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[12]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[11]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[10]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[9]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[8]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[0]"/>
+          </bus>
+          <net is_signal_inverted="no" name="data_io:mist_spi_interface|request"/>
+        </data_view>
+        <setup_view>
+          <net is_signal_inverted="no" name="SPI_DI"/>
+          <net is_signal_inverted="no" name="SPI_DO"/>
+          <net is_signal_inverted="no" name="SPI_SS2"/>
+          <net is_signal_inverted="no" name="CONF_DATA0"/>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|cmd_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cmd_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|cnt_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[15]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[14]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[13]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[12]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[11]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[10]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[9]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[8]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|cnt_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|sbuf_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sbuf_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|ADDR" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[8]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|ADDR[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|DATA_OUT" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|DATA_OUT[0]"/>
+          </bus>
+          <net is_signal_inverted="no" name="data_io:mist_spi_interface|WR_EN"/>
+          <net is_signal_inverted="no" name="data_io:mist_spi_interface|ready"/>
+          <bus is_signal_inverted="no" link="all" name="pia:b2v_inst16|portb_output_reg" order="msb_to_lsb" radix="hex" state="collapse" type="register">
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[7]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[6]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[5]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[4]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[3]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[2]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[1]"/>
+            <net is_signal_inverted="no" name="pia:b2v_inst16|portb_output_reg[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="zpu_config_regs:b2v_inst24|sector" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[31]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[30]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[29]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[28]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[27]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[26]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[25]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[24]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[23]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[22]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[21]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[20]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[19]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[18]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[17]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[16]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[15]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[14]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[13]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[12]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[11]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[10]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[9]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[8]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[7]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[6]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[5]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[4]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[3]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[2]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[1]"/>
+            <net is_signal_inverted="no" name="zpu_config_regs:b2v_inst24|sector[0]"/>
+          </bus>
+          <bus is_signal_inverted="no" link="all" name="data_io:mist_spi_interface|sector" order="msb_to_lsb" radix="hex" state="collapse" type="combinatorial">
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[23]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[22]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[21]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[20]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[19]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[18]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[17]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[16]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[15]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[14]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[13]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[12]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[11]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[10]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[9]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[8]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[7]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[6]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[5]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[4]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[3]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[2]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[1]"/>
+            <net is_signal_inverted="no" name="data_io:mist_spi_interface|sector[0]"/>
+          </bus>
+          <net is_signal_inverted="no" name="data_io:mist_spi_interface|request"/>
+        </setup_view>
+      </presentation>
+      <trigger CRC="93686559" attribute_mem_mode="false" gap_record="true" global_temp="1" is_expanded="true" name="trigger: 2014/03/08 18:45:04  #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_in="dont_care" trigger_out="active high" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no" trigger_in="dont_care" trigger_out="active high"/>
+        <events use_custom_flow_control="no">
+          <level enabled="yes" name="condition1" type="basic">'SPI_SS2' == falling edge
+            <power_up enabled="yes">
+            </power_up><op_node/>
+          </level>
+        </events>
+        <storage_qualifier_events>
+          <transitional>11111111111111111111111111111111111011111111111111111100000000000000000000000000000000000000000000000000000000000000000
+            <pwr_up_transitional>00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+        <log>
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+          <extradata>1111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>
+        </log>
+      </trigger>
+    </signal_set>
+    <position_info>
+      <single attribute="active tab" value="0"/>
+      <single attribute="data horizontal scroll position" value="0"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="setup horizontal scroll position" value="0"/>
+      <single attribute="setup vertical scroll position" value="0"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="1"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="130816"/>
+    </position_info>
+  </instance>
+  <mnemonics/>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="1"/>
+    <single attribute="hierarchy widget visible" value="1"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <multi attribute="column width" size="23" value="34,34,140,74,68,70,88,88,98,98,88,88,352,101,101,101,101,101,101,101,101,107,78"/>
+    <multi attribute="frame size" size="2" value="1488,1006"/>
+    <multi attribute="jtag widget size" size="2" value="334,120"/>
+  </global_info>
+</session>
Index: unmerged/core/mist/user_io.v.bak
===================================================================
--- unmerged/core/mist/user_io.v.bak	(nonexistent)
+++ unmerged/core/mist/user_io.v.bak	(revision 1)
@@ -0,0 +1,72 @@
+module user_io(
+	   input      SPI_CLK,
+	   input      SPI_SS_IO,
+	   output     reg SPI_MISO,
+	   input      SPI_MOSI,
+	   input [7:0] CORE_TYPE,
+		output [5:0] JOY0,
+		output [5:0] JOY1,
+		output [1:0] BUTTONS,
+		output [1:0] SWITCHES
+	   );
+
+   reg [6:0]         sbuf;
+   reg [7:0]         cmd;
+   reg [4:0] 	      cnt;
+   reg [5:0]         joystick0;
+   reg [5:0]         joystick1;
+   reg [3:0] 	      but_sw;
+
+	assign JOY0 = joystick0;
+	assign JOY1 = joystick1;
+	assign BUTTONS = but_sw[1:0];
+	assign SWITCHES = but_sw[3:2];
+   
+   always@(negedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+		   SPI_MISO <= 1'bZ;
+		end else begin
+	      if(cnt < 8) begin
+			  SPI_MISO <= CORE_TYPE[7-cnt];
+			end else begin
+		     SPI_MISO <= 1'bZ;
+			end
+	   end
+	end
+		
+   always@(posedge SPI_CLK) begin
+		if(SPI_SS_IO == 1) begin
+        cnt <= 0;
+		end else begin
+			sbuf[6:1] <= sbuf[5:0];
+			sbuf[0] <= SPI_MOSI;
+
+			cnt <= cnt + 1;
+
+	      if(cnt == 7) begin
+			   cmd[7:1] <= sbuf; 
+				cmd[0] <= SPI_MOSI;
+		   end	
+
+	      if(cnt == 15) begin
+			   if(cmd == 1) begin
+					 but_sw[3:1] <= sbuf[2:0]; 
+					 but_sw[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 2) begin
+					 joystick0[5:1] <= sbuf[4:0]; 
+					 joystick0[0] <= SPI_MOSI; 
+				end
+			   if(cmd == 3) begin
+					 joystick1[5:1] <= sbuf[4:0]; 
+					 joystick1[0] <= SPI_MOSI; 
+				end
+			end	
+		end
+	end
+   
+//   always@(posedge clk2) begin
+//      LED <= ~LED;
+//   end
+   
+endmodule
Index: unmerged/core/mist/zpu/bootdump.c
===================================================================
--- unmerged/core/mist/zpu/bootdump.c	(nonexistent)
+++ unmerged/core/mist/zpu/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/core/mist/zpu/integer.h
===================================================================
--- unmerged/core/mist/zpu/integer.h	(nonexistent)
+++ unmerged/core/mist/zpu/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/core/mist/zpu/mmc.c
===================================================================
--- unmerged/core/mist/zpu/mmc.c	(nonexistent)
+++ unmerged/core/mist/zpu/mmc.c	(revision 1)
@@ -0,0 +1,269 @@
+/*! \file mmc.c \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.c'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+//----- Include Files ---------------------------------------------------------
+#include "spi.h"		// include spi bus support
+
+
+//#define spiTransferTwoFF()	{ spiTransferFF(); spiTransferFF(); }
+
+
+#include "mmc.h"
+
+// include project-specific hardware configuration
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+	// initialize SPI interface
+	spiInit();
+	// release chip select
+	mmcChipSelect(0);
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(1);
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+	u08 retry=0xff;	//255x
+	//
+
+	spiTransferFF();
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+	//
+	spiTransferByte(arg>>24);
+	spiTransferByte(arg>>16);
+	spiTransferByte(arg>>8);
+	spiTransferByte(arg);
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+		retry--;
+	}
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
Index: unmerged/core/mist/zpu/pause.h
===================================================================
--- unmerged/core/mist/zpu/pause.h	(nonexistent)
+++ unmerged/core/mist/zpu/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/core/mist/zpu/regs.h
===================================================================
--- unmerged/core/mist/zpu/regs.h	(nonexistent)
+++ unmerged/core/mist/zpu/regs.h	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_dmactl;
+
+#endif // regs_h
Index: unmerged/core/mist/zpu/spi.c
===================================================================
--- unmerged/core/mist/zpu/spi.c	(nonexistent)
+++ unmerged/core/mist/zpu/spi.c	(revision 1)
@@ -0,0 +1,116 @@
+/*! \file spi.c \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.c'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include "spi.h"
+
+#include "regs.h"
+#include "spi.h"
+
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+	updateSpiState();
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+	updateSpiState();
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+}
+
Index: unmerged/core/mist/zpu/uart.c
===================================================================
--- unmerged/core/mist/zpu/uart.c	(nonexistent)
+++ unmerged/core/mist/zpu/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/core/mist/zpu_config_regs.vhdl.bak
===================================================================
--- unmerged/core/mist/zpu_config_regs.vhdl.bak	(nonexistent)
+++ unmerged/core/mist/zpu_config_regs.vhdl.bak	(revision 1)
@@ -0,0 +1,475 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+ENTITY zpu_config_regs IS
+PORT 
+( 
+	CLK : IN STD_LOGIC;
+	
+	ENABLE_179 : in std_logic;
+	
+	ADDR : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
+	CPU_DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	WR_EN : IN STD_LOGIC;
+	
+	-- SWITCHES
+	SWITCH : in std_logic_vector(9 downto 0); -- already synchronized
+	KEY : in std_logic_vector(3 downto 0); -- already synchronized
+	
+	-- LEDS
+	LEDG : out std_logic_vector(7 downto 0);
+	LEDR : out std_logic_vector(9 downto 0);
+	
+	-- SDCARD
+	SDCARD_CLK : out std_logic;
+	SDCARD_CMD : out std_logic;
+	SDCARD_DAT : in std_logic;
+	SDCARD_DAT3 : out std_logic;
+	
+	-- ATARI interface (in future we can also turbo load by directly hitting memory...)
+	SIO_DATA_IN  : out std_logic;
+	SIO_COMMAND_OUT : in std_logic;
+	SIO_DATA_OUT : in std_logic;
+	
+	-- CPU interface
+	DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+	PAUSE_ZPU : out std_logic;
+	
+	-- SYSTEM CONFIG SETTINGS (legacy from switches - hardcoded to start with, then much fancier)
+	PAL : OUT STD_LOGIC;
+	TURBO : OUT STD_LOGIC;
+	USE_SDRAM : OUT STD_LOGIC;
+	RAM_SELECT : OUT STD_LOGIC_VECTOR(1 downto 0);
+	VGA : OUT STD_LOGIC;
+	COMPOSITE_ON_HSYNC : OUT STD_LOGIC;
+	GPIO_ENABLE : OUT STD_LOGIC;
+	ROM_SELECT : out stD_logic_vector(1 downto 0);
+
+	-- system reset/halt
+	PLL_LOCKED : IN STD_LOGIC; -- pll locked
+	REQUEST_RESET_ZPU : in std_logic; -- from keyboard (f12 to start with)
+	
+	RESET_6502 : OUT STD_LOGIC; -- i.e. cpu reset - 6502
+	RESET_ZPU : OUT STD_LOGIC; -- i.e. cpu reset - zpu
+	RESET_N : OUT STD_LOGIC; -- i.e. reset line on flip flops
+	
+	PAUSE_6502 : out std_logic;
+	
+	THROTTLE_COUNT_6502 : out std_logic_vector(5 downto 0);
+	
+	ZPU_HEX : out std_logic_vector(15 downto 0)
+
+--	-- synchronize async inputs
+--	locked_synchronizer : synchronizer
+--		port map (clk=>clk, raw=>LOCKED, sync=>LOCKED_REG);
+	
+);
+END zpu_config_regs;
+
+ARCHITECTURE vhdl OF zpu_config_regs IS
+	COMPONENT complete_address_decoder IS
+	generic (width : natural := 4);
+	PORT 
+	( 
+		addr_in : in std_logic_vector(width-1 downto 0);			
+		addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+	);
+	END component;
+	
+	COMPONENT spi_master IS
+	  GENERIC(
+		 slaves  : INTEGER := 4;  --number of spi slaves
+		 d_width : INTEGER := 2); --data bus width
+	  PORT(
+		 clock   : IN     STD_LOGIC;                             --system clock
+		 reset_n : IN     STD_LOGIC;                             --asynchronous reset
+		 enable  : IN     STD_LOGIC;                             --initiate transaction
+		 cpol    : IN     STD_LOGIC;                             --spi clock polarity
+		 cpha    : IN     STD_LOGIC;                             --spi clock phase
+		 cont    : IN     STD_LOGIC;                             --continuous mode command
+		 clk_div : IN     INTEGER;                               --system clock cycles per 1/2 period of sclk
+		 addr    : IN     INTEGER;                               --address of slave
+		 tx_data : IN     STD_LOGIC_VECTOR(d_width-1 DOWNTO 0);  --data to transmit
+		 miso    : IN     STD_LOGIC;                             --master in, slave out
+		 sclk    : BUFFER STD_LOGIC;                             --spi clock
+		 ss_n    : BUFFER STD_LOGIC_VECTOR(slaves-1 DOWNTO 0);   --slave select
+		 mosi    : OUT    STD_LOGIC;                             --master out, slave in
+		 busy    : OUT    STD_LOGIC;                             --busy / data ready signal
+		 rx_data : OUT    STD_LOGIC_VECTOR(d_width-1 DOWNTO 0)); --data received
+	END component;	
+	
+
+	component pokey IS
+	PORT 
+	( 
+		CLK : IN STD_LOGIC;
+		--ENABLE_179 :in std_logic;
+		CPU_MEMORY_READY :in std_logic;
+		ANTIC_MEMORY_READY :in std_logic;
+		ADDR : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+		DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+		WR_EN : IN STD_LOGIC;
+		
+		RESET_N : IN STD_LOGIC;
+		
+		-- keyboard interface
+		keyboard_scan : out std_logic_vector(5 downto 0);
+		keyboard_response : in std_logic_vector(1 downto 0);
+		
+		-- pots - go high as capacitor charges
+		POT_IN : in std_logic_vector(7 downto 0);
+		
+		-- sio interface
+		SIO_IN1 : IN std_logic;
+		SIO_IN2 : IN std_logic;
+		SIO_IN3 : IN std_logic;
+		
+		DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+		
+		CHANNEL_0_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_1_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_2_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		CHANNEL_3_OUT : OUT STD_LOGIC_VECTOR(3 downto 0);
+		
+		IRQ_N_OUT : OUT std_logic;
+		
+		SIO_OUT1 : OUT std_logic;
+		SIO_OUT2 : OUT std_logic;
+		SIO_OUT3 : OUT std_logic;
+		
+		SIO_CLOCK : INOUT std_logic; -- TODO, should not use internally
+		
+		POT_RESET : out std_logic
+	);
+	END component;	
+	
+	function vectorize(s: std_logic) return std_logic_vector is
+	variable v: std_logic_vector(0 downto 0);
+	begin
+		v(0) := s;
+		return v;
+	end;
+	
+	signal addr_decoded : std_logic_vector(15 downto 0);	
+	
+	signal config_6502_next : std_logic_vector(7 downto 0);
+	signal config_6502_reg : std_logic_vector(7 downto 0);
+	
+	signal pause_next : std_logic_vector(31 downto 0);
+	signal pause_reg : std_logic_vector(31 downto 0);
+	signal paused_next : std_logic;
+	signal paused_reg : std_logic;
+	
+	signal ledg_next : std_logic_vector(7 downto 0);
+	signal ledg_reg : std_logic_vector(7 downto 0);
+
+	signal ledr_next : std_logic_vector(9 downto 0);
+	signal ledr_reg : std_logic_vector(9 downto 0);
+	
+	signal reset_n_next : std_logic;
+	signal reset_n_reg : std_logic;
+	
+	signal reset_6502_cpu_next : std_logic;
+	signal reset_6502_cpu_reg : std_logic;
+	
+	signal reset_zpu_next : std_logic;
+	signal reset_zpu_reg : std_logic;	
+	
+	signal spi_miso : std_logic;
+	signal spi_mosi : std_logic;
+	signal spi_busy : std_logic;	
+	signal spi_enable : std_logic;
+	signal spi_chip_select : std_logic_vector(0 downto 0);
+	signal spi_clk_out : std_logic;
+	
+	signal spi_tx_data : std_logic_vector(7 downto 0);
+	signal spi_rx_data : std_logic_vector(7 downto 0);
+	
+	signal spi_addr_next : std_logic;
+	signal spi_addr_reg : std_logic;
+	signal spi_speed_next : std_logic_vector(7 downto 0);
+	signal spi_speed_reg : std_logic_vector(7 downto 0);
+
+	signal zpu_hex_next : std_logic_vector(15 downto 0);
+	signal zpu_hex_reg : std_logic_vector(15 downto 0);
+	
+	signal pokey_data_out : std_logic_vector(7 downto 0);
+begin
+	-- register
+	process(clk,pll_locked)
+	begin
+		if (clk'event and clk='1') then	
+			if (pll_locked = '0') then
+				config_6502_reg <= "1"&"0"&"011111"; -- reset_6502, halt_6502, run_every 32 cycles
+				pause_reg <= (others=>'0');
+				paused_reg <= '0';
+				ledg_reg <= (others=>'0');
+				ledr_reg <= (others=>'0');
+				
+				spi_addr_reg <= '1';
+				spi_speed_reg <= X"80";
+				
+				zpu_hex_reg <= X"b007";
+				
+				reset_n_reg <= '0';			
+				reset_zpu_reg <= '1';
+				reset_6502_cpu_reg <= '1';											
+			else
+				config_6502_reg <= config_6502_next;
+				pause_reg <= pause_next;
+				paused_reg <= paused_next;
+				ledg_reg <= ledg_next;
+				ledr_reg <= ledr_next;
+				
+				spi_addr_reg <= spi_addr_next;
+				spi_speed_reg <= spi_speed_next;
+	
+				zpu_hex_reg <= zpu_hex_next;
+	
+				reset_n_reg <= reset_n_next;			
+				reset_zpu_reg <= reset_zpu_next;
+				reset_6502_cpu_reg <= reset_6502_cpu_next;							
+			end if;
+		end if;
+	end process;
+
+	-- decode address
+	decode_addr1 : complete_address_decoder
+		generic map(width=>4)
+		port map (addr_in=>addr(3 downto 0), addr_decoded=>addr_decoded);
+
+	-- spi - for sd card access without bit banging...
+	-- 200KHz to start with - probably fine for 8-bit, can up it later after init
+	spi_master1 : spi_master
+		generic map(slaves=>1,d_width=>8)
+		port map (clock=>clk,reset_n=>pll_locked,enable=>spi_enable,cpol=>'0',cpha=>'0',cont=>'0',clk_div=>to_integer(unsigned(spi_speed_reg)),addr=>to_integer(unsigned(vectorize(spi_addr_reg))),
+		          tx_data=>spi_tx_data, miso=>spi_miso,sclk=>spi_clk_out,ss_n=>spi_chip_select,mosi=>spi_mosi,
+					 rx_data=>spi_rx_data,busy=>spi_busy);
+					 
+	-- spi-programming model:
+	-- reg for write/read
+	-- data (send/receive)
+	-- busy
+	-- speed - 0=400KHz, 1=10MHz? Start with 400KHz then atari800core...
+	-- chip select
+	
+	-- uart - another Pokey! Running at atari frequency.
+	uart1 : pokey
+		port map (clk=>clk,CPU_MEMORY_READY=>enable_179,ANTIC_MEMORY_READY=>enable_179,addr=>addr(3 downto 0),data_in=>cpu_data_in(7 downto 0),wr_en=>addr(4) and wr_en, 
+		reset_n=>pll_locked,keyboard_response=>"11",pot_in=>X"00",
+		sio_in1=>sio_data_out,sio_in2=>'1',sio_in3=>'1', -- TODO, pokey dir...
+		data_out=>pokey_data_out, 
+		sio_out1=>sio_data_in);
+
+	-- hardware regs for ZPU
+	--
+	-- KEYS -> all for ZPU. SWITCHES -> all for ZPU
+	-- i.e. zpu must control: rom/ram select, turbo, 6502 reset, scandoubler, rom wait states, pal/ntsc, gpio enable, sdram vs sram
+	-- these need storing somewhere...
+	-- TODO - volume output from here
+	-- TODO - hex digits register
+	-- TODO - if we take over antic we need to point antic to alternative RAM!
+	-- TODO - if we take over antic we need to point it back at the original display list... e.g. freeze, store state, restore state...
+	-- TODO - reset pokey and pia interrupts too?
+	--
+	-- virtual joystick button -> keyboard (windows key?)
+	-- reset -> keyboard -> f12 -> zpu reset. Then zpu controls 6502 reset.
+	--
+	-- important todo -> speed up clearing ram. e.g. 32-bit sram write. Only clear bit we need to.
+	--
+	-- STEP 1 -> joystick -> keyboard (DONE)
+	-- STEP 2 -> hardcode switch inputs to 65XE, PAL, non scandoubled  (DONE)
+	-- STEP 3 -> 6502 reset (DONE))/turbo under zpu control (DONE)
+	-- STEP 4 -> zpu starts 6502 on key1 (DONE)
+	-- STEP 5 -> simple OSD! ok, just make antic display mode 2 on reset with hello world, joystick to select... (CLOSE)
+	--
+	-- CONFIG_6502: TODO 
+	-- 	W: 0-5: run every n cycles (0-63), 6: pause, 7: reset 
+	-- PAUSE (DONE) -- W: 0-31:wait for n cycles
+	-- SWITCH (DONE)
+	--		R: 0-9 - switches
+	-- KEY (DONE)
+	--    R: 0-3 - keys
+	-- LEDG (DONE) 
+	--    R/W: 0-9
+	-- LEDR (DONE) 
+	--    R/W: 0-9
+	-- SPI_DATA (DONE) 
+	--		W - write data (starts transmission)
+	--		R - read data (wait for complete first)
+	-- SPI_STATE/SPI_CTRL (DONE) 
+	--    R: 0=busy
+	--    W: 0=select_n, speed
+	-- SIO
+	--    R: 0=CMD
+	-- FPGA board (DONE) 
+	--    R(32 bits) 0=DE1
+	-- HEX digits
+	--    W(16 bits)
+	
+	-- TODO, ROM select, RAM select etc etc
+	-- TODO firmware with OSD!
+				
+	-- Writes to registers
+	process(cpu_data_in,wr_en,addr,addr_decoded, ledg_reg, ledr_reg, pause_reg, config_6502_reg, spi_speed_reg, spi_addr_reg, zpu_hex_reg)
+	begin
+		config_6502_next <= config_6502_reg;
+		pause_next <= pause_reg;
+		ledg_next <= ledg_reg;
+		ledr_next <= ledr_reg;
+		
+		spi_speed_next <= spi_speed_reg;
+		spi_addr_next <= spi_addr_reg;
+		spi_tx_data <= (others=>'0');
+		spi_enable <= '0';
+		
+		zpu_hex_next <= zpu_hex_reg;
+		
+		paused_next <= '0';
+		if (not(pause_reg = X"00000000")) then
+			pause_next <= std_LOGIC_VECTOR(unsigned(pause_reg)-to_unsigned(1,32));
+			paused_next <= '1';
+		end if;
+	
+		if (wr_en = '1' and addr(4) = '0') then
+			if(addr_decoded(0) = '1') then
+				config_6502_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(1) = '1') then
+				pause_next <= cpu_data_in;
+				paused_next <= '1';
+			end if;				
+
+			if(addr_decoded(4) = '1') then
+				ledg_next <= cpu_data_in(7 downto 0);
+			end if;	
+			
+			if(addr_decoded(5) = '1') then
+				ledr_next <= cpu_data_in(9 downto 0);
+			end if;	
+
+			if(addr_decoded(6) = '1') then
+				-- TODO, check overrun?
+				spi_tx_data <= cpu_data_in(7 downto 0);
+				spi_enable <= '1';
+			end if;	
+
+			if(addr_decoded(7) = '1') then
+				spi_addr_next <= cpu_data_in(0);
+				if (cpu_data_in(1) = '1') then
+					spi_speed_next <= X"80"; -- slow, for init
+				else
+					spi_speed_next <= X"04"; -- turbo!
+				end if;
+			end if;	
+
+			if(addr_decoded(10) = '1') then
+				zpu_hex_next <= cpu_data_in(15 downto 0);
+			end if;	
+			
+		end if;
+	end process;
+	
+	-- Read from registers
+	process(addr,addr_decoded, ledg_reg, ledr_reg, SWITCH, KEY, SIO_COMMAND_OUT, spi_rx_data, spi_busy, pokey_data_out, zpu_hex_reg)
+	begin
+		data_out <= (others=>'0');
+
+		if (addr(4) = '0') then
+			if (addr_decoded(2) = '1') then
+				data_out(9 downto 0) <= SWITCH;
+			end if;		
+			
+			if (addr_decoded(3) = '1') then
+				data_out(3 downto 0) <= KEY;
+			end if;		
+			
+			if (addr_decoded(4) = '1') then
+				data_out(7 downto 0) <= ledg_reg;
+			end if;
+
+			if (addr_decoded(5) = '1') then
+				data_out(9 downto 0) <= ledr_reg;
+			end if;
+
+			if (addr_decoded(6) = '1') then
+				data_out(7 downto 0) <= spi_rx_data;
+			end if;
+
+			if (addr_decoded(7) = '1') then
+				data_out(0) <= spi_busy;
+			end if;		
+
+			if(addr_decoded(8) = '1') then
+				data_out(0) <= sio_command_OUT;
+			end if;	
+			
+			if (addr_decoded(9) = '1') then
+				data_out <= X"00000000"; -- DE1!
+				--data_out <= X"00000001"; -- DE2!
+				--data_out <= X"00000002"; -- SOCKIT!
+				--data_out <= X"00000003"; -- REPLAY!
+				--data_out <= X"00000004"; -- MMC!		
+			end if;
+			
+			if (addr_decoded(10) = '1') then
+				data_out(15 downto 0) <= zpu_hex_reg;
+			end if;			
+		else
+			data_out(7 downto 0) <= pokey_data_out;
+		end if;
+	end process;	
+	
+	process(request_reset_zpu, config_6502_next, config_6502_reg)
+	begin
+		reset_n_next <= '1';
+		reset_zpu_next <= '0';
+		reset_6502_cpu_next <= config_6502_reg(7);
+		
+		if (request_reset_zpu = '1') then
+			reset_n_next <= '0';
+			reset_zpu_next <= '1';
+			reset_6502_cpu_next <= '1';
+		end if;
+	end process;
+	
+	-- outputs
+	PAUSE_ZPU <= paused_reg;
+	LEDG <= ledg_reg;
+	LEDR <= ledr_reg;
+	
+	SDCARD_CLK <= spi_clk_out;
+	SDCARD_CMD <= spi_mosi;
+	spi_miso <= SDCARD_DAT; -- INPUT!! XXX
+	SDCARD_DAT3 <= spi_chip_select(0);
+	
+	PAL <= '1';
+	TURBO <= '0';
+	USE_SDRAM <= switch(7); -- should not be all or nothing. can mix for higher ram settings...
+	RAM_SELECT <= "00";
+	VGA <= switch(9);
+	COMPOSITE_ON_HSYNC <= switch(8);
+	GPIO_ENABLE <= '0'; -- need to fix carts! TODO FIXME XXX
+	ROM_SELECT <= switch(6 downto 5);
+	
+	reset_n <= reset_n_reg; -- system reset or pll not locked
+	reset_zpu <= reset_zpu_reg; -- system_reset or pll not locked
+	reset_6502 <= reset_6502_cpu_reg; -- zpu software controlled
+	
+	pause_6502 <= config_6502_reg(6); -- zpu software controlled
+	
+	throttle_count_6502 <= config_6502_reg(5 downto 0); -- zpu software controlled	
+	
+	zpu_hex <= zpu_hex_reg;
+end vhdl;
+
+
Index: unmerged/core/mist/zpu_ram.cmp
===================================================================
--- unmerged/core/mist/zpu_ram.cmp	(nonexistent)
+++ unmerged/core/mist/zpu_ram.cmp	(revision 1)
@@ -0,0 +1,25 @@
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+component zpu_ram
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+end component;
Index: unmerged/core/mist/zpu_rom.qip
===================================================================
--- unmerged/core/mist/zpu_rom.qip	(nonexistent)
+++ unmerged/core/mist/zpu_rom.qip	(revision 1)
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "12.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "zpu_rom.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.bsf"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "zpu_rom.cmp"]
Index: unmerged/core_merge/de1_replay_changes_summary
===================================================================
--- unmerged/core_merge/de1_replay_changes_summary	(nonexistent)
+++ unmerged/core_merge/de1_replay_changes_summary	(revision 1)
@@ -0,0 +1,21 @@
+diff -r ./antic.vhdl ../../../common/a8core/antic.vhdl
+NEEDS GENERIC FOR CYCLES, other than that TAKE REPLAY
+
+Only in .: sdram_statemachine.vhdl
+DELETED - TAKEN FROM MIST
+
+diff -r ./shared_enable.vhdl ../../../common/a8core/shared_enable.vhdl
+NEEDS GENERIC FOR CYCLES, other than that TAKE DE1 probably - scandoubler stuff?
+NEEDS A RETHINK REALLY... Replace?
+
+Only in .: zpu
+Only in .: zpu_config_regs.vhdl
+Only in .: zpu_core.vhd
+Only in .: zpu_glue.vhdl
+Only in .: zpupkg.vhd
+Only in .: zpu_ram.cmp
+Only in .: zpu_ram.qip
+Only in .: zpu_ram.vhd
+Only in .: zpu_rom.cmp
+Only in .: zpu_rom.qip
+Only in .: zpu_rom.vhd
Index: unmerged/core_merge/mist_replay_changes_summary
===================================================================
--- unmerged/core_merge/mist_replay_changes_summary	(nonexistent)
+++ unmerged/core_merge/mist_replay_changes_summary	(revision 1)
@@ -0,0 +1 @@
+Only in mist/: zpu
Index: unmerged/zpu_firmware/de1_old/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/zpu_firmware/de1_old/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,3366 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b80e2;
+00a2 : f4738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
+00a9 : ff040000;
+00aa : 00000000;
+00ab : 00000000;
+00ac : 00000000;
+00ad : 00000000;
+00ae : 00000000;
+00af : 00000000;
+00b0 : 0b0b0b88;
+00b1 : d8040000;
+00b2 : 00000000;
+00b3 : 00000000;
+00b4 : 00000000;
+00b5 : 00000000;
+00b6 : 00000000;
+00b7 : 00000000;
+00b8 : 72097081;
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+0b69 : a13f83e0;
+0b6a : 80087083;
+0b6b : e0800c54;
+0b6c : 853d0d83;
+0b6d : e08c0c04;
+0b6e : 83e08c08;
+0b6f : 0283e08c;
+0b70 : 0cf93d0d;
+0b71 : 800b83e0;
+0b72 : 8c08fc05;
+0b73 : 0c83e08c;
+0b74 : 08880508;
+0b75 : 8025b938;
+0b76 : 83e08c08;
+0b77 : 88050830;
+0b78 : 83e08c08;
+0b79 : 88050c80;
+0b7a : 0b83e08c;
+0b7b : 08f4050c;
+0b7c : 83e08c08;
+0b7d : fc05088a;
+0b7e : 38810b83;
+0b7f : e08c08f4;
+0b80 : 050c83e0;
+0b81 : 8c08f405;
+0b82 : 0883e08c;
+0b83 : 08fc050c;
+0b84 : 83e08c08;
+0b85 : 8c050880;
+0b86 : 25b93883;
+0b87 : e08c088c;
+0b88 : 05083083;
+0b89 : e08c088c;
+0b8a : 050c800b;
+0b8b : 83e08c08;
+0b8c : f0050c83;
+0b8d : e08c08fc;
+0b8e : 05088a38;
+0b8f : 810b83e0;
+0b90 : 8c08f005;
+0b91 : 0c83e08c;
+0b92 : 08f00508;
+0b93 : 83e08c08;
+0b94 : fc050c80;
+0b95 : 5383e08c;
+0b96 : 088c0508;
+0b97 : 5283e08c;
+0b98 : 08880508;
+0b99 : 5181df3f;
+0b9a : 83e08008;
+0b9b : 7083e08c;
+0b9c : 08f8050c;
+0b9d : 5483e08c;
+0b9e : 08fc0508;
+0b9f : 802e9038;
+0ba0 : 83e08c08;
+0ba1 : f8050830;
+0ba2 : 83e08c08;
+0ba3 : f8050c83;
+0ba4 : e08c08f8;
+0ba5 : 05087083;
+0ba6 : e0800c54;
+0ba7 : 893d0d83;
+0ba8 : e08c0c04;
+0ba9 : 83e08c08;
+0baa : 0283e08c;
+0bab : 0cfb3d0d;
+0bac : 800b83e0;
+0bad : 8c08fc05;
+0bae : 0c83e08c;
+0baf : 08880508;
+0bb0 : 80259938;
+0bb1 : 83e08c08;
+0bb2 : 88050830;
+0bb3 : 83e08c08;
+0bb4 : 88050c81;
+0bb5 : 0b83e08c;
+0bb6 : 08fc050c;
+0bb7 : 83e08c08;
+0bb8 : 8c050880;
+0bb9 : 25903883;
+0bba : e08c088c;
+0bbb : 05083083;
+0bbc : e08c088c;
+0bbd : 050c8153;
+0bbe : 83e08c08;
+0bbf : 8c050852;
+0bc0 : 83e08c08;
+0bc1 : 88050851;
+0bc2 : bd3f83e0;
+0bc3 : 80087083;
+0bc4 : e08c08f8;
+0bc5 : 050c5483;
+0bc6 : e08c08fc;
+0bc7 : 0508802e;
+0bc8 : 903883e0;
+0bc9 : 8c08f805;
+0bca : 083083e0;
+0bcb : 8c08f805;
+0bcc : 0c83e08c;
+0bcd : 08f80508;
+0bce : 7083e080;
+0bcf : 0c54873d;
+0bd0 : 0d83e08c;
+0bd1 : 0c0483e0;
+0bd2 : 8c080283;
+0bd3 : e08c0cfd;
+0bd4 : 3d0d810b;
+0bd5 : 83e08c08;
+0bd6 : fc050c80;
+0bd7 : 0b83e08c;
+0bd8 : 08f8050c;
+0bd9 : 83e08c08;
+0bda : 8c050883;
+0bdb : e08c0888;
+0bdc : 050827b9;
+0bdd : 3883e08c;
+0bde : 08fc0508;
+0bdf : 802eae38;
+0be0 : 800b83e0;
+0be1 : 8c088c05;
+0be2 : 0824a238;
+0be3 : 83e08c08;
+0be4 : 8c050810;
+0be5 : 83e08c08;
+0be6 : 8c050c83;
+0be7 : e08c08fc;
+0be8 : 05081083;
+0be9 : e08c08fc;
+0bea : 050cffb8;
+0beb : 3983e08c;
+0bec : 08fc0508;
+0bed : 802e80e1;
+0bee : 3883e08c;
+0bef : 088c0508;
+0bf0 : 83e08c08;
+0bf1 : 88050826;
+0bf2 : ad3883e0;
+0bf3 : 8c088805;
+0bf4 : 0883e08c;
+0bf5 : 088c0508;
+0bf6 : 3183e08c;
+0bf7 : 0888050c;
+0bf8 : 83e08c08;
+0bf9 : f8050883;
+0bfa : e08c08fc;
+0bfb : 05080783;
+0bfc : e08c08f8;
+0bfd : 050c83e0;
+0bfe : 8c08fc05;
+0bff : 08812a83;
+0c00 : e08c08fc;
+0c01 : 050c83e0;
+0c02 : 8c088c05;
+0c03 : 08812a83;
+0c04 : e08c088c;
+0c05 : 050cff95;
+0c06 : 3983e08c;
+0c07 : 08900508;
+0c08 : 802e9338;
+0c09 : 83e08c08;
+0c0a : 88050870;
+0c0b : 83e08c08;
+0c0c : f4050c51;
+0c0d : 913983e0;
+0c0e : 8c08f805;
+0c0f : 087083e0;
+0c10 : 8c08f405;
+0c11 : 0c5183e0;
+0c12 : 8c08f405;
+0c13 : 0883e080;
+0c14 : 0c853d0d;
+0c15 : 83e08c0c;
+0c16 : 0483e08c;
+0c17 : 080283e0;
+0c18 : 8c0cff3d;
+0c19 : 0d800b83;
+0c1a : e08c08fc;
+0c1b : 050c83e0;
+0c1c : 8c088805;
+0c1d : 088106ff;
+0c1e : 11700970;
+0c1f : 83e08c08;
+0c20 : 8c050806;
+0c21 : 83e08c08;
+0c22 : fc050811;
+0c23 : 83e08c08;
+0c24 : fc050c83;
+0c25 : e08c0888;
+0c26 : 0508812a;
+0c27 : 83e08c08;
+0c28 : 88050c83;
+0c29 : e08c088c;
+0c2a : 05081083;
+0c2b : e08c088c;
+0c2c : 050c5151;
+0c2d : 515183e0;
+0c2e : 8c088805;
+0c2f : 08802e84;
+0c30 : 38ffab39;
+0c31 : 83e08c08;
+0c32 : fc050870;
+0c33 : 83e0800c;
+0c34 : 51833d0d;
+0c35 : 83e08c0c;
+0c36 : 04fc3d0d;
+0c37 : 7670797b;
+0c38 : 55555555;
+0c39 : 8f72278c;
+0c3a : 38727507;
+0c3b : 83065170;
+0c3c : 802ea938;
+0c3d : ff125271;
+0c3e : ff2e9838;
+0c3f : 72708105;
+0c40 : 54337470;
+0c41 : 81055634;
+0c42 : ff125271;
+0c43 : ff2e0981;
+0c44 : 06ea3874;
+0c45 : 83e0800c;
+0c46 : 863d0d04;
+0c47 : 74517270;
+0c48 : 84055408;
+0c49 : 71708405;
+0c4a : 530c7270;
+0c4b : 84055408;
+0c4c : 71708405;
+0c4d : 530c7270;
+0c4e : 84055408;
+0c4f : 71708405;
+0c50 : 530c7270;
+0c51 : 84055408;
+0c52 : 71708405;
+0c53 : 530cf012;
+0c54 : 52718f26;
+0c55 : c9388372;
+0c56 : 27953872;
+0c57 : 70840554;
+0c58 : 08717084;
+0c59 : 05530cfc;
+0c5a : 12527183;
+0c5b : 26ed3870;
+0c5c : 54ff8139;
+0c5d : 00ffffff;
+0c5e : ff00ffff;
+0c5f : ffff00ff;
+0c60 : ffffff00;
+0c61 : 70707042;
+0c62 : 409c0202;
+0c63 : 02020202;
+0c64 : 02020202;
+0c65 : 02020202;
+0c66 : 02020202;
+0c67 : 02020202;
+0c68 : 02704100;
+0c69 : 06000000;
+0c6a : 2f000000;
+0c6b : 4f70656e;
+0c6c : 696e673a;
+0c6d : 00000000;
+0c6e : 6661696c;
+0c6f : 0a000000;
+0c70 : 6f6b0a00;
+0c71 : 436f756c;
+0c72 : 64206e6f;
+0c73 : 74207265;
+0c74 : 61642068;
+0c75 : 65616465;
+0c76 : 720a0000;
+0c77 : 556e6b6e;
+0c78 : 6f776e20;
+0c79 : 66696c65;
+0c7a : 20747970;
+0c7b : 65000000;
+0c7c : 41545220;
+0c7d : 00000000;
+0c7e : 58442000;
+0c7f : 300a0000;
+0c80 : 58464420;
+0c81 : 00000000;
+0c82 : 42414420;
+0c83 : 73656374;
+0c84 : 6f722073;
+0c85 : 697a6500;
+0c86 : 4d442000;
+0c87 : 58455820;
+0c88 : 00000000;
+0c89 : 53442000;
+0c8a : 44442000;
+0c8b : 44495220;
+0c8c : 00000000;
+0c8d : 426f6f74;
+0c8e : 696e672e;
+0c8f : 2e2e0000;
+0c90 : 6f70656e;
+0c91 : 64697220;
+0c92 : 6661696c;
+0c93 : 65640a00;
+0c94 : 636d643a;
+0c95 : 00000000;
+0c96 : 45525220;
+0c97 : 00000000;
+0c98 : 53504453;
+0c99 : 00000000;
+0c9a : 53504446;
+0c9b : 00000000;
+0c9c : 2873656e;
+0c9d : 643a0000;
+0c9e : 3a63686b;
+0c9f : 3a000000;
+0ca0 : 29000000;
+0ca1 : 73646361;
+0ca2 : 72640a00;
+0ca3 : 6469736b;
+0ca4 : 5f696e69;
+0ca5 : 743a0000;
+0ca6 : 6d6f756e;
+0ca7 : 743a0000;
+0ca8 : 6f70656e;
+0ca9 : 6469723a;
+0caa : 00000000;
+0cab : 424f4f54;
+0cac : 2e415452;
+0cad : 00000000;
+0cae : 50617573;
+0caf : 65640a00;
+0cb0 : 53706565;
+0cb1 : 643a0000;
+0cb2 : 53746174;
+0cb3 : 3a000000;
+0cb4 : 3a646f6e;
+0cb5 : 650a0000;
+0cb6 : 53656374;
+0cb7 : 6f723a00;
+0cb8 : 20726563;
+0cb9 : 65697665;
+0cba : 3a000000;
+0cbb : 2073656e;
+0cbc : 64696e67;
+0cbd : 0a000000;
+0cbe : 64617461;
+0cbf : 20000000;
+0cc0 : 6e616d65;
+0cc1 : 20000000;
+0cc2 : 626f6f74;
+0cc3 : 20000000;
+0cc4 : 6e756d74;
+0cc5 : 6f627566;
+0cc6 : 66657220;
+0cc7 : 00000000;
+0cc8 : 00000000;
+0cc9 : 00000000;
+0cca : 72025f07;
+0ccb : f807a900;
+0ccc : 8d04038d;
+0ccd : 4402a907;
+0cce : 8d0503a9;
+0ccf : 708d0a03;
+0cd0 : a9018d0b;
+0cd1 : 03850960;
+0cd2 : 7d8a4820;
+0cd3 : 53e488d0;
+0cd4 : fa68aa8c;
+0cd5 : 8e07ad7d;
+0cd6 : 07ee8e07;
+0cd7 : 60a9938d;
+0cd8 : e202a907;
+0cd9 : 8de302a2;
+0cda : 0220da07;
+0cdb : 954320da;
+0cdc : 07954435;
+0cdd : 43c9fff0;
+0cde : f0caca10;
+0cdf : ec3006e6;
+0ce0 : 45d002e6;
+0ce1 : 4620da07;
+0ce2 : a2018144;
+0ce3 : b545d543;
+0ce4 : d0edca10;
+0ce5 : f720d207;
+0ce6 : 4c9407a9;
+0ce7 : 038d0fd2;
+0ce8 : 6ce202ad;
+0ce9 : 8e07cd7f;
+0cea : 07d0abee;
+0ceb : 0a03d003;
+0cec : ee0b03ad;
+0ced : 7d070d7e;
+0cee : 07d08e20;
+0cef : d2076ce0;
+0cf0 : 0220da07;
+0cf1 : 8de00220;
+0cf2 : da078de1;
+0cf3 : 022de002;
+0cf4 : c9fff0ed;
+0cf5 : a9008d8e;
+0cf6 : 07f08200;
+0cf7 : 0001d400;
+0cf8 : 0001d409;
+0cf9 : 0001d010;
+0cfa : 0001d301;
+0cfb : 0001d300;
+0cfc : 0001d20a;
+0cfd : 0001d01b;
+0cfe : 0001d018;
+0cff : 0001d017;
+0d00 : 0001d01a;
+0d01 : 0001d403;
+0d02 : 0001d402;
+0d03 : 0001d40e;
+0d04 : 0002007c;
+0d05 : 00020078;
+0d06 : 00020074;
+0d07 : 00020068;
+0d08 : 00020060;
+0d09 : 0002005c;
+0d0a : 00020058;
+0d0b : 00020054;
+0d0c : 00020050;
+0d0d : 0002004c;
+0d0e : 00020048;
+0d0f : 00020044;
+0d10 : 00020040;
+0d11 : 00020028;
+0d12 : 00020024;
+0d13 : 00020020;
+0d14 : 0002001c;
+0d15 : 00020018;
+0d16 : 00020014;
+0d17 : 00020010;
+0d18 : 0002000c;
+0d19 : 00020008;
+0d1a : 00020004;
+END; 
Index: unmerged/zpu_firmware/de1_old/bootdump.c
===================================================================
--- unmerged/zpu_firmware/de1_old/bootdump.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/zpu_firmware/de1_old/debug.c
===================================================================
--- unmerged/zpu_firmware/de1_old/debug.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/debug.c	(revision 1)
@@ -0,0 +1,170 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/core_merge/de1_replay_changes
===================================================================
--- unmerged/core_merge/de1_replay_changes	(nonexistent)
+++ unmerged/core_merge/de1_replay_changes	(revision 1)
@@ -0,0 +1,2062 @@
+diff -r ./address_decoder.vhdl ../../../common/a8core/address_decoder.vhdl
+12a13
+> 
+61c62,64
+< 	rom_select : in std_logic_vector(1 downto 0);
+---
+> 	rom_select : in std_logic_vector(5 downto 0);
+> 	cart_select : in std_logic_vector(6 downto 0);
+> 	cart_activate : in std_logic;
+63c66
+< 	ram_select : in std_logic_vector(1 downto 0);
+---
+> 	ram_select : in std_logic_vector(2 downto 0);
+90c93,94
+< 	
+---
+> 	D6_WR_ENABLE : OUT STD_LOGIC;
+>  	
+113c117,118
+< 	SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+---
+> 	--SDRAM_REQUEST : out std_logic; -- Toggle this to issue a new request
+> 	SDRAM_REQUEST : out std_logic; -- Usual pattern
+116c121,122
+< 	SDRAM_REPLY : in std_logic; -- This matches the request once complete
+---
+> 	--SDRAM_REPLY : in std_logic; -- This matches the request once complete
+> 	SDRAM_REQUEST_COMPLETE : in std_logic;
+146a153
+> 	signal extended_access_addr : std_logic;
+152a160,162
+> 	signal extended_self_test : std_logic;
+> 	signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
+> 	
+164,166c174,176
+< 	signal sdram_request_next : std_logic;
+< 	signal sdram_request_reg : std_logic;
+< 	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+---
+> --	signal sdram_request_next : std_logic;
+> --	signal sdram_request_reg : std_logic;
+> --	signal SDRAM_REQUEST_COMPLETE	: std_logic;
+169a180,195
+> 	signal fetch_wait_next : std_logic_vector(8 downto 0);
+> 	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
+> 	
+> 	signal rom_in_ram : std_logic;
+> 	
+> 	signal antic_fetch_real_next : std_logic;
+> 	signal antic_fetch_real_reg : std_logic;
+> 	signal cpu_fetch_real_next : std_logic;
+> 	signal cpu_fetch_real_reg : std_logic;
+> 
+> 	signal SDRAM_CART_ADDR   : std_logic_vector(22 downto 0);
+> 	signal SDRAM_BASIC_ROM_ADDR  : std_logic_vector(22 downto 0);
+> 	signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
+> 	
+> 	signal sdram_only_bank : std_logic;
+> 	
+182,183c208,213
+< 			sdram_request_reg <= '0';
+< 		elsif (clk'event and clk='1') then
+---
+> 			--sdram_request_reg <= '0';
+> 			fetch_wait_reg <= (others=>'0');
+> 
+> 			cpu_fetch_real_reg <= '0';
+> 			antic_fetch_real_reg <= '0';	
+> 	elsif (clk'event and clk='1') then
+191c221,225
+< 			sdram_request_reg <= sdram_request_next;
+---
+> 			--sdram_request_reg <= sdram_request_next;
+> 			fetch_wait_reg <= fetch_wait_next;
+> 			
+> 			cpu_fetch_real_reg <= cpu_fetch_real_next;
+> 			antic_fetch_real_reg <= antic_fetch_real_next;
+214c248
+< 	process(state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
+---
+> 	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
+220a255
+> 		fetch_wait_next <= std_logic_vector(unsigned(fetch_wait_reg) +1);
+228a264,266
+> 		antic_fetch_real_next <= antic_fetch_real_reg;
+> 		cpu_fetch_real_next <= cpu_fetch_real_reg;
+> 		
+230a269
+> 				fetch_wait_next <= (others=>'0');
+247a287
+> 					antic_fetch_real_next <= '1';
+274a315
+> 					cpu_fetch_real_next <= '1';
+276a318,319
+> 				when others =>
+> 					-- nop
+292a336,337
+> 			when others =>
+> 				-- NOP
+303,304c348,350
+< 	SDRAM_REQUEST <= sdram_request_next;
+< 	SDRAM_REFRESH <= '0'; -- TODO, BROKEN! antic_refresh;
+---
+> 	SDRAM_REQUEST <= sdram_chip_select;
+> 	--SDRAM_REQUEST <= sdram_request_next;
+> 	SDRAM_REFRESH <= '0'; --fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+315,316c361,362
+< 	SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+< 	sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+---
+> 	--SDRAM_REQUEST_COMPLETE <= (SDRAM_REPLY xnor sdram_request_reg) and not(start_request);
+> 	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+318a365
+> 	extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
+320,321c367,420
+< 	extended_access_antic <= (antic_fetch and not(portb(5)));
+< 	extended_access_cpu <= not(antic_fetch) and not(portb(4));
+---
+> 	extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
+> 	extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
+> 	extended_access_either <= extended_access_addr and not(portb(4));
+> 	sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
+> 	
+> 	process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
+> 	begin	
+> 		extended_bank <= "0000000"&addr_next(15 downto 14);
+> 		extended_self_test <= '1';
+> 		
+> 		case ram_select is
+> 			when "000" => -- 64k
+> 				-- default
+> 			when "001" => -- 128k			
+> 				if (extended_access_cpu_or_antic='1') then
+> 					extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
+> 				end if;
+> 			when "010" => -- 320k compy shop
+> 				if (extended_access_cpu_or_antic='1') then
+> 					extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
+> 					extended_self_test <= '0';
+> 				end if;
+> 			when "011" => -- 320k rambo
+> 				if (extended_access_either='1')then
+> 					extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
+> 				end if;
+> 			when "100" => -- 576k compy shop
+> 				if (extended_access_cpu_or_antic='1') then
+> 					extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
+> 					extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
+> 					extended_self_test <= '0';
+> 				end if;
+> 			when "101" => -- 576k rambo
+> 				if (extended_access_either='1') then
+> 					extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
+> 					extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
+> 				end if;
+> 			when "110" => -- 1088k rambo
+> 				if (extended_access_either='1') then
+> 					extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
+> 					extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
+> 					extended_self_test <= '0';
+> 				end if;
+> 			when "111" => -- 4MB!	
+> 				if (extended_access_addr='1') then
+> 					extended_bank(7 downto 0) <= portb(7 downto 0);				
+> 					extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
+> 					extended_self_test <= and_reduce(portb(6 downto 4));	 -- which means self-test is in the middle of half the banks - euuugh, oh well!						
+> 				end if;
+> 			when others =>
+> 				-- TODO - portc!
+> 		end case;
+> 	end process;
+> 
+323c422,436
+< 	extended_access_either <= not(portb(4));
+---
+> 	-- SRAM memory map (512k)
+> 	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
+> 	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP)
+> 	-- SDRAM memory map (8MB)
+> 	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
+> 	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP) 
+> 	-- to 4MB RAM    - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
+> 	-- +64k          - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
+> 	-- SCRATCH       - 4MB+64k-5MB
+> 	-- CARTS         -              "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
+> 	SDRAM_CART_ADDR      <= "101"&cart_select& "0000000000000";
+> 	-- BASIC/OS ROM  -              "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K				
+> 	SDRAM_BASIC_ROM_ADDR <= "111"&"000000"   &"00000000000000";
+> 	SDRAM_OS_ROM_ADDR    <= "111"&rom_select &"00000000000000";
+> 	-- SYSTEM        -              "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
+333c446
+< 		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
+---
+> 		ram_select,cart_rd4,cart_rd5,
+345c458,465
+< 		start_request
+---
+> 		start_request,
+> 		
+> 		rom_in_ram,
+> 		
+> 		-- SDRAM base addresses
+> 		extended_self_test,extended_bank,sdram_only_bank,
+> 		SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
+> 		
+364a485
+> 		D6_WR_ENABLE <= '0';
+377a499,500
+> 		
+> 		rom_in_ram <= '1';
+382,384c505,519
+< 		RAM_ADDR(18 downto 16) <= "000";	
+< 		SDRAM_ADDR(22 downto 16) <= "0000000";
+< 	
+---
+> 		SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
+> 		SDRAM_ADDR(22 downto 14) <= extended_bank;
+> 		RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
+> 		RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
+> 					
+> 		if ((use_sdram or sdram_only_bank)='1') then
+> 			MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+> 			sdram_chip_select <= start_request;
+> 			request_complete <= sdram_request_COMPLETE;														
+> 		else
+> 			MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+> 			ram_chip_select <= start_request;
+> 			request_complete <= ram_request_COMPLETE;									
+> 		end if;
+> 		
+391a527,528
+> 					sdram_chip_select <= '0';
+> 					ram_chip_select <= '0';
+404a542,543
+> 					sdram_chip_select <= '0';
+> 					ram_chip_select <= '0';					
+411a551,552
+> 					sdram_chip_select <= '0';
+> 					ram_chip_select <= '0';					
+418a560,561
+> 					sdram_chip_select <= '0';
+> 					ram_chip_select <= '0';					
+421a565,566
+> 					sdram_chip_select <= '0';
+> 					ram_chip_select <= '0';				
+433,463c578,581
+< 				-- XE RAM
+< 				when 
+< 					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+< 					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+< 					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+< 					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+< 					
+< 					if (use_sdram = '1') then
+< 						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+< 						sdram_chip_select <= start_request;
+< 						request_complete <= sdram_request_COMPLETE;														
+< 					else
+< 						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+< 						ram_chip_select <= start_request;
+< 						request_complete <= ram_request_COMPLETE;									
+< 					end if;
+< 					
+< 					case ram_select is
+< 						when "00" => -- 64k
+< 							-- default
+< 						when "01" => -- 128k					
+< 							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+< 							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+< 						when "10" => -- 320k compy shop
+< 							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+< 							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+< 						when "11" => -- 320k rambo
+< 							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+< 							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+< 					end case;
+< 					
+---
+> 				when X"D6" =>
+> 					D6_WR_ENABLE <= write_enable_next;
+> 					-- TODO - should this still have RAM with covox here?
+> 										
+468,484c586,590
+< 					if (portb(7) = '0' and portb(0) = '1') then
+< 						request_complete <= ROM_REQUEST_COMPLETE;
+< 						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+< 						rom_request <= start_request;					
+< 						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+< 						case rom_select is
+< 							when "00" =>
+< 								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+< 							when "01" =>
+< 								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+< 							when "10" =>
+< 								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+< 							when "11" =>
+< 								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+< 						end case;														
+< 					else				
+< 						if (use_sdram = '1') then
+---
+> 					if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
+> 						sdram_chip_select <= '0';
+> 						ram_chip_select <= '0';	
+> 						
+> 						if (rom_in_ram = '1') then
+486,487d591
+< 							sdram_chip_select <= start_request;
+< 							request_complete <= sdram_request_COMPLETE;														
+489,491c593
+< 							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+< 							ram_chip_select <= start_request;
+< 							request_complete <= ram_request_COMPLETE;									
+---
+> 							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+494,506c596,610
+< 						case ram_select is
+< 							when "00" => -- 64k
+< 								-- default
+< 							when "01" => -- 128k					
+< 								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+< 								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+< 							when "10" => -- 320k compy shop
+< 								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+< 								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+< 							when "11" => -- 320k rambo
+< 								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+< 								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+< 						end case;
+---
+> 						if (write_enable_next = '1') then
+> 							request_complete <= '1';
+> 						else
+> 							if (rom_in_ram = '1') then
+> 								request_complete <= sdram_request_COMPLETE;							
+> 								sdram_chip_select <= start_request;							
+> 							else
+> 								request_complete <= rom_request_COMPLETE;							
+> 								rom_request <= start_request;															
+> 							end if;
+> 						end if;
+> 						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+> 						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
+> 						SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
+> 						ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k						
+519,528c623,624
+< 					else
+< 						if (use_sdram = '1') then
+< 							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+< 							sdram_chip_select <= start_request;
+< 							request_complete <= sdram_request_COMPLETE;														
+< 						else
+< 							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+< 							ram_chip_select <= start_request;
+< 							request_complete <= ram_request_COMPLETE;									
+< 						end if;
+---
+> 						sdram_chip_select <= '0';
+> 						ram_chip_select <= '0';							
+540a637,638
+> 						sdram_chip_select <= '0';
+> 						ram_chip_select <= '0';													
+543,548c641,646
+< 							request_complete <= ROM_REQUEST_COMPLETE;
+< 							MEMORY_DATA(7 downto 0) <= ROM_DATA;
+< 							rom_request <= start_request;
+< 							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+< 						else
+< 							if (use_sdram = '1') then
+---
+> 							sdram_chip_select <= '0';
+> 							ram_chip_select <= '0';							
+> 							--request_complete <= ROM_REQUEST_COMPLETE;
+> 							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+> 							--rom_request <= start_request;					
+> 							if (rom_in_ram = '1') then
+550,551d647
+< 								sdram_chip_select <= start_request;
+< 								request_complete <= sdram_request_COMPLETE;														
+553,555c649
+< 								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+< 								ram_chip_select <= start_request;
+< 								request_complete <= ram_request_COMPLETE;									
+---
+> 								MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+556a651,665
+> 							if (write_enable_next = '1') then
+> 								request_complete <= '1';
+> 							else
+> 								if (rom_in_ram = '1') then
+> 									request_complete <= sdram_request_COMPLETE;							
+> 									sdram_chip_select <= start_request;							
+> 								else
+> 									request_complete <= rom_request_COMPLETE;							
+> 									rom_request <= start_request;															
+> 								end if;
+> 							end if;
+> 						
+> 							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+> 						 SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
+> 						 SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k							
+569,584c678,683
+< 						request_complete <= ROM_REQUEST_COMPLETE;
+< 						MEMORY_DATA(7 downto 0) <= ROM_DATA;
+< 						rom_request <= start_request;
+< 						case rom_select is
+< 							when "00" =>
+< 								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+< 							when "01" =>
+< 								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+< 							when "10" =>
+< 								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+< 							when "11" =>
+< 								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+< 						end case;
+< 								
+< 					else
+< 						if (use_sdram = '1') then
+---
+> 						sdram_chip_select <= '0';
+> 						ram_chip_select <= '0';																		
+> 						--request_complete <= ROM_REQUEST_COMPLETE;
+> 						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+> 						--rom_request <= start_request;					
+> 						if (rom_in_ram = '1') then
+586,587d684
+< 							sdram_chip_select <= start_request;
+< 							request_complete <= sdram_request_COMPLETE;														
+589,591c686
+< 							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+< 							ram_chip_select <= start_request;
+< 							request_complete <= ram_request_COMPLETE;									
+---
+> 							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
+592a688,702
+> 						if (write_enable_next = '1') then
+> 							request_complete <= '1';
+> 						else
+> 								if (rom_in_ram = '1') then
+> 									request_complete <= sdram_request_COMPLETE;							
+> 									sdram_chip_select <= start_request;							
+> 								else
+> 									request_complete <= rom_request_COMPLETE;							
+> 									rom_request <= start_request;															
+> 								end if;						
+> 						end if;																			
+> 
+> 						ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+> 						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
+> 						SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
+596,604d705
+< 					if (use_sdram = '1') then
+< 						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+< 						sdram_chip_select <= start_request;
+< 						request_complete <= sdram_request_COMPLETE;														
+< 					else
+< 						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+< 						ram_chip_select <= start_request;
+< 						request_complete <= ram_request_COMPLETE;									
+< 					end if;
+606a708,709
+> 			sdram_chip_select <= '0';
+> 			ram_chip_select <= '0';													
+626a730,731
+> 				when others =>
+> 					-- NOP
+diff -r ./antic.vhdl ../../../common/a8core/antic.vhdl
+50c50,52
+< 	dma_clock_out : out std_logic
+---
+> 	dma_clock_out : out std_logic;
+> 	hcount_out : out std_logic_vector(7 downto 0);
+> 	vcount_out : out std_logic_vector(8 downto 0)
+478,479c480,482
+< 	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+< 	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
+---
+> 	-- TODO - these should change with cycle_length...
+> 	signal colour_clock_count_next : std_logic_vector(3 downto 0);
+> 	signal colour_clock_count_reg : std_logic_vector(3 downto 0);
+481c484
+< 	constant cycle_length : integer := 32;	
+---
+> 	constant cycle_length : integer := 16;	
+658c661
+< 			colour_clock_count_next <= "00001";
+---
+> 			colour_clock_count_next <= "0001";
+663,664c666,667
+< 		case colour_clock_count_reg(4 downto 0) is
+< 		when "00000" =>
+---
+> 		case colour_clock_count_reg(3 downto 0) is
+> 		when "0000" =>
+669c672
+< 		when "00100" =>
+---
+> 		when "0010" =>
+671c674
+< 		when "01000" =>
+---
+> 		when "0100" =>
+674c677
+< 		when "01100" =>
+---
+> 		when "0110" =>
+676c679
+< 		when "10000" =>			
+---
+> 		when "1000" =>			
+680c683
+< 		when "10100" =>
+---
+> 		when "1010" =>
+682c685
+< 		when "11000" =>
+---
+> 		when "1100" =>
+685c688
+< 		when "11100" =>
+---
+> 		when "1110" =>
+1157a1161,1162
+> 			when others =>
+> 				-- nothing
+1401a1407,1408
+> 			when others =>
+> 				-- nothing
+1593a1601,1602
+> 					when others =>
+> 						-- nop
+1606a1616,1617
+> 					when others =>
+> 						-- nop
+1821a1833,1835
+> 
+> 	vcount_out <= vcount_reg;
+> 	hcount_out <= hcount_reg;
+Only in .: atari800core.jdi
+Only in .: atari800core.qpf
+Only in .: atari800core.qsf
+Only in .: atari800core.qsf~
+Only in .: atari800core.qws
+Only in .: atari800core.sdc
+Only in .: atari800core.sdc~
+diff -r ./atari800core.vhd ../../../common/a8core/atari800core.vhd
+1d0
+< -- Copyright (C) 1991-2012 Altera Corporation
+20a20,21
+> use IEEE.STD_LOGIC_MISC.all;
+> use ieee.numeric_std.all;
+27,44c28,30
+< 		CLOCK_50 :  IN  STD_LOGIC;
+< 		AUD_BCLK :  IN  STD_LOGIC;
+< 		AUD_DACLRCK :  IN  STD_LOGIC;
+< 		PS2_CLK :  IN  STD_LOGIC;
+< 		PS2_DAT :  IN  STD_LOGIC;
+< 		UART_RXD :  IN  STD_LOGIC;
+< 		SD_DATA :  IN  STD_LOGIC;
+< 		I2C_SCLK :  INOUT  STD_LOGIC;
+< 		I2C_SDAT :  INOUT  STD_LOGIC;
+< 		DRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		FL_DQ :  IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		GPIO_0 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+< 		GPIO_1 :  INOUT  STD_LOGIC_VECTOR(35 DOWNTO 0);
+< 		KEY :  IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		SRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		SW :  IN  STD_LOGIC_VECTOR(9 DOWNTO 0);
+< 		AUD_XCK :  OUT  STD_LOGIC;
+< 		AUD_DACDAT :  OUT  STD_LOGIC;
+---
+> 		CLK :  IN  STD_LOGIC;
+> 		PLL_LOCKED: IN STD_LOGIC;
+> 
+47,80c33,66
+< 		FL_OE_N :  OUT  STD_LOGIC;
+< 		FL_WE_N :  OUT  STD_LOGIC;
+< 		FL_RST_N :  OUT  STD_LOGIC;
+< 		SRAM_CE_N :  OUT  STD_LOGIC;
+< 		SRAM_OE_N :  OUT  STD_LOGIC;
+< 		SRAM_WE_N :  OUT  STD_LOGIC;
+< 		SRAM_LB_N :  OUT  STD_LOGIC;
+< 		SRAM_UB_N :  OUT  STD_LOGIC;
+< 		UART_TXD :  OUT  STD_LOGIC;
+< 		DRAM_BA_0 :  OUT  STD_LOGIC;
+< 		DRAM_BA_1 :  OUT  STD_LOGIC;
+< 		DRAM_CS_N :  OUT  STD_LOGIC;
+< 		DRAM_RAS_N :  OUT  STD_LOGIC;
+< 		DRAM_CAS_N :  OUT  STD_LOGIC;
+< 		DRAM_WE_N :  OUT  STD_LOGIC;
+< 		DRAM_LDQM :  OUT  STD_LOGIC;
+< 		DRAM_UDQM :  OUT  STD_LOGIC;
+< 		DRAM_CLK :  OUT  STD_LOGIC;
+< 		DRAM_CKE :  OUT  STD_LOGIC;
+< 		SD_CLK :  OUT  STD_LOGIC;
+< 		SD_CMD :  OUT  STD_LOGIC;
+< 		SD_THREE :  OUT  STD_LOGIC;
+< 		DRAM_ADDR :  OUT  STD_LOGIC_VECTOR(11 DOWNTO 0);
+< 		FL_ADDR :  OUT  STD_LOGIC_VECTOR(21 DOWNTO 0);
+< 		HEX0 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+< 		HEX1 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+< 		HEX2 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+< 		HEX3 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0);
+< 		LEDG :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		LEDR :  OUT  STD_LOGIC_VECTOR(9 DOWNTO 0);
+< 		SRAM_ADDR :  OUT  STD_LOGIC_VECTOR(17 DOWNTO 0);
+< 		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0)
+---
+> 		VGA_B :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+> 		VGA_G :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+> 		VGA_R :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+> 		
+> 		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+> 		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+> 
+> 		matrix_out : in std_logic_vector(15 downto 0);
+> 		matrix_in : out std_logic_vector(7 downto 0);
+> 		static_keys : in std_logic_vector(6 downto 0);
+> 		pause_key : in std_logic;
+> 		
+> 		AUDIO_L : OUT std_logic_vector(15 downto 0);
+> 		AUDIO_R : OUT std_logic_vector(15 downto 0);
+> 
+> 		SDRAM_REQUEST : OUT std_logic;
+> 		SDRAM_REQUEST_COMPLETE : IN std_logic;
+> 		SDRAM_READ_ENABLE : out STD_LOGIC;
+> 		SDRAM_WRITE_ENABLE : out std_logic;
+> 		SDRAM_DI : out std_logic_vector(31 downto 0);
+> 		SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
+> 		SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
+> 		SDRAM_WIDTH_8bit_ACCESS : out std_logic;
+> 		SDRAM_WIDTH_16bit_ACCESS : out std_logic;
+> 		SDRAM_WIDTH_32bit_ACCESS : out std_logic;
+> 
+> 		SIO_RXD : in std_logic;
+> 		SIO_TXD : out std_logic;
+> 		SIO_COMMAND_TX : out std_logic;
+> 
+>    		ram_select : in std_logic_vector(2 downto 0);
+>     		rom_select : in std_logic_vector(5 downto 0);
+> 
+> 		halt : in std_logic
+84a71,87
+> component synchronizer IS
+> PORT 
+> ( 
+> 	CLK : IN STD_LOGIC;
+> 	RAW : IN STD_LOGIC;
+> 	SYNC : OUT STD_LOGIC
+> );
+> END component;
+> 
+> COMPONENT complete_address_decoder IS
+> generic (width : natural := 1);
+> PORT 
+> ( 
+> 	addr_in : in std_logic_vector(width-1 downto 0);			
+> 	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
+> );
+> END component;
+103,126c106,121
+< COMPONENT hexdecoder
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 NUMBER : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		 DIGIT : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT sram
+< 	PORT(WREN : IN STD_LOGIC;
+< 		 clk : IN STD_LOGIC;
+< 		 reset_n : IN STD_LOGIC;
+< 		 request : IN STD_LOGIC;
+< 		 width_16bit : IN STD_LOGIC;
+< 		 ADDRESS : IN STD_LOGIC_VECTOR(18 DOWNTO 0);
+< 		 DIN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		 SRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		 SRAM_CE_N : OUT STD_LOGIC;
+< 		 SRAM_OE_N : OUT STD_LOGIC;
+< 		 SRAM_WE_N : OUT STD_LOGIC;
+< 		 SRAM_LB_N : OUT STD_LOGIC;
+< 		 SRAM_UB_N : OUT STD_LOGIC;
+< 		 complete : OUT STD_LOGIC;
+< 		 DOUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		 SRAM_ADDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0)
+---
+> component internalromram IS
+>   PORT(
+>     clock   : IN     STD_LOGIC;                             --system clock
+>     reset_n : IN     STD_LOGIC;                             --asynchronous reset
+> 
+> 	ROM_ADDR : in STD_LOGIC_VECTOR(21 downto 0);
+> 	ROM_REQUEST_COMPLETE : out STD_LOGIC;
+> 	ROM_REQUEST : in std_logic;
+> 	ROM_DATA : out std_logic_vector(7 downto 0);
+> 	
+> 	RAM_ADDR : in STD_LOGIC_VECTOR(18 downto 0);
+> 	RAM_WR_ENABLE : in std_logic;
+> 	RAM_DATA_IN : in STD_LOGIC_VECTOR(7 downto 0);
+> 	RAM_REQUEST_COMPLETE : out STD_LOGIC;
+> 	RAM_REQUEST : in std_logic;
+> 	RAM_DATA : out std_logic_vector(7 downto 0)
+128c123,124
+< END COMPONENT;
+---
+> 	
+> END component;
+149a146,147
+> 		 hcount_out : out std_logic_vector(7 downto 0);
+> 		 vcount_out : out std_logic_vector(8 downto 0);
+156,164d153
+< COMPONENT ledsw
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+< 		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+171a161,162
+> 		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+> 		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+177,188d167
+< COMPONENT ps2_keyboard
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 RESET_N : IN STD_LOGIC;
+< 		 PS2_CLK : IN STD_LOGIC;
+< 		 PS2_DAT : IN STD_LOGIC;
+< 		 KEY_EVENT : OUT STD_LOGIC;
+< 		 KEY_EXTENDED : OUT STD_LOGIC;
+< 		 KEY_UP : OUT STD_LOGIC;
+< 		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+197a177
+> 		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+292,375d271
+< COMPONENT pokey_ps2_decoder
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 RESET_N : IN STD_LOGIC;
+< 		 KEY_EVENT : IN STD_LOGIC;
+< 		 KEY_EXTENDED : IN STD_LOGIC;
+< 		 KEY_UP : IN STD_LOGIC;
+< 		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 KEY_HELD : OUT STD_LOGIC;
+< 		 SHIFT_PRESSED : OUT STD_LOGIC;
+< 		 BREAK_PRESSED : OUT STD_LOGIC;
+< 		 KEY_INTERRUPT : OUT STD_LOGIC;
+< 		 CONSOL_START : OUT STD_LOGIC;
+< 		 CONSOL_SELECT : OUT STD_LOGIC;
+< 		 CONSOL_OPTION : OUT STD_LOGIC;
+< 		 SYSTEM_RESET : OUT STD_LOGIC;
+< 		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT gpio
+< 	PORT(
+< 	clk : in std_logic;
+< 	
+< 	gpio_enable : in std_logic;
+< 
+< 	-- pia
+< 	porta_in : out std_logic_vector(7 downto 0);
+< 	virtual_stick_in : in std_logic_vector(7 downto 0);
+< 	porta_out : in std_logic_vector(7 downto 0);
+< 	porta_output : in std_logic_vector(7 downto 0);
+< 	CA2_DIR_OUT : IN std_logic;
+< 	CA2_OUT : IN std_logic;
+< 	CA2_IN : OUT STD_LOGIC;
+< 	CB2_DIR_OUT : IN std_logic;
+< 	CB2_OUT : IN std_logic;
+< 	CB2_IN : OUT STD_LOGIC;
+< 	
+< 	-- gtia
+< 	virtual_trig_in : in std_logic_vector(3 downto 0);
+< 	trig_in : out std_logic_vector(3 downto 0);
+< 	
+< 	-- antic
+< 	lightpen : out std_logic;
+< 	
+< 	-- pokey
+< 	pot_reset : in std_logic;
+< 	pot_in : out std_logic_vector(7 downto 0);
+< 	keyboard_scan : in std_logic_vector(5 downto 0);
+< 	keyboard_response : out std_logic_vector(1 downto 0);
+< 	virtual_keycode : in std_logic_vector(5 downto 0);
+< 	virtual_keyheld : in std_logic;
+< 	virtual_shift_pressed : in std_logic;
+< 	virtual_control_pressed : in std_logic;
+< 	virtual_break_pressed : in std_logic;
+< 	SIO_IN : OUT STD_LOGIC;
+< 	SIO_OUT : IN STD_LOGIC;
+< 	
+< 	-- cartridge
+< 	pbi_addr_out : in std_logic_vector(15 downto 0);
+< 	pbi_write_enable : in std_logic;
+< 	cart_data_read : out std_logic_vector(7 downto 0);
+< 	cart_request : in std_logic;
+< 	cart_complete : out std_logic;
+< 	cart_data_write : in std_logic_vector(7 downto 0);
+< 	rd4 : out std_logic;
+< 	rd5 : out std_logic;
+< 	s4_n : in std_logic;
+< 	s5_n : in std_logic;
+< 	cctl_n : in std_logic;
+< 	
+< 	monitor : in std_logic;
+< 	
+< 	-- gpio connections
+< 	GPIO_0_IN : in std_logic_vector(35 downto 0);
+< 	GPIO_0_OUT : out std_logic_vector(35 downto 0);
+< 	GPIO_0_DIR_OUT : out std_logic_vector(35 downto 0);
+< 	GPIO_1_IN : in std_logic_vector(35 downto 0);
+< 	GPIO_1_OUT : out std_logic_vector(35 downto 0);
+< 	GPIO_1_DIR_OUT : out std_logic_vector(35 downto 0)
+< 	);
+< END COMPONENT;
+< 
+394c290
+< 		 SDRAM_REPLY : IN STD_LOGIC;
+---
+> 		 SDRAM_REQUEST_COMPLETE : IN STD_LOGIC;
+410c306
+< 		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+---
+> 		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+412c308,310
+< 		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+---
+> 		 rom_select : in std_logic_vector(5 downto 0);
+> 		 cart_select : in std_logic_vector(6 downto 0);
+> 		 cart_activate : in std_logic;
+445,479c343,344
+< 		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT sdram_statemachine
+< GENERIC (ADDRESS_WIDTH : INTEGER;
+< 			AP_BIT : INTEGER;
+< 			COLUMN_WIDTH : INTEGER;
+< 			ROW_WIDTH : INTEGER
+< 			);
+< 	PORT(CLK_SYSTEM : IN STD_LOGIC;
+< 		 CLK_SDRAM : IN STD_LOGIC;
+< 		 RESET_N : IN STD_LOGIC;
+< 		 READ_EN : IN STD_LOGIC;
+< 		 WRITE_EN : IN STD_LOGIC;
+< 		 REQUEST : IN STD_LOGIC;
+< 		 BYTE_ACCESS : IN STD_LOGIC;
+< 		 WORD_ACCESS : IN STD_LOGIC;
+< 		 LONGWORD_ACCESS : IN STD_LOGIC;
+< 		 REFRESH : IN STD_LOGIC;
+< 		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+< 		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+< 		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		 REPLY : OUT STD_LOGIC;
+< 		 SDRAM_BA0 : OUT STD_LOGIC;
+< 		 SDRAM_BA1 : OUT STD_LOGIC;
+< 		 SDRAM_CKE : OUT STD_LOGIC;
+< 		 SDRAM_CS_N : OUT STD_LOGIC;
+< 		 SDRAM_RAS_N : OUT STD_LOGIC;
+< 		 SDRAM_CAS_N : OUT STD_LOGIC;
+< 		 SDRAM_WE_N : OUT STD_LOGIC;
+< 		 SDRAM_ldqm : OUT STD_LOGIC;
+< 		 SDRAM_udqm : OUT STD_LOGIC;
+< 		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+< 		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+---
+> 		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+> 		 D6_WR_ENABLE : out std_logic
+490,515c355,379
+< COMPONENT scandoubler
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 RESET_N : IN STD_LOGIC;
+< 		 VGA : IN STD_LOGIC;
+< 		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+< 		 colour_enable : IN STD_LOGIC;
+< 		 doubled_enable : IN STD_LOGIC;
+< 		 vsync_in : IN STD_LOGIC;
+< 		 hsync_in : IN STD_LOGIC;
+< 		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 VSYNC : OUT STD_LOGIC;
+< 		 HSYNC : OUT STD_LOGIC;
+< 		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+< 		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT zpu_ram
+< 	PORT(wren : IN STD_LOGIC;
+< 		 clock : IN STD_LOGIC;
+< 		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+< 		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+< 	);
+< END COMPONENT;
+---
+> --COMPONENT zpu_ram
+> --	PORT(wren : IN STD_LOGIC;
+> --		 clock : IN STD_LOGIC;
+> --		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+> --		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+> --		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+> --	);
+> --END COMPONENT;
+> 
+> component generic_ram_infer IS
+>         generic
+>         (
+>                 ADDRESS_WIDTH : natural := 9;
+>                 SPACE : natural := 512;
+>                 DATA_WIDTH : natural := 8
+>         );
+>    PORT
+>    (
+>       clock: IN   std_logic;
+>       data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+>       address:  IN   std_logic_vector(address_width-1 downto 0);
+>       we:    IN   std_logic;
+>       q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+>    );
+> END component;
+547c411
+< 		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+---
+> 		 RAM_SELECT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+550,589c414,417
+< 		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT i2c_loader
+< GENERIC (device_address : INTEGER;
+< 			log2_divider : INTEGER;
+< 			num_retries : INTEGER
+< 			);
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 nRESET : IN STD_LOGIC;
+< 		 I2C_SCL : INOUT STD_LOGIC;
+< 		 I2C_SDA : INOUT STD_LOGIC;
+< 		 IS_DONE : OUT STD_LOGIC;
+< 		 IS_ERROR : OUT STD_LOGIC
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT flashrom
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 RESET_N : IN STD_LOGIC;
+< 		 REQUEST : IN STD_LOGIC;
+< 		 ADDRESS : IN STD_LOGIC_VECTOR(21 DOWNTO 0);
+< 		 FLASH_D : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 FLASH_CE_N : OUT STD_LOGIC;
+< 		 FLASH_OE_N : OUT STD_LOGIC;
+< 		 FLASH_WE_N : OUT STD_LOGIC;
+< 		 FLASH_RESET_N : OUT STD_LOGIC;
+< 		 COMPLETE : OUT STD_LOGIC;
+< 		 DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+< 		 FLASH_ADDRESS : OUT STD_LOGIC_VECTOR(21 DOWNTO 0)
+< 	);
+< END COMPONENT;
+< 
+< COMPONENT pll
+< 	PORT(inclk0 : IN STD_LOGIC;
+< 		 c0 : OUT STD_LOGIC;
+< 		 c1 : OUT STD_LOGIC;
+< 		 c2 : OUT STD_LOGIC;
+< 		 locked : OUT STD_LOGIC
+---
+> 		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+> 		 sector : out std_logic_vector(31 downto 0);
+> 		 sector_request : out std_logic;
+> 		 sector_ready : in std_logic
+593,602c421,430
+< COMPONENT i2sslave
+< 	PORT(CLK : IN STD_LOGIC;
+< 		 BCLK : IN STD_LOGIC;
+< 		 DACLRC : IN STD_LOGIC;
+< 		 LEFT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		 RIGHT_IN : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+< 		 MCLK_2 : OUT STD_LOGIC;
+< 		 DACDAT : OUT STD_LOGIC
+< 	);
+< END COMPONENT;
+---
+> COMPONENT gtia_palette IS
+> PORT 
+> ( 
+> 	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
+> 	
+> 	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+> 	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
+> 	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
+> );
+> END component;
+628a457
+> 		 BLANK : OUT STD_LOGIC;
+659a489,505
+> component covox IS
+> PORT 
+> ( 
+> 	CLK : IN STD_LOGIC;
+> 	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
+> 	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+> 	WR_EN : IN STD_LOGIC;
+> 	
+> 	covox_channel0 : out std_logic_vector(7 downto 0);
+> 	covox_channel1 : out std_logic_vector(7 downto 0);
+> 	covox_channel2 : out std_logic_vector(7 downto 0);
+> 	covox_channel3 : out std_logic_vector(7 downto 0)
+> );
+> END component;
+> 
+> 
+> 
+672,673d517
+< SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+< SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+675c519
+< SIGNAL	CART_CCTL_N :  STD_LOGIC;
+---
+> 
+682a527
+> signal CART_CCTL_N : std_logic;
+687,688d531
+< SIGNAL	CLK :  STD_LOGIC;
+< SIGNAL	CLK_SDRAM :  STD_LOGIC;
+731a575
+> SIGNAL	HALT_OR_PAUSE_6502 :  STD_LOGIC;
+739d582
+< SIGNAL	PLL_LOCKED :  STD_LOGIC;
+759c602
+< SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+---
+> SIGNAL	RAM_SELECT_dummy :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+766c609
+< SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+---
+> SIGNAL	ROM_SELECT_dummy :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+769,771d611
+< SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+< SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+< SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+773,775c613
+< SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+< SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+< SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+---
+> --SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+788a627
+> SIGNAL	VIRTUAL_KEYS :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+807a647
+> SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+809,823d648
+< SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+< SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+< SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+< SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+< SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+< SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+< SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+824a650,652
+> SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+> SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+> signal UART_TXD_dummy : std_logic;
+826c654,688
+< BEGIN 
+---
+> SIGNAL		SD_DAT0 :  STD_LOGIC;
+> SIGNAL		SD_CLK :  STD_LOGIC;
+> SIGNAL		SD_CMD :  STD_LOGIC;
+> SIGNAL		SD_DAT3 :  STD_LOGIC;
+> 
+> signal mist_buttons : std_logic_vector(1 downto 0);
+> signal mist_switches : std_logic_vector(1 downto 0);
+> 
+> SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
+> SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
+> SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
+> 
+> signal dummy_sector_request : std_logic;
+> signal dummy_sector : std_logic_vector(31 downto 0);
+> 
+> signal COLOUR : std_logic_vector(7 downto 0);
+> 
+> signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
+> signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
+> signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
+> signal POKEY1_CHANNEL3 : std_logic_vector(3 downto 0);
+> 
+> signal POKEY2_CHANNEL0 : std_logic_vector(3 downto 0);
+> signal POKEY2_CHANNEL1 : std_logic_vector(3 downto 0);
+> signal POKEY2_CHANNEL2 : std_logic_vector(3 downto 0);
+> signal POKEY2_CHANNEL3 : std_logic_vector(3 downto 0);
+> 
+> signal hcount_temp : std_logic_vector(7 downto 0);
+> signal vcount_temp : std_logic_vector(8 downto 0);
+> signal VGA_G_dummy : std_logic_vector(7 downto 0);
+> signal VGA_B_dummy : std_logic_vector(7 downto 0);
+> 
+> signal matrix_out_match : std_logic_vector(7 downto 0);
+> 
+> signal keyboard_scan_inv : std_logic_vector(5 downto 0);
+827a690,694
+> signal covox_write_enable : std_logic;
+> signal covox_channel0 : std_logic_vector(7 downto 0);
+> signal covox_channel1 : std_logic_vector(7 downto 0);
+> signal covox_channel2 : std_logic_vector(7 downto 0);
+> signal covox_channel3 : std_logic_vector(7 downto 0);
+828a696
+> signal gtia_blank : std_logic;
+830c698,700
+< b2v_a_6502 : cpu
+---
+> BEGIN 
+> 
+> cpu6502 : cpu
+845,889c715,716
+< 
+< b2v_hex0_inst : hexdecoder
+< PORT MAP(CLK => CLK,
+< 		 NUMBER => ZPU_HEX(3 DOWNTO 0),
+< 		 DIGIT => HEX0);
+< 
+< 
+< b2v_hex0_inst2 : hexdecoder
+< PORT MAP(CLK => CLK,
+< 		 NUMBER => ZPU_HEX(7 DOWNTO 4),
+< 		 DIGIT => HEX1);
+< 
+< 
+< b2v_hex0_inst3 : hexdecoder
+< PORT MAP(CLK => CLK,
+< 		 NUMBER => ZPU_HEX(11 DOWNTO 8),
+< 		 DIGIT => HEX2);
+< 
+< 
+< b2v_hex0_inst4 : hexdecoder
+< PORT MAP(CLK => CLK,
+< 		 NUMBER => ZPU_HEX(15 DOWNTO 12),
+< 		 DIGIT => HEX3);
+< 
+< 
+< b2v_inst : sram
+< PORT MAP(WREN => RAM_WRITE_ENABLE,
+< 		 clk => CLK,
+< 		 reset_n => RESET_N,
+< 		 request => RAM_REQUEST,
+< 		 width_16bit => WIDTH_16BIT_ACCESS,
+< 		 ADDRESS => RAM_ADDR,
+< 		 DIN => WRITE_DATA(15 DOWNTO 0),
+< 		 SRAM_DQ => SRAM_DQ,
+< 		 SRAM_CE_N => SRAM_CE_N,
+< 		 SRAM_OE_N => SRAM_OE_N,
+< 		 SRAM_WE_N => SRAM_WE_N,
+< 		 SRAM_LB_N => SRAM_LB_N,
+< 		 SRAM_UB_N => SRAM_UB_N,
+< 		 complete => RAM_REQUEST_COMPLETE,
+< 		 DOUT => RAM_DO,
+< 		 SRAM_ADDR => SRAM_ADDR);
+< 
+< 
+< b2v_inst1 : antic
+---
+> LIGHTPEN <= '1';
+> antic1 : antic
+906a734,735
+> 		 hcount_out => hcount_temp,
+> 		 vcount_out => vcount_temp,
+912,921c741
+< 
+< b2v_inst10 : ledsw
+< PORT MAP(CLK => CLK,
+< 		 KEY => KEY,
+< 		 SW => SW,
+< 		 SYNC_KEYS => SYNC_KEYS,
+< 		 SYNC_SWITCHES => SYNC_SWITCHES);
+< 
+< 
+< b2v_inst11 : pokey_mixer
+---
+> pokey_mixer_l : pokey_mixer
+924,927c744,747
+< 		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+< 		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+< 		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+< 		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
+---
+> 		 CHANNEL_0 => POKEY1_CHANNEL0,
+> 		 CHANNEL_1 => POKEY1_CHANNEL1,
+> 		 CHANNEL_2 => POKEY1_CHANNEL2,
+> 		 CHANNEL_3 => POKEY1_CHANNEL3,
+929,943c749,753
+< 		 VOLUME_OUT => AUDIO_LEFT);
+< 
+< 
+< b2v_inst12 : ps2_keyboard
+< PORT MAP(CLK => CLK,
+< 		 RESET_N => RESET_N,
+< 		 PS2_CLK => PS2_CLK,
+< 		 PS2_DAT => PS2_DAT,
+< 		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+< 		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+< 		 KEY_UP => SYNTHESIZED_WIRE_10,
+< 		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+< 
+< 
+< b2v_inst13 : zpu_glue
+---
+> 		 COVOX_CHANNEL_0 => covox_channel0,
+> 		 COVOX_CHANNEL_1 => covox_channel1,
+> 		 VOLUME_OUT => AUDIO_L);
+> 		 
+> zpu_glue1 : zpu_glue
+951a762
+> 		 ZPU_SECTOR_DI => zpu_sector_data,
+964c775
+< b2v_inst14 : pokey_mixer
+---
+> pokey_mixer_r : pokey_mixer
+967,970c778,783
+< 		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+< 		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+< 		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+< 		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
+---
+> 		 CHANNEL_0 => POKEY2_CHANNEL0,
+> 		 CHANNEL_1 => POKEY2_CHANNEL1,
+> 		 CHANNEL_2 => POKEY2_CHANNEL2,
+> 		 CHANNEL_3 => POKEY2_CHANNEL3,
+> 		 COVOX_CHANNEL_0 => covox_channel2,
+> 		 COVOX_CHANNEL_1 => covox_channel3,
+972c785
+< 		 VOLUME_OUT => AUDIO_RIGHT);
+---
+> 		 VOLUME_OUT => AUDIO_R);
+975c788
+< b2v_inst15 : pokey
+---
+> pokey2 : pokey
+983,986c796,799
+< 		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+< 		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+< 		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+< 		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
+---
+> 		 CHANNEL_0_OUT => POKEY2_CHANNEL0,
+> 		 CHANNEL_1_OUT => POKEY2_CHANNEL1,
+> 		 CHANNEL_2_OUT => POKEY2_CHANNEL2,
+> 		 CHANNEL_3_OUT => POKEY2_CHANNEL3,
+1001a815
+> SIO_COMMAND_TX <= SIO_COMMAND_OUT;
+1003a818,820
+> GPIO_CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
+> GPIO_CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
+> GPIO_PORTA_IN <= ((JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)&JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
+1005c822
+< b2v_inst16 : pia
+---
+> pia1 : pia
+1030c847,848
+< b2v_inst17 : shared_enable
+---
+> HALT_OR_PAUSE_6502 <= HALT or PAUSE_6502;
+> enables : shared_enable
+1035c853
+< 		 PAUSE_6502 => PAUSE_6502,
+---
+> 		 PAUSE_6502 => HALT_OR_PAUSE_6502,
+1043a862,866
+> -- no cart!
+> CART_RD4 <= '0';
+> CART_RD5 <= '0';
+> CART_REQUEST_COMPLETE <= '0';
+> CART_ROM_DO <= (others=>'0');
+1045,1121c868
+< b2v_inst18 : pokey_ps2_decoder
+< PORT MAP(CLK => CLK,
+< 		 RESET_N => RESET_N,
+< 		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+< 		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+< 		 KEY_UP => SYNTHESIZED_WIRE_10,
+< 		 KEY_CODE => SYNTHESIZED_WIRE_11,
+< 		 KEY_HELD => KEY_HELD,
+< 		 SHIFT_PRESSED => SHIFT_PRESSED,
+< 		 BREAK_PRESSED => BREAK_PRESSED,
+< 		 CONSOL_START => CONSOL_START,
+< 		 CONSOL_SELECT => CONSOL_SELECT,
+< 		 CONSOL_OPTION => CONSOL_OPTION,
+< 		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+< 		 KBCODE => KBCODE,
+< 		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+< 		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS);
+< 
+< gpio0_gen:
+<    for I in 0 to 35 generate
+< 		gpio_0(I) <= gpio_0_out(I) when gpio_0_dir_out(I)='1' else 'Z';
+<    end generate gpio0_gen;
+< 
+< gpio1_gen:
+<    for I in 0 to 35 generate
+< 		gpio_1(I) <= gpio_1_out(I) when gpio_1_dir_out(I)='1' else 'Z';
+<    end generate gpio1_gen;
+< 	
+< b2v_inst19 : gpio
+< PORT MAP(clk => CLK,
+< 		 gpio_enable => GPIO_ENABLE,
+< 		 pot_reset => POT_RESET,
+< 		 virtual_keyheld => KEY_HELD,
+< 		 virtual_shift_pressed => SHIFT_PRESSED,
+< 		 virtual_control_pressed => KBCODE(7),
+< 		 virtual_break_pressed => BREAK_PRESSED,
+< 		 pbi_write_enable => PBI_WRITE_ENABLE,
+< 		 cart_request => CART_REQUEST,
+< 		 s4_n => CART_S4_n,
+< 		 s5_n => CART_S5_N,
+< 		 cctl_n => CART_CCTL_N,
+< 		 cart_data_write => WRITE_DATA(7 DOWNTO 0),
+< 		 GPIO_0_IN => GPIO_0,
+< 		 GPIO_0_OUT => GPIO_0_OUT,
+< 		 GPIO_0_DIR_OUT => GPIO_0_DIR_OUT,
+< 		 GPIO_1_IN => GPIO_1,
+< 		 GPIO_1_OUT => GPIO_1_OUT,
+< 		 GPIO_1_DIR_OUT => GPIO_1_DIR_OUT,		 
+< 		 keyboard_scan => KEYBOARD_SCAN,
+< 		 pbi_addr_out => PBI_ADDR,
+< 		 porta_out => PORTA_OUT,
+< 		 porta_output => PORTA_DIR_OUT,
+< 		 virtual_keycode => KBCODE(5 DOWNTO 0),
+< 		 virtual_stick_in => VIRTUAL_STICKS,
+< 		 virtual_trig_in => VIRTUAL_TRIGGERS,
+< 		 lightpen => LIGHTPEN,
+< 		 cart_complete => CART_REQUEST_COMPLETE,
+< 		 rd4 => CART_RD4,
+< 		 rd5 => CART_RD5,
+< 		 cart_data_read => CART_ROM_DO,
+< 		 keyboard_response => KEYBOARD_RESPONSE,
+< 		 porta_in => GPIO_PORTA_IN,
+< 		 pot_in => POT_IN,
+< 		 trig_in => TRIGGERS,
+< 		 monitor => SIO_DATA_IN, -- i.e. zpu sio out
+< 		 CA2_DIR_OUT => CA2_DIR_OUT,
+< 		 CA2_OUT => CA2_OUT,
+< 		 CA2_IN => GPIO_CA2_IN,
+< 		 CB2_DIR_OUT => CB2_DIR_OUT,
+< 		 CB2_OUT => CB2_OUT,
+< 		 CB2_IN => GPIO_CB2_IN,
+< 		 SIO_IN => GPIO_SIO_IN,
+< 		 SIO_OUT => GPIO_SIO_OUT
+< 		 );
+< 
+< 
+< b2v_inst2 : address_decoder
+---
+> mmu1 : address_decoder
+1139c886
+< 		 SDRAM_REPLY => SDRAM_REPLY,
+---
+> 		 SDRAM_REQUEST_COMPLETE => SDRAM_REQUEST_COMPLETE,
+1155c902
+< 		 ram_select => RAM_SELECT,
+---
+> 		 ram_select => RAM_SELECT(2 downto 0),
+1157c904
+< 		 rom_select => ROM_SELECT,
+---
+> 		 rom_select => ROM_SELECT, 
+1190,1191c937,940
+< 		 WRITE_DATA => WRITE_DATA);
+< 
+---
+> 		 WRITE_DATA => WRITE_DATA,
+> 		 d6_wr_enable => covox_write_enable,
+> 		 cart_select => "0000000",
+> 		 cart_activate => '0');
+1193,1226c942
+< b2v_inst20 : sdram_statemachine
+< GENERIC MAP(ADDRESS_WIDTH => 22,
+< 			AP_BIT => 10,
+< 			COLUMN_WIDTH => 8,
+< 			ROW_WIDTH => 12
+< 			)
+< PORT MAP(CLK_SYSTEM => CLK,
+< 		 CLK_SDRAM => CLK_SDRAM,
+< 		 RESET_N => RESET_N,
+< 		 READ_EN => SDRAM_READ_ENABLE,
+< 		 WRITE_EN => SDRAM_WRITE_ENABLE,
+< 		 REQUEST => SDRAM_REQUEST,
+< 		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+< 		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+< 		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+< 		 REFRESH => SDRAM_REFRESH,
+< 		 ADDRESS_IN => SDRAM_ADDR,
+< 		 DATA_IN => WRITE_DATA,
+< 		 SDRAM_DQ => DRAM_DQ,
+< 		 REPLY => SDRAM_REPLY,
+< 		 SDRAM_BA0 => DRAM_BA_0,
+< 		 SDRAM_BA1 => DRAM_BA_1,
+< 		 SDRAM_CKE => DRAM_CKE,
+< 		 SDRAM_CS_N => DRAM_CS_N,
+< 		 SDRAM_RAS_N => DRAM_RAS_N,
+< 		 SDRAM_CAS_N => DRAM_CAS_N,
+< 		 SDRAM_WE_N => DRAM_WE_N,
+< 		 SDRAM_ldqm => DRAM_LDQM,
+< 		 SDRAM_udqm => DRAM_UDQM,
+< 		 DATA_OUT => SDRAM_DO,
+< 		 SDRAM_ADDR => DRAM_ADDR);
+< 
+< 
+< b2v_inst21 : zpu_rom
+---
+> zpu_rom1 : zpu_rom
+1229a946,952
+> --
+> --b2v_inst23 : zpu_ram
+> --PORT MAP(wren => ZPU_STACK_WRITE(2),
+> --		 clock => CLK,
+> --		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+> --		 data => ZPU_DO(23 DOWNTO 16),
+> --		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+1231,1257c954,970
+< 
+< b2v_inst22 : scandoubler
+< PORT MAP(CLK => CLK,
+< 		 RESET_N => RESET_N,
+< 		 VGA => VGA,
+< 		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+< 		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+< 		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+< 		 vsync_in => SYNTHESIZED_WIRE_12,
+< 		 hsync_in => SYNTHESIZED_WIRE_13,
+< 		 colour_in => SYNTHESIZED_WIRE_14,
+< 		 VSYNC => VGA_VS,
+< 		 HSYNC => VGA_HS,
+< 		 B => VGA_B,
+< 		 G => VGA_G,
+< 		 R => VGA_R);
+< 
+< 
+< b2v_inst23 : zpu_ram
+< PORT MAP(wren => ZPU_STACK_WRITE(2),
+< 		 clock => CLK,
+< 		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+< 		 data => ZPU_DO(23 DOWNTO 16),
+< 		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+< 
+< 
+< b2v_inst24 : zpu_config_regs
+---
+> zpu_ram1 : generic_ram_infer
+> generic map
+> (
+> 	ADDRESS_WIDTH => 10,
+> 	SPACE => 1024,
+> 	DATA_WIDTH =>8
+> )
+> PORT MAP(clock => clk,
+> 		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+> 		 data => ZPU_DO(23 downto 16),
+> 		 we => ZPU_STACK_WRITE(2),
+> 		 q => ZPU_RAM_DATA(23 downto 16)
+> 		 );	
+> 
+> SYNC_KEYS <= (others=> '0');
+> SYNC_SWITCHES <= (others=> '1');
+> zpu_config1 : zpu_config_regs
+1261c974
+< 		 SDCARD_DAT => SD_DATA,
+---
+> 		 SDCARD_DAT => SD_DAT0,
+1268c981
+< 		 KEY => SYNC_KEYS,
+---
+> 		 KEY => VIRTUAL_KEYS, --SYNC_KEYS,
+1272c985
+< 		 SDCARD_DAT3 => SD_THREE,
+---
+> 		 SDCARD_DAT3 => SD_DAT3,
+1285,1288c998,1001
+< 		 LEDG => LEDG,
+< 		 LEDR => LEDR,
+< 		 RAM_SELECT => RAM_SELECT,
+< 		 ROM_SELECT => ROM_SELECT,
+---
+> 		 LEDG => LEDG_dummy,
+> 		 LEDR => LEDR_dummy,
+> 		 RAM_SELECT => RAM_SELECT_dummy,
+> 		 ROM_SELECT => ROM_SELECT_dummy(1 downto 0),
+1290,1326c1003,1008
+< 		 ZPU_HEX => ZPU_HEX);
+< 
+< 
+< b2v_inst25 : zpu_ram
+< PORT MAP(wren => ZPU_STACK_WRITE(3),
+< 		 clock => CLK,
+< 		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+< 		 data => ZPU_DO(31 DOWNTO 24),
+< 		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+< 
+< 
+< b2v_inst26 : zpu_ram
+< PORT MAP(wren => ZPU_STACK_WRITE(0),
+< 		 clock => CLK,
+< 		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+< 		 data => ZPU_DO(7 DOWNTO 0),
+< 		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+< 
+< 
+< b2v_inst27 : zpu_ram
+< PORT MAP(wren => ZPU_STACK_WRITE(1),
+< 		 clock => CLK,
+< 		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+< 		 data => ZPU_DO(15 DOWNTO 8),
+< 		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+< 
+< 
+< b2v_inst3 : i2c_loader
+< GENERIC MAP(device_address => 26,
+< 			log2_divider => 6,
+< 			num_retries => 0
+< 			)
+< PORT MAP(CLK => CLK,
+< 		 nRESET => RESET_N,
+< 		 I2C_SCL => I2C_SCLK,
+< 		 I2C_SDA => I2C_SDAT);
+< 
+---
+> 		 ZPU_HEX => ZPU_HEX,
+> 		 sector_request => dummy_sector_request,
+> 		 sector => dummy_sector,
+> 		 sector_ready => '0'
+> 		 );
+> ROM_SELECT_dummy(5 downto 2) <= "0000";
+1328,1347c1010,1016
+< b2v_inst4 : flashrom
+< PORT MAP(CLK => CLK,
+< 		 RESET_N => RESET_N,
+< 		 REQUEST => ROM_REQUEST,
+< 		 ADDRESS => ROM_ADDR,
+< 		 FLASH_D => FL_DQ,
+< 		 FLASH_OE_N => FL_OE_N,
+< 		 FLASH_WE_N => FL_WE_N,
+< 		 FLASH_RESET_N => FL_RST_N,
+< 		 COMPLETE => ROM_REQUEST_COMPLETE,
+< 		 DOUT => ROM_DO,
+< 		 FLASH_ADDRESS => FL_ADDR);
+< 
+< 
+< b2v_inst5 : pll
+< PORT MAP(inclk0 => CLOCK_50,
+< 		 c0 => CLK_SDRAM,
+< 		 c1 => CLK,
+< 		 c2 => DRAM_CLK,
+< 		 locked => PLL_LOCKED);
+---
+> --
+> --b2v_inst25 : zpu_ram
+> --PORT MAP(wren => ZPU_STACK_WRITE(3),
+> --		 clock => CLK,
+> --		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+> --		 data => ZPU_DO(31 DOWNTO 24),
+> --		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+1348a1018,1038
+> zpu_ram2 : generic_ram_infer
+> generic map
+> (
+> 	ADDRESS_WIDTH => 10,
+> 	SPACE => 1024,
+> 	DATA_WIDTH =>8
+> )
+> PORT MAP(clock => clk,
+> 		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+> 		 data => ZPU_DO(31 downto 24),
+> 		 we => ZPU_STACK_WRITE(3),
+> 		 q => ZPU_RAM_DATA(31 downto 24)
+> 		 );	
+> 
+> 
+> --b2v_inst26 : zpu_ram
+> --PORT MAP(wren => ZPU_STACK_WRITE(0),
+> --		 clock => CLK,
+> --		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+> --		 data => ZPU_DO(7 DOWNTO 0),
+> --		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+1350,1357c1040,1060
+< b2v_inst6 : i2sslave
+< PORT MAP(CLK => CLK,
+< 		 BCLK => AUD_BCLK,
+< 		 DACLRC => AUD_DACLRCK,
+< 		 LEFT_IN => AUDIO_LEFT,
+< 		 RIGHT_IN => AUDIO_RIGHT,
+< 		 MCLK_2 => AUD_XCK,
+< 		 DACDAT => AUD_DACDAT);
+---
+> zpu_ram3 : generic_ram_infer
+> generic map
+> (
+> 	ADDRESS_WIDTH => 10,
+> 	SPACE => 1024,
+> 	DATA_WIDTH =>8
+> )
+> PORT MAP(clock => clk,
+> 		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+> 		 data => ZPU_DO(7 downto 0),
+> 		 we => ZPU_STACK_WRITE(0),
+> 		 q => ZPU_RAM_DATA(7 downto 0)
+> 		 );	
+> 
+> 
+> --b2v_inst27 : zpu_ram
+> --PORT MAP(wren => ZPU_STACK_WRITE(1),
+> --		 clock => CLK,
+> --		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+> --		 data => ZPU_DO(15 DOWNTO 8),
+> --		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+1358a1062,1074
+> zpu_ram4 : generic_ram_infer
+> generic map
+> (
+> 	ADDRESS_WIDTH => 10,
+> 	SPACE => 1024,
+> 	DATA_WIDTH =>8
+> )
+> PORT MAP(clock => clk,
+> 		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
+> 		 data => ZPU_DO(15 downto 8),
+> 		 we => ZPU_STACK_WRITE(1),
+> 		 q => ZPU_RAM_DATA(15 downto 8)
+> 		 );	
+1360c1076
+< b2v_inst7 : pokey
+---
+> pokey1 : pokey
+1366,1367c1082,1083
+< 		 SIO_IN1 => UART_RXD,
+< 		 SIO_IN2 => GPIO_SIO_IN,
+---
+> 		 SIO_IN1 => SIO_RXD,
+> 		 SIO_IN2 => '1',
+1374c1090
+< 		 SIO_OUT1 => UART_TXD,
+---
+> 		 SIO_OUT1 => SIO_TXD,
+1378,1381c1094,1097
+< 		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+< 		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+< 		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+< 		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
+---
+> 		 CHANNEL_0_OUT => POKEY1_CHANNEL0,
+> 		 CHANNEL_1_OUT => POKEY1_CHANNEL1,
+> 		 CHANNEL_2_OUT => POKEY1_CHANNEL2,
+> 		 CHANNEL_3_OUT => POKEY1_CHANNEL3,
+1385c1101,1145
+< b2v_inst8 : gtia
+---
+> 	keyboard_scan_inv <= not(keyboard_scan);
+> 
+> a4051: complete_address_decoder
+> 	generic map (width => 3)
+> 	PORT map ( addr_in => keyboard_scan_inv(5 downto 3), addr_decoded => matrix_in ); 
+> 
+> b4051: complete_address_decoder
+> 	generic map (width => 3)
+> 	PORT map ( addr_in => keyboard_scan_inv(2 downto 0), addr_decoded => matrix_out_match ); 
+> 
+> 	process(matrix_out, matrix_out_match)
+> 	begin
+> 		keyboard_response(0) <= '1';
+> 
+> 		if (or_reduce(matrix_out(7 downto 0) and matrix_out_match(7 downto 0)) = '1') then
+> 			keyboard_response(0) <= '0';
+> 		end if;
+> 	end process;
+> 
+> 	process(static_keys, pause_key)
+> 	begin
+> 		keyboard_response(1) <= '1';
+> 
+> 		if (keyboard_scan(5 downto 4)="00" and pause_key = '1') then
+> 			keyboard_response(1) <= '0';
+> 		end if;
+> 		
+> 		if (keyboard_scan(5 downto 4)="10" and static_keys(0) = '1') then
+> 			keyboard_response(1) <= '0';
+> 		end if;
+> 
+> 		if (keyboard_scan(5 downto 4)="11" and static_keys(1) = '1') then
+> 			keyboard_response(1) <= '0';
+> 		end if;
+> 	end process;
+> 
+> 	CONSOL_START <= static_keys(6);
+> 	CONSOL_SELECT <= static_keys(5);
+> 	CONSOL_OPTION <= static_keys(4);
+> 	system_reset_request <= static_keys(3);
+> 
+> 	virtual_keys <= "000"&static_keys(2); -- todo need more static keys!! though on second thoughts using replay menu for options/loading...
+> 	virtual_triggers <= "00"&joy1_n(4)&joy2_n(4); -- todo joystick...
+> 		 	 
+> gtia1 : gtia
+1400,1403c1160,1167
+< 		 TRIG0 => TRIGGERS(0),
+< 		 TRIG1 => TRIGGERS(1),
+< 		 TRIG2 => TRIGGERS(2),
+< 		 TRIG3 => TRIGGERS(3),
+---
+> 		 TRIG0 => joy2_n(4), -- TODO - joystick trigger too
+> 		 TRIG1 => joy1_n(4),
+> 		 --TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+> 		 --TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+> 		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+> 		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+> 		 TRIG2 => VIRTUAL_TRIGGERS(2),
+> 		 TRIG3 => VIRTUAL_TRIGGERS(3),
+1408,1409c1172,1174
+< 		 VSYNC => SYNTHESIZED_WIRE_12,
+< 		 HSYNC => SYNTHESIZED_WIRE_13,
+---
+> 		 VSYNC => VGA_VS,
+> 		 HSYNC => VGA_HS,
+> 		 BLANK => GTIA_BLANK,
+1411c1176
+< 		 COLOUR_out => SYNTHESIZED_WIRE_14,
+---
+> 		 COLOUR_out => COLOUR,
+1413a1179,1199
+> 	-- colour palette
+> --	Color             Value         Color             Value
+> --Black           0,      0	Medium blue     8,    128
+> --Rust            1,     16       Dark blue       9,    144
+> --Red-orange      2,     32       Blue-grey      10,    160
+> --Dark orange     3,     48       Olive green    11,    176
+> --Red             4,     64       Medium green   12,    192
+> --Dk lavender     5,     80       Dark green     13,    208
+> --Cobalt blue     6,     96       Orange-green   14,    224
+> --Ultramarine     7,    112       Orange         15,    240
+> 
+> -- from altirra	
+> 	palette1 : entity work.gtia_palette(altirra)
+> 		port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R, G_next=>VGA_G, B_next=>VGA_B);
+> 	--VGA_B <= hcount_temp;
+> 	--VGA_G <= vcount_temp(7 downto 0);
+> 		
+> -- from lao
+> --	palette2 : entity work.gtia_palette(laoo)
+> --		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
+> 
+1415c1201
+< b2v_inst9 : irq_glue
+---
+> irq_glue1 : irq_glue
+1461c1247,1283
+< END bdf_type;
+\ No newline at end of file
+---
+> internalromram1 : internalromram
+>   PORT map(
+>     clock => clk,
+>     reset_n => reset_n,
+> 
+> 	ROM_ADDR =>rom_addr,
+> 	ROM_REQUEST_COMPLETE => rom_REQUEST_COMPLETE,
+> 	ROM_REQUEST => rom_REQUEST,
+> 	ROM_DATA => rom_DO,
+> 	
+> 	RAM_ADDR => ram_addr,
+> 	RAM_WR_ENABLE => ram_WRITE_ENABLE,
+> 	RAM_DATA_IN => wriTE_DATA(7 downto 0),
+> 	RAM_REQUEST_COMPLETE => ram_REQUEST_COMPLETE,
+> 	RAM_REQUEST => ram_REQUEST,
+> 	RAM_DATA => ram_do(7 downto 0)
+> 	);
+> 
+> SDRAM_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
+> SDRAM_WIDTH_16bit_ACCESS <= WIDTH_16bit_access;
+> SDRAM_WIDTH_32bit_ACCESS <= WIDTH_32bit_access;
+> SDRAM_DI <= WRITE_DATA;
+> 
+> covox1 : covox
+> 	PORT map
+> 	( 
+> 		clk => clk,
+> 		addr => pbi_addr(1 downto 0),
+> 		data_in => WRITE_DATA(7 DOWNTO 0),
+> 		wr_en => covox_write_enable,
+> 		covox_channel0 => covox_channel0,
+> 		covox_channel1 => covox_channel1,
+> 		covox_channel2 => covox_channel2,
+> 		covox_channel3 => covox_channel3
+> 	);
+> 
+> END bdf_type;
+Only in ../../../common/a8core/: basic.vhdl
+Only in .: CHANGELOG
+Only in .: COPYRIGHT_NOTICE
+Only in ../../../common/a8core/: covox.vhd
+diff -r ./cpu_6510.vhd ../../../common/a8core/cpu_6510.vhd
+101,139d100
+< 	MyBitfade: if emulate_bitfade generate
+< 		bitfade7 : entity work.chameleon_bitfade
+< 			generic map (
+< 				max_fade_timer => 100
+< 			)
+< 			port map (
+< 				clk => clk,
+< 				ena_1khz => ena_1khz,
+< 				
+< 				dir => ioDir(7),
+< 				d => ioData(7),
+< 				q => ioFade(7)
+< 			);
+< 		bitfade6 : entity work.chameleon_bitfade
+< 			generic map (
+< 				max_fade_timer => 100
+< 			)
+< 			port map (
+< 				clk => clk,
+< 				ena_1khz => ena_1khz,
+< 				
+< 				dir => ioDir(6),
+< 				d => ioData(6),
+< 				q => ioFade(6)
+< 			);
+< 		bitfade3 : entity work.chameleon_bitfade
+< 			generic map (
+< 				max_fade_timer => 100
+< 			)
+< 			port map (
+< 				clk => clk,
+< 				ena_1khz => ena_1khz,
+< 				
+< 				dir => ioDir(3),
+< 				d => ioData(3),
+< 				q => ioFade(3)
+< 			);
+< 	end generate;
+< 	
+diff -r ./cpu_65xx_a.vhd ../../../common/a8core/cpu_65xx_a.vhd
+1441c1441
+< calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+---
+> calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset, processInt)
+diff -r ./cpu.vhd ../../../common/a8core/cpu.vhd
+111c111
+< 			debugY => debugOpcode,
+---
+> 			debugY => debugY,
+Only in .: flashrom.vhdl
+Only in ../../../common/a8core/: generic_ram_infer.vhdl
+Only in .: gpio.vhd
+diff -r ./gtia_palette.vhdl ../../../common/a8core/gtia_palette.vhdl
+1051a1052,1053
+> 				when others =>
+> 					-- nop
+2087a2090,2091
+> 					when others =>
+> 						-- nop
+diff -r ./gtia_player.vhdl ../../../common/a8core/gtia_player.vhdl
+75a76,77
+> 						when others=>
+> 							--hang!
+83a86,87
+> 						when others=>
+> 							--hang!
+96a101,102
+> 						when others=>
+> 							--hang!
+97a104,105
+> 				when others=>
+> 					--hang!
+108c116
+< end vhdl;
+\ No newline at end of file
+---
+> end vhdl;
+diff -r ./gtia.vhdl ../../../common/a8core/gtia.vhdl
+55a56
+> 	BLANK : out std_logic;
+218a220,224
+> 	signal grafm_reg10_extended : std_logic_vector(7 downto 0);
+> 	signal grafm_reg32_extended : std_logic_vector(7 downto 0);
+> 	signal grafm_reg54_extended : std_logic_vector(7 downto 0);
+> 	signal grafm_reg76_extended : std_logic_vector(7 downto 0);
+> 
+797a804,805
+> 					when others =>
+> 						-- nop
+1009a1018,1021
+> 	grafm_reg10_extended <= grafm_reg(1 downto 0)&"000000";
+> 	grafm_reg32_extended <= grafm_reg(3 downto 2)&"000000";
+> 	grafm_reg54_extended <= grafm_reg(5 downto 4)&"000000";
+> 	grafm_reg76_extended <= grafm_reg(7 downto 6)&"000000";
+1011c1023
+< 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg(1 downto 0)&"000000", output=>active_m0_live);
+---
+> 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg10_extended, output=>active_m0_live);
+1013c1025
+< 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg(3 downto 2)&"000000", output=>active_m1_live);
+---
+> 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg32_extended, output=>active_m1_live);
+1015c1027
+< 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg(5 downto 4)&"000000", output=>active_m2_live);
+---
+> 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg54_extended, output=>active_m2_live);
+1017c1029
+< 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg(7 downto 6)&"000000", output=>active_m3_live);
+---
+> 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg76_extended, output=>active_m3_live);
+1537c1549
+< 			data_out <= "00000"&not(pal&pal&pal);
+---
+> 			data_out <= "0000"&not(pal&pal&pal)&'1';
+1550a1563
+> 	blank<=hblank_reg or vsync_reg;
+Only in .: hexdecoder.vhd
+Only in .: i2c_loader.vhd
+Only in .: i2s_intf.vhd
+Only in .: i2sslave.vhdl
+Only in ../../../common/a8core/: internalromram.vhd
+Only in .: ledsw.vhd
+Only in ../../../common/a8core/: os16.vhdl
+diff -r ./pia.vhdl ../../../common/a8core/pia.vhdl
+312a313,314
+> 				when others =>
+> 					-- nop
+365a368,369
+> 				when others =>
+> 					--nop
+Only in .: pll.cmp
+Only in .: pll.ppf
+Only in .: pll.qip
+Only in .: pll.vhd
+diff -r ./pokey_keyboard_scanner.vhdl ../../../common/a8core/pokey_keyboard_scanner.vhdl
+152a153,155
+> 
+> 			when others=> 
+> 				state_next <= state_wait_key; 
+179c182
+< end vhdl;
+\ No newline at end of file
+---
+> end vhdl;
+diff -r ./pokey_mixer.vhdl ../../../common/a8core/pokey_mixer.vhdl
+24a25,27
+> 
+> 	COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
+> 	COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+32a36
+> 	signal volume_next_real : std_logic_vector(15 downto 0);	
+41c45
+< 	signal gtia_en : std_logic_vector(5 downto 0);
+---
+> 	signal gtia_en : std_logic_vector(15 downto 0);
+47c51
+< 			volume_reg <= volume_next;
+---
+> 			volume_reg <= volume_next_real;
+76,78c80
+< 	gtia_en <= "0000"&gtia_sound&gtia_sound;  -- only room for 3 more! TODO, regenerate...
+< 	
+< 	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
+---
+> 	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_en)
+92,93d93
+< 					+ 
+< 					unsigned(gtia_en)
+97c97,100
+< 	process (volume_sum)
+---
+> 	gtia_en(15 downto 13) <= (others=>'0');
+> 	gtia_en(12) <= gtia_sound;
+> 	gtia_en(11 downto 0) <= (others=>'0');
+>  	process (volume_sum, volume_next, gtia_en, covOX_CHANNEL_0,covOX_CHANNEL_1)
+225a229,242
+> --		volume_next_real <= std_LOGIC_vector(
+> --			(unsigned('0'&volume_next(15 downto 1)) 
+> --			+ unsigned(gtia_en)) 
+> --			+ (unsigned("00"&covox_CHANNEL_0) 
+> --			+ unsigned("00"&covox_CHANNEL_1)));
+> 		
+> 		--volume_next_real <= '0'&volume_next(15 downto 1);
+> 		
+> 		volume_next_real <= std_LOGIC_vector(
+> 			(unsigned("00"&volume_next(15 downto 2)) 
+> 			+ unsigned(gtia_en)) 		
+> 			+ (unsigned("000"&covox_CHANNEL_0&"00000") 
+> 			+ unsigned("000"&covox_CHANNEL_1&"00000")));
+> 		
+228a246
+> 	-- TODO
+Only in .: pokey_ps2_decoder.vhdl
+diff -r ./pokey.vhdl ../../../common/a8core/pokey.vhdl
+332a333
+> 	signal serout_sync_reset : std_logic;
+938a940
+>         serout_sync_reset <= serial_reset or stimer_write_delayed;
+941c943
+< 		port map (clk=>clk, sync_reset=>serial_reset or stimer_write_delayed,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+---
+> 		port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+1133a1136,1137
+> 			when others =>
+> 				-- nop
+Only in .: ps2_keyboard.vhdl
+Only in .: scandouble_ram_infer.vhdl
+Only in .: scandoubler.vhdl
+Only in .: sdram_statemachine.vhdl
+diff -r ./shared_enable.vhdl ../../../common/a8core/shared_enable.vhdl
+52a53
+> 		SYNC_RESET : IN STD_LOGIC;
+80a82,83
+> 
+> 	constant cycle_length : integer := 16;	
+90,91c93
+< 		--generic map (COUNT=>16)
+< 		generic map (COUNT=>32)
+---
+> 		generic map (COUNT=>cycle_length)
+123,125c125,126
+< 		--generic map (COUNT=>15)
+< 		generic map (COUNT=>31)
+< 		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+---
+> 		generic map (COUNT=>cycle_length-1)
+> 		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+128,130c129,130
+< 		--generic map (COUNT=>15)
+< 		generic map (COUNT=>16)
+< 		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+---
+> 		generic map (COUNT=>cycle_length/2)
+> 		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+Only in .: spi_master.vhd
+Only in .: sram.vhdl
+Only in .: zpu
+Only in .: zpu_config_regs.vhdl
+Only in .: zpu_core.vhd
+Only in .: zpu_glue.vhdl
+Only in .: zpupkg.vhd
+Only in .: zpu_ram.cmp
+Only in .: zpu_ram.qip
+Only in .: zpu_ram.vhd
+Only in .: zpu_rom.cmp
+Only in .: zpu_rom.qip
+Only in .: zpu_rom.vhd
Index: unmerged/core_merge/mist_replay_changes
===================================================================
--- unmerged/core_merge/mist_replay_changes	(nonexistent)
+++ unmerged/core_merge/mist_replay_changes	(revision 1)
@@ -0,0 +1,2250 @@
+diff -ur mist/address_decoder.vhdl ../../common/a8core/address_decoder.vhdl
+--- mist/address_decoder.vhdl	2014-03-09 20:12:21.000000000 +0000
++++ ../../common/a8core/address_decoder.vhdl	2014-03-23 08:03:29.673482072 +0000
+@@ -315,6 +315,8 @@
+ 					cpu_fetch_real_next <= '1';
+ 				when "000" =>
+ 					-- no requests
++				when others =>
++					-- nop
+ 				end case;
+ 			when state_waiting_antic =>
+ 				if (request_complete = '1') then
+@@ -331,6 +333,8 @@
+ 					notify_cpu <= '1';
+ 					state_next <= state_idle;
+ 				end if;				
++			when others =>
++				-- NOP
+ 		end case;
+ 	end process;
+ 	
+@@ -723,6 +727,8 @@
+ 					sdram_chip_select <= start_request;
+ 					request_complete <= sdram_request_COMPLETE;	
+ 					SDRAM_ADDR <= addr_next(22 downto 0);				
++				when others =>
++					-- NOP
+ 			end case;
+ 		end if;
+ 		
+Only in mist/: address_decoder.vhdl.bak
+diff -ur mist/antic.vhdl ../../common/a8core/antic.vhdl
+--- mist/antic.vhdl	2014-01-18 11:23:43.000000000 +0000
++++ ../../common/a8core/antic.vhdl	2014-03-23 08:03:29.677482072 +0000
+@@ -47,7 +47,9 @@
+ 	refresh_out : out std_logic; -- used by sdram
+ 	
+ 	-- for debugging
+-	dma_clock_out : out std_logic
++	dma_clock_out : out std_logic;
++	hcount_out : out std_logic_vector(7 downto 0);
++	vcount_out : out std_logic_vector(8 downto 0)
+ );
+ END antic;
+ 
+@@ -475,10 +477,11 @@
+ 	signal colour_clock_selected : std_logic;
+ 	signal colour_clock_selected_highres : std_logic;
+ 	
+-	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+-	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
++	-- TODO - these should change with cycle_length...
++	signal colour_clock_count_next : std_logic_vector(3 downto 0);
++	signal colour_clock_count_reg : std_logic_vector(3 downto 0);
+ 	
+-	constant cycle_length : integer := 32;	
++	constant cycle_length : integer := 16;	
+ 	
+ 	signal memory_ready_both : std_logic;
+ 	
+@@ -655,34 +658,34 @@
+ 		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+ 		
+ 		if (ANTIC_ENABLE_179 = '1') then -- resync...
+-			colour_clock_count_next <= "00001";
++			colour_clock_count_next <= "0001";
+ 		end if;
+ 
+ 		colour_clock_8x <= '1';
+ 		
+-		case colour_clock_count_reg(4 downto 0) is
+-		when "00000" =>
++		case colour_clock_count_reg(3 downto 0) is
++		when "0000" =>
+ 			colour_clock_half_x <= '1';
+ 			colour_clock_1x <= '1';
+ 			colour_clock_2x <= '1';
+ 			colour_clock_4x <= '1';
+-		when "00100" =>
++		when "0010" =>
+ 			colour_clock_4x <= '1';
+-		when "01000" =>
++		when "0100" =>
+ 			colour_clock_2x <= '1';			
+ 			colour_clock_4x <= '1';			
+-		when "01100" =>
++		when "0110" =>
+ 			colour_clock_4x <= '1';
+-		when "10000" =>			
++		when "1000" =>			
+ 			colour_clock_1x <= '1';
+ 			colour_clock_2x <= '1';
+ 			colour_clock_4x <= '1';
+-		when "10100" =>
++		when "1010" =>
+ 			colour_clock_4x <= '1';
+-		when "11000" =>
++		when "1100" =>
+ 			colour_clock_2x <= '1';			
+ 			colour_clock_4x <= '1';			
+-		when "11100" =>
++		when "1110" =>
+ 			colour_clock_4x <= '1';			
+ 		when others =>
+ 			-- nop
+@@ -1155,6 +1158,8 @@
+ 				medium_dma_s <= '1';
+ 			when fast_dma =>
+ 				fast_dma_s <= '1';
++			when others =>
++				-- nothing
+ 		end case;
+ 	end process;
+ 	
+@@ -1399,6 +1404,8 @@
+ 				shift_rate_next <= fast_shift;
+ 				shift_twobit_next <= '1';
+ 				twopixel_next <= '1';
++			when others =>
++				-- nothing
+ 				
+ 		end case;
+ 	end process;
+@@ -1591,6 +1598,8 @@
+ 						an_current <= "101";			
+ 					when "11" =>
+ 						an_current <= "11"&delay_display_shift_reg(4);										
++					when others =>
++						-- nop
+ 				end case;				
+ 			end if;
+ 			
+@@ -1604,6 +1613,8 @@
+ 						an_current <= "101";			
+ 					when "11" =>
+ 						an_current <= "110";										
++					when others =>
++						-- nop
+ 				end case;
+ 			end if;
+ 		else
+@@ -1819,6 +1830,9 @@
+ 	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+ 	COLOUR_CLOCK_OUT <= colour_clock_selected;
+ 	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
++
++	vcount_out <= vcount_reg;
++	hcount_out <= hcount_reg;
+ 	
+ END vhdl;
+ 
+Only in mist/: antic.vhdl.bak
+Only in mist/: atari800core_assignment_defaults.qdf
+Only in mist/: atari800core.jdi
+Only in mist/: atari800core.qpf
+Only in mist/: atari800core.qsf
+Only in mist/: atari800core.qsf~
+Only in mist/: atari800core.qsf.bak
+Only in mist/: atari800core.qws
+Only in mist/: atari800core.sdc
+Only in mist/: atari800core.sdc.bak
+diff -ur mist/atari800core.vhd ../../common/a8core/atari800core.vhd
+--- mist/atari800core.vhd	2014-03-12 05:00:20.000000000 +0000
++++ ../../common/a8core/atari800core.vhd	2014-03-23 08:03:29.697482071 +0000
+@@ -1,4 +1,3 @@
+--- Copyright (C) 1991-2012 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+@@ -18,6 +17,7 @@
+ 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all; 
++use IEEE.STD_LOGIC_MISC.all;
+ use ieee.numeric_std.all;
+ 
+ LIBRARY work;
+@@ -25,91 +25,49 @@
+ ENTITY atari800core IS 
+ 	PORT
+ 	(
+-		CLOCK_27 :  IN  STD_LOGIC_VECTOR(1 downto 0);
+---		PS2K_CLK :  IN  STD_LOGIC;
+---		PS2K_DAT :  IN  STD_LOGIC;
+---		PS2M_CLK :  IN  STD_LOGIC;
+---		PS2M_DAT :  IN  STD_LOGIC;		
++		CLK :  IN  STD_LOGIC;
++		PLL_LOCKED: IN STD_LOGIC;
+ 
+ 		VGA_VS :  OUT  STD_LOGIC;
+ 		VGA_HS :  OUT  STD_LOGIC;
+-		VGA_B :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-		VGA_G :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-		VGA_R :  OUT  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		VGA_B :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
++		VGA_G :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
++		VGA_R :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		
+---		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+---		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++
++		matrix_out : in std_logic_vector(15 downto 0);
++		matrix_in : out std_logic_vector(7 downto 0);
++		static_keys : in std_logic_vector(6 downto 0);
++		pause_key : in std_logic;
+ 		
+-		AUDIO_L : OUT std_logic;
+-		AUDIO_R : OUT std_logic;
++		AUDIO_L : OUT std_logic_vector(15 downto 0);
++		AUDIO_R : OUT std_logic_vector(15 downto 0);
+ 
+-		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+-		SDRAM_nCS :  OUT  STD_LOGIC;
+-		SDRAM_nRAS :  OUT  STD_LOGIC;
+-		SDRAM_nCAS :  OUT  STD_LOGIC;
+-		SDRAM_nWE :  OUT  STD_LOGIC;
+-		SDRAM_DQMH :  OUT  STD_LOGIC;
+-		SDRAM_DQML :  OUT  STD_LOGIC;
+-		SDRAM_CLK :  OUT  STD_LOGIC;
+-		SDRAM_CKE :  OUT  STD_LOGIC;
+-		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+-		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+-
+---		SD_DAT0 :  IN  STD_LOGIC;
+---		SD_CLK :  OUT  STD_LOGIC;
+---		SD_CMD :  OUT  STD_LOGIC;
+---		SD_DAT3 :  OUT  STD_LOGIC
++		SDRAM_REQUEST : OUT std_logic;
++		SDRAM_REQUEST_COMPLETE : IN std_logic;
++		SDRAM_READ_ENABLE : out STD_LOGIC;
++		SDRAM_WRITE_ENABLE : out std_logic;
++		SDRAM_DI : out std_logic_vector(31 downto 0);
++		SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
++		SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
++		SDRAM_WIDTH_8bit_ACCESS : out std_logic;
++		SDRAM_WIDTH_16bit_ACCESS : out std_logic;
++		SDRAM_WIDTH_32bit_ACCESS : out std_logic;
++
++		SIO_RXD : in std_logic;
++		SIO_TXD : out std_logic;
++		SIO_COMMAND_TX : out std_logic;
+ 
+-		LED : OUT std_logic;
+-		
+-		UART_TX :  OUT  STD_LOGIC;
+-		UART_RX :  IN  STD_LOGIC;
+-		
+-		SPI_DO :  INOUT  STD_LOGIC;
+-		SPI_DI :  IN  STD_LOGIC;
+-		SPI_SCK :  IN  STD_LOGIC;
+-		SPI_SS2 :  IN  STD_LOGIC;		
+-		SPI_SS3 :  IN  STD_LOGIC;		
+-		SPI_SS4 :  IN  STD_LOGIC;
+-		CONF_DATA0 :  IN  STD_LOGIC -- AKA SPI_SS5
++   		ram_select : in std_logic_vector(2 downto 0);
++    		rom_select : in std_logic_vector(5 downto 0);
++
++		halt : in std_logic
+ 	);
+ END atari800core;
+ 
+ ARCHITECTURE bdf_type OF atari800core IS 
+---
+---component generic_ram_infer IS
+---	generic
+---	(
+---		ADDRESS_WIDTH : natural := 9;
+---		SPACE : natural := 512;
+---		DATA_WIDTH : natural := 8
+---	);
+---   PORT
+---   (
+---      clock: IN   std_logic;
+---      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
+---      address:  IN   std_logic_vector(address_width-1 downto 0);
+---      we:    IN   std_logic;
+---      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
+---   );
+---END component;
+-
+-component mist_sector_buffer IS
+-	PORT
+-	(
+-		address_a		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+-		address_b		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+-		clock_a		: IN STD_LOGIC  := '1';
+-		clock_b		: IN STD_LOGIC ;
+-		data_a		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+-		data_b		: IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+-		wren_a		: IN STD_LOGIC  := '0';
+-		wren_b		: IN STD_LOGIC  := '0';
+-		q_a		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+-		q_b		: OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
+-	);
+-END component;
+-
+ component synchronizer IS
+ PORT 
+ ( 
+@@ -119,46 +77,6 @@
+ );
+ END component;
+ 
+-component data_io IS 
+-	PORT
+-	(
+-		CLK : in std_logic;
+-		RESET_n : in std_logic;
+-		
+-		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+-	   SPI_CLK : in std_logic;
+-	   SPI_SS_IO : in std_logic;
+-	   SPI_MISO: out std_logic;
+-	   SPI_MOSI : in std_logic;
+-		
+-		-- Sector access request
+-		request : in std_logic;
+-		sector : in std_logic_vector(23 downto 0);
+-		ready : out std_logic;
+-		
+-		-- DMA to RAM
+-		ADDR: out std_logic_vector(8 downto 0);
+-		DATA_OUT : out std_logic_vector(7 downto 0);
+-		DATA_IN : in std_logic_vector(7 downto 0);
+-		WR_EN : out std_logic
+-	 );
+-end component;
+-
+-component user_io
+-	PORT(
+-	   SPI_CLK : in std_logic;
+-	   SPI_SS_IO : in std_logic;
+-	   SPI_MISO : out std_logic;
+-	   SPI_MOSI : in std_logic;
+-	   CORE_TYPE : in std_logic_vector(7 downto 0);
+-		JOY0 : out std_logic_vector(5 downto 0);
+-		JOY1 : out std_logic_vector(5 downto 0);
+-		KEYBOARD : out std_logic_vector(127 downto 0);
+-		BUTTONS : out std_logic_vector(1 downto 0);
+-		SWITCHES : out std_logic_vector(1 downto 0)
+-	  );
+-end component;
+-
+ COMPONENT complete_address_decoder IS
+ generic (width : natural := 1);
+ PORT 
+@@ -185,16 +103,6 @@
+ 	);
+ END COMPONENT;
+ 
+-component hq_dac
+-port (
+-  reset :in std_logic;
+-  clk :in std_logic;
+-  clk_ena : in std_logic;
+-  pcm_in : in std_logic_vector(19 downto 0);
+-  dac_out : out std_logic
+-);
+-end component;
+-
+ component internalromram IS
+   PORT(
+     clock   : IN     STD_LOGIC;                             --system clock
+@@ -235,21 +143,14 @@
+ 		 dma_fetch_out : OUT STD_LOGIC;
+ 		 refresh_out : OUT STD_LOGIC;
+ 		 dma_clock_out : OUT STD_LOGIC;
++		 hcount_out : out std_logic_vector(7 downto 0);
++		 vcount_out : out std_logic_vector(8 downto 0);
+ 		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT ledsw
+-	PORT(CLK : IN STD_LOGIC;
+-		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+ COMPONENT pokey_mixer
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 GTIA_SOUND : IN STD_LOGIC;
+@@ -264,18 +165,6 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT ps2_keyboard
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 PS2_CLK : IN STD_LOGIC;
+-		 PS2_DAT : IN STD_LOGIC;
+-		 KEY_EVENT : OUT STD_LOGIC;
+-		 KEY_EXTENDED : OUT STD_LOGIC;
+-		 KEY_UP : OUT STD_LOGIC;
+-		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+ COMPONENT zpu_glue
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 RESET : IN STD_LOGIC;
+@@ -380,29 +269,6 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT pokey_ps2_decoder
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 KEY_EVENT : IN STD_LOGIC;
+-		 KEY_EXTENDED : IN STD_LOGIC;
+-		 KEY_UP : IN STD_LOGIC;
+-		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 KEY_HELD : OUT STD_LOGIC;
+-		 SHIFT_PRESSED : OUT STD_LOGIC;
+-		 BREAK_PRESSED : OUT STD_LOGIC;
+-		 KEY_INTERRUPT : OUT STD_LOGIC;
+-		 CONSOL_START : OUT STD_LOGIC;
+-		 CONSOL_SELECT : OUT STD_LOGIC;
+-		 CONSOL_OPTION : OUT STD_LOGIC;
+-		 SYSTEM_RESET : OUT STD_LOGIC;
+-		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+-	);
+-END COMPONENT;
+-
+-
+ COMPONENT address_decoder
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 CPU_FETCH : IN STD_LOGIC;
+@@ -479,84 +345,6 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT sdram_statemachine
+-GENERIC (ADDRESS_WIDTH : INTEGER;
+-			AP_BIT : INTEGER;
+-			COLUMN_WIDTH : INTEGER;
+-			ROW_WIDTH : INTEGER
+-			);
+-	PORT(CLK_SYSTEM : IN STD_LOGIC;
+-		 CLK_SDRAM : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 READ_EN : IN STD_LOGIC;
+-		 WRITE_EN : IN STD_LOGIC;
+-		 REQUEST : IN STD_LOGIC;
+-		 BYTE_ACCESS : IN STD_LOGIC;
+-		 WORD_ACCESS : IN STD_LOGIC;
+-		 LONGWORD_ACCESS : IN STD_LOGIC;
+-		 REFRESH : IN STD_LOGIC;
+-		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+-		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+-		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 COMPLETE : OUT STD_LOGIC;
+-		 SDRAM_BA0 : OUT STD_LOGIC;
+-		 SDRAM_BA1 : OUT STD_LOGIC;
+-		 SDRAM_CKE : OUT STD_LOGIC;
+-		 SDRAM_CS_N : OUT STD_LOGIC;
+-		 SDRAM_RAS_N : OUT STD_LOGIC;
+-		 SDRAM_CAS_N : OUT STD_LOGIC;
+-		 SDRAM_WE_N : OUT STD_LOGIC;
+-		 SDRAM_ldqm : OUT STD_LOGIC;
+-		 SDRAM_udqm : OUT STD_LOGIC;
+-		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+-		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+-component sdram_statemachine_mcc IS
+-generic
+-(
+-	ADDRESS_WIDTH : natural := 22;
+-	ROW_WIDTH : natural := 12;
+-	AP_BIT : natural := 10;
+-	COLUMN_WIDTH : natural := 8
+-);
+-PORT 
+-( 
+-	CLK_SYSTEM : IN STD_LOGIC;
+-	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+-	RESET_N : in STD_LOGIC;
+-	
+-	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+-	DATA_IN : in std_logic_vector(31 downto 0);
+-	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+-	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+-	WRITE_EN : in std_logic;
+-	REQUEST : in std_logic; -- Toggle this to issue a new request
+-	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+-	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+-	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+-	REFRESH : in std_logic;
+-
+-	REPLY : out std_logic; -- This matches the request once complete
+-	DATA_OUT : out std_logic_vector(31 downto 0);
+-
+-	-- sdram itself
+-	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+-	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+-	SDRAM_BA0 : out std_logic;
+-	SDRAM_BA1 : out std_logic;
+-	
+-	SDRAM_CS_N : out std_logic;
+-	SDRAM_RAS_N : out std_logic;
+-	SDRAM_CAS_N : out std_logic;
+-	SDRAM_WE_N : out std_logic;
+-	
+-	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+-	SDRAM_udqm : out std_logic
+-);
+-END component;
+-
+ COMPONENT zpu_rom
+ 	PORT(clock : IN STD_LOGIC;
+ 		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+@@ -564,32 +352,31 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT scandoubler
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 VGA : IN STD_LOGIC;
+-		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+-		 colour_enable : IN STD_LOGIC;
+-		 doubled_enable : IN STD_LOGIC;
+-		 vsync_in : IN STD_LOGIC;
+-		 hsync_in : IN STD_LOGIC;
+-		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VSYNC : OUT STD_LOGIC;
+-		 HSYNC : OUT STD_LOGIC;
+-		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+-	);
+-END COMPONENT;
++--COMPONENT zpu_ram
++--	PORT(wren : IN STD_LOGIC;
++--		 clock : IN STD_LOGIC;
++--		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
++--		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
++--		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
++--	);
++--END COMPONENT;
+ 
+-COMPONENT zpu_ram
+-	PORT(wren : IN STD_LOGIC;
+-		 clock : IN STD_LOGIC;
+-		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+-	);
+-END COMPONENT;
++component generic_ram_infer IS
++        generic
++        (
++                ADDRESS_WIDTH : natural := 9;
++                SPACE : natural := 512;
++                DATA_WIDTH : natural := 8
++        );
++   PORT
++   (
++      clock: IN   std_logic;
++      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
++      address:  IN   std_logic_vector(address_width-1 downto 0);
++      we:    IN   std_logic;
++      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
++   );
++END component;
+ 
+ COMPONENT zpu_config_regs
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -621,8 +408,8 @@
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 RAM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 ROM_SELECT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
++		 RAM_SELECT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
++		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ 		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+ 		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ 		 sector : out std_logic_vector(31 downto 0);
+@@ -631,14 +418,16 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT pll
+-	PORT(inclk0 : IN STD_LOGIC;
+-		 c0 : OUT STD_LOGIC;
+-		 c1 : OUT STD_LOGIC;
+-		 c2 : OUT STD_LOGIC;
+-		 locked : OUT STD_LOGIC
+-	);
+-END COMPONENT;
++COMPONENT gtia_palette IS
++PORT 
++( 
++	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
++	
++	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
++	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
++	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
++);
++END component;
+ 
+ COMPONENT gtia
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -665,6 +454,7 @@
+ 		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 VSYNC : OUT STD_LOGIC;
+ 		 HSYNC : OUT STD_LOGIC;
++		 BLANK : OUT STD_LOGIC;
+ 		 sound : OUT STD_LOGIC;
+ 		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+@@ -711,6 +501,8 @@
+ );
+ END component;
+ 
++
++
+ SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL	ANTIC_COLOUR_CLOCK_OUT :  STD_LOGIC;
+@@ -723,8 +515,6 @@
+ SIGNAL	ANTIC_RDY :  STD_LOGIC;
+ SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+ SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+-SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+-SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+ 
+ SIGNAL	CART_RD4 :  STD_LOGIC;
+@@ -739,8 +529,6 @@
+ SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+ SIGNAL	CB2_OUT :  STD_LOGIC;
+ SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+-SIGNAL	CLK :  STD_LOGIC;
+-SIGNAL	CLK_SDRAM :  STD_LOGIC;
+ SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+ SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+ SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+@@ -771,7 +559,7 @@
+ SIGNAL	GTIA_SOUND :  STD_LOGIC;
+ SIGNAL	GTIA_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	IRQ_n :  STD_LOGIC;
+-SIGNAL	KBCODE_DUMMY :  STD_LOGIC_VECTOR(7 DOWNTO 0);
++SIGNAL	KBCODE :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	KEY_HELD :  STD_LOGIC;
+ SIGNAL	KEY_INTERRUPT :  STD_LOGIC;
+ SIGNAL	KEYBOARD_RESPONSE :  STD_LOGIC_VECTOR(1 DOWNTO 0);
+@@ -784,6 +572,7 @@
+ SIGNAL	NMI_n :  STD_LOGIC;
+ SIGNAL	PAL :  STD_LOGIC;
+ SIGNAL	PAUSE_6502 :  STD_LOGIC;
++SIGNAL	HALT_OR_PAUSE_6502 :  STD_LOGIC;
+ SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+@@ -791,7 +580,6 @@
+ SIGNAL	PIA_IRQB :  STD_LOGIC;
+ SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+-SIGNAL	PLL_LOCKED :  STD_LOGIC;
+ SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+@@ -811,24 +599,18 @@
+ SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	RAM_REQUEST :  STD_LOGIC;
+ SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
++SIGNAL	RAM_SELECT_dummy :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	RESET_N :  STD_LOGIC;
+ SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+ SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	ROM_REQUEST :  STD_LOGIC;
+ SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(3 DOWNTO 0);
++SIGNAL	ROM_SELECT_dummy :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+ SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+ SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+-SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+-SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+-SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+ --SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+-SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+-SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+ SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+ SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+@@ -864,35 +646,11 @@
+ SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 
+ SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+ SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ signal UART_TXD_dummy : std_logic;
+ 
+--- STUB OUT FOR NOW
+-SIGNAL		PS2K_CLK :  STD_LOGIC;
+-SIGNAL		PS2K_DAT :  STD_LOGIC;
+-signal		JOY1_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-signal		JOY2_n :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-signal		JOY1 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-signal		JOY2 :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+-
+-
+ SIGNAL		SD_DAT0 :  STD_LOGIC;
+ SIGNAL		SD_CLK :  STD_LOGIC;
+ SIGNAL		SD_CMD :  STD_LOGIC;
+@@ -901,36 +659,33 @@
+ signal mist_buttons : std_logic_vector(1 downto 0);
+ signal mist_switches : std_logic_vector(1 downto 0);
+ 
+-signal keyboard : std_logic_vector(127 downto 0);
+-signal atari_keyboard : std_logic_vector(63 downto 0);
+-
+ SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
+ SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
+ SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
+ 
+-SIGNAL	CONSOL_OPTION_DUMMY :  STD_LOGIC;
+-SIGNAL	CONSOL_SELECT_DUMMY :  STD_LOGIC;
+-SIGNAL	CONSOL_START_DUMMY :  STD_LOGIC;
+-
+-signal capslock_pressed : std_logic;
+-signal capsheld_next : std_logic;
+-signal capsheld_reg : std_logic;
+-
+-signal mist_sector_ready : std_logic;
+-signal mist_sector_ready_sync : std_logic;
+-signal mist_sector_request : std_logic;
+-signal mist_sector_request_sync : std_logic;
+-signal mist_sector : std_logic_vector(31 downto 0);
+-signal mist_sector_sync : std_logic_vector(31 downto 0);
++signal dummy_sector_request : std_logic;
++signal dummy_sector : std_logic_vector(31 downto 0);
+ 
+-		
+-signal mist_addr : std_logic_vector(8 downto 0);
+-signal mist_do : std_logic_vector(7 downto 0);
+-signal mist_di : std_logic_vector(7 downto 0);
+-signal mist_wren : std_logic;
++signal COLOUR : std_logic_vector(7 downto 0);
++
++signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
++signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
++signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
++signal POKEY1_CHANNEL3 : std_logic_vector(3 downto 0);
++
++signal POKEY2_CHANNEL0 : std_logic_vector(3 downto 0);
++signal POKEY2_CHANNEL1 : std_logic_vector(3 downto 0);
++signal POKEY2_CHANNEL2 : std_logic_vector(3 downto 0);
++signal POKEY2_CHANNEL3 : std_logic_vector(3 downto 0);
++
++signal hcount_temp : std_logic_vector(7 downto 0);
++signal vcount_temp : std_logic_vector(8 downto 0);
++signal VGA_G_dummy : std_logic_vector(7 downto 0);
++signal VGA_B_dummy : std_logic_vector(7 downto 0);
+ 
+-signal spi_miso_data : std_logic;
+-signal spi_miso_io : std_logic;
++signal matrix_out_match : std_logic_vector(7 downto 0);
++
++signal keyboard_scan_inv : std_logic_vector(5 downto 0);
+ 
+ signal covox_write_enable : std_logic;
+ signal covox_channel0 : std_logic_vector(7 downto 0);
+@@ -938,291 +693,11 @@
+ signal covox_channel2 : std_logic_vector(7 downto 0);
+ signal covox_channel3 : std_logic_vector(7 downto 0);
+ 
+-BEGIN 
+-
+-	
+--- mist spi io
+-mist_spi_interface : data_io 
+-	PORT map
+-	(
+-		CLK =>spi_sck,
+-		RESET_n =>reset_n,
+-		
+-		-- SPI connection - up to upstream to make miso 'Z' on ss_io going high
+-		SPI_CLK =>spi_sck,
+-		SPI_SS_IO => spi_ss2,
+-		SPI_MISO => spi_miso_data,
+-		SPI_MOSI => spi_di,
+-		
+-		-- Sector access request
+-		request => mist_sector_request_sync,
+-		sector => mist_sector_sync(23 downto 0),
+-		ready => mist_sector_ready,
+-		
+-		-- DMA to RAM
+-		ADDR => mist_addr,
+-		DATA_OUT => mist_do,
+-		DATA_IN => mist_di,
+-		WR_EN => mist_wren
+-	 );
+- 
+-	select_sync : synchronizer
+-	PORT MAP ( CLK => clk, raw => mist_sector_ready, sync=>mist_sector_ready_sync);
+-
+-	select_sync2 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector_request, sync=>mist_sector_request_sync);
+-
+-	sector_sync0 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(0), sync=>mist_sector_sync(0));
+-
+-	sector_sync1 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(1), sync=>mist_sector_sync(1));
+-
+-	sector_sync2 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(2), sync=>mist_sector_sync(2));
+-
+-	sector_sync3 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(3), sync=>mist_sector_sync(3));
+-
+-	sector_sync4 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(4), sync=>mist_sector_sync(4));
+-
+-	sector_sync5 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(5), sync=>mist_sector_sync(5));
+-
+-	sector_sync6 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(6), sync=>mist_sector_sync(6));
+-
+-	sector_sync7 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(7), sync=>mist_sector_sync(7));
+-
+-	sector_sync8 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(8), sync=>mist_sector_sync(8));
+-
+-	sector_sync9 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(9), sync=>mist_sector_sync(9));
+-
+-	sector_sync10 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(10), sync=>mist_sector_sync(10));
+-
+-	sector_sync11 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(11), sync=>mist_sector_sync(11));
+-
+-	sector_sync12 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(12), sync=>mist_sector_sync(12));
+-
+-	sector_sync13 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(13), sync=>mist_sector_sync(13));
+-
+-	sector_sync14 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(14), sync=>mist_sector_sync(14));
++signal gtia_blank : std_logic;
+ 
+-	sector_sync15 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(15), sync=>mist_sector_sync(15));
+-
+-	sector_sync16 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(16), sync=>mist_sector_sync(16));
+-
+-	sector_sync17 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(17), sync=>mist_sector_sync(17));
+-
+-	sector_sync18 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(18), sync=>mist_sector_sync(18));
+-
+-	sector_sync19 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(19), sync=>mist_sector_sync(19));
+-
+-	sector_sync20 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(20), sync=>mist_sector_sync(20));
+-
+-	sector_sync21 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(21), sync=>mist_sector_sync(21));
+-
+-	sector_sync22 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(22), sync=>mist_sector_sync(22));
+-
+-	sector_sync23 : synchronizer
+-	PORT MAP ( CLK => spi_sck, raw => mist_sector(23), sync=>mist_sector_sync(23));
+-	
+-	
+-	spi_do <= spi_miso_io when CONF_DATA0 ='0' else spi_miso_data when spi_SS2='0' else 'Z';
+-
+-	-- TODO, dual port, dual clock! 
+---	mist_sector_buffer : generic_ram_infer
+---	generic map
+---	(
+---		ADDRESS_WIDTH => 9,
+---		SPACE => 512,
+---		DATA_WIDTH => 8
+---	)
+---   PORT map
+---   (
+---      clock => spi_sck,
+---      data => mist_do,
+---      address => mist_addr,
+---      we => mist_wren,
+---      q => mist_di
+---   );
+-
+-mist_sector_buffer1 : mist_sector_buffer
+-	PORT map
+-	(
+-		address_a		=> mist_addr,
+-		address_b		=> ZPU_ADDR_ROM_RAM(8 DOWNTO 2),
+-		clock_a		=> spi_sck,
+-		clock_b		=> clk,
+-		data_a		=> mist_do,
+-		data_b		=> zpu_do,
+-		wren_a		=> mist_wren,
+-		wren_b		=> '0',
+-		q_a		=> mist_di,
+-		q_b		=> zpu_sector_data
+-	);
+-	
+-my_user_io : user_io
+-	PORT map(
+-	   SPI_CLK => SPI_SCK,
+-	   SPI_SS_IO => CONF_DATA0,
+-	   SPI_MISO => SPI_miso_io,
+-	   SPI_MOSI => SPI_DI,
+-	   CORE_TYPE => x"A4",
+-		JOY0 => joy1,
+-		JOY1 => joy2,
+-		KEYBOARD => keyboard,
+-		BUTTONS => mist_buttons,
+-		SWITCHES => mist_switches
+-	  );
+-	  
+-	 joy1_n <= not(joy1);
+-	 joy2_n <= not(joy2);
+-	 
+-	process(clk,reset_n)
+-	begin
+-		if (reset_n='0') then
+-			capsheld_reg <= '0';
+-		elsif (clk'event and clk='1') then
+-			capsheld_reg <= capsheld_next;
+-		end if;
+-	end process;
+-
+-	process(keyboard,capsheld_reg)
+-	begin
+-		capsheld_next <= capsheld_reg;
+-		capslock_pressed <= '0';
+-		
+-		if ((keyboard(58) xor capsheld_reg)='1') then
+-			capsheld_next <= keyboard(58);
+-			
+-			-- assert something for 10 frames
+-			capslock_pressed <= '1';
+-		end if;
+-	end process;
+-	
+-atari_keyboard(63) <= keyboard(30);
+-atari_keyboard(62) <= keyboard(31);
+-atari_keyboard(61) <= keyboard(34);
+-atari_keyboard(60) <= '0';
+-atari_keyboard(58) <= keyboard(32);
+-atari_keyboard(57) <= keyboard(35);
+-atari_keyboard(56) <= keyboard(33);
+-atari_keyboard(55) <= keyboard(13);
+-atari_keyboard(54) <= keyboard(12);
+-atari_keyboard(53) <= keyboard(9);
+-atari_keyboard(52) <= keyboard(14);
+-atari_keyboard(51) <= keyboard(8);
+-atari_keyboard(50) <= keyboard(11);
+-atari_keyboard(48) <= keyboard(10);
+-atari_keyboard(47) <= keyboard(16);
+-atari_keyboard(46) <= keyboard(17);
+-atari_keyboard(45) <= keyboard(20);
+-atari_keyboard(44) <= keyboard(15);
+-atari_keyboard(43) <= keyboard(21);
+-atari_keyboard(42) <= keyboard(18);
+-atari_keyboard(40) <= keyboard(19);
+-atari_keyboard(39) <= keyboard(56);
+-atari_keyboard(38) <= keyboard(53);
+-atari_keyboard(37) <= keyboard(50);
+-atari_keyboard(35) <= keyboard(49);
+-atari_keyboard(34) <= keyboard(52);
+-atari_keyboard(33) <= keyboard(57);
+-atari_keyboard(32) <= keyboard(51);
+-atari_keyboard(31) <= keyboard(2);
+-atari_keyboard(30) <= keyboard(3);
+-atari_keyboard(29) <= keyboard(6);
+-atari_keyboard(28) <= keyboard(1);
+-atari_keyboard(27) <= keyboard(7);
+-atari_keyboard(26) <= keyboard(4);
+-atari_keyboard(24) <= keyboard(5);
+-atari_keyboard(23) <= keyboard(44);
+-atari_keyboard(22) <= keyboard(45);
+-atari_keyboard(21) <= keyboard(48);
+-atari_keyboard(18) <= keyboard(46);
+-atari_keyboard(17) <= keyboard(59);
+-atari_keyboard(16) <= keyboard(47);
+-atari_keyboard(15) <= keyboard(27);
+-atari_keyboard(14) <= keyboard(26);
+-atari_keyboard(13) <= keyboard(23);
+-atari_keyboard(12) <= keyboard(28);
+-atari_keyboard(11) <= keyboard(22);
+-atari_keyboard(10) <= keyboard(25);
+-atari_keyboard(8) <= keyboard(24);
+-atari_keyboard(7) <= keyboard(41);
+-atari_keyboard(6) <= keyboard(40);
+-atari_keyboard(5) <= keyboard(37);
+-atari_keyboard(2) <= keyboard(39);
+-atari_keyboard(1) <= keyboard(36);
+-atari_keyboard(0) <= keyboard(38);
+-
+-	  
+-shift_pressed <= keyboard(54) or keyboard(42);
+-control_pressed <= keyboard(29);
+-break_pressed <= keyboard(96); -- TODO - not on st keyboard
+-
+-consol_start <= keyboard(60); --F2
+-consol_select <= keyboard(61); --F3
+-consol_option <= keyboard(62); -- F4
+-		
+---f5 <= keyboard(63);
+---f6 <= keyboard(64);
+---f7 <= keyboard(65);
+---f8 <= keyboard(66);
+---f9 <= keyboard(67);
+---f10 <= keyboard(68);
+-
+-virtual_keys <= keyboard(65)&keyboard(66)&keyboard(67)&keyboard(68);
+-SYSTEM_RESET_REQUEST <= keyboard(63);
+-
+-process(keyboard_scan, atari_keyboard, control_pressed, shift_pressed, break_pressed)
+-	begin	
+-		keyboard_response <= (others=>'1');		
+-		
+-		if (atari_keyboard(to_integer(unsigned(not(keyboard_scan)))) = '1') then
+-			keyboard_response(0) <= '0';
+-		end if;
+-		
+---		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+---			keyboard_response(0) <= '0';
+---		end if;
+-		
+-		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+-			keyboard_response(1) <= '0';
+-		end if;
+-		
+-		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+-			keyboard_response(1) <= '0';
+-		end if;
++BEGIN 
+ 
+-		if (keyboard_scan(5 downto 4)="11" and control_pressed = '1') then
+-			keyboard_response(1) <= '0';
+-		end if;
+-end process;		 
+-		  
+-	-- decode address
+---decode_addr1 : complete_address_decoder
+---	generic map(width=>6)
+---	port map (addr_in=>keyboard_scan, addr_decoded=>keyboard_scan_decoded);
+-	  
+-b2v_a_6502 : cpu
++cpu6502 : cpu
+ PORT MAP(CLK => CLK,
+ 		 RESET => CPU_6502_RESET,
+ 		 ENABLE => RESET_N,
+@@ -1238,7 +713,7 @@
+ 		 DO => CPU_DO);
+ 
+ LIGHTPEN <= '1';
+-b2v_inst1 : antic
++antic1 : antic
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => ANTIC_WRITE_ENABLE,
+ 		 RESET_N => RESET_N,
+@@ -1256,56 +731,26 @@
+ 		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+ 		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+ 		 dma_fetch_out => ANTIC_FETCH,
++		 hcount_out => hcount_temp,
++		 vcount_out => vcount_temp,
+ 		 refresh_out => ANTIC_REFRESH,
+ 		 AN => ANTIC_AN,
+ 		 DATA_OUT => ANTIC_DO,
+ 		 dma_address_out => ANTIC_ADDR);
+ 
+-b2v_inst11 : pokey_mixer
++pokey_mixer_l : pokey_mixer
+ PORT MAP(CLK => CLK,
+ 		 GTIA_SOUND => GTIA_SOUND,
+-		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+-		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+-		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+-		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
++		 CHANNEL_0 => POKEY1_CHANNEL0,
++		 CHANNEL_1 => POKEY1_CHANNEL1,
++		 CHANNEL_2 => POKEY1_CHANNEL2,
++		 CHANNEL_3 => POKEY1_CHANNEL3,
++		 CHANNEL_ENABLE => "1111",
+ 		 COVOX_CHANNEL_0 => covox_channel0,
+ 		 COVOX_CHANNEL_1 => covox_channel1,
+-		 CHANNEL_ENABLE => "1111",
+-		 VOLUME_OUT => AUDIO_LEFT);
++		 VOLUME_OUT => AUDIO_L);
+ 		 
+-dac_left : hq_dac
+-port map
+-(
+-  reset => not(reset_n),
+-  clk => clk,
+-  clk_ena => '1',
+-  pcm_in => audio_left&"0000",
+-  dac_out => audio_l
+-);
+-
+-dac_right : hq_dac
+-port map
+-(
+-  reset => not(reset_n),
+-  clk => clk,
+-  clk_ena => '1',
+-  pcm_in => audio_right&"0000",
+-  dac_out => audio_r
+-);
+-
+-
+-b2v_inst12 : ps2_keyboard
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 PS2_CLK => PS2K_CLK,
+-		 PS2_DAT => PS2K_DAT,
+-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+-		 KEY_UP => SYNTHESIZED_WIRE_10,
+-		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+-
+-
+-b2v_inst13 : zpu_glue
++zpu_glue1 : zpu_glue
+ PORT MAP(CLK => CLK,
+ 		 RESET => ZPU_RESET,
+ 		 PAUSE => ZPU_PAUSE,
+@@ -1327,20 +772,20 @@
+ 		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+ 
+ 
+-b2v_inst14 : pokey_mixer
++pokey_mixer_r : pokey_mixer
+ PORT MAP(CLK => CLK,
+ 		 GTIA_SOUND => GTIA_SOUND,
+-		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+-		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+-		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+-		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
++		 CHANNEL_0 => POKEY2_CHANNEL0,
++		 CHANNEL_1 => POKEY2_CHANNEL1,
++		 CHANNEL_2 => POKEY2_CHANNEL2,
++		 CHANNEL_3 => POKEY2_CHANNEL3,
+ 		 COVOX_CHANNEL_0 => covox_channel2,
+-		 COVOX_CHANNEL_1 => covox_channel3, 
++		 COVOX_CHANNEL_1 => covox_channel3,
+ 		 CHANNEL_ENABLE => "1111",
+-		 VOLUME_OUT => AUDIO_RIGHT);
++		 VOLUME_OUT => AUDIO_R);
+ 
+ 
+-b2v_inst15 : pokey
++pokey2 : pokey
+ PORT MAP(CLK => CLK,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+ 		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+@@ -1348,10 +793,10 @@
+ 		 RESET_N => RESET_N,
+ 		 ADDR => PBI_ADDR(3 DOWNTO 0),
+ 		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
++		 CHANNEL_0_OUT => POKEY2_CHANNEL0,
++		 CHANNEL_1_OUT => POKEY2_CHANNEL1,
++		 CHANNEL_2_OUT => POKEY2_CHANNEL2,
++		 CHANNEL_3_OUT => POKEY2_CHANNEL3,
+ 		 DATA_OUT => POKEY2_DO,
+ 		 SIO_IN1 => '1',
+ 		 SIO_IN2 => '1',
+@@ -1367,13 +812,14 @@
+ --GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+ --CB2_IN <= GPIO_O[1];
+ SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
++SIO_COMMAND_TX <= SIO_COMMAND_OUT;
+ -- TODO - sioto gpio!
+ GPIO_PORTB_IN <= PORTB_OUT;
+-GPIO_CA2_IN <= CA2_OUT;
+-GPIO_CB2_IN <= CB2_OUT;
+-GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
++GPIO_CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
++GPIO_CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
++GPIO_PORTA_IN <= ((JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)&JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
+ 
+-b2v_inst16 : pia
++pia1 : pia
+ PORT MAP(CLK => CLK,
+ 		 EN => PIA_READ_ENABLE,
+ 		 WR_EN => PIA_WRITE_ENABLE,
+@@ -1398,12 +844,13 @@
+ 		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+ 		 PORTB_OUT => PORTB_OUT);
+ 
+-b2v_inst17 : shared_enable
++HALT_OR_PAUSE_6502 <= HALT or PAUSE_6502;
++enables : shared_enable
+ PORT MAP(CLK => CLK,
+ 		 RESET_N => RESET_N,
+ 		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+ 		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+-		 PAUSE_6502 => PAUSE_6502,
++		 PAUSE_6502 => HALT_OR_PAUSE_6502,
+ 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+ 		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+ 		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+@@ -1412,35 +859,13 @@
+ 		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+ 		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+ 
+-
+-virtual_sticks <= (others=>'1');
+-virtual_triggers <= "0011";
+---b2v_inst18 : pokey_ps2_decoder
+---PORT MAP(CLK => CLK,
+---		 RESET_N => RESET_N,
+---		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+---		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+---		 KEY_UP => SYNTHESIZED_WIRE_10,
+---		 KEY_CODE => SYNTHESIZED_WIRE_11,
+---		 KEY_HELD => KEY_HELD,
+---		 SHIFT_PRESSED => SHIFT_PRESSED_DUMMY,
+---		 BREAK_PRESSED => BREAK_PRESSED_DUMMY,
+---		 CONSOL_START => CONSOL_START_DUMMY,
+---		 CONSOL_SELECT => CONSOL_SELECT_DUMMY,
+---		 CONSOL_OPTION => CONSOL_OPTION_DUMMY,
+---		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+---		 KBCODE => KBCODE_dummy,
+---		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+---		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+---		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+-
+ -- no cart!
+ CART_RD4 <= '0';
+ CART_RD5 <= '0';
+ CART_REQUEST_COMPLETE <= '0';
+ CART_ROM_DO <= (others=>'0');
+ 
+-b2v_inst2 : address_decoder
++mmu1 : address_decoder
+ PORT MAP(CLK => CLK,
+ 		 CPU_FETCH => CPU_FETCH,
+ 		 CPU_WRITE_N => R_W_N,
+@@ -1476,7 +901,7 @@
+ 		 RAM_DATA => RAM_DO,
+ 		 ram_select => RAM_SELECT(2 downto 0),
+ 		 ROM_DATA => ROM_DO,
+-		 rom_select => "00"&ROM_SELECT, -- TODO
++		 rom_select => ROM_SELECT, 
+ 		 SDRAM_DATA => SDRAM_DO,
+ 		 ZPU_ADDR => ZPU_ADDR_FETCH,
+ 		 ZPU_WRITE_DATA => ZPU_DO,
+@@ -1514,38 +939,35 @@
+ 		 cart_select => "0000000",
+ 		 cart_activate => '0');
+ 
+-b2v_inst21 : zpu_rom
++zpu_rom1 : zpu_rom
+ PORT MAP(clock => CLK,
+ 		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+ 		 q => ZPU_ROM_DATA);
++--
++--b2v_inst23 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(2),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(23 DOWNTO 16),
++--		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+ 
+-
+-b2v_inst22 : scandoubler
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 VGA => VGA,
+-		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+-		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+-		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+-		 vsync_in => SYNTHESIZED_WIRE_12,
+-		 hsync_in => SYNTHESIZED_WIRE_13,
+-		 colour_in => SYNTHESIZED_WIRE_14,
+-		 VSYNC => VGA_VS,
+-		 HSYNC => VGA_HS,
+-		 B => VGA_B(5 downto 2),
+-		 G => VGA_G(5 downto 2),
+-		 R => VGA_R(5 downto 2));
+-
+-b2v_inst23 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(2),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(23 DOWNTO 16),
+-		 q => ZPU_RAM_DATA(23 DOWNTO 16));
++zpu_ram1 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(23 downto 16),
++		 we => ZPU_STACK_WRITE(2),
++		 q => ZPU_RAM_DATA(23 downto 16)
++		 );	
+ 
+ SYNC_KEYS <= (others=> '0');
+ SYNC_SWITCHES <= (others=> '1');
+-b2v_inst24 : zpu_config_regs
++zpu_config1 : zpu_config_regs
+ PORT MAP(CLK => CLK,
+ 		 ENABLE_179 => POKEY_ENABLE_179,
+ 		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+@@ -1575,54 +997,89 @@
+ 		 DATA_OUT => ZPU_CONFIG_DO,
+ 		 LEDG => LEDG_dummy,
+ 		 LEDR => LEDR_dummy,
+-		 RAM_SELECT => RAM_SELECT,
+-		 ROM_SELECT => ROM_SELECT,
++		 RAM_SELECT => RAM_SELECT_dummy,
++		 ROM_SELECT => ROM_SELECT_dummy(1 downto 0),
+ 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+ 		 ZPU_HEX => ZPU_HEX,
+-		 sector_request => mist_sector_request,
+-		 sector => mist_sector,
+-		 sector_ready => mist_sector_ready_sync
++		 sector_request => dummy_sector_request,
++		 sector => dummy_sector,
++		 sector_ready => '0'
+ 		 );
++ROM_SELECT_dummy(5 downto 2) <= "0000";
+ 
++--
++--b2v_inst25 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(3),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(31 DOWNTO 24),
++--		 q => ZPU_RAM_DATA(31 DOWNTO 24));
++
++zpu_ram2 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(31 downto 24),
++		 we => ZPU_STACK_WRITE(3),
++		 q => ZPU_RAM_DATA(31 downto 24)
++		 );	
++
++
++--b2v_inst26 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(0),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(7 DOWNTO 0),
++--		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+ 
+-b2v_inst25 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(3),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(31 DOWNTO 24),
+-		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+-
+-
+-b2v_inst26 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(0),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(7 DOWNTO 0),
+-		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+-
+-
+-b2v_inst27 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(1),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(15 DOWNTO 8),
+-		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+-
+-
+-b2v_inst5 : pll
+-PORT MAP(inclk0 => CLOCK_27(0),
+-		 c0 => CLK_SDRAM,
+-		 c1 => CLK,
+-		 c2 => SDRAM_CLK,
+-		 locked => PLL_LOCKED);
++zpu_ram3 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(7 downto 0),
++		 we => ZPU_STACK_WRITE(0),
++		 q => ZPU_RAM_DATA(7 downto 0)
++		 );	
++
++
++--b2v_inst27 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(1),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(15 DOWNTO 8),
++--		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+ 
+-b2v_inst7 : pokey
++zpu_ram4 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(15 downto 8),
++		 we => ZPU_STACK_WRITE(1),
++		 q => ZPU_RAM_DATA(15 downto 8)
++		 );	
++
++pokey1 : pokey
+ PORT MAP(CLK => CLK,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+ 		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+ 		 WR_EN => POKEY_WRITE_ENABLE,
+ 		 RESET_N => RESET_N,
+-		 SIO_IN1 => '1',
++		 SIO_IN1 => SIO_RXD,
+ 		 SIO_IN2 => '1',
+ 		 SIO_IN3 => SIO_DATA_IN,
+ 		 ADDR => PBI_ADDR(3 DOWNTO 0),
+@@ -1630,39 +1087,62 @@
+ 		 keyboard_response => KEYBOARD_RESPONSE,
+ 		 POT_IN => POT_IN,
+ 		 IRQ_N_OUT => POKEY_IRQ,
+-		 SIO_OUT1 => UART_TXD_dummy,
++		 SIO_OUT1 => SIO_TXD,
+ 		 SIO_OUT2 => GPIO_SIO_OUT,
+ 		 SIO_OUT3 => SIO_DATA_OUT,
+ 		 POT_RESET => POT_RESET,
+-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
++		 CHANNEL_0_OUT => POKEY1_CHANNEL0,
++		 CHANNEL_1_OUT => POKEY1_CHANNEL1,
++		 CHANNEL_2_OUT => POKEY1_CHANNEL2,
++		 CHANNEL_3_OUT => POKEY1_CHANNEL3,
+ 		 DATA_OUT => POKEY_DO,
+ 		 keyboard_scan => KEYBOARD_SCAN);
+ 
+---	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+---	begin	
+---		keyboard_response <= (others=>'1');
+---		
+---		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
+---			keyboard_response(0) <= '0';
+---		end if;
+---		
+---		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
+---			keyboard_response(1) <= '0';
+---		end if;
+---		
+---		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
+---			keyboard_response(1) <= '0';
+---		end if;
+---
+---		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
+---			keyboard_response(1) <= '0';
+---		end if;
+---	end process;		 
+---		 	 
+-b2v_inst8 : gtia
++	keyboard_scan_inv <= not(keyboard_scan);
++
++a4051: complete_address_decoder
++	generic map (width => 3)
++	PORT map ( addr_in => keyboard_scan_inv(5 downto 3), addr_decoded => matrix_in ); 
++
++b4051: complete_address_decoder
++	generic map (width => 3)
++	PORT map ( addr_in => keyboard_scan_inv(2 downto 0), addr_decoded => matrix_out_match ); 
++
++	process(matrix_out, matrix_out_match)
++	begin
++		keyboard_response(0) <= '1';
++
++		if (or_reduce(matrix_out(7 downto 0) and matrix_out_match(7 downto 0)) = '1') then
++			keyboard_response(0) <= '0';
++		end if;
++	end process;
++
++	process(static_keys, pause_key)
++	begin
++		keyboard_response(1) <= '1';
++
++		if (keyboard_scan(5 downto 4)="00" and pause_key = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++		
++		if (keyboard_scan(5 downto 4)="10" and static_keys(0) = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++
++		if (keyboard_scan(5 downto 4)="11" and static_keys(1) = '1') then
++			keyboard_response(1) <= '0';
++		end if;
++	end process;
++
++	CONSOL_START <= static_keys(6);
++	CONSOL_SELECT <= static_keys(5);
++	CONSOL_OPTION <= static_keys(4);
++	system_reset_request <= static_keys(3);
++
++	virtual_keys <= "000"&static_keys(2); -- todo need more static keys!! though on second thoughts using replay menu for options/loading...
++	virtual_triggers <= "00"&joy1_n(4)&joy2_n(4); -- todo joystick...
++		 	 
++gtia1 : gtia
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => GTIA_WRITE_ENABLE,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+@@ -1677,8 +1157,10 @@
+ 		 CONSOL_START => CONSOL_START,
+ 		 CONSOL_SELECT => CONSOL_SELECT,
+ 		 CONSOL_OPTION => CONSOL_OPTION,
+-		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+-		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
++		 TRIG0 => joy2_n(4), -- TODO - joystick trigger too
++		 TRIG1 => joy1_n(4),
++		 --TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
++		 --TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+ 		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+ 		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+ 		 TRIG2 => VIRTUAL_TRIGGERS(2),
+@@ -1687,14 +1169,36 @@
+ 		 AN => ANTIC_AN,
+ 		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+ 		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+-		 VSYNC => SYNTHESIZED_WIRE_12,
+-		 HSYNC => SYNTHESIZED_WIRE_13,
++		 VSYNC => VGA_VS,
++		 HSYNC => VGA_HS,
++		 BLANK => GTIA_BLANK,
+ 		 sound => GTIA_SOUND,
+-		 COLOUR_out => SYNTHESIZED_WIRE_14,
++		 COLOUR_out => COLOUR,
+ 		 DATA_OUT => GTIA_DO);
+ 
++	-- colour palette
++--	Color             Value         Color             Value
++--Black           0,      0	Medium blue     8,    128
++--Rust            1,     16       Dark blue       9,    144
++--Red-orange      2,     32       Blue-grey      10,    160
++--Dark orange     3,     48       Olive green    11,    176
++--Red             4,     64       Medium green   12,    192
++--Dk lavender     5,     80       Dark green     13,    208
++--Cobalt blue     6,     96       Orange-green   14,    224
++--Ultramarine     7,    112       Orange         15,    240
++
++-- from altirra	
++	palette1 : entity work.gtia_palette(altirra)
++		port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R, G_next=>VGA_G, B_next=>VGA_B);
++	--VGA_B <= hcount_temp;
++	--VGA_G <= vcount_temp(7 downto 0);
++		
++-- from lao
++--	palette2 : entity work.gtia_palette(laoo)
++--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
++
+ 
+-b2v_inst9 : irq_glue
++irq_glue1 : irq_glue
+ PORT MAP(pokey_irq => POKEY_IRQ,
+ 		 pia_irqa => PIA_IRQA,
+ 		 pia_irqb => PIA_IRQB,
+@@ -1740,7 +1244,7 @@
+ 	DATA_OUT => CACHE_ANTIC_DO
+ );	
+ 
+-irr : internalromram
++internalromram1 : internalromram
+   PORT map(
+     clock => clk,
+     reset_n => reset_n,
+@@ -1758,77 +1262,10 @@
+ 	RAM_DATA => ram_do(7 downto 0)
+ 	);
+ 
+-b2v_inst20 : sdram_statemachine
+-GENERIC MAP(ADDRESS_WIDTH => 22,
+-			AP_BIT => 10,
+-			COLUMN_WIDTH => 8,
+-			ROW_WIDTH => 12
+-			)
+-PORT MAP(CLK_SYSTEM => CLK,
+-		 CLK_SDRAM => CLK_SDRAM,
+-		 RESET_N => RESET_N,
+-		 READ_EN => SDRAM_READ_ENABLE,
+-		 WRITE_EN => SDRAM_WRITE_ENABLE,
+-		 REQUEST => SDRAM_REQUEST,
+-		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+-		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+-		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+-		 REFRESH => SDRAM_REFRESH,
+-		 ADDRESS_IN => SDRAM_ADDR,
+-		 DATA_IN => WRITE_DATA,
+-		 SDRAM_DQ => SDRAM_DQ,
+-		 COMPLETE => SDRAM_REQUEST_COMPLETE,
+-		 SDRAM_BA0 => SDRAM_BA(0),
+-		 SDRAM_BA1 => SDRAM_BA(1),
+-		 SDRAM_CKE => SDRAM_CKE,
+-		 SDRAM_CS_N => SDRAM_nCS,
+-		 SDRAM_RAS_N => SDRAM_nRAS,
+-		 SDRAM_CAS_N => SDRAM_nCAS,
+-		 SDRAM_WE_N => SDRAM_nWE,
+-		 SDRAM_ldqm => SDRAM_DQML,
+-		 SDRAM_udqm => SDRAM_DQMH,
+-		 DATA_OUT => SDRAM_DO,
+-		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+-		 
+-SDRAM_A(12) <= '0';
+-
+---b2v_inst20 : sdram_statemachine_mcc
+---GENERIC MAP(ADDRESS_WIDTH => 22,
+---			AP_BIT => 10,
+---			COLUMN_WIDTH => 8,
+---			ROW_WIDTH => 12
+---			)
+---PORT MAP(CLK_SYSTEM => CLK,
+---		 CLK_SDRAM => CLK_SDRAM,
+---		 RESET_N => RESET_N,
+---		 READ_EN => SDRAM_READ_ENABLE,
+---		 WRITE_EN => SDRAM_WRITE_ENABLE,
+---		 REQUEST => SDRAM_REQUEST,
+---		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+---		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+---		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+---		 REFRESH => SDRAM_REFRESH,
+---		 ADDRESS_IN => SDRAM_ADDR,
+---		 DATA_IN => WRITE_DATA,
+---		 SDRAM_DQ => SDRAM_DQ,
+---		 REPLY => SDRAM_REQUEST_COMPLETE,
+---		 SDRAM_BA0 => SDRAM_BA(0),
+---		 SDRAM_BA1 => SDRAM_BA(1),
+---		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+---		 SDRAM_CS_N => SDRAM_nCS,
+---		 SDRAM_RAS_N => SDRAM_nRAS,
+---		 SDRAM_CAS_N => SDRAM_nCAS,
+---		 SDRAM_WE_N => SDRAM_nWE,
+---		 SDRAM_ldqm => SDRAM_DQML,
+---		 SDRAM_udqm => SDRAM_DQMH,
+---		 DATA_OUT => SDRAM_DO,
+---		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
+-
+---SDRAM_CKE <= '1';		 
+-LED <= '0';
+-VGA_R(1 downto 0) <= "00";
+-VGA_G(1 downto 0) <= "00";
+-VGA_B(1 downto 0) <= "00";
++SDRAM_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
++SDRAM_WIDTH_16bit_ACCESS <= WIDTH_16bit_access;
++SDRAM_WIDTH_32bit_ACCESS <= WIDTH_32bit_access;
++SDRAM_DI <= WRITE_DATA;
+ 
+ covox1 : covox
+ 	PORT map
+@@ -1842,5 +1279,5 @@
+ 		covox_channel2 => covox_channel2,
+ 		covox_channel3 => covox_channel3
+ 	);
+-		
+-END bdf_type;
+\ No newline at end of file
++
++END bdf_type;
+Only in mist/: atari800core.vhd.bak
+Only in mist/: ataribas.mif
+Only in mist/: basic.cmp
+Only in mist/: basic.qip
+Only in mist/: basic.vhd
+Only in ../../common/a8core/: basic.vhdl
+Only in mist/: CHANGELOG
+Only in mist/: COPYRIGHT_NOTICE
+Only in mist/: covox.vhd.bak
+diff -ur mist/cpu_6510.vhd ../../common/a8core/cpu_6510.vhd
+--- mist/cpu_6510.vhd	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/cpu_6510.vhd	2014-03-23 08:03:29.689482071 +0000
+@@ -98,45 +98,6 @@
+ 			debug_flags => debug_flags
+ 		);
+ 	
+-	MyBitfade: if emulate_bitfade generate
+-		bitfade7 : entity work.chameleon_bitfade
+-			generic map (
+-				max_fade_timer => 100
+-			)
+-			port map (
+-				clk => clk,
+-				ena_1khz => ena_1khz,
+-				
+-				dir => ioDir(7),
+-				d => ioData(7),
+-				q => ioFade(7)
+-			);
+-		bitfade6 : entity work.chameleon_bitfade
+-			generic map (
+-				max_fade_timer => 100
+-			)
+-			port map (
+-				clk => clk,
+-				ena_1khz => ena_1khz,
+-				
+-				dir => ioDir(6),
+-				d => ioData(6),
+-				q => ioFade(6)
+-			);
+-		bitfade3 : entity work.chameleon_bitfade
+-			generic map (
+-				max_fade_timer => 100
+-			)
+-			port map (
+-				clk => clk,
+-				ena_1khz => ena_1khz,
+-				
+-				dir => ioDir(3),
+-				d => ioData(3),
+-				q => ioFade(3)
+-			);
+-	end generate;
+-	
+ 	process(localA)
+ 	begin
+ 		accessIO <= '0';
+diff -ur mist/cpu_65xx_a.vhd ../../common/a8core/cpu_65xx_a.vhd
+--- mist/cpu_65xx_a.vhd	2014-01-18 14:29:19.000000000 +0000
++++ ../../common/a8core/cpu_65xx_a.vhd	2014-03-23 08:03:29.661482072 +0000
+@@ -1438,7 +1438,7 @@
+ -- -----------------------------------------------------------------------
+ -- Address generation
+ -- -----------------------------------------------------------------------
+-calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
++calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset, processInt)
+ 	begin
+ 		nextAddr <= nextAddrIncr;
+ 		case theCpuCycle is
+Only in mist/: cpu_65xx_a.vhd.bak
+diff -ur mist/cpu.vhd ../../common/a8core/cpu.vhd
+--- mist/cpu.vhd	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/cpu.vhd	2014-03-23 08:03:29.677482072 +0000
+@@ -108,7 +108,7 @@
+ 			debugPc => debugPc,
+ 			debugA => debugA,
+ 			debugX => debugX,
+-			debugY => debugOpcode,
++			debugY => debugY,
+ 			debugS => debugS
+ 		);
+ 		CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
+Only in mist/: custom_io.vhd
+Only in mist/: data_io.v~
+Only in mist/: data_io.vhdl
+Only in mist/: data_io.vhdl.bak
+Only in mist/: flashrom.vhdl
+Only in mist/: generic_ram_infer.vhdl.bak
+Only in mist/: gpio.vhd
+diff -ur mist/gtia_palette.vhdl ../../common/a8core/gtia_palette.vhdl
+--- mist/gtia_palette.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/gtia_palette.vhdl	2014-03-23 08:03:29.665482072 +0000
+@@ -1049,6 +1049,8 @@
+ 					R_next <= X"ff";
+ 					G_next <= X"f3";
+ 					B_next <= X"9a";
++				when others =>
++					-- nop
+ 			end case;
+ 			
+ 		end process;
+@@ -2085,6 +2087,8 @@
+ 						R_next <= X"ff";
+ 						G_next <= X"e3";
+ 						B_next <= X"a1";
++					when others =>
++						-- nop
+ 			end case;
+ 			
+ 		end process;
+diff -ur mist/gtia_player.vhdl ../../common/a8core/gtia_player.vhdl
+--- mist/gtia_player.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/gtia_player.vhdl	2014-03-23 08:03:29.673482072 +0000
+@@ -73,6 +73,8 @@
+ 							shift_next <= shift_reg(6 downto 0) &'0';
+ 						when "01"|"10" =>
+ 							count_next <= "10";						
++						when others=>
++							--hang!
+ 					end case;					
+ 				when "01" =>					
+ 					case count_reg is
+@@ -81,6 +83,8 @@
+ 							shift_next <= shift_reg(6 downto 0) &'0';
+ 						when "00"|"10" =>
+ 							count_next <= "01";							
++						when others=>
++							--hang!
+ 					end case;					
+ 
+ 				when "11" =>
+@@ -94,7 +98,11 @@
+ 						when "11" =>
+ 							shift_next <= shift_reg(6 downto 0) &'0';
+ 							count_next <= "00";
++						when others=>
++							--hang!
+ 					end case;
++				when others=>
++					--hang!
+ 			end case;	
+ 
+ 			if (live_position = player_position) then
+@@ -105,4 +113,4 @@
+ 		
+ 	end process;
+ 	
+-end vhdl;
+\ No newline at end of file
++end vhdl;
+diff -ur mist/gtia.vhdl ../../common/a8core/gtia.vhdl
+--- mist/gtia.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/gtia.vhdl	2014-03-23 08:03:29.697482071 +0000
+@@ -53,6 +53,7 @@
+ 	
+ 	VSYNC : out std_logic;
+ 	HSYNC : out std_logic;
++	BLANK : out std_logic;
+ 	
+ 	-- To speaker
+ 	sound : out std_logic
+@@ -216,6 +217,11 @@
+ 	signal grafm_next : std_logic_vector(7 downto 0);
+ 	signal grafm_reg : std_logic_vector(7 downto 0);
+ 
++	signal grafm_reg10_extended : std_logic_vector(7 downto 0);
++	signal grafm_reg32_extended : std_logic_vector(7 downto 0);
++	signal grafm_reg54_extended : std_logic_vector(7 downto 0);
++	signal grafm_reg76_extended : std_logic_vector(7 downto 0);
++
+ 	signal colpm0_raw_next : std_logic_vector(7 downto 1);
+ 	signal colpm0_raw_reg : std_logic_vector(7 downto 1);
+ 	signal colpm1_raw_next : std_logic_vector(7 downto 1);
+@@ -795,6 +801,8 @@
+ 						if (active_bk_modify_next(7 downto 4) = "0000") then
+ 							active_bk_valid_next(3 downto 0) <= "0000";
+ 						end if;
++					when others =>
++						-- nop
+ 				end case;
+ 			end if;
+ 			
+@@ -1007,14 +1015,18 @@
+ 	player3 : gtia_player
+ 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);				
+ 
++	grafm_reg10_extended <= grafm_reg(1 downto 0)&"000000";
++	grafm_reg32_extended <= grafm_reg(3 downto 2)&"000000";
++	grafm_reg54_extended <= grafm_reg(5 downto 4)&"000000";
++	grafm_reg76_extended <= grafm_reg(7 downto 6)&"000000";
+ 	missile0 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg(1 downto 0)&"000000", output=>active_m0_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg10_extended, output=>active_m0_live);
+ 	missile1 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg(3 downto 2)&"000000", output=>active_m1_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg32_extended, output=>active_m1_live);
+ 	missile2 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg(5 downto 4)&"000000", output=>active_m2_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg54_extended, output=>active_m2_live);
+ 	missile3 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg(7 downto 6)&"000000", output=>active_m3_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg76_extended, output=>active_m3_live);
+ 		
+ 	-- calculate atari colour
+ 	priority_rules : gtia_priority
+@@ -1534,7 +1546,7 @@
+ 		end if;
+ 		
+ 		if (addr_decoded(20) = '1') then
+-			data_out <= "00000"&not(pal&pal&pal);
++			data_out <= "0000"&not(pal&pal&pal)&'1';
+ 		end if;
+ 
+ 		if (addr_decoded(31) = '1') then
+@@ -1548,6 +1560,7 @@
+ 	
+ 	vsync<=vsync_reg;
+ 	hsync<=hsync_reg;
++	blank<=hblank_reg or vsync_reg;
+ 	
+ 	sound <= consol_output_reg(3);
+ 
+Only in mist/: hexdecoder.vhd
+Only in mist/: hq_dac.v
+Only in mist/: i2c_loader.vhd
+Only in mist/: i2s_intf.vhd
+Only in mist/: i2sslave.vhdl
+diff -ur mist/internalromram.vhd ../../common/a8core/internalromram.vhd
+--- mist/internalromram.vhd	2014-03-08 17:35:06.000000000 +0000
++++ ../../common/a8core/internalromram.vhd	2014-03-23 08:03:29.689482071 +0000
+@@ -23,18 +23,35 @@
+ END internalromram;
+ 
+ architecture vhdl of internalromram is
+-component ramint IS
+-	PORT
+-	(
+-		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+-		clock		: IN STD_LOGIC  := '1';
+-		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+-		wren		: IN STD_LOGIC ;
+-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+-	);
++--component ramint IS
++--	PORT
++--	(
++--		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
++--		clock		: IN STD_LOGIC  := '1';
++--		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
++--		wren		: IN STD_LOGIC ;
++--		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
++--	);
++--END component;
++
++component generic_ram_infer IS
++        generic
++        (
++                ADDRESS_WIDTH : natural := 9;
++                SPACE : natural := 512;
++                DATA_WIDTH : natural := 8
++        );
++   PORT
++   (
++      clock: IN   std_logic;
++      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
++      address:  IN   std_logic_vector(address_width-1 downto 0);
++      we:    IN   std_logic;
++      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
++   );
+ END component;
+ 
+-component rom16 IS
++component os16 IS
+ 	PORT
+ 	(
+ 		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+@@ -89,27 +106,33 @@
+ 	
+ 	--ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
+ 	--ROM_DATA <= ROMHI_DATA;
+---	basic1 : basic
+---	PORT MAP(clock => clock,
+---			 address => rom_addr(12 downto 0),
+---			 q => BASIC_data
+---			 );			 
+---			 
+---	rom16a : rom16
+---	PORT MAP(clock => clock,
+---			 address => rom_addr(13 downto 0),
+---			 q => ROM16_data
+---			 );
+---	
+---	ramint1 : ramint
+---	PORT MAP(clock => clock,
+---			 address => ram_addr(12 downto 0),
+---			 data => ram_data_in(7 downto 0),
+---			 wren => RAM_WR_ENABLE_REAL,
+---			 q => iram_data
+---			 );	
++	basic1 : basic
++	PORT MAP(clock => clock,
++			 address => rom_addr(12 downto 0),
++			 q => BASIC_data
++			 );			 
++			 
++	rom16a : os16
++	PORT MAP(clock => clock,
++			 address => rom_addr(13 downto 0),
++			 q => ROM16_data
++			 );
++	
++	ramint1 : generic_ram_infer
++        generic map
++        (
++                ADDRESS_WIDTH => 14,
++                SPACE => 16384,
++                DATA_WIDTH =>8
++        )
++	PORT MAP(clock => clock,
++			 address => ram_addr(13 downto 0),
++			 data => ram_data_in(7 downto 0),
++			 we => RAM_WR_ENABLE_REAL,
++			 q => iram_data
++			 );	
+ 	ram_request_complete <= ram_request_reg;
+ 	
+-	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
+-	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
+-end vhdl;
+\ No newline at end of file
++	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 14)= "00" else X"FF";
++	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 14)="00" else '0'; -- ban writes over 16k when using int ram - HACK
++end vhdl;
+Only in mist/: internalromram.vhd.bak
+Only in mist/: ledsw.vhd
+Only in mist/: mist_sector_buffer.cmp
+Only in mist/: mist_sector_buffer.qip
+Only in mist/: mist_sector_buffer.vhd
+Only in mist/: os16.mif
+Only in ../../common/a8core/: os16.vhdl
+Only in mist/: output_file.rbf
+diff -ur mist/pia.vhdl ../../common/a8core/pia.vhdl
+--- mist/pia.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/pia.vhdl	2014-03-23 08:03:29.645482073 +0000
+@@ -310,6 +310,8 @@
+ 						-- ca1 restore
+ 						ca2_output_next <= '1';	
+ 					end if;				
++				when others =>
++					-- nop
+ 			end case;					
+ 		end if;
+ 
+@@ -363,6 +365,8 @@
+ 						-- cb1 restore
+ 						cb2_output_next <= '1';	
+ 					end if;				
++				when others =>
++					--nop
+ 			end case;					
+ 		end if;
+ 
+Only in mist/: pll.bsf
+Only in mist/: pll.cmp
+Only in mist/: PLLJ_PLLSPE_INFO.txt
+Only in mist/: pll.ppf
+Only in mist/: pll.qip
+Only in mist/: pll.vhd
+Only in mist/: pll.vhd.bak
+diff -ur mist/pokey_keyboard_scanner.vhdl ../../common/a8core/pokey_keyboard_scanner.vhdl
+--- mist/pokey_keyboard_scanner.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/pokey_keyboard_scanner.vhdl	2014-03-23 08:03:29.769482067 +0000
+@@ -150,6 +150,9 @@
+ 				if (my_key = '1') then
+ 					state_next <= state_wait_key;
+ 				end if;
++
++			when others=> 
++				state_next <= state_wait_key; 
+ 			end case;
+ 
+ 			if (bincnt_reg(3 downto 0)  = "0000") then
+@@ -176,4 +179,4 @@
+ 	shift_pressed <= shift_pressed_reg;
+ 	control_pressed <= control_pressed_reg;
+ 	other_key_irq <= irq_reg;
+-end vhdl;
+\ No newline at end of file
++end vhdl;
+Only in mist/: pokey_mixer.vhdl.bak
+Only in mist/: pokey_ps2_decoder.vhdl
+Only in mist/: pokey_ps2_decoder.vhdl.bak
+diff -ur mist/pokey.vhdl ../../common/a8core/pokey.vhdl
+--- mist/pokey.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/pokey.vhdl	2014-03-23 15:34:33.619247550 +0000
+@@ -330,6 +330,7 @@
+ 	signal serout_active_reg : std_logic;
+ 	
+ 	signal serial_reset : std_logic;
++	signal serout_sync_reset : std_logic;
+ 	signal skrest_write : std_logic;
+ 	
+ 	signal serout_enable : std_logic;
+@@ -764,7 +765,7 @@
+ 		end if;		
+ 
+ 		if (addr_decoded(15) = '1') then --SKSTAT
+-			data_out <= not(serial_ip_framing_reg)&not(serial_ip_overrun_reg)&not(keyboard_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
++			data_out <= not(serial_ip_framing_reg)&not(keyboard_overrun_reg)&not(serial_ip_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
+ 		end if;		
+ 		
+ 	end process;
+@@ -936,9 +937,10 @@
+ 	
+ 	-- serial port output	
+ 	-- urghhh
++        serout_sync_reset <= serial_reset or stimer_write_delayed;
+ 	serout_clock_delay : delay_line
+ 		generic map (count=>2)
+-		port map (clk=>clk, sync_reset=>serial_reset or stimer_write_delayed,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
++		port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+ 		
+ 	
+ 	process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
+@@ -1131,6 +1133,8 @@
+ 			when "111" =>			
+ 				serin_enable <= audf3_pulse;
+ 				serout_enable <= audf1_pulse;
++			when others =>
++				-- nop
+ 		end case;
+ 	end process;
+ 	
+Only in mist/: ps2_keyboard.vhdl
+Only in mist/: ramint.bsf
+Only in mist/: ramint.cmp
+Only in mist/: ramint.qip
+Only in mist/: ramint.vhd
+Only in mist/: rom16.cmp
+Only in mist/: rom16.qip
+Only in mist/: rom16.vhd
+Only in mist/: romhi.bsf
+Only in mist/: romhi.cmp
+Only in mist/: romhi.qip
+Only in mist/: romhi.vhd
+Only in mist/: romlo.bsf
+Only in mist/: romlo.cmp
+Only in mist/: romlo.qip
+Only in mist/: romlo.vhd
+Only in mist/: scandouble_ram_infer.vhdl
+Only in mist/: scandoubler.vhdl
+Only in mist/: sdram_ctrl_4_ports.v
+Only in mist/: sdram_ctrl_4_ports.v.bak
+Only in mist/: sdram_statemachine_mcc.vhdl
+Only in mist/: sdram_statemachine_mcc.vhdl.bak
+Only in mist/: sdram_statemachine.vhdl
+Only in mist/: sdram_statemachine.vhdl.bak
+diff -ur mist/shared_enable.vhdl ../../common/a8core/shared_enable.vhdl
+--- mist/shared_enable.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../common/a8core/shared_enable.vhdl	2014-03-23 08:03:29.653482073 +0000
+@@ -50,6 +50,7 @@
+ 	PORT 
+ 	( 
+ 		CLK : IN STD_LOGIC;
++		SYNC_RESET : IN STD_LOGIC;
+ 		DATA_IN : IN STD_LOGIC;
+ 		ENABLE : IN STD_LOGIC;
+ 		RESET_N : IN STD_LOGIC;
+@@ -78,6 +79,8 @@
+ 	signal enable_179_expanded : std_logic;
+ 	
+ 	signal memory_ready : std_logic;
++
++	constant cycle_length : integer := 16;	
+ begin
+ 	-- instantiate some clock calcs
+ 	SCANDOUBLER_ENABLE_HIGH <= '1';
+@@ -87,8 +90,7 @@
+ 		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
+ 
+ 	enable_179_clock_div : enable_divider
+-		--generic map (COUNT=>16)
+-		generic map (COUNT=>32)
++		generic map (COUNT=>cycle_length)
+ 		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
+ 		
+ 	process(THROTTLE_COUNT_6502, throttle_count_reg, enable_179)
+@@ -120,14 +122,12 @@
+ 	end process;
+ 
+ 	delay_line_phase : delay_line
+-		--generic map (COUNT=>15)
+-		generic map (COUNT=>31)
+-		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
++		generic map (COUNT=>cycle_length-1)
++		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+ 
+ 	delay_line_phase2 : delay_line
+-		--generic map (COUNT=>15)
+-		generic map (COUNT=>16)
+-		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
++		generic map (COUNT=>cycle_length/2)
++		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+ 	
+ 	-- registers
+ 	process(clk,reset_n)
+Only in mist/: spi_master.vhd
+Only in mist/: sram.vhdl
+Only in mist/: stp1.stp
+Only in mist/: user_io.v
+Only in mist/: user_io.v.bak
+Only in mist/: zpu
+Only in mist/: zpu_config_regs.vhdl
+Only in mist/: zpu_config_regs.vhdl.bak
+Only in mist/: zpu_core.vhd
+Only in mist/: zpu_glue.vhdl
+Only in mist/: zpu_glue.vhdl.bak
+Only in mist/: zpupkg.vhd
+Only in mist/: zpu_ram.cmp
+Only in mist/: zpu_ram.qip
+Only in mist/: zpu_ram.vhd
+Only in mist/: zpu_rom.cmp
+Only in mist/: zpu_rom.qip
+Only in mist/: zpu_rom.vhd
Index: unmerged/zpu_firmware/de1_old/HelloTinyROM.rpt
===================================================================
--- unmerged/zpu_firmware/de1_old/HelloTinyROM.rpt	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/HelloTinyROM.rpt	(revision 1)
@@ -0,0 +1,3 @@
+End of code:	0000346c g       *ABS*	00000000 _romend
+Start of BSS:	0000f000 g       .bss	00000000 __bss_start__
+End of BSS:	0000f3bc g       *ABS*	00000000 __bss_end__
Index: unmerged/zpu_firmware/de1_old/bootdump
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/bootdump
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/de1_old/crt0.S
===================================================================
--- unmerged/zpu_firmware/de1_old/crt0.S	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/crt0.S	(revision 1)
@@ -0,0 +1,974 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	
+	
+	
+;	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+; DANGER!!!! 
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!! 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jsr address
+			im _memreg     	; save R0
+			load
+			im _memreg+4	; save R1
+			load
+			im _memreg+8	; save R2
+			load
+			fixedim \address
+			call
+			im _memreg+8
+			store		; restore R2
+			im _memreg+4
+			store		; restore R1
+			im _memreg
+			store		; restore R0
+	.endm
+
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+		
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		; intSp must be 0 when we jump to _premain
+		
+		im ZPU_ID
+		loadsp 0
+		im _cpu_config
+		store
+		config
+		jmp _premain
+
+
+
+        .balign 32,0
+# offset 0x0000 0020
+		.globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+		jmp ___zpu_interrupt_vector
+
+
+        .balign 16,0
+# offset 0x0000 0030
+		.globl _memreg
+		.weak _memreg
+_memreg:
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+        .globl ___zpu_interrupt_vector
+        .weak ___zpu_interrupt_vector
+
+___zpu_interrupt_vector:
+	jsr _zpu_interrupt
+	poppc
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+

Property changes on: unmerged/zpu_firmware/de1_old/crt0.S
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: unmerged/core/mist/zpu_glue.vhdl
===================================================================
--- unmerged/core/mist/zpu_glue.vhdl	(nonexistent)
+++ unmerged/core/mist/zpu_glue.vhdl	(revision 1)
@@ -0,0 +1,379 @@
+---------------------------------------------------------------------------
+-- (c) 2013 mark watson
+-- I am happy for anyone to use this for non-commercial use.
+-- If my vhdl files are used commercially or otherwise sold,
+-- please contact me for explicit permission at scrameta (gmail).
+-- This applies for source and binary form and derived works.
+---------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+use IEEE.STD_LOGIC_MISC.all;
+
+library work;
+use work.zpupkg.all;
+
+ENTITY zpu_glue IS
+PORT 
+(
+	CLK : in std_logic;
+	RESET : in std_logic;
+	PAUSE : in std_logic;
+
+	ZPU_DI : in std_logic_vector(31 downto 0); -- response from general memory - for areas that only support 8/16 bit set top bits to 0
+	ZPU_ROM_DI : in std_logic_vector(31 downto 0); -- response from own program memory
+	ZPU_RAM_DI : in std_logic_vector(31 downto 0); -- response from own stack	
+	ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+	ZPU_CONFIG_DI : in std_logic_vector(31 downto 0); -- response from config registers
+	
+	ZPU_DO : out std_logic_vector(31 downto 0);
+	
+	ZPU_ADDR_ROM_RAM : out std_logic_vector(23 downto 0); -- direct from zpu, for short paths
+	ZPU_ADDR_FETCH : out std_logic_vector(23 downto 0); -- clk->q, for longer paths
+	
+	-- request
+	MEMORY_FETCH : out std_logic;
+	ZPU_READ_ENABLE : out std_logic;
+	ZPU_32BIT_WRITE_ENABLE : out std_logic; -- common case
+	ZPU_16BIT_WRITE_ENABLE : out std_logic; -- for sram (never happens yet!)
+	ZPU_8BIT_WRITE_ENABLE : out std_logic; -- for hardware regs
+	
+	-- config
+	ZPU_CONFIG_WRITE : out std_logic;
+	
+	-- stack request
+	ZPU_STACK_WRITE : out std_logic_vector(3 downto 0);
+
+	-- response
+	MEMORY_READY : in std_logic
+);
+END zpu_glue;
+
+architecture sticky of zpu_glue is
+component ZPUMediumCore is
+   generic(
+      WORD_SIZE    : integer:=32;  -- 16/32 (2**wordPower)
+      ADDR_W       : integer:=24;  -- Total address space width (incl. I/O)
+      MEM_W        : integer:=16;  -- Memory (prog+data+stack) width - stack at end of memory - so end of sdram. 32K ROM, 32K RAM (MAX)
+      D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+      MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+      BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+      ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+      ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+      ENA_LEVEL2   : boolean:=true; -- lessthanorequal, ulessthanorequal, call and poppcrel
+      ENA_LSHR     : boolean:=true;  -- lshiftright
+      ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+      FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+   port(
+      clk_i        : in  std_logic; -- CPU Clock
+      reset_i      : in  std_logic; -- Sync Reset
+      enable_i     : in  std_logic; -- Hold the CPU (after reset)
+      break_o      : out std_logic; -- Break instruction executed
+      dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+      -- Memory interface
+      mem_busy_i   : in  std_logic; -- Memory is busy
+      data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+      data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+      addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+      write_en_o   : out std_logic;  -- Memory write enable (32-bit)
+      read_en_o    : out std_logic; -- Memory read enable (32-bit)
+		byte_read_o : out std_logic;
+		byte_write_o : out std_logic;
+		short_write_o: out std_logic); -- never happens
+	end component;	
+			
+	signal zpu_addr_unsigned : unsigned(23 downto 0);
+	signal zpu_do_unsigned : unsigned(31 downto 0);
+	signal ZPU_DI_unsigned : unsigned(31 downto 0);
+	signal zpu_break : std_logic;
+	signal zpu_debug : zpu_dbgo_t;
+	
+	signal zpu_mem_busy : std_logic;
+	
+	signal zpu_memory_fetch_pending_next : std_logic;
+	signal zpu_memory_fetch_pending_reg : std_logic;
+	
+	signal ZPU_32bit_READ_ENABLE_temp : std_logic;
+	signal ZPU_8bit_READ_ENABLE_temp : std_logic;	
+	signal ZPU_READ_temp : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_temp : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_temp : std_logic;	
+	signal ZPU_WRITE_temp : std_logic;
+	
+	signal ZPU_32BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_next : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_next : std_logic;	
+	signal ZPU_READ_next : std_logic;
+	signal ZPU_32BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_16BIT_WRITE_ENABLE_reg : std_logic;
+	signal ZPU_8BIT_WRITE_ENABLE_reg : std_logic;	
+	signal ZPU_READ_reg : std_logic;
+	
+	signal block_mem : std_logic;
+	signal config_mem : std_logic;
+	signal special_mem : std_logic;
+	
+	signal result_next : std_logic_vector(4 downto 0);
+	signal result_reg : std_logic_vector(4 downto 0);
+	constant result_external   : std_logic_vector(4 downto 0) := "00000";
+	constant result_ram        : std_logic_vector(4 downto 0) := "00001";
+	constant result_ram_8bit_0 : std_logic_vector(4 downto 0) := "00010";
+	constant result_ram_8bit_1 : std_logic_vector(4 downto 0) := "00011";
+	constant result_ram_8bit_2 : std_logic_vector(4 downto 0) := "00100";
+	constant result_ram_8bit_3 : std_logic_vector(4 downto 0) := "00101";
+	constant result_rom        : std_logic_vector(4 downto 0) := "00110";
+	constant result_rom_8bit_0 : std_logic_vector(4 downto 0) := "00111";
+	constant result_rom_8bit_1 : std_logic_vector(4 downto 0) := "01000";
+	constant result_rom_8bit_2 : std_logic_vector(4 downto 0) := "01001";
+	constant result_rom_8bit_3 : std_logic_vector(4 downto 0) := "01010";	
+	constant result_config     : std_logic_vector(4 downto 0) := "01011";	
+	constant result_external_special : std_logic_vector(4 downto 0) := "01100";
+	constant result_sec        : std_logic_vector(4 downto 0) := "01101";
+	constant result_sec_8bit_0 : std_logic_vector(4 downto 0) := "01110";
+	constant result_sec_8bit_1 : std_logic_vector(4 downto 0) := "01111";
+	constant result_sec_8bit_2 : std_logic_vector(4 downto 0) := "10000";
+	constant result_sec_8bit_3 : std_logic_vector(4 downto 0) := "10001";
+	
+	signal request_type : std_logic_vector(4 downto 0);
+	
+	signal zpu_di_use : std_logic_vector(31 downto 0);
+	
+	signal memORY_ACCESS : std_logic;
+
+	-- 1 cycle delay on memory read - needed to allow running at higher clock
+	signal zpu_di_next : std_logic_vector(31 downto 0);
+	signal zpu_di_reg : std_logic_vector(31 downto 0);
+	
+	signal memory_ready_next : std_logic;
+	signal memory_ready_reg : std_logic;
+	
+	signal zpu_enable : std_logic;
+	
+	signal zpu_addr_next : std_logic_vector(23 downto 0);
+	signal zpu_addr_reg : std_logic_vector(23 downto 0);
+	
+begin
+		-- register
+	process(clk,reset)
+	begin
+		if (reset='1') then
+			zpu_memory_fetch_pending_reg <= '0';
+			result_reg <= result_rom;
+			zpu_di_reg <= (others=>'0');
+			memory_ready_reg <= '0';
+			zpu_addr_reg <= (others=>'0');
+			ZPU_32BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_16BIT_WRITE_ENABLE_reg <= '0';
+			ZPU_8BIT_WRITE_ENABLE_reg <= '0';	
+			ZPU_READ_reg <= '0';
+		elsif (clk'event and clk='1') then
+			zpu_memory_fetch_pending_reg <= zpu_memory_fetch_pending_next;
+			result_reg <= result_next;
+			zpu_di_reg <= zpu_di_next;
+			memory_ready_reg <= memORY_READY_next;
+			zpu_addr_reg <=zpu_addr_next;
+			ZPU_32BIT_WRITE_ENABLE_reg <= ZPU_32BIT_WRITE_ENABLE_next;
+			ZPU_16BIT_WRITE_ENABLE_reg <= ZPU_16BIT_WRITE_ENABLE_next;
+			ZPU_8BIT_WRITE_ENABLE_reg <= ZPU_8BIT_WRITE_ENABLE_next;
+			ZPU_READ_reg <= ZPU_READ_next;
+		end if;
+	end process;
+
+-- a little glue
+	process(zpu_ADDR_unsigned)
+	begin
+		block_mem <= '0';
+		config_mem <= '0';
+		special_mem <= '0';
+		-- $00000-$0FFFF = Own ROM/RAM
+		-- $10000-$1FFFF = Atari
+		-- $20000-$2FFFF = Atari - savestate (gtia/antic/pokey have memory behind them)
+		-- $40000-$4FFFF = Config area
+		if (or_reduce(std_logic_vector(zpu_ADDR_unsigned(23 downto 21))) = '0') then -- special area
+			block_mem <= not(zpu_addr_unsigned(18) or zpu_addr_unsigned(17) or zpu_addr_unsigned(16));
+			config_mem <= zpu_addr_unsigned(18);
+			special_mem <= zpu_addr_unsigned(17);
+		end if;	
+	end process;
+
+	ZPU_READ_TEMP <= zpu_32bit_read_enable_temp or zpu_8BIT_read_enable_temp;
+	ZPU_WRITE_TEMP<= zpu_32BIT_WRITE_ENABLE_temp or zpu_16BIT_WRITE_ENABLE_temp or zpu_8BIT_WRITE_ENABLE_temp;
+	process(zpu_addr_reg,pause,memory_ready,zpu_memory_fetch_pending_next,request_type, zpu_memory_fetch_pending_reg, memory_ready_reg, zpu_ADDR_unsigned, zpu_8bit_read_enable_temp, zpu_write_temp, result_reg, block_mem, config_mem, memORY_ACCESS,
+	        zpu_read_reg,zpu_8BIT_WRITE_ENABLE_reg, zpu_16BIT_WRITE_ENABLE_reg, zpu_32BIT_WRITE_ENABLE_reg,
+			  zpu_read_temp,zpu_8BIT_WRITE_ENABLE_temp, zpu_16BIT_WRITE_ENABLE_temp, zpu_32BIT_WRITE_ENABLE_temp,
+			  special_mem
+			  )
+	begin
+		zpu_memory_fetch_pending_next <= zpu_memory_fetch_pending_reg;
+		result_next <= result_reg;
+		memory_ready_next <= memory_ready;
+		zpu_stACK_WRITE <= (others=>'0');
+		ZPU_config_write <= '0';
+		zpu_addr_next <= zpu_addr_reg;
+	
+		ZPU_MEM_BUSY <= pause;
+		
+		MEMORY_ACCESS <= zpu_READ_temp or ZPU_WRITE_temp;
+		
+		memory_fetch <= zpu_memory_fetch_pending_reg;
+		
+		zpu_read_next <= zpu_read_reg;
+		zpu_8bit_write_enable_next <= zpu_8bit_write_enable_reg;
+		zpu_16bit_write_enable_next <= zpu_16bit_write_enable_reg;
+		zpu_32bit_write_enable_next <= zpu_32bit_write_enable_reg;	
+		
+		request_type <= config_mem&block_mem&zpu_addr_unsigned(15)&memORY_ACCESS&zpu_memory_fetch_pending_reg;
+		case request_type is
+			when "00010"|"00110" =>
+				zpu_memory_fetch_pending_next <= '1';
+				if (special_mem='0') then
+					result_next <= result_external;
+				else
+					result_next <= result_external_special;
+				end if;
+				
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+				zpu_read_next <= zpu_read_temp;
+				zpu_8bit_write_enable_next <= zpu_8bit_write_enable_temp;
+				zpu_16bit_write_enable_next <= zpu_16bit_write_enable_temp;
+				zpu_32bit_write_enable_next <= zpu_32bit_write_enable_temp;					
+			when "01010" =>
+				-- TODO - addr(14) should just feed 1 bit in result reg!
+				if (zpu_addr_unsigned(14) = '1') then
+					if (zpu_8bit_read_enable_temp='1') then
+						case (zpu_addr_unsigned(1 downto 0)) is
+						when "00" =>
+							result_next <= result_sec_8bit_0;										
+						when "01" =>
+							result_next <= result_sec_8bit_1;
+						when "10" =>
+							result_next <= result_sec_8bit_2;										
+						when "11" =>
+							result_next <= result_sec_8bit_3;
+						end case;
+					else
+						result_next <= result_sec;
+					end if;					
+				else
+					if (zpu_8bit_read_enable_temp='1') then
+						case (zpu_addr_unsigned(1 downto 0)) is
+						when "00" =>
+							result_next <= result_rom_8bit_3;										
+						when "01" =>
+							result_next <= result_rom_8bit_2;
+						when "10" =>
+							result_next <= result_rom_8bit_1;										
+						when "11" =>
+							result_next <= result_rom_8bit_0;
+						end case;
+					else
+						result_next <= result_rom;
+					end if;
+				end if;
+				ZPU_MEM_BUSY <= '1';
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "01110" =>
+				if (zpu_8bit_read_enable_temp='1' or zpu_8BIT_WRITE_ENABLE_temp='1') then
+					case (zpu_addr_unsigned(1 downto 0)) is
+					when "00" =>
+						result_next <= result_ram_8bit_3;										
+						ZPU_STACK_WRITE(3) <= zpu_8BIT_write_enable_temp;
+					when "01" =>
+						result_next <= result_ram_8bit_2;
+						ZPU_STACK_WRITE(2) <= zpu_8BIT_write_enable_temp;
+					when "10" =>
+						result_next <= result_ram_8bit_1;					
+						ZPU_STACK_WRITE(1) <= zpu_8BIT_write_enable_temp;					
+					when "11" =>
+						result_next <= result_ram_8bit_0;
+						ZPU_STACK_WRITE(0) <= zpu_8BIT_write_enable_temp;
+					end case;
+				else
+					result_next <= result_ram;
+					ZPU_STACK_WRITE <= (others=>zpu_write_temp);					
+				end if;
+				ZPU_MEM_BUSY <= '1';				
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);
+			when "10110"|"10010" =>
+				result_next <= result_config;
+				ZPU_MEM_BUSY <= '1';
+				ZPU_config_write <= ZPU_WRITE_temp; 
+				zpu_addr_next <= std_logic_vector(zpu_addr_unsigned);				
+			when "00001"|"00011"|"00101"|"00111"|"01001"|"01011"|"01101"|"01111"|
+				  "10001"|"10011"|"10101"|"10111"|"11001"|"11011"|"11101"|"11111" =>
+				ZPU_MEM_BUSY <= not(memORY_READY_reg) or pause;
+				zpu_memory_fetch_pending_next <= not(memORY_READY);
+			when others =>
+				-- keep
+		end case;
+	end process;
+
+	zpu_di_next <= zpu_di;
+	process(result_reg, zpu_di_reg, zpu_rom_di, zpu_ram_di, zpu_config_di, zpu_sector_di)
+	begin
+		zpu_di_use <= (others=>'0');
+		case result_reg is 
+			when result_external =>
+				zpu_di_use <= zpu_di_reg;
+			when result_external_special =>
+				zpu_di_use(7 downto 0) <= zpu_di_reg(15 downto 8);				
+			when result_rom =>
+				zpu_di_use <= zpu_rom_DI;
+			when result_rom_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(7 downto 0);
+			when result_rom_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(15 downto 8);
+			when result_rom_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(23 downto 16);
+			when result_rom_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_rom_DI(31 downto 24);				
+			when result_ram =>
+				zpu_di_use <= zpu_ram_DI;
+			when result_ram_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(7 downto 0);
+			when result_ram_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(15 downto 8);
+			when result_ram_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(23 downto 16);
+			when result_ram_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_ram_DI(31 downto 24);				
+			when result_sec =>
+				zpu_di_use <= zpu_sector_DI;
+			when result_sec_8bit_0 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(7 downto 0);
+			when result_sec_8bit_1 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(15 downto 8);
+			when result_sec_8bit_2 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(23 downto 16);
+			when result_sec_8bit_3 =>
+				zpu_di_use(7 downto 0) <= zpu_sector_DI(31 downto 24);								
+			when result_config =>
+				zpu_di_use <= zpu_config_di;
+			when others =>
+				-- nothing
+		end case;
+	end process;
+
+-- zpu itself
+	--zpu_enable <= enable and not(pause);
+	zpu_enable <= '1'; -- does nothing useful...
+	
+myzpu: ZPUMediumCore
+	port map (clk_i=>clk, reset_i=>reset,enable_i=>zpu_enable,break_o=>zpu_break,dbg_o=>zpu_debug,mem_busy_i=>ZPU_MEM_BUSY,
+	data_i=>zpu_di_unsigned,data_o=>zpu_do_unsigned,addr_o=>zpu_addr_unsigned,write_en_o=>zpu_32bit_write_enable_temp,read_en_o=>zpu_32bit_read_enable_temp,
+	byte_read_o=>zpu_8bit_read_enable_temp, byte_write_o=>zpu_8bit_write_enable_temp,short_write_o=>zpu_16bit_write_enable_temp);
+	
+	zpu_di_unsigned <= unsigned(zpu_di_use);
+	zpu_do <= std_logic_vector(zpu_do_unsigned);
+	ZPU_ADDR_ROM_RAM <= zpu_addr_next;
+	ZPU_ADDR_FETCH <= zpu_addr_reg;
+		
+	zpu_read_enable <= zpu_read_reg;
+	zpu_8bit_write_enable <= zpu_8bit_write_enable_reg;
+	zpu_16bit_write_enable <= zpu_16bit_write_enable_reg;
+	zpu_32bit_write_enable <= zpu_32bit_write_enable_reg;
+
+end sticky;
Index: unmerged/core/mist/zpu_ram.vhd
===================================================================
--- unmerged/core/mist/zpu_ram.vhd	(nonexistent)
+++ unmerged/core/mist/zpu_ram.vhd	(revision 1)
@@ -0,0 +1,181 @@
+-- megafunction wizard: %RAM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: zpu_ram.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 12.1 Build 243 01/31/2013 SP 1.33 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2012 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY zpu_ram IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		wren		: IN STD_LOGIC ;
+		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+END zpu_ram;
+
+
+ARCHITECTURE SYN OF zpu_ram IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+
+
+
+	COMPONENT altsyncram
+	GENERIC (
+		clock_enable_input_a		: STRING;
+		clock_enable_output_a		: STRING;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		numwords_a		: NATURAL;
+		operation_mode		: STRING;
+		outdata_aclr_a		: STRING;
+		outdata_reg_a		: STRING;
+		power_up_uninitialized		: STRING;
+		widthad_a		: NATURAL;
+		width_a		: NATURAL;
+		width_byteena_a		: NATURAL
+	);
+	PORT (
+			address_a	: IN STD_LOGIC_VECTOR (9 DOWNTO 0);
+			clock0	: IN STD_LOGIC ;
+			data_a	: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+			wren_a	: IN STD_LOGIC ;
+			q_a	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+	);
+	END COMPONENT;
+
+BEGIN
+	q    <= sub_wire0(7 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		intended_device_family => "Cyclone II",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 1024,
+		operation_mode => "SINGLE_PORT",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "UNREGISTERED",
+		power_up_uninitialized => "FALSE",
+		widthad_a => 10,
+		width_a => 8,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		data_a => data,
+		wren_a => wren,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrData NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: DataBusSeparated NUMERIC "1"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING ""
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegData NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "1"
+-- Retrieval info: PRIVATE: WRCONTROL_ACLR_A NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "10"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "8"
+-- Retrieval info: PRIVATE: rden NUMERIC "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "1024"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "10"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 10 0 INPUT NODEFVAL "address[9..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
+-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT NODEFVAL "wren"
+-- Retrieval info: CONNECT: @address_a 0 0 10 0 address 0 0 10 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @data_a 0 0 8 0 data 0 0 8 0
+-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram.bsf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL zpu_ram_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
Index: unmerged/core/mist/zpupkg.vhd
===================================================================
--- unmerged/core/mist/zpupkg.vhd	(nonexistent)
+++ unmerged/core/mist/zpupkg.vhd	(revision 1)
@@ -0,0 +1,292 @@
+------------------------------------------------------------------------------
+----                                                                      ----
+----  ZPU Package                                                         ----
+----                                                                      ----
+----  http://www.opencores.org/                                           ----
+----                                                                      ----
+----  Description:                                                        ----
+----  ZPU is a 32 bits small stack cpu. This is the package.              ----
+----                                                                      ----
+----  To Do:                                                              ----
+----  -                                                                   ----
+----                                                                      ----
+----  Author:                                                             ----
+----    - Øyvind Harboe, oyvind.harboe zylin.com                          ----
+----    - Salvador E. Tropea, salvador inti.gob.ar                        ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Copyright (c) 2008 Øyvind Harboe <oyvind.harboe zylin.com>           ----
+---- Copyright (c) 2008 Salvador E. Tropea <salvador inti.gob.ar>         ----
+---- Copyright (c) 2008 Instituto Nacional de Tecnología Industrial       ----
+----                                                                      ----
+---- Distributed under the BSD license                                    ----
+----                                                                      ----
+------------------------------------------------------------------------------
+----                                                                      ----
+---- Design unit:      zpupkg, UART (Package)                             ----
+---- File name:        zpu_medium.vhdl                                    ----
+---- Note:             None                                               ----
+---- Limitations:      None known                                         ----
+---- Errors:           None known                                         ----
+---- Library:          zpu                                                ----
+---- Dependencies:     IEEE.std_logic_1164                                ----
+----                   IEEE.numeric_std                                   ----
+---- Target FPGA:      Spartan 3 (XC3S400-4-FT256)                        ----
+---- Language:         VHDL                                               ----
+---- Wishbone:         No                                                 ----
+---- Synthesis tools:  Xilinx Release 9.2.03i - xst J.39                  ----
+---- Simulation tools: GHDL [Sokcho edition] (0.2x)                       ----
+---- Text editor:      SETEdit 0.5.x                                      ----
+----                                                                      ----
+------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package zpupkg is
+   constant OPCODE_W : integer:=8;
+
+   -- Debug structure, currently only for the trace module
+   type zpu_dbgo_t is record
+      b_inst : std_logic;
+      opcode : unsigned(OPCODE_W-1 downto 0);
+      pc     : unsigned(31 downto 0);
+      sp     : unsigned(31 downto 0);
+      stk_a  : unsigned(31 downto 0);
+      stk_b  : unsigned(31 downto 0);
+   end record;
+
+   component Trace is
+      generic(
+         LOG_FILE   : string:="trace.txt"; -- Name of the trace file
+         ADDR_W     : integer:=16;  -- Address width
+         WORD_SIZE  : integer:=32); -- 16/32
+      port(
+         clk_i      : in std_logic;
+         dbg_i      : in zpu_dbgo_t;
+         stop_i     : in std_logic;
+         busy_i     : in std_logic
+         );
+   end component Trace;
+
+   component ZPUSmallCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'); -- Value used to fill the unsused bits
+      port(
+         clk_i        : in  std_logic; -- System Clock
+         reset_i      : in  std_logic; -- Synchronous Reset
+         interrupt_i  : in  std_logic; -- Interrupt
+         break_o      : out std_logic; -- Breakpoint opcode executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- BRAM (text, data, bss and stack)
+         a_we_o       : out std_logic; -- BRAM A port Write Enable
+         a_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM A Address
+         a_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM A port
+         a_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM A port
+         b_we_o       : out std_logic; -- BRAM B port Write Enable
+         b_addr_o     : out unsigned(MEM_W-1 downto WORD_SIZE/16):=(others => '0'); -- BRAM B Address
+         b_o          : out unsigned(WORD_SIZE-1 downto 0):=(others => '0'); -- Data to BRAM B port
+         b_i          : in  unsigned(WORD_SIZE-1 downto 0); -- Data from BRAM B port
+         -- Memory mapped I/O
+         mem_busy_i   : in  std_logic;
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0);
+         data_o       : out unsigned(WORD_SIZE-1 downto 0);
+         addr_o       : out unsigned(ADDR_W-1 downto 0);
+         write_en_o   : out std_logic;
+         read_en_o    : out std_logic);
+   end component ZPUSmallCore;
+
+   component ZPUMediumCore is
+      generic(
+         WORD_SIZE    : integer:=32;  -- Data width 16/32
+         ADDR_W       : integer:=16;  -- Total address space width (incl. I/O)
+         MEM_W        : integer:=15;  -- Memory (prog+data+stack) width
+         D_CARE_VAL   : std_logic:='X'; -- Value used to fill the unsused bits
+         MULT_PIPE    : boolean:=false; -- Pipeline multiplication
+         BINOP_PIPE   : integer range 0 to 2:=0; -- Pipeline binary operations (-, =, < and <=)
+         ENA_LEVEL0   : boolean:=true;  -- eq, loadb, neqbranch and pushspadd
+         ENA_LEVEL1   : boolean:=true;  -- lessthan, ulessthan, mult, storeb, callpcrel and sub
+         ENA_LEVEL2   : boolean:=false; -- lessthanorequal, ulessthanorequal, call and poppcrel
+         ENA_LSHR     : boolean:=true;  -- lshiftright
+         ENA_IDLE     : boolean:=false; -- Enable the enable_i input
+         FAST_FETCH   : boolean:=true); -- Merge the st_fetch with the st_execute states
+      port(
+         clk_i        : in  std_logic; -- CPU Clock
+         reset_i      : in  std_logic; -- Sync Reset
+         enable_i     : in  std_logic; -- Hold the CPU (after reset)
+         break_o      : out std_logic; -- Break instruction executed
+         dbg_o        : out zpu_dbgo_t; -- Debug outputs (i.e. trace log)
+         -- Memory interface
+         mem_busy_i   : in  std_logic; -- Memory is busy
+         data_i       : in  unsigned(WORD_SIZE-1 downto 0); -- Data from mem
+         data_o       : out unsigned(WORD_SIZE-1 downto 0); -- Data to mem
+         addr_o       : out unsigned(ADDR_W-1 downto 0); -- Memory address
+         write_en_o   : out std_logic;  -- Memory write enable
+         read_en_o    : out std_logic); -- Memory read enable
+   end component ZPUMediumCore;
+
+   component Timer is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned(0 downto 0);
+         data_o   : out unsigned(31 downto 0));
+   end component Timer;
+
+   component gpio is
+      port(
+         clk_i    : in  std_logic;
+         reset_i  : in  std_logic;
+         --
+         we_i     : in  std_logic;
+         data_i   : in  unsigned(31 downto 0);
+         addr_i   : in  unsigned( 0 downto 0);
+         data_o   : out unsigned(31 downto 0);
+         --
+         port_in  : in  std_logic_vector(31 downto 0);
+         port_out : out std_logic_vector(31 downto 0);
+         port_dir : out std_logic_vector(31 downto 0)
+         );
+   end component gpio;
+
+
+   component ZPUPhiIO is
+      generic(
+         BRDIVISOR : positive:=1;   -- Baud rate divisor i.e. br_clk/9600/4
+         ENA_LOG   : boolean:=true; -- Enable log
+         LOG_FILE  : string:="log.txt"); -- Name for the log file
+      port(
+         clk_i      : in  std_logic; -- System Clock
+         reset_i    : in  std_logic; -- Synchronous Reset
+         busy_o     : out std_logic; -- I/O is busy
+         we_i       : in  std_logic; -- Write Enable
+         re_i       : in  std_logic; -- Read Enable
+         data_i     : in  unsigned(31 downto 0);
+         data_o     : out unsigned(31 downto 0);
+         addr_i     : in  unsigned(2  downto 0); -- Address bits 4-2
+         --
+         rs232_rx_i : in  std_logic;  -- UART Rx input
+         rs232_tx_o : out std_logic;  -- UART Tx output
+         br_clk_i   : in  std_logic;  -- UART base clock (enable)
+         --
+         gpio_in    : in  std_logic_vector(31 downto 0);
+         gpio_out   : out std_logic_vector(31 downto 0);
+         gpio_dir   : out std_logic_vector(31 downto 0)
+         );
+   end component ZPUPhiIO;
+
+   -- Opcode decode constants
+   -- Note: these are the basic opcodes, always implemented using hardware.
+   constant OPCODE_IM        : unsigned(7 downto 7):="1";
+   constant OPCODE_STORESP   : unsigned(7 downto 5):="010";
+   constant OPCODE_LOADSP    : unsigned(7 downto 5):="011";
+   constant OPCODE_EMULATE   : unsigned(7 downto 5):="001";
+   constant OPCODE_ADDSP     : unsigned(7 downto 4):="0001";
+   constant OPCODE_SHORT     : unsigned(7 downto 4):="0000";
+   
+   constant OPCODE_BREAK     : unsigned(3 downto 0):="0000";
+   constant OPCODE_SHIFTLEFT : unsigned(3 downto 0):="0001";
+   constant OPCODE_PUSHSP    : unsigned(3 downto 0):="0010";
+   constant OPCODE_PUSHINT   : unsigned(3 downto 0):="0011";
+   
+   constant OPCODE_POPPC     : unsigned(3 downto 0):="0100";
+   constant OPCODE_ADD       : unsigned(3 downto 0):="0101";
+   constant OPCODE_AND       : unsigned(3 downto 0):="0110";
+   constant OPCODE_OR        : unsigned(3 downto 0):="0111";
+   
+   constant OPCODE_LOAD      : unsigned(3 downto 0):="1000";
+   constant OPCODE_NOT       : unsigned(3 downto 0):="1001";
+   constant OPCODE_FLIP      : unsigned(3 downto 0):="1010";
+   constant OPCODE_NOP       : unsigned(3 downto 0):="1011";
+   
+   constant OPCODE_STORE     : unsigned(3 downto 0):="1100";
+   constant OPCODE_POPSP     : unsigned(3 downto 0):="1101";
+   constant OPCODE_COMPARE   : unsigned(3 downto 0):="1110";
+   constant OPCODE_POPINT    : unsigned(3 downto 0):="1111";
+
+   -- The following instructions are emulated in the small version and
+   -- implemented as hardware in the full version.
+   -- The constants correpond to the "emulated" instruction number.
+
+   -- Enabled by the ENA_LEVEL0 generic:
+   constant OPCODE_EQ               : unsigned(5 downto 0):=to_unsigned(46,6);
+   constant OPCODE_LOADB            : unsigned(5 downto 0):=to_unsigned(51,6);
+   constant OPCODE_NEQBRANCH        : unsigned(5 downto 0):=to_unsigned(56,6);
+   constant OPCODE_PUSHSPADD        : unsigned(5 downto 0):=to_unsigned(61,6);
+   -- Enabled by the ENA_LEVEL1 generic:
+   constant OPCODE_LESSTHAN         : unsigned(5 downto 0):=to_unsigned(36,6);
+   constant OPCODE_ULESSTHAN        : unsigned(5 downto 0):=to_unsigned(38,6);
+   constant OPCODE_MULT             : unsigned(5 downto 0):=to_unsigned(41,6);
+   constant OPCODE_STOREB           : unsigned(5 downto 0):=to_unsigned(52,6);
+   constant OPCODE_CALLPCREL        : unsigned(5 downto 0):=to_unsigned(63,6);
+   constant OPCODE_SUB              : unsigned(5 downto 0):=to_unsigned(49,6);
+   -- Enabled by the ENA_LEVEL2 generic:
+   constant OPCODE_LESSTHANOREQUAL  : unsigned(5 downto 0):=to_unsigned(37,6);
+   constant OPCODE_ULESSTHANOREQUAL : unsigned(5 downto 0):=to_unsigned(39,6);
+   constant OPCODE_CALL             : unsigned(5 downto 0):=to_unsigned(45,6);
+   constant OPCODE_POPPCREL         : unsigned(5 downto 0):=to_unsigned(57,6);
+   -- Enabled by the ENA_LSHR generic:
+   constant OPCODE_LSHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(42,6);
+   -- The following opcodes are always emulated.
+   constant OPCODE_LOADH            : unsigned(5 downto 0):=to_unsigned(34,6);
+   constant OPCODE_STOREH           : unsigned(5 downto 0):=to_unsigned(35,6);
+   constant OPCODE_ASHIFTLEFT       : unsigned(5 downto 0):=to_unsigned(43,6);
+   constant OPCODE_ASHIFTRIGHT      : unsigned(5 downto 0):=to_unsigned(44,6);
+   constant OPCODE_NEQ              : unsigned(5 downto 0):=to_unsigned(47,6);
+   constant OPCODE_NEG              : unsigned(5 downto 0):=to_unsigned(48,6);
+   constant OPCODE_XOR              : unsigned(5 downto 0):=to_unsigned(50,6);
+   constant OPCODE_DIV              : unsigned(5 downto 0):=to_unsigned(53,6);
+   constant OPCODE_MOD              : unsigned(5 downto 0):=to_unsigned(54,6);
+   constant OPCODE_EQBRANCH         : unsigned(5 downto 0):=to_unsigned(55,6);
+   constant OPCODE_CONFIG           : unsigned(5 downto 0):=to_unsigned(58,6);
+   constant OPCODE_PUSHPC           : unsigned(5 downto 0):=to_unsigned(59,6);
+end package zpupkg;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package UART is
+   ----------------------
+   -- Very simple UART --
+   ----------------------
+   component RxUnit is
+      port(
+         clk_i    : in  std_logic;  -- System clock signal
+         reset_i  : in  std_logic;  -- Reset input (sync)
+         enable_i : in  std_logic;  -- Enable input (rate*4)
+         read_i   : in  std_logic;  -- Received Byte Read
+         rxd_i    : in  std_logic;  -- RS-232 data input
+         rxav_o   : out std_logic;  -- Byte available
+         datao_o  : out std_logic_vector(7 downto 0)); -- Byte received
+   end component RxUnit;
+
+   component TxUnit is
+     port (
+        clk_i    : in  std_logic;  -- Clock signal
+        reset_i  : in  std_logic;  -- Reset input
+        enable_i : in  std_logic;  -- Enable input
+        load_i   : in  std_logic;  -- Load input
+        txd_o    : out std_logic;  -- RS-232 data output
+        busy_o   : out std_logic;  -- Tx Busy
+        datai_i  : in  std_logic_vector(7 downto 0)); -- Byte to transmit
+   end component TxUnit;
+
+   component BRGen is
+     generic(
+        COUNT : integer range 0 to 65535);-- Count revolution
+     port (
+        clk_i   : in  std_logic;  -- Clock
+        reset_i : in  std_logic;  -- Reset input
+        ce_i    : in  std_logic;  -- Chip Enable
+        o_o     : out std_logic); -- Output
+   end component BRGen;
+end package UART;
+
Index: unmerged/core_merge/mcc_deplay_changes_summary
===================================================================
Index: unmerged/zpu_firmware/de1_old/HelloTinyROM.elf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/HelloTinyROM.elf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/de1_old/a.out
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/a.out
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/de1_old/chksum.c
===================================================================
--- unmerged/zpu_firmware/de1_old/chksum.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/chksum.c	(revision 1)
@@ -0,0 +1,40 @@
+unsigned char abuffer[] = {
+0x00,0x03,0x00,0x07,0x14,0x07,0x4c,0x14,0x07,0x74,0x0d,0x00,0x00,0xa9,0x46,0x8d
+,0xc6,0x02,0xd0,0xfe,0xa0,0x00,0xa9,0x6b,0x91,0x58,0x20,0xd9,0x07,0xb0,0xee,0x20
+,0xc4,0x07,0xad,0x7a,0x08,0x0d,0x76,0x08,0xd0,0xe3,0xa5,0x80,0x8d,0xe0,0x02,0xa5
+,0x81,0x8d,0xe1,0x02,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20,0xeb,0x07,0xb0
+,0xcc,0xa0,0x00,0x91,0x80,0xa5,0x80,0xc5,0x82,0xd0,0x06,0xa5,0x81,0xc5,0x83,0xf0
+,0x08,0xe6,0x80,0xd0,0x02,0xe6,0x81,0xd0,0xe3,0xad,0x76,0x08,0xd0,0xaf,0xad,0xe2
+,0x02,0x8d,0x70,0x07,0x0d,0xe3,0x02,0xf0,0x0e,0xad,0xe3,0x02,0x8d,0x71,0x07,0x20
+,0xff,0xff,0xad,0x7a,0x08,0xd0,0x13,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20
+};
+
+
+unsigned char buffer[] = {
+0x98,0xff,0xe0,0x00
+};
+
+typedef unsigned short u16;
+typedef unsigned char u08;
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+        u16 i;
+        u08 sumo,sum;
+        sum=sumo=0;
+        for(i=0;i<len;i++)
+        {
+                sum+=buffer[i];
+                if(sum<sumo) sum++;
+                sumo = sum;
+        }
+        return sum;
+}
+
+int main(void)
+{
+	int res = get_checksum(buffer,sizeof(buffer));
+	printf("%x %d\n",res,sizeof(buffer));
+	return 0;
+}
+
Index: unmerged/core_merge/mcc_deplay_changes
===================================================================
--- unmerged/core_merge/mcc_deplay_changes	(nonexistent)
+++ unmerged/core_merge/mcc_deplay_changes	(revision 1)
@@ -0,0 +1,2555 @@
+diff -ur mcc216/address_decoder.vhdl ../../../atari_800xl/common/a8core/address_decoder.vhdl
+--- mcc216/address_decoder.vhdl	2014-01-30 21:32:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/address_decoder.vhdl	2014-03-23 08:03:29.673482072 +0000
+@@ -59,9 +59,11 @@
+ 	
+ 	reset_n : in std_logic;
+ 	
+-	rom_select : in std_logic_vector(1 downto 0);
++	rom_select : in std_logic_vector(5 downto 0);
++	cart_select : in std_logic_vector(6 downto 0);
++	cart_activate : in std_logic;
+ 	
+-	ram_select : in std_logic_vector(1 downto 0);
++	ram_select : in std_logic_vector(2 downto 0);
+ 	
+ 	CART_RD4 : in std_logic;
+ 	CART_RD5 : in std_logic;
+@@ -88,7 +90,8 @@
+ 	PIA_RD_ENABLE : OUT STD_LOGIC; -- ... except PIA takes action on reads!
+ 	RAM_WR_ENABLE : OUT STD_LOGIC;	
+ 	PBI_WR_ENABLE : OUT STD_LOGIC;
+-	
++	D6_WR_ENABLE : OUT STD_LOGIC;
++ 	
+ 	-- ROM and RAM have extended address busses to allow for bank switching etc.
+ 	ROM_ADDR : OUT STD_LOGIC_VECTOR(21 downto 0);
+ 	RAM_ADDR : OUT STD_LOGIC_VECTOR(18 downto 0);
+@@ -147,12 +150,16 @@
+ 	signal notify_cpu : std_logic;
+ 	signal start_request : std_logic;
+ 	
++	signal extended_access_addr : std_logic;
+ 	signal extended_access_cpu_or_antic : std_logic;
+ 	signal extended_access_antic : std_logic;
+ 	signal extended_access_cpu: std_logic; -- 130XE and compy shop switch antic seperately
+ 	
+ 	signal extended_access_either: std_logic; -- RAMBO switches both together using CPU bit
+ 
++	signal extended_self_test : std_logic;
++	signal extended_bank : std_logic_vector(8 downto 0); -- ONLY "000" - "103" valid...
++	
+ 	-- even though we have 3 targets (flash, ram, rom) and 3 masters, only allow access to one a a time - simpler.
+ 	signal state_next : std_logic_vector(1 downto 0);
+ 	signal state_reg : std_logic_vector(1 downto 0);
+@@ -173,6 +180,19 @@
+ 	signal fetch_wait_next : std_logic_vector(8 downto 0);
+ 	signal fetch_wait_reg : std_logic_vector(8 downto 0);	
+ 	
++	signal rom_in_ram : std_logic;
++	
++	signal antic_fetch_real_next : std_logic;
++	signal antic_fetch_real_reg : std_logic;
++	signal cpu_fetch_real_next : std_logic;
++	signal cpu_fetch_real_reg : std_logic;
++
++	signal SDRAM_CART_ADDR   : std_logic_vector(22 downto 0);
++	signal SDRAM_BASIC_ROM_ADDR  : std_logic_vector(22 downto 0);
++	signal SDRAM_OS_ROM_ADDR : std_logic_vector(22 downto 0);
++	
++	signal sdram_only_bank : std_logic;
++	
+ BEGIN
+ 		-- register
+ 	process(clk,reset_n)
+@@ -187,7 +207,10 @@
+ 			data_write_reg <= (others=> '0');
+ 			--sdram_request_reg <= '0';
+ 			fetch_wait_reg <= (others=>'0');
+-		elsif (clk'event and clk='1') then
++
++			cpu_fetch_real_reg <= '0';
++			antic_fetch_real_reg <= '0';	
++	elsif (clk'event and clk='1') then
+ 			addr_reg <= addr_next;
+ 			state_reg <= state_next;
+ 			width_8bit_reg <= width_8bit_next;
+@@ -197,6 +220,9 @@
+ 			data_write_reg <= data_WRITE_next;
+ 			--sdram_request_reg <= sdram_request_next;
+ 			fetch_wait_reg <= fetch_wait_next;
++			
++			cpu_fetch_real_reg <= cpu_fetch_real_next;
++			antic_fetch_real_reg <= antic_fetch_real_next;
+ 		end if;
+ 	end process;
+ 	
+@@ -219,7 +245,7 @@
+ 	
+ 	-- state machine impl
+ 	fetch_priority <= ANTIC_FETCH&ZPU_FETCH&CPU_FETCH;
+-	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA)
++	process(fetch_wait_reg, state_reg, addr_reg, data_write_reg, width_8bit_reg, width_16bit_reg, width_32bit_reg, write_enable_reg, fetch_priority, antic_addr, zpu_addr, cpu_addr, request_complete, zpu_8bit_write_enable,zpu_16bit_write_enable,zpu_32bit_write_enable,zpu_read_enable, cpu_write_n, CPU_WRITE_DATA, ZPU_WRITE_DATA, antic_fetch_real_reg, cpu_fetch_real_reg)
+ 	begin
+ 		start_request <= '0';
+ 		notify_antic <= '0';
+@@ -235,6 +261,9 @@
+ 		width_32bit_next <= width_32bit_reg;		
+ 		write_enable_next <= write_enable_reg;
+ 		
++		antic_fetch_real_next <= antic_fetch_real_reg;
++		cpu_fetch_real_next <= cpu_fetch_real_reg;
++		
+ 		case state_reg is
+ 			when state_idle =>
+ 				fetch_wait_next <= (others=>'0');
+@@ -255,6 +284,7 @@
+ 					else
+ 						state_next <= state_waiting_antic;
+ 					end if;
++					antic_fetch_real_next <= '1';
+ 				when "010"|"011" => -- zpu wins (zpu usually accesses own ROM memory - this is NOT a zpu_fetch)
+ 					start_request <= '1';
+ 					addr_next <= zpu_ADDR;
+@@ -282,8 +312,11 @@
+ 					else
+ 						state_next <= state_waiting_cpu;
+ 					end if;
++					cpu_fetch_real_next <= '1';
+ 				when "000" =>
+ 					-- no requests
++				when others =>
++					-- nop
+ 				end case;
+ 			when state_waiting_antic =>
+ 				if (request_complete = '1') then
+@@ -300,6 +333,8 @@
+ 					notify_cpu <= '1';
+ 					state_next <= state_idle;
+ 				end if;				
++			when others =>
++				-- NOP
+ 		end case;
+ 	end process;
+ 	
+@@ -312,7 +347,7 @@
+ 		
+ 	SDRAM_REQUEST <= sdram_chip_select;
+ 	--SDRAM_REQUEST <= sdram_request_next;
+-	SDRAM_REFRESH <= fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
++	SDRAM_REFRESH <= '0'; --fetch_wait_reg(7); -- TODO, BROKEN! antic_refresh;
+ 	SDRAM_READ_EN <= not(write_enable_next);
+ 	SDRAM_WRITE_EN <= write_enable_next;
+ 	
+@@ -327,11 +362,78 @@
+ 	--sdram_request_next <= sdram_request_reg xor sdram_chip_select;	
+ 	
+ 	-- Calculate which memory area to use
++	extended_access_addr <= addr_next(14) and not(addr_next(15)); --0x4000 to 0x7fff
+ 	extended_access_cpu_or_antic <= extended_access_antic or extended_access_cpu;
+-	extended_access_antic <= (antic_fetch and not(portb(5)));
+-	extended_access_cpu <= not(antic_fetch) and not(portb(4));
++	extended_access_antic <= (extended_access_addr and antic_fetch_real_next and not(portb(5)));
++	extended_access_cpu <= (extended_access_addr and cpu_fetch_real_next and not(portb(4)));
++	extended_access_either <= extended_access_addr and not(portb(4));
++	sdram_only_bank <= or_reduce(extended_bank(8 downto 5));
++	
++	process(extended_access_cpu_or_antic,extended_access_either,extended_access_addr,addr_next,ram_select,portb)
++	begin	
++		extended_bank <= "0000000"&addr_next(15 downto 14);
++		extended_self_test <= '1';
++		
++		case ram_select is
++			when "000" => -- 64k
++				-- default
++			when "001" => -- 128k			
++				if (extended_access_cpu_or_antic='1') then
++					extended_bank(2 downto 0) <= '1'&portb(3 downto 2);
++				end if;
++			when "010" => -- 320k compy shop
++				if (extended_access_cpu_or_antic='1') then
++					extended_bank(4 downto 0) <= '1'&portb(7 downto 6)&portb(3 downto 2);
++					extended_self_test <= '0';
++				end if;
++			when "011" => -- 320k rambo
++				if (extended_access_either='1')then
++					extended_bank(4 downto 0) <= '1'&portb(6 downto 5)&portb(3 downto 2);
++				end if;
++			when "100" => -- 576k compy shop
++				if (extended_access_cpu_or_antic='1') then
++					extended_bank(4 downto 0) <= portb(7 downto 6)&portb(3 downto 1);
++					extended_bank(5) <= not(or_reduce(portb(7 downto 6)&portb(3)));
++					extended_self_test <= '0';
++				end if;
++			when "101" => -- 576k rambo
++				if (extended_access_either='1') then
++					extended_bank(4 downto 0) <= portb(6 downto 5)&portb(3 downto 1);
++					extended_bank(5) <= not(or_reduce(portb(6 downto 5)&portb(3)));
++				end if;
++			when "110" => -- 1088k rambo
++				if (extended_access_either='1') then
++					extended_bank(5 downto 0) <= portb(7 downto 5)&portb(3 downto 1);
++					extended_bank(6) <= not(or_reduce(portb(7 downto 5)&portb(3)));
++					extended_self_test <= '0';
++				end if;
++			when "111" => -- 4MB!	
++				if (extended_access_addr='1') then
++					extended_bank(7 downto 0) <= portb(7 downto 0);				
++					extended_bank(8) <= not(or_reduce(portb(7 downto 2)));
++					extended_self_test <= and_reduce(portb(6 downto 4));	 -- which means self-test is in the middle of half the banks - euuugh, oh well!						
++				end if;
++			when others =>
++				-- TODO - portc!
++		end case;
++	end process;
++
+ 	
+-	extended_access_either <= not(portb(4));
++	-- SRAM memory map (512k)
++	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
++	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP)
++	-- SDRAM memory map (8MB)
++	-- base 64k RAM  - banks 0-3    "000 0000 1111 1111 1111 1111" (TOP)
++	-- to 512k RAM   - banks 4-31   "000 0111 1111 1111 1111 1111" (TOP) 
++	-- to 4MB RAM    - banks 32-255 "011 1111 1111 1111 1111 1111" (TOP)
++	-- +64k          - banks 256-259"100 0000 0000 1111 1111 1111" (TOP)
++	-- SCRATCH       - 4MB+64k-5MB
++	-- CARTS         -              "101 YYYY YYY0 0000 0000 0000" (BOT) - 2MB! 8kb banks
++	SDRAM_CART_ADDR      <= "101"&cart_select& "0000000000000";
++	-- BASIC/OS ROM  -              "111 XXXX XX00 0000 0000 0000" (BOT) (BASIC IN SLOT 0!), 2nd to last 512K				
++	SDRAM_BASIC_ROM_ADDR <= "111"&"000000"   &"00000000000000";
++	SDRAM_OS_ROM_ADDR    <= "111"&rom_select &"00000000000000";
++	-- SYSTEM        -              "111 1000 0000 0000 0000 0000" (BOT) - LAST 512K
+ 	
+   	process(
+ 		-- address and writing absolutely points us at a device
+@@ -341,7 +443,7 @@
+ 		portb, 
+ 		antic_fetch,
+ 		rom_select,
+-		extended_access_cpu_or_antic,extended_access_either,ram_select,cart_rd4,cart_rd5,
++		ram_select,cart_rd4,cart_rd5,
+ 		use_sdram,
+ 		
+ 		-- input data from n sources
+@@ -353,7 +455,14 @@
+ 		ram_request_complete,sdram_request_complete,rom_request_complete,cart_request_complete,
+ 		
+ 		-- on new access this is set - we must select the appropriate device - for this cycle only
+-		start_request
++		start_request,
++		
++		rom_in_ram,
++		
++		-- SDRAM base addresses
++		extended_self_test,extended_bank,sdram_only_bank,
++		SDRAM_BASIC_ROM_ADDR,SDRAM_CART_ADDR,SDRAM_OS_ROM_ADDR
++		
+ 	)
+ 	begin
+ 		MEMORY_DATA <= (others => '1');
+@@ -373,6 +482,7 @@
+ 		PIA_WR_ENABLE <= '0';
+ 		PIA_RD_ENABLE <= '0';
+ 		PBI_WR_ENABLE <= '0';
++		D6_WR_ENABLE <= '0';
+ 
+ 		RAM_WR_ENABLE <= write_enable_next;
+ 		SDRAM_WRITE_EN <= write_enable_next;		
+@@ -386,13 +496,27 @@
+ 		
+ 		ram_chip_select <= '0';
+ 		sdram_chip_select <= '0';
++		
++		rom_in_ram <= '1';
+ 
+ 	--	if (addr_next(23 downto 17) = "0000000" ) then -- bit 16 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+ 		if (or_reduce(addr_next(23 downto 18)) = '0' ) then -- bit 16,17 left out on purpose, so the Atari 64k is available as 64k-128k for zpu. The zpu has rom at 0-64k...
+ 
+-		RAM_ADDR(18 downto 16) <= "000";	
+-		SDRAM_ADDR(22 downto 16) <= "0000000";
+-	
++		SDRAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
++		SDRAM_ADDR(22 downto 14) <= extended_bank;
++		RAM_ADDR(13 downto 0) <= addr_next(13 downto 0);
++		RAM_ADDR(18 downto 14) <= extended_bank(4 downto 0);
++					
++		if ((use_sdram or sdram_only_bank)='1') then
++			MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++			sdram_chip_select <= start_request;
++			request_complete <= sdram_request_COMPLETE;														
++		else
++			MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
++			ram_chip_select <= start_request;
++			request_complete <= ram_request_COMPLETE;									
++		end if;
++		
+ 		case addr_next(15 downto 8) is 
+ 				-- GTIA
+ 				when X"D0" =>
+@@ -400,6 +524,8 @@
+ 					MEMORY_DATA(7 downto 0) <= GTIA_DATA;
+ 					MEMORY_DATA(15 downto 8) <= CACHE_GTIA_DATA;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';
+ 			
+ 				-- POKEY
+ 				when X"D2" =>				
+@@ -413,6 +539,8 @@
+ 						MEMORY_DATA(15 downto 8) <= CACHE_POKEY2_DATA;
+ 					end if;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';					
+ 
+ 				-- PIA
+ 				when X"D3" =>
+@@ -420,6 +548,8 @@
+ 					PIA_RD_ENABLE <= '1';
+ 					MEMORY_DATA(7 downto 0) <= PIA_DATA;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';					
+ 					
+ 				-- ANTIC
+ 				when X"D4" =>
+@@ -427,9 +557,13 @@
+ 					MEMORY_DATA(7 downto 0) <= ANTIC_DATA;
+ 					MEMORY_DATA(15 downto 8) <= CACHE_ANTIC_DATA;
+ 					request_complete <= '1';
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';					
+ 					
+ 				-- CART_CONFIG -- TODO - wait for n cycles (for now non-turbo mode should work?)
+ 				when X"D5" =>
++					sdram_chip_select <= '0';
++					ram_chip_select <= '0';				
+ 					if ((CART_RD4 or CART_RD5) = '1') then
+ 						PBI_WR_ENABLE <= write_enable_next;
+ 						MEMORY_DATA(7 downto 0) <= CART_ROM_DATA;
+@@ -441,92 +575,39 @@
+ 						request_complete <= '1';
+ 					end if;
+ 					
+-				-- XE RAM
+-				when 
+-					X"40"|X"41"|X"42"|X"43"|X"44"|X"45"|X"46"|X"47"|X"48"|X"49"|X"4A"|X"4B"|X"4C"|X"4D"|X"4E"|X"4F"
+-					|X"58"|X"59"|X"5A"|X"5B"|X"5C"|X"5D"|X"5E"|X"5F"
+-					|X"60"|X"61"|X"62"|X"63"|X"64"|X"65"|X"66"|X"67"|X"68"|X"69"|X"6A"|X"6B"|X"6C"|X"6D"|X"6E"|X"6F"
+-					|X"70"|X"71"|X"72"|X"73"|X"74"|X"75"|X"76"|X"77"|X"78"|X"79"|X"7A"|X"7B"|X"7C"|X"7D"|X"7E"|X"7F" =>
+-					
+-					if (use_sdram = '1') then
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-						sdram_chip_select <= start_request;
+-						request_complete <= sdram_request_COMPLETE;														
+-					else
+-						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-						ram_chip_select <= start_request;
+-						request_complete <= ram_request_COMPLETE;									
+-					end if;
+-					
+-					case ram_select is
+-						when "00" => -- 64k
+-							-- default
+-						when "01" => -- 128k					
+-							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+-							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+-						when "10" => -- 320k compy shop
+-							RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-							SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-						when "11" => -- 320k rambo
+-							RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-							SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-					end case;
+-					
++				when X"D6" =>
++					D6_WR_ENABLE <= write_enable_next;
++					-- TODO - should this still have RAM with covox here?
++										
+ 				-- SELF TEST ROM 0x5000->0x57ff and XE RAM
+ 				when 
+ 					X"50"|X"51"|X"52"|X"53"|X"54"|X"55"|X"56"|X"57" =>
+ 									
+-					if (portb(7) = '0' and portb(0) = '1') then
+-						--request_complete <= ROM_REQUEST_COMPLETE;
+-						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+-						--rom_request <= start_request;					
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++					if (portb(7) = '0' and portb(0) = '1' and extended_self_test = '1') then
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';	
++						
++						if (rom_in_ram = '1') then
++							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						else
++							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
++						end if;
+ 						
+ 						if (write_enable_next = '1') then
+ 							request_complete <= '1';
+ 						else
+-							request_complete <= sdram_request_COMPLETE;							
+-							sdram_chip_select <= start_request;							
++							if (rom_in_ram = '1') then
++								request_complete <= sdram_request_COMPLETE;							
++								sdram_chip_select <= start_request;							
++							else
++								request_complete <= rom_request_COMPLETE;							
++								rom_request <= start_request;															
++							end if;
+ 						end if;
+ 						--ROM_ADDR <= "000000"&"00010"&ADDR(10 downto 0); -- x01000 based 2k (i.e. self test is 4k in - usually under hardware regs)
+-						case rom_select is
+-							when "00" =>
+-								ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+-						    SDRAM_ADDR <="0010000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k
+-							when "01" =>
+-								ROM_ADDR <= "000000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k
+-							 SDRAM_ADDR <="0010000"&"01"&"010"&ADDR_next(10 downto 0); -- x05000 based 2k								
+-							when "10" =>
+-								ROM_ADDR <= "000000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k
+-							 SDRAM_ADDR <="0010000"&"10"&"010"&ADDR_next(10 downto 0); -- x09000 based 2k							
+-							when "11" =>
+-								ROM_ADDR <= "000001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)
+-							SDRAM_ADDR <= "0010001"&"00"&"010"&ADDR_next(10 downto 0); -- x11000 based 2k (0xd000 already taken by basic!)								
+-						end case;														
+-					else				
+-						if (use_sdram = '1') then
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-							sdram_chip_select <= start_request;
+-							request_complete <= sdram_request_COMPLETE;														
+-						else
+-							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-							ram_chip_select <= start_request;
+-							request_complete <= ram_request_COMPLETE;									
+-						end if;
+-						
+-						case ram_select is
+-							when "00" => -- 64k
+-								-- default
+-							when "01" => -- 128k					
+-								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);
+-								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&"00"&portb(3 downto 2);						
+-							when "10" => -- 320k compy shop
+-								RAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-								SDRAM_ADDR(18 downto 14) <= extended_access_cpu_or_antic&portb(7 downto 6)&portb(3 downto 2);
+-							when "11" => -- 320k rambo
+-								RAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-								SDRAM_ADDR(18 downto 14) <= extended_access_either&portb(6 downto 5)&portb(3 downto 2);				
+-						end case;
++						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
++						SDRAM_ADDR(13 downto 0) <= "010"&ADDR_next(10 downto 0);
++						ROM_ADDR <= "000000"&"00"&"010"&ADDR_next(10 downto 0); -- x01000 based 2k						
+ 					end if;
+ 				
+ 				-- 0x80 cart
+@@ -539,16 +620,8 @@
+ 						rom_request <= start_request;
+ 						CART_S4_n <= '0';
+ 						request_complete <= CART_REQUEST_COMPLETE;
+-					else
+-						if (use_sdram = '1') then
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-							sdram_chip_select <= start_request;
+-							request_complete <= sdram_request_COMPLETE;														
+-						else
+-							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-							ram_chip_select <= start_request;
+-							request_complete <= ram_request_COMPLETE;									
+-						end if;
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';							
+ 					end if;	
+ 			
+ 				-- 0xa0 cart (BASIC ROM 0xa000 - 0xbfff (8k))
+@@ -561,31 +634,35 @@
+ 						cart_request <= start_request;
+ 						CART_S5_n <= '0';
+ 						request_complete <= CART_REQUEST_COMPLETE;
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';													
+ 					else
+ 						if (portb(1) = '0') then
++							sdram_chip_select <= '0';
++							ram_chip_select <= '0';							
+ 							--request_complete <= ROM_REQUEST_COMPLETE;
+ 							--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+ 							--rom_request <= start_request;					
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++							if (rom_in_ram = '1') then
++								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++							else
++								MEMORY_DATA(7 downto 0) <= ROM_DATA;						
++							end if;
+ 							if (write_enable_next = '1') then
+ 								request_complete <= '1';
+ 							else
+-								request_complete <= sdram_request_COMPLETE;							
+-								sdram_chip_select <= start_request;								
++								if (rom_in_ram = '1') then
++									request_complete <= sdram_request_COMPLETE;							
++									sdram_chip_select <= start_request;							
++								else
++									request_complete <= rom_request_COMPLETE;							
++									rom_request <= start_request;															
++								end if;
+ 							end if;
+ 						
+ 							ROM_ADDR <= "000000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k
+-						 SDRAM_ADDR <="0010000"&"110"&ADDR_next(12 downto 0); -- x0C000 based 8k							
+-						else
+-							if (use_sdram = '1') then
+-								MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-								sdram_chip_select <= start_request;
+-								request_complete <= sdram_request_COMPLETE;														
+-							else
+-								MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-								ram_chip_select <= start_request;
+-								request_complete <= ram_request_COMPLETE;									
+-							end if;
++						 SDRAM_ADDR <= SDRAM_BASIC_ROM_ADDR;
++						 SDRAM_ADDR(12 downto 0) <= ADDR_next(12 downto 0); -- x0C000 based 8k							
+ 						end if;
+ 					end if;
+ 					
+@@ -598,56 +675,38 @@
+ 					|X"F0"|X"F1"|X"F2"|X"F3"|X"F4"|X"F5"|X"F6"|X"F7"|X"F8"|X"F9"|X"FA"|X"FB"|X"FC"|X"FD"|X"FE"|X"FF" =>
+ 					
+ 					if (portb(0) = '1') then
++						sdram_chip_select <= '0';
++						ram_chip_select <= '0';																		
+ 						--request_complete <= ROM_REQUEST_COMPLETE;
+ 						--MEMORY_DATA(7 downto 0) <= ROM_DATA;
+ 						--rom_request <= start_request;					
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						if (rom_in_ram = '1') then
++							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
++						else
++							MEMORY_DATA(7 downto 0) <= ROM_DATA;						
++						end if;
+ 						if (write_enable_next = '1') then
+ 							request_complete <= '1';
+ 						else
+-							request_complete <= sdram_request_COMPLETE;							
+-							sdram_chip_select <= start_request;							
++								if (rom_in_ram = '1') then
++									request_complete <= sdram_request_COMPLETE;							
++									sdram_chip_select <= start_request;							
++								else
++									request_complete <= rom_request_COMPLETE;							
++									rom_request <= start_request;															
++								end if;						
+ 						end if;																			
+ 
+-						case rom_select is
+-							when "00" =>
+-								ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+-							SDRAM_ADDR <= "0010000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
+-							when "01" =>
+-								ROM_ADDR <= "000000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+-							SDRAM_ADDR <= "0010000"&"01"&ADDR_next(13 downto 0); -- x04000 based 16k
+-							when "10" =>
+-								ROM_ADDR <= "000000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+-							SDRAM_ADDR <= "0010000"&"10"&ADDR_next(13 downto 0); -- x08000 based 16k
+-							when "11" =>
+-								ROM_ADDR <= "000001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+-							SDRAM_ADDR <= "0010001"&"00"&ADDR_next(13 downto 0); -- x10000 based 16k (0xc000 already taken by basic!)
+-						end case;
+-								
+-					else
+-						if (use_sdram = '1') then
+-							MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-							sdram_chip_select <= start_request;
+-							request_complete <= sdram_request_COMPLETE;														
+-						else
+-							MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-							ram_chip_select <= start_request;
+-							request_complete <= ram_request_COMPLETE;									
+-						end if;
++						ROM_ADDR <= "000000"&"00"&ADDR_next(13 downto 0); -- x00000 based 16k
++						SDRAM_ADDR <= SDRAM_OS_ROM_ADDR;
++						SDRAM_ADDR(13 downto 0) <= ADDR_next(13 downto 0);
+ 					end if;
+ 					
+ 				when others =>
+-					if (use_sdram = '1') then
+-						MEMORY_DATA(7 downto 0) <= SDRAM_DATA(7 downto 0);
+-						sdram_chip_select <= start_request;
+-						request_complete <= sdram_request_COMPLETE;														
+-					else
+-						MEMORY_DATA(7 downto 0) <= RAM_DATA(7 downto 0);
+-						ram_chip_select <= start_request;
+-						request_complete <= ram_request_COMPLETE;									
+-					end if;
+ 			end case;				
+ 		else		
++			sdram_chip_select <= '0';
++			ram_chip_select <= '0';													
+ 			case addr_next(23 downto 21) is			
+ 				when "000" =>				
+ 					-- internal area for zpu, never happens!
+@@ -668,6 +727,8 @@
+ 					sdram_chip_select <= start_request;
+ 					request_complete <= sdram_request_COMPLETE;	
+ 					SDRAM_ADDR <= addr_next(22 downto 0);				
++				when others =>
++					-- NOP
+ 			end case;
+ 		end if;
+ 		
+diff -ur mcc216/antic.vhdl ../../../atari_800xl/common/a8core/antic.vhdl
+--- mcc216/antic.vhdl	2014-01-18 11:23:43.000000000 +0000
++++ ../../../atari_800xl/common/a8core/antic.vhdl	2014-03-23 08:03:29.677482072 +0000
+@@ -47,7 +47,9 @@
+ 	refresh_out : out std_logic; -- used by sdram
+ 	
+ 	-- for debugging
+-	dma_clock_out : out std_logic
++	dma_clock_out : out std_logic;
++	hcount_out : out std_logic_vector(7 downto 0);
++	vcount_out : out std_logic_vector(8 downto 0)
+ );
+ END antic;
+ 
+@@ -475,10 +477,11 @@
+ 	signal colour_clock_selected : std_logic;
+ 	signal colour_clock_selected_highres : std_logic;
+ 	
+-	signal colour_clock_count_next : std_logic_vector(4 downto 0);
+-	signal colour_clock_count_reg : std_logic_vector(4 downto 0);
++	-- TODO - these should change with cycle_length...
++	signal colour_clock_count_next : std_logic_vector(3 downto 0);
++	signal colour_clock_count_reg : std_logic_vector(3 downto 0);
+ 	
+-	constant cycle_length : integer := 32;	
++	constant cycle_length : integer := 16;	
+ 	
+ 	signal memory_ready_both : std_logic;
+ 	
+@@ -655,34 +658,34 @@
+ 		colour_clock_count_next <= std_logic_vector(unsigned(colour_clock_count_reg) + 1);
+ 		
+ 		if (ANTIC_ENABLE_179 = '1') then -- resync...
+-			colour_clock_count_next <= "00001";
++			colour_clock_count_next <= "0001";
+ 		end if;
+ 
+ 		colour_clock_8x <= '1';
+ 		
+-		case colour_clock_count_reg(4 downto 0) is
+-		when "00000" =>
++		case colour_clock_count_reg(3 downto 0) is
++		when "0000" =>
+ 			colour_clock_half_x <= '1';
+ 			colour_clock_1x <= '1';
+ 			colour_clock_2x <= '1';
+ 			colour_clock_4x <= '1';
+-		when "00100" =>
++		when "0010" =>
+ 			colour_clock_4x <= '1';
+-		when "01000" =>
++		when "0100" =>
+ 			colour_clock_2x <= '1';			
+ 			colour_clock_4x <= '1';			
+-		when "01100" =>
++		when "0110" =>
+ 			colour_clock_4x <= '1';
+-		when "10000" =>			
++		when "1000" =>			
+ 			colour_clock_1x <= '1';
+ 			colour_clock_2x <= '1';
+ 			colour_clock_4x <= '1';
+-		when "10100" =>
++		when "1010" =>
+ 			colour_clock_4x <= '1';
+-		when "11000" =>
++		when "1100" =>
+ 			colour_clock_2x <= '1';			
+ 			colour_clock_4x <= '1';			
+-		when "11100" =>
++		when "1110" =>
+ 			colour_clock_4x <= '1';			
+ 		when others =>
+ 			-- nop
+@@ -1155,6 +1158,8 @@
+ 				medium_dma_s <= '1';
+ 			when fast_dma =>
+ 				fast_dma_s <= '1';
++			when others =>
++				-- nothing
+ 		end case;
+ 	end process;
+ 	
+@@ -1399,6 +1404,8 @@
+ 				shift_rate_next <= fast_shift;
+ 				shift_twobit_next <= '1';
+ 				twopixel_next <= '1';
++			when others =>
++				-- nothing
+ 				
+ 		end case;
+ 	end process;
+@@ -1591,6 +1598,8 @@
+ 						an_current <= "101";			
+ 					when "11" =>
+ 						an_current <= "11"&delay_display_shift_reg(4);										
++					when others =>
++						-- nop
+ 				end case;				
+ 			end if;
+ 			
+@@ -1604,6 +1613,8 @@
+ 						an_current <= "101";			
+ 					when "11" =>
+ 						an_current <= "110";										
++					when others =>
++						-- nop
+ 				end case;
+ 			end if;
+ 		else
+@@ -1819,6 +1830,9 @@
+ 	COLOUR_CLOCK_ORIGINAL_OUT <= colour_clock_1x;
+ 	COLOUR_CLOCK_OUT <= colour_clock_selected;
+ 	HIGHRES_COLOUR_CLOCK_OUT <= colour_clock_selected_highres;
++
++	vcount_out <= vcount_reg;
++	hcount_out <= hcount_reg;
+ 	
+ END vhdl;
+ 
+Only in mcc216/: atari800core.jdi
+Only in mcc216/: atari800core.qpf
+Only in mcc216/: atari800core.qsf
+Only in mcc216/: atari800core.qsf~
+Only in mcc216/: atari800core.qws
+Only in mcc216/: atari800core.sdc
+diff -ur mcc216/atari800core.vhd ../../../atari_800xl/common/a8core/atari800core.vhd
+--- mcc216/atari800core.vhd	2014-01-28 20:47:59.000000000 +0000
++++ ../../../atari_800xl/common/a8core/atari800core.vhd	2014-03-23 08:03:29.697482071 +0000
+@@ -1,4 +1,3 @@
+--- Copyright (C) 1991-2012 Altera Corporation
+ -- Your use of Altera Corporation's design tools, logic functions 
+ -- and other software and tools, and its AMPP partner logic 
+ -- functions, and any output files from any of the foregoing 
+@@ -18,49 +17,74 @@
+ 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all; 
++use IEEE.STD_LOGIC_MISC.all;
++use ieee.numeric_std.all;
+ 
+ LIBRARY work;
+ 
+ ENTITY atari800core IS 
+ 	PORT
+ 	(
+-		FPGA_CLK :  IN  STD_LOGIC;
+-		PS2K_CLK :  IN  STD_LOGIC;
+-		PS2K_DAT :  IN  STD_LOGIC;
+-		PS2M_CLK :  IN  STD_LOGIC;
+-		PS2M_DAT :  IN  STD_LOGIC;		
++		CLK :  IN  STD_LOGIC;
++		PLL_LOCKED: IN STD_LOGIC;
+ 
+ 		VGA_VS :  OUT  STD_LOGIC;
+ 		VGA_HS :  OUT  STD_LOGIC;
+-		VGA_B :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		VGA_G :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		VGA_R :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
++		VGA_B :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
++		VGA_G :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
++		VGA_R :  OUT  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		
+ 		JOY1_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
+ 		JOY2_n :  IN  STD_LOGIC_VECTOR(5 DOWNTO 0);
++
++		matrix_out : in std_logic_vector(15 downto 0);
++		matrix_in : out std_logic_vector(7 downto 0);
++		static_keys : in std_logic_vector(6 downto 0);
++		pause_key : in std_logic;
+ 		
+-		AUDIO_L : OUT std_logic;
+-		AUDIO_R : OUT std_logic;
++		AUDIO_L : OUT std_logic_vector(15 downto 0);
++		AUDIO_R : OUT std_logic_vector(15 downto 0);
++
++		SDRAM_REQUEST : OUT std_logic;
++		SDRAM_REQUEST_COMPLETE : IN std_logic;
++		SDRAM_READ_ENABLE : out STD_LOGIC;
++		SDRAM_WRITE_ENABLE : out std_logic;
++		SDRAM_DI : out std_logic_vector(31 downto 0);
++		SDRAM_ADDR : out STD_LOGIC_VECTOR(22 DOWNTO 0);
++		SDRAM_DO : in STD_LOGIC_VECTOR(31 DOWNTO 0);
++		SDRAM_WIDTH_8bit_ACCESS : out std_logic;
++		SDRAM_WIDTH_16bit_ACCESS : out std_logic;
++		SDRAM_WIDTH_32bit_ACCESS : out std_logic;
++
++		SIO_RXD : in std_logic;
++		SIO_TXD : out std_logic;
++		SIO_COMMAND_TX : out std_logic;
++
++   		ram_select : in std_logic_vector(2 downto 0);
++    		rom_select : in std_logic_vector(5 downto 0);
+ 
+-		SDRAM_BA :  OUT  STD_LOGIC_VECTOR(1 downto 0);
+-		SDRAM_CS_N :  OUT  STD_LOGIC;
+-		SDRAM_RAS_N :  OUT  STD_LOGIC;
+-		SDRAM_CAS_N :  OUT  STD_LOGIC;
+-		SDRAM_WE_N :  OUT  STD_LOGIC;
+-		SDRAM_DQM_n :  OUT  STD_LOGIC_vector(1 downto 0);
+-		SDRAM_CLK :  OUT  STD_LOGIC;
+-		--SDRAM_CKE :  OUT  STD_LOGIC;
+-		SDRAM_A :  OUT  STD_LOGIC_VECTOR(12 DOWNTO 0);
+-		SDRAM_DQ :  INOUT  STD_LOGIC_VECTOR(15 DOWNTO 0);
+-
+-		SD_DAT0 :  IN  STD_LOGIC;
+-		SD_CLK :  OUT  STD_LOGIC;
+-		SD_CMD :  OUT  STD_LOGIC;
+-		SD_DAT3 :  OUT  STD_LOGIC
++		halt : in std_logic
+ 	);
+ END atari800core;
+ 
+ ARCHITECTURE bdf_type OF atari800core IS 
++component synchronizer IS
++PORT 
++( 
++	CLK : IN STD_LOGIC;
++	RAW : IN STD_LOGIC;
++	SYNC : OUT STD_LOGIC
++);
++END component;
++
++COMPONENT complete_address_decoder IS
++generic (width : natural := 1);
++PORT 
++( 
++	addr_in : in std_logic_vector(width-1 downto 0);			
++	addr_decoded : out std_logic_vector((2**width)-1 downto 0)
++);
++END component;
+ 
+ COMPONENT cpu
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -79,16 +103,6 @@
+ 	);
+ END COMPONENT;
+ 
+-component hq_dac
+-port (
+-  reset :in std_logic;
+-  clk :in std_logic;
+-  clk_ena : in std_logic;
+-  pcm_in : in std_logic_vector(19 downto 0);
+-  dac_out : out std_logic
+-);
+-end component;
+-
+ component internalromram IS
+   PORT(
+     clock   : IN     STD_LOGIC;                             --system clock
+@@ -129,21 +143,14 @@
+ 		 dma_fetch_out : OUT STD_LOGIC;
+ 		 refresh_out : OUT STD_LOGIC;
+ 		 dma_clock_out : OUT STD_LOGIC;
++		 hcount_out : out std_logic_vector(7 downto 0);
++		 vcount_out : out std_logic_vector(8 downto 0);
+ 		 AN : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 dma_address_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT ledsw
+-	PORT(CLK : IN STD_LOGIC;
+-		 KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 SW : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 SYNC_KEYS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 SYNC_SWITCHES : OUT STD_LOGIC_VECTOR(9 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+ COMPONENT pokey_mixer
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 GTIA_SOUND : IN STD_LOGIC;
+@@ -151,23 +158,13 @@
+ 		 CHANNEL_1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 CHANNEL_2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 CHANNEL_3 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
++		 COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
++		 COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+ 		 CHANNEL_ENABLE : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
+ 		 VOLUME_OUT : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT ps2_keyboard
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 PS2_CLK : IN STD_LOGIC;
+-		 PS2_DAT : IN STD_LOGIC;
+-		 KEY_EVENT : OUT STD_LOGIC;
+-		 KEY_EXTENDED : OUT STD_LOGIC;
+-		 KEY_UP : OUT STD_LOGIC;
+-		 KEY_VALUE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+ COMPONENT zpu_glue
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 RESET : IN STD_LOGIC;
+@@ -177,6 +174,7 @@
+ 		 ZPU_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 ZPU_RAM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 ZPU_ROM_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
++		 ZPU_SECTOR_DI : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 MEMORY_FETCH : OUT STD_LOGIC;
+ 		 ZPU_READ_ENABLE : OUT STD_LOGIC;
+ 		 ZPU_32BIT_WRITE_ENABLE : OUT STD_LOGIC;
+@@ -271,29 +269,6 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT pokey_ps2_decoder
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 KEY_EVENT : IN STD_LOGIC;
+-		 KEY_EXTENDED : IN STD_LOGIC;
+-		 KEY_UP : IN STD_LOGIC;
+-		 KEY_CODE : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 KEY_HELD : OUT STD_LOGIC;
+-		 SHIFT_PRESSED : OUT STD_LOGIC;
+-		 BREAK_PRESSED : OUT STD_LOGIC;
+-		 KEY_INTERRUPT : OUT STD_LOGIC;
+-		 CONSOL_START : OUT STD_LOGIC;
+-		 CONSOL_SELECT : OUT STD_LOGIC;
+-		 CONSOL_OPTION : OUT STD_LOGIC;
+-		 SYSTEM_RESET : OUT STD_LOGIC;
+-		 KBCODE : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VIRTUAL_STICKS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VIRTUAL_TRIGGER : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 VIRTUAL_KEYS : out std_logic_vector(3 downto 0)
+-	);
+-END COMPONENT;
+-
+-
+ COMPONENT address_decoder
+ 	PORT(CLK : IN STD_LOGIC;
+ 		 CPU_FETCH : IN STD_LOGIC;
+@@ -328,9 +303,11 @@
+ 		 CACHE_POKEY_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 PORTB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 RAM_DATA : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 ram_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
++		 ram_select : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
+ 		 ROM_DATA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 rom_select : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
++		 rom_select : in std_logic_vector(5 downto 0);
++		 cart_select : in std_logic_vector(6 downto 0);
++		 cart_activate : in std_logic;
+ 		 SDRAM_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 ZPU_ADDR : IN STD_LOGIC_VECTOR(23 DOWNTO 0);
+ 		 ZPU_WRITE_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+@@ -363,88 +340,11 @@
+ 		 RAM_ADDR : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
+ 		 ROM_ADDR : OUT STD_LOGIC_VECTOR(21 DOWNTO 0);
+ 		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(22 DOWNTO 0);
+-		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+-COMPONENT sdram_statemachine
+-GENERIC (ADDRESS_WIDTH : INTEGER;
+-			AP_BIT : INTEGER;
+-			COLUMN_WIDTH : INTEGER;
+-			ROW_WIDTH : INTEGER
+-			);
+-	PORT(CLK_SYSTEM : IN STD_LOGIC;
+-		 CLK_SDRAM : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 READ_EN : IN STD_LOGIC;
+-		 WRITE_EN : IN STD_LOGIC;
+-		 REQUEST : IN STD_LOGIC;
+-		 BYTE_ACCESS : IN STD_LOGIC;
+-		 WORD_ACCESS : IN STD_LOGIC;
+-		 LONGWORD_ACCESS : IN STD_LOGIC;
+-		 REFRESH : IN STD_LOGIC;
+-		 ADDRESS_IN : IN STD_LOGIC_VECTOR(22 DOWNTO 0);
+-		 DATA_IN : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
+-		 SDRAM_DQ : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+-		 REPLY : OUT STD_LOGIC;
+-		 SDRAM_BA0 : OUT STD_LOGIC;
+-		 SDRAM_BA1 : OUT STD_LOGIC;
+-		 SDRAM_CKE : OUT STD_LOGIC;
+-		 SDRAM_CS_N : OUT STD_LOGIC;
+-		 SDRAM_RAS_N : OUT STD_LOGIC;
+-		 SDRAM_CAS_N : OUT STD_LOGIC;
+-		 SDRAM_WE_N : OUT STD_LOGIC;
+-		 SDRAM_ldqm : OUT STD_LOGIC;
+-		 SDRAM_udqm : OUT STD_LOGIC;
+-		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+-		 SDRAM_ADDR : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
++		 WRITE_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
++		 D6_WR_ENABLE : out std_logic
+ 	);
+ END COMPONENT;
+ 
+-component sdram_statemachine_mcc IS
+-generic
+-(
+-	ADDRESS_WIDTH : natural := 22;
+-	ROW_WIDTH : natural := 12;
+-	AP_BIT : natural := 10;
+-	COLUMN_WIDTH : natural := 8
+-);
+-PORT 
+-( 
+-	CLK_SYSTEM : IN STD_LOGIC;
+-	CLK_SDRAM : IN STD_LOGIC; -- this is a exact multiple of system clock
+-	RESET_N : in STD_LOGIC;
+-	
+-	-- interface as though SRAM - this module can take care of caching/write combining etc etc. For first cut... nothing. TODO: What extra info would help me here?
+-	DATA_IN : in std_logic_vector(31 downto 0);
+-	ADDRESS_IN : in std_logic_vector(ADDRESS_WIDTH downto 0); -- 1 extra bit for byte alignment
+-	READ_EN : in std_logic; -- if no reads pending may be a good time to do a refresh
+-	WRITE_EN : in std_logic;
+-	REQUEST : in std_logic; -- Toggle this to issue a new request
+-	BYTE_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0111, if 1=1011. Data fields valid:7 downto 0.
+-	WORD_ACCESS : in std_logic; -- ldqm/udqm set based on a(0) - if 0=0011, if 1=1001. Data fields valid:15 downto 0.
+-	LONGWORD_ACCESS : in std_logic; -- a(0) ignored. lqdm/udqm mask is 0000
+-	REFRESH : in std_logic;
+-
+-	REPLY : out std_logic; -- This matches the request once complete
+-	DATA_OUT : out std_logic_vector(31 downto 0);
+-
+-	-- sdram itself
+-	SDRAM_ADDR : out std_logic_vector(ROW_WIDTH downto 0);
+-	SDRAM_DQ : inout std_logic_vector(15 downto 0);
+-	SDRAM_BA0 : out std_logic;
+-	SDRAM_BA1 : out std_logic;
+-	
+-	SDRAM_CS_N : out std_logic;
+-	SDRAM_RAS_N : out std_logic;
+-	SDRAM_CAS_N : out std_logic;
+-	SDRAM_WE_N : out std_logic;
+-	
+-	SDRAM_ldqm : out std_logic; -- low enable, high disable - for byte addressing - NB, cas latency applies to reads
+-	SDRAM_udqm : out std_logic
+-);
+-END component;
+-
+ COMPONENT zpu_rom
+ 	PORT(clock : IN STD_LOGIC;
+ 		 address : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
+@@ -452,32 +352,31 @@
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT scandoubler
+-	PORT(CLK : IN STD_LOGIC;
+-		 RESET_N : IN STD_LOGIC;
+-		 VGA : IN STD_LOGIC;
+-		 COMPOSITE_ON_HSYNC : IN STD_LOGIC;
+-		 colour_enable : IN STD_LOGIC;
+-		 doubled_enable : IN STD_LOGIC;
+-		 vsync_in : IN STD_LOGIC;
+-		 hsync_in : IN STD_LOGIC;
+-		 colour_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 VSYNC : OUT STD_LOGIC;
+-		 HSYNC : OUT STD_LOGIC;
+-		 B : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 G : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
+-		 R : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
+-	);
+-END COMPONENT;
+-
+-COMPONENT zpu_ram
+-	PORT(wren : IN STD_LOGIC;
+-		 clock : IN STD_LOGIC;
+-		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+-		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+-	);
+-END COMPONENT;
++--COMPONENT zpu_ram
++--	PORT(wren : IN STD_LOGIC;
++--		 clock : IN STD_LOGIC;
++--		 address : IN STD_LOGIC_VECTOR(9 DOWNTO 0);
++--		 data : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
++--		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
++--	);
++--END COMPONENT;
++
++component generic_ram_infer IS
++        generic
++        (
++                ADDRESS_WIDTH : natural := 9;
++                SPACE : natural := 512;
++                DATA_WIDTH : natural := 8
++        );
++   PORT
++   (
++      clock: IN   std_logic;
++      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
++      address:  IN   std_logic_vector(address_width-1 downto 0);
++      we:    IN   std_logic;
++      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
++   );
++END component;
+ 
+ COMPONENT zpu_config_regs
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -509,21 +408,26 @@
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
+ 		 LEDG : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 LEDR : OUT STD_LOGIC_VECTOR(9 DOWNTO 0);
+-		 RAM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
++		 RAM_SELECT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ 		 ROM_SELECT : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ 		 THROTTLE_COUNT_6502 : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
+-		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
++		 ZPU_HEX : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
++		 sector : out std_logic_vector(31 downto 0);
++		 sector_request : out std_logic;
++		 sector_ready : in std_logic
+ 	);
+ END COMPONENT;
+ 
+-COMPONENT pll
+-	PORT(inclk0 : IN STD_LOGIC;
+-		 c0 : OUT STD_LOGIC;
+-		 c1 : OUT STD_LOGIC;
+-		 c2 : OUT STD_LOGIC;
+-		 locked : OUT STD_LOGIC
+-	);
+-END COMPONENT;
++COMPONENT gtia_palette IS
++PORT 
++( 
++	ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
++	
++	R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
++	G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
++	B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
++);
++END component;
+ 
+ COMPONENT gtia
+ 	PORT(CLK : IN STD_LOGIC;
+@@ -550,6 +454,7 @@
+ 		 MEMORY_DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 VSYNC : OUT STD_LOGIC;
+ 		 HSYNC : OUT STD_LOGIC;
++		 BLANK : OUT STD_LOGIC;
+ 		 sound : OUT STD_LOGIC;
+ 		 COLOUR_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 		 DATA_OUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
+@@ -581,6 +486,22 @@
+ );
+ END component;
+ 
++component covox IS
++PORT 
++( 
++	CLK : IN STD_LOGIC;
++	ADDR : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
++	DATA_IN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
++	WR_EN : IN STD_LOGIC;
++	
++	covox_channel0 : out std_logic_vector(7 downto 0);
++	covox_channel1 : out std_logic_vector(7 downto 0);
++	covox_channel2 : out std_logic_vector(7 downto 0);
++	covox_channel3 : out std_logic_vector(7 downto 0)
++);
++END component;
++
++
+ 
+ SIGNAL	ANTIC_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	ANTIC_AN :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+@@ -594,8 +515,6 @@
+ SIGNAL	ANTIC_RDY :  STD_LOGIC;
+ SIGNAL	ANTIC_REFRESH :  STD_LOGIC;
+ SIGNAL	ANTIC_WRITE_ENABLE :  STD_LOGIC;
+-SIGNAL	AUDIO_LEFT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+-SIGNAL	AUDIO_RIGHT :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	BREAK_PRESSED :  STD_LOGIC;
+ 
+ SIGNAL	CART_RD4 :  STD_LOGIC;
+@@ -610,8 +529,6 @@
+ SIGNAL	CA2_DIR_OUT:  STD_LOGIC;
+ SIGNAL	CB2_OUT :  STD_LOGIC;
+ SIGNAL	CB2_DIR_OUT:  STD_LOGIC;
+-SIGNAL	CLK :  STD_LOGIC;
+-SIGNAL	CLK_SDRAM :  STD_LOGIC;
+ SIGNAL	COMPOSITE_ON_HSYNC :  STD_LOGIC;
+ SIGNAL	CONSOL_OPTION :  STD_LOGIC;
+ SIGNAL	CONSOL_SELECT :  STD_LOGIC;
+@@ -655,6 +572,7 @@
+ SIGNAL	NMI_n :  STD_LOGIC;
+ SIGNAL	PAL :  STD_LOGIC;
+ SIGNAL	PAUSE_6502 :  STD_LOGIC;
++SIGNAL	HALT_OR_PAUSE_6502 :  STD_LOGIC;
+ SIGNAL	PBI_ADDR :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	PBI_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	PIA_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+@@ -662,7 +580,6 @@
+ SIGNAL	PIA_IRQB :  STD_LOGIC;
+ SIGNAL	PIA_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	PIA_WRITE_ENABLE :  STD_LOGIC;
+-SIGNAL	PLL_LOCKED :  STD_LOGIC;
+ SIGNAL	POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	CACHE_POKEY2_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	POKEY2_WRITE_ENABLE :  STD_LOGIC;
+@@ -682,24 +599,18 @@
+ SIGNAL	RAM_DO :  STD_LOGIC_VECTOR(15 DOWNTO 0);
+ SIGNAL	RAM_REQUEST :  STD_LOGIC;
+ SIGNAL	RAM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	RAM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
++SIGNAL	RAM_SELECT_dummy :  STD_LOGIC_VECTOR(2 DOWNTO 0);
+ SIGNAL	RAM_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	RESET_N :  STD_LOGIC;
+ SIGNAL	ROM_ADDR :  STD_LOGIC_VECTOR(21 DOWNTO 0);
+ SIGNAL	ROM_DO :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ SIGNAL	ROM_REQUEST :  STD_LOGIC;
+ SIGNAL	ROM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	ROM_SELECT :  STD_LOGIC_VECTOR(1 DOWNTO 0);
++SIGNAL	ROM_SELECT_dummy :  STD_LOGIC_VECTOR(5 DOWNTO 0);
+ SIGNAL	SCANDOUBLER_SHARED_ENABLE_HIGH :  STD_LOGIC;
+ SIGNAL	SCANDOUBLER_SHARED_ENABLE_LOW :  STD_LOGIC;
+-SIGNAL	SDRAM_ADDR :  STD_LOGIC_VECTOR(22 DOWNTO 0);
+-SIGNAL	SDRAM_DO :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+-SIGNAL	SDRAM_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	SDRAM_REFRESH :  STD_LOGIC;
+ --SIGNAL	SDRAM_REPLY :  STD_LOGIC;
+-SIGNAL	SDRAM_REQUEST_COMPLETE :  STD_LOGIC;
+-SIGNAL	SDRAM_REQUEST :  STD_LOGIC;
+-SIGNAL	SDRAM_WRITE_ENABLE :  STD_LOGIC;
+ SIGNAL	SHIFT_PRESSED :  STD_LOGIC;
+ SIGNAL	SIO_COMMAND_OUT :  STD_LOGIC;
+ SIGNAL	SIO_DATA_IN :  STD_LOGIC;
+@@ -733,32 +644,60 @@
+ SIGNAL	ZPU_READ_ENABLE :  STD_LOGIC;
+ SIGNAL	ZPU_RESET :  STD_LOGIC;
+ SIGNAL	ZPU_ROM_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
++SIGNAL	ZPU_SECTOR_DATA :  STD_LOGIC_VECTOR(31 DOWNTO 0);
+ SIGNAL	ZPU_STACK_WRITE :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_4 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_5 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_6 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_7 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_8 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_9 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_10 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_11 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+-SIGNAL	SYNTHESIZED_WIRE_12 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_13 :  STD_LOGIC;
+-SIGNAL	SYNTHESIZED_WIRE_14 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ 
+ SIGNAL	LEDR_dummy :  STD_LOGIC_VECTOR(9 DOWNTO 0);
+ SIGNAL	LEDG_dummy :  STD_LOGIC_VECTOR(7 DOWNTO 0);
+ signal UART_TXD_dummy : std_logic;
+ 
+-BEGIN 
++SIGNAL		SD_DAT0 :  STD_LOGIC;
++SIGNAL		SD_CLK :  STD_LOGIC;
++SIGNAL		SD_CMD :  STD_LOGIC;
++SIGNAL		SD_DAT3 :  STD_LOGIC;
++
++signal mist_buttons : std_logic_vector(1 downto 0);
++signal mist_switches : std_logic_vector(1 downto 0);
++
++SIGNAL	SHIFT_PRESSED_DUMMY :  STD_LOGIC;
++SIGNAL	BREAK_PRESSED_DUMMY :  STD_LOGIC;
++SIGNAL	CONTROL_PRESSED :  STD_LOGIC;
++
++signal dummy_sector_request : std_logic;
++signal dummy_sector : std_logic_vector(31 downto 0);
++
++signal COLOUR : std_logic_vector(7 downto 0);
+ 
++signal POKEY1_CHANNEL0 : std_logic_vector(3 downto 0);
++signal POKEY1_CHANNEL1 : std_logic_vector(3 downto 0);
++signal POKEY1_CHANNEL2 : std_logic_vector(3 downto 0);
++signal POKEY1_CHANNEL3 : std_logic_vector(3 downto 0);
+ 
++signal POKEY2_CHANNEL0 : std_logic_vector(3 downto 0);
++signal POKEY2_CHANNEL1 : std_logic_vector(3 downto 0);
++signal POKEY2_CHANNEL2 : std_logic_vector(3 downto 0);
++signal POKEY2_CHANNEL3 : std_logic_vector(3 downto 0);
+ 
+-b2v_a_6502 : cpu
++signal hcount_temp : std_logic_vector(7 downto 0);
++signal vcount_temp : std_logic_vector(8 downto 0);
++signal VGA_G_dummy : std_logic_vector(7 downto 0);
++signal VGA_B_dummy : std_logic_vector(7 downto 0);
++
++signal matrix_out_match : std_logic_vector(7 downto 0);
++
++signal keyboard_scan_inv : std_logic_vector(5 downto 0);
++
++signal covox_write_enable : std_logic;
++signal covox_channel0 : std_logic_vector(7 downto 0);
++signal covox_channel1 : std_logic_vector(7 downto 0);
++signal covox_channel2 : std_logic_vector(7 downto 0);
++signal covox_channel3 : std_logic_vector(7 downto 0);
++
++signal gtia_blank : std_logic;
++
++BEGIN 
++
++cpu6502 : cpu
+ PORT MAP(CLK => CLK,
+ 		 RESET => CPU_6502_RESET,
+ 		 ENABLE => RESET_N,
+@@ -774,7 +713,7 @@
+ 		 DO => CPU_DO);
+ 
+ LIGHTPEN <= '1';
+-b2v_inst1 : antic
++antic1 : antic
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => ANTIC_WRITE_ENABLE,
+ 		 RESET_N => RESET_N,
+@@ -792,54 +731,26 @@
+ 		 COLOUR_CLOCK_OUT => ANTIC_COLOUR_CLOCK_OUT,
+ 		 HIGHRES_COLOUR_CLOCK_OUT => ANTIC_HIGHRES_COLOUR_CLOCK_OUT,
+ 		 dma_fetch_out => ANTIC_FETCH,
++		 hcount_out => hcount_temp,
++		 vcount_out => vcount_temp,
+ 		 refresh_out => ANTIC_REFRESH,
+ 		 AN => ANTIC_AN,
+ 		 DATA_OUT => ANTIC_DO,
+ 		 dma_address_out => ANTIC_ADDR);
+ 
+-b2v_inst11 : pokey_mixer
++pokey_mixer_l : pokey_mixer
+ PORT MAP(CLK => CLK,
+ 		 GTIA_SOUND => GTIA_SOUND,
+-		 CHANNEL_0 => SYNTHESIZED_WIRE_0,
+-		 CHANNEL_1 => SYNTHESIZED_WIRE_1,
+-		 CHANNEL_2 => SYNTHESIZED_WIRE_2,
+-		 CHANNEL_3 => SYNTHESIZED_WIRE_3,
++		 CHANNEL_0 => POKEY1_CHANNEL0,
++		 CHANNEL_1 => POKEY1_CHANNEL1,
++		 CHANNEL_2 => POKEY1_CHANNEL2,
++		 CHANNEL_3 => POKEY1_CHANNEL3,
+ 		 CHANNEL_ENABLE => "1111",
+-		 VOLUME_OUT => AUDIO_LEFT);
++		 COVOX_CHANNEL_0 => covox_channel0,
++		 COVOX_CHANNEL_1 => covox_channel1,
++		 VOLUME_OUT => AUDIO_L);
+ 		 
+-dac_left : hq_dac
+-port map
+-(
+-  reset => not(reset_n),
+-  clk => clk,
+-  clk_ena => '1',
+-  pcm_in => audio_left&"0000",
+-  dac_out => audio_l
+-);
+-
+-dac_right : hq_dac
+-port map
+-(
+-  reset => not(reset_n),
+-  clk => clk,
+-  clk_ena => '1',
+-  pcm_in => audio_right&"0000",
+-  dac_out => audio_r
+-);
+-
+-
+-b2v_inst12 : ps2_keyboard
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 PS2_CLK => PS2K_CLK,
+-		 PS2_DAT => PS2K_DAT,
+-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+-		 KEY_UP => SYNTHESIZED_WIRE_10,
+-		 KEY_VALUE => SYNTHESIZED_WIRE_11);
+-
+-
+-b2v_inst13 : zpu_glue
++zpu_glue1 : zpu_glue
+ PORT MAP(CLK => CLK,
+ 		 RESET => ZPU_RESET,
+ 		 PAUSE => ZPU_PAUSE,
+@@ -848,6 +759,7 @@
+ 		 ZPU_DI => MEMORY_DATA,
+ 		 ZPU_RAM_DI => ZPU_RAM_DATA,
+ 		 ZPU_ROM_DI => ZPU_ROM_DATA,
++		 ZPU_SECTOR_DI => zpu_sector_data,
+ 		 MEMORY_FETCH => ZPU_FETCH,
+ 		 ZPU_READ_ENABLE => ZPU_READ_ENABLE,
+ 		 ZPU_32BIT_WRITE_ENABLE => ZPU_32BIT_WRITE_ENABLE,
+@@ -860,18 +772,20 @@
+ 		 ZPU_STACK_WRITE => ZPU_STACK_WRITE);
+ 
+ 
+-b2v_inst14 : pokey_mixer
++pokey_mixer_r : pokey_mixer
+ PORT MAP(CLK => CLK,
+ 		 GTIA_SOUND => GTIA_SOUND,
+-		 CHANNEL_0 => SYNTHESIZED_WIRE_4,
+-		 CHANNEL_1 => SYNTHESIZED_WIRE_5,
+-		 CHANNEL_2 => SYNTHESIZED_WIRE_6,
+-		 CHANNEL_3 => SYNTHESIZED_WIRE_7,
++		 CHANNEL_0 => POKEY2_CHANNEL0,
++		 CHANNEL_1 => POKEY2_CHANNEL1,
++		 CHANNEL_2 => POKEY2_CHANNEL2,
++		 CHANNEL_3 => POKEY2_CHANNEL3,
++		 COVOX_CHANNEL_0 => covox_channel2,
++		 COVOX_CHANNEL_1 => covox_channel3,
+ 		 CHANNEL_ENABLE => "1111",
+-		 VOLUME_OUT => AUDIO_RIGHT);
++		 VOLUME_OUT => AUDIO_R);
+ 
+ 
+-b2v_inst15 : pokey
++pokey2 : pokey
+ PORT MAP(CLK => CLK,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+ 		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+@@ -879,10 +793,10 @@
+ 		 RESET_N => RESET_N,
+ 		 ADDR => PBI_ADDR(3 DOWNTO 0),
+ 		 DATA_IN => WRITE_DATA(7 DOWNTO 0),
+-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_4,
+-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_5,
+-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_6,
+-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_7,
++		 CHANNEL_0_OUT => POKEY2_CHANNEL0,
++		 CHANNEL_1_OUT => POKEY2_CHANNEL1,
++		 CHANNEL_2_OUT => POKEY2_CHANNEL2,
++		 CHANNEL_3_OUT => POKEY2_CHANNEL3,
+ 		 DATA_OUT => POKEY2_DO,
+ 		 SIO_IN1 => '1',
+ 		 SIO_IN2 => '1',
+@@ -898,13 +812,14 @@
+ --GPIO_O[1] <= CB2_OUT when CB2_DIR_OUT='1' else 'Z';
+ --CB2_IN <= GPIO_O[1];
+ SIO_COMMAND_OUT <= CB2_OUT; -- we generate command frame, use internal rather than from pin
++SIO_COMMAND_TX <= SIO_COMMAND_OUT;
+ -- TODO - sioto gpio!
+ GPIO_PORTB_IN <= PORTB_OUT;
+-GPIO_CA2_IN <= CA2_OUT;
+-GPIO_CB2_IN <= CB2_OUT;
+-GPIO_PORTA_IN <= VIRTUAL_STICKS and (JOY1_n(0)&JOY1_n(1)&JOY1_n(2)&JOY1_n(3)&JOY2_n(0)&JOY2_n(1)&JOY2_n(2)&JOY2_n(3));
++GPIO_CA2_IN <= CA2_OUT when CA2_DIR_OUT='1' else '1';
++GPIO_CB2_IN <= CB2_OUT when CB2_DIR_OUT='1' else '1';
++GPIO_PORTA_IN <= ((JOY1_n(3)&JOY1_n(2)&JOY1_n(1)&JOY1_n(0)&JOY2_n(3)&JOY2_n(2)&JOY2_n(1)&JOY2_n(0)) and not (porta_dir_out)) or (porta_dir_out and porta_out);
+ 
+-b2v_inst16 : pia
++pia1 : pia
+ PORT MAP(CLK => CLK,
+ 		 EN => PIA_READ_ENABLE,
+ 		 WR_EN => PIA_WRITE_ENABLE,
+@@ -929,12 +844,13 @@
+ 		 PORTB_DIR_OUT => PORTB_DIR_OUT,
+ 		 PORTB_OUT => PORTB_OUT);
+ 
+-b2v_inst17 : shared_enable
++HALT_OR_PAUSE_6502 <= HALT or PAUSE_6502;
++enables : shared_enable
+ PORT MAP(CLK => CLK,
+ 		 RESET_N => RESET_N,
+ 		 MEMORY_READY_CPU => MEMORY_READY_CPU,
+ 		 MEMORY_READY_ANTIC => MEMORY_READY_ANTIC,
+-		 PAUSE_6502 => PAUSE_6502,
++		 PAUSE_6502 => HALT_OR_PAUSE_6502,
+ 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+ 		 POKEY_ENABLE_179 => POKEY_ENABLE_179,
+ 		 ANTIC_ENABLE_179 => ANTIC_ENABLE_179,
+@@ -943,33 +859,13 @@
+ 		 SCANDOUBLER_ENABLE_LOW => SCANDOUBLER_SHARED_ENABLE_LOW,
+ 		 SCANDOUBLER_ENABLE_HIGH => SCANDOUBLER_SHARED_ENABLE_HIGH);
+ 
+-
+-b2v_inst18 : pokey_ps2_decoder
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 KEY_EVENT => SYNTHESIZED_WIRE_8,
+-		 KEY_EXTENDED => SYNTHESIZED_WIRE_9,
+-		 KEY_UP => SYNTHESIZED_WIRE_10,
+-		 KEY_CODE => SYNTHESIZED_WIRE_11,
+-		 KEY_HELD => KEY_HELD,
+-		 SHIFT_PRESSED => SHIFT_PRESSED,
+-		 BREAK_PRESSED => BREAK_PRESSED,
+-		 CONSOL_START => CONSOL_START,
+-		 CONSOL_SELECT => CONSOL_SELECT,
+-		 CONSOL_OPTION => CONSOL_OPTION,
+-		 SYSTEM_RESET => SYSTEM_RESET_REQUEST,
+-		 KBCODE => KBCODE,
+-		 VIRTUAL_STICKS => VIRTUAL_STICKS,
+-		 VIRTUAL_TRIGGER => VIRTUAL_TRIGGERS,
+-		 VIRTUAL_KEYS => VIRTUAL_KEYS);
+-
+ -- no cart!
+ CART_RD4 <= '0';
+ CART_RD5 <= '0';
+ CART_REQUEST_COMPLETE <= '0';
+ CART_ROM_DO <= (others=>'0');
+ 
+-b2v_inst2 : address_decoder
++mmu1 : address_decoder
+ PORT MAP(CLK => CLK,
+ 		 CPU_FETCH => CPU_FETCH,
+ 		 CPU_WRITE_N => R_W_N,
+@@ -1003,9 +899,9 @@
+ 		 CACHE_POKEY_DATA => CACHE_POKEY_DO,
+ 		 PORTB => PORTB_OUT,
+ 		 RAM_DATA => RAM_DO,
+-		 ram_select => RAM_SELECT,
++		 ram_select => RAM_SELECT(2 downto 0),
+ 		 ROM_DATA => ROM_DO,
+-		 rom_select => ROM_SELECT,
++		 rom_select => ROM_SELECT, 
+ 		 SDRAM_DATA => SDRAM_DO,
+ 		 ZPU_ADDR => ZPU_ADDR_FETCH,
+ 		 ZPU_WRITE_DATA => ZPU_DO,
+@@ -1038,41 +934,40 @@
+ 		 RAM_ADDR => RAM_ADDR,
+ 		 ROM_ADDR => ROM_ADDR,
+ 		 SDRAM_ADDR => SDRAM_ADDR,
+-		 WRITE_DATA => WRITE_DATA);
++		 WRITE_DATA => WRITE_DATA,
++		 d6_wr_enable => covox_write_enable,
++		 cart_select => "0000000",
++		 cart_activate => '0');
+ 
+-b2v_inst21 : zpu_rom
++zpu_rom1 : zpu_rom
+ PORT MAP(clock => CLK,
+ 		 address => ZPU_ADDR_ROM_RAM(13 DOWNTO 2),
+ 		 q => ZPU_ROM_DATA);
++--
++--b2v_inst23 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(2),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(23 DOWNTO 16),
++--		 q => ZPU_RAM_DATA(23 DOWNTO 16));
+ 
+-
+-b2v_inst22 : scandoubler
+-PORT MAP(CLK => CLK,
+-		 RESET_N => RESET_N,
+-		 VGA => VGA,
+-		 COMPOSITE_ON_HSYNC => COMPOSITE_ON_HSYNC,
+-		 colour_enable => SCANDOUBLER_SHARED_ENABLE_LOW,
+-		 doubled_enable => SCANDOUBLER_SHARED_ENABLE_HIGH,
+-		 vsync_in => SYNTHESIZED_WIRE_12,
+-		 hsync_in => SYNTHESIZED_WIRE_13,
+-		 colour_in => SYNTHESIZED_WIRE_14,
+-		 VSYNC => VGA_VS,
+-		 HSYNC => VGA_HS,
+-		 B => VGA_B,
+-		 G => VGA_G,
+-		 R => VGA_R);
+-
+-
+-b2v_inst23 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(2),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(23 DOWNTO 16),
+-		 q => ZPU_RAM_DATA(23 DOWNTO 16));
++zpu_ram1 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(23 downto 16),
++		 we => ZPU_STACK_WRITE(2),
++		 q => ZPU_RAM_DATA(23 downto 16)
++		 );	
+ 
+ SYNC_KEYS <= (others=> '0');
+ SYNC_SWITCHES <= (others=> '1');
+-b2v_inst24 : zpu_config_regs
++zpu_config1 : zpu_config_regs
+ PORT MAP(CLK => CLK,
+ 		 ENABLE_179 => POKEY_ENABLE_179,
+ 		 WR_EN => ZPU_CONFIG_WRITE_ENABLE,
+@@ -1102,50 +997,89 @@
+ 		 DATA_OUT => ZPU_CONFIG_DO,
+ 		 LEDG => LEDG_dummy,
+ 		 LEDR => LEDR_dummy,
+-		 RAM_SELECT => RAM_SELECT,
+-		 ROM_SELECT => ROM_SELECT,
++		 RAM_SELECT => RAM_SELECT_dummy,
++		 ROM_SELECT => ROM_SELECT_dummy(1 downto 0),
+ 		 THROTTLE_COUNT_6502 => THROTTLE_COUNT_6502,
+-		 ZPU_HEX => ZPU_HEX);
++		 ZPU_HEX => ZPU_HEX,
++		 sector_request => dummy_sector_request,
++		 sector => dummy_sector,
++		 sector_ready => '0'
++		 );
++ROM_SELECT_dummy(5 downto 2) <= "0000";
++
++--
++--b2v_inst25 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(3),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(31 DOWNTO 24),
++--		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+ 
++zpu_ram2 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(31 downto 24),
++		 we => ZPU_STACK_WRITE(3),
++		 q => ZPU_RAM_DATA(31 downto 24)
++		 );	
++
++
++--b2v_inst26 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(0),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(7 DOWNTO 0),
++--		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+ 
+-b2v_inst25 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(3),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(31 DOWNTO 24),
+-		 q => ZPU_RAM_DATA(31 DOWNTO 24));
+-
+-
+-b2v_inst26 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(0),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(7 DOWNTO 0),
+-		 q => ZPU_RAM_DATA(7 DOWNTO 0));
+-
+-
+-b2v_inst27 : zpu_ram
+-PORT MAP(wren => ZPU_STACK_WRITE(1),
+-		 clock => CLK,
+-		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
+-		 data => ZPU_DO(15 DOWNTO 8),
+-		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+-
++zpu_ram3 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(7 downto 0),
++		 we => ZPU_STACK_WRITE(0),
++		 q => ZPU_RAM_DATA(7 downto 0)
++		 );	
++
++
++--b2v_inst27 : zpu_ram
++--PORT MAP(wren => ZPU_STACK_WRITE(1),
++--		 clock => CLK,
++--		 address => ZPU_ADDR_ROM_RAM(11 DOWNTO 2),
++--		 data => ZPU_DO(15 DOWNTO 8),
++--		 q => ZPU_RAM_DATA(15 DOWNTO 8));
+ 
+-b2v_inst5 : pll
+-PORT MAP(inclk0 => FPGA_CLK,
+-		 c0 => CLK_SDRAM,
+-		 c1 => CLK,
+-		 c2 => SDRAM_CLK,
+-		 locked => PLL_LOCKED);
++zpu_ram4 : generic_ram_infer
++generic map
++(
++	ADDRESS_WIDTH => 10,
++	SPACE => 1024,
++	DATA_WIDTH =>8
++)
++PORT MAP(clock => clk,
++		 address => ZPU_ADDR_ROM_RAM(11 downto 2),
++		 data => ZPU_DO(15 downto 8),
++		 we => ZPU_STACK_WRITE(1),
++		 q => ZPU_RAM_DATA(15 downto 8)
++		 );	
+ 
+-b2v_inst7 : pokey
++pokey1 : pokey
+ PORT MAP(CLK => CLK,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+ 		 ANTIC_MEMORY_READY => MEMORY_READY_ANTIC,
+ 		 WR_EN => POKEY_WRITE_ENABLE,
+ 		 RESET_N => RESET_N,
+-		 SIO_IN1 => '1',
++		 SIO_IN1 => SIO_RXD,
+ 		 SIO_IN2 => '1',
+ 		 SIO_IN3 => SIO_DATA_IN,
+ 		 ADDR => PBI_ADDR(3 DOWNTO 0),
+@@ -1153,39 +1087,62 @@
+ 		 keyboard_response => KEYBOARD_RESPONSE,
+ 		 POT_IN => POT_IN,
+ 		 IRQ_N_OUT => POKEY_IRQ,
+-		 SIO_OUT1 => UART_TXD_dummy,
++		 SIO_OUT1 => SIO_TXD,
+ 		 SIO_OUT2 => GPIO_SIO_OUT,
+ 		 SIO_OUT3 => SIO_DATA_OUT,
+ 		 POT_RESET => POT_RESET,
+-		 CHANNEL_0_OUT => SYNTHESIZED_WIRE_0,
+-		 CHANNEL_1_OUT => SYNTHESIZED_WIRE_1,
+-		 CHANNEL_2_OUT => SYNTHESIZED_WIRE_2,
+-		 CHANNEL_3_OUT => SYNTHESIZED_WIRE_3,
++		 CHANNEL_0_OUT => POKEY1_CHANNEL0,
++		 CHANNEL_1_OUT => POKEY1_CHANNEL1,
++		 CHANNEL_2_OUT => POKEY1_CHANNEL2,
++		 CHANNEL_3_OUT => POKEY1_CHANNEL3,
+ 		 DATA_OUT => POKEY_DO,
+ 		 keyboard_scan => KEYBOARD_SCAN);
+ 
+-	process(keyboard_scan, kbcode, key_held, shift_pressed, break_pressed)
+-	begin	
+-		keyboard_response <= (others=>'1');
+-		
+-		if (key_held='1' and kbcode(5 downto 0) = not(keyboard_scan)) then
++	keyboard_scan_inv <= not(keyboard_scan);
++
++a4051: complete_address_decoder
++	generic map (width => 3)
++	PORT map ( addr_in => keyboard_scan_inv(5 downto 3), addr_decoded => matrix_in ); 
++
++b4051: complete_address_decoder
++	generic map (width => 3)
++	PORT map ( addr_in => keyboard_scan_inv(2 downto 0), addr_decoded => matrix_out_match ); 
++
++	process(matrix_out, matrix_out_match)
++	begin
++		keyboard_response(0) <= '1';
++
++		if (or_reduce(matrix_out(7 downto 0) and matrix_out_match(7 downto 0)) = '1') then
+ 			keyboard_response(0) <= '0';
+ 		end if;
+-		
+-		if (keyboard_scan(5 downto 4)="00" and break_pressed = '1') then
++	end process;
++
++	process(static_keys, pause_key)
++	begin
++		keyboard_response(1) <= '1';
++
++		if (keyboard_scan(5 downto 4)="00" and pause_key = '1') then
+ 			keyboard_response(1) <= '0';
+ 		end if;
+ 		
+-		if (keyboard_scan(5 downto 4)="10" and shift_pressed = '1') then
++		if (keyboard_scan(5 downto 4)="10" and static_keys(0) = '1') then
+ 			keyboard_response(1) <= '0';
+ 		end if;
+ 
+-		if (keyboard_scan(5 downto 4)="11" and kbcode(7) = '1') then
++		if (keyboard_scan(5 downto 4)="11" and static_keys(1) = '1') then
+ 			keyboard_response(1) <= '0';
+ 		end if;
+-	end process;		 
++	end process;
++
++	CONSOL_START <= static_keys(6);
++	CONSOL_SELECT <= static_keys(5);
++	CONSOL_OPTION <= static_keys(4);
++	system_reset_request <= static_keys(3);
++
++	virtual_keys <= "000"&static_keys(2); -- todo need more static keys!! though on second thoughts using replay menu for options/loading...
++	virtual_triggers <= "00"&joy1_n(4)&joy2_n(4); -- todo joystick...
+ 		 	 
+-b2v_inst8 : gtia
++gtia1 : gtia
+ PORT MAP(CLK => CLK,
+ 		 WR_EN => GTIA_WRITE_ENABLE,
+ 		 CPU_MEMORY_READY => MEMORY_READY_CPU,
+@@ -1200,8 +1157,10 @@
+ 		 CONSOL_START => CONSOL_START,
+ 		 CONSOL_SELECT => CONSOL_SELECT,
+ 		 CONSOL_OPTION => CONSOL_OPTION,
+-		 TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
+-		 TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
++		 TRIG0 => joy2_n(4), -- TODO - joystick trigger too
++		 TRIG1 => joy1_n(4),
++		 --TRIG0 => VIRTUAL_TRIGGERS(0) and joy2_n(4), -- TODO - joystick trigger too
++		 --TRIG1 => VIRTUAL_TRIGGERS(1) and joy1_n(4),
+ 		 --TRIG0 => VIRTUAL_TRIGGERS(0),
+ 		 --TRIG1 => VIRTUAL_TRIGGERS(1),
+ 		 TRIG2 => VIRTUAL_TRIGGERS(2),
+@@ -1210,14 +1169,36 @@
+ 		 AN => ANTIC_AN,
+ 		 CPU_DATA_IN => WRITE_DATA(7 DOWNTO 0),
+ 		 MEMORY_DATA_IN => MEMORY_DATA(7 DOWNTO 0),
+-		 VSYNC => SYNTHESIZED_WIRE_12,
+-		 HSYNC => SYNTHESIZED_WIRE_13,
++		 VSYNC => VGA_VS,
++		 HSYNC => VGA_HS,
++		 BLANK => GTIA_BLANK,
+ 		 sound => GTIA_SOUND,
+-		 COLOUR_out => SYNTHESIZED_WIRE_14,
++		 COLOUR_out => COLOUR,
+ 		 DATA_OUT => GTIA_DO);
+ 
++	-- colour palette
++--	Color             Value         Color             Value
++--Black           0,      0	Medium blue     8,    128
++--Rust            1,     16       Dark blue       9,    144
++--Red-orange      2,     32       Blue-grey      10,    160
++--Dark orange     3,     48       Olive green    11,    176
++--Red             4,     64       Medium green   12,    192
++--Dk lavender     5,     80       Dark green     13,    208
++--Cobalt blue     6,     96       Orange-green   14,    224
++--Ultramarine     7,    112       Orange         15,    240
++
++-- from altirra	
++	palette1 : entity work.gtia_palette(altirra)
++		port map (ATARI_COLOUR=>COLOUR, R_next=>VGA_R, G_next=>VGA_G, B_next=>VGA_B);
++	--VGA_B <= hcount_temp;
++	--VGA_G <= vcount_temp(7 downto 0);
++		
++-- from lao
++--	palette2 : entity work.gtia_palette(laoo)
++--		port map (ATARI_COLOUR=>COLOUR, R_next=>R_next, G_next=>G_next, B_next=>B_next);		
++
+ 
+-b2v_inst9 : irq_glue
++irq_glue1 : irq_glue
+ PORT MAP(pokey_irq => POKEY_IRQ,
+ 		 pia_irqa => PIA_IRQA,
+ 		 pia_irqb => PIA_IRQB,
+@@ -1263,7 +1244,7 @@
+ 	DATA_OUT => CACHE_ANTIC_DO
+ );	
+ 
+-irr : internalromram
++internalromram1 : internalromram
+   PORT map(
+     clock => clk,
+     reset_n => reset_n,
+@@ -1281,69 +1262,22 @@
+ 	RAM_DATA => ram_do(7 downto 0)
+ 	);
+ 
+---b2v_inst20 : sdram_statemachine
+---GENERIC MAP(ADDRESS_WIDTH => 22,
+---			AP_BIT => 10,
+---			COLUMN_WIDTH => 8,
+---			ROW_WIDTH => 12
+---			)
+---PORT MAP(CLK_SYSTEM => CLK,
+---		 CLK_SDRAM => CLK_SDRAM,
+---		 RESET_N => RESET_N,
+---		 READ_EN => SDRAM_READ_ENABLE,
+---		 WRITE_EN => SDRAM_WRITE_ENABLE,
+---		 REQUEST => SDRAM_REQUEST,
+---		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+---		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+---		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+---		 REFRESH => SDRAM_REFRESH,
+---		 ADDRESS_IN => SDRAM_ADDR,
+---		 DATA_IN => WRITE_DATA,
+---		 SDRAM_DQ => SDRAM_DQ,
+---		 REPLY => SDRAM_REPLY,
+---		 SDRAM_BA0 => SDRAM_BA(0),
+---		 SDRAM_BA1 => SDRAM_BA(1),
+---		 SDRAM_CKE => SDRAM_A(12),
+---		 SDRAM_CS_N => SDRAM_CS_N,
+---		 SDRAM_RAS_N => SDRAM_RAS_N,
+---		 SDRAM_CAS_N => SDRAM_CAS_N,
+---		 SDRAM_WE_N => SDRAM_WE_N,
+---		 SDRAM_ldqm => SDRAM_DQM_n(0),
+---		 SDRAM_udqm => SDRAM_DQM_n(1),
+---		 DATA_OUT => SDRAM_DO,
+---		 SDRAM_ADDR => SDRAM_A(11 downto 0));
+-
+-b2v_inst20 : sdram_statemachine_mcc
+-GENERIC MAP(ADDRESS_WIDTH => 22,
+-			AP_BIT => 10,
+-			COLUMN_WIDTH => 8,
+-			ROW_WIDTH => 12
+-			)
+-PORT MAP(CLK_SYSTEM => CLK,
+-		 CLK_SDRAM => CLK_SDRAM,
+-		 RESET_N => RESET_N,
+-		 READ_EN => SDRAM_READ_ENABLE,
+-		 WRITE_EN => SDRAM_WRITE_ENABLE,
+-		 REQUEST => SDRAM_REQUEST,
+-		 BYTE_ACCESS => WIDTH_8BIT_ACCESS,
+-		 WORD_ACCESS => WIDTH_16BIT_ACCESS,
+-		 LONGWORD_ACCESS => WIDTH_32BIT_ACCESS,
+-		 REFRESH => SDRAM_REFRESH,
+-		 ADDRESS_IN => SDRAM_ADDR,
+-		 DATA_IN => WRITE_DATA,
+-		 SDRAM_DQ => SDRAM_DQ,
+-		 REPLY => SDRAM_REQUEST_COMPLETE,
+-		 SDRAM_BA0 => SDRAM_BA(0),
+-		 SDRAM_BA1 => SDRAM_BA(1),
+-		 --SDRAM_CKE => SDRAM_A(12), -- TODO?
+-		 SDRAM_CS_N => SDRAM_CS_N,
+-		 SDRAM_RAS_N => SDRAM_RAS_N,
+-		 SDRAM_CAS_N => SDRAM_CAS_N,
+-		 SDRAM_WE_N => SDRAM_WE_N,
+-		 SDRAM_ldqm => SDRAM_DQM_n(0),
+-		 SDRAM_udqm => SDRAM_DQM_n(1),
+-		 DATA_OUT => SDRAM_DO,
+-		 SDRAM_ADDR => SDRAM_A(12 downto 0)); -- TODO?
++SDRAM_WIDTH_8bit_ACCESS <= WIDTH_8bit_access;
++SDRAM_WIDTH_16bit_ACCESS <= WIDTH_16bit_access;
++SDRAM_WIDTH_32bit_ACCESS <= WIDTH_32bit_access;
++SDRAM_DI <= WRITE_DATA;
++
++covox1 : covox
++	PORT map
++	( 
++		clk => clk,
++		addr => pbi_addr(1 downto 0),
++		data_in => WRITE_DATA(7 DOWNTO 0),
++		wr_en => covox_write_enable,
++		covox_channel0 => covox_channel0,
++		covox_channel1 => covox_channel1,
++		covox_channel2 => covox_channel2,
++		covox_channel3 => covox_channel3
++	);
+ 
+-		
+-END bdf_type;
+\ No newline at end of file
++END bdf_type;
+Only in ../../../atari_800xl/common/a8core/: basic.vhdl
+Only in mcc216/: CHANGELOG
+Only in mcc216/: COPYRIGHT_NOTICE
+Only in ../../../atari_800xl/common/a8core/: covox.vhd
+diff -ur mcc216/cpu_6510.vhd ../../../atari_800xl/common/a8core/cpu_6510.vhd
+--- mcc216/cpu_6510.vhd	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/cpu_6510.vhd	2014-03-23 08:03:29.689482071 +0000
+@@ -98,45 +98,6 @@
+ 			debug_flags => debug_flags
+ 		);
+ 	
+-	MyBitfade: if emulate_bitfade generate
+-		bitfade7 : entity work.chameleon_bitfade
+-			generic map (
+-				max_fade_timer => 100
+-			)
+-			port map (
+-				clk => clk,
+-				ena_1khz => ena_1khz,
+-				
+-				dir => ioDir(7),
+-				d => ioData(7),
+-				q => ioFade(7)
+-			);
+-		bitfade6 : entity work.chameleon_bitfade
+-			generic map (
+-				max_fade_timer => 100
+-			)
+-			port map (
+-				clk => clk,
+-				ena_1khz => ena_1khz,
+-				
+-				dir => ioDir(6),
+-				d => ioData(6),
+-				q => ioFade(6)
+-			);
+-		bitfade3 : entity work.chameleon_bitfade
+-			generic map (
+-				max_fade_timer => 100
+-			)
+-			port map (
+-				clk => clk,
+-				ena_1khz => ena_1khz,
+-				
+-				dir => ioDir(3),
+-				d => ioData(3),
+-				q => ioFade(3)
+-			);
+-	end generate;
+-	
+ 	process(localA)
+ 	begin
+ 		accessIO <= '0';
+diff -ur mcc216/cpu_65xx_a.vhd ../../../atari_800xl/common/a8core/cpu_65xx_a.vhd
+--- mcc216/cpu_65xx_a.vhd	2014-01-18 14:29:19.000000000 +0000
++++ ../../../atari_800xl/common/a8core/cpu_65xx_a.vhd	2014-03-23 08:03:29.661482072 +0000
+@@ -1438,7 +1438,7 @@
+ -- -----------------------------------------------------------------------
+ -- Address generation
+ -- -----------------------------------------------------------------------
+-calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
++calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset, processInt)
+ 	begin
+ 		nextAddr <= nextAddrIncr;
+ 		case theCpuCycle is
+diff -ur mcc216/cpu.vhd ../../../atari_800xl/common/a8core/cpu.vhd
+--- mcc216/cpu.vhd	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/cpu.vhd	2014-03-23 08:03:29.677482072 +0000
+@@ -108,7 +108,7 @@
+ 			debugPc => debugPc,
+ 			debugA => debugA,
+ 			debugX => debugX,
+-			debugY => debugOpcode,
++			debugY => debugY,
+ 			debugS => debugS
+ 		);
+ 		CPU_ENABLE_RDY <= (CPU_ENABLE and (rdy or we)) or reset;
+Only in mcc216/: flashrom.vhdl
+Only in ../../../atari_800xl/common/a8core/: generic_ram_infer.vhdl
+Only in mcc216/: gpio.vhd
+diff -ur mcc216/gtia_palette.vhdl ../../../atari_800xl/common/a8core/gtia_palette.vhdl
+--- mcc216/gtia_palette.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/gtia_palette.vhdl	2014-03-23 08:03:29.665482072 +0000
+@@ -1049,6 +1049,8 @@
+ 					R_next <= X"ff";
+ 					G_next <= X"f3";
+ 					B_next <= X"9a";
++				when others =>
++					-- nop
+ 			end case;
+ 			
+ 		end process;
+@@ -2085,6 +2087,8 @@
+ 						R_next <= X"ff";
+ 						G_next <= X"e3";
+ 						B_next <= X"a1";
++					when others =>
++						-- nop
+ 			end case;
+ 			
+ 		end process;
+diff -ur mcc216/gtia_player.vhdl ../../../atari_800xl/common/a8core/gtia_player.vhdl
+--- mcc216/gtia_player.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/gtia_player.vhdl	2014-03-23 08:03:29.673482072 +0000
+@@ -73,6 +73,8 @@
+ 							shift_next <= shift_reg(6 downto 0) &'0';
+ 						when "01"|"10" =>
+ 							count_next <= "10";						
++						when others=>
++							--hang!
+ 					end case;					
+ 				when "01" =>					
+ 					case count_reg is
+@@ -81,6 +83,8 @@
+ 							shift_next <= shift_reg(6 downto 0) &'0';
+ 						when "00"|"10" =>
+ 							count_next <= "01";							
++						when others=>
++							--hang!
+ 					end case;					
+ 
+ 				when "11" =>
+@@ -94,7 +98,11 @@
+ 						when "11" =>
+ 							shift_next <= shift_reg(6 downto 0) &'0';
+ 							count_next <= "00";
++						when others=>
++							--hang!
+ 					end case;
++				when others=>
++					--hang!
+ 			end case;	
+ 
+ 			if (live_position = player_position) then
+@@ -105,4 +113,4 @@
+ 		
+ 	end process;
+ 	
+-end vhdl;
+\ No newline at end of file
++end vhdl;
+diff -ur mcc216/gtia.vhdl ../../../atari_800xl/common/a8core/gtia.vhdl
+--- mcc216/gtia.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/gtia.vhdl	2014-03-23 08:03:29.697482071 +0000
+@@ -53,6 +53,7 @@
+ 	
+ 	VSYNC : out std_logic;
+ 	HSYNC : out std_logic;
++	BLANK : out std_logic;
+ 	
+ 	-- To speaker
+ 	sound : out std_logic
+@@ -216,6 +217,11 @@
+ 	signal grafm_next : std_logic_vector(7 downto 0);
+ 	signal grafm_reg : std_logic_vector(7 downto 0);
+ 
++	signal grafm_reg10_extended : std_logic_vector(7 downto 0);
++	signal grafm_reg32_extended : std_logic_vector(7 downto 0);
++	signal grafm_reg54_extended : std_logic_vector(7 downto 0);
++	signal grafm_reg76_extended : std_logic_vector(7 downto 0);
++
+ 	signal colpm0_raw_next : std_logic_vector(7 downto 1);
+ 	signal colpm0_raw_reg : std_logic_vector(7 downto 1);
+ 	signal colpm1_raw_next : std_logic_vector(7 downto 1);
+@@ -795,6 +801,8 @@
+ 						if (active_bk_modify_next(7 downto 4) = "0000") then
+ 							active_bk_valid_next(3 downto 0) <= "0000";
+ 						end if;
++					when others =>
++						-- nop
+ 				end case;
+ 			end if;
+ 			
+@@ -1007,14 +1015,18 @@
+ 	player3 : gtia_player
+ 		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposp3_delayed_reg,size=>sizep3_delayed_reg(1 downto 0),bitmap=>grafp3_reg, output=>active_p3_live);				
+ 
++	grafm_reg10_extended <= grafm_reg(1 downto 0)&"000000";
++	grafm_reg32_extended <= grafm_reg(3 downto 2)&"000000";
++	grafm_reg54_extended <= grafm_reg(5 downto 4)&"000000";
++	grafm_reg76_extended <= grafm_reg(7 downto 6)&"000000";
+ 	missile0 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg(1 downto 0)&"000000", output=>active_m0_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm0_delayed_reg,size=>sizem_delayed_reg(1 downto 0),bitmap=>grafm_reg10_extended, output=>active_m0_live);
+ 	missile1 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg(3 downto 2)&"000000", output=>active_m1_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm1_delayed_reg,size=>sizem_delayed_reg(3 downto 2),bitmap=>grafm_reg32_extended, output=>active_m1_live);
+ 	missile2 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg(5 downto 4)&"000000", output=>active_m2_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm2_delayed_reg,size=>sizem_delayed_reg(5 downto 4),bitmap=>grafm_reg54_extended, output=>active_m2_live);
+ 	missile3 : gtia_player
+-		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg(7 downto 6)&"000000", output=>active_m3_live);
++		port map(clk=>clk,reset_n=>reset_n,colour_enable=>COLOUR_CLOCK_ORIGINAL,live_position=>hpos_reg,player_position=>hposm3_delayed_reg,size=>sizem_delayed_reg(7 downto 6),bitmap=>grafm_reg76_extended, output=>active_m3_live);
+ 		
+ 	-- calculate atari colour
+ 	priority_rules : gtia_priority
+@@ -1534,7 +1546,7 @@
+ 		end if;
+ 		
+ 		if (addr_decoded(20) = '1') then
+-			data_out <= "00000"&not(pal&pal&pal);
++			data_out <= "0000"&not(pal&pal&pal)&'1';
+ 		end if;
+ 
+ 		if (addr_decoded(31) = '1') then
+@@ -1548,6 +1560,7 @@
+ 	
+ 	vsync<=vsync_reg;
+ 	hsync<=hsync_reg;
++	blank<=hblank_reg or vsync_reg;
+ 	
+ 	sound <= consol_output_reg(3);
+ 
+Only in mcc216/: hexdecoder.vhd
+Only in mcc216/: hq_dac.v
+Only in mcc216/: i2c_loader.vhd
+Only in mcc216/: i2s_intf.vhd
+Only in mcc216/: i2sslave.vhdl
+diff -ur mcc216/internalromram.vhd ../../../atari_800xl/common/a8core/internalromram.vhd
+--- mcc216/internalromram.vhd	2014-01-21 20:44:04.000000000 +0000
++++ ../../../atari_800xl/common/a8core/internalromram.vhd	2014-03-23 08:03:29.689482071 +0000
+@@ -23,27 +23,44 @@
+ END internalromram;
+ 
+ architecture vhdl of internalromram is
+-component ramint IS
+-	PORT
+-	(
+-		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+-		clock		: IN STD_LOGIC  := '1';
+-		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+-		wren		: IN STD_LOGIC ;
+-		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+-	);
++--component ramint IS
++--	PORT
++--	(
++--		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
++--		clock		: IN STD_LOGIC  := '1';
++--		data		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
++--		wren		: IN STD_LOGIC ;
++--		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
++--	);
++--END component;
++
++component generic_ram_infer IS
++        generic
++        (
++                ADDRESS_WIDTH : natural := 9;
++                SPACE : natural := 512;
++                DATA_WIDTH : natural := 8
++        );
++   PORT
++   (
++      clock: IN   std_logic;
++      data:  IN   std_logic_vector (data_width-1 DOWNTO 0);
++      address:  IN   std_logic_vector(address_width-1 downto 0);
++      we:    IN   std_logic;
++      q:     OUT  std_logic_vector (data_width-1 DOWNTO 0)
++   );
+ END component;
+ 
+-component romlo IS
++component os16 IS
+ 	PORT
+ 	(
+-		address		: IN STD_LOGIC_VECTOR (10 DOWNTO 0);
++		address		: IN STD_LOGIC_VECTOR (13 DOWNTO 0);
+ 		clock		: IN STD_LOGIC  := '1';
+ 		q		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ 	);
+ END component;
+ 
+-component romhi IS
++component basic IS
+ 	PORT
+ 	(
+ 		address		: IN STD_LOGIC_VECTOR (12 DOWNTO 0);
+@@ -55,8 +72,8 @@
+ 	signal rom_request_reg : std_logic;
+ 	signal ram_request_reg : std_logic;
+ 	
+-	signal ROMLO_DATA : std_logic_vector(7 downto 0);
+-	signal ROMHI_DATA : std_logic_vector(7 downto 0);
++	signal ROM16_DATA : std_logic_vector(7 downto 0);
++	signal BASIC_DATA : std_logic_vector(7 downto 0);	
+ 	
+ 	signal RAM_WR_ENABLE_REAL : std_logic;
+ 	signal IRAM_DATA : std_logic_vector(7 downto 0);
+@@ -74,26 +91,48 @@
+ 	end process;
+ 
+ 	rom_request_complete <= rom_request_reg;
+-	ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
+-	romlo1 : romlo
+-	PORT MAP(clock => clock,
+-			 address => rom_addr(10 downto 0),
+-			 q => ROMLO_data
+-			 );	
+-	romhi1 : romhi
++	--C000 = basic. 
++	--0000-07FF = low
++	--0800-27ff high
++	
++	process(rom16_data,basic_data, rom_addr(15 downto 0))
++	begin
++		ROM_DATA <= ROM16_DATA;
++		if (rom_addr(15)='1') then
++			ROM_DATA <= BASIC_DATA;
++		end if;
++	end process;
++	
++	
++	--ROM_DATA <= ROMLO_DATA when rom_addr(15 downto 12)=X"D" else ROMHI_DATA;	
++	--ROM_DATA <= ROMHI_DATA;
++	basic1 : basic
+ 	PORT MAP(clock => clock,
+ 			 address => rom_addr(12 downto 0),
+-			 q => ROMHI_data
++			 q => BASIC_data
++			 );			 
++			 
++	rom16a : os16
++	PORT MAP(clock => clock,
++			 address => rom_addr(13 downto 0),
++			 q => ROM16_data
+ 			 );
+ 	
+-	ramint1 : ramint
++	ramint1 : generic_ram_infer
++        generic map
++        (
++                ADDRESS_WIDTH => 14,
++                SPACE => 16384,
++                DATA_WIDTH =>8
++        )
+ 	PORT MAP(clock => clock,
+-			 address => ram_addr(12 downto 0),
++			 address => ram_addr(13 downto 0),
+ 			 data => ram_data_in(7 downto 0),
+-			 wren => RAM_WR_ENABLE_REAL,
++			 we => RAM_WR_ENABLE_REAL,
+ 			 q => iram_data
+ 			 );	
+ 	ram_request_complete <= ram_request_reg;
+-	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 13)= "000" else X"FF";
+-	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 13)="000" else '0'; -- ban writes over 8k when using int ram - HACK
+-end vhdl;
+\ No newline at end of file
++	
++	RAM_DATA <= IRAM_DATA when ram_addr(15 downto 14)= "00" else X"FF";
++	RAM_WR_ENABLE_REAL <= RAM_WR_ENABLE when ram_addr(15 downto 14)="00" else '0'; -- ban writes over 16k when using int ram - HACK
++end vhdl;
+Only in mcc216/: ledsw.vhd
+Only in ../../../atari_800xl/common/a8core/: os16.vhdl
+diff -ur mcc216/pia.vhdl ../../../atari_800xl/common/a8core/pia.vhdl
+--- mcc216/pia.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/pia.vhdl	2014-03-23 08:03:29.645482073 +0000
+@@ -310,6 +310,8 @@
+ 						-- ca1 restore
+ 						ca2_output_next <= '1';	
+ 					end if;				
++				when others =>
++					-- nop
+ 			end case;					
+ 		end if;
+ 
+@@ -363,6 +365,8 @@
+ 						-- cb1 restore
+ 						cb2_output_next <= '1';	
+ 					end if;				
++				when others =>
++					--nop
+ 			end case;					
+ 		end if;
+ 
+Only in mcc216/: pll.bsf
+Only in mcc216/: pll.cmp
+Only in mcc216/: PLLJ_PLLSPE_INFO.txt
+Only in mcc216/: pll.ppf
+Only in mcc216/: pll.qip
+Only in mcc216/: pll.vhd
+diff -ur mcc216/pokey_keyboard_scanner.vhdl ../../../atari_800xl/common/a8core/pokey_keyboard_scanner.vhdl
+--- mcc216/pokey_keyboard_scanner.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/pokey_keyboard_scanner.vhdl	2014-03-23 08:03:29.769482067 +0000
+@@ -150,6 +150,9 @@
+ 				if (my_key = '1') then
+ 					state_next <= state_wait_key;
+ 				end if;
++
++			when others=> 
++				state_next <= state_wait_key; 
+ 			end case;
+ 
+ 			if (bincnt_reg(3 downto 0)  = "0000") then
+@@ -176,4 +179,4 @@
+ 	shift_pressed <= shift_pressed_reg;
+ 	control_pressed <= control_pressed_reg;
+ 	other_key_irq <= irq_reg;
+-end vhdl;
+\ No newline at end of file
++end vhdl;
+diff -ur mcc216/pokey_mixer.vhdl ../../../atari_800xl/common/a8core/pokey_mixer.vhdl
+--- mcc216/pokey_mixer.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/pokey_mixer.vhdl	2014-03-23 08:03:29.649482073 +0000
+@@ -22,6 +22,9 @@
+ 	CHANNEL_3 : IN STD_LOGIC_VECTOR(3 downto 0);
+ 	
+ 	GTIA_SOUND : IN STD_LOGIC;
++
++	COVOX_CHANNEL_0 : IN STD_LOGIC_VECTOR(7 downto 0);
++	COVOX_CHANNEL_1 : IN STD_LOGIC_VECTOR(7 downto 0);
+ 	
+ 	VOLUME_OUT : OUT STD_LOGIC_vector(15 downto 0)
+ );
+@@ -30,6 +33,7 @@
+ ARCHITECTURE vhdl OF pokey_mixer IS
+ 	signal volume_reg : std_logic_vector(15 downto 0);
+ 	signal volume_next : std_logic_vector(15 downto 0);
++	signal volume_next_real : std_logic_vector(15 downto 0);	
+ 	
+ 	signal volume_sum : std_logic_vector(5 downto 0);
+ 	
+@@ -38,13 +42,13 @@
+ 	signal channel_2_en : std_logic_vector(3 downto 0);
+ 	signal channel_3_en : std_logic_vector(3 downto 0);
+ 	
+-	signal gtia_en : std_logic_vector(5 downto 0);
++	signal gtia_en : std_logic_vector(15 downto 0);
+ BEGIN
+ 	-- register
+ 	process(clk)
+ 	begin
+ 		if (clk'event and clk='1') then
+-			volume_reg <= volume_next;
++			volume_reg <= volume_next_real;
+ 		end if;
+ 	end process;
+ 	
+@@ -73,9 +77,7 @@
+ --		end if;
+ 	end process;
+ 	
+-	gtia_en <= "0000"&gtia_sound&gtia_sound;  -- only room for 3 more! TODO, regenerate...
+-	
+-	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,gtia_en)
++	process (channel_0_en,channel_1_en,channel_2_en,channel_3_en,covox_CHANNEL_0,covox_channel_1,gtia_en)
+ 	begin
+ 		volume_sum <= 
+ 			std_logic_vector
+@@ -89,12 +91,13 @@
+ 						unsigned('0'&CHANNEL_2_en) + 
+ 						unsigned('0'&CHANNEL_3_en)
+ 					))
+-					+ 
+-					unsigned(gtia_en)
+ 			);
+ 	end process;
+ 	
+-	process (volume_sum)
++	gtia_en(15 downto 13) <= (others=>'0');
++	gtia_en(12) <= gtia_sound;
++	gtia_en(11 downto 0) <= (others=>'0');
++ 	process (volume_sum, volume_next, gtia_en, covOX_CHANNEL_0,covOX_CHANNEL_1)
+ 	begin
+ 		case volume_sum is 
+ 			when "000000" =>
+@@ -223,9 +226,24 @@
+ 				volume_next <= X"79FF"; -- in case GTIA playing at full vol!
+ 		end case;
+ 		
++--		volume_next_real <= std_LOGIC_vector(
++--			(unsigned('0'&volume_next(15 downto 1)) 
++--			+ unsigned(gtia_en)) 
++--			+ (unsigned("00"&covox_CHANNEL_0) 
++--			+ unsigned("00"&covox_CHANNEL_1)));
++		
++		--volume_next_real <= '0'&volume_next(15 downto 1);
++		
++		volume_next_real <= std_LOGIC_vector(
++			(unsigned("00"&volume_next(15 downto 2)) 
++			+ unsigned(gtia_en)) 		
++			+ (unsigned("000"&covox_CHANNEL_0&"00000") 
++			+ unsigned("000"&covox_CHANNEL_1&"00000")));
++		
+ 	end process;
+ 			
+ 	-- output
++	-- TODO
+ 	volume_out <= volume_reg;
+ 		
+ END vhdl;
+\ No newline at end of file
+Only in mcc216/: pokey_ps2_decoder.vhdl
+diff -ur mcc216/pokey.vhdl ../../../atari_800xl/common/a8core/pokey.vhdl
+--- mcc216/pokey.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/pokey.vhdl	2014-03-23 15:34:33.619247550 +0000
+@@ -330,6 +330,7 @@
+ 	signal serout_active_reg : std_logic;
+ 	
+ 	signal serial_reset : std_logic;
++	signal serout_sync_reset : std_logic;
+ 	signal skrest_write : std_logic;
+ 	
+ 	signal serout_enable : std_logic;
+@@ -764,7 +765,7 @@
+ 		end if;		
+ 
+ 		if (addr_decoded(15) = '1') then --SKSTAT
+-			data_out <= not(serial_ip_framing_reg)&not(serial_ip_overrun_reg)&not(keyboard_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
++			data_out <= not(serial_ip_framing_reg)&not(keyboard_overrun_reg)&not(serial_ip_overrun_reg)&sio_in_reg&not(SHIFT_PRESSED)&not(KEY_HELD)&waiting_for_start_bit&"1";
+ 		end if;		
+ 		
+ 	end process;
+@@ -936,9 +937,10 @@
+ 	
+ 	-- serial port output	
+ 	-- urghhh
++        serout_sync_reset <= serial_reset or stimer_write_delayed;
+ 	serout_clock_delay : delay_line
+ 		generic map (count=>2)
+-		port map (clk=>clk, sync_reset=>serial_reset or stimer_write_delayed,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
++		port map (clk=>clk, sync_reset=>serout_sync_reset,data_in=>serout_enable, enable=>enable_179, reset_n=>reset_n, data_out=>serout_enable_delayed);
+ 		
+ 	
+ 	process(serout_enable_delayed, skctl_reg, serout_active_reg, serout_clock_last_reg,serout_clock_reg, serout_holding_load, serout_holding_reg, serout_holding_full_reg, serout_shift_reg, serout_bitcount_reg, serial_out_reg, twotone_reg, audf0_pulse, audf1_pulse, serial_reset)
+@@ -1131,6 +1133,8 @@
+ 			when "111" =>			
+ 				serin_enable <= audf3_pulse;
+ 				serout_enable <= audf1_pulse;
++			when others =>
++				-- nop
+ 		end case;
+ 	end process;
+ 	
+Only in mcc216/: ps2_keyboard.vhdl
+Only in mcc216/: ramint.bsf
+Only in mcc216/: ramint.cmp
+Only in mcc216/: ramint.qip
+Only in mcc216/: ramint.vhd
+Only in mcc216/: romhi.bsf
+Only in mcc216/: romhi.cmp
+Only in mcc216/: romhi.qip
+Only in mcc216/: romhi.vhd
+Only in mcc216/: romlo.bsf
+Only in mcc216/: romlo.cmp
+Only in mcc216/: romlo.qip
+Only in mcc216/: romlo.vhd
+Only in mcc216/: scandouble_ram_infer.vhdl
+Only in mcc216/: scandoubler.vhdl
+Only in mcc216/: sdram_ctrl_4_ports.v
+Only in mcc216/: sdram_statemachine_mcc.vhdl
+Only in mcc216/: sdram_statemachine.vhdl
+diff -ur mcc216/shared_enable.vhdl ../../../atari_800xl/common/a8core/shared_enable.vhdl
+--- mcc216/shared_enable.vhdl	2014-01-17 20:20:16.000000000 +0000
++++ ../../../atari_800xl/common/a8core/shared_enable.vhdl	2014-03-23 08:03:29.653482073 +0000
+@@ -50,6 +50,7 @@
+ 	PORT 
+ 	( 
+ 		CLK : IN STD_LOGIC;
++		SYNC_RESET : IN STD_LOGIC;
+ 		DATA_IN : IN STD_LOGIC;
+ 		ENABLE : IN STD_LOGIC;
+ 		RESET_N : IN STD_LOGIC;
+@@ -78,6 +79,8 @@
+ 	signal enable_179_expanded : std_logic;
+ 	
+ 	signal memory_ready : std_logic;
++
++	constant cycle_length : integer := 16;	
+ begin
+ 	-- instantiate some clock calcs
+ 	SCANDOUBLER_ENABLE_HIGH <= '1';
+@@ -87,8 +90,7 @@
+ 		port map(clk=>CLK,reset_n=>reset_n,enable_in=>'1',enable_out=>SCANDOUBLER_ENABLE_LOW);		
+ 
+ 	enable_179_clock_div : enable_divider
+-		--generic map (COUNT=>16)
+-		generic map (COUNT=>32)
++		generic map (COUNT=>cycle_length)
+ 		port map(clk=>clk,reset_n=>reset_n,enable_in=>'1',enable_out=>enable_179);
+ 		
+ 	process(THROTTLE_COUNT_6502, throttle_count_reg, enable_179)
+@@ -120,14 +122,12 @@
+ 	end process;
+ 
+ 	delay_line_phase : delay_line
+-		--generic map (COUNT=>15)
+-		generic map (COUNT=>31)
+-		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
++		generic map (COUNT=>cycle_length-1)
++		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_early);	
+ 
+ 	delay_line_phase2 : delay_line
+-		--generic map (COUNT=>15)
+-		generic map (COUNT=>16)
+-		port map(clk=>clk,reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
++		generic map (COUNT=>cycle_length/2)
++		port map(clk=>clk,sync_reset=>'0',reset_n=>reset_n,data_in=>enable_179, enable=>'1', data_out=>enable_179_late);		
+ 	
+ 	-- registers
+ 	process(clk,reset_n)
+Only in mcc216/: spi_master.vhd
+Only in mcc216/: sram.vhdl
+Only in mcc216/: zpu
+Only in mcc216/: zpu_config_regs.vhdl
+Only in mcc216/: zpu_core.vhd
+Only in mcc216/: zpu_glue.vhdl
+Only in mcc216/: zpupkg.vhd
+Only in mcc216/: zpu_ram.cmp
+Only in mcc216/: zpu_ram.qip
+Only in mcc216/: zpu_ram.vhd
+Only in mcc216/: zpu_rom.cmp
+Only in mcc216/: zpu_rom.qip
+Only in mcc216/: zpu_rom.vhd
Index: unmerged/zpu_firmware/de1_old/HelloTinyROM.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/HelloTinyROM.bin
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/de1_old/Makefile
===================================================================
--- unmerged/zpu_firmware/de1_old/Makefile	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c mmc.c    spi.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/zpu_firmware/de1_old/bootloader
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/bootloader
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/de1_old/fat.h
===================================================================
--- unmerged/zpu_firmware/de1_old/fat.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/fat.h	(revision 1)
@@ -0,0 +1,435 @@
+/*! \file fat.h \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.h'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup general
+/// \defgroup fat FAT16/32 File System Interface (fat.c)
+/// \code #include "fat.h" \endcode
+/// \par Overview
+///		This FAT16/32 interface allows you to detect and mount FAT16/32
+///		partitions, browse directories and files, and read file data.
+///		The interface is designed to operate with the avrlib IDE/ATA driver.
+///		Reading FAT efficiently requires at least 512+ bytes of RAM so this
+///		interface may not be suitable for processors with less than 1K of RAM.
+///		This interface will properly follow a file's cluster chain so files
+///		need not be defragmented.
+///
+/// \note This code is based in part on work done by Jesper Hansen for his
+///		excellent YAMPP MP3 player project.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef FAT_H
+#define FAT_H
+
+#define FALSE 0
+#define TRUE -1
+
+#define DRIVE0 1
+
+// Some useful cluster numbers
+#define MSDOSFSROOT     0		// cluster 0 means the root dir
+#define CLUST_FREE      0               // cluster 0 also means a free cluster
+#define MSDOSFSFREE     CLUST_FREE
+#define CLUST_FIRST     2               // first legal cluster number
+#define CLUST_RSRVD     0xfffffff6      // reserved cluster range
+#define CLUST_BAD       0xfffffff7      // a cluster with a defect
+#define CLUST_EOFS      0xfffffff8      // start of eof cluster range
+#define CLUST_EOFE      0xffffffff      // end of eof cluster range
+
+#define FAT12_MASK      0x00000fff      // mask for 12 bit cluster numbers
+#define FAT16_MASK      0x0000ffff      // mask for 16 bit cluster numbers
+#define FAT32_MASK      0x0fffffff      // mask for FAT32 cluster numbers
+
+
+// Partition Type used in the partition record
+#define PART_TYPE_UNKNOWN		0x00
+#define PART_TYPE_FAT12			0x01
+#define PART_TYPE_XENIX			0x02
+#define PART_TYPE_DOSFAT16		0x04
+#define PART_TYPE_EXTDOS		0x05
+#define PART_TYPE_FAT16			0x06
+#define PART_TYPE_NTFS			0x07
+#define PART_TYPE_FAT32			0x0B
+#define PART_TYPE_FAT32LBA		0x0C
+#define PART_TYPE_FAT16LBA		0x0E
+#define PART_TYPE_EXTDOSLBA		0x0F
+#define PART_TYPE_ONTRACK		0x33
+#define PART_TYPE_NOVELL		0x40
+#define PART_TYPE_PCIX			0x4B
+#define PART_TYPE_PHOENIXSAVE	0xA0
+#define PART_TYPE_CPM			0xDB
+#define PART_TYPE_DBFS			0xE0
+#define PART_TYPE_BBT			0xFF
+
+struct partrecord // length 16 bytes
+{			
+	unsigned char	prIsActive;					// 0x80 indicates active partition
+	unsigned char	prStartHead;				// starting head for partition
+	unsigned short	prStartCylSect;				// starting cylinder and sector
+	unsigned char	prPartType;					// partition type (see above)
+	unsigned char	prEndHead;					// ending head for this partition
+	unsigned short	prEndCylSect;				// ending cylinder and sector
+	unsigned long	prStartLBA;					// first LBA sector for this partition
+	unsigned long	prSize;						// size of this partition (bytes or sectors ?)
+};
+
+        
+struct partsector
+{
+	unsigned char	psPartCode[512-64-2];		// pad so struct is 512b
+	unsigned char	psPart[64];					// four partition records (64 bytes)
+	unsigned char	psBootSectSig0;				// two signature bytes (2 bytes)
+	unsigned char	psBootSectSig1;
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+
+// Format of a boot sector.  This is the first sector on a DOS floppy disk
+// or the first sector of a partition on a hard disk.  But, it is not the
+// first sector of a partitioned hard disk.
+struct bootsector33 {
+	unsigned char 	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[19];					// BIOS parameter block
+	unsigned char	bsDriveNumber;				// drive number (0x80)
+	unsigned char	bsBootCode[479];			// pad so struct is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct extboot {
+	unsigned char	exDriveNumber;				// drive number (0x80)
+	unsigned char	exReserved1;				// reserved
+	unsigned char	exBootSignature;			// ext. boot signature (0x29)
+#define EXBOOTSIG       0x29
+	unsigned char	exVolumeID[4];				// volume ID number
+	unsigned char	exVolumeLabel[11];			// volume label
+	unsigned char	exFileSysType[8];			// fs type (FAT12 or FAT16)
+};
+
+struct bootsector50 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[25];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[448];			// pad so structure is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55 
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct bootsector710 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOEMName[8];				// OEM name and version
+	unsigned char	bsBPB[53];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[418];			// pad so structure is 512b
+	unsigned char	bsBootSectSig2;				// 2 & 3 are only defined for FAT32?
+	unsigned char	bsBootSectSig3;
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+#define BOOTSIG2        0
+#define BOOTSIG3        0
+};
+
+
+/***************************************************************/
+/***************************************************************/
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct bpb33 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char    bpbSecPerClust;	// sectors per cluster
+        unsigned short	bpbResSectors;	// number of reserved sectors
+        unsigned char	bpbFATs;		// number of FATs
+        unsigned short	bpbRootDirEnts;	// number of root directory entries
+        unsigned short	bpbSectors;		// total number of sectors
+        unsigned char	bpbMedia;		// media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned short	bpbHiddenSecs;  // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not present in the DOS 3.3 bpb.
+struct bpb50 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char	bpbSecPerClust; // sectors per cluster
+        unsigned short	bpbResSectors;  // number of reserved sectors
+        unsigned char	bpbFATs;        // number of FATs
+        unsigned short	bpbRootDirEnts; // number of root directory entries
+        unsigned short	bpbSectors;     // total number of sectors
+        unsigned char	bpbMedia;       // media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned long	bpbHiddenSecs;  // # of hidden sectors
+// 3.3 compat ends here
+        unsigned long	bpbHugeSectors; // # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32)
+// This one has a few extensions to bpb50.
+struct bpb710 {
+		unsigned short	bpbBytesPerSec;	// bytes per sector
+		unsigned char	bpbSecPerClust;	// sectors per cluster
+		unsigned short	bpbResSectors;	// number of reserved sectors
+		unsigned char	bpbFATs;		// number of FATs
+		unsigned short	bpbRootDirEnts;	// number of root directory entries
+		unsigned short	bpbSectors;		// total number of sectors
+		unsigned char	bpbMedia;		// media descriptor
+		unsigned short	bpbFATsecs;		// number of sectors per FAT
+		unsigned short	bpbSecPerTrack;	// sectors per track
+		unsigned short	bpbHeads;		// number of heads
+		unsigned long	bpbHiddenSecs;	// # of hidden sectors
+// 3.3 compat ends here
+		unsigned long	bpbHugeSectors;	// # of sectors if bpbSectors == 0
+// 5.0 compat ends here
+		unsigned long     bpbBigFATsecs;// like bpbFATsecs for FAT32
+		unsigned short      bpbExtFlags;	// extended flags:
+#define FATNUM    0xf			// mask for numbering active FAT
+#define FATMIRROR 0x80			// FAT is mirrored (like it always was)
+		unsigned short      bpbFSVers;	// filesystem version
+#define FSVERS    0				// currently only 0 is understood
+		unsigned long     bpbRootClust;	// start cluster for root directory
+		unsigned short      bpbFSInfo;	// filesystem info structure sector
+		unsigned short      bpbBackup;	// backup boot sector
+		// There is a 12 byte filler here, but we ignore it
+};
+
+
+// ***************************************************************
+// * byte versions of the above structs                          *
+// ***************************************************************
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct byte_bpb33 {
+        unsigned char bpbBytesPerSec[2];		// bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[2];      // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not in the 3.3 bpb.
+struct byte_bpb50 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // number of hidden sectors
+        unsigned char bpbHugeSectors[4];		// # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32).
+// This one has a few extensions to bpb50.
+struct byte_bpb710 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // # of hidden sectors
+        unsigned char bpbHugeSectors[4];     // # of sectors if bpbSectors == 0
+        unsigned char bpbBigFATsecs[4];      // like bpbFATsecs for FAT32
+        unsigned char bpbExtFlags[2];        // extended flags:
+        unsigned char bpbFSVers[2];          // filesystem version
+        unsigned char bpbRootClust[4];       // start cluster for root directory
+        unsigned char bpbFSInfo[2];          // filesystem info structure sector
+        unsigned char bpbBackup[2];          // backup boot sector
+        // There is a 12 byte filler here, but we ignore it
+};
+
+// FAT32 FSInfo block.
+struct fsinfo {
+        unsigned char fsisig1[4];
+        unsigned char fsifill1[480];
+        unsigned char fsisig2[4];
+        unsigned char fsinfree[4];
+        unsigned char fsinxtfree[4];
+        unsigned char fsifill2[12];
+        unsigned char fsisig3[4];
+        unsigned char fsifill3[508];
+        unsigned char fsisig4[4];
+};
+
+
+// Structure of a dos directory entry.
+struct direntry {
+		unsigned char		deName[8];      // filename, blank filled
+#define SLOT_EMPTY      0x00            // slot has never been used
+#define SLOT_E5         0x05            // the real value is 0xE5
+#define SLOT_DELETED    0xE5            // file in this slot deleted
+		unsigned char		deExtension[3]; // extension, blank filled
+		unsigned char		deAttributes;   // file attributes
+#define ATTR_NORMAL     0x00            // normal file
+#define ATTR_READONLY   0x01            // file is readonly
+#define ATTR_HIDDEN     0x02            // file is hidden
+#define ATTR_SYSTEM     0x04            // file is a system file
+#define ATTR_VOLUME     0x08            // entry is a volume label
+#define ATTR_LONG_FILENAME	0x0F		// this is a long filename entry			    
+#define ATTR_DIRECTORY  0x10            // entry is a directory name
+#define ATTR_ARCHIVE    0x20            // file is new or modified
+		unsigned char        deLowerCase;    // NT VFAT lower case flags  (set to zero)
+#define LCASE_BASE      0x08            // filename base in lower case
+#define LCASE_EXT       0x10            // filename extension in lower case
+		unsigned char        deCHundredth;   // hundredth of seconds in CTime
+		unsigned char        deCTime[2];     // create time
+		unsigned char        deCDate[2];     // create date
+		unsigned char        deADate[2];     // access date
+		unsigned short        deHighClust; 	// high bytes of cluster number
+		unsigned char        deMTime[2];     // last update time
+		unsigned char        deMDate[2];     // last update date
+		unsigned short        deStartCluster; // starting cluster of file
+		unsigned long       deFileSize;  	// size of file in bytes
+};
+
+// number of directory entries in one sector
+#define DIRENTRIES_PER_SECTOR	0x10
+
+// Structure of a Win95 long name directory entry
+struct winentry {
+		unsigned char		weCnt;			// 
+#define WIN_LAST        0x40
+#define WIN_CNT         0x3f
+		unsigned char		wePart1[10];
+		unsigned char		weAttributes;
+#define ATTR_WIN95      0x0f
+		unsigned char		weReserved1;
+		unsigned char		weChksum;
+		unsigned char		wePart2[12];
+		unsigned short       	weReserved2;
+		unsigned char		wePart3[4];
+};
+
+#define WIN_ENTRY_CHARS	13      // Number of chars per winentry
+
+// Maximum filename length in Win95
+// Note: Must be < sizeof(dirent.d_name)
+#define WIN_MAXLEN      255
+
+// This is the format of the contents of the deTime field in the direntry
+// structure.
+// We don't use bitfields because we don't know how compilers for
+// arbitrary machines will lay them out.
+#define DT_2SECONDS_MASK        0x1F    // seconds divided by 2
+#define DT_2SECONDS_SHIFT       0
+#define DT_MINUTES_MASK         0x7E0   // minutes
+#define DT_MINUTES_SHIFT        5
+#define DT_HOURS_MASK           0xF800  // hours
+#define DT_HOURS_SHIFT          11
+
+// This is the format of the contents of the deDate field in the direntry
+// structure.
+#define DD_DAY_MASK				0x1F	// day of month
+#define DD_DAY_SHIFT			0
+#define DD_MONTH_MASK			0x1E0	// month
+#define DD_MONTH_SHIFT			5
+#define DD_YEAR_MASK			0xFE00	// year - 1980
+#define DD_YEAR_SHIFT			9
+
+
+#define FLAGS_ATRMEDIUMSIZE		0x80
+#define FLAGS_XEXLOADER			0x40
+#define FLAGS_ATRDOUBLESECTORS	0x20
+#define FLAGS_XFDTYPE			0x10
+#define FLAGS_READONLY			0x08
+#define FLAGS_WRITEERROR		0x04
+#define FLAGS_DRIVEON			0x01
+
+// Stuctures
+typedef struct						//2+2+2+2+2+4+1=15
+{
+	unsigned short start_cluster;		//< file starting cluster
+	unsigned short dir_cluster;
+	unsigned short current_cluster;
+	unsigned short ncluster;
+	unsigned short file_index;			//< file index
+	unsigned long size;					//< file size
+	unsigned char flags;				//< file flags
+}virtual_disk_t;
+
+struct FileInfoStruct
+{
+	unsigned char Attr;				//< file attr for last file accessed
+	unsigned short Date;			//< last update date
+	unsigned short Time;			//< last update time
+	unsigned char percomstate;		//=0 default, 1=percomwrite ok (single sectors), 2=percomwrite ok (double sectors), 3=percomwrite bad
+	//
+	virtual_disk_t vDisk;
+};
+
+struct GlobalSystemValues			//4+4+2+2+1=13 bytes
+{
+	unsigned long FirstFATSector;
+	unsigned long FirstDataSector;
+	unsigned short RootDirSectors;
+	unsigned short BytesPerSector;
+	unsigned char SectorsPerCluster;
+};
+
+#define FirstFATSector		GS.FirstFATSector
+#define FirstDataSector		GS.FirstDataSector
+#define RootDirSectors		GS.RootDirSectors
+#define BytesPerSector		GS.BytesPerSector
+#define SectorsPerCluster	GS.SectorsPerCluster
+
+
+unsigned char fatInit();
+unsigned long fatClustToSect(unsigned short clust);
+unsigned char fatChangeDirectory(unsigned short entry);
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names);
+unsigned short nextCluster(unsigned short cluster);
+
+#endif
Index: unmerged/zpu_firmware/de1_old/main.c
===================================================================
--- unmerged/zpu_firmware/de1_old/main.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/main.c	(revision 1)
@@ -0,0 +1,1166 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (reset_n == 1)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<7;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	unsigned int volatile * config_6502 = (unsigned int *)(0*4+regbase);
+
+	if (pause == 0)
+		*config_6502 = 0;
+	else
+		*config_6502 = 1<<6;
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+
+	if ((1&*zpu_key) == 1)
+	{
+		// stop 6502
+		pause_6502(1);
+
+		// write a display list in page 6 (TODO, backup first...)
+		*((volatile unsigned char *)(0x600 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x601 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x602 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x603 + 0x10000)) = 0x42;
+		*((volatile unsigned char *)(0x604 + 0x10000)) = 0x40;
+		*((volatile unsigned char *)(0x605 + 0x10000)) = 0x06;
+		*((volatile unsigned char *)(0x606 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x607 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x608 + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x609 + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60a + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60b + 0x10000)) = 0x2;
+		*((volatile unsigned char *)(0x60c + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60d + 0x10000)) = 0x70;
+		*((volatile unsigned char *)(0x60e + 0x10000)) = 0x41;
+		*((volatile unsigned char *)(0x60f + 0x10000)) = 0x00;
+		*((volatile unsigned char *)(0x610 + 0x10000)) = 0x06;
+
+		*((volatile unsigned char *)(0x640 + 0x10000)) = 'H';
+		*((volatile unsigned char *)(0x641 + 0x10000)) = 'E';
+		*((volatile unsigned char *)(0x642 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x643 + 0x10000)) = 'L';
+		*((volatile unsigned char *)(0x644 + 0x10000)) = 'O';
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+
+		// wait 10 seconds
+		for (i=0; i!=10000; ++i)
+		{
+			*atari_colbk = *atari_random;
+			wait_us(1000);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		int fileno;
+		int skip;
+		int plotted = 0;
+		unsigned char volatile * mem;
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		for (;;)
+		{
+			int i = 0;
+			int go = 0;
+			fileno = 0;
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			if (FR_OK != pf_opendir(&dir,"/"))
+			{
+				debug("opendir failed\n");
+				while(1);
+			}
+
+			plotted = 0;
+			skip = 0;
+			if (selfileno>20)
+			{
+				skip = selfileno-20;
+				skip&=0xfffffffe;
+			}
+			if (selfileno<0)
+			{
+				selfileno = 0;
+			}
+			while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+			{
+				if (filinfo.fattrib & AM_SYS)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_HID)
+				{
+					continue;
+				}
+				if (filinfo.fattrib & AM_DIR)
+				{
+					debug("DIR ");
+				}
+				if (selfileno == fileno)
+				{
+					for (i=0;i!=256;++i)
+					{
+						atari_sector_buffer[i] = filinfo.fname[i];
+						if (0==filinfo.fname[i]) break;
+						filinfo.fname[i]+=128;
+					}
+				}
+				if (--skip<0)
+				{
+					debug(filinfo.fname);
+					++plotted;
+					if (plotted&1)
+					{
+						setxpos(20);
+					}
+					else
+					{
+						debug("\n");
+					}
+					if (plotted==40)
+					{
+						break;
+					}
+				}
+				fileno++;
+			}
+			debug("\n");
+			setypos(21);
+			openfile(atari_sector_buffer);
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					selfileno+=2;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					selfileno-=2;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					selfileno|=1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					selfileno&=0xfffffffe;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+			if (go == 1)
+			{
+				debug("Booting...");
+				wait_us(500000);
+
+				// reset process
+				reset_6502(0);
+				*atari_nmien = 0x00;
+				clear_64k_ram();
+				reset_6502(1);
+				break;
+			}
+			wait_us(80000);
+		}
+		initdebug(debugmode);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	speed = speedslow;
+	if (2==(2&(*zpu_switches)))
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+
+		wait_us(2000000);
+	}
+
+	if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	do
+	{
+		mmcInit();
+	}
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	openfile("BOOT.ATR");
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId == 0x31)
+ 	 	{
+			int sent = 0;
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/zpu_firmware/de1_old/mt6502dis
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/mt6502dis
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
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+application/octet-stream
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Index: unmerged/zpu_firmware/de1_old/pff.h
===================================================================
--- unmerged/zpu_firmware/de1_old/pff.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/zpu_firmware/de1_old/rom_prologue.vhd
===================================================================
--- unmerged/zpu_firmware/de1_old/rom_prologue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/zpu_firmware/de1_old/standalone_simple.ld
===================================================================
--- unmerged/zpu_firmware/de1_old/standalone_simple.ld	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/zpu_firmware/de1_old/fat.c
===================================================================
--- unmerged/zpu_firmware/de1_old/fat.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/fat.c	(revision 1)
@@ -0,0 +1,445 @@
+/*! \file fat.c \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.c'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// This code is based in part on work done by Jesper Hansen for his
+//		YAMPP MP3 player project.
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include <stdio.h>
+#include <string.h>
+
+#include "fat.h"
+#include "mmc.h"
+#include "spi.h"
+
+void USART_SendString(char *buff);
+void mmcReadCached(u32 sector);
+
+
+#define FileNameBuffer atari_sector_buffer
+extern unsigned char atari_sector_buffer[256];
+extern unsigned char mmc_sector_buffer[512];	// one sector
+extern struct GlobalSystemValues GS;
+extern struct FileInfoStruct FileInfo;			//< file information for last file accessed
+
+
+unsigned long fatClustToSect(unsigned short clust)
+{
+	u32 ret;
+	if(clust==MSDOSFSROOT)
+	{
+		debug("fatClustToSect:");
+		u32 res = (u32)((u32)(FirstDataSector) - (u32)(RootDirSectors));
+		plotnextnumber(res);
+		debug(" ");
+		plotnextnumber(FirstDataSector);
+		debug(" ");
+		plotnextnumber(RootDirSectors);
+		debug("\n");
+		return res;
+	}
+	
+	ret = (u32)(clust-2);
+	ret *= (u32)SectorsPerCluster;
+	ret += (u32)FirstDataSector;
+	return ((unsigned long)ret);
+}
+
+
+//POZOR - DEBUG !!!
+//prvne definovana promenna
+u32 debug_endofvariables;		//promenna co je v pameti jako posledni (za ni je uz jen stack)
+//POZOR - DEBUG !!!
+
+unsigned short last_dir_start_cluster;
+unsigned char last_dir_valid;
+unsigned short last_dir_entry;
+unsigned long last_dir_sector;
+unsigned char last_dir_sector_count;
+unsigned short last_dir_cluster;
+unsigned char last_dir_index;
+
+
+unsigned char fatInit()
+{
+	struct partrecord PartInfo;
+	struct bpb710 *bpb;
+
+	// Moved here since init vars are in ROM!
+	last_dir_entry=0x0;
+	last_dir_sector=0;
+	last_dir_sector_count=0;
+	last_dir_cluster=0;
+	last_dir_index=0;
+
+	// read partition table
+	// TODO.... error checking
+	debug("FAT INIT:");
+	mmcReadCached(0);
+	// map first partition record	
+	// save partition information to global PartInfo
+	PartInfo = *((struct partrecord *) ((struct partsector *) (char*)mmc_sector_buffer)->psPart);
+
+	if(mmc_sector_buffer[0x36]=='F' && mmc_sector_buffer[0x37]=='A' && mmc_sector_buffer[0x38]=='T' && mmc_sector_buffer[0x39]=='1' && mmc_sector_buffer[0x3a]=='6')
+	{
+		PartInfo.prPartType = PART_TYPE_FAT16LBA; //0x04
+		PartInfo.prStartLBA = 0x00;
+	}
+	
+	// Read the Partition BootSector
+	// **first sector of partition in PartInfo.prStartLBA
+	mmcReadCached(PartInfo.prStartLBA);
+	bpb = (struct bpb710 *) ((struct bootsector710 *) (char*)mmc_sector_buffer)->bsBPB;
+
+	// setup global disk constants
+	PartInfo.prStartLBA = 0x1e8; // FIXME
+	FirstDataSector	= PartInfo.prStartLBA;
+
+	RootDirSectors = bpb->bpbRootDirEnts>>4; // /16 ; 512/16 = 32  (sector size / max entries in one sector = number of sectors)
+
+	debug("PartInto ");
+	plotnextnumber(PartInfo.prStartLBA);
+	debug(" ");
+	plotnextnumber(bpb->bpbRootDirEnts>>4);
+	debug("\n");
+
+	// bpbFATsecs is non-zero and is therefore valid
+	FirstDataSector	+= bpb->bpbResSectors + bpb->bpbFATs * bpb->bpbFATsecs + RootDirSectors;
+
+	SectorsPerCluster	= bpb->bpbSecPerClust;
+	BytesPerSector		= bpb->bpbBytesPerSec;
+	FirstFATSector		= bpb->bpbResSectors + PartInfo.prStartLBA;
+
+	// set current directory to root (\)
+	FileInfo.vDisk.dir_cluster = MSDOSFSROOT; //RootDirStartCluster;
+
+    last_dir_start_cluster=0xffff;
+	//last_dir_valid=0;		//<-- neni potreba, protoze na zacatku fatGetDirEntry se pri zjisteni
+							//ze je (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+							//vynuluje last_dir_valid=0;
+
+	if (   PartInfo.prPartType==PART_TYPE_DOSFAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16LBA
+	   )
+	{
+		return 1; //je to ok
+		debug("OK\n");
+	}
+	else
+	{
+		return 0; //neni to zadny filesystem co umime
+		debug("FAIL\n");
+	}
+}
+
+//////////////////////////////////////////////////////////////
+
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names)
+{
+	unsigned long sector;
+	struct direntry *de = 0;	// avoid compiler warning by initializing
+	struct winentry *we;
+	unsigned char haveLongNameEntry;
+	unsigned char gotEntry;
+	unsigned short b;
+	u08 index;
+	unsigned short entrycount = 0;
+	unsigned short actual_cluster = FileInfo.vDisk.dir_cluster;
+	unsigned char seccount=0;
+
+	haveLongNameEntry = 0;
+	gotEntry = 0;
+
+	if (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+	{
+		//zmenil se adresar, takze musi pracovat s nim
+		//a zneplatnit last_dir polozky
+		last_dir_start_cluster=FileInfo.vDisk.dir_cluster;
+		last_dir_valid=0;
+
+		debug("LastDirStartCluster:");
+		plotnextnumber(last_dir_start_cluster);
+		plotnextnumber(last_dir_valid);
+		debug("\n");
+	}
+
+	if ( !last_dir_valid
+		 || (entry<=last_dir_entry && (entry!=last_dir_entry || last_dir_valid!=1 || use_long_names!=0))
+	   )
+	{
+		//musi zacit od zacatku
+		sector = fatClustToSect(FileInfo.vDisk.dir_cluster);
+		//index = 0;
+		debug("ReadFromBegin:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_begin;
+	}
+	else
+	{
+		//muze zacit od posledne pouzite
+		entrycount=last_dir_entry;
+		index = last_dir_index;
+		sector=last_dir_sector;
+		actual_cluster=last_dir_cluster;
+		seccount = last_dir_sector_count;
+		debug("ReadFromLastEntry:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_last_entry;
+	}
+
+	while(1)
+	{
+		debug("Index:");
+		plotnextnumber(index);
+		debug("\n");
+		if(index==16)	// time for next sector ?
+		{
+			if ( actual_cluster==MSDOSFSROOT )
+			{
+				//v MSDOSFSROOT se nerozlisuji clustery
+				//protoze MSDOSFSROOT ma sektory stale dal za sebou bez clusterovani
+				if (seccount>=RootDirSectors) return 0; //prekrocil maximalni pocet polozek v MSDOSFSROOT
+			}
+			else //MUSI BYT!!! (aby neporovnaval seccount je-li actual_cluster==MSDOSFSROOT)
+			if( seccount>=SectorsPerCluster )
+			{
+				//next cluster
+				//pri prechodu pres pocet sektoru v clusteru
+				actual_cluster = nextCluster(actual_cluster);
+				sector=fatClustToSect(actual_cluster);
+				seccount=0;
+			}
+fat_read_from_begin:
+			index = 0;
+			seccount++;		//ted bude nacitat dalsi sektor (musi ho zapocitat)
+fat_read_from_last_entry:
+			mmcReadCached( sector++ ); 	//prave ho nacetl
+			de = (struct direntry *) (char*)mmc_sector_buffer;
+			de+=index;
+		}
+		
+		// check the status of this directory entry slot
+		if(de->deName[0] == 0x00) //SLOT_EMPTY
+		{
+			// slot is empty and this is the end of directory
+			gotEntry = 0;
+			break;
+		}
+		else if(de->deName[0] == 0xE5)	//SLOT_DELETED
+		{
+			// this is an empty slot
+			// do nothing and move to the next one
+		}
+		else
+		{
+			// this is a valid and occupied entry
+			// is it a part of a long file/dir name?
+			if( de->deAttributes==ATTR_LONG_FILENAME )
+			{
+				// we have a long name entry
+				// cast this directory entry as a "windows" (LFN: LongFileName) entry
+				u08 i;
+				unsigned char *fnbPtr;
+
+				//pokud nechceme longname, NESMI je vubec kompletovat
+				//a preskoci na dalsi polozku
+				//( takze ani haveLongNameEntry nikdy nebude nastaveno na 1)
+				//Jinak by totiz preplacaval dalsi kusy atari_sector_bufferu 12-255 ! BACHA!!!
+				if (!use_long_names) goto fat_next_dir_entry;
+
+				we = (struct winentry *) de;
+				
+				b = WIN_ENTRY_CHARS*( (unsigned short)((we->weCnt-1) & 0x0f));		// index into string
+				fnbPtr = &FileNameBuffer[b];
+
+				for (i=0;i<5;i++)	*fnbPtr++ = we->wePart1[i*2];	// copy first part
+				for (i=0;i<6;i++)	*fnbPtr++ = we->wePart2[i*2];	// second part
+				for (i=0;i<2;i++)	*fnbPtr++ = we->wePart3[i*2];	// and third part
+
+				/*
+				{
+				//unsigned char * sptr;
+				//sptr=we->wePart1;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart1+10)); // copy first part
+				//^-- pouziti jen tohoto prvniho a druhe dva pres normalni for(..) uspori 10 bajtu,
+				//pri pouziti i dalsich dvou timto stylem uz se to ale zase prodlouzi - nechaaaaaapu!
+				//sptr=we->wePart2;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart2+12)); // second part
+				//sptr=we->wePart3;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart3+4));  // and third part
+				}
+				*/
+
+				if (we->weCnt & WIN_LAST) *fnbPtr = 0;				// in case dirnamelength is multiple of 13, add termination
+				if ((we->weCnt & 0x0f) == 1) haveLongNameEntry = 1;	// flag that we have a complete long name entry set
+			}
+			else
+			{
+				// we have a short name entry
+				
+				// check if this is the short name entry corresponding
+				// to the end of a multi-part long name entry
+				if(haveLongNameEntry)
+				{
+					// a long entry name has been collected
+					if(entrycount == entry)		
+					{
+						// desired entry has been found, break out
+						gotEntry = 2;
+						break;
+					}
+					// otherwise
+					haveLongNameEntry = 0;	// clear long name flag
+					entrycount++;			// increment entry counter		
+				}
+				else
+				{
+					// entry is a short name (8.3 format) without a
+					// corresponding multi-part long name entry
+
+					//Zcela vynecha adresar "." a disk label
+					if( (de->deName[0]=='.' && de->deName[1]==' ' && (de->deAttributes & ATTR_DIRECTORY) ) //je to "." adresar
+						|| (de->deAttributes & ATTR_VOLUME) ) goto fat_next_dir_entry;
+
+					if(entrycount == entry)
+					{
+						/*
+						fnbPtr = &FileNameBuffer[string_offset];
+						for (i=0;i<8;i++)	*fnbPtr++ = de->deName[i];		// copy name
+						for (i=0;i<3;i++)	*fnbPtr++ = de->deExtension[i];	// copy extension
+						*fnbPtr = 0;										// null-terminate
+						*/
+						u08 i;
+						unsigned char *dptr;
+
+						dptr = &FileNameBuffer;
+						for (i=0;i<11;i++)	*dptr++ = de->deName[i];		// copy name+ext
+						*dptr=0;	//ukonceni za nazvem
+
+						// desired entry has been found, break out
+						//pokud chtel longname, tak to neni a proto upravi 8+3 jmeno na nazev.ext
+						//aby to melo formatovani jako longname
+						if (use_long_names)
+						{
+							//upravi 'NAME    EXT' na 'NAME.EXT'
+							//(vyhazi mezery a prida tecku)
+							//krome nazvu '.          ', a '..         ', tam jen vyhaze mezery
+							unsigned char *sptr;
+							//EXT => .EXT   (posune vcetne 0x00 za koncem extenderu)
+							dptr=(FileNameBuffer+12);
+							i=4; do { sptr=dptr-1; *dptr=*sptr; dptr=sptr; i--; } while(i>0);
+							if (FileNameBuffer[0]!='.') *dptr='.'; //jen pro jine nez '.' a '..'
+							//NAME    .EXT => NAME.EXT
+							sptr=dptr=&FileNameBuffer;
+							do
+							{
+							 if ((*sptr)!=' ') *dptr++=*sptr;
+							 sptr++;
+							} while (*sptr);
+							*dptr=0; //ukonceni
+						}
+						//
+						gotEntry = 1;
+						break;
+					}
+					// otherwise
+					entrycount++;			// increment entry counter		
+				}
+			}
+		}
+fat_next_dir_entry:
+		// next directory entry
+		de++;
+		// next index
+		index++;
+	}
+	
+	// we have a file/dir to return
+	// store file/dir starting cluster (start of data)
+	FileInfo.vDisk.start_cluster = (unsigned short) (de->deStartCluster);
+	// fileindex
+	FileInfo.vDisk.file_index = entry;	//fileindex teto polozky
+	// store file/dir size (note: size field for subdirectory entries is always zero)
+	FileInfo.vDisk.size = de->deFileSize;
+	// store file/dir attributes
+	FileInfo.Attr = de->deAttributes;
+	// store file/dir last update time
+	FileInfo.Time = (unsigned short) (de->deMTime[0] | de->deMTime[1]<<8);
+	// store file/dir last update date
+	FileInfo.Date = (unsigned short) (de->deMDate[0] | de->deMDate[1]<<8);
+
+	if(gotEntry)
+	{
+		debug(" gotEntry ");
+		last_dir_entry = entrycount;
+		last_dir_index = index;
+		last_dir_sector = sector-1; //protoze ihned po nacteni se posune
+		last_dir_cluster = actual_cluster;
+		last_dir_sector_count = seccount; //skace se az za inkrementaci seccount, takze tady se 1 neodecita!
+		last_dir_valid=gotEntry;
+	}
+	else
+	{
+		debug(" not gotEntry ");
+	}
+
+	return gotEntry;
+}
+
+
+unsigned short nextCluster(unsigned short cluster)
+{
+	  unsigned short nextCluster;
+	  unsigned long fatOffset;
+	  unsigned long sector;
+	  unsigned long offset;
+
+	  // two FAT bytes (16 bits) for every cluster
+	  fatOffset = ((u32)cluster) << 1;
+
+	  // calculate the FAT sector that we're interested in
+	  sector = FirstFATSector + (fatOffset / ((u32)BytesPerSector));
+	  // calculate offset of the our entry within that FAT sector
+	  offset = fatOffset % ((u32)BytesPerSector);
+
+	  // if we don't already have this FAT chunk loaded, go get it
+	  // read sector of FAT table
+  	  mmcReadCached( sector );
+
+	  // read the nextCluster value
+	  nextCluster = (*((unsigned short*) &((char*)mmc_sector_buffer)[offset])) & FAT16_MASK;
+
+	  // check to see if we're at the end of the chain
+	  if (nextCluster == (CLUST_EOFE & FAT16_MASK))
+		nextCluster = 0;
+
+	return (nextCluster&0xFFFF);
+}
Index: unmerged/zpu_firmware/de1_old/led.h
===================================================================
--- unmerged/zpu_firmware/de1_old/led.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/zpu_firmware/de1_old/mmcconf.h
===================================================================
--- unmerged/zpu_firmware/de1_old/mmcconf.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/mmcconf.h	(revision 1)
@@ -0,0 +1,33 @@
+/*! \file mmcconf.h \brief MultiMedia and SD Flash Card Interface Configuration. */
+//*****************************************************************************
+//
+// File Name	: 'mmcconf.h'
+// Title		: MultiMedia and SD Flash Card Interface Configuration
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef MMCCONF_H
+#define MMCCONF_H
+
+#endif
Index: unmerged/zpu_firmware/de1_old/pff.c
===================================================================
--- unmerged/zpu_firmware/de1_old/pff.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/zpu_firmware/de1_old/rom_epilogue.vhd
===================================================================
--- unmerged/zpu_firmware/de1_old/rom_epilogue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/zpu_firmware/de1_old/spi.h
===================================================================
--- unmerged/zpu_firmware/de1_old/spi.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/spi.h	(revision 1)
@@ -0,0 +1,65 @@
+/*! \file spi.h \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.h'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup driver_avr
+/// \defgroup spi SPI (Serial Peripheral Interface) Function Library (spi.c)
+/// \code #include "spi.h" \endcode
+/// \par Overview
+///		Provides basic byte and word transmitting and receiving via the AVR
+///	SPI interface.� Due to the nature of SPI, every SPI communication operation
+/// is both a transmit and simultaneous receive.
+///
+///	\note Currently, only MASTER mode is supported.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef SPI_H
+#define SPI_H
+
+#include "types.h"
+
+// function prototypes
+void mmcChipSelect(int select);
+
+
+// SPI interface initializer
+void spiInit(void);
+
+// spiTransferByte(u08 data) waits until the SPI interface is ready
+// and then sends a single byte over the SPI port.  The function also
+// returns the byte that was received during transmission.
+u08 spiTransferByte(u08 data);
+
+// spiTransferWord(u08 data) works just like spiTransferByte but
+// operates on a whole word (16-bits of data).
+u08 spiTransferFF();
+void spiTransferTwoFF();
+
+void spiDisplay(int i);
+
+#endif
Index: unmerged/zpu_firmware/de1_old/types.h
===================================================================
--- unmerged/zpu_firmware/de1_old/types.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/zpu_firmware/de1_old/diskio.h
===================================================================
--- unmerged/zpu_firmware/de1_old/diskio.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/zpu_firmware/de1_old/led.c
===================================================================
--- unmerged/zpu_firmware/de1_old/led.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/zpu_firmware/de1_old/mmc.h
===================================================================
--- unmerged/zpu_firmware/de1_old/mmc.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/mmc.h	(revision 1)
@@ -0,0 +1,145 @@
+/*! \file mmc.h \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.h'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+///	\ingroup driver_hw
+/// \defgroup mmc MultiMedia and SD Flash Card Interface (mmc.c)
+/// \code #include "mmc.h" \endcode
+/// \par Description
+///		This library offers some simple functions which can be used
+///		to read and write data on a MultiMedia or SecureDigital (SD) Flash
+///		Card.  Although MM and SD Cards are designed to operate with their own
+///		special bus wiring and protocols, both types of cards also provide a
+///		simple SPI-like interface mode which is exceptionally useful when 
+///		attempting to use the cards in embedded systems.
+///
+/// \par Wiring
+///		To work with this library, the card must be wired to the SPI port of
+///		the Atmel microcontroller as described below.  Typical cards can
+///		operate at up to 25MHz maximum SPI clock rate (thus faster than most
+///		AVR's maximum SPI clock rate).
+/// <pre>
+///	      _________________
+///	     /  1 2 3 4 5 6 78 |	<- view of MMC/SD card looking at contacts
+///	    / 9                |	Pins 8 and 9 are present only on SD cards
+///	    |    MMC/SD Card   |
+///	    |                  |
+///	    --------------------
+///	    1 - CS   (chip select)          - wire to any available I/O pin(*)
+///	    2 - DIN  (data in, card<-host)  - wire to SPI MOSI pin
+///	    3 - VSS  (ground)               - wire to ground
+///	    4 - VDD  (power, 3.3V only?)    - wire to power (MIGHT BE 3.3V ONLY!)
+///	    5 - SCLK (data clock)           - wire to SPI SCK pin
+///	    6 - VSS  (ground)               - wire to ground
+///	    7 - DOUT (data out, card->host) - wire to SPI MISO pin
+///
+///	    (*) you must define this chip select I/O pin in mmcconf.h
+/// </pre>
+/// \note This code is currently below version 1.0, and therefore is considered
+/// to be lacking in some functionality or documentation, or may not be fully
+/// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "types.h"
+
+// constants/macros/typdefs
+// MMC commands (taken from sandisk MMC reference)
+#define MMC_GO_IDLE_STATE			0		///< initialize card to SPI-type access
+#define MMC_SEND_OP_COND			1		///< set card operational mode
+#define MMC_SEND_CSD				9		///< get card's CSD
+#define MMC_SEND_CID				10		///< get card's CID
+#define MMC_SEND_STATUS				13
+#define MMC_SET_BLOCKLEN			16		///< Set number of bytes to transfer per block
+#define MMC_READ_SINGLE_BLOCK		17		///< read a block
+#define MMC_WRITE_BLOCK				24		///< write a block
+#define MMC_PROGRAM_CSD				27
+#define MMC_SET_WRITE_PROT			28
+#define MMC_CLR_WRITE_PROT			29
+#define MMC_SEND_WRITE_PROT			30
+#define MMC_TAG_SECTOR_START		32
+#define MMC_TAG_SECTOR_END			33
+#define MMC_UNTAG_SECTOR			34
+#define MMC_TAG_ERASE_GROUP_START 	35		///< Sets beginning of erase group (mass erase)
+#define MMC_TAG_ERARE_GROUP_END		36		///< Sets end of erase group (mass erase)
+#define MMC_UNTAG_ERASE_GROUP		37		///< Untag (unset) erase group (mass erase)
+#define MMC_ERASE					38		///< Perform block/mass erase
+#define MMC_CRC_ON_OFF				59		///< Turns CRC check on/off
+// R1 Response bit-defines
+#define MMC_R1_BUSY					0x80	///< R1 response: bit indicates card is busy
+#define MMC_R1_PARAMETER			0x40
+#define MMC_R1_ADDRESS				0x20
+#define MMC_R1_ERASE_SEQ			0x10
+#define MMC_R1_COM_CRC				0x08
+#define MMC_R1_ILLEGAL_COM			0x04
+#define MMC_R1_ERASE_RESET			0x02
+#define MMC_R1_IDLE_STATE			0x01
+// Data Start tokens
+#define MMC_STARTBLOCK_READ			0xFE	///< when received from card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_WRITE		0xFE	///< when sent to card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_MWRITE		0xFC
+// Data Stop tokens
+#define MMC_STOPTRAN_WRITE			0xFD
+// Data Error Token values
+#define MMC_DE_MASK					0x1F
+#define MMC_DE_ERROR				0x01
+#define MMC_DE_CC_ERROR				0x02
+#define MMC_DE_ECC_FAIL				0x04
+#define MMC_DE_OUT_OF_RANGE			0x04
+#define MMC_DE_CARD_LOCKED			0x04
+// Data Response Token values
+#define MMC_DR_MASK					0x1F
+#define MMC_DR_ACCEPT				0x05
+#define MMC_DR_REJECT_CRC			0x0B
+#define MMC_DR_REJECT_WRITE_ERROR	0x0D
+
+// functions
+
+//! Initialize AVR<->MMC hardware interface.
+/// Prepares hardware for MMC access.
+void mmcInit(void);
+
+//! Initialize the card and prepare it for use.
+/// Returns zero if successful.
+u08 mmcReset(void);
+
+//! Send card an MMC command.
+/// Returns R1 result code.
+u08 mmcSendCommand(u08 cmd, u32 arg);
+
+//! Read 512-byte sector from card to buffer
+/// Returns zero if successful.
+u08 mmcRead(u32 sector);
+
+//! Write 512-byte sector from buffer to card
+/// Returns zero if successful.
+u08 mmcWrite(u32 sector);
+
+//! Internal command function.
+/// Issues a generic MMC command as specified by cmd and arg.
+u08 mmcCommand(u08 cmd, u32 arg);
+
+#endif
Index: unmerged/zpu_firmware/de1_old/pause.h
===================================================================
--- unmerged/zpu_firmware/de1_old/pause.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/zpu_firmware/de1_old/regs.h
===================================================================
--- unmerged/zpu_firmware/de1_old/regs.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/regs.h	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_dmactl;
+
+#endif // regs_h
Index: unmerged/zpu_firmware/de1_old/spi.c
===================================================================
--- unmerged/zpu_firmware/de1_old/spi.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/spi.c	(revision 1)
@@ -0,0 +1,116 @@
+/*! \file spi.c \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.c'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include "spi.h"
+
+#include "regs.h"
+#include "spi.h"
+
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+	updateSpiState();
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+	updateSpiState();
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+}
+
Index: unmerged/zpu_firmware/de1_old/test.c
===================================================================
--- unmerged/zpu_firmware/de1_old/test.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/test.c	(revision 1)
@@ -0,0 +1,71 @@
+
+
+unsigned char toatarichar(int val)
+{
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else
+	{
+		val = 0;
+	}
+	return val;
+}
+
+int xpos = 0;
+int ypos = 0;
+
+void nextline()
+{
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+}
+void plot(unsigned char a, int x, int y)
+{
+	printf("%d %d %d\n",a,x,y);
+}
+
+void debug(char const * str)
+{
+//        char buffer[256];
+//        buffer[0] = 'W';
+//        buffer[1] = 'T';
+//        buffer[2] = 'F';
+//        buffer[3] = 0;
+//        str = buffer;
+
+        while (1)
+        {
+                int val = *str++;
+                if (val==0) break;
+
+                plot(toatarichar(val),xpos,ypos);
+                ++xpos;
+                if (xpos==40)
+                {
+                        nextline();
+                }
+        }
+        nextline();
+        //Delay100usX(10000);
+}
+
+
+int main(void)
+{
+	printf("%d %d\n", 'H', toatarichar('H'));
+	debug("Goodbye sweet world!");
+	return 0;
+}
+
Index: unmerged/zpu_firmware/de1_old/zpuromgen
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/de1_old/zpuromgen
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/de1_replaysvn/bootdump.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/bootdump.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/zpu_firmware/de1_replaysvn/integer.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/integer.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/zpu_firmware/de1_replaysvn/mmc.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/mmc.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/mmc.c	(revision 1)
@@ -0,0 +1,269 @@
+/*! \file mmc.c \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.c'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+//----- Include Files ---------------------------------------------------------
+#include "spi.h"		// include spi bus support
+
+
+//#define spiTransferTwoFF()	{ spiTransferFF(); spiTransferFF(); }
+
+
+#include "mmc.h"
+
+// include project-specific hardware configuration
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+	// initialize SPI interface
+	spiInit();
+	// release chip select
+	mmcChipSelect(0);
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(1);
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+	u08 retry=0xff;	//255x
+	//
+
+	spiTransferFF();
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+	//
+	spiTransferByte(arg>>24);
+	spiTransferByte(arg>>16);
+	spiTransferByte(arg>>8);
+	spiTransferByte(arg);
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+		retry--;
+	}
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
Index: unmerged/zpu_firmware/de1_replaysvn/pause.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/pause.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/zpu_firmware/de1_old/debug.h
===================================================================
--- unmerged/zpu_firmware/de1_old/debug.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/debug.h	(revision 1)
@@ -0,0 +1,19 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/zpu_firmware/de1_old/integer.h
===================================================================
--- unmerged/zpu_firmware/de1_old/integer.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/zpu_firmware/de1_old/mmc.c
===================================================================
--- unmerged/zpu_firmware/de1_old/mmc.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/mmc.c	(revision 1)
@@ -0,0 +1,269 @@
+/*! \file mmc.c \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.c'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+//----- Include Files ---------------------------------------------------------
+#include "spi.h"		// include spi bus support
+
+
+//#define spiTransferTwoFF()	{ spiTransferFF(); spiTransferFF(); }
+
+
+#include "mmc.h"
+
+// include project-specific hardware configuration
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+	// initialize SPI interface
+	spiInit();
+	// release chip select
+	mmcChipSelect(0);
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(1);
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+	u08 retry=0xff;	//255x
+	//
+
+	spiTransferFF();
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+	//
+	spiTransferByte(arg>>24);
+	spiTransferByte(arg>>16);
+	spiTransferByte(arg>>8);
+	spiTransferByte(arg);
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+		retry--;
+	}
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
Index: unmerged/zpu_firmware/de1_old/mycrt0.s
===================================================================
--- unmerged/zpu_firmware/de1_old/mycrt0.s	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/zpu_firmware/de1_old/regs.c
===================================================================
--- unmerged/zpu_firmware/de1_old/regs.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/regs.c	(revision 1)
@@ -0,0 +1,46 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+
+#endif // regs_h
Index: unmerged/zpu_firmware/de1_old/setup
===================================================================
--- unmerged/zpu_firmware/de1_old/setup	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/zpu_firmware/de1_old/stuff.c
===================================================================
--- unmerged/zpu_firmware/de1_old/stuff.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/stuff.c	(revision 1)
@@ -0,0 +1,13 @@
+#include "regs.h"
+#include "regs.c"
+#include "main.c"
+#include "fat.c" 
+#include "SDrive.c"
+#include "mmc.c"
+#include "spi.c"
+#include "uart.c"
+#include "led.c"
+#include "pind.c" 
+#include "eeprom.c"
+#include "pause.c"
+
Index: unmerged/zpu_firmware/de1_old/uart.h
===================================================================
--- unmerged/zpu_firmware/de1_old/uart.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/zpu_firmware/de1_replaysvn/Makefile
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/Makefile	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c mmc.c    spi.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/zpu_firmware/de1_replaysvn/diskio.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/diskio.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/zpu_firmware/de1_replaysvn/main.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/main.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/main.c	(revision 1)
@@ -0,0 +1,1511 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+int opendrive;
+char filename_d1[15];
+char filename_d2[15];
+char filename_d3[15];
+char filename_d4[15];
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+int
+selectfile(char * filename)
+{
+	int fileno;
+	int skip;
+	int plotted = 0;
+	wait_us(200000);
+	for(;;)
+	{
+		int i = 0;
+		int go = 0;
+		fileno = 0;
+		topofscreen();
+		for (i=0; i!=(24*40); ++i)
+		{
+			*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+		}
+		if (FR_OK != pf_opendir(&dir,"/"))
+		{
+			debug("opendir failed\n");
+			while(1);
+		}
+
+		plotted = 0;
+		skip = 0;
+		if (selfileno>20)
+		{
+			skip = selfileno-20;
+			skip&=0xfffffffe;
+		}
+		if (selfileno<0)
+		{
+			selfileno = 0;
+		}
+		while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+		{
+			if (filinfo.fattrib & AM_SYS)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_HID)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_DIR)
+			{
+				debug("DIR ");
+			}
+			if (selfileno == fileno)
+			{
+				for (i=0;i!=15;++i)
+				{
+					filename[i] = filinfo.fname[i];
+					if (0==filinfo.fname[i]) break;
+					filinfo.fname[i]+=128;
+				}
+			}
+			if (--skip<0)
+			{
+				debug(filinfo.fname);
+				++plotted;
+				if (plotted&1)
+				{
+					setxpos(20);
+				}
+				else
+				{
+					debug("\n");
+				}
+				if (plotted==40)
+				{
+					break;
+				}
+			}
+			fileno++;
+		}
+		debug("\n");
+		setypos(21);
+		opendrive = 0;
+		openfile(filename);
+		for (;;)
+		{
+			unsigned char porta = *atari_porta;
+			if (0==(porta&0x2)) // down
+			{
+				selfileno+=2;
+				break;
+			}
+			else if (0==(porta&0x1)) // up
+			{
+				selfileno-=2;
+				break;
+			}
+			else if (0==(porta&0x8)) // right
+			{
+				selfileno|=1;
+				break;
+			}
+			else if (0==(porta&0x4)) // left
+			{
+				selfileno&=0xfffffffe;
+				break;
+			}
+			else if (0==(*atari_trig0)) // fire
+			{
+				go = 1;
+				while(0==(*atari_trig0));
+				break;
+			}
+			topofscreen();
+			//plotnextnumber(porta);
+			*atari_colbk = *atari_random;
+			//wait_us(200);
+		}
+		if (go == 1)
+		{
+			wait_us(200000);
+			return validfile; // TODO, another way to quit without selecting...
+		}
+		wait_us(80000);
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	int prev = *zpu_config;
+	if (reset_n == 1)
+		*zpu_config = prev&~(1<<7);
+	else
+		*zpu_config = prev|(1<<7);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	int prev = *zpu_config;
+	if (pause == 0)
+		*zpu_config = prev&~(1<<6);
+	else
+		*zpu_config = prev|(1<<6);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+	//unsigned volatile char * store = 0xf00000; // SDRAM - fails!!
+	unsigned volatile char * store = 0x27f000; // SRAM...
+
+	if ((1&*zpu_key) == 1)
+	{
+		unsigned char volatile * mem;
+		unsigned char store_portb;
+		int temp;
+		int row = 0;
+		int next = 0;
+		int go = 0;
+
+		// stop 6502
+		pause_6502(1);
+
+		// TODO - 
+		// menu for 64k/128k/320K Compy/320K Rambo
+		// menu for ROM bank
+		// menu for GPIO on/off
+
+		initdebug(1);
+
+		mem = 0x9c00 + 0x10000;
+		// Copy 1k from 0x$9c00 to sdram
+		// 0x200000; sram
+		// 0x800000; sdram (always use...)
+		for (i=0x0; i!=1024; i++)
+		{
+			store[i] = mem[i];
+		}
+		for (i=0x40; i!=1024; i++)
+		{
+			mem[i] = 0;
+		}
+		store_portb = *atari_portb;
+
+		// write a display list at 9c00
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x9c
+		};
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x9c;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+		*atari_portb = 0xff;
+
+		for (;;)
+		{
+			wait_us(120000);
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			// 0-5 speed
+			// 6-pause
+			// 7-reset
+			// 8-9-ram
+			// 12-13-rom
+			// 16-gpio_enable
+			debug("System settings\n");
+			debug("---------------\n");
+			debug("Memory:");
+			temp = 0xf&((*zpu_config)>>8);
+			if (row == 0)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xfffff0ff)|((temp&0x3)<<8);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("64KiB");
+				break;
+			case 1:
+				debug("128KiB");
+				break;
+			case 2:
+				debug("320KiB Compy Shop");
+				break;
+			case 3:
+				debug("320KiB Rambo");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("ROM bank:");
+			temp = 0xf&((*zpu_config)>>12);
+			if (row == 1)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xffff0fff)|((temp&0x3)<<12);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("0 (default:XL)");
+				break;
+			case 1:
+				debug("1 (default:XL + hi speed)");
+				break;
+			case 2:
+				debug("2 (default:Ultimon)");
+				break;
+			case 3:
+				debug("3 (default:OS B + hi speed)");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("Speed:");
+			temp = 0x3f&((*zpu_config)>>0);
+			if (row == 2)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					if (temp < 0) temp =0;
+					*zpu_config = (*zpu_config&0xffffffc0)|(temp&0x3f);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			plotnextnumber(57500/(temp+1));
+			debug(" KHz\nD1:"); // Bring up selector, instead of booting changes disk image
+			if (row == 3)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d1);
+			debug("\nD2:");
+			if (row == 4)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d2);
+			debug("\nD3:");
+			if (row == 5)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d3);
+			debug("\nD4:");
+			if (row == 6)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d4);
+			if (row>=3 && row<7)
+			{
+				if (go==1)
+				{
+					switch (row)
+					{
+					case 3:
+						selectfile(filename_d1);
+						break;
+					case 4:
+						selectfile(filename_d2);
+						break;
+					case 5:
+						selectfile(filename_d3);
+						break;
+					case 6:
+						selectfile(filename_d4);
+						break;
+					}
+					opendrive = row-2;
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d4[i];
+						filename_d4[i] = filename_d3[i];
+						filename_d3[i] = filename_d2[i];
+						filename_d2[i] = filename_d1[i];
+						filename_d1[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==-1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d1[i];
+						filename_d1[i] = filename_d2[i];
+						filename_d2[i] = filename_d3[i];
+						filename_d3[i] = filename_d4[i];
+						filename_d4[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+			}
+			if (row == 7)
+			{
+				debugoffset(128);
+			}
+			debug("\nReboot");
+			if (row == 7)
+			{
+				if (go==1)
+				{
+					debug("Booting...");
+					wait_us(500000);
+
+					// reset process
+					reset_6502(0);
+					*atari_nmien = 0x00;
+					clear_64k_ram();
+					reset_6502(1);
+					break;
+				}
+			}
+			if (row == 8)
+			{
+				debugoffset(128);
+			}
+			debug("\nExit");
+			if (row == 8)
+			{
+				if (go==1)
+					break;
+			}
+
+			next = 0;
+			go = 0;
+
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					row+=1;
+					if (row>8) row = 8;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					row-=1;
+					if (row<0) row = 0;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					next = 1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					next = -1;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					while(0==(*atari_trig0));
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+		}
+
+		// wait 2 seconds
+		//for (i=0; i!=2000; ++i)
+		//{
+		//	*atari_colbk = *atari_random;
+		//	wait_us(1000);
+		//}
+
+		for (i=0x040; i!=1024; i++)
+		{
+			mem[i] = store[i];
+		}
+
+		*atari_portb = store_portb;
+		initdebug(debugmode);
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		unsigned char volatile * mem;
+
+		// TODO - disk swapping!
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		if (selectfile(filename_d1))
+		{
+			opendrive = 1;
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		initdebug(debugmode);
+		pause_6502(0);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	opendrive = 0;
+	pause_6502(1);
+	speed = speedslow;
+	if (2==(2&(*zpu_switches)))
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+
+		wait_us(2000000);
+	}
+
+	if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	pause_6502(1);
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	do
+	{
+		mmcInit();
+	}
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+	char const * default_filename = "BOOT.ATR";
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	for (i=0;i!=15;++i)
+	{
+		filename_d1[i] = default_filename[i];
+		filename_d2[i] = default_filename[i];
+		filename_d3[i] = default_filename[i];
+		filename_d4[i] = default_filename[i];
+		if (default_filename[i] == 0) break;
+	}
+	opendrive = 1;
+	openfile(filename_d1);
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId >= 0x31 && command.deviceId < 0x34)
+ 	 	{
+			int sent = 0;
+			int drive = 0;
+
+			drive = command.deviceId&0xf;
+			if (drive!=opendrive)
+			{
+				opendrive = drive;
+				switch(drive)
+				{
+				case 1:
+					openfile(filename_d1);
+					break;
+				case 2:
+					openfile(filename_d2);
+					break;
+				case 3:
+					openfile(filename_d3);
+					break;
+				case 4:
+					openfile(filename_d4);
+					break;
+				}
+			}
+
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/zpu_firmware/de1_replaysvn/mycrt0.s
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/mycrt0.s	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/zpu_firmware/de1_old/uart.c
===================================================================
--- unmerged/zpu_firmware/de1_old/uart.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/de1_old/zpuromgen.c
===================================================================
--- unmerged/zpu_firmware/de1_old/zpuromgen.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_old/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/zpu_firmware/de1_replaysvn/debug.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/debug.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/debug.c	(revision 1)
@@ -0,0 +1,178 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+int debugoffsetval;
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val+debugoffsetval;
+}
+void debugoffset(int x)
+{
+	debugoffsetval = x;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+	debugoffsetval = 0;
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+	debugoffsetval = 0;
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/de1_replaysvn/led.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/led.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/zpu_firmware/de1_replaysvn/mmc.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/mmc.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/mmc.h	(revision 1)
@@ -0,0 +1,145 @@
+/*! \file mmc.h \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.h'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+///	\ingroup driver_hw
+/// \defgroup mmc MultiMedia and SD Flash Card Interface (mmc.c)
+/// \code #include "mmc.h" \endcode
+/// \par Description
+///		This library offers some simple functions which can be used
+///		to read and write data on a MultiMedia or SecureDigital (SD) Flash
+///		Card.  Although MM and SD Cards are designed to operate with their own
+///		special bus wiring and protocols, both types of cards also provide a
+///		simple SPI-like interface mode which is exceptionally useful when 
+///		attempting to use the cards in embedded systems.
+///
+/// \par Wiring
+///		To work with this library, the card must be wired to the SPI port of
+///		the Atmel microcontroller as described below.  Typical cards can
+///		operate at up to 25MHz maximum SPI clock rate (thus faster than most
+///		AVR's maximum SPI clock rate).
+/// <pre>
+///	      _________________
+///	     /  1 2 3 4 5 6 78 |	<- view of MMC/SD card looking at contacts
+///	    / 9                |	Pins 8 and 9 are present only on SD cards
+///	    |    MMC/SD Card   |
+///	    |                  |
+///	    --------------------
+///	    1 - CS   (chip select)          - wire to any available I/O pin(*)
+///	    2 - DIN  (data in, card<-host)  - wire to SPI MOSI pin
+///	    3 - VSS  (ground)               - wire to ground
+///	    4 - VDD  (power, 3.3V only?)    - wire to power (MIGHT BE 3.3V ONLY!)
+///	    5 - SCLK (data clock)           - wire to SPI SCK pin
+///	    6 - VSS  (ground)               - wire to ground
+///	    7 - DOUT (data out, card->host) - wire to SPI MISO pin
+///
+///	    (*) you must define this chip select I/O pin in mmcconf.h
+/// </pre>
+/// \note This code is currently below version 1.0, and therefore is considered
+/// to be lacking in some functionality or documentation, or may not be fully
+/// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "types.h"
+
+// constants/macros/typdefs
+// MMC commands (taken from sandisk MMC reference)
+#define MMC_GO_IDLE_STATE			0		///< initialize card to SPI-type access
+#define MMC_SEND_OP_COND			1		///< set card operational mode
+#define MMC_SEND_CSD				9		///< get card's CSD
+#define MMC_SEND_CID				10		///< get card's CID
+#define MMC_SEND_STATUS				13
+#define MMC_SET_BLOCKLEN			16		///< Set number of bytes to transfer per block
+#define MMC_READ_SINGLE_BLOCK		17		///< read a block
+#define MMC_WRITE_BLOCK				24		///< write a block
+#define MMC_PROGRAM_CSD				27
+#define MMC_SET_WRITE_PROT			28
+#define MMC_CLR_WRITE_PROT			29
+#define MMC_SEND_WRITE_PROT			30
+#define MMC_TAG_SECTOR_START		32
+#define MMC_TAG_SECTOR_END			33
+#define MMC_UNTAG_SECTOR			34
+#define MMC_TAG_ERASE_GROUP_START 	35		///< Sets beginning of erase group (mass erase)
+#define MMC_TAG_ERARE_GROUP_END		36		///< Sets end of erase group (mass erase)
+#define MMC_UNTAG_ERASE_GROUP		37		///< Untag (unset) erase group (mass erase)
+#define MMC_ERASE					38		///< Perform block/mass erase
+#define MMC_CRC_ON_OFF				59		///< Turns CRC check on/off
+// R1 Response bit-defines
+#define MMC_R1_BUSY					0x80	///< R1 response: bit indicates card is busy
+#define MMC_R1_PARAMETER			0x40
+#define MMC_R1_ADDRESS				0x20
+#define MMC_R1_ERASE_SEQ			0x10
+#define MMC_R1_COM_CRC				0x08
+#define MMC_R1_ILLEGAL_COM			0x04
+#define MMC_R1_ERASE_RESET			0x02
+#define MMC_R1_IDLE_STATE			0x01
+// Data Start tokens
+#define MMC_STARTBLOCK_READ			0xFE	///< when received from card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_WRITE		0xFE	///< when sent to card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_MWRITE		0xFC
+// Data Stop tokens
+#define MMC_STOPTRAN_WRITE			0xFD
+// Data Error Token values
+#define MMC_DE_MASK					0x1F
+#define MMC_DE_ERROR				0x01
+#define MMC_DE_CC_ERROR				0x02
+#define MMC_DE_ECC_FAIL				0x04
+#define MMC_DE_OUT_OF_RANGE			0x04
+#define MMC_DE_CARD_LOCKED			0x04
+// Data Response Token values
+#define MMC_DR_MASK					0x1F
+#define MMC_DR_ACCEPT				0x05
+#define MMC_DR_REJECT_CRC			0x0B
+#define MMC_DR_REJECT_WRITE_ERROR	0x0D
+
+// functions
+
+//! Initialize AVR<->MMC hardware interface.
+/// Prepares hardware for MMC access.
+void mmcInit(void);
+
+//! Initialize the card and prepare it for use.
+/// Returns zero if successful.
+u08 mmcReset(void);
+
+//! Send card an MMC command.
+/// Returns R1 result code.
+u08 mmcSendCommand(u08 cmd, u32 arg);
+
+//! Read 512-byte sector from card to buffer
+/// Returns zero if successful.
+u08 mmcRead(u32 sector);
+
+//! Write 512-byte sector from buffer to card
+/// Returns zero if successful.
+u08 mmcWrite(u32 sector);
+
+//! Internal command function.
+/// Issues a generic MMC command as specified by cmd and arg.
+u08 mmcCommand(u08 cmd, u32 arg);
+
+#endif
Index: unmerged/zpu_firmware/de1_replaysvn/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,3965 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
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+0d7b : 0283e08c;
+0d7c : 0cf93d0d;
+0d7d : 800b83e0;
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+0d80 : 08880508;
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+0d86 : 0b83e08c;
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+0d88 : 83e08c08;
+0d89 : fc05088a;
+0d8a : 38810b83;
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+0d8c : 050c83e0;
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+0d8e : 0883e08c;
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+0d90 : 83e08c08;
+0d91 : 8c050880;
+0d92 : 25b93883;
+0d93 : e08c088c;
+0d94 : 05083083;
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+0d96 : 050c800b;
+0d97 : 83e08c08;
+0d98 : f0050c83;
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+0da4 : 08880508;
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+0da8 : 08f8050c;
+0da9 : 5483e08c;
+0daa : 08fc0508;
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+0dbb : 08880508;
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+0dc4 : 8c050880;
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+0dca : 83e08c08;
+0dcb : 8c050852;
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+0dcd : 88050851;
+0dce : bd3f83e0;
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+0dd3 : 0508802e;
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+0dda : 7083e080;
+0ddb : 0c54873d;
+0ddc : 0d83e08c;
+0ddd : 0c0483e0;
+0dde : 8c080283;
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+0de0 : 3d0d810b;
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+0de2 : fc050c80;
+0de3 : 0b83e08c;
+0de4 : 08f8050c;
+0de5 : 83e08c08;
+0de6 : 8c050883;
+0de7 : e08c0888;
+0de8 : 050827b9;
+0de9 : 3883e08c;
+0dea : 08fc0508;
+0deb : 802eae38;
+0dec : 800b83e0;
+0ded : 8c088c05;
+0dee : 0824a238;
+0def : 83e08c08;
+0df0 : 8c050810;
+0df1 : 83e08c08;
+0df2 : 8c050c83;
+0df3 : e08c08fc;
+0df4 : 05081083;
+0df5 : e08c08fc;
+0df6 : 050cffb8;
+0df7 : 3983e08c;
+0df8 : 08fc0508;
+0df9 : 802e80e1;
+0dfa : 3883e08c;
+0dfb : 088c0508;
+0dfc : 83e08c08;
+0dfd : 88050826;
+0dfe : ad3883e0;
+0dff : 8c088805;
+0e00 : 0883e08c;
+0e01 : 088c0508;
+0e02 : 3183e08c;
+0e03 : 0888050c;
+0e04 : 83e08c08;
+0e05 : f8050883;
+0e06 : e08c08fc;
+0e07 : 05080783;
+0e08 : e08c08f8;
+0e09 : 050c83e0;
+0e0a : 8c08fc05;
+0e0b : 08812a83;
+0e0c : e08c08fc;
+0e0d : 050c83e0;
+0e0e : 8c088c05;
+0e0f : 08812a83;
+0e10 : e08c088c;
+0e11 : 050cff95;
+0e12 : 3983e08c;
+0e13 : 08900508;
+0e14 : 802e9338;
+0e15 : 83e08c08;
+0e16 : 88050870;
+0e17 : 83e08c08;
+0e18 : f4050c51;
+0e19 : 913983e0;
+0e1a : 8c08f805;
+0e1b : 087083e0;
+0e1c : 8c08f405;
+0e1d : 0c5183e0;
+0e1e : 8c08f405;
+0e1f : 0883e080;
+0e20 : 0c853d0d;
+0e21 : 83e08c0c;
+0e22 : 0483e08c;
+0e23 : 080283e0;
+0e24 : 8c0cff3d;
+0e25 : 0d800b83;
+0e26 : e08c08fc;
+0e27 : 050c83e0;
+0e28 : 8c088805;
+0e29 : 088106ff;
+0e2a : 11700970;
+0e2b : 83e08c08;
+0e2c : 8c050806;
+0e2d : 83e08c08;
+0e2e : fc050811;
+0e2f : 83e08c08;
+0e30 : fc050c83;
+0e31 : e08c0888;
+0e32 : 0508812a;
+0e33 : 83e08c08;
+0e34 : 88050c83;
+0e35 : e08c088c;
+0e36 : 05081083;
+0e37 : e08c088c;
+0e38 : 050c5151;
+0e39 : 515183e0;
+0e3a : 8c088805;
+0e3b : 08802e84;
+0e3c : 38ffab39;
+0e3d : 83e08c08;
+0e3e : fc050870;
+0e3f : 83e0800c;
+0e40 : 51833d0d;
+0e41 : 83e08c0c;
+0e42 : 04fc3d0d;
+0e43 : 7670797b;
+0e44 : 55555555;
+0e45 : 8f72278c;
+0e46 : 38727507;
+0e47 : 83065170;
+0e48 : 802ea938;
+0e49 : ff125271;
+0e4a : ff2e9838;
+0e4b : 72708105;
+0e4c : 54337470;
+0e4d : 81055634;
+0e4e : ff125271;
+0e4f : ff2e0981;
+0e50 : 06ea3874;
+0e51 : 83e0800c;
+0e52 : 863d0d04;
+0e53 : 74517270;
+0e54 : 84055408;
+0e55 : 71708405;
+0e56 : 530c7270;
+0e57 : 84055408;
+0e58 : 71708405;
+0e59 : 530c7270;
+0e5a : 84055408;
+0e5b : 71708405;
+0e5c : 530c7270;
+0e5d : 84055408;
+0e5e : 71708405;
+0e5f : 530cf012;
+0e60 : 52718f26;
+0e61 : c9388372;
+0e62 : 27953872;
+0e63 : 70840554;
+0e64 : 08717084;
+0e65 : 05530cfc;
+0e66 : 12527183;
+0e67 : 26ed3870;
+0e68 : 54ff8139;
+0e69 : 00ffffff;
+0e6a : ff00ffff;
+0e6b : ffff00ff;
+0e6c : ffffff00;
+0e6d : 70707042;
+0e6e : 409c0202;
+0e6f : 02020202;
+0e70 : 02020202;
+0e71 : 02020202;
+0e72 : 02020202;
+0e73 : 02020202;
+0e74 : 02704100;
+0e75 : 06000000;
+0e76 : 70707042;
+0e77 : 409c0202;
+0e78 : 02020202;
+0e79 : 02020202;
+0e7a : 02020202;
+0e7b : 02020202;
+0e7c : 02020202;
+0e7d : 02704100;
+0e7e : 9c000000;
+0e7f : 2f000000;
+0e80 : 4f70656e;
+0e81 : 696e673a;
+0e82 : 00000000;
+0e83 : 6661696c;
+0e84 : 0a000000;
+0e85 : 6f6b0a00;
+0e86 : 436f756c;
+0e87 : 64206e6f;
+0e88 : 74207265;
+0e89 : 61642068;
+0e8a : 65616465;
+0e8b : 720a0000;
+0e8c : 556e6b6e;
+0e8d : 6f776e20;
+0e8e : 66696c65;
+0e8f : 20747970;
+0e90 : 65000000;
+0e91 : 41545220;
+0e92 : 00000000;
+0e93 : 58442000;
+0e94 : 300a0000;
+0e95 : 58464420;
+0e96 : 00000000;
+0e97 : 42414420;
+0e98 : 73656374;
+0e99 : 6f722073;
+0e9a : 697a6500;
+0e9b : 4d442000;
+0e9c : 58455820;
+0e9d : 00000000;
+0e9e : 53442000;
+0e9f : 44442000;
+0ea0 : 44495220;
+0ea1 : 00000000;
+0ea2 : 6f70656e;
+0ea3 : 64697220;
+0ea4 : 6661696c;
+0ea5 : 65640a00;
+0ea6 : 426f6f74;
+0ea7 : 696e672e;
+0ea8 : 2e2e0000;
+0ea9 : 53797374;
+0eaa : 656d2073;
+0eab : 65747469;
+0eac : 6e67730a;
+0ead : 00000000;
+0eae : 2d2d2d2d;
+0eaf : 2d2d2d2d;
+0eb0 : 2d2d2d2d;
+0eb1 : 2d2d2d0a;
+0eb2 : 00000000;
+0eb3 : 4d656d6f;
+0eb4 : 72793a00;
+0eb5 : 556e6b6e;
+0eb6 : 6f776e00;
+0eb7 : 524f4d20;
+0eb8 : 62616e6b;
+0eb9 : 3a000000;
+0eba : 53706565;
+0ebb : 643a0000;
+0ebc : 204b487a;
+0ebd : 0a44313a;
+0ebe : 00000000;
+0ebf : 0a44323a;
+0ec0 : 00000000;
+0ec1 : 0a44333a;
+0ec2 : 00000000;
+0ec3 : 0a44343a;
+0ec4 : 00000000;
+0ec5 : 0a526562;
+0ec6 : 6f6f7400;
+0ec7 : 0a457869;
+0ec8 : 74000000;
+0ec9 : 3332304b;
+0eca : 69422052;
+0ecb : 616d626f;
+0ecc : 00000000;
+0ecd : 30202864;
+0ece : 65666175;
+0ecf : 6c743a58;
+0ed0 : 4c290000;
+0ed1 : 31202864;
+0ed2 : 65666175;
+0ed3 : 6c743a58;
+0ed4 : 4c202b20;
+0ed5 : 68692073;
+0ed6 : 70656564;
+0ed7 : 29000000;
+0ed8 : 3332304b;
+0ed9 : 69422043;
+0eda : 6f6d7079;
+0edb : 2053686f;
+0edc : 70000000;
+0edd : 36344b69;
+0ede : 42000000;
+0edf : 3132384b;
+0ee0 : 69420000;
+0ee1 : 32202864;
+0ee2 : 65666175;
+0ee3 : 6c743a55;
+0ee4 : 6c74696d;
+0ee5 : 6f6e2900;
+0ee6 : 33202864;
+0ee7 : 65666175;
+0ee8 : 6c743a4f;
+0ee9 : 53204220;
+0eea : 2b206869;
+0eeb : 20737065;
+0eec : 65642900;
+0eed : 636d643a;
+0eee : 00000000;
+0eef : 45525220;
+0ef0 : 00000000;
+0ef1 : 53504453;
+0ef2 : 00000000;
+0ef3 : 53504446;
+0ef4 : 00000000;
+0ef5 : 2873656e;
+0ef6 : 643a0000;
+0ef7 : 3a63686b;
+0ef8 : 3a000000;
+0ef9 : 73646361;
+0efa : 72640a00;
+0efb : 6469736b;
+0efc : 5f696e69;
+0efd : 743a0000;
+0efe : 6d6f756e;
+0eff : 743a0000;
+0f00 : 6f70656e;
+0f01 : 6469723a;
+0f02 : 00000000;
+0f03 : 424f4f54;
+0f04 : 2e415452;
+0f05 : 00000000;
+0f06 : 50617573;
+0f07 : 65640a00;
+0f08 : 53746174;
+0f09 : 3a000000;
+0f0a : 3a646f6e;
+0f0b : 650a0000;
+0f0c : 53656374;
+0f0d : 6f723a00;
+0f0e : 20726563;
+0f0f : 65697665;
+0f10 : 3a000000;
+0f11 : 2073656e;
+0f12 : 64696e67;
+0f13 : 0a000000;
+0f14 : 64617461;
+0f15 : 20000000;
+0f16 : 6e616d65;
+0f17 : 20000000;
+0f18 : 6e756d74;
+0f19 : 6f627566;
+0f1a : 66657220;
+0f1b : 00000000;
+0f1c : 626f6f74;
+0f1d : 20000000;
+0f1e : 00000000;
+0f1f : 00000000;
+0f20 : 72025f07;
+0f21 : f807a900;
+0f22 : 8d04038d;
+0f23 : 4402a907;
+0f24 : 8d0503a9;
+0f25 : 708d0a03;
+0f26 : a9018d0b;
+0f27 : 03850960;
+0f28 : 7d8a4820;
+0f29 : 53e488d0;
+0f2a : fa68aa8c;
+0f2b : 8e07ad7d;
+0f2c : 07ee8e07;
+0f2d : 60a9938d;
+0f2e : e202a907;
+0f2f : 8de302a2;
+0f30 : 0220da07;
+0f31 : 954320da;
+0f32 : 07954435;
+0f33 : 43c9fff0;
+0f34 : f0caca10;
+0f35 : ec3006e6;
+0f36 : 45d002e6;
+0f37 : 4620da07;
+0f38 : a2018144;
+0f39 : b545d543;
+0f3a : d0edca10;
+0f3b : f720d207;
+0f3c : 4c9407a9;
+0f3d : 038d0fd2;
+0f3e : 6ce202ad;
+0f3f : 8e07cd7f;
+0f40 : 07d0abee;
+0f41 : 0a03d003;
+0f42 : ee0b03ad;
+0f43 : 7d070d7e;
+0f44 : 07d08e20;
+0f45 : d2076ce0;
+0f46 : 0220da07;
+0f47 : 8de00220;
+0f48 : da078de1;
+0f49 : 022de002;
+0f4a : c9fff0ed;
+0f4b : a9008d8e;
+0f4c : 07f08200;
+0f4d : 0001d400;
+0f4e : 0001d409;
+0f4f : 0001d010;
+0f50 : 0001d301;
+0f51 : 0001d300;
+0f52 : 0001d20a;
+0f53 : 0001d01b;
+0f54 : 0001d018;
+0f55 : 0001d017;
+0f56 : 0001d01a;
+0f57 : 0001d403;
+0f58 : 0001d402;
+0f59 : 0001d40e;
+0f5a : 0002007c;
+0f5b : 00020078;
+0f5c : 00020074;
+0f5d : 00020068;
+0f5e : 00020060;
+0f5f : 0002005c;
+0f60 : 00020058;
+0f61 : 00020054;
+0f62 : 00020050;
+0f63 : 0002004c;
+0f64 : 00020048;
+0f65 : 00020044;
+0f66 : 00020040;
+0f67 : 00020028;
+0f68 : 00020024;
+0f69 : 00020020;
+0f6a : 0002001c;
+0f6b : 00020018;
+0f6c : 00020014;
+0f6d : 00020010;
+0f6e : 0002000c;
+0f6f : 00020008;
+0f70 : 00020004;
+0f71 : 00020000;
+END; 
Index: unmerged/zpu_firmware/de1_replaysvn/debug.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/debug.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/debug.h	(revision 1)
@@ -0,0 +1,20 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debugoffset(int x);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/zpu_firmware/de1_replaysvn/led.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/led.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/zpu_firmware/de1_replaysvn/mmcconf.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/mmcconf.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/mmcconf.h	(revision 1)
@@ -0,0 +1,33 @@
+/*! \file mmcconf.h \brief MultiMedia and SD Flash Card Interface Configuration. */
+//*****************************************************************************
+//
+// File Name	: 'mmcconf.h'
+// Title		: MultiMedia and SD Flash Card Interface Configuration
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef MMCCONF_H
+#define MMCCONF_H
+
+#endif
Index: unmerged/zpu_firmware/de1_replaysvn/pff.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/pff.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/zpu_firmware/de1_replaysvn/rom_prologue.vhd
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/rom_prologue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/zpu_firmware/de1_replaysvn/standalone_simple.ld
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/standalone_simple.ld	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/zpu_firmware/de1_replaysvn/zpuromgen.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/zpuromgen.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/zpu_firmware/de1_replaysvn/pff.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/pff.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/zpu_firmware/de1_replaysvn/rom_epilogue.vhd
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/rom_epilogue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/zpu_firmware/de1_replaysvn/spi.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/spi.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/spi.h	(revision 1)
@@ -0,0 +1,65 @@
+/*! \file spi.h \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.h'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup driver_avr
+/// \defgroup spi SPI (Serial Peripheral Interface) Function Library (spi.c)
+/// \code #include "spi.h" \endcode
+/// \par Overview
+///		Provides basic byte and word transmitting and receiving via the AVR
+///	SPI interface.� Due to the nature of SPI, every SPI communication operation
+/// is both a transmit and simultaneous receive.
+///
+///	\note Currently, only MASTER mode is supported.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef SPI_H
+#define SPI_H
+
+#include "types.h"
+
+// function prototypes
+void mmcChipSelect(int select);
+
+
+// SPI interface initializer
+void spiInit(void);
+
+// spiTransferByte(u08 data) waits until the SPI interface is ready
+// and then sends a single byte over the SPI port.  The function also
+// returns the byte that was received during transmission.
+u08 spiTransferByte(u08 data);
+
+// spiTransferWord(u08 data) works just like spiTransferByte but
+// operates on a whole word (16-bits of data).
+u08 spiTransferFF();
+void spiTransferTwoFF();
+
+void spiDisplay(int i);
+
+#endif
Index: unmerged/zpu_firmware/de1_replaysvn/uart.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/uart.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/zpu_firmware/mcc216/HelloTinyROM.rpt
===================================================================
--- unmerged/zpu_firmware/mcc216/HelloTinyROM.rpt	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/HelloTinyROM.rpt	(revision 1)
@@ -0,0 +1,3 @@
+End of code:	00003f04 g       *ABS*	00000000 _romend
+Start of BSS:	0000f000 g       .bss	00000000 __bss_start__
+End of BSS:	0000f404 g       *ABS*	00000000 __bss_end__
Index: unmerged/zpu_firmware/de1_replaysvn/regs.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/regs.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/regs.c	(revision 1)
@@ -0,0 +1,47 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+int volatile * zpu_config = (int *)(0*4+regbase);
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+
+#endif // regs_h
Index: unmerged/zpu_firmware/de1_replaysvn/setup
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/setup	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/zpu_firmware/de1_replaysvn/types.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/types.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/zpu_firmware/mcc216/HelloTinyROM.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/HelloTinyROM.bin
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/Makefile
===================================================================
--- unmerged/zpu_firmware/mcc216/Makefile	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c mmc.c    spi.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/zpu_firmware/mcc216/bootloader
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/bootloader
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/debug.c
===================================================================
--- unmerged/zpu_firmware/mcc216/debug.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/debug.c	(revision 1)
@@ -0,0 +1,178 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+int debugoffsetval;
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val+debugoffsetval;
+}
+void debugoffset(int x)
+{
+	debugoffsetval = x;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+	debugoffsetval = 0;
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+	debugoffsetval = 0;
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/mcc216/bootdump
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/bootdump
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/chksum.c
===================================================================
--- unmerged/zpu_firmware/mcc216/chksum.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/chksum.c	(revision 1)
@@ -0,0 +1,40 @@
+unsigned char abuffer[] = {
+0x00,0x03,0x00,0x07,0x14,0x07,0x4c,0x14,0x07,0x74,0x0d,0x00,0x00,0xa9,0x46,0x8d
+,0xc6,0x02,0xd0,0xfe,0xa0,0x00,0xa9,0x6b,0x91,0x58,0x20,0xd9,0x07,0xb0,0xee,0x20
+,0xc4,0x07,0xad,0x7a,0x08,0x0d,0x76,0x08,0xd0,0xe3,0xa5,0x80,0x8d,0xe0,0x02,0xa5
+,0x81,0x8d,0xe1,0x02,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20,0xeb,0x07,0xb0
+,0xcc,0xa0,0x00,0x91,0x80,0xa5,0x80,0xc5,0x82,0xd0,0x06,0xa5,0x81,0xc5,0x83,0xf0
+,0x08,0xe6,0x80,0xd0,0x02,0xe6,0x81,0xd0,0xe3,0xad,0x76,0x08,0xd0,0xaf,0xad,0xe2
+,0x02,0x8d,0x70,0x07,0x0d,0xe3,0x02,0xf0,0x0e,0xad,0xe3,0x02,0x8d,0x71,0x07,0x20
+,0xff,0xff,0xad,0x7a,0x08,0xd0,0x13,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20
+};
+
+
+unsigned char buffer[] = {
+0x98,0xff,0xe0,0x00
+};
+
+typedef unsigned short u16;
+typedef unsigned char u08;
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+        u16 i;
+        u08 sumo,sum;
+        sum=sumo=0;
+        for(i=0;i<len;i++)
+        {
+                sum+=buffer[i];
+                if(sum<sumo) sum++;
+                sumo = sum;
+        }
+        return sum;
+}
+
+int main(void)
+{
+	int res = get_checksum(buffer,sizeof(buffer));
+	printf("%x %d\n",res,sizeof(buffer));
+	return 0;
+}
+
Index: unmerged/zpu_firmware/mcc216/diskio.h
===================================================================
--- unmerged/zpu_firmware/mcc216/diskio.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/zpu_firmware/mcc216/led.c
===================================================================
--- unmerged/zpu_firmware/mcc216/led.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/zpu_firmware/de1_replaysvn/regs.h
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/regs.h	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/regs.h	(revision 1)
@@ -0,0 +1,47 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x20000
+extern int volatile * zpu_config;
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_dmactl;
+
+#endif // regs_h
Index: unmerged/zpu_firmware/de1_replaysvn/spi.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/spi.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/spi.c	(revision 1)
@@ -0,0 +1,116 @@
+/*! \file spi.c \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.c'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include "spi.h"
+
+#include "regs.h"
+#include "spi.h"
+
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+	updateSpiState();
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+	updateSpiState();
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+}
+
Index: unmerged/zpu_firmware/de1_replaysvn/uart.c
===================================================================
--- unmerged/zpu_firmware/de1_replaysvn/uart.c	(nonexistent)
+++ unmerged/zpu_firmware/de1_replaysvn/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/mcc216/mmc.h
===================================================================
--- unmerged/zpu_firmware/mcc216/mmc.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/mmc.h	(revision 1)
@@ -0,0 +1,145 @@
+/*! \file mmc.h \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.h'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+///	\ingroup driver_hw
+/// \defgroup mmc MultiMedia and SD Flash Card Interface (mmc.c)
+/// \code #include "mmc.h" \endcode
+/// \par Description
+///		This library offers some simple functions which can be used
+///		to read and write data on a MultiMedia or SecureDigital (SD) Flash
+///		Card.  Although MM and SD Cards are designed to operate with their own
+///		special bus wiring and protocols, both types of cards also provide a
+///		simple SPI-like interface mode which is exceptionally useful when 
+///		attempting to use the cards in embedded systems.
+///
+/// \par Wiring
+///		To work with this library, the card must be wired to the SPI port of
+///		the Atmel microcontroller as described below.  Typical cards can
+///		operate at up to 25MHz maximum SPI clock rate (thus faster than most
+///		AVR's maximum SPI clock rate).
+/// <pre>
+///	      _________________
+///	     /  1 2 3 4 5 6 78 |	<- view of MMC/SD card looking at contacts
+///	    / 9                |	Pins 8 and 9 are present only on SD cards
+///	    |    MMC/SD Card   |
+///	    |                  |
+///	    --------------------
+///	    1 - CS   (chip select)          - wire to any available I/O pin(*)
+///	    2 - DIN  (data in, card<-host)  - wire to SPI MOSI pin
+///	    3 - VSS  (ground)               - wire to ground
+///	    4 - VDD  (power, 3.3V only?)    - wire to power (MIGHT BE 3.3V ONLY!)
+///	    5 - SCLK (data clock)           - wire to SPI SCK pin
+///	    6 - VSS  (ground)               - wire to ground
+///	    7 - DOUT (data out, card->host) - wire to SPI MISO pin
+///
+///	    (*) you must define this chip select I/O pin in mmcconf.h
+/// </pre>
+/// \note This code is currently below version 1.0, and therefore is considered
+/// to be lacking in some functionality or documentation, or may not be fully
+/// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef MMC_H
+#define MMC_H
+
+#include "types.h"
+
+// constants/macros/typdefs
+// MMC commands (taken from sandisk MMC reference)
+#define MMC_GO_IDLE_STATE			0		///< initialize card to SPI-type access
+#define MMC_SEND_OP_COND			1		///< set card operational mode
+#define MMC_SEND_CSD				9		///< get card's CSD
+#define MMC_SEND_CID				10		///< get card's CID
+#define MMC_SEND_STATUS				13
+#define MMC_SET_BLOCKLEN			16		///< Set number of bytes to transfer per block
+#define MMC_READ_SINGLE_BLOCK		17		///< read a block
+#define MMC_WRITE_BLOCK				24		///< write a block
+#define MMC_PROGRAM_CSD				27
+#define MMC_SET_WRITE_PROT			28
+#define MMC_CLR_WRITE_PROT			29
+#define MMC_SEND_WRITE_PROT			30
+#define MMC_TAG_SECTOR_START		32
+#define MMC_TAG_SECTOR_END			33
+#define MMC_UNTAG_SECTOR			34
+#define MMC_TAG_ERASE_GROUP_START 	35		///< Sets beginning of erase group (mass erase)
+#define MMC_TAG_ERARE_GROUP_END		36		///< Sets end of erase group (mass erase)
+#define MMC_UNTAG_ERASE_GROUP		37		///< Untag (unset) erase group (mass erase)
+#define MMC_ERASE					38		///< Perform block/mass erase
+#define MMC_CRC_ON_OFF				59		///< Turns CRC check on/off
+// R1 Response bit-defines
+#define MMC_R1_BUSY					0x80	///< R1 response: bit indicates card is busy
+#define MMC_R1_PARAMETER			0x40
+#define MMC_R1_ADDRESS				0x20
+#define MMC_R1_ERASE_SEQ			0x10
+#define MMC_R1_COM_CRC				0x08
+#define MMC_R1_ILLEGAL_COM			0x04
+#define MMC_R1_ERASE_RESET			0x02
+#define MMC_R1_IDLE_STATE			0x01
+// Data Start tokens
+#define MMC_STARTBLOCK_READ			0xFE	///< when received from card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_WRITE		0xFE	///< when sent to card, indicates that a block of data will follow
+#define MMC_STARTBLOCK_MWRITE		0xFC
+// Data Stop tokens
+#define MMC_STOPTRAN_WRITE			0xFD
+// Data Error Token values
+#define MMC_DE_MASK					0x1F
+#define MMC_DE_ERROR				0x01
+#define MMC_DE_CC_ERROR				0x02
+#define MMC_DE_ECC_FAIL				0x04
+#define MMC_DE_OUT_OF_RANGE			0x04
+#define MMC_DE_CARD_LOCKED			0x04
+// Data Response Token values
+#define MMC_DR_MASK					0x1F
+#define MMC_DR_ACCEPT				0x05
+#define MMC_DR_REJECT_CRC			0x0B
+#define MMC_DR_REJECT_WRITE_ERROR	0x0D
+
+// functions
+
+//! Initialize AVR<->MMC hardware interface.
+/// Prepares hardware for MMC access.
+void mmcInit(void);
+
+//! Initialize the card and prepare it for use.
+/// Returns zero if successful.
+u08 mmcReset(void);
+
+//! Send card an MMC command.
+/// Returns R1 result code.
+u08 mmcSendCommand(u08 cmd, u32 arg);
+
+//! Read 512-byte sector from card to buffer
+/// Returns zero if successful.
+u08 mmcRead(u32 sector);
+
+//! Write 512-byte sector from buffer to card
+/// Returns zero if successful.
+u08 mmcWrite(u32 sector);
+
+//! Internal command function.
+/// Issues a generic MMC command as specified by cmd and arg.
+u08 mmcCommand(u08 cmd, u32 arg);
+
+#endif
Index: unmerged/zpu_firmware/mcc216/pause.h
===================================================================
--- unmerged/zpu_firmware/mcc216/pause.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/zpu_firmware/mcc216/regs.h
===================================================================
--- unmerged/zpu_firmware/mcc216/regs.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/regs.h	(revision 1)
@@ -0,0 +1,49 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x40000
+extern int volatile * zpu_config;
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_chactl;
+extern unsigned char volatile * atari_dmactl;
+extern unsigned char volatile * atari_skctl;
+
+#endif // regs_h
Index: unmerged/zpu_firmware/mcc216/HelloTinyROM.elf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/HelloTinyROM.elf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/a.out
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/a.out
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/changes
===================================================================
--- unmerged/zpu_firmware/mcc216/changes	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/changes	(revision 1)
@@ -0,0 +1,32 @@
+Only in .: ¬
+Only in .: ¬!
+Only in .: 1
+Only in .: a.out
+Only in .: bootdump
+Only in .: bootloader
+Only in .: changes
+Only in .: chksum.c
+Only in .: crt0.S
+Only in .: defunct
+Only in .: DOCS
+Only in .: ._.DS_Store
+Only in .: fat.c
+Only in .: fat.h
+Only in .: HelloTinyROM.bin
+Only in .: HelloTinyROM.elf
+Only in .: HelloTinyROM.rpt
+Only in .: mt6502dis
+Only in .: SDrive081012
+Only in .: SDrive081012.zip
+Only in .: SDrive20090403
+Only in .: SDrive20090403.zip
+Only in .: sdrive_hias
+Only in .: sdrive-hias-090705.zip
+Only in .: stuff.c
+Only in ../../../replay/src/hw/replay/cores/atari_800/zpu/: .svn
+Only in .: SW
+Only in .: test
+Only in .: test2
+Only in .: test.c
+Only in .: zpu_obj
+Only in .: zpuromgen
Index: unmerged/zpu_firmware/mcc216/debug.h
===================================================================
--- unmerged/zpu_firmware/mcc216/debug.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/debug.h	(revision 1)
@@ -0,0 +1,20 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debugoffset(int x);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/zpu_firmware/mcc216/integer.h
===================================================================
--- unmerged/zpu_firmware/mcc216/integer.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/zpu_firmware/mcc216/mmc.c
===================================================================
--- unmerged/zpu_firmware/mcc216/mmc.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/mmc.c	(revision 1)
@@ -0,0 +1,269 @@
+/*! \file mmc.c \brief MultiMedia and SD Flash Card Interface. */
+//*****************************************************************************
+//
+// File Name	: 'mmc.c'
+// Title		: MultiMedia and SD Flash Card Interface
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+//----- Include Files ---------------------------------------------------------
+#include "spi.h"		// include spi bus support
+
+
+//#define spiTransferTwoFF()	{ spiTransferFF(); spiTransferFF(); }
+
+
+#include "mmc.h"
+
+// include project-specific hardware configuration
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+	// initialize SPI interface
+	spiInit();
+	// release chip select
+	mmcChipSelect(0);
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(1);
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	i=0x80;	//512
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+	u08 retry=0xff;	//255x
+	//
+
+	spiTransferFF();
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+	//
+	spiTransferByte(arg>>24);
+	spiTransferByte(arg>>16);
+	spiTransferByte(arg>>8);
+	spiTransferByte(arg);
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+		retry--;
+	}
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
Index: unmerged/zpu_firmware/mcc216/fat.h
===================================================================
--- unmerged/zpu_firmware/mcc216/fat.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/fat.h	(revision 1)
@@ -0,0 +1,435 @@
+/*! \file fat.h \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.h'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup general
+/// \defgroup fat FAT16/32 File System Interface (fat.c)
+/// \code #include "fat.h" \endcode
+/// \par Overview
+///		This FAT16/32 interface allows you to detect and mount FAT16/32
+///		partitions, browse directories and files, and read file data.
+///		The interface is designed to operate with the avrlib IDE/ATA driver.
+///		Reading FAT efficiently requires at least 512+ bytes of RAM so this
+///		interface may not be suitable for processors with less than 1K of RAM.
+///		This interface will properly follow a file's cluster chain so files
+///		need not be defragmented.
+///
+/// \note This code is based in part on work done by Jesper Hansen for his
+///		excellent YAMPP MP3 player project.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef FAT_H
+#define FAT_H
+
+#define FALSE 0
+#define TRUE -1
+
+#define DRIVE0 1
+
+// Some useful cluster numbers
+#define MSDOSFSROOT     0		// cluster 0 means the root dir
+#define CLUST_FREE      0               // cluster 0 also means a free cluster
+#define MSDOSFSFREE     CLUST_FREE
+#define CLUST_FIRST     2               // first legal cluster number
+#define CLUST_RSRVD     0xfffffff6      // reserved cluster range
+#define CLUST_BAD       0xfffffff7      // a cluster with a defect
+#define CLUST_EOFS      0xfffffff8      // start of eof cluster range
+#define CLUST_EOFE      0xffffffff      // end of eof cluster range
+
+#define FAT12_MASK      0x00000fff      // mask for 12 bit cluster numbers
+#define FAT16_MASK      0x0000ffff      // mask for 16 bit cluster numbers
+#define FAT32_MASK      0x0fffffff      // mask for FAT32 cluster numbers
+
+
+// Partition Type used in the partition record
+#define PART_TYPE_UNKNOWN		0x00
+#define PART_TYPE_FAT12			0x01
+#define PART_TYPE_XENIX			0x02
+#define PART_TYPE_DOSFAT16		0x04
+#define PART_TYPE_EXTDOS		0x05
+#define PART_TYPE_FAT16			0x06
+#define PART_TYPE_NTFS			0x07
+#define PART_TYPE_FAT32			0x0B
+#define PART_TYPE_FAT32LBA		0x0C
+#define PART_TYPE_FAT16LBA		0x0E
+#define PART_TYPE_EXTDOSLBA		0x0F
+#define PART_TYPE_ONTRACK		0x33
+#define PART_TYPE_NOVELL		0x40
+#define PART_TYPE_PCIX			0x4B
+#define PART_TYPE_PHOENIXSAVE	0xA0
+#define PART_TYPE_CPM			0xDB
+#define PART_TYPE_DBFS			0xE0
+#define PART_TYPE_BBT			0xFF
+
+struct partrecord // length 16 bytes
+{			
+	unsigned char	prIsActive;					// 0x80 indicates active partition
+	unsigned char	prStartHead;				// starting head for partition
+	unsigned short	prStartCylSect;				// starting cylinder and sector
+	unsigned char	prPartType;					// partition type (see above)
+	unsigned char	prEndHead;					// ending head for this partition
+	unsigned short	prEndCylSect;				// ending cylinder and sector
+	unsigned long	prStartLBA;					// first LBA sector for this partition
+	unsigned long	prSize;						// size of this partition (bytes or sectors ?)
+};
+
+        
+struct partsector
+{
+	unsigned char	psPartCode[512-64-2];		// pad so struct is 512b
+	unsigned char	psPart[64];					// four partition records (64 bytes)
+	unsigned char	psBootSectSig0;				// two signature bytes (2 bytes)
+	unsigned char	psBootSectSig1;
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+
+// Format of a boot sector.  This is the first sector on a DOS floppy disk
+// or the first sector of a partition on a hard disk.  But, it is not the
+// first sector of a partitioned hard disk.
+struct bootsector33 {
+	unsigned char 	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[19];					// BIOS parameter block
+	unsigned char	bsDriveNumber;				// drive number (0x80)
+	unsigned char	bsBootCode[479];			// pad so struct is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct extboot {
+	unsigned char	exDriveNumber;				// drive number (0x80)
+	unsigned char	exReserved1;				// reserved
+	unsigned char	exBootSignature;			// ext. boot signature (0x29)
+#define EXBOOTSIG       0x29
+	unsigned char	exVolumeID[4];				// volume ID number
+	unsigned char	exVolumeLabel[11];			// volume label
+	unsigned char	exFileSysType[8];			// fs type (FAT12 or FAT16)
+};
+
+struct bootsector50 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[25];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[448];			// pad so structure is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55 
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct bootsector710 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOEMName[8];				// OEM name and version
+	unsigned char	bsBPB[53];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[418];			// pad so structure is 512b
+	unsigned char	bsBootSectSig2;				// 2 & 3 are only defined for FAT32?
+	unsigned char	bsBootSectSig3;
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+#define BOOTSIG2        0
+#define BOOTSIG3        0
+};
+
+
+/***************************************************************/
+/***************************************************************/
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct bpb33 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char    bpbSecPerClust;	// sectors per cluster
+        unsigned short	bpbResSectors;	// number of reserved sectors
+        unsigned char	bpbFATs;		// number of FATs
+        unsigned short	bpbRootDirEnts;	// number of root directory entries
+        unsigned short	bpbSectors;		// total number of sectors
+        unsigned char	bpbMedia;		// media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned short	bpbHiddenSecs;  // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not present in the DOS 3.3 bpb.
+struct bpb50 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char	bpbSecPerClust; // sectors per cluster
+        unsigned short	bpbResSectors;  // number of reserved sectors
+        unsigned char	bpbFATs;        // number of FATs
+        unsigned short	bpbRootDirEnts; // number of root directory entries
+        unsigned short	bpbSectors;     // total number of sectors
+        unsigned char	bpbMedia;       // media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned long	bpbHiddenSecs;  // # of hidden sectors
+// 3.3 compat ends here
+        unsigned long	bpbHugeSectors; // # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32)
+// This one has a few extensions to bpb50.
+struct bpb710 {
+		unsigned short	bpbBytesPerSec;	// bytes per sector
+		unsigned char	bpbSecPerClust;	// sectors per cluster
+		unsigned short	bpbResSectors;	// number of reserved sectors
+		unsigned char	bpbFATs;		// number of FATs
+		unsigned short	bpbRootDirEnts;	// number of root directory entries
+		unsigned short	bpbSectors;		// total number of sectors
+		unsigned char	bpbMedia;		// media descriptor
+		unsigned short	bpbFATsecs;		// number of sectors per FAT
+		unsigned short	bpbSecPerTrack;	// sectors per track
+		unsigned short	bpbHeads;		// number of heads
+		unsigned long	bpbHiddenSecs;	// # of hidden sectors
+// 3.3 compat ends here
+		unsigned long	bpbHugeSectors;	// # of sectors if bpbSectors == 0
+// 5.0 compat ends here
+		unsigned long     bpbBigFATsecs;// like bpbFATsecs for FAT32
+		unsigned short      bpbExtFlags;	// extended flags:
+#define FATNUM    0xf			// mask for numbering active FAT
+#define FATMIRROR 0x80			// FAT is mirrored (like it always was)
+		unsigned short      bpbFSVers;	// filesystem version
+#define FSVERS    0				// currently only 0 is understood
+		unsigned long     bpbRootClust;	// start cluster for root directory
+		unsigned short      bpbFSInfo;	// filesystem info structure sector
+		unsigned short      bpbBackup;	// backup boot sector
+		// There is a 12 byte filler here, but we ignore it
+};
+
+
+// ***************************************************************
+// * byte versions of the above structs                          *
+// ***************************************************************
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct byte_bpb33 {
+        unsigned char bpbBytesPerSec[2];		// bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[2];      // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not in the 3.3 bpb.
+struct byte_bpb50 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // number of hidden sectors
+        unsigned char bpbHugeSectors[4];		// # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32).
+// This one has a few extensions to bpb50.
+struct byte_bpb710 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // # of hidden sectors
+        unsigned char bpbHugeSectors[4];     // # of sectors if bpbSectors == 0
+        unsigned char bpbBigFATsecs[4];      // like bpbFATsecs for FAT32
+        unsigned char bpbExtFlags[2];        // extended flags:
+        unsigned char bpbFSVers[2];          // filesystem version
+        unsigned char bpbRootClust[4];       // start cluster for root directory
+        unsigned char bpbFSInfo[2];          // filesystem info structure sector
+        unsigned char bpbBackup[2];          // backup boot sector
+        // There is a 12 byte filler here, but we ignore it
+};
+
+// FAT32 FSInfo block.
+struct fsinfo {
+        unsigned char fsisig1[4];
+        unsigned char fsifill1[480];
+        unsigned char fsisig2[4];
+        unsigned char fsinfree[4];
+        unsigned char fsinxtfree[4];
+        unsigned char fsifill2[12];
+        unsigned char fsisig3[4];
+        unsigned char fsifill3[508];
+        unsigned char fsisig4[4];
+};
+
+
+// Structure of a dos directory entry.
+struct direntry {
+		unsigned char		deName[8];      // filename, blank filled
+#define SLOT_EMPTY      0x00            // slot has never been used
+#define SLOT_E5         0x05            // the real value is 0xE5
+#define SLOT_DELETED    0xE5            // file in this slot deleted
+		unsigned char		deExtension[3]; // extension, blank filled
+		unsigned char		deAttributes;   // file attributes
+#define ATTR_NORMAL     0x00            // normal file
+#define ATTR_READONLY   0x01            // file is readonly
+#define ATTR_HIDDEN     0x02            // file is hidden
+#define ATTR_SYSTEM     0x04            // file is a system file
+#define ATTR_VOLUME     0x08            // entry is a volume label
+#define ATTR_LONG_FILENAME	0x0F		// this is a long filename entry			    
+#define ATTR_DIRECTORY  0x10            // entry is a directory name
+#define ATTR_ARCHIVE    0x20            // file is new or modified
+		unsigned char        deLowerCase;    // NT VFAT lower case flags  (set to zero)
+#define LCASE_BASE      0x08            // filename base in lower case
+#define LCASE_EXT       0x10            // filename extension in lower case
+		unsigned char        deCHundredth;   // hundredth of seconds in CTime
+		unsigned char        deCTime[2];     // create time
+		unsigned char        deCDate[2];     // create date
+		unsigned char        deADate[2];     // access date
+		unsigned short        deHighClust; 	// high bytes of cluster number
+		unsigned char        deMTime[2];     // last update time
+		unsigned char        deMDate[2];     // last update date
+		unsigned short        deStartCluster; // starting cluster of file
+		unsigned long       deFileSize;  	// size of file in bytes
+};
+
+// number of directory entries in one sector
+#define DIRENTRIES_PER_SECTOR	0x10
+
+// Structure of a Win95 long name directory entry
+struct winentry {
+		unsigned char		weCnt;			// 
+#define WIN_LAST        0x40
+#define WIN_CNT         0x3f
+		unsigned char		wePart1[10];
+		unsigned char		weAttributes;
+#define ATTR_WIN95      0x0f
+		unsigned char		weReserved1;
+		unsigned char		weChksum;
+		unsigned char		wePart2[12];
+		unsigned short       	weReserved2;
+		unsigned char		wePart3[4];
+};
+
+#define WIN_ENTRY_CHARS	13      // Number of chars per winentry
+
+// Maximum filename length in Win95
+// Note: Must be < sizeof(dirent.d_name)
+#define WIN_MAXLEN      255
+
+// This is the format of the contents of the deTime field in the direntry
+// structure.
+// We don't use bitfields because we don't know how compilers for
+// arbitrary machines will lay them out.
+#define DT_2SECONDS_MASK        0x1F    // seconds divided by 2
+#define DT_2SECONDS_SHIFT       0
+#define DT_MINUTES_MASK         0x7E0   // minutes
+#define DT_MINUTES_SHIFT        5
+#define DT_HOURS_MASK           0xF800  // hours
+#define DT_HOURS_SHIFT          11
+
+// This is the format of the contents of the deDate field in the direntry
+// structure.
+#define DD_DAY_MASK				0x1F	// day of month
+#define DD_DAY_SHIFT			0
+#define DD_MONTH_MASK			0x1E0	// month
+#define DD_MONTH_SHIFT			5
+#define DD_YEAR_MASK			0xFE00	// year - 1980
+#define DD_YEAR_SHIFT			9
+
+
+#define FLAGS_ATRMEDIUMSIZE		0x80
+#define FLAGS_XEXLOADER			0x40
+#define FLAGS_ATRDOUBLESECTORS	0x20
+#define FLAGS_XFDTYPE			0x10
+#define FLAGS_READONLY			0x08
+#define FLAGS_WRITEERROR		0x04
+#define FLAGS_DRIVEON			0x01
+
+// Stuctures
+typedef struct						//2+2+2+2+2+4+1=15
+{
+	unsigned short start_cluster;		//< file starting cluster
+	unsigned short dir_cluster;
+	unsigned short current_cluster;
+	unsigned short ncluster;
+	unsigned short file_index;			//< file index
+	unsigned long size;					//< file size
+	unsigned char flags;				//< file flags
+}virtual_disk_t;
+
+struct FileInfoStruct
+{
+	unsigned char Attr;				//< file attr for last file accessed
+	unsigned short Date;			//< last update date
+	unsigned short Time;			//< last update time
+	unsigned char percomstate;		//=0 default, 1=percomwrite ok (single sectors), 2=percomwrite ok (double sectors), 3=percomwrite bad
+	//
+	virtual_disk_t vDisk;
+};
+
+struct GlobalSystemValues			//4+4+2+2+1=13 bytes
+{
+	unsigned long FirstFATSector;
+	unsigned long FirstDataSector;
+	unsigned short RootDirSectors;
+	unsigned short BytesPerSector;
+	unsigned char SectorsPerCluster;
+};
+
+#define FirstFATSector		GS.FirstFATSector
+#define FirstDataSector		GS.FirstDataSector
+#define RootDirSectors		GS.RootDirSectors
+#define BytesPerSector		GS.BytesPerSector
+#define SectorsPerCluster	GS.SectorsPerCluster
+
+
+unsigned char fatInit();
+unsigned long fatClustToSect(unsigned short clust);
+unsigned char fatChangeDirectory(unsigned short entry);
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names);
+unsigned short nextCluster(unsigned short cluster);
+
+#endif
Index: unmerged/zpu_firmware/mcc216/main.c
===================================================================
--- unmerged/zpu_firmware/mcc216/main.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/main.c	(revision 1)
@@ -0,0 +1,1604 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+int opendrive;
+char filename_d1[15];
+char filename_d2[15];
+char filename_d3[15];
+char filename_d4[15];
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+int
+selectfile(char * filename)
+{
+	int fileno;
+	int skip;
+	int plotted = 0;
+	wait_us(200000);
+	for(;;)
+	{
+		int i = 0;
+		int go = 0;
+		fileno = 0;
+		topofscreen();
+		for (i=0; i!=(24*40); ++i)
+		{
+			*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+		}
+		if (FR_OK != pf_opendir(&dir,"/"))
+		{
+			debug("opendir failed\n");
+			while(1);
+		}
+
+		plotted = 0;
+		skip = 0;
+		if (selfileno>20)
+		{
+			skip = selfileno-20;
+			skip&=0xfffffffe;
+		}
+		if (selfileno<0)
+		{
+			selfileno = 0;
+		}
+		while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+		{
+			if (filinfo.fattrib & AM_SYS)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_HID)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_DIR)
+			{
+				debug("DIR ");
+			}
+			if (selfileno == fileno)
+			{
+				for (i=0;i!=15;++i)
+				{
+					filename[i] = filinfo.fname[i];
+					if (0==filinfo.fname[i]) break;
+					filinfo.fname[i]+=128;
+				}
+			}
+			if (--skip<0)
+			{
+				debug(filinfo.fname);
+				++plotted;
+				if (plotted&1)
+				{
+					setxpos(20);
+				}
+				else
+				{
+					debug("\n");
+				}
+				if (plotted==40)
+				{
+					break;
+				}
+			}
+			fileno++;
+		}
+		debug("\n");
+		setypos(21);
+		opendrive = 0;
+		openfile(filename);
+		for (;;)
+		{
+			unsigned char porta = *atari_porta;
+			if (0==(porta&0x2)) // down
+			{
+				selfileno+=2;
+				break;
+			}
+			else if (0==(porta&0x1)) // up
+			{
+				selfileno-=2;
+				break;
+			}
+			else if (0==(porta&0x8)) // right
+			{
+				selfileno|=1;
+				break;
+			}
+			else if (0==(porta&0x4)) // left
+			{
+				selfileno&=0xfffffffe;
+				break;
+			}
+			else if (0==(*atari_trig0)) // fire
+			{
+				go = 1;
+				while(0==(*atari_trig0));
+				break;
+			}
+			topofscreen();
+			//plotnextnumber(porta);
+			*atari_colbk = *atari_random;
+			//wait_us(200);
+		}
+		if (go == 1)
+		{
+			wait_us(200000);
+			return validfile; // TODO, another way to quit without selecting...
+		}
+		wait_us(80000);
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	int prev = *zpu_config;
+	if (reset_n == 1)
+		*zpu_config = prev&~(1<<7);
+	else
+		*zpu_config = prev|(1<<7);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	int prev = *zpu_config;
+	if (pause == 0)
+		*zpu_config = prev&~(1<<6);
+	else
+		*zpu_config = prev|(1<<6);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+	//unsigned volatile char * store = 0xf00000; // SDRAM - fails!!
+	unsigned volatile char * store = 0x97f000; // SRAM...
+	unsigned volatile char * store2 = 0x970000; // custom chips...
+
+	if ((1&*zpu_key) == 1)
+	{
+		unsigned char volatile * mem;
+		unsigned char volatile * mem2;
+		unsigned char volatile * mem3;
+		unsigned char store_portb;
+		int reboot = 0;
+		int temp;
+		int row = 0;
+		int next = 0;
+		int go = 0;
+
+		// stop 6502
+		pause_6502(1);
+
+		// TODO - 
+		// menu for 64k/128k/320K Compy/320K Rambo
+		// menu for ROM bank
+		// menu for GPIO on/off
+
+		initdebug(1);
+
+		mem = 0x9c00 + 0x10000;
+		// Copy 1k from 0x$9c00 to sdram
+		// 0x200000; sram
+		// 0x800000; sdram (always use...)
+		for (i=0x0; i!=1024; i++)
+		{
+			store[i] = mem[i];
+		}
+		for (i=0x40; i!=1024; i++)
+		{
+			mem[i] = 0;
+		}
+
+		{
+			//gtia
+			mem2 = 0x20000;
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+		}
+
+		store_portb = *atari_portb;
+
+		// write a display list at 9c00
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x9c
+		};
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x9c;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+		*atari_portb = 0xff;
+		*atari_skctl = 0x3;
+		*atari_chactl = 0x2;
+
+		for (;;)
+		{
+			wait_us(120000);
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			// 0-5 speed
+			// 6-pause
+			// 7-reset
+			// 8-9-ram
+			// 12-13-rom
+			// 16-gpio_enable
+			debug("System settings\n");
+			debug("---------------\n");
+			debug("Memory:");
+			temp = 0xf&((*zpu_config)>>8);
+			if (row == 0)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xfffff0ff)|((temp&0x3)<<8);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("64KiB");
+				break;
+			case 1:
+				debug("128KiB");
+				break;
+			case 2:
+				debug("320KiB Compy Shop");
+				break;
+			case 3:
+				debug("320KiB Rambo");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("ROM bank:");
+			temp = 0xf&((*zpu_config)>>12);
+			if (row == 1)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xffff0fff)|((temp&0x3)<<12);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("0 (default:XL)");
+				break;
+			case 1:
+				debug("1 (default:XL + hi speed)");
+				break;
+			case 2:
+				debug("2 (default:Ultimon)");
+				break;
+			case 3:
+				debug("3 (default:OS B + hi speed)");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("Speed:");
+			temp = 0x3f&((*zpu_config)>>0);
+			if (row == 2)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					if (temp < 0) temp =0;
+					*zpu_config = (*zpu_config&0xffffffc0)|(temp&0x3f);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			plotnextnumber(57500/(temp+1));
+			debug(" KHz\nD1:"); // Bring up selector, instead of booting changes disk image
+			if (row == 3)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d1);
+			debug("\nD2:");
+			if (row == 4)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d2);
+			debug("\nD3:");
+			if (row == 5)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d3);
+			debug("\nD4:");
+			if (row == 6)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d4);
+			if (row>=3 && row<7)
+			{
+				if (go==1)
+				{
+					switch (row)
+					{
+					case 3:
+						selectfile(filename_d1);
+						break;
+					case 4:
+						selectfile(filename_d2);
+						break;
+					case 5:
+						selectfile(filename_d3);
+						break;
+					case 6:
+						selectfile(filename_d4);
+						break;
+					}
+					opendrive = row-2;
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d4[i];
+						filename_d4[i] = filename_d3[i];
+						filename_d3[i] = filename_d2[i];
+						filename_d2[i] = filename_d1[i];
+						filename_d1[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==-1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d1[i];
+						filename_d1[i] = filename_d2[i];
+						filename_d2[i] = filename_d3[i];
+						filename_d3[i] = filename_d4[i];
+						filename_d4[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+			}
+			if (row == 7)
+			{
+				debugoffset(128);
+			}
+			debug("\nReboot");
+			if (row == 7)
+			{
+				if (go==1)
+				{
+					reboot = 1;
+					break;
+				}
+			}
+			if (row == 8)
+			{
+				debugoffset(128);
+			}
+			debug("\nExit");
+			if (row == 8)
+			{
+				if (go==1)
+					break;
+			}
+
+			next = 0;
+			go = 0;
+
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					row+=1;
+					if (row>8) row = 8;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					row-=1;
+					if (row<0) row = 0;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					next = 1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					next = -1;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					while(0==(*atari_trig0));
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+		}
+
+		// wait 2 seconds
+		//for (i=0; i!=2000; ++i)
+		//{
+		//	*atari_colbk = *atari_random;
+		//	wait_us(1000);
+		//}
+
+		for (i=0x040; i!=1024; i++)
+		{
+			mem[i] = store[i];
+		}
+
+		{
+			//gtia
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+		}
+		*atari_portb = store_portb;
+		initdebug(debugmode);
+
+
+		if (reboot)
+		{
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		unsigned char volatile * mem;
+
+		// TODO - disk swapping!
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		if (selectfile(filename_d1))
+		{
+			opendrive = 1;
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		initdebug(debugmode);
+		pause_6502(0);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	opendrive = 0;
+	pause_6502(1);
+
+
+	/*	wait_us(5000000);
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+	for(;;);*/
+
+	speed = speedslow;
+	//FIXME if (2==(2&(*zpu_switches)))
+	if (0)
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+
+		wait_us(2000000);
+	}
+
+	//FIXME if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	pause_6502(1);
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	do
+	{
+		mmcInit();
+	}
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+	char const * default_filename = "BOOT.ATR";
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	for (i=0;i!=15;++i)
+	{
+		filename_d1[i] = default_filename[i];
+		filename_d2[i] = default_filename[i];
+		filename_d3[i] = default_filename[i];
+		filename_d4[i] = default_filename[i];
+		if (default_filename[i] == 0) break;
+	}
+
+	if (FR_OK!=pf_open("atarirom.bin"))
+	{
+		debug("fail\n");
+		for (i=0;i<1000;++i)
+		{
+			wait_us(200);
+			*atari_colbk = *atari_random;
+		}
+	}
+	else
+	{
+		char volatile * addr = (char volatile *)0x900000;
+		while (1)
+		{
+			int i=0;
+			read = 0;
+			pf_read(&mmc_sector_buffer[0],512,&read);
+
+			for (i=0;i!=read;++i)
+			{
+				*addr++ = mmc_sector_buffer[i];
+			}
+
+			if (read!=512) break;
+		}
+	}
+
+	opendrive = 1;
+	openfile(filename_d1);
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		/*FIXME if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}*/
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId >= 0x31 && command.deviceId < 0x34)
+ 	 	{
+			int sent = 0;
+			int drive = 0;
+
+			drive = command.deviceId&0xf;
+			if (drive!=opendrive)
+			{
+				opendrive = drive;
+				switch(drive)
+				{
+				case 1:
+					openfile(filename_d1);
+					break;
+				case 2:
+					openfile(filename_d2);
+					break;
+				case 3:
+					openfile(filename_d3);
+					break;
+				case 4:
+					openfile(filename_d4);
+					break;
+				}
+			}
+
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = 0; //get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/zpu_firmware/mcc216/mycrt0.s
===================================================================
--- unmerged/zpu_firmware/mcc216/mycrt0.s	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/zpu_firmware/mcc216/mt6502dis
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/mt6502dis
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/zpu_firmware/mcc216/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,4044 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b80f5;
+00a2 : d0738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
+00a9 : ff040000;
+00aa : 00000000;
+00ab : 00000000;
+00ac : 00000000;
+00ad : 00000000;
+00ae : 00000000;
+00af : 00000000;
+00b0 : 0b0b0b88;
+00b1 : d8040000;
+00b2 : 00000000;
+00b3 : 00000000;
+00b4 : 00000000;
+00b5 : 00000000;
+00b6 : 00000000;
+00b7 : 00000000;
+00b8 : 72097081;
+00b9 : 0509060a;
+00ba : 8106ff05;
+00bb : 70547106;
+00bc : 73097274;
+00bd : 05ff0506;
+00be : 07515151;
+00bf : 04000000;
+00c0 : 72097081;
+00c1 : 0509060a;
+00c2 : 098106ff;
+00c3 : 05705471;
+00c4 : 06730972;
+00c5 : 7405ff05;
+00c6 : 06075151;
+00c7 : 51040000;
+00c8 : 05ff0504;
+00c9 : 00000000;
+00ca : 00000000;
+00cb : 00000000;
+00cc : 00000000;
+00cd : 00000000;
+00ce : 00000000;
+00cf : 00000000;
+00d0 : 810b80fb;
+00d1 : ac0c5104;
+00d2 : 00000000;
+00d3 : 00000000;
+00d4 : 00000000;
+00d5 : 00000000;
+00d6 : 00000000;
+00d7 : 00007181;
+00d8 : 05520400;
+00d9 : 00000000;
+00da : 00000000;
+00db : 00000000;
+00dc : 00000000;
+00dd : 00000000;
+00de : 00000000;
+00df : 00000000;
+00e0 : 00000000;
+00e1 : 00000000;
+00e2 : 00000000;
+00e3 : 00000000;
+00e4 : 00000000;
+00e5 : 00000000;
+00e6 : 00000000;
+00e7 : 00000284;
+00e8 : 05721010;
+00e9 : 05520400;
+00ea : 00000000;
+00eb : 00000000;
+00ec : 00000000;
+00ed : 00000000;
+00ee : 00000000;
+00ef : 00000000;
+00f0 : 00000000;
+00f1 : 00000000;
+00f2 : 00000000;
+00f3 : 00000000;
+00f4 : 00000000;
+00f5 : 00000000;
+00f6 : 00000000;
+00f7 : 00007171;
+00f8 : 05ff0571;
+00f9 : 5351020d;
+00fa : 04000000;
+00fb : 00000000;
+00fc : 00000000;
+00fd : 00000000;
+00fe : 00000000;
+00ff : 00000000;
+0100 : 10101010;
+0101 : 10101010;
+0102 : 10101010;
+0103 : 10101010;
+0104 : 10101010;
+0105 : 10101010;
+0106 : 10101010;
+0107 : 10101053;
+0108 : 51047381;
+0109 : ff067383;
+010a : 06098105;
+010b : 83051010;
+010c : 102b0772;
+010d : fc060c51;
+010e : 51043c04;
+010f : 72728072;
+0110 : 8106ff05;
+0111 : 09720605;
+0112 : 71105272;
+0113 : 0a100a53;
+0114 : 72ed3851;
+0115 : 51535104;
+0116 : 83e08008;
+0117 : 83e08408;
+0118 : 83e08808;
+0119 : 757580ef;
+011a : fe2d5050;
+011b : 83e08008;
+011c : 5683e088;
+011d : 0c83e084;
+011e : 0c83e080;
+011f : 0c510483;
+0120 : e0800883;
+0121 : e0840883;
+0122 : e0880875;
+0123 : 7580ee92;
+0124 : 2d505083;
+0125 : e0800856;
+0126 : 83e0880c;
+0127 : 83e0840c;
+0128 : 83e0800c;
+0129 : 51040000;
+012a : 800489aa;
+012b : 0489aa0b;
+012c : 80c1a404;
+012d : fd3d0d75;
+012e : b9297681;
+012f : 2a0580fd;
+0130 : fc085473;
+0131 : 0c853d0d;
+0132 : 04803d0d;
+0133 : 81ff5180;
+0134 : 0b83e0c8;
+0135 : 1234ff11;
+0136 : 5170f438;
+0137 : 823d0d04;
+0138 : fa3d0d78;
+0139 : 0b0b80f6;
+013a : a85383e2;
+013b : f4525680;
+013c : cdd13f80;
+013d : 5383e080;
+013e : 08732e8a;
+013f : 387283e0;
+0140 : 800c883d;
+0141 : 0d0483e0;
+0142 : 945283e2;
+0143 : f45180ce;
+0144 : c53f83e0;
+0145 : 800880d5;
+0146 : 3883e09d;
+0147 : 33537280;
+0148 : 2e80ca38;
+0149 : 83e09c33;
+014a : 70822a70;
+014b : 81065154;
+014c : 5472d338;
+014d : 73812a70;
+014e : 81065153;
+014f : 72c83873;
+0150 : 842a7081;
+0151 : 06515372;
+0152 : ffbc3875;
+0153 : 83e09d56;
+0154 : 54733375;
+0155 : 33585372;
+0156 : 772e0981;
+0157 : 06ffa738;
+0158 : 72802e93;
+0159 : 38811481;
+015a : 165654e5;
+015b : 39800b83;
+015c : e0800c88;
+015d : 3d0d0483;
+015e : e0940883;
+015f : e0800c88;
+0160 : 3d0d04fd;
+0161 : 3d0d800b;
+0162 : 80fdec08;
+0163 : 5353ff72;
+0164 : 0c80fdf0;
+0165 : 0873710c;
+0166 : 5284d851;
+0167 : fe963f88;
+0168 : 800a5380;
+0169 : 73708105;
+016a : 553472a8;
+016b : 800a2e09;
+016c : 8106f038;
+016d : 80fdec08;
+016e : 5485aad5;
+016f : aad5740c;
+0170 : 80fdf008;
+0171 : 5285aad5;
+0172 : aad5720c;
+0173 : 82800a53;
+0174 : 80737084;
+0175 : 05550c72;
+0176 : 81800a2e;
+0177 : 098106f0;
+0178 : 3880740c;
+0179 : ff720c84;
+017a : d851fdc8;
+017b : 3f853d0d;
+017c : 04fd3d0d;
+017d : 800b80fd;
+017e : ec085353;
+017f : ff87c3e1;
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+0e8c : 8c0c04fc;
+0e8d : 3d0d7670;
+0e8e : 797b5555;
+0e8f : 55558f72;
+0e90 : 278c3872;
+0e91 : 75078306;
+0e92 : 5170802e;
+0e93 : a938ff12;
+0e94 : 5271ff2e;
+0e95 : 98387270;
+0e96 : 81055433;
+0e97 : 74708105;
+0e98 : 5634ff12;
+0e99 : 5271ff2e;
+0e9a : 098106ea;
+0e9b : 387483e0;
+0e9c : 800c863d;
+0e9d : 0d047451;
+0e9e : 72708405;
+0e9f : 54087170;
+0ea0 : 8405530c;
+0ea1 : 72708405;
+0ea2 : 54087170;
+0ea3 : 8405530c;
+0ea4 : 72708405;
+0ea5 : 54087170;
+0ea6 : 8405530c;
+0ea7 : 72708405;
+0ea8 : 54087170;
+0ea9 : 8405530c;
+0eaa : f0125271;
+0eab : 8f26c938;
+0eac : 83722795;
+0ead : 38727084;
+0eae : 05540871;
+0eaf : 70840553;
+0eb0 : 0cfc1252;
+0eb1 : 718326ed;
+0eb2 : 387054ff;
+0eb3 : 81390000;
+0eb4 : 00ffffff;
+0eb5 : ff00ffff;
+0eb6 : ffff00ff;
+0eb7 : ffffff00;
+0eb8 : 70707042;
+0eb9 : 409c0202;
+0eba : 02020202;
+0ebb : 02020202;
+0ebc : 02020202;
+0ebd : 02020202;
+0ebe : 02020202;
+0ebf : 02704100;
+0ec0 : 06000000;
+0ec1 : 70707042;
+0ec2 : 409c0202;
+0ec3 : 02020202;
+0ec4 : 02020202;
+0ec5 : 02020202;
+0ec6 : 02020202;
+0ec7 : 02020202;
+0ec8 : 02704100;
+0ec9 : 9c000000;
+0eca : 2f000000;
+0ecb : 4f70656e;
+0ecc : 696e673a;
+0ecd : 00000000;
+0ece : 6661696c;
+0ecf : 0a000000;
+0ed0 : 6f6b0a00;
+0ed1 : 436f756c;
+0ed2 : 64206e6f;
+0ed3 : 74207265;
+0ed4 : 61642068;
+0ed5 : 65616465;
+0ed6 : 720a0000;
+0ed7 : 556e6b6e;
+0ed8 : 6f776e20;
+0ed9 : 66696c65;
+0eda : 20747970;
+0edb : 65000000;
+0edc : 41545220;
+0edd : 00000000;
+0ede : 58442000;
+0edf : 300a0000;
+0ee0 : 58464420;
+0ee1 : 00000000;
+0ee2 : 42414420;
+0ee3 : 73656374;
+0ee4 : 6f722073;
+0ee5 : 697a6500;
+0ee6 : 4d442000;
+0ee7 : 58455820;
+0ee8 : 00000000;
+0ee9 : 53442000;
+0eea : 44442000;
+0eeb : 44495220;
+0eec : 00000000;
+0eed : 6f70656e;
+0eee : 64697220;
+0eef : 6661696c;
+0ef0 : 65640a00;
+0ef1 : 426f6f74;
+0ef2 : 696e672e;
+0ef3 : 2e2e0000;
+0ef4 : 53797374;
+0ef5 : 656d2073;
+0ef6 : 65747469;
+0ef7 : 6e67730a;
+0ef8 : 00000000;
+0ef9 : 2d2d2d2d;
+0efa : 2d2d2d2d;
+0efb : 2d2d2d2d;
+0efc : 2d2d2d0a;
+0efd : 00000000;
+0efe : 4d656d6f;
+0eff : 72793a00;
+0f00 : 556e6b6e;
+0f01 : 6f776e00;
+0f02 : 524f4d20;
+0f03 : 62616e6b;
+0f04 : 3a000000;
+0f05 : 53706565;
+0f06 : 643a0000;
+0f07 : 204b487a;
+0f08 : 0a44313a;
+0f09 : 00000000;
+0f0a : 0a44323a;
+0f0b : 00000000;
+0f0c : 0a44333a;
+0f0d : 00000000;
+0f0e : 0a44343a;
+0f0f : 00000000;
+0f10 : 0a526562;
+0f11 : 6f6f7400;
+0f12 : 0a457869;
+0f13 : 74000000;
+0f14 : 3332304b;
+0f15 : 69422052;
+0f16 : 616d626f;
+0f17 : 00000000;
+0f18 : 30202864;
+0f19 : 65666175;
+0f1a : 6c743a58;
+0f1b : 4c290000;
+0f1c : 31202864;
+0f1d : 65666175;
+0f1e : 6c743a58;
+0f1f : 4c202b20;
+0f20 : 68692073;
+0f21 : 70656564;
+0f22 : 29000000;
+0f23 : 3332304b;
+0f24 : 69422043;
+0f25 : 6f6d7079;
+0f26 : 2053686f;
+0f27 : 70000000;
+0f28 : 36344b69;
+0f29 : 42000000;
+0f2a : 3132384b;
+0f2b : 69420000;
+0f2c : 32202864;
+0f2d : 65666175;
+0f2e : 6c743a55;
+0f2f : 6c74696d;
+0f30 : 6f6e2900;
+0f31 : 33202864;
+0f32 : 65666175;
+0f33 : 6c743a4f;
+0f34 : 53204220;
+0f35 : 2b206869;
+0f36 : 20737065;
+0f37 : 65642900;
+0f38 : 636d643a;
+0f39 : 00000000;
+0f3a : 45525220;
+0f3b : 00000000;
+0f3c : 53504453;
+0f3d : 00000000;
+0f3e : 53504446;
+0f3f : 00000000;
+0f40 : 2873656e;
+0f41 : 643a0000;
+0f42 : 3a63686b;
+0f43 : 3a000000;
+0f44 : 73646361;
+0f45 : 72640a00;
+0f46 : 6469736b;
+0f47 : 5f696e69;
+0f48 : 743a0000;
+0f49 : 6d6f756e;
+0f4a : 743a0000;
+0f4b : 6f70656e;
+0f4c : 6469723a;
+0f4d : 00000000;
+0f4e : 424f4f54;
+0f4f : 2e415452;
+0f50 : 00000000;
+0f51 : 61746172;
+0f52 : 69726f6d;
+0f53 : 2e62696e;
+0f54 : 00000000;
+0f55 : 53746174;
+0f56 : 3a000000;
+0f57 : 3a646f6e;
+0f58 : 650a0000;
+0f59 : 53656374;
+0f5a : 6f723a00;
+0f5b : 20726563;
+0f5c : 65697665;
+0f5d : 3a000000;
+0f5e : 2073656e;
+0f5f : 64696e67;
+0f60 : 0a000000;
+0f61 : 64617461;
+0f62 : 20000000;
+0f63 : 626f6f74;
+0f64 : 20000000;
+0f65 : 6e616d65;
+0f66 : 20000000;
+0f67 : 6e756d74;
+0f68 : 6f627566;
+0f69 : 66657220;
+0f6a : 00000000;
+0f6b : 00000000;
+0f6c : 00000000;
+0f6d : 72025f07;
+0f6e : f807a900;
+0f6f : 8d04038d;
+0f70 : 4402a907;
+0f71 : 8d0503a9;
+0f72 : 708d0a03;
+0f73 : a9018d0b;
+0f74 : 03850960;
+0f75 : 7d8a4820;
+0f76 : 53e488d0;
+0f77 : fa68aa8c;
+0f78 : 8e07ad7d;
+0f79 : 07ee8e07;
+0f7a : 60a9938d;
+0f7b : e202a907;
+0f7c : 8de302a2;
+0f7d : 0220da07;
+0f7e : 954320da;
+0f7f : 07954435;
+0f80 : 43c9fff0;
+0f81 : f0caca10;
+0f82 : ec3006e6;
+0f83 : 45d002e6;
+0f84 : 4620da07;
+0f85 : a2018144;
+0f86 : b545d543;
+0f87 : d0edca10;
+0f88 : f720d207;
+0f89 : 4c9407a9;
+0f8a : 038d0fd2;
+0f8b : 6ce202ad;
+0f8c : 8e07cd7f;
+0f8d : 07d0abee;
+0f8e : 0a03d003;
+0f8f : ee0b03ad;
+0f90 : 7d070d7e;
+0f91 : 07d08e20;
+0f92 : d2076ce0;
+0f93 : 0220da07;
+0f94 : 8de00220;
+0f95 : da078de1;
+0f96 : 022de002;
+0f97 : c9fff0ed;
+0f98 : a9008d8e;
+0f99 : 07f08200;
+0f9a : 0001d20f;
+0f9b : 0001d400;
+0f9c : 0001d401;
+0f9d : 0001d409;
+0f9e : 0001d010;
+0f9f : 0001d301;
+0fa0 : 0001d300;
+0fa1 : 0001d20a;
+0fa2 : 0001d01b;
+0fa3 : 0001d018;
+0fa4 : 0001d017;
+0fa5 : 0001d01a;
+0fa6 : 0001d403;
+0fa7 : 0001d402;
+0fa8 : 0001d40e;
+0fa9 : 0004007c;
+0faa : 00040078;
+0fab : 00040074;
+0fac : 00040068;
+0fad : 00040060;
+0fae : 0004005c;
+0faf : 00040058;
+0fb0 : 00040054;
+0fb1 : 00040050;
+0fb2 : 0004004c;
+0fb3 : 00040048;
+0fb4 : 00040044;
+0fb5 : 00040040;
+0fb6 : 00040028;
+0fb7 : 00040024;
+0fb8 : 00040020;
+0fb9 : 0004001c;
+0fba : 00040018;
+0fbb : 00040014;
+0fbc : 00040010;
+0fbd : 0004000c;
+0fbe : 00040008;
+0fbf : 00040004;
+0fc0 : 00040000;
+END; 
Index: unmerged/zpu_firmware/mcc216/regs.c
===================================================================
--- unmerged/zpu_firmware/mcc216/regs.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/regs.c	(revision 1)
@@ -0,0 +1,49 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x40000
+int volatile * zpu_config = (int *)(0*4+regbase);
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_chactl = (unsigned char *)(0xd401 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+unsigned char volatile * atari_skctl = (unsigned char *)(0xd20f + 0x10000);
+
+#endif // regs_h
Index: unmerged/zpu_firmware/mcc216/pff.h
===================================================================
--- unmerged/zpu_firmware/mcc216/pff.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/zpu_firmware/mcc216/bootdump.c
===================================================================
--- unmerged/zpu_firmware/mcc216/bootdump.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/zpu_firmware/mcc216/crt0.S
===================================================================
--- unmerged/zpu_firmware/mcc216/crt0.S	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/crt0.S	(revision 1)
@@ -0,0 +1,974 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	
+	
+	
+;	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+; DANGER!!!! 
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!! 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jsr address
+			im _memreg     	; save R0
+			load
+			im _memreg+4	; save R1
+			load
+			im _memreg+8	; save R2
+			load
+			fixedim \address
+			call
+			im _memreg+8
+			store		; restore R2
+			im _memreg+4
+			store		; restore R1
+			im _memreg
+			store		; restore R0
+	.endm
+
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+		
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		; intSp must be 0 when we jump to _premain
+		
+		im ZPU_ID
+		loadsp 0
+		im _cpu_config
+		store
+		config
+		jmp _premain
+
+
+
+        .balign 32,0
+# offset 0x0000 0020
+		.globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+		jmp ___zpu_interrupt_vector
+
+
+        .balign 16,0
+# offset 0x0000 0030
+		.globl _memreg
+		.weak _memreg
+_memreg:
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+        .globl ___zpu_interrupt_vector
+        .weak ___zpu_interrupt_vector
+
+___zpu_interrupt_vector:
+	jsr _zpu_interrupt
+	poppc
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+

Property changes on: unmerged/zpu_firmware/mcc216/crt0.S
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/fat.c
===================================================================
--- unmerged/zpu_firmware/mcc216/fat.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/fat.c	(revision 1)
@@ -0,0 +1,445 @@
+/*! \file fat.c \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.c'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// This code is based in part on work done by Jesper Hansen for his
+//		YAMPP MP3 player project.
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include <stdio.h>
+#include <string.h>
+
+#include "fat.h"
+#include "mmc.h"
+#include "spi.h"
+
+void USART_SendString(char *buff);
+void mmcReadCached(u32 sector);
+
+
+#define FileNameBuffer atari_sector_buffer
+extern unsigned char atari_sector_buffer[256];
+extern unsigned char mmc_sector_buffer[512];	// one sector
+extern struct GlobalSystemValues GS;
+extern struct FileInfoStruct FileInfo;			//< file information for last file accessed
+
+
+unsigned long fatClustToSect(unsigned short clust)
+{
+	u32 ret;
+	if(clust==MSDOSFSROOT)
+	{
+		debug("fatClustToSect:");
+		u32 res = (u32)((u32)(FirstDataSector) - (u32)(RootDirSectors));
+		plotnextnumber(res);
+		debug(" ");
+		plotnextnumber(FirstDataSector);
+		debug(" ");
+		plotnextnumber(RootDirSectors);
+		debug("\n");
+		return res;
+	}
+	
+	ret = (u32)(clust-2);
+	ret *= (u32)SectorsPerCluster;
+	ret += (u32)FirstDataSector;
+	return ((unsigned long)ret);
+}
+
+
+//POZOR - DEBUG !!!
+//prvne definovana promenna
+u32 debug_endofvariables;		//promenna co je v pameti jako posledni (za ni je uz jen stack)
+//POZOR - DEBUG !!!
+
+unsigned short last_dir_start_cluster;
+unsigned char last_dir_valid;
+unsigned short last_dir_entry;
+unsigned long last_dir_sector;
+unsigned char last_dir_sector_count;
+unsigned short last_dir_cluster;
+unsigned char last_dir_index;
+
+
+unsigned char fatInit()
+{
+	struct partrecord PartInfo;
+	struct bpb710 *bpb;
+
+	// Moved here since init vars are in ROM!
+	last_dir_entry=0x0;
+	last_dir_sector=0;
+	last_dir_sector_count=0;
+	last_dir_cluster=0;
+	last_dir_index=0;
+
+	// read partition table
+	// TODO.... error checking
+	debug("FAT INIT:");
+	mmcReadCached(0);
+	// map first partition record	
+	// save partition information to global PartInfo
+	PartInfo = *((struct partrecord *) ((struct partsector *) (char*)mmc_sector_buffer)->psPart);
+
+	if(mmc_sector_buffer[0x36]=='F' && mmc_sector_buffer[0x37]=='A' && mmc_sector_buffer[0x38]=='T' && mmc_sector_buffer[0x39]=='1' && mmc_sector_buffer[0x3a]=='6')
+	{
+		PartInfo.prPartType = PART_TYPE_FAT16LBA; //0x04
+		PartInfo.prStartLBA = 0x00;
+	}
+	
+	// Read the Partition BootSector
+	// **first sector of partition in PartInfo.prStartLBA
+	mmcReadCached(PartInfo.prStartLBA);
+	bpb = (struct bpb710 *) ((struct bootsector710 *) (char*)mmc_sector_buffer)->bsBPB;
+
+	// setup global disk constants
+	PartInfo.prStartLBA = 0x1e8; // FIXME
+	FirstDataSector	= PartInfo.prStartLBA;
+
+	RootDirSectors = bpb->bpbRootDirEnts>>4; // /16 ; 512/16 = 32  (sector size / max entries in one sector = number of sectors)
+
+	debug("PartInto ");
+	plotnextnumber(PartInfo.prStartLBA);
+	debug(" ");
+	plotnextnumber(bpb->bpbRootDirEnts>>4);
+	debug("\n");
+
+	// bpbFATsecs is non-zero and is therefore valid
+	FirstDataSector	+= bpb->bpbResSectors + bpb->bpbFATs * bpb->bpbFATsecs + RootDirSectors;
+
+	SectorsPerCluster	= bpb->bpbSecPerClust;
+	BytesPerSector		= bpb->bpbBytesPerSec;
+	FirstFATSector		= bpb->bpbResSectors + PartInfo.prStartLBA;
+
+	// set current directory to root (\)
+	FileInfo.vDisk.dir_cluster = MSDOSFSROOT; //RootDirStartCluster;
+
+    last_dir_start_cluster=0xffff;
+	//last_dir_valid=0;		//<-- neni potreba, protoze na zacatku fatGetDirEntry se pri zjisteni
+							//ze je (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+							//vynuluje last_dir_valid=0;
+
+	if (   PartInfo.prPartType==PART_TYPE_DOSFAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16LBA
+	   )
+	{
+		return 1; //je to ok
+		debug("OK\n");
+	}
+	else
+	{
+		return 0; //neni to zadny filesystem co umime
+		debug("FAIL\n");
+	}
+}
+
+//////////////////////////////////////////////////////////////
+
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names)
+{
+	unsigned long sector;
+	struct direntry *de = 0;	// avoid compiler warning by initializing
+	struct winentry *we;
+	unsigned char haveLongNameEntry;
+	unsigned char gotEntry;
+	unsigned short b;
+	u08 index;
+	unsigned short entrycount = 0;
+	unsigned short actual_cluster = FileInfo.vDisk.dir_cluster;
+	unsigned char seccount=0;
+
+	haveLongNameEntry = 0;
+	gotEntry = 0;
+
+	if (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+	{
+		//zmenil se adresar, takze musi pracovat s nim
+		//a zneplatnit last_dir polozky
+		last_dir_start_cluster=FileInfo.vDisk.dir_cluster;
+		last_dir_valid=0;
+
+		debug("LastDirStartCluster:");
+		plotnextnumber(last_dir_start_cluster);
+		plotnextnumber(last_dir_valid);
+		debug("\n");
+	}
+
+	if ( !last_dir_valid
+		 || (entry<=last_dir_entry && (entry!=last_dir_entry || last_dir_valid!=1 || use_long_names!=0))
+	   )
+	{
+		//musi zacit od zacatku
+		sector = fatClustToSect(FileInfo.vDisk.dir_cluster);
+		//index = 0;
+		debug("ReadFromBegin:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_begin;
+	}
+	else
+	{
+		//muze zacit od posledne pouzite
+		entrycount=last_dir_entry;
+		index = last_dir_index;
+		sector=last_dir_sector;
+		actual_cluster=last_dir_cluster;
+		seccount = last_dir_sector_count;
+		debug("ReadFromLastEntry:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_last_entry;
+	}
+
+	while(1)
+	{
+		debug("Index:");
+		plotnextnumber(index);
+		debug("\n");
+		if(index==16)	// time for next sector ?
+		{
+			if ( actual_cluster==MSDOSFSROOT )
+			{
+				//v MSDOSFSROOT se nerozlisuji clustery
+				//protoze MSDOSFSROOT ma sektory stale dal za sebou bez clusterovani
+				if (seccount>=RootDirSectors) return 0; //prekrocil maximalni pocet polozek v MSDOSFSROOT
+			}
+			else //MUSI BYT!!! (aby neporovnaval seccount je-li actual_cluster==MSDOSFSROOT)
+			if( seccount>=SectorsPerCluster )
+			{
+				//next cluster
+				//pri prechodu pres pocet sektoru v clusteru
+				actual_cluster = nextCluster(actual_cluster);
+				sector=fatClustToSect(actual_cluster);
+				seccount=0;
+			}
+fat_read_from_begin:
+			index = 0;
+			seccount++;		//ted bude nacitat dalsi sektor (musi ho zapocitat)
+fat_read_from_last_entry:
+			mmcReadCached( sector++ ); 	//prave ho nacetl
+			de = (struct direntry *) (char*)mmc_sector_buffer;
+			de+=index;
+		}
+		
+		// check the status of this directory entry slot
+		if(de->deName[0] == 0x00) //SLOT_EMPTY
+		{
+			// slot is empty and this is the end of directory
+			gotEntry = 0;
+			break;
+		}
+		else if(de->deName[0] == 0xE5)	//SLOT_DELETED
+		{
+			// this is an empty slot
+			// do nothing and move to the next one
+		}
+		else
+		{
+			// this is a valid and occupied entry
+			// is it a part of a long file/dir name?
+			if( de->deAttributes==ATTR_LONG_FILENAME )
+			{
+				// we have a long name entry
+				// cast this directory entry as a "windows" (LFN: LongFileName) entry
+				u08 i;
+				unsigned char *fnbPtr;
+
+				//pokud nechceme longname, NESMI je vubec kompletovat
+				//a preskoci na dalsi polozku
+				//( takze ani haveLongNameEntry nikdy nebude nastaveno na 1)
+				//Jinak by totiz preplacaval dalsi kusy atari_sector_bufferu 12-255 ! BACHA!!!
+				if (!use_long_names) goto fat_next_dir_entry;
+
+				we = (struct winentry *) de;
+				
+				b = WIN_ENTRY_CHARS*( (unsigned short)((we->weCnt-1) & 0x0f));		// index into string
+				fnbPtr = &FileNameBuffer[b];
+
+				for (i=0;i<5;i++)	*fnbPtr++ = we->wePart1[i*2];	// copy first part
+				for (i=0;i<6;i++)	*fnbPtr++ = we->wePart2[i*2];	// second part
+				for (i=0;i<2;i++)	*fnbPtr++ = we->wePart3[i*2];	// and third part
+
+				/*
+				{
+				//unsigned char * sptr;
+				//sptr=we->wePart1;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart1+10)); // copy first part
+				//^-- pouziti jen tohoto prvniho a druhe dva pres normalni for(..) uspori 10 bajtu,
+				//pri pouziti i dalsich dvou timto stylem uz se to ale zase prodlouzi - nechaaaaaapu!
+				//sptr=we->wePart2;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart2+12)); // second part
+				//sptr=we->wePart3;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart3+4));  // and third part
+				}
+				*/
+
+				if (we->weCnt & WIN_LAST) *fnbPtr = 0;				// in case dirnamelength is multiple of 13, add termination
+				if ((we->weCnt & 0x0f) == 1) haveLongNameEntry = 1;	// flag that we have a complete long name entry set
+			}
+			else
+			{
+				// we have a short name entry
+				
+				// check if this is the short name entry corresponding
+				// to the end of a multi-part long name entry
+				if(haveLongNameEntry)
+				{
+					// a long entry name has been collected
+					if(entrycount == entry)		
+					{
+						// desired entry has been found, break out
+						gotEntry = 2;
+						break;
+					}
+					// otherwise
+					haveLongNameEntry = 0;	// clear long name flag
+					entrycount++;			// increment entry counter		
+				}
+				else
+				{
+					// entry is a short name (8.3 format) without a
+					// corresponding multi-part long name entry
+
+					//Zcela vynecha adresar "." a disk label
+					if( (de->deName[0]=='.' && de->deName[1]==' ' && (de->deAttributes & ATTR_DIRECTORY) ) //je to "." adresar
+						|| (de->deAttributes & ATTR_VOLUME) ) goto fat_next_dir_entry;
+
+					if(entrycount == entry)
+					{
+						/*
+						fnbPtr = &FileNameBuffer[string_offset];
+						for (i=0;i<8;i++)	*fnbPtr++ = de->deName[i];		// copy name
+						for (i=0;i<3;i++)	*fnbPtr++ = de->deExtension[i];	// copy extension
+						*fnbPtr = 0;										// null-terminate
+						*/
+						u08 i;
+						unsigned char *dptr;
+
+						dptr = &FileNameBuffer;
+						for (i=0;i<11;i++)	*dptr++ = de->deName[i];		// copy name+ext
+						*dptr=0;	//ukonceni za nazvem
+
+						// desired entry has been found, break out
+						//pokud chtel longname, tak to neni a proto upravi 8+3 jmeno na nazev.ext
+						//aby to melo formatovani jako longname
+						if (use_long_names)
+						{
+							//upravi 'NAME    EXT' na 'NAME.EXT'
+							//(vyhazi mezery a prida tecku)
+							//krome nazvu '.          ', a '..         ', tam jen vyhaze mezery
+							unsigned char *sptr;
+							//EXT => .EXT   (posune vcetne 0x00 za koncem extenderu)
+							dptr=(FileNameBuffer+12);
+							i=4; do { sptr=dptr-1; *dptr=*sptr; dptr=sptr; i--; } while(i>0);
+							if (FileNameBuffer[0]!='.') *dptr='.'; //jen pro jine nez '.' a '..'
+							//NAME    .EXT => NAME.EXT
+							sptr=dptr=&FileNameBuffer;
+							do
+							{
+							 if ((*sptr)!=' ') *dptr++=*sptr;
+							 sptr++;
+							} while (*sptr);
+							*dptr=0; //ukonceni
+						}
+						//
+						gotEntry = 1;
+						break;
+					}
+					// otherwise
+					entrycount++;			// increment entry counter		
+				}
+			}
+		}
+fat_next_dir_entry:
+		// next directory entry
+		de++;
+		// next index
+		index++;
+	}
+	
+	// we have a file/dir to return
+	// store file/dir starting cluster (start of data)
+	FileInfo.vDisk.start_cluster = (unsigned short) (de->deStartCluster);
+	// fileindex
+	FileInfo.vDisk.file_index = entry;	//fileindex teto polozky
+	// store file/dir size (note: size field for subdirectory entries is always zero)
+	FileInfo.vDisk.size = de->deFileSize;
+	// store file/dir attributes
+	FileInfo.Attr = de->deAttributes;
+	// store file/dir last update time
+	FileInfo.Time = (unsigned short) (de->deMTime[0] | de->deMTime[1]<<8);
+	// store file/dir last update date
+	FileInfo.Date = (unsigned short) (de->deMDate[0] | de->deMDate[1]<<8);
+
+	if(gotEntry)
+	{
+		debug(" gotEntry ");
+		last_dir_entry = entrycount;
+		last_dir_index = index;
+		last_dir_sector = sector-1; //protoze ihned po nacteni se posune
+		last_dir_cluster = actual_cluster;
+		last_dir_sector_count = seccount; //skace se az za inkrementaci seccount, takze tady se 1 neodecita!
+		last_dir_valid=gotEntry;
+	}
+	else
+	{
+		debug(" not gotEntry ");
+	}
+
+	return gotEntry;
+}
+
+
+unsigned short nextCluster(unsigned short cluster)
+{
+	  unsigned short nextCluster;
+	  unsigned long fatOffset;
+	  unsigned long sector;
+	  unsigned long offset;
+
+	  // two FAT bytes (16 bits) for every cluster
+	  fatOffset = ((u32)cluster) << 1;
+
+	  // calculate the FAT sector that we're interested in
+	  sector = FirstFATSector + (fatOffset / ((u32)BytesPerSector));
+	  // calculate offset of the our entry within that FAT sector
+	  offset = fatOffset % ((u32)BytesPerSector);
+
+	  // if we don't already have this FAT chunk loaded, go get it
+	  // read sector of FAT table
+  	  mmcReadCached( sector );
+
+	  // read the nextCluster value
+	  nextCluster = (*((unsigned short*) &((char*)mmc_sector_buffer)[offset])) & FAT16_MASK;
+
+	  // check to see if we're at the end of the chain
+	  if (nextCluster == (CLUST_EOFE & FAT16_MASK))
+		nextCluster = 0;
+
+	return (nextCluster&0xFFFF);
+}
Index: unmerged/zpu_firmware/mcc216/led.h
===================================================================
--- unmerged/zpu_firmware/mcc216/led.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/zpu_firmware/mcc216/mmcconf.h
===================================================================
--- unmerged/zpu_firmware/mcc216/mmcconf.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/mmcconf.h	(revision 1)
@@ -0,0 +1,33 @@
+/*! \file mmcconf.h \brief MultiMedia and SD Flash Card Interface Configuration. */
+//*****************************************************************************
+//
+// File Name	: 'mmcconf.h'
+// Title		: MultiMedia and SD Flash Card Interface Configuration
+// Author		: Pascal Stang - Copyright (C) 2004
+// Created		: 2004.09.22
+// Revised		: 2004.09.22
+// Version		: 0.1
+// Target MCU	: Atmel AVR Series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef MMCCONF_H
+#define MMCCONF_H
+
+#endif
Index: unmerged/zpu_firmware/mcc216/pff.c
===================================================================
--- unmerged/zpu_firmware/mcc216/pff.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/zpu_firmware/mcc216/rom_epilogue.vhd
===================================================================
--- unmerged/zpu_firmware/mcc216/rom_epilogue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/zpu_firmware/mcc216/spi.h
===================================================================
--- unmerged/zpu_firmware/mcc216/spi.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/spi.h	(revision 1)
@@ -0,0 +1,65 @@
+/*! \file spi.h \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.h'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup driver_avr
+/// \defgroup spi SPI (Serial Peripheral Interface) Function Library (spi.c)
+/// \code #include "spi.h" \endcode
+/// \par Overview
+///		Provides basic byte and word transmitting and receiving via the AVR
+///	SPI interface.� Due to the nature of SPI, every SPI communication operation
+/// is both a transmit and simultaneous receive.
+///
+///	\note Currently, only MASTER mode is supported.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+
+#ifndef SPI_H
+#define SPI_H
+
+#include "types.h"
+
+// function prototypes
+void mmcChipSelect(int select);
+
+
+// SPI interface initializer
+void spiInit(void);
+
+// spiTransferByte(u08 data) waits until the SPI interface is ready
+// and then sends a single byte over the SPI port.  The function also
+// returns the byte that was received during transmission.
+u08 spiTransferByte(u08 data);
+
+// spiTransferWord(u08 data) works just like spiTransferByte but
+// operates on a whole word (16-bits of data).
+u08 spiTransferFF();
+void spiTransferTwoFF();
+
+void spiDisplay(int i);
+
+#endif
Index: unmerged/zpu_firmware/mcc216/types.h
===================================================================
--- unmerged/zpu_firmware/mcc216/types.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/zpu_firmware/mcc216/zpuromgen
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mcc216/zpuromgen
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/HelloTinyROM.rpt
===================================================================
--- unmerged/zpu_firmware/mist/HelloTinyROM.rpt	(nonexistent)
+++ unmerged/zpu_firmware/mist/HelloTinyROM.rpt	(revision 1)
@@ -0,0 +1,3 @@
+End of code:	00003c08 g       *ABS*	00000000 _romend
+Start of BSS:	0000f000 g       .bss	00000000 __bss_start__
+End of BSS:	0000f1fc g       *ABS*	00000000 __bss_end__
Index: unmerged/zpu_firmware/mcc216/spi.c
===================================================================
--- unmerged/zpu_firmware/mcc216/spi.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/spi.c	(revision 1)
@@ -0,0 +1,116 @@
+/*! \file spi.c \brief SPI interface driver. */
+//*****************************************************************************
+//
+// File Name	: 'spi.c'
+// Title		: SPI interface driver
+// Author		: Pascal Stang - Copyright (C) 2000-2002
+// Created		: 11/22/2000
+// Revised		: 06/06/2002
+// Version		: 0.6
+// Target MCU	: Atmel AVR series
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include "spi.h"
+
+#include "regs.h"
+#include "spi.h"
+
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+	updateSpiState();
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+	updateSpiState();
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+}
+
Index: unmerged/zpu_firmware/mcc216/test.c
===================================================================
--- unmerged/zpu_firmware/mcc216/test.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/test.c	(revision 1)
@@ -0,0 +1,71 @@
+
+
+unsigned char toatarichar(int val)
+{
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else
+	{
+		val = 0;
+	}
+	return val;
+}
+
+int xpos = 0;
+int ypos = 0;
+
+void nextline()
+{
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+}
+void plot(unsigned char a, int x, int y)
+{
+	printf("%d %d %d\n",a,x,y);
+}
+
+void debug(char const * str)
+{
+//        char buffer[256];
+//        buffer[0] = 'W';
+//        buffer[1] = 'T';
+//        buffer[2] = 'F';
+//        buffer[3] = 0;
+//        str = buffer;
+
+        while (1)
+        {
+                int val = *str++;
+                if (val==0) break;
+
+                plot(toatarichar(val),xpos,ypos);
+                ++xpos;
+                if (xpos==40)
+                {
+                        nextline();
+                }
+        }
+        nextline();
+        //Delay100usX(10000);
+}
+
+
+int main(void)
+{
+	printf("%d %d\n", 'H', toatarichar('H'));
+	debug("Goodbye sweet world!");
+	return 0;
+}
+
Index: unmerged/zpu_firmware/mcc216/setup
===================================================================
--- unmerged/zpu_firmware/mcc216/setup	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/zpu_firmware/mcc216/stuff.c
===================================================================
--- unmerged/zpu_firmware/mcc216/stuff.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/stuff.c	(revision 1)
@@ -0,0 +1,13 @@
+#include "regs.h"
+#include "regs.c"
+#include "main.c"
+#include "fat.c" 
+#include "SDrive.c"
+#include "mmc.c"
+#include "spi.c"
+#include "uart.c"
+#include "led.c"
+#include "pind.c" 
+#include "eeprom.c"
+#include "pause.c"
+
Index: unmerged/zpu_firmware/mcc216/uart.h
===================================================================
--- unmerged/zpu_firmware/mcc216/uart.h	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/zpu_firmware/mist/HelloTinyROM.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/HelloTinyROM.bin
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/Makefile
===================================================================
--- unmerged/zpu_firmware/mist/Makefile	(nonexistent)
+++ unmerged/zpu_firmware/mist/Makefile	(revision 1)
@@ -0,0 +1,86 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c pff.c uart.c led.c regs.c debug.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O2 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -Os
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/zpu_firmware/mist/bootloader
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/bootloader
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/debug.c
===================================================================
--- unmerged/zpu_firmware/mist/debug.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/debug.c	(revision 1)
@@ -0,0 +1,178 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+int debugoffsetval;
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val+debugoffsetval;
+}
+void debugoffset(int x)
+{
+	debugoffsetval = x;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+	debugoffsetval = 0;
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+	debugoffsetval = 0;
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/mcc216/rom_prologue.vhd
===================================================================
--- unmerged/zpu_firmware/mcc216/rom_prologue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/zpu_firmware/mcc216/standalone_simple.ld
===================================================================
--- unmerged/zpu_firmware/mcc216/standalone_simple.ld	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/zpu_firmware/mcc216/uart.c
===================================================================
--- unmerged/zpu_firmware/mcc216/uart.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/mcc216/zpuromgen.c
===================================================================
--- unmerged/zpu_firmware/mcc216/zpuromgen.c	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/zpu_firmware/mist/bootdump
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/bootdump
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/chksum.c
===================================================================
--- unmerged/zpu_firmware/mist/chksum.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/chksum.c	(revision 1)
@@ -0,0 +1,40 @@
+unsigned char abuffer[] = {
+0x00,0x03,0x00,0x07,0x14,0x07,0x4c,0x14,0x07,0x74,0x0d,0x00,0x00,0xa9,0x46,0x8d
+,0xc6,0x02,0xd0,0xfe,0xa0,0x00,0xa9,0x6b,0x91,0x58,0x20,0xd9,0x07,0xb0,0xee,0x20
+,0xc4,0x07,0xad,0x7a,0x08,0x0d,0x76,0x08,0xd0,0xe3,0xa5,0x80,0x8d,0xe0,0x02,0xa5
+,0x81,0x8d,0xe1,0x02,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20,0xeb,0x07,0xb0
+,0xcc,0xa0,0x00,0x91,0x80,0xa5,0x80,0xc5,0x82,0xd0,0x06,0xa5,0x81,0xc5,0x83,0xf0
+,0x08,0xe6,0x80,0xd0,0x02,0xe6,0x81,0xd0,0xe3,0xad,0x76,0x08,0xd0,0xaf,0xad,0xe2
+,0x02,0x8d,0x70,0x07,0x0d,0xe3,0x02,0xf0,0x0e,0xad,0xe3,0x02,0x8d,0x71,0x07,0x20
+,0xff,0xff,0xad,0x7a,0x08,0xd0,0x13,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20
+};
+
+
+unsigned char buffer[] = {
+0x98,0xff,0xe0,0x00
+};
+
+typedef unsigned short u16;
+typedef unsigned char u08;
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+        u16 i;
+        u08 sumo,sum;
+        sum=sumo=0;
+        for(i=0;i<len;i++)
+        {
+                sum+=buffer[i];
+                if(sum<sumo) sum++;
+                sumo = sum;
+        }
+        return sum;
+}
+
+int main(void)
+{
+	int res = get_checksum(buffer,sizeof(buffer));
+	printf("%x %d\n",res,sizeof(buffer));
+	return 0;
+}
+
Index: unmerged/zpu_firmware/mist/diskio.h
===================================================================
--- unmerged/zpu_firmware/mist/diskio.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/zpu_firmware/mist/led.c
===================================================================
--- unmerged/zpu_firmware/mist/led.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/zpu_firmware/mist/fat.h
===================================================================
--- unmerged/zpu_firmware/mist/fat.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/fat.h	(revision 1)
@@ -0,0 +1,435 @@
+/*! \file fat.h \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.h'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup general
+/// \defgroup fat FAT16/32 File System Interface (fat.c)
+/// \code #include "fat.h" \endcode
+/// \par Overview
+///		This FAT16/32 interface allows you to detect and mount FAT16/32
+///		partitions, browse directories and files, and read file data.
+///		The interface is designed to operate with the avrlib IDE/ATA driver.
+///		Reading FAT efficiently requires at least 512+ bytes of RAM so this
+///		interface may not be suitable for processors with less than 1K of RAM.
+///		This interface will properly follow a file's cluster chain so files
+///		need not be defragmented.
+///
+/// \note This code is based in part on work done by Jesper Hansen for his
+///		excellent YAMPP MP3 player project.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef FAT_H
+#define FAT_H
+
+#define FALSE 0
+#define TRUE -1
+
+#define DRIVE0 1
+
+// Some useful cluster numbers
+#define MSDOSFSROOT     0		// cluster 0 means the root dir
+#define CLUST_FREE      0               // cluster 0 also means a free cluster
+#define MSDOSFSFREE     CLUST_FREE
+#define CLUST_FIRST     2               // first legal cluster number
+#define CLUST_RSRVD     0xfffffff6      // reserved cluster range
+#define CLUST_BAD       0xfffffff7      // a cluster with a defect
+#define CLUST_EOFS      0xfffffff8      // start of eof cluster range
+#define CLUST_EOFE      0xffffffff      // end of eof cluster range
+
+#define FAT12_MASK      0x00000fff      // mask for 12 bit cluster numbers
+#define FAT16_MASK      0x0000ffff      // mask for 16 bit cluster numbers
+#define FAT32_MASK      0x0fffffff      // mask for FAT32 cluster numbers
+
+
+// Partition Type used in the partition record
+#define PART_TYPE_UNKNOWN		0x00
+#define PART_TYPE_FAT12			0x01
+#define PART_TYPE_XENIX			0x02
+#define PART_TYPE_DOSFAT16		0x04
+#define PART_TYPE_EXTDOS		0x05
+#define PART_TYPE_FAT16			0x06
+#define PART_TYPE_NTFS			0x07
+#define PART_TYPE_FAT32			0x0B
+#define PART_TYPE_FAT32LBA		0x0C
+#define PART_TYPE_FAT16LBA		0x0E
+#define PART_TYPE_EXTDOSLBA		0x0F
+#define PART_TYPE_ONTRACK		0x33
+#define PART_TYPE_NOVELL		0x40
+#define PART_TYPE_PCIX			0x4B
+#define PART_TYPE_PHOENIXSAVE	0xA0
+#define PART_TYPE_CPM			0xDB
+#define PART_TYPE_DBFS			0xE0
+#define PART_TYPE_BBT			0xFF
+
+struct partrecord // length 16 bytes
+{			
+	unsigned char	prIsActive;					// 0x80 indicates active partition
+	unsigned char	prStartHead;				// starting head for partition
+	unsigned short	prStartCylSect;				// starting cylinder and sector
+	unsigned char	prPartType;					// partition type (see above)
+	unsigned char	prEndHead;					// ending head for this partition
+	unsigned short	prEndCylSect;				// ending cylinder and sector
+	unsigned long	prStartLBA;					// first LBA sector for this partition
+	unsigned long	prSize;						// size of this partition (bytes or sectors ?)
+};
+
+        
+struct partsector
+{
+	unsigned char	psPartCode[512-64-2];		// pad so struct is 512b
+	unsigned char	psPart[64];					// four partition records (64 bytes)
+	unsigned char	psBootSectSig0;				// two signature bytes (2 bytes)
+	unsigned char	psBootSectSig1;
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+
+// Format of a boot sector.  This is the first sector on a DOS floppy disk
+// or the first sector of a partition on a hard disk.  But, it is not the
+// first sector of a partitioned hard disk.
+struct bootsector33 {
+	unsigned char 	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[19];					// BIOS parameter block
+	unsigned char	bsDriveNumber;				// drive number (0x80)
+	unsigned char	bsBootCode[479];			// pad so struct is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct extboot {
+	unsigned char	exDriveNumber;				// drive number (0x80)
+	unsigned char	exReserved1;				// reserved
+	unsigned char	exBootSignature;			// ext. boot signature (0x29)
+#define EXBOOTSIG       0x29
+	unsigned char	exVolumeID[4];				// volume ID number
+	unsigned char	exVolumeLabel[11];			// volume label
+	unsigned char	exFileSysType[8];			// fs type (FAT12 or FAT16)
+};
+
+struct bootsector50 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[25];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[448];			// pad so structure is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55 
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct bootsector710 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOEMName[8];				// OEM name and version
+	unsigned char	bsBPB[53];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[418];			// pad so structure is 512b
+	unsigned char	bsBootSectSig2;				// 2 & 3 are only defined for FAT32?
+	unsigned char	bsBootSectSig3;
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+#define BOOTSIG2        0
+#define BOOTSIG3        0
+};
+
+
+/***************************************************************/
+/***************************************************************/
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct bpb33 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char    bpbSecPerClust;	// sectors per cluster
+        unsigned short	bpbResSectors;	// number of reserved sectors
+        unsigned char	bpbFATs;		// number of FATs
+        unsigned short	bpbRootDirEnts;	// number of root directory entries
+        unsigned short	bpbSectors;		// total number of sectors
+        unsigned char	bpbMedia;		// media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned short	bpbHiddenSecs;  // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not present in the DOS 3.3 bpb.
+struct bpb50 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char	bpbSecPerClust; // sectors per cluster
+        unsigned short	bpbResSectors;  // number of reserved sectors
+        unsigned char	bpbFATs;        // number of FATs
+        unsigned short	bpbRootDirEnts; // number of root directory entries
+        unsigned short	bpbSectors;     // total number of sectors
+        unsigned char	bpbMedia;       // media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned long	bpbHiddenSecs;  // # of hidden sectors
+// 3.3 compat ends here
+        unsigned long	bpbHugeSectors; // # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32)
+// This one has a few extensions to bpb50.
+struct bpb710 {
+		unsigned short	bpbBytesPerSec;	// bytes per sector
+		unsigned char	bpbSecPerClust;	// sectors per cluster
+		unsigned short	bpbResSectors;	// number of reserved sectors
+		unsigned char	bpbFATs;		// number of FATs
+		unsigned short	bpbRootDirEnts;	// number of root directory entries
+		unsigned short	bpbSectors;		// total number of sectors
+		unsigned char	bpbMedia;		// media descriptor
+		unsigned short	bpbFATsecs;		// number of sectors per FAT
+		unsigned short	bpbSecPerTrack;	// sectors per track
+		unsigned short	bpbHeads;		// number of heads
+		unsigned long	bpbHiddenSecs;	// # of hidden sectors
+// 3.3 compat ends here
+		unsigned long	bpbHugeSectors;	// # of sectors if bpbSectors == 0
+// 5.0 compat ends here
+		unsigned long     bpbBigFATsecs;// like bpbFATsecs for FAT32
+		unsigned short      bpbExtFlags;	// extended flags:
+#define FATNUM    0xf			// mask for numbering active FAT
+#define FATMIRROR 0x80			// FAT is mirrored (like it always was)
+		unsigned short      bpbFSVers;	// filesystem version
+#define FSVERS    0				// currently only 0 is understood
+		unsigned long     bpbRootClust;	// start cluster for root directory
+		unsigned short      bpbFSInfo;	// filesystem info structure sector
+		unsigned short      bpbBackup;	// backup boot sector
+		// There is a 12 byte filler here, but we ignore it
+};
+
+
+// ***************************************************************
+// * byte versions of the above structs                          *
+// ***************************************************************
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct byte_bpb33 {
+        unsigned char bpbBytesPerSec[2];		// bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[2];      // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not in the 3.3 bpb.
+struct byte_bpb50 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // number of hidden sectors
+        unsigned char bpbHugeSectors[4];		// # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32).
+// This one has a few extensions to bpb50.
+struct byte_bpb710 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // # of hidden sectors
+        unsigned char bpbHugeSectors[4];     // # of sectors if bpbSectors == 0
+        unsigned char bpbBigFATsecs[4];      // like bpbFATsecs for FAT32
+        unsigned char bpbExtFlags[2];        // extended flags:
+        unsigned char bpbFSVers[2];          // filesystem version
+        unsigned char bpbRootClust[4];       // start cluster for root directory
+        unsigned char bpbFSInfo[2];          // filesystem info structure sector
+        unsigned char bpbBackup[2];          // backup boot sector
+        // There is a 12 byte filler here, but we ignore it
+};
+
+// FAT32 FSInfo block.
+struct fsinfo {
+        unsigned char fsisig1[4];
+        unsigned char fsifill1[480];
+        unsigned char fsisig2[4];
+        unsigned char fsinfree[4];
+        unsigned char fsinxtfree[4];
+        unsigned char fsifill2[12];
+        unsigned char fsisig3[4];
+        unsigned char fsifill3[508];
+        unsigned char fsisig4[4];
+};
+
+
+// Structure of a dos directory entry.
+struct direntry {
+		unsigned char		deName[8];      // filename, blank filled
+#define SLOT_EMPTY      0x00            // slot has never been used
+#define SLOT_E5         0x05            // the real value is 0xE5
+#define SLOT_DELETED    0xE5            // file in this slot deleted
+		unsigned char		deExtension[3]; // extension, blank filled
+		unsigned char		deAttributes;   // file attributes
+#define ATTR_NORMAL     0x00            // normal file
+#define ATTR_READONLY   0x01            // file is readonly
+#define ATTR_HIDDEN     0x02            // file is hidden
+#define ATTR_SYSTEM     0x04            // file is a system file
+#define ATTR_VOLUME     0x08            // entry is a volume label
+#define ATTR_LONG_FILENAME	0x0F		// this is a long filename entry			    
+#define ATTR_DIRECTORY  0x10            // entry is a directory name
+#define ATTR_ARCHIVE    0x20            // file is new or modified
+		unsigned char        deLowerCase;    // NT VFAT lower case flags  (set to zero)
+#define LCASE_BASE      0x08            // filename base in lower case
+#define LCASE_EXT       0x10            // filename extension in lower case
+		unsigned char        deCHundredth;   // hundredth of seconds in CTime
+		unsigned char        deCTime[2];     // create time
+		unsigned char        deCDate[2];     // create date
+		unsigned char        deADate[2];     // access date
+		unsigned short        deHighClust; 	// high bytes of cluster number
+		unsigned char        deMTime[2];     // last update time
+		unsigned char        deMDate[2];     // last update date
+		unsigned short        deStartCluster; // starting cluster of file
+		unsigned long       deFileSize;  	// size of file in bytes
+};
+
+// number of directory entries in one sector
+#define DIRENTRIES_PER_SECTOR	0x10
+
+// Structure of a Win95 long name directory entry
+struct winentry {
+		unsigned char		weCnt;			// 
+#define WIN_LAST        0x40
+#define WIN_CNT         0x3f
+		unsigned char		wePart1[10];
+		unsigned char		weAttributes;
+#define ATTR_WIN95      0x0f
+		unsigned char		weReserved1;
+		unsigned char		weChksum;
+		unsigned char		wePart2[12];
+		unsigned short       	weReserved2;
+		unsigned char		wePart3[4];
+};
+
+#define WIN_ENTRY_CHARS	13      // Number of chars per winentry
+
+// Maximum filename length in Win95
+// Note: Must be < sizeof(dirent.d_name)
+#define WIN_MAXLEN      255
+
+// This is the format of the contents of the deTime field in the direntry
+// structure.
+// We don't use bitfields because we don't know how compilers for
+// arbitrary machines will lay them out.
+#define DT_2SECONDS_MASK        0x1F    // seconds divided by 2
+#define DT_2SECONDS_SHIFT       0
+#define DT_MINUTES_MASK         0x7E0   // minutes
+#define DT_MINUTES_SHIFT        5
+#define DT_HOURS_MASK           0xF800  // hours
+#define DT_HOURS_SHIFT          11
+
+// This is the format of the contents of the deDate field in the direntry
+// structure.
+#define DD_DAY_MASK				0x1F	// day of month
+#define DD_DAY_SHIFT			0
+#define DD_MONTH_MASK			0x1E0	// month
+#define DD_MONTH_SHIFT			5
+#define DD_YEAR_MASK			0xFE00	// year - 1980
+#define DD_YEAR_SHIFT			9
+
+
+#define FLAGS_ATRMEDIUMSIZE		0x80
+#define FLAGS_XEXLOADER			0x40
+#define FLAGS_ATRDOUBLESECTORS	0x20
+#define FLAGS_XFDTYPE			0x10
+#define FLAGS_READONLY			0x08
+#define FLAGS_WRITEERROR		0x04
+#define FLAGS_DRIVEON			0x01
+
+// Stuctures
+typedef struct						//2+2+2+2+2+4+1=15
+{
+	unsigned short start_cluster;		//< file starting cluster
+	unsigned short dir_cluster;
+	unsigned short current_cluster;
+	unsigned short ncluster;
+	unsigned short file_index;			//< file index
+	unsigned long size;					//< file size
+	unsigned char flags;				//< file flags
+}virtual_disk_t;
+
+struct FileInfoStruct
+{
+	unsigned char Attr;				//< file attr for last file accessed
+	unsigned short Date;			//< last update date
+	unsigned short Time;			//< last update time
+	unsigned char percomstate;		//=0 default, 1=percomwrite ok (single sectors), 2=percomwrite ok (double sectors), 3=percomwrite bad
+	//
+	virtual_disk_t vDisk;
+};
+
+struct GlobalSystemValues			//4+4+2+2+1=13 bytes
+{
+	unsigned long FirstFATSector;
+	unsigned long FirstDataSector;
+	unsigned short RootDirSectors;
+	unsigned short BytesPerSector;
+	unsigned char SectorsPerCluster;
+};
+
+#define FirstFATSector		GS.FirstFATSector
+#define FirstDataSector		GS.FirstDataSector
+#define RootDirSectors		GS.RootDirSectors
+#define BytesPerSector		GS.BytesPerSector
+#define SectorsPerCluster	GS.SectorsPerCluster
+
+
+unsigned char fatInit();
+unsigned long fatClustToSect(unsigned short clust);
+unsigned char fatChangeDirectory(unsigned short entry);
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names);
+unsigned short nextCluster(unsigned short cluster);
+
+#endif
Index: unmerged/zpu_firmware/mist/mycrt0.s
===================================================================
--- unmerged/zpu_firmware/mist/mycrt0.s	(nonexistent)
+++ unmerged/zpu_firmware/mist/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/zpu_firmware/mist/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/zpu_firmware/mist/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/zpu_firmware/mist/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,3853 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ad040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b80ef;
+00a2 : 98738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
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+0dd1 : 54087170;
+0dd2 : 8405530c;
+0dd3 : 72708405;
+0dd4 : 54087170;
+0dd5 : 8405530c;
+0dd6 : 72708405;
+0dd7 : 54087170;
+0dd8 : 8405530c;
+0dd9 : 72708405;
+0dda : 54087170;
+0ddb : 8405530c;
+0ddc : f0125271;
+0ddd : 8f26c938;
+0dde : 83722795;
+0ddf : 38727084;
+0de0 : 05540871;
+0de1 : 70840553;
+0de2 : 0cfc1252;
+0de3 : 718326ed;
+0de4 : 387054ff;
+0de5 : 81390000;
+0de6 : 00ffffff;
+0de7 : ff00ffff;
+0de8 : ffff00ff;
+0de9 : ffffff00;
+0dea : 70707042;
+0deb : 409c0202;
+0dec : 02020202;
+0ded : 02020202;
+0dee : 02020202;
+0def : 02020202;
+0df0 : 02020202;
+0df1 : 02704100;
+0df2 : 9c000000;
+0df3 : 0000175d;
+0df4 : 00001754;
+0df5 : 0000174b;
+0df6 : 00001742;
+0df7 : 00001739;
+0df8 : 00001730;
+0df9 : 00001727;
+0dfa : 000011b0;
+0dfb : 2f000000;
+0dfc : 4f70656e;
+0dfd : 696e673a;
+0dfe : 00000000;
+0dff : 6661696c;
+0e00 : 0a000000;
+0e01 : 6f6b0a00;
+0e02 : 436f756c;
+0e03 : 64206e6f;
+0e04 : 74207265;
+0e05 : 61642068;
+0e06 : 65616465;
+0e07 : 720a0000;
+0e08 : 556e6b6e;
+0e09 : 6f776e20;
+0e0a : 66696c65;
+0e0b : 20747970;
+0e0c : 65000000;
+0e0d : 41545220;
+0e0e : 00000000;
+0e0f : 58442000;
+0e10 : 300a0000;
+0e11 : 58464420;
+0e12 : 00000000;
+0e13 : 42414420;
+0e14 : 73656374;
+0e15 : 6f722073;
+0e16 : 697a6500;
+0e17 : 4d442000;
+0e18 : 58455820;
+0e19 : 00000000;
+0e1a : 53442000;
+0e1b : 44442000;
+0e1c : 44495220;
+0e1d : 00000000;
+0e1e : 6f70656e;
+0e1f : 64697220;
+0e20 : 6661696c;
+0e21 : 65640a00;
+0e22 : 426f6f74;
+0e23 : 696e672e;
+0e24 : 2e2e0000;
+0e25 : 53797374;
+0e26 : 656d2073;
+0e27 : 65747469;
+0e28 : 6e67730a;
+0e29 : 00000000;
+0e2a : 2d2d2d2d;
+0e2b : 2d2d2d2d;
+0e2c : 2d2d2d2d;
+0e2d : 2d2d2d0a;
+0e2e : 00000000;
+0e2f : 4d656d6f;
+0e30 : 72793a00;
+0e31 : 344d4221;
+0e32 : 00000000;
+0e33 : 524f4d20;
+0e34 : 62616e6b;
+0e35 : 3a000000;
+0e36 : 556e6b6e;
+0e37 : 6f776e00;
+0e38 : 53706565;
+0e39 : 643a0000;
+0e3a : 204b487a;
+0e3b : 0a44313a;
+0e3c : 00000000;
+0e3d : 0a44323a;
+0e3e : 00000000;
+0e3f : 0a44333a;
+0e40 : 00000000;
+0e41 : 0a44343a;
+0e42 : 00000000;
+0e43 : 0a526562;
+0e44 : 6f6f7400;
+0e45 : 0a457869;
+0e46 : 74000000;
+0e47 : 34202864;
+0e48 : 65666175;
+0e49 : 6c743a4f;
+0e4a : 53204220;
+0e4b : 2b206869;
+0e4c : 20737065;
+0e4d : 65642900;
+0e4e : 32202864;
+0e4f : 65666175;
+0e50 : 6c743a58;
+0e51 : 4c202b20;
+0e52 : 68692073;
+0e53 : 70656564;
+0e54 : 29000000;
+0e55 : 31202864;
+0e56 : 65666175;
+0e57 : 6c743a58;
+0e58 : 4c290000;
+0e59 : 33202864;
+0e5a : 65666175;
+0e5b : 6c743a55;
+0e5c : 6c74696d;
+0e5d : 6f6e2900;
+0e5e : 31303838;
+0e5f : 4b694220;
+0e60 : 52616d62;
+0e61 : 6f000000;
+0e62 : 3537364b;
+0e63 : 69422052;
+0e64 : 616d626f;
+0e65 : 00000000;
+0e66 : 3537364b;
+0e67 : 69422043;
+0e68 : 6f6d7079;
+0e69 : 2053686f;
+0e6a : 70000000;
+0e6b : 3332304b;
+0e6c : 69422052;
+0e6d : 616d626f;
+0e6e : 00000000;
+0e6f : 3332304b;
+0e70 : 69422043;
+0e71 : 6f6d7079;
+0e72 : 2053686f;
+0e73 : 70000000;
+0e74 : 3132384b;
+0e75 : 69420000;
+0e76 : 36344b69;
+0e77 : 42000000;
+0e78 : 636d643a;
+0e79 : 00000000;
+0e7a : 45525220;
+0e7b : 00000000;
+0e7c : 53504453;
+0e7d : 00000000;
+0e7e : 53504446;
+0e7f : 00000000;
+0e80 : 2873656e;
+0e81 : 643a0000;
+0e82 : 3a63686b;
+0e83 : 3a000000;
+0e84 : 73646361;
+0e85 : 72640a00;
+0e86 : 6469736b;
+0e87 : 5f696e69;
+0e88 : 743a0000;
+0e89 : 6d6f756e;
+0e8a : 743a0000;
+0e8b : 6f70656e;
+0e8c : 6469723a;
+0e8d : 00000000;
+0e8e : 424f4f54;
+0e8f : 2e415452;
+0e90 : 00000000;
+0e91 : 61746172;
+0e92 : 69726f6d;
+0e93 : 2e62696e;
+0e94 : 00000000;
+0e95 : 53746174;
+0e96 : 3a000000;
+0e97 : 3a646f6e;
+0e98 : 650a0000;
+0e99 : 53656374;
+0e9a : 6f723a00;
+0e9b : 20726563;
+0e9c : 65697665;
+0e9d : 3a000000;
+0e9e : 2073656e;
+0e9f : 64696e67;
+0ea0 : 0a000000;
+0ea1 : 64617461;
+0ea2 : 20000000;
+0ea3 : 626f6f74;
+0ea4 : 20000000;
+0ea5 : 6e616d65;
+0ea6 : 20000000;
+0ea7 : 6e756d74;
+0ea8 : 6f627566;
+0ea9 : 66657220;
+0eaa : 00000000;
+0eab : 00000000;
+0eac : 00000000;
+0ead : 72025f07;
+0eae : f807a900;
+0eaf : 8d04038d;
+0eb0 : 4402a907;
+0eb1 : 8d0503a9;
+0eb2 : 708d0a03;
+0eb3 : a9018d0b;
+0eb4 : 03850960;
+0eb5 : 7d8a4820;
+0eb6 : 53e488d0;
+0eb7 : fa68aa8c;
+0eb8 : 8e07ad7d;
+0eb9 : 07ee8e07;
+0eba : 60a9938d;
+0ebb : e202a907;
+0ebc : 8de302a2;
+0ebd : 0220da07;
+0ebe : 954320da;
+0ebf : 07954435;
+0ec0 : 43c9fff0;
+0ec1 : f0caca10;
+0ec2 : ec3006e6;
+0ec3 : 45d002e6;
+0ec4 : 4620da07;
+0ec5 : a2018144;
+0ec6 : b545d543;
+0ec7 : d0edca10;
+0ec8 : f720d207;
+0ec9 : 4c9407a9;
+0eca : 038d0fd2;
+0ecb : 6ce202ad;
+0ecc : 8e07cd7f;
+0ecd : 07d0abee;
+0ece : 0a03d003;
+0ecf : ee0b03ad;
+0ed0 : 7d070d7e;
+0ed1 : 07d08e20;
+0ed2 : d2076ce0;
+0ed3 : 0220da07;
+0ed4 : 8de00220;
+0ed5 : da078de1;
+0ed6 : 022de002;
+0ed7 : c9fff0ed;
+0ed8 : a9008d8e;
+0ed9 : 07f08200;
+0eda : 0001d20f;
+0edb : 0001d400;
+0edc : 0001d401;
+0edd : 0001d409;
+0ede : 0001d010;
+0edf : 0001d301;
+0ee0 : 0001d300;
+0ee1 : 0001d20a;
+0ee2 : 0001d01b;
+0ee3 : 0001d018;
+0ee4 : 0001d017;
+0ee5 : 0001d01a;
+0ee6 : 0001d403;
+0ee7 : 0001d402;
+0ee8 : 0001d40e;
+0ee9 : 0004007c;
+0eea : 00040078;
+0eeb : 00040074;
+0eec : 00040068;
+0eed : 00040060;
+0eee : 0004005c;
+0eef : 00040058;
+0ef0 : 00040054;
+0ef1 : 00040050;
+0ef2 : 0004004c;
+0ef3 : 00040048;
+0ef4 : 00040044;
+0ef5 : 00040040;
+0ef6 : 0004002c;
+0ef7 : 00040028;
+0ef8 : 00040024;
+0ef9 : 00040020;
+0efa : 0004001c;
+0efb : 00040018;
+0efc : 00040014;
+0efd : 00040010;
+0efe : 0004000c;
+0eff : 00040008;
+0f00 : 00040004;
+0f01 : 00040000;
+END; 
Index: unmerged/zpu_firmware/mist/regs.c
===================================================================
--- unmerged/zpu_firmware/mist/regs.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/regs.c	(revision 1)
@@ -0,0 +1,50 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x40000
+int volatile * zpu_config = (int *)(0*4+regbase);
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+int volatile * zpu_sector = (int *)(11*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_chactl = (unsigned char *)(0xd401 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+unsigned char volatile * atari_skctl = (unsigned char *)(0xd20f + 0x10000);
+
+#endif // regs_h
Index: unmerged/zpu_firmware/mist/setup
===================================================================
--- unmerged/zpu_firmware/mist/setup	(nonexistent)
+++ unmerged/zpu_firmware/mist/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/zpu_firmware/mist/bootdump.c
===================================================================
--- unmerged/zpu_firmware/mist/bootdump.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/zpu_firmware/mist/main.c
===================================================================
--- unmerged/zpu_firmware/mist/main.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/main.c	(revision 1)
@@ -0,0 +1,1716 @@
+#include "types.h"
+#include "regs.h"
+#include "pause.h"
+#include "debug.h"
+#include "pff.h"
+#include "diskio.h"
+
+#define send_ACK()	USART_Transmit_Byte('A');
+#define send_NACK()	USART_Transmit_Byte('N');
+#define send_CMPL()	USART_Transmit_Byte('C');
+#define send_ERR()	USART_Transmit_Byte('E');
+
+/* BiboDos needs at least 50us delay before ACK */
+#define DELAY_T2_MIN wait_us(100);
+
+/* the QMEG OS needs at least 300usec delay between ACK and complete */
+#define DELAY_T5_MIN wait_us(300);
+
+/* QMEG OS 3 needs a delay of 150usec between complete and data */
+#define DELAY_T3_PERIPH wait_us(150);
+
+int opendrive;
+char filename_d1[15];
+char filename_d2[15];
+char filename_d3[15];
+char filename_d4[15];
+
+FATFS fatfs;
+DIR dir;
+FILINFO filinfo;
+struct ATRHeader atr_header;
+int selfileno;
+int debugmode;
+int validfile;
+int speed;
+#define speedslow 0x28
+#define speedfast 0x6
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+	*zpu_pause = cycles;
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+unsigned char * mmc_sector_buffer;
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+}
+
+int
+filesize(char const * filename)
+{
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		return 0;
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+
+int
+selectfile(char * filename)
+{
+	int fileno;
+	int skip;
+	int plotted = 0;
+	wait_us(200000);
+	for(;;)
+	{
+		int i = 0;
+		int go = 0;
+		fileno = 0;
+		topofscreen();
+		for (i=0; i!=(24*40); ++i)
+		{
+			*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+		}
+		if (FR_OK != pf_opendir(&dir,"/"))
+		{
+			debug("opendir failed\n");
+			mmcReadCached(0);
+			hexdump_pure(mmc_sector_buffer,512);
+			
+			while(1);
+		}
+
+		plotted = 0;
+		skip = 0;
+		if (selfileno>20)
+		{
+			skip = selfileno-20;
+			skip&=0xfffffffe;
+		}
+		if (selfileno<0)
+		{
+			selfileno = 0;
+		}
+		while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+		{
+			if (filinfo.fattrib & AM_SYS)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_HID)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_DIR)
+			{
+				debug("DIR ");
+			}
+			if (selfileno == fileno)
+			{
+				for (i=0;i!=15;++i)
+				{
+					filename[i] = filinfo.fname[i];
+					if (0==filinfo.fname[i]) break;
+					filinfo.fname[i]+=128;
+				}
+			}
+			if (--skip<0)
+			{
+				debug(filinfo.fname);
+				++plotted;
+				if (plotted&1)
+				{
+					setxpos(20);
+				}
+				else
+				{
+					debug("\n");
+				}
+				if (plotted==40)
+				{
+					break;
+				}
+			}
+			fileno++;
+		}
+		debug("\n");
+		setypos(21);
+		opendrive = 0;
+		openfile(filename);
+		for (;;)
+		{
+			unsigned char porta = *atari_porta;
+			if (0==(porta&0x2)) // down
+			{
+				selfileno+=2;
+				break;
+			}
+			else if (0==(porta&0x1)) // up
+			{
+				selfileno-=2;
+				break;
+			}
+			else if (0==(porta&0x8)) // right
+			{
+				selfileno|=1;
+				break;
+			}
+			else if (0==(porta&0x4)) // left
+			{
+				selfileno&=0xfffffffe;
+				break;
+			}
+			else if (0==(*atari_trig0)) // fire
+			{
+				go = 1;
+				while(0==(*atari_trig0));
+				break;
+			}
+			topofscreen();
+			//plotnextnumber(porta);
+			*atari_colbk = *atari_random;
+			//wait_us(200);
+		}
+		if (go == 1)
+		{
+			wait_us(200000);
+			return validfile; // TODO, another way to quit without selecting...
+		}
+		wait_us(80000);
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+	*zpu_ledg = 0x0;
+	wait_us(600);
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xffffffff;
+	wait_us(600);
+	return;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	int prev = *zpu_config;
+	if (reset_n == 1)
+		*zpu_config = prev&~(1<<7);
+	else
+		*zpu_config = prev|(1<<7);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	int prev = *zpu_config;
+	if (pause == 0)
+		*zpu_config = prev&~(1<<6);
+	else
+		*zpu_config = prev|(1<<6);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void actions()
+{
+	unsigned int i = 0;
+	//unsigned volatile char * store = 0xf00000; // SDRAM - fails!!
+	unsigned volatile char * store  = 0xf80000; // SRAM...
+	unsigned volatile char * store2 = 0xfc0000; // custom chips...
+
+	if ((1&*zpu_key) == 1)
+	{
+		unsigned char volatile * mem;
+		unsigned char volatile * mem2;
+		unsigned char volatile * mem3;
+		unsigned char store_portb;
+		int reboot = 0;
+		int temp;
+		int row = 0;
+		int next = 0;
+		int go = 0;
+
+		// stop 6502
+		pause_6502(1);
+
+		// TODO - 
+		// menu for 64k/128k/320K Compy/320K Rambo
+		// menu for ROM bank
+		// menu for GPIO on/off
+
+		initdebug(1);
+
+		mem = 0x9c00 + 0x10000;
+		// Copy 1k from 0x$9c00 to sdram
+		// 0x200000; sram
+		// 0x800000; sdram (always use...)
+		for (i=0x0; i!=1024; i++)
+		{
+			store[i] = mem[i];
+		}
+		for (i=0x40; i!=1024; i++)
+		{
+			mem[i] = 0;
+		}
+
+		{
+			//gtia
+			mem2 = 0x20000;
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+		}
+
+		store_portb = *atari_portb;
+
+		// write a display list at 9c00
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x9c
+		};
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x9c;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+		*atari_portb = 0xff;
+		*atari_skctl = 0x3;
+		*atari_chactl = 0x2;
+
+		for (;;)
+		{
+			wait_us(120000);
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			// 0-5 speed
+			// 6-pause
+			// 7-reset
+			// 8-9-ram
+			// 12-13-rom
+			// 16-gpio_enable
+			debug("System settings\n");
+			debug("---------------\n");
+			debug("Memory:");
+			temp = 0xf&((*zpu_config)>>8);
+			if (row == 0)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xfffff0ff)|((temp)<<8);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("64KiB");
+				break;
+			case 1:
+				debug("128KiB");
+				break;
+			case 2:
+				debug("320KiB Compy Shop");
+				break;
+			case 3:
+				debug("320KiB Rambo");
+				break;
+			case 4:
+				debug("576KiB Compy Shop");
+				break;
+			case 5:
+				debug("576KiB Rambo");
+				break;
+			case 6:
+				debug("1088KiB Rambo");
+				break;
+			case 7:
+				debug("4MB!");
+				break;
+			}
+			debug("\n");
+			debug("ROM bank:");
+			temp = 0xf&((*zpu_config)>>12);
+			if (row == 1)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xffff0fff)|((temp&0xf)<<12);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 1:
+				debug("1 (default:XL)");
+				break;
+			case 2:
+				debug("2 (default:XL + hi speed)");
+				break;
+			case 3:
+				debug("3 (default:Ultimon)");
+				break;
+			case 4:
+				debug("4 (default:OS B + hi speed)");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("Speed:");
+			temp = 0x3f&((*zpu_config)>>0);
+			if (row == 2)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					if (temp < 0) temp =0;
+					*zpu_config = (*zpu_config&0xffffffc0)|(temp&0x3f);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			plotnextnumber(57500/(temp+1));
+			debug(" KHz\nD1:"); // Bring up selector, instead of booting changes disk image
+			if (row == 3)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d1);
+			debug("\nD2:");
+			if (row == 4)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d2);
+			debug("\nD3:");
+			if (row == 5)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d3);
+			debug("\nD4:");
+			if (row == 6)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d4);
+			if (row>=3 && row<7)
+			{
+				if (go==1)
+				{
+					switch (row)
+					{
+					case 3:
+						selectfile(filename_d1);
+						break;
+					case 4:
+						selectfile(filename_d2);
+						break;
+					case 5:
+						selectfile(filename_d3);
+						break;
+					case 6:
+						selectfile(filename_d4);
+						break;
+					}
+					opendrive = row-2;
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d4[i];
+						filename_d4[i] = filename_d3[i];
+						filename_d3[i] = filename_d2[i];
+						filename_d2[i] = filename_d1[i];
+						filename_d1[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==-1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d1[i];
+						filename_d1[i] = filename_d2[i];
+						filename_d2[i] = filename_d3[i];
+						filename_d3[i] = filename_d4[i];
+						filename_d4[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+			}
+			if (row == 7)
+			{
+				debugoffset(128);
+			}
+			debug("\nReboot");
+			if (row == 7)
+			{
+				if (go==1)
+				{
+					reboot = 1;
+					break;
+				}
+			}
+			if (row == 8)
+			{
+				debugoffset(128);
+			}
+			debug("\nExit");
+			if (row == 8)
+			{
+				if (go==1)
+					break;
+			}
+
+			next = 0;
+			go = 0;
+
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					row+=1;
+					if (row>8) row = 8;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					row-=1;
+					if (row<0) row = 0;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					next = 1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					next = -1;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					while(0==(*atari_trig0));
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+		}
+
+		// wait 2 seconds
+		//for (i=0; i!=2000; ++i)
+		//{
+		//	*atari_colbk = *atari_random;
+		//	wait_us(1000);
+		//}
+
+		for (i=0x040; i!=1024; i++)
+		{
+			mem[i] = store[i];
+		}
+
+		{
+			//gtia
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+		}
+		*atari_portb = store_portb;
+		initdebug(debugmode);
+
+
+		if (reboot)
+		{
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		unsigned char volatile * mem;
+		unsigned char volatile * mem2;
+		unsigned char volatile * mem3;
+		unsigned char store_portb;
+		int reboot = 0;
+		int temp;
+		int row = 0;
+		int next = 0;
+		int go = 0;
+
+		// stop 6502
+		pause_6502(1);
+
+		// TODO - 
+		// menu for 64k/128k/320K Compy/320K Rambo
+		// menu for ROM bank
+		// menu for GPIO on/off
+
+		initdebug(1);
+
+		mem = 0x9c00 + 0x10000;
+		// Copy 1k from 0x$9c00 to sdram
+		// 0x200000; sram
+		// 0x800000; sdram (always use...)
+		for (i=0x0; i!=1024; i++)
+		{
+			store[i] = mem[i];
+		}
+		for (i=0x40; i!=1024; i++)
+		{
+			mem[i] = 0;
+		}
+
+		{
+			//gtia
+			mem2 = 0x20000;
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+		}
+
+		store_portb = *atari_portb;
+
+		// write a display list at 9c00
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x9c
+		};
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x9c;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+		*atari_portb = 0xff;
+		*atari_skctl = 0x3;
+		*atari_chactl = 0x2;
+
+		initdebug(1);
+
+		if (selectfile(filename_d1))
+		{
+			opendrive = 1;
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		initdebug(debugmode);
+		pause_6502(0);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	opendrive = 0;
+	pause_6502(1);
+
+
+/*		//wait_us(5000000);
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+	for(;;)
+	{
+		int j;
+		for (j=0; j!=1000; ++j)
+		{
+			mmcReadCached(j);
+		}
+	}
+*/
+
+	speed = speedslow;
+	//FIXME if (2==(2&(*zpu_switches)))
+	if (0)
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+
+		wait_us(2000000);
+	}
+
+	//FIXME if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	pause_6502(1);
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+	//do
+	//{
+	//	mmcInit();
+	//}
+	//while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	//set_spi_clock_freq();
+
+	// no longer in ram (yet!), misuse will break us...
+	mmc_sector_buffer = (unsigned char *)0x4000;
+
+	stat = RES_OK;
+
+	return stat;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+	in[0] = in[1];
+	in[1] = temp;
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+	char const * default_filename = "BOOT.ATR";
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	for (i=0;i!=15;++i)
+	{
+		filename_d1[i] = default_filename[i];
+		filename_d2[i] = default_filename[i];
+		filename_d3[i] = default_filename[i];
+		filename_d4[i] = default_filename[i];
+		if (default_filename[i] == 0) break;
+	}
+
+	if (FR_OK!=pf_open("atarirom.bin"))
+	{
+		debug("fail\n");
+		*atari_skctl = 0;
+		*atari_skctl = 0x3;
+		for (i=0;i<1000;++i)
+		{
+			wait_us(5000);
+			*atari_colbk = *atari_random;
+		}
+	}
+	else
+	{
+		char volatile * addr = (char volatile *)0xf04000;
+		while (1)
+		{
+			int i=0;
+			read = 0;
+			pf_read(&mmc_sector_buffer[0],512,&read);
+
+			for (i=0;i!=read;++i)
+			{
+				*addr++ = mmc_sector_buffer[i];
+			}
+
+			if (read!=512) break;
+		}
+
+			// Old file format is:
+			// 0000 - ROM
+			// 4000 - ROM
+			// 8000 - ROM
+			// c000 - BASIC
+			//10000 - ROM
+
+		{
+			// Copy basic to the beginning
+			char * from = 0xf10000;
+			char * to   = 0xf00000;
+			int len = 16384;
+			while (len--)
+			{
+				*to++ = *from++;
+			}
+		}
+
+		{
+			// Copy 4th rom over where basic was
+			char * from = 0xf14000;
+			char * to   = 0xf10000;
+			int len = 16384;
+			while (len--)
+			{
+				*to++ = *from++;
+			}
+		}
+	}
+
+	opendrive = 1;
+	openfile(filename_d1);
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		/*FIXME if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}*/
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId >= 0x31 && command.deviceId < 0x34)
+ 	 	{
+			int sent = 0;
+			int drive = 0;
+
+			drive = command.deviceId&0xf;
+			if (drive!=opendrive)
+			{
+				opendrive = drive;
+				switch(drive)
+				{
+				case 1:
+					openfile(filename_d1);
+					break;
+				case 2:
+					openfile(filename_d2);
+					break;
+				case 3:
+					openfile(filename_d3);
+					break;
+				case 4:
+					openfile(filename_d4);
+					break;
+				}
+			}
+
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = 0; //get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	//u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	//retry=0; //zkusi to maximalne 256x
+	/*do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+*/
+
+	*zpu_sector = sector;
+	while ((1&*zpu_sector)==1)
+	{
+		// Wait until ready
+	}
+
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+	for(i=0;i<len;i++)
+	{
+		sum+=buffer[i];
+		if(sum<sumo) sum++;
+		sumo = sum;
+	}
+	return sum;
+}
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+	u08 check_sum;
+	debug("(send:");
+	plotnextnumber(len);
+
+	DELAY_T5_MIN;
+	send_CMPL();
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+	USART_Transmit_Byte(check_sum);
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+	plotnextnumber(check_sum);
+	debug(")");
+}
Index: unmerged/zpu_firmware/mist/crt0.S
===================================================================
--- unmerged/zpu_firmware/mist/crt0.S	(nonexistent)
+++ unmerged/zpu_firmware/mist/crt0.S	(revision 1)
@@ -0,0 +1,974 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	
+	
+	
+;	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+; DANGER!!!! 
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!! 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jsr address
+			im _memreg     	; save R0
+			load
+			im _memreg+4	; save R1
+			load
+			im _memreg+8	; save R2
+			load
+			fixedim \address
+			call
+			im _memreg+8
+			store		; restore R2
+			im _memreg+4
+			store		; restore R1
+			im _memreg
+			store		; restore R0
+	.endm
+
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+		
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		; intSp must be 0 when we jump to _premain
+		
+		im ZPU_ID
+		loadsp 0
+		im _cpu_config
+		store
+		config
+		jmp _premain
+
+
+
+        .balign 32,0
+# offset 0x0000 0020
+		.globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+		jmp ___zpu_interrupt_vector
+
+
+        .balign 16,0
+# offset 0x0000 0030
+		.globl _memreg
+		.weak _memreg
+_memreg:
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+        .globl ___zpu_interrupt_vector
+        .weak ___zpu_interrupt_vector
+
+___zpu_interrupt_vector:
+	jsr _zpu_interrupt
+	poppc
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+

Property changes on: unmerged/zpu_firmware/mist/crt0.S
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/fat.c
===================================================================
--- unmerged/zpu_firmware/mist/fat.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/fat.c	(revision 1)
@@ -0,0 +1,445 @@
+/*! \file fat.c \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.c'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// This code is based in part on work done by Jesper Hansen for his
+//		YAMPP MP3 player project.
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include <stdio.h>
+#include <string.h>
+
+#include "fat.h"
+#include "mmc.h"
+#include "spi.h"
+
+void USART_SendString(char *buff);
+void mmcReadCached(u32 sector);
+
+
+#define FileNameBuffer atari_sector_buffer
+extern unsigned char atari_sector_buffer[256];
+extern unsigned char mmc_sector_buffer[512];	// one sector
+extern struct GlobalSystemValues GS;
+extern struct FileInfoStruct FileInfo;			//< file information for last file accessed
+
+
+unsigned long fatClustToSect(unsigned short clust)
+{
+	u32 ret;
+	if(clust==MSDOSFSROOT)
+	{
+		debug("fatClustToSect:");
+		u32 res = (u32)((u32)(FirstDataSector) - (u32)(RootDirSectors));
+		plotnextnumber(res);
+		debug(" ");
+		plotnextnumber(FirstDataSector);
+		debug(" ");
+		plotnextnumber(RootDirSectors);
+		debug("\n");
+		return res;
+	}
+	
+	ret = (u32)(clust-2);
+	ret *= (u32)SectorsPerCluster;
+	ret += (u32)FirstDataSector;
+	return ((unsigned long)ret);
+}
+
+
+//POZOR - DEBUG !!!
+//prvne definovana promenna
+u32 debug_endofvariables;		//promenna co je v pameti jako posledni (za ni je uz jen stack)
+//POZOR - DEBUG !!!
+
+unsigned short last_dir_start_cluster;
+unsigned char last_dir_valid;
+unsigned short last_dir_entry;
+unsigned long last_dir_sector;
+unsigned char last_dir_sector_count;
+unsigned short last_dir_cluster;
+unsigned char last_dir_index;
+
+
+unsigned char fatInit()
+{
+	struct partrecord PartInfo;
+	struct bpb710 *bpb;
+
+	// Moved here since init vars are in ROM!
+	last_dir_entry=0x0;
+	last_dir_sector=0;
+	last_dir_sector_count=0;
+	last_dir_cluster=0;
+	last_dir_index=0;
+
+	// read partition table
+	// TODO.... error checking
+	debug("FAT INIT:");
+	mmcReadCached(0);
+	// map first partition record	
+	// save partition information to global PartInfo
+	PartInfo = *((struct partrecord *) ((struct partsector *) (char*)mmc_sector_buffer)->psPart);
+
+	if(mmc_sector_buffer[0x36]=='F' && mmc_sector_buffer[0x37]=='A' && mmc_sector_buffer[0x38]=='T' && mmc_sector_buffer[0x39]=='1' && mmc_sector_buffer[0x3a]=='6')
+	{
+		PartInfo.prPartType = PART_TYPE_FAT16LBA; //0x04
+		PartInfo.prStartLBA = 0x00;
+	}
+	
+	// Read the Partition BootSector
+	// **first sector of partition in PartInfo.prStartLBA
+	mmcReadCached(PartInfo.prStartLBA);
+	bpb = (struct bpb710 *) ((struct bootsector710 *) (char*)mmc_sector_buffer)->bsBPB;
+
+	// setup global disk constants
+	PartInfo.prStartLBA = 0x1e8; // FIXME
+	FirstDataSector	= PartInfo.prStartLBA;
+
+	RootDirSectors = bpb->bpbRootDirEnts>>4; // /16 ; 512/16 = 32  (sector size / max entries in one sector = number of sectors)
+
+	debug("PartInto ");
+	plotnextnumber(PartInfo.prStartLBA);
+	debug(" ");
+	plotnextnumber(bpb->bpbRootDirEnts>>4);
+	debug("\n");
+
+	// bpbFATsecs is non-zero and is therefore valid
+	FirstDataSector	+= bpb->bpbResSectors + bpb->bpbFATs * bpb->bpbFATsecs + RootDirSectors;
+
+	SectorsPerCluster	= bpb->bpbSecPerClust;
+	BytesPerSector		= bpb->bpbBytesPerSec;
+	FirstFATSector		= bpb->bpbResSectors + PartInfo.prStartLBA;
+
+	// set current directory to root (\)
+	FileInfo.vDisk.dir_cluster = MSDOSFSROOT; //RootDirStartCluster;
+
+    last_dir_start_cluster=0xffff;
+	//last_dir_valid=0;		//<-- neni potreba, protoze na zacatku fatGetDirEntry se pri zjisteni
+							//ze je (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+							//vynuluje last_dir_valid=0;
+
+	if (   PartInfo.prPartType==PART_TYPE_DOSFAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16LBA
+	   )
+	{
+		return 1; //je to ok
+		debug("OK\n");
+	}
+	else
+	{
+		return 0; //neni to zadny filesystem co umime
+		debug("FAIL\n");
+	}
+}
+
+//////////////////////////////////////////////////////////////
+
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names)
+{
+	unsigned long sector;
+	struct direntry *de = 0;	// avoid compiler warning by initializing
+	struct winentry *we;
+	unsigned char haveLongNameEntry;
+	unsigned char gotEntry;
+	unsigned short b;
+	u08 index;
+	unsigned short entrycount = 0;
+	unsigned short actual_cluster = FileInfo.vDisk.dir_cluster;
+	unsigned char seccount=0;
+
+	haveLongNameEntry = 0;
+	gotEntry = 0;
+
+	if (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+	{
+		//zmenil se adresar, takze musi pracovat s nim
+		//a zneplatnit last_dir polozky
+		last_dir_start_cluster=FileInfo.vDisk.dir_cluster;
+		last_dir_valid=0;
+
+		debug("LastDirStartCluster:");
+		plotnextnumber(last_dir_start_cluster);
+		plotnextnumber(last_dir_valid);
+		debug("\n");
+	}
+
+	if ( !last_dir_valid
+		 || (entry<=last_dir_entry && (entry!=last_dir_entry || last_dir_valid!=1 || use_long_names!=0))
+	   )
+	{
+		//musi zacit od zacatku
+		sector = fatClustToSect(FileInfo.vDisk.dir_cluster);
+		//index = 0;
+		debug("ReadFromBegin:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_begin;
+	}
+	else
+	{
+		//muze zacit od posledne pouzite
+		entrycount=last_dir_entry;
+		index = last_dir_index;
+		sector=last_dir_sector;
+		actual_cluster=last_dir_cluster;
+		seccount = last_dir_sector_count;
+		debug("ReadFromLastEntry:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_last_entry;
+	}
+
+	while(1)
+	{
+		debug("Index:");
+		plotnextnumber(index);
+		debug("\n");
+		if(index==16)	// time for next sector ?
+		{
+			if ( actual_cluster==MSDOSFSROOT )
+			{
+				//v MSDOSFSROOT se nerozlisuji clustery
+				//protoze MSDOSFSROOT ma sektory stale dal za sebou bez clusterovani
+				if (seccount>=RootDirSectors) return 0; //prekrocil maximalni pocet polozek v MSDOSFSROOT
+			}
+			else //MUSI BYT!!! (aby neporovnaval seccount je-li actual_cluster==MSDOSFSROOT)
+			if( seccount>=SectorsPerCluster )
+			{
+				//next cluster
+				//pri prechodu pres pocet sektoru v clusteru
+				actual_cluster = nextCluster(actual_cluster);
+				sector=fatClustToSect(actual_cluster);
+				seccount=0;
+			}
+fat_read_from_begin:
+			index = 0;
+			seccount++;		//ted bude nacitat dalsi sektor (musi ho zapocitat)
+fat_read_from_last_entry:
+			mmcReadCached( sector++ ); 	//prave ho nacetl
+			de = (struct direntry *) (char*)mmc_sector_buffer;
+			de+=index;
+		}
+		
+		// check the status of this directory entry slot
+		if(de->deName[0] == 0x00) //SLOT_EMPTY
+		{
+			// slot is empty and this is the end of directory
+			gotEntry = 0;
+			break;
+		}
+		else if(de->deName[0] == 0xE5)	//SLOT_DELETED
+		{
+			// this is an empty slot
+			// do nothing and move to the next one
+		}
+		else
+		{
+			// this is a valid and occupied entry
+			// is it a part of a long file/dir name?
+			if( de->deAttributes==ATTR_LONG_FILENAME )
+			{
+				// we have a long name entry
+				// cast this directory entry as a "windows" (LFN: LongFileName) entry
+				u08 i;
+				unsigned char *fnbPtr;
+
+				//pokud nechceme longname, NESMI je vubec kompletovat
+				//a preskoci na dalsi polozku
+				//( takze ani haveLongNameEntry nikdy nebude nastaveno na 1)
+				//Jinak by totiz preplacaval dalsi kusy atari_sector_bufferu 12-255 ! BACHA!!!
+				if (!use_long_names) goto fat_next_dir_entry;
+
+				we = (struct winentry *) de;
+				
+				b = WIN_ENTRY_CHARS*( (unsigned short)((we->weCnt-1) & 0x0f));		// index into string
+				fnbPtr = &FileNameBuffer[b];
+
+				for (i=0;i<5;i++)	*fnbPtr++ = we->wePart1[i*2];	// copy first part
+				for (i=0;i<6;i++)	*fnbPtr++ = we->wePart2[i*2];	// second part
+				for (i=0;i<2;i++)	*fnbPtr++ = we->wePart3[i*2];	// and third part
+
+				/*
+				{
+				//unsigned char * sptr;
+				//sptr=we->wePart1;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart1+10)); // copy first part
+				//^-- pouziti jen tohoto prvniho a druhe dva pres normalni for(..) uspori 10 bajtu,
+				//pri pouziti i dalsich dvou timto stylem uz se to ale zase prodlouzi - nechaaaaaapu!
+				//sptr=we->wePart2;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart2+12)); // second part
+				//sptr=we->wePart3;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart3+4));  // and third part
+				}
+				*/
+
+				if (we->weCnt & WIN_LAST) *fnbPtr = 0;				// in case dirnamelength is multiple of 13, add termination
+				if ((we->weCnt & 0x0f) == 1) haveLongNameEntry = 1;	// flag that we have a complete long name entry set
+			}
+			else
+			{
+				// we have a short name entry
+				
+				// check if this is the short name entry corresponding
+				// to the end of a multi-part long name entry
+				if(haveLongNameEntry)
+				{
+					// a long entry name has been collected
+					if(entrycount == entry)		
+					{
+						// desired entry has been found, break out
+						gotEntry = 2;
+						break;
+					}
+					// otherwise
+					haveLongNameEntry = 0;	// clear long name flag
+					entrycount++;			// increment entry counter		
+				}
+				else
+				{
+					// entry is a short name (8.3 format) without a
+					// corresponding multi-part long name entry
+
+					//Zcela vynecha adresar "." a disk label
+					if( (de->deName[0]=='.' && de->deName[1]==' ' && (de->deAttributes & ATTR_DIRECTORY) ) //je to "." adresar
+						|| (de->deAttributes & ATTR_VOLUME) ) goto fat_next_dir_entry;
+
+					if(entrycount == entry)
+					{
+						/*
+						fnbPtr = &FileNameBuffer[string_offset];
+						for (i=0;i<8;i++)	*fnbPtr++ = de->deName[i];		// copy name
+						for (i=0;i<3;i++)	*fnbPtr++ = de->deExtension[i];	// copy extension
+						*fnbPtr = 0;										// null-terminate
+						*/
+						u08 i;
+						unsigned char *dptr;
+
+						dptr = &FileNameBuffer;
+						for (i=0;i<11;i++)	*dptr++ = de->deName[i];		// copy name+ext
+						*dptr=0;	//ukonceni za nazvem
+
+						// desired entry has been found, break out
+						//pokud chtel longname, tak to neni a proto upravi 8+3 jmeno na nazev.ext
+						//aby to melo formatovani jako longname
+						if (use_long_names)
+						{
+							//upravi 'NAME    EXT' na 'NAME.EXT'
+							//(vyhazi mezery a prida tecku)
+							//krome nazvu '.          ', a '..         ', tam jen vyhaze mezery
+							unsigned char *sptr;
+							//EXT => .EXT   (posune vcetne 0x00 za koncem extenderu)
+							dptr=(FileNameBuffer+12);
+							i=4; do { sptr=dptr-1; *dptr=*sptr; dptr=sptr; i--; } while(i>0);
+							if (FileNameBuffer[0]!='.') *dptr='.'; //jen pro jine nez '.' a '..'
+							//NAME    .EXT => NAME.EXT
+							sptr=dptr=&FileNameBuffer;
+							do
+							{
+							 if ((*sptr)!=' ') *dptr++=*sptr;
+							 sptr++;
+							} while (*sptr);
+							*dptr=0; //ukonceni
+						}
+						//
+						gotEntry = 1;
+						break;
+					}
+					// otherwise
+					entrycount++;			// increment entry counter		
+				}
+			}
+		}
+fat_next_dir_entry:
+		// next directory entry
+		de++;
+		// next index
+		index++;
+	}
+	
+	// we have a file/dir to return
+	// store file/dir starting cluster (start of data)
+	FileInfo.vDisk.start_cluster = (unsigned short) (de->deStartCluster);
+	// fileindex
+	FileInfo.vDisk.file_index = entry;	//fileindex teto polozky
+	// store file/dir size (note: size field for subdirectory entries is always zero)
+	FileInfo.vDisk.size = de->deFileSize;
+	// store file/dir attributes
+	FileInfo.Attr = de->deAttributes;
+	// store file/dir last update time
+	FileInfo.Time = (unsigned short) (de->deMTime[0] | de->deMTime[1]<<8);
+	// store file/dir last update date
+	FileInfo.Date = (unsigned short) (de->deMDate[0] | de->deMDate[1]<<8);
+
+	if(gotEntry)
+	{
+		debug(" gotEntry ");
+		last_dir_entry = entrycount;
+		last_dir_index = index;
+		last_dir_sector = sector-1; //protoze ihned po nacteni se posune
+		last_dir_cluster = actual_cluster;
+		last_dir_sector_count = seccount; //skace se az za inkrementaci seccount, takze tady se 1 neodecita!
+		last_dir_valid=gotEntry;
+	}
+	else
+	{
+		debug(" not gotEntry ");
+	}
+
+	return gotEntry;
+}
+
+
+unsigned short nextCluster(unsigned short cluster)
+{
+	  unsigned short nextCluster;
+	  unsigned long fatOffset;
+	  unsigned long sector;
+	  unsigned long offset;
+
+	  // two FAT bytes (16 bits) for every cluster
+	  fatOffset = ((u32)cluster) << 1;
+
+	  // calculate the FAT sector that we're interested in
+	  sector = FirstFATSector + (fatOffset / ((u32)BytesPerSector));
+	  // calculate offset of the our entry within that FAT sector
+	  offset = fatOffset % ((u32)BytesPerSector);
+
+	  // if we don't already have this FAT chunk loaded, go get it
+	  // read sector of FAT table
+  	  mmcReadCached( sector );
+
+	  // read the nextCluster value
+	  nextCluster = (*((unsigned short*) &((char*)mmc_sector_buffer)[offset])) & FAT16_MASK;
+
+	  // check to see if we're at the end of the chain
+	  if (nextCluster == (CLUST_EOFE & FAT16_MASK))
+		nextCluster = 0;
+
+	return (nextCluster&0xFFFF);
+}
Index: unmerged/zpu_firmware/mist/led.h
===================================================================
--- unmerged/zpu_firmware/mist/led.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/zpu_firmware/mist/pause.h
===================================================================
--- unmerged/zpu_firmware/mist/pause.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/zpu_firmware/mist/regs.h
===================================================================
--- unmerged/zpu_firmware/mist/regs.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/regs.h	(revision 1)
@@ -0,0 +1,50 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x40000
+extern int volatile * zpu_config;
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+extern int volatile * zpu_sector;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_chactl;
+extern unsigned char volatile * atari_dmactl;
+extern unsigned char volatile * atari_skctl;
+
+#endif // regs_h
Index: unmerged/zpu_firmware/mist/standalone_simple.ld
===================================================================
--- unmerged/zpu_firmware/mist/standalone_simple.ld	(nonexistent)
+++ unmerged/zpu_firmware/mist/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/zpu_firmware/mist/types.h
===================================================================
--- unmerged/zpu_firmware/mist/types.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/zpu_firmware/mist/zpuromgen
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/zpuromgen
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mcc216/x
===================================================================
--- unmerged/zpu_firmware/mcc216/x	(nonexistent)
+++ unmerged/zpu_firmware/mcc216/x	(revision 1)
@@ -0,0 +1,20289 @@
+
+HelloTinyROM.elf:     file format elf32-zpu
+
+Disassembly of section .fixed_vectors:
+
+00000000 <_start>:
+   0:	0b          	nop
+   1:	0b          	nop
+   2:	0b          	nop
+   3:	89          	im 9
+   4:	ad          	im 45
+   5:	04          	poppc
+   6:	0b          	nop
+   7:	0b          	nop
+   8:	0b          	nop
+   9:	0b          	nop
+   a:	0b          	nop
+   b:	0b          	nop
+   c:	0b          	nop
+   d:	0b          	nop
+   e:	0b          	nop
+   f:	0b          	nop
+  10:	0b          	nop
+  11:	0b          	nop
+  12:	0b          	nop
+  13:	0b          	nop
+  14:	0b          	nop
+  15:	0b          	nop
+  16:	0b          	nop
+  17:	0b          	nop
+  18:	0b          	nop
+  19:	0b          	nop
+  1a:	0b          	nop
+  1b:	0b          	nop
+  1c:	0b          	nop
+  1d:	0b          	nop
+  1e:	0b          	nop
+  1f:	0b          	nop
+  20:	0b          	nop
+  21:	0b          	nop
+  22:	0b          	nop
+  23:	0b          	nop
+	...
+
+00000040 <_loadh>:
+  40:	71          	loadsp 4
+  41:	fd          	im -3
+  42:	06          	and
+  43:	08          	load
+  44:	72          	loadsp 8
+  45:	83          	im 3
+  46:	06          	and
+  47:	09          	not
+  48:	81          	im 1
+  49:	05          	add
+  4a:	82          	im 2
+  4b:	05          	add
+  4c:	83          	im 3
+  4d:	2b          	ashiftleft
+  4e:	2a          	lshiftright
+  4f:	83          	im 3
+  50:	ff          	im -1
+  51:	ff          	im -1
+  52:	06          	and
+  53:	52          	storesp 8
+  54:	04          	poppc
+	...
+
+00000060 <_storeh>:
+  60:	71          	loadsp 4
+  61:	fd          	im -3
+  62:	06          	and
+  63:	08          	load
+  64:	83          	im 3
+  65:	ff          	im -1
+  66:	ff          	im -1
+  67:	73          	loadsp 12
+  68:	83          	im 3
+  69:	06          	and
+  6a:	09          	not
+  6b:	81          	im 1
+  6c:	05          	add
+  6d:	82          	im 2
+  6e:	05          	add
+  6f:	83          	im 3
+  70:	2b          	ashiftleft
+  71:	2b          	ashiftleft
+  72:	09          	not
+  73:	06          	and
+  74:	73          	loadsp 12
+  75:	83          	im 3
+  76:	ff          	im -1
+  77:	ff          	im -1
+  78:	0b          	nop
+  79:	0b          	nop
+  7a:	0b          	nop
+  7b:	0b          	nop
+  7c:	83          	im 3
+  7d:	a7          	im 39
+  7e:	04          	poppc
+	...
+
+00000080 <_lessthan>:
+  80:	72          	loadsp 8
+  81:	09          	not
+  82:	81          	im 1
+  83:	05          	add
+  84:	72          	loadsp 8
+  85:	05          	add
+  86:	73          	loadsp 12
+  87:	73          	loadsp 12
+  88:	09          	not
+  89:	06          	and
+  8a:	09          	not
+  8b:	06          	and
+  8c:	73          	loadsp 12
+  8d:	09          	not
+  8e:	73          	loadsp 12
+  8f:	06          	and
+  90:	07          	or
+  91:	0a          	flip
+  92:	81          	im 1
+  93:	06          	and
+  94:	53          	storesp 12
+  95:	51          	storesp 4
+  96:	04          	poppc
+	...
+
+000000a0 <_lessthanorequal>:
+  a0:	72          	loadsp 8
+  a1:	72          	loadsp 8
+  a2:	24          	lessthan
+  a3:	73          	loadsp 12
+  a4:	73          	loadsp 12
+  a5:	2e          	eq
+  a6:	07          	or
+  a7:	53          	storesp 12
+  a8:	51          	storesp 4
+  a9:	04          	poppc
+	...
+
+000000c0 <_ulessthan>:
+  c0:	71          	loadsp 4
+  c1:	73          	loadsp 12
+  c2:	71          	loadsp 4
+  c3:	09          	not
+  c4:	71          	loadsp 4
+  c5:	06          	and
+  c6:	81          	im 1
+  c7:	06          	and
+  c8:	30          	neg
+  c9:	72          	loadsp 8
+  ca:	0a          	flip
+  cb:	10          	addsp 0
+  cc:	0a          	flip
+  cd:	72          	loadsp 8
+  ce:	0a          	flip
+  cf:	10          	addsp 0
+  d0:	0a          	flip
+  d1:	31          	sub
+  d2:	05          	add
+  d3:	0a          	flip
+  d4:	81          	im 1
+  d5:	06          	and
+  d6:	51          	storesp 4
+  d7:	51          	storesp 4
+  d8:	53          	storesp 12
+  d9:	51          	storesp 4
+  da:	04          	poppc
+  db:	00          	breakpoint
+  dc:	00          	breakpoint
+  dd:	00          	breakpoint
+	...
+
+000000e0 <_ulessthanorequal>:
+  e0:	72          	loadsp 8
+  e1:	72          	loadsp 8
+  e2:	26          	ulessthan
+  e3:	73          	loadsp 12
+  e4:	73          	loadsp 12
+  e5:	2e          	eq
+  e6:	07          	or
+  e7:	53          	storesp 12
+  e8:	51          	storesp 4
+  e9:	04          	poppc
+	...
+
+00000100 <_swap>:
+	...
+
+00000120 <_slowmult>:
+ 120:	0b          	nop
+ 121:	0b          	nop
+ 122:	0b          	nop
+ 123:	88          	im 8
+ 124:	bc          	im 60
+ 125:	04          	poppc
+	...
+
+00000140 <_lshiftright>:
+ 140:	72          	loadsp 8
+ 141:	0a          	flip
+ 142:	72          	loadsp 8
+ 143:	2b          	ashiftleft
+ 144:	0a          	flip
+ 145:	53          	storesp 12
+ 146:	51          	storesp 4
+ 147:	04          	poppc
+	...
+
+00000160 <_ashiftleft>:
+ 160:	72          	loadsp 8
+ 161:	72          	loadsp 8
+ 162:	9f          	im 31
+ 163:	06          	and
+ 164:	09          	not
+ 165:	81          	im 1
+ 166:	05          	add
+ 167:	0b          	nop
+ 168:	0b          	nop
+ 169:	0b          	nop
+ 16a:	88          	im 8
+ 16b:	9f          	im 31
+ 16c:	05          	add
+ 16d:	04          	poppc
+	...
+
+00000180 <_ashiftright>:
+ 180:	72          	loadsp 8
+ 181:	72          	loadsp 8
+ 182:	2a          	lshiftright
+ 183:	ff          	im -1
+ 184:	73          	loadsp 12
+ 185:	9f          	im 31
+ 186:	06          	and
+ 187:	2a          	lshiftright
+ 188:	09          	not
+ 189:	74          	loadsp 16
+ 18a:	09          	not
+ 18b:	0a          	flip
+ 18c:	81          	im 1
+ 18d:	06          	and
+ 18e:	ff          	im -1
+ 18f:	05          	add
+ 190:	06          	and
+ 191:	07          	or
+ 192:	53          	storesp 12
+ 193:	51          	storesp 4
+ 194:	04          	poppc
+	...
+
+000001a0 <_call>:
+ 1a0:	71          	loadsp 4
+ 1a1:	71          	loadsp 4
+ 1a2:	53          	storesp 12
+ 1a3:	51          	storesp 4
+ 1a4:	02          	pushsp
+ 1a5:	0d          	popsp
+ 1a6:	04          	poppc
+
+000001a7 <_storehtail>:
+ 1a7:	06          	and
+ 1a8:	73          	loadsp 12
+ 1a9:	83          	im 3
+ 1aa:	06          	and
+ 1ab:	09          	not
+ 1ac:	81          	im 1
+ 1ad:	05          	add
+ 1ae:	82          	im 2
+ 1af:	05          	add
+ 1b0:	83          	im 3
+ 1b1:	2b          	ashiftleft
+ 1b2:	0b          	nop
+ 1b3:	2b          	ashiftleft
+ 1b4:	07          	or
+ 1b5:	72          	loadsp 8
+ 1b6:	fc          	im -4
+ 1b7:	06          	and
+ 1b8:	0c          	store
+ 1b9:	51          	storesp 4
+ 1ba:	51          	storesp 4
+ 1bb:	04          	poppc
+ 1bc:	00          	breakpoint
+ 1bd:	00          	breakpoint
+	...
+
+000001c0 <_eq>:
+ 1c0:	72          	loadsp 8
+ 1c1:	09          	not
+ 1c2:	81          	im 1
+ 1c3:	05          	add
+ 1c4:	72          	loadsp 8
+ 1c5:	05          	add
+ 1c6:	09          	not
+ 1c7:	70          	loadsp 0
+ 1c8:	81          	im 1
+ 1c9:	05          	add
+ 1ca:	09          	not
+ 1cb:	06          	and
+ 1cc:	0a          	flip
+ 1cd:	81          	im 1
+ 1ce:	06          	and
+ 1cf:	53          	storesp 12
+ 1d0:	51          	storesp 4
+ 1d1:	04          	poppc
+	...
+
+000001e0 <_neq>:
+ 1e0:	72          	loadsp 8
+ 1e1:	09          	not
+ 1e2:	81          	im 1
+ 1e3:	05          	add
+ 1e4:	72          	loadsp 8
+ 1e5:	05          	add
+ 1e6:	09          	not
+ 1e7:	70          	loadsp 0
+ 1e8:	81          	im 1
+ 1e9:	05          	add
+ 1ea:	09          	not
+ 1eb:	06          	and
+ 1ec:	0a          	flip
+ 1ed:	09          	not
+ 1ee:	81          	im 1
+ 1ef:	06          	and
+ 1f0:	53          	storesp 12
+ 1f1:	51          	storesp 4
+ 1f2:	04          	poppc
+	...
+
+00000200 <_neg>:
+ 200:	71          	loadsp 4
+ 201:	09          	not
+ 202:	81          	im 1
+ 203:	05          	add
+ 204:	52          	storesp 8
+ 205:	04          	poppc
+	...
+
+00000220 <_sub>:
+ 220:	72          	loadsp 8
+ 221:	72          	loadsp 8
+ 222:	09          	not
+ 223:	81          	im 1
+ 224:	05          	add
+ 225:	05          	add
+ 226:	53          	storesp 12
+ 227:	51          	storesp 4
+ 228:	04          	poppc
+	...
+
+00000240 <_xor>:
+ 240:	72          	loadsp 8
+ 241:	09          	not
+ 242:	72          	loadsp 8
+ 243:	06          	and
+ 244:	73          	loadsp 12
+ 245:	73          	loadsp 12
+ 246:	09          	not
+ 247:	06          	and
+ 248:	07          	or
+ 249:	53          	storesp 12
+ 24a:	51          	storesp 4
+ 24b:	04          	poppc
+	...
+
+00000260 <_loadb>:
+ 260:	71          	loadsp 4
+ 261:	fc          	im -4
+ 262:	06          	and
+ 263:	08          	load
+ 264:	72          	loadsp 8
+ 265:	83          	im 3
+ 266:	06          	and
+ 267:	09          	not
+ 268:	81          	im 1
+ 269:	05          	add
+ 26a:	83          	im 3
+ 26b:	05          	add
+ 26c:	10          	addsp 0
+ 26d:	10          	addsp 0
+ 26e:	10          	addsp 0
+ 26f:	2a          	lshiftright
+ 270:	81          	im 1
+ 271:	ff          	im -1
+ 272:	06          	and
+ 273:	52          	storesp 8
+ 274:	04          	poppc
+	...
+
+00000280 <_storeb>:
+ 280:	71          	loadsp 4
+ 281:	fc          	im -4
+ 282:	06          	and
+ 283:	08          	load
+ 284:	0b          	nop
+ 285:	0b          	nop
+ 286:	80          	im 0
+ 287:	f4          	im -12
+ 288:	a4          	im 36
+ 289:	73          	loadsp 12
+ 28a:	83          	im 3
+ 28b:	06          	and
+ 28c:	10          	addsp 0
+ 28d:	10          	addsp 0
+ 28e:	05          	add
+ 28f:	08          	load
+ 290:	06          	and
+ 291:	0b          	nop
+ 292:	0b          	nop
+ 293:	0b          	nop
+ 294:	88          	im 8
+ 295:	a2          	im 34
+ 296:	04          	poppc
+	...
+
+000002a0 <_div>:
+ 2a0:	0b          	nop
+ 2a1:	0b          	nop
+ 2a2:	0b          	nop
+ 2a3:	88          	im 8
+ 2a4:	ff          	im -1
+ 2a5:	04          	poppc
+	...
+
+000002c0 <_mod>:
+ 2c0:	0b          	nop
+ 2c1:	0b          	nop
+ 2c2:	0b          	nop
+ 2c3:	88          	im 8
+ 2c4:	d8          	im -40
+ 2c5:	04          	poppc
+	...
+
+000002e0 <_eqbranch>:
+ 2e0:	72          	loadsp 8
+ 2e1:	09          	not
+ 2e2:	70          	loadsp 0
+ 2e3:	81          	im 1
+ 2e4:	05          	add
+ 2e5:	09          	not
+ 2e6:	06          	and
+ 2e7:	0a          	flip
+ 2e8:	81          	im 1
+ 2e9:	06          	and
+ 2ea:	ff          	im -1
+ 2eb:	05          	add
+ 2ec:	70          	loadsp 0
+ 2ed:	54          	storesp 16
+ 2ee:	71          	loadsp 4
+ 2ef:	06          	and
+ 2f0:	73          	loadsp 12
+ 2f1:	09          	not
+ 2f2:	72          	loadsp 8
+ 2f3:	74          	loadsp 16
+ 2f4:	05          	add
+ 2f5:	ff          	im -1
+ 2f6:	05          	add
+ 2f7:	06          	and
+ 2f8:	07          	or
+ 2f9:	51          	storesp 4
+ 2fa:	51          	storesp 4
+ 2fb:	51          	storesp 4
+ 2fc:	04          	poppc
+ 2fd:	00          	breakpoint
+	...
+
+00000300 <_neqbranch>:
+ 300:	72          	loadsp 8
+ 301:	09          	not
+ 302:	70          	loadsp 0
+ 303:	81          	im 1
+ 304:	05          	add
+ 305:	09          	not
+ 306:	06          	and
+ 307:	0a          	flip
+ 308:	09          	not
+ 309:	81          	im 1
+ 30a:	06          	and
+ 30b:	ff          	im -1
+ 30c:	05          	add
+ 30d:	70          	loadsp 0
+ 30e:	54          	storesp 16
+ 30f:	71          	loadsp 4
+ 310:	06          	and
+ 311:	73          	loadsp 12
+ 312:	09          	not
+ 313:	72          	loadsp 8
+ 314:	74          	loadsp 16
+ 315:	05          	add
+ 316:	ff          	im -1
+ 317:	05          	add
+ 318:	06          	and
+ 319:	07          	or
+ 31a:	51          	storesp 4
+ 31b:	51          	storesp 4
+ 31c:	51          	storesp 4
+ 31d:	04          	poppc
+	...
+
+00000320 <_poppcrel>:
+ 320:	05          	add
+ 321:	ff          	im -1
+ 322:	05          	add
+ 323:	04          	poppc
+	...
+
+00000340 <_config>:
+ 340:	81          	im 1
+ 341:	0b          	nop
+ 342:	80          	im 0
+ 343:	f9          	im -7
+ 344:	f0          	im -16
+ 345:	0c          	store
+ 346:	51          	storesp 4
+ 347:	04          	poppc
+	...
+
+0000035e <_pushpc>:
+ 35e:	71          	loadsp 4
+ 35f:	81          	im 1
+ 360:	05          	add
+ 361:	52          	storesp 8
+ 362:	04          	poppc
+	...
+
+0000037e <_syscall_emulate>:
+	...
+
+0000039e <_pushspadd>:
+ 39e:	02          	pushsp
+ 39f:	84          	im 4
+ 3a0:	05          	add
+ 3a1:	72          	loadsp 8
+ 3a2:	10          	addsp 0
+ 3a3:	10          	addsp 0
+ 3a4:	05          	add
+ 3a5:	52          	storesp 8
+ 3a6:	04          	poppc
+	...
+
+000003be <_halfmult>:
+	...
+
+000003de <_callpcrel>:
+ 3de:	71          	loadsp 4
+ 3df:	71          	loadsp 4
+ 3e0:	05          	add
+ 3e1:	ff          	im -1
+ 3e2:	05          	add
+ 3e3:	71          	loadsp 4
+ 3e4:	53          	storesp 12
+ 3e5:	51          	storesp 4
+ 3e6:	02          	pushsp
+ 3e7:	0d          	popsp
+ 3e8:	04          	poppc
+	...
+Disassembly of section .text:
+
+00000400 <_ashiftleftBegin>:
+     400:	10          	addsp 0
+     401:	10          	addsp 0
+     402:	10          	addsp 0
+     403:	10          	addsp 0
+     404:	10          	addsp 0
+     405:	10          	addsp 0
+     406:	10          	addsp 0
+     407:	10          	addsp 0
+     408:	10          	addsp 0
+     409:	10          	addsp 0
+     40a:	10          	addsp 0
+     40b:	10          	addsp 0
+     40c:	10          	addsp 0
+     40d:	10          	addsp 0
+     40e:	10          	addsp 0
+     40f:	10          	addsp 0
+     410:	10          	addsp 0
+     411:	10          	addsp 0
+     412:	10          	addsp 0
+     413:	10          	addsp 0
+     414:	10          	addsp 0
+     415:	10          	addsp 0
+     416:	10          	addsp 0
+     417:	10          	addsp 0
+     418:	10          	addsp 0
+     419:	10          	addsp 0
+     41a:	10          	addsp 0
+     41b:	10          	addsp 0
+     41c:	10          	addsp 0
+     41d:	10          	addsp 0
+     41e:	10          	addsp 0
+
+0000041f <_ashiftleftEnd>:
+     41f:	53          	storesp 12
+     420:	51          	storesp 4
+     421:	04          	poppc
+
+00000422 <_storebtail>:
+     422:	73          	loadsp 12
+     423:	81          	im 1
+     424:	ff          	im -1
+     425:	06          	and
+     426:	73          	loadsp 12
+     427:	83          	im 3
+     428:	06          	and
+     429:	09          	not
+     42a:	81          	im 1
+     42b:	05          	add
+     42c:	83          	im 3
+     42d:	05          	add
+     42e:	10          	addsp 0
+     42f:	10          	addsp 0
+     430:	10          	addsp 0
+     431:	2b          	ashiftleft
+     432:	07          	or
+     433:	72          	loadsp 8
+     434:	fc          	im -4
+     435:	06          	and
+     436:	0c          	store
+     437:	51          	storesp 4
+     438:	51          	storesp 4
+     439:	04          	poppc
+
+0000043a <_syscall>:
+     43a:	3c          	syscall
+     43b:	04          	poppc
+
+0000043c <_slowmultImpl>:
+     43c:	72          	loadsp 8
+     43d:	72          	loadsp 8
+     43e:	80          	im 0
+     43f:	72          	loadsp 8
+     440:	81          	im 1
+     441:	06          	and
+     442:	ff          	im -1
+     443:	05          	add
+     444:	09          	not
+     445:	72          	loadsp 8
+     446:	06          	and
+     447:	05          	add
+     448:	71          	loadsp 4
+     449:	10          	addsp 0
+     44a:	52          	storesp 8
+     44b:	72          	loadsp 8
+     44c:	0a          	flip
+     44d:	10          	addsp 0
+     44e:	0a          	flip
+     44f:	53          	storesp 12
+     450:	72          	loadsp 8
+     451:	ed          	im -19
+     452:	38          	neqbranch
+     453:	51          	storesp 4
+     454:	51          	storesp 4
+     455:	53          	storesp 12
+     456:	51          	storesp 4
+     457:	04          	poppc
+
+00000458 <___mod>:
+     458:	83          	im 3
+     459:	e0          	im -32
+     45a:	80          	im 0
+     45b:	08          	load
+     45c:	83          	im 3
+     45d:	e0          	im -32
+     45e:	84          	im 4
+     45f:	08          	load
+     460:	83          	im 3
+     461:	e0          	im -32
+     462:	88          	im 8
+     463:	08          	load
+     464:	75          	loadsp 20
+     465:	75          	loadsp 20
+     466:	80          	im 0
+     467:	ee          	im -18
+     468:	d4          	im -44
+     469:	2d          	call
+     46a:	50          	storesp 0
+     46b:	50          	storesp 0
+     46c:	83          	im 3
+     46d:	e0          	im -32
+     46e:	80          	im 0
+     46f:	08          	load
+     470:	56          	storesp 24
+     471:	83          	im 3
+     472:	e0          	im -32
+     473:	88          	im 8
+     474:	0c          	store
+     475:	83          	im 3
+     476:	e0          	im -32
+     477:	84          	im 4
+     478:	0c          	store
+     479:	83          	im 3
+     47a:	e0          	im -32
+     47b:	80          	im 0
+     47c:	0c          	store
+     47d:	51          	storesp 4
+     47e:	04          	poppc
+
+0000047f <___div>:
+     47f:	83          	im 3
+     480:	e0          	im -32
+     481:	80          	im 0
+     482:	08          	load
+     483:	83          	im 3
+     484:	e0          	im -32
+     485:	84          	im 4
+     486:	08          	load
+     487:	83          	im 3
+     488:	e0          	im -32
+     489:	88          	im 8
+     48a:	08          	load
+     48b:	75          	loadsp 20
+     48c:	75          	loadsp 20
+     48d:	80          	im 0
+     48e:	ec          	im -20
+     48f:	e8          	im -24
+     490:	2d          	call
+     491:	50          	storesp 0
+     492:	50          	storesp 0
+     493:	83          	im 3
+     494:	e0          	im -32
+     495:	80          	im 0
+     496:	08          	load
+     497:	56          	storesp 24
+     498:	83          	im 3
+     499:	e0          	im -32
+     49a:	88          	im 8
+     49b:	0c          	store
+     49c:	83          	im 3
+     49d:	e0          	im -32
+     49e:	84          	im 4
+     49f:	0c          	store
+     4a0:	83          	im 3
+     4a1:	e0          	im -32
+     4a2:	80          	im 0
+     4a3:	0c          	store
+     4a4:	51          	storesp 4
+     4a5:	04          	poppc
+	...
+
+000004a8 <_boot>:
+     4a8:	80          	im 0
+     4a9:	04          	poppc
+
+000004aa <_break>:
+     4aa:	89          	im 9
+     4ab:	aa          	im 42
+     4ac:	04          	poppc
+
+000004ad <_premain>:
+     4ad:	89          	im 9
+     4ae:	aa          	im 42
+     4af:	0b          	nop
+     4b0:	bf          	im 63
+     4b1:	fb          	im -5
+     4b2:	04          	poppc
+
+000004b3 <wait_us>:
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+     4b3:	fd          	im -3
+     4b4:	3d          	pushspadd
+     4b5:	0d          	popsp
+
+000004b6 <.LM2>:
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+     4b6:	75          	loadsp 20
+     4b7:	b9          	im 57
+     4b8:	29          	mult
+     4b9:	76          	loadsp 24
+     4ba:	81          	im 1
+     4bb:	2a          	lshiftright
+     4bc:	05          	add
+
+000004bd <.LM3>:
+	*zpu_pause = cycles;
+     4bd:	80          	im 0
+     4be:	fc          	im -4
+     4bf:	c0          	im -64
+     4c0:	08          	load
+     4c1:	54          	storesp 16
+     4c2:	73          	loadsp 12
+     4c3:	0c          	store
+     4c4:	85          	im 5
+     4c5:	3d          	pushspadd
+     4c6:	0d          	popsp
+     4c7:	04          	poppc
+
+000004c8 <clearAtariSectorBuffer>:
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+     4c8:	80          	im 0
+     4c9:	3d          	pushspadd
+     4ca:	0d          	popsp
+
+000004cb <.LM5>:
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+     4cb:	81          	im 1
+     4cc:	ff          	im -1
+     4cd:	51          	storesp 4
+
+000004ce <.L5>:
+     4ce:	80          	im 0
+     4cf:	0b          	nop
+     4d0:	83          	im 3
+     4d1:	e0          	im -32
+     4d2:	c8          	im -56
+     4d3:	12          	addsp 8
+     4d4:	34          	storeb
+     4d5:	ff          	im -1
+     4d6:	11          	addsp 4
+     4d7:	51          	storesp 4
+     4d8:	70          	loadsp 0
+     4d9:	f4          	im -12
+     4da:	38          	neqbranch
+     4db:	82          	im 2
+     4dc:	3d          	pushspadd
+     4dd:	0d          	popsp
+     4de:	04          	poppc
+
+000004df <filesize>:
+}
+
+int
+filesize(char const * filename)
+{
+     4df:	fa          	im -6
+     4e0:	3d          	pushspadd
+     4e1:	0d          	popsp
+     4e2:	78          	loadsp 32
+
+000004e3 <.LM7>:
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+     4e3:	0b          	nop
+     4e4:	0b          	nop
+     4e5:	80          	im 0
+     4e6:	f4          	im -12
+     4e7:	fc          	im -4
+     4e8:	53          	storesp 12
+     4e9:	83          	im 3
+     4ea:	e2          	im -30
+     4eb:	f4          	im -12
+     4ec:	52          	storesp 8
+     4ed:	56          	storesp 24
+     4ee:	80          	im 0
+     4ef:	cc          	im -52
+     4f0:	a8          	im 40
+     4f1:	3f          	callpcrel
+
+000004f2 <.LM8>:
+	{
+		return 0;
+     4f2:	80          	im 0
+     4f3:	53          	storesp 12
+
+000004f4 <.LM9>:
+     4f4:	83          	im 3
+     4f5:	e0          	im -32
+     4f6:	80          	im 0
+     4f7:	08          	load
+     4f8:	73          	loadsp 12
+     4f9:	2e          	eq
+     4fa:	8a          	im 10
+     4fb:	38          	neqbranch
+
+000004fc <.LM10>:
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+     4fc:	72          	loadsp 8
+     4fd:	83          	im 3
+     4fe:	e0          	im -32
+     4ff:	80          	im 0
+     500:	0c          	store
+     501:	88          	im 8
+     502:	3d          	pushspadd
+     503:	0d          	popsp
+     504:	04          	poppc
+
+00000505 <.L26>:
+     505:	83          	im 3
+     506:	e0          	im -32
+     507:	94          	im 20
+     508:	52          	storesp 8
+     509:	83          	im 3
+     50a:	e2          	im -30
+     50b:	f4          	im -12
+     50c:	51          	storesp 4
+     50d:	80          	im 0
+     50e:	cd          	im -51
+     50f:	9c          	im 28
+     510:	3f          	callpcrel
+     511:	83          	im 3
+     512:	e0          	im -32
+     513:	80          	im 0
+     514:	08          	load
+     515:	80          	im 0
+     516:	d5          	im -43
+     517:	38          	neqbranch
+     518:	83          	im 3
+     519:	e0          	im -32
+     51a:	9d          	im 29
+     51b:	33          	loadb
+     51c:	53          	storesp 12
+     51d:	72          	loadsp 8
+     51e:	80          	im 0
+     51f:	2e          	eq
+     520:	80          	im 0
+     521:	ca          	im -54
+     522:	38          	neqbranch
+
+00000523 <.LM12>:
+     523:	83          	im 3
+     524:	e0          	im -32
+     525:	9c          	im 28
+     526:	33          	loadb
+     527:	70          	loadsp 0
+     528:	82          	im 2
+     529:	2a          	lshiftright
+     52a:	70          	loadsp 0
+     52b:	81          	im 1
+     52c:	06          	and
+     52d:	51          	storesp 4
+     52e:	54          	storesp 16
+     52f:	54          	storesp 16
+     530:	72          	loadsp 8
+     531:	d3          	im -45
+     532:	38          	neqbranch
+
+00000533 <.LM13>:
+     533:	73          	loadsp 12
+     534:	81          	im 1
+     535:	2a          	lshiftright
+     536:	70          	loadsp 0
+     537:	81          	im 1
+     538:	06          	and
+     539:	51          	storesp 4
+     53a:	53          	storesp 12
+     53b:	72          	loadsp 8
+     53c:	c8          	im -56
+     53d:	38          	neqbranch
+
+0000053e <.LM14>:
+     53e:	73          	loadsp 12
+     53f:	84          	im 4
+     540:	2a          	lshiftright
+     541:	70          	loadsp 0
+     542:	81          	im 1
+     543:	06          	and
+     544:	51          	storesp 4
+     545:	53          	storesp 12
+     546:	72          	loadsp 8
+     547:	ff          	im -1
+     548:	bc          	im 60
+     549:	38          	neqbranch
+
+0000054a <.LM15>:
+     54a:	75          	loadsp 20
+
+0000054b <.LM16>:
+     54b:	83          	im 3
+     54c:	e0          	im -32
+     54d:	9d          	im 29
+     54e:	56          	storesp 24
+     54f:	54          	storesp 16
+
+00000550 <.L16>:
+     550:	73          	loadsp 12
+     551:	33          	loadb
+     552:	75          	loadsp 20
+     553:	33          	loadb
+     554:	58          	storesp 32
+     555:	53          	storesp 12
+     556:	72          	loadsp 8
+     557:	77          	loadsp 28
+     558:	2e          	eq
+     559:	09          	not
+     55a:	81          	im 1
+     55b:	06          	and
+     55c:	ff          	im -1
+     55d:	a7          	im 39
+     55e:	38          	neqbranch
+
+0000055f <.LM18>:
+     55f:	72          	loadsp 8
+     560:	80          	im 0
+     561:	2e          	eq
+     562:	93          	im 19
+     563:	38          	neqbranch
+
+00000564 <.LM19>:
+     564:	81          	im 1
+     565:	14          	addsp 16
+
+00000566 <.LM20>:
+     566:	81          	im 1
+     567:	16          	addsp 24
+     568:	56          	storesp 24
+     569:	54          	storesp 16
+     56a:	e5          	im -27
+     56b:	39          	poppcrel
+
+0000056c <.L12>:
+     56c:	80          	im 0
+
+0000056d <.LM22>:
+     56d:	0b          	nop
+     56e:	83          	im 3
+     56f:	e0          	im -32
+     570:	80          	im 0
+     571:	0c          	store
+     572:	88          	im 8
+     573:	3d          	pushspadd
+     574:	0d          	popsp
+     575:	04          	poppc
+
+00000576 <.L22>:
+     576:	83          	im 3
+     577:	e0          	im -32
+     578:	94          	im 20
+     579:	08          	load
+
+0000057a <.LM24>:
+     57a:	83          	im 3
+     57b:	e0          	im -32
+     57c:	80          	im 0
+     57d:	0c          	store
+     57e:	88          	im 8
+     57f:	3d          	pushspadd
+     580:	0d          	popsp
+     581:	04          	poppc
+
+00000582 <clear_ram>:
+
+int
+selectfile(char * filename)
+{
+	int fileno;
+	int skip;
+	int plotted = 0;
+	wait_us(200000);
+	for(;;)
+	{
+		int i = 0;
+		int go = 0;
+		fileno = 0;
+		topofscreen();
+		for (i=0; i!=(24*40); ++i)
+		{
+			*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+		}
+		if (FR_OK != pf_opendir(&dir,"/"))
+		{
+			debug("opendir failed\n");
+			while(1);
+		}
+
+		plotted = 0;
+		skip = 0;
+		if (selfileno>20)
+		{
+			skip = selfileno-20;
+			skip&=0xfffffffe;
+		}
+		if (selfileno<0)
+		{
+			selfileno = 0;
+		}
+		while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+		{
+			if (filinfo.fattrib & AM_SYS)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_HID)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_DIR)
+			{
+				debug("DIR ");
+			}
+			if (selfileno == fileno)
+			{
+				for (i=0;i!=15;++i)
+				{
+					filename[i] = filinfo.fname[i];
+					if (0==filinfo.fname[i]) break;
+					filinfo.fname[i]+=128;
+				}
+			}
+			if (--skip<0)
+			{
+				debug(filinfo.fname);
+				++plotted;
+				if (plotted&1)
+				{
+					setxpos(20);
+				}
+				else
+				{
+					debug("\n");
+				}
+				if (plotted==40)
+				{
+					break;
+				}
+			}
+			fileno++;
+		}
+		debug("\n");
+		setypos(21);
+		opendrive = 0;
+		openfile(filename);
+		for (;;)
+		{
+			unsigned char porta = *atari_porta;
+			if (0==(porta&0x2)) // down
+			{
+				selfileno+=2;
+				break;
+			}
+			else if (0==(porta&0x1)) // up
+			{
+				selfileno-=2;
+				break;
+			}
+			else if (0==(porta&0x8)) // right
+			{
+				selfileno|=1;
+				break;
+			}
+			else if (0==(porta&0x4)) // left
+			{
+				selfileno&=0xfffffffe;
+				break;
+			}
+			else if (0==(*atari_trig0)) // fire
+			{
+				go = 1;
+				while(0==(*atari_trig0));
+				break;
+			}
+			topofscreen();
+			//plotnextnumber(porta);
+			*atari_colbk = *atari_random;
+			//wait_us(200);
+		}
+		if (go == 1)
+		{
+			wait_us(200000);
+			return validfile; // TODO, another way to quit without selecting...
+		}
+		wait_us(80000);
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+     582:	fd          	im -3
+     583:	3d          	pushspadd
+     584:	0d          	popsp
+
+00000585 <.LM26>:
+	int i=0;
+     585:	80          	im 0
+
+00000586 <.LM27>:
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+     586:	0b          	nop
+     587:	80          	im 0
+     588:	fc          	im -4
+     589:	b0          	im 48
+     58a:	08          	load
+     58b:	53          	storesp 12
+     58c:	53          	storesp 12
+     58d:	ff          	im -1
+     58e:	72          	loadsp 8
+     58f:	0c          	store
+
+00000590 <.LM28>:
+	*zpu_ledg = 0x0;
+     590:	80          	im 0
+     591:	fc          	im -4
+     592:	b4          	im 52
+     593:	08          	load
+     594:	73          	loadsp 12
+     595:	71          	loadsp 4
+     596:	0c          	store
+     597:	52          	storesp 8
+
+00000598 <.LM29>:
+	wait_us(600);
+     598:	84          	im 4
+     599:	d8          	im -40
+     59a:	51          	storesp 4
+     59b:	fe          	im -2
+     59c:	96          	im 22
+     59d:	3f          	callpcrel
+
+0000059e <.LM30>:
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+     59e:	88          	im 8
+     59f:	80          	im 0
+     5a0:	0a          	flip
+     5a1:	53          	storesp 12
+
+000005a2 <.L32>:
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+     5a2:	80          	im 0
+     5a3:	73          	loadsp 12
+     5a4:	70          	loadsp 0
+     5a5:	81          	im 1
+     5a6:	05          	add
+     5a7:	55          	storesp 20
+     5a8:	34          	storeb
+
+000005a9 <.LM32>:
+     5a9:	72          	loadsp 8
+     5aa:	a8          	im 40
+     5ab:	80          	im 0
+     5ac:	0a          	flip
+     5ad:	2e          	eq
+     5ae:	09          	not
+     5af:	81          	im 1
+     5b0:	06          	and
+     5b1:	f0          	im -16
+     5b2:	38          	neqbranch
+
+000005b3 <.LM33>:
+	}
+
+	*zpu_ledr = 0x55555555;
+     5b3:	80          	im 0
+     5b4:	fc          	im -4
+     5b5:	b0          	im 48
+     5b6:	08          	load
+     5b7:	54          	storesp 16
+     5b8:	85          	im 5
+     5b9:	aa          	im 42
+     5ba:	d5          	im -43
+     5bb:	aa          	im 42
+     5bc:	d5          	im -43
+     5bd:	74          	loadsp 16
+     5be:	0c          	store
+
+000005bf <.LM34>:
+	*zpu_ledg = 0x55555555;
+     5bf:	80          	im 0
+     5c0:	fc          	im -4
+     5c1:	b4          	im 52
+     5c2:	08          	load
+     5c3:	52          	storesp 8
+     5c4:	85          	im 5
+     5c5:	aa          	im 42
+     5c6:	d5          	im -43
+     5c7:	aa          	im 42
+     5c8:	d5          	im -43
+     5c9:	72          	loadsp 8
+     5ca:	0c          	store
+
+000005cb <.LM35>:
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+     5cb:	82          	im 2
+     5cc:	80          	im 0
+     5cd:	0a          	flip
+     5ce:	53          	storesp 12
+
+000005cf <.L36>:
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+     5cf:	80          	im 0
+     5d0:	73          	loadsp 12
+     5d1:	70          	loadsp 0
+     5d2:	84          	im 4
+     5d3:	05          	add
+     5d4:	55          	storesp 20
+     5d5:	0c          	store
+
+000005d6 <.LM37>:
+     5d6:	72          	loadsp 8
+     5d7:	81          	im 1
+     5d8:	80          	im 0
+     5d9:	0a          	flip
+     5da:	2e          	eq
+     5db:	09          	not
+     5dc:	81          	im 1
+     5dd:	06          	and
+     5de:	f0          	im -16
+     5df:	38          	neqbranch
+
+000005e0 <.LM38>:
+	}
+
+	*zpu_ledr = 0;
+     5e0:	80          	im 0
+     5e1:	74          	loadsp 16
+     5e2:	0c          	store
+
+000005e3 <.LM39>:
+	*zpu_ledg = 0xffffffff;
+     5e3:	ff          	im -1
+     5e4:	72          	loadsp 8
+     5e5:	0c          	store
+
+000005e6 <.LM40>:
+	wait_us(600);
+     5e6:	84          	im 4
+     5e7:	d8          	im -40
+     5e8:	51          	storesp 4
+     5e9:	fd          	im -3
+     5ea:	c8          	im -56
+     5eb:	3f          	callpcrel
+
+000005ec <.LM41>:
+	return;
+     5ec:	85          	im 5
+     5ed:	3d          	pushspadd
+     5ee:	0d          	popsp
+     5ef:	04          	poppc
+
+000005f0 <clear_64k_ram>:
+}
+
+void clear_64k_ram()
+{
+     5f0:	fd          	im -3
+     5f1:	3d          	pushspadd
+     5f2:	0d          	popsp
+
+000005f3 <.LM43>:
+	int i=0;
+     5f3:	80          	im 0
+
+000005f4 <.LM44>:
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+     5f4:	0b          	nop
+     5f5:	80          	im 0
+     5f6:	fc          	im -4
+     5f7:	b0          	im 48
+     5f8:	08          	load
+     5f9:	53          	storesp 12
+     5fa:	53          	storesp 12
+     5fb:	ff          	im -1
+     5fc:	87          	im 7
+     5fd:	c3          	im -61
+     5fe:	e1          	im -31
+     5ff:	f0          	im -16
+     600:	72          	loadsp 8
+     601:	0c          	store
+
+00000602 <.LM45>:
+	*zpu_ledg = 0x0;
+     602:	80          	im 0
+     603:	fc          	im -4
+     604:	b4          	im 52
+     605:	08          	load
+     606:	73          	loadsp 12
+     607:	71          	loadsp 4
+     608:	0c          	store
+     609:	52          	storesp 8
+
+0000060a <.LM46>:
+	wait_us(200000);
+     60a:	8c          	im 12
+     60b:	9a          	im 26
+     60c:	c0          	im -64
+     60d:	51          	storesp 4
+     60e:	fd          	im -3
+     60f:	a3          	im 35
+     610:	3f          	callpcrel
+
+00000611 <.LM47>:
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+     611:	88          	im 8
+     612:	80          	im 0
+     613:	0a          	flip
+     614:	53          	storesp 12
+
+00000615 <.L46>:
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+     615:	80          	im 0
+     616:	73          	loadsp 12
+     617:	70          	loadsp 0
+     618:	81          	im 1
+     619:	05          	add
+     61a:	55          	storesp 20
+     61b:	34          	storeb
+
+0000061c <.LM49>:
+     61c:	72          	loadsp 8
+     61d:	81          	im 1
+     61e:	84          	im 4
+     61f:	80          	im 0
+     620:	80          	im 0
+     621:	2e          	eq
+     622:	09          	not
+     623:	81          	im 1
+     624:	06          	and
+     625:	ef          	im -17
+     626:	38          	neqbranch
+
+00000627 <.LM50>:
+	}
+
+	*zpu_ledr = 0x55555555;
+     627:	80          	im 0
+     628:	fc          	im -4
+     629:	b0          	im 48
+     62a:	08          	load
+     62b:	54          	storesp 16
+     62c:	85          	im 5
+     62d:	aa          	im 42
+     62e:	d5          	im -43
+     62f:	aa          	im 42
+     630:	d5          	im -43
+     631:	74          	loadsp 16
+     632:	0c          	store
+
+00000633 <.LM51>:
+	*zpu_ledg = 0x55555555;
+     633:	80          	im 0
+     634:	fc          	im -4
+     635:	b4          	im 52
+     636:	08          	load
+     637:	52          	storesp 8
+     638:	85          	im 5
+     639:	aa          	im 42
+     63a:	d5          	im -43
+     63b:	aa          	im 42
+     63c:	d5          	im -43
+     63d:	72          	loadsp 8
+     63e:	0c          	store
+
+0000063f <.LM52>:
+
+	for (i=0x800000; i!=0x810000; i+=4)
+     63f:	82          	im 2
+     640:	80          	im 0
+     641:	0a          	flip
+     642:	53          	storesp 12
+
+00000643 <.L50>:
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+     643:	80          	im 0
+     644:	73          	loadsp 12
+     645:	70          	loadsp 0
+     646:	84          	im 4
+     647:	05          	add
+     648:	55          	storesp 20
+     649:	0c          	store
+
+0000064a <.LM54>:
+     64a:	72          	loadsp 8
+     64b:	84          	im 4
+     64c:	84          	im 4
+     64d:	80          	im 0
+     64e:	80          	im 0
+     64f:	2e          	eq
+     650:	09          	not
+     651:	81          	im 1
+     652:	06          	and
+     653:	ef          	im -17
+     654:	38          	neqbranch
+
+00000655 <.LM55>:
+	}
+
+	*zpu_ledr = 0;
+     655:	80          	im 0
+     656:	74          	loadsp 16
+     657:	0c          	store
+
+00000658 <.LM56>:
+	*zpu_ledg = 0xf0f0f0f0;
+     658:	ff          	im -1
+     659:	87          	im 7
+     65a:	c3          	im -61
+     65b:	e1          	im -31
+     65c:	f0          	im -16
+     65d:	72          	loadsp 8
+     65e:	0c          	store
+
+0000065f <.LM57>:
+	wait_us(200000);
+     65f:	8c          	im 12
+     660:	9a          	im 26
+     661:	c0          	im -64
+     662:	51          	storesp 4
+     663:	fc          	im -4
+     664:	ce          	im -50
+     665:	3f          	callpcrel
+
+00000666 <.LM58>:
+	return;
+     666:	85          	im 5
+     667:	3d          	pushspadd
+     668:	0d          	popsp
+     669:	04          	poppc
+
+0000066a <reset_6502>:
+}
+
+void reset_6502(unsigned int reset_n)
+{
+     66a:	ff          	im -1
+     66b:	3d          	pushspadd
+     66c:	0d          	popsp
+
+0000066d <.LM60>:
+	int prev = *zpu_config;
+     66d:	80          	im 0
+     66e:	fc          	im -4
+     66f:	c4          	im -60
+     670:	08          	load
+     671:	70          	loadsp 0
+     672:	08          	load
+     673:	52          	storesp 8
+     674:	52          	storesp 8
+
+00000675 <.LM61>:
+	if (reset_n == 1)
+     675:	73          	loadsp 12
+     676:	81          	im 1
+     677:	2e          	eq
+     678:	8b          	im 11
+     679:	38          	neqbranch
+
+0000067a <.LM62>:
+		*zpu_config = prev&~(1<<7);
+	else
+		*zpu_config = prev|(1<<7);
+     67a:	70          	loadsp 0
+     67b:	81          	im 1
+     67c:	80          	im 0
+     67d:	07          	or
+     67e:	72          	loadsp 8
+     67f:	0c          	store
+
+00000680 <.LM63>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+     680:	83          	im 3
+     681:	3d          	pushspadd
+     682:	0d          	popsp
+     683:	04          	poppc
+
+00000684 <.L61>:
+     684:	70          	loadsp 0
+     685:	fe          	im -2
+     686:	ff          	im -1
+     687:	06          	and
+
+00000688 <.LM65>:
+     688:	72          	loadsp 8
+     689:	0c          	store
+
+0000068a <.LM66>:
+     68a:	83          	im 3
+     68b:	3d          	pushspadd
+     68c:	0d          	popsp
+     68d:	04          	poppc
+
+0000068e <pause_6502>:
+
+void pause_6502(unsigned int pause)
+{
+     68e:	ff          	im -1
+     68f:	3d          	pushspadd
+     690:	0d          	popsp
+
+00000691 <.LM68>:
+	int prev = *zpu_config;
+     691:	80          	im 0
+     692:	fc          	im -4
+     693:	c4          	im -60
+     694:	08          	load
+     695:	70          	loadsp 0
+     696:	08          	load
+     697:	52          	storesp 8
+     698:	52          	storesp 8
+
+00000699 <.LM69>:
+	if (pause == 0)
+     699:	73          	loadsp 12
+     69a:	8b          	im 11
+     69b:	38          	neqbranch
+
+0000069c <.LM70>:
+		*zpu_config = prev&~(1<<6);
+     69c:	70          	loadsp 0
+     69d:	ff          	im -1
+     69e:	bf          	im 63
+     69f:	06          	and
+
+000006a0 <.LM71>:
+	else
+		*zpu_config = prev|(1<<6);
+     6a0:	72          	loadsp 8
+     6a1:	0c          	store
+
+000006a2 <.LM72>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+     6a2:	83          	im 3
+     6a3:	3d          	pushspadd
+     6a4:	0d          	popsp
+     6a5:	04          	poppc
+
+000006a6 <.L63>:
+     6a6:	70          	loadsp 0
+     6a7:	80          	im 0
+     6a8:	c0          	im -64
+     6a9:	07          	or
+     6aa:	72          	loadsp 8
+     6ab:	0c          	store
+
+000006ac <.LM74>:
+     6ac:	83          	im 3
+     6ad:	3d          	pushspadd
+     6ae:	0d          	popsp
+     6af:	04          	poppc
+
+000006b0 <disk_initialize>:
+
+void actions()
+{
+	unsigned int i = 0;
+	//unsigned volatile char * store = 0xf00000; // SDRAM - fails!!
+	unsigned volatile char * store = 0x27f000; // SRAM...
+	unsigned volatile char * store2 = 0x270000; // custom chips...
+
+	if ((1&*zpu_key) == 1)
+	{
+		unsigned char volatile * mem;
+		unsigned char volatile * mem2;
+		unsigned char volatile * mem3;
+		unsigned char store_portb;
+		int reboot = 0;
+		int temp;
+		int row = 0;
+		int next = 0;
+		int go = 0;
+
+		// stop 6502
+		pause_6502(1);
+
+		// TODO - 
+		// menu for 64k/128k/320K Compy/320K Rambo
+		// menu for ROM bank
+		// menu for GPIO on/off
+
+		initdebug(1);
+
+		mem = 0x9c00 + 0x10000;
+		// Copy 1k from 0x$9c00 to sdram
+		// 0x200000; sram
+		// 0x800000; sdram (always use...)
+		for (i=0x0; i!=1024; i++)
+		{
+			store[i] = mem[i];
+		}
+		for (i=0x40; i!=1024; i++)
+		{
+			mem[i] = 0;
+		}
+
+		{
+			//gtia
+			mem2 = 0x20000;
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+		}
+
+		store_portb = *atari_portb;
+
+		// write a display list at 9c00
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x9c
+		};
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x9c;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+		*atari_portb = 0xff;
+		*atari_skctl = 0x3;
+		*atari_chactl = 0x2;
+
+		for (;;)
+		{
+			wait_us(120000);
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			// 0-5 speed
+			// 6-pause
+			// 7-reset
+			// 8-9-ram
+			// 12-13-rom
+			// 16-gpio_enable
+			debug("System settings\n");
+			debug("---------------\n");
+			debug("Memory:");
+			temp = 0xf&((*zpu_config)>>8);
+			if (row == 0)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xfffff0ff)|((temp&0x3)<<8);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("64KiB");
+				break;
+			case 1:
+				debug("128KiB");
+				break;
+			case 2:
+				debug("320KiB Compy Shop");
+				break;
+			case 3:
+				debug("320KiB Rambo");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("ROM bank:");
+			temp = 0xf&((*zpu_config)>>12);
+			if (row == 1)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xffff0fff)|((temp&0x3)<<12);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("0 (default:XL)");
+				break;
+			case 1:
+				debug("1 (default:XL + hi speed)");
+				break;
+			case 2:
+				debug("2 (default:Ultimon)");
+				break;
+			case 3:
+				debug("3 (default:OS B + hi speed)");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("Speed:");
+			temp = 0x3f&((*zpu_config)>>0);
+			if (row == 2)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					if (temp < 0) temp =0;
+					*zpu_config = (*zpu_config&0xffffffc0)|(temp&0x3f);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			plotnextnumber(57500/(temp+1));
+			debug(" KHz\nD1:"); // Bring up selector, instead of booting changes disk image
+			if (row == 3)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d1);
+			debug("\nD2:");
+			if (row == 4)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d2);
+			debug("\nD3:");
+			if (row == 5)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d3);
+			debug("\nD4:");
+			if (row == 6)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d4);
+			if (row>=3 && row<7)
+			{
+				if (go==1)
+				{
+					switch (row)
+					{
+					case 3:
+						selectfile(filename_d1);
+						break;
+					case 4:
+						selectfile(filename_d2);
+						break;
+					case 5:
+						selectfile(filename_d3);
+						break;
+					case 6:
+						selectfile(filename_d4);
+						break;
+					}
+					opendrive = row-2;
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d4[i];
+						filename_d4[i] = filename_d3[i];
+						filename_d3[i] = filename_d2[i];
+						filename_d2[i] = filename_d1[i];
+						filename_d1[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==-1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d1[i];
+						filename_d1[i] = filename_d2[i];
+						filename_d2[i] = filename_d3[i];
+						filename_d3[i] = filename_d4[i];
+						filename_d4[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+			}
+			if (row == 7)
+			{
+				debugoffset(128);
+			}
+			debug("\nReboot");
+			if (row == 7)
+			{
+				if (go==1)
+				{
+					reboot = 1;
+					break;
+				}
+			}
+			if (row == 8)
+			{
+				debugoffset(128);
+			}
+			debug("\nExit");
+			if (row == 8)
+			{
+				if (go==1)
+					break;
+			}
+
+			next = 0;
+			go = 0;
+
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					row+=1;
+					if (row>8) row = 8;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					row-=1;
+					if (row<0) row = 0;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					next = 1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					next = -1;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					while(0==(*atari_trig0));
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+		}
+
+		// wait 2 seconds
+		//for (i=0; i!=2000; ++i)
+		//{
+		//	*atari_colbk = *atari_random;
+		//	wait_us(1000);
+		//}
+
+		for (i=0x040; i!=1024; i++)
+		{
+			mem[i] = store[i];
+		}
+
+		{
+			//gtia
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+		}
+		*atari_portb = store_portb;
+		initdebug(debugmode);
+
+
+		if (reboot)
+		{
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		unsigned char volatile * mem;
+
+		// TODO - disk swapping!
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		if (selectfile(filename_d1))
+		{
+			opendrive = 1;
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		initdebug(debugmode);
+		pause_6502(0);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	opendrive = 0;
+	pause_6502(1);
+
+	speed = speedslow;
+	//FIXME if (2==(2&(*zpu_switches)))
+	if (0)
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+
+		wait_us(2000000);
+	}
+
+	//FIXME if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	pause_6502(1);
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+     6b0:	ff          	im -1
+     6b1:	0b          	nop
+     6b2:	83          	im 3
+     6b3:	e0          	im -32
+     6b4:	b0          	im 48
+     6b5:	0c          	store
+
+000006b6 <.L68>:
+	do
+	{
+		mmcInit();
+     6b6:	80          	im 0
+     6b7:	cd          	im -51
+     6b8:	ba          	im 58
+     6b9:	3f          	callpcrel
+
+000006ba <.LBE2>:
+	}
+     6ba:	80          	im 0
+     6bb:	d0          	im -48
+     6bc:	be          	im 62
+     6bd:	3f          	callpcrel
+     6be:	83          	im 3
+     6bf:	e0          	im -32
+     6c0:	80          	im 0
+     6c1:	08          	load
+     6c2:	f3          	im -13
+     6c3:	38          	neqbranch
+
+000006c4 <.LM79>:
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+     6c4:	80          	im 0
+     6c5:	d3          	im -45
+     6c6:	83          	im 3
+     6c7:	3f          	callpcrel
+
+000006c8 <.LM80>:
+
+	stat = RES_OK;
+
+	return stat;
+}
+     6c8:	80          	im 0
+     6c9:	0b          	nop
+     6ca:	83          	im 3
+     6cb:	e0          	im -32
+     6cc:	80          	im 0
+     6cd:	0c          	store
+     6ce:	04          	poppc
+
+000006cf <disk_writep>:
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+     6cf:	80          	im 0
+     6d0:	3d          	pushspadd
+     6d1:	0d          	popsp
+
+000006d2 <.LM82>:
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+     6d2:	70          	loadsp 0
+     6d3:	83          	im 3
+     6d4:	e0          	im -32
+     6d5:	80          	im 0
+     6d6:	0c          	store
+     6d7:	82          	im 2
+     6d8:	3d          	pushspadd
+     6d9:	0d          	popsp
+     6da:	04          	poppc
+
+000006db <byteswap>:
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+     6db:	ff          	im -1
+     6dc:	3d          	pushspadd
+     6dd:	0d          	popsp
+     6de:	73          	loadsp 12
+
+000006df <.LM84>:
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+     6df:	70          	loadsp 0
+     6e0:	33          	loadb
+     6e1:	53          	storesp 12
+     6e2:	51          	storesp 4
+
+000006e3 <.LM85>:
+	in[0] = in[1];
+     6e3:	81          	im 1
+     6e4:	11          	addsp 4
+     6e5:	33          	loadb
+     6e6:	71          	loadsp 4
+     6e7:	34          	storeb
+
+000006e8 <.LM86>:
+	in[1] = temp;
+     6e8:	71          	loadsp 4
+     6e9:	81          	im 1
+     6ea:	12          	addsp 8
+     6eb:	34          	storeb
+     6ec:	83          	im 3
+     6ed:	3d          	pushspadd
+     6ee:	0d          	popsp
+     6ef:	04          	poppc
+
+000006f0 <get_checksum>:
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+	char const * default_filename = "BOOT.ATR";
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	for (i=0;i!=15;++i)
+	{
+		filename_d1[i] = default_filename[i];
+		filename_d2[i] = default_filename[i];
+		filename_d3[i] = default_filename[i];
+		filename_d4[i] = default_filename[i];
+		if (default_filename[i] == 0) break;
+	}
+	opendrive = 1;
+	openfile(filename_d1);
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		/*FIXME if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}*/
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId >= 0x31 && command.deviceId < 0x34)
+ 	 	{
+			int sent = 0;
+			int drive = 0;
+
+			drive = command.deviceId&0xf;
+			if (drive!=opendrive)
+			{
+				opendrive = drive;
+				switch(drive)
+				{
+				case 1:
+					openfile(filename_d1);
+					break;
+				case 2:
+					openfile(filename_d2);
+					break;
+				case 3:
+					openfile(filename_d3);
+					break;
+				case 4:
+					openfile(filename_d4);
+					break;
+				}
+			}
+
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+     6f0:	fb          	im -5
+     6f1:	3d          	pushspadd
+     6f2:	0d          	popsp
+     6f3:	77          	loadsp 28
+     6f4:	02          	pushsp
+     6f5:	84          	im 4
+     6f6:	05          	add
+     6f7:	a2          	im 34
+     6f8:	05          	add
+     6f9:	22          	loadh
+     6fa:	56          	storesp 24
+     6fb:	56          	storesp 24
+
+000006fc <.LM88>:
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+     6fc:	80          	im 0
+     6fd:	70          	loadsp 0
+
+000006fe <.LM89>:
+	for(i=0;i<len;i++)
+     6fe:	71          	loadsp 4
+     6ff:	55          	storesp 20
+     700:	55          	storesp 20
+     701:	52          	storesp 8
+     702:	71          	loadsp 4
+     703:	75          	loadsp 20
+     704:	27          	ulessthanorequal
+     705:	ac          	im 44
+     706:	38          	neqbranch
+
+00000707 <.L83>:
+	{
+		sum+=buffer[i];
+     707:	75          	loadsp 20
+     708:	13          	addsp 12
+     709:	70          	loadsp 0
+     70a:	33          	loadb
+     70b:	70          	loadsp 0
+     70c:	14          	addsp 16
+     70d:	70          	loadsp 0
+     70e:	81          	im 1
+     70f:	ff          	im -1
+     710:	06          	and
+     711:	55          	storesp 20
+     712:	51          	storesp 4
+     713:	51          	storesp 4
+     714:	51          	storesp 4
+
+00000715 <.LM91>:
+		if(sum<sumo) sum++;
+     715:	71          	loadsp 4
+     716:	74          	loadsp 16
+     717:	27          	ulessthanorequal
+     718:	89          	im 9
+     719:	38          	neqbranch
+     71a:	81          	im 1
+     71b:	12          	addsp 8
+     71c:	70          	loadsp 0
+     71d:	81          	im 1
+     71e:	ff          	im -1
+     71f:	06          	and
+     720:	53          	storesp 12
+     721:	51          	storesp 4
+
+00000722 <.L82>:
+		sumo = sum;
+     722:	71          	loadsp 4
+
+00000723 <.LM93>:
+     723:	81          	im 1
+     724:	14          	addsp 16
+     725:	70          	loadsp 0
+     726:	83          	im 3
+     727:	ff          	im -1
+     728:	ff          	im -1
+     729:	06          	and
+     72a:	55          	storesp 20
+     72b:	52          	storesp 8
+     72c:	54          	storesp 16
+     72d:	74          	loadsp 16
+     72e:	73          	loadsp 12
+     72f:	26          	ulessthan
+     730:	d6          	im -42
+     731:	38          	neqbranch
+
+00000732 <.L85>:
+	}
+	return sum;
+}
+     732:	71          	loadsp 4
+     733:	83          	im 3
+     734:	e0          	im -32
+     735:	80          	im 0
+     736:	0c          	store
+     737:	87          	im 7
+     738:	3d          	pushspadd
+     739:	0d          	popsp
+     73a:	04          	poppc
+
+0000073b <openfile>:
+     73b:	f8          	im -8
+     73c:	3d          	pushspadd
+     73d:	0d          	popsp
+     73e:	7a          	loadsp 40
+     73f:	57          	storesp 28
+
+00000740 <.LM96>:
+     740:	80          	im 0
+     741:	0b          	nop
+     742:	8a          	im 10
+     743:	3d          	pushspadd
+     744:	23          	storeh
+
+00000745 <.LM97>:
+     745:	80          	im 0
+
+00000746 <.LM98>:
+     746:	70          	loadsp 0
+
+00000747 <.LM99>:
+     747:	71          	loadsp 4
+     748:	83          	im 3
+     749:	e2          	im -30
+     74a:	e4          	im -28
+     74b:	0c          	store
+
+0000074c <.LM100>:
+     74c:	0b          	nop
+     74d:	0b          	nop
+     74e:	80          	im 0
+     74f:	f5          	im -11
+     750:	80          	im 0
+     751:	53          	storesp 12
+     752:	57          	storesp 28
+     753:	58          	storesp 32
+     754:	80          	im 0
+     755:	d9          	im -39
+     756:	96          	im 22
+     757:	3f          	callpcrel
+
+00000758 <.LM101>:
+     758:	76          	loadsp 24
+     759:	51          	storesp 4
+     75a:	80          	im 0
+     75b:	d9          	im -39
+     75c:	90          	im 16
+     75d:	3f          	callpcrel
+
+0000075e <.LM102>:
+     75e:	0b          	nop
+     75f:	0b          	nop
+     760:	80          	im 0
+     761:	f9          	im -7
+     762:	b8          	im 56
+     763:	51          	storesp 4
+     764:	80          	im 0
+     765:	d9          	im -39
+     766:	86          	im 6
+     767:	3f          	callpcrel
+
+00000768 <.LM103>:
+     768:	76          	loadsp 24
+     769:	51          	storesp 4
+     76a:	80          	im 0
+     76b:	c1          	im -63
+     76c:	c8          	im -56
+     76d:	3f          	callpcrel
+     76e:	83          	im 3
+     76f:	e0          	im -32
+     770:	80          	im 0
+     771:	08          	load
+     772:	78          	loadsp 32
+     773:	2e          	eq
+     774:	8f          	im 15
+     775:	38          	neqbranch
+
+00000776 <.LM104>:
+     776:	0b          	nop
+     777:	0b          	nop
+     778:	80          	im 0
+     779:	f5          	im -11
+     77a:	8c          	im 12
+     77b:	51          	storesp 4
+
+0000077c <.LM105>:
+     77c:	80          	im 0
+     77d:	d8          	im -40
+     77e:	ee          	im -18
+     77f:	3f          	callpcrel
+
+00000780 <.L87>:
+     780:	8a          	im 10
+     781:	3d          	pushspadd
+     782:	0d          	popsp
+     783:	04          	poppc
+
+00000784 <.L88>:
+     784:	0b          	nop
+     785:	0b          	nop
+     786:	80          	im 0
+     787:	f5          	im -11
+     788:	94          	im 20
+     789:	51          	storesp 4
+     78a:	80          	im 0
+     78b:	d8          	im -40
+     78c:	e0          	im -32
+     78d:	3f          	callpcrel
+
+0000078e <.L89>:
+     78e:	75          	loadsp 20
+     78f:	17          	addsp 28
+     790:	70          	loadsp 0
+     791:	33          	loadb
+     792:	55          	storesp 20
+     793:	55          	storesp 20
+     794:	73          	loadsp 12
+     795:	80          	im 0
+     796:	2e          	eq
+     797:	80          	im 0
+     798:	fd          	im -3
+     799:	38          	neqbranch
+
+0000079a <.LM109>:
+     79a:	73          	loadsp 12
+     79b:	ae          	im 46
+     79c:	2e          	eq
+     79d:	86          	im 6
+     79e:	38          	neqbranch
+
+0000079f <.LM110>:
+     79f:	81          	im 1
+     7a0:	16          	addsp 24
+     7a1:	56          	storesp 24
+     7a2:	eb          	im -21
+     7a3:	39          	poppcrel
+
+000007a4 <.L92>:
+     7a4:	80          	im 0
+     7a5:	0b          	nop
+     7a6:	81          	im 1
+     7a7:	16          	addsp 24
+     7a8:	33          	loadb
+     7a9:	55          	storesp 20
+     7aa:	56          	storesp 24
+     7ab:	73          	loadsp 12
+     7ac:	80          	im 0
+     7ad:	d8          	im -40
+     7ae:	2e          	eq
+     7af:	09          	not
+     7b0:	81          	im 1
+     7b1:	06          	and
+     7b2:	83          	im 3
+     7b3:	38          	neqbranch
+     7b4:	81          	im 1
+     7b5:	56          	storesp 24
+
+000007b6 <.L94>:
+     7b6:	73          	loadsp 12
+     7b7:	80          	im 0
+     7b8:	f8          	im -8
+     7b9:	32          	xor
+     7ba:	70          	loadsp 0
+     7bb:	30          	neg
+     7bc:	70          	loadsp 0
+     7bd:	80          	im 0
+     7be:	25          	lessthanorequal
+     7bf:	78          	loadsp 32
+     7c0:	07          	or
+     7c1:	51          	storesp 4
+     7c2:	51          	storesp 4
+     7c3:	54          	storesp 16
+     7c4:	73          	loadsp 12
+     7c5:	80          	im 0
+     7c6:	2e          	eq
+     7c7:	80          	im 0
+     7c8:	cd          	im -51
+     7c9:	38          	neqbranch
+
+000007ca <.LM112>:
+     7ca:	80          	im 0
+     7cb:	0b          	nop
+     7cc:	82          	im 2
+     7cd:	16          	addsp 24
+     7ce:	33          	loadb
+     7cf:	55          	storesp 20
+     7d0:	56          	storesp 24
+     7d1:	73          	loadsp 12
+     7d2:	80          	im 0
+     7d3:	c6          	im -58
+     7d4:	2e          	eq
+     7d5:	09          	not
+     7d6:	81          	im 1
+     7d7:	06          	and
+     7d8:	83          	im 3
+     7d9:	38          	neqbranch
+     7da:	81          	im 1
+     7db:	56          	storesp 24
+
+000007dc <.L97>:
+     7dc:	73          	loadsp 12
+     7dd:	80          	im 0
+     7de:	e6          	im -26
+     7df:	32          	xor
+     7e0:	70          	loadsp 0
+     7e1:	30          	neg
+     7e2:	70          	loadsp 0
+     7e3:	80          	im 0
+     7e4:	25          	lessthanorequal
+     7e5:	78          	loadsp 32
+     7e6:	07          	or
+     7e7:	51          	storesp 4
+     7e8:	51          	storesp 4
+     7e9:	54          	storesp 16
+     7ea:	73          	loadsp 12
+     7eb:	80          	im 0
+     7ec:	2e          	eq
+     7ed:	a8          	im 40
+     7ee:	38          	neqbranch
+
+000007ef <.LM113>:
+     7ef:	80          	im 0
+     7f0:	0b          	nop
+     7f1:	83          	im 3
+     7f2:	16          	addsp 24
+     7f3:	33          	loadb
+     7f4:	55          	storesp 20
+     7f5:	56          	storesp 24
+     7f6:	73          	loadsp 12
+     7f7:	80          	im 0
+     7f8:	c4          	im -60
+     7f9:	2e          	eq
+     7fa:	09          	not
+     7fb:	81          	im 1
+     7fc:	06          	and
+     7fd:	83          	im 3
+     7fe:	38          	neqbranch
+     7ff:	81          	im 1
+     800:	56          	storesp 24
+
+00000801 <.L100>:
+     801:	73          	loadsp 12
+     802:	80          	im 0
+     803:	e4          	im -28
+     804:	32          	xor
+     805:	70          	loadsp 0
+     806:	30          	neg
+     807:	70          	loadsp 0
+     808:	80          	im 0
+     809:	25          	lessthanorequal
+     80a:	78          	loadsp 32
+     80b:	07          	or
+     80c:	51          	storesp 4
+     80d:	51          	storesp 4
+     80e:	54          	storesp 16
+     80f:	73          	loadsp 12
+     810:	80          	im 0
+     811:	2e          	eq
+     812:	83          	im 3
+     813:	38          	neqbranch
+
+00000814 <.LM114>:
+     814:	81          	im 1
+     815:	58          	storesp 32
+
+00000816 <.L90>:
+     816:	80          	im 0
+     817:	0b          	nop
+     818:	8a          	im 10
+     819:	3d          	pushspadd
+     81a:	23          	storeh
+
+0000081b <.LM116>:
+     81b:	8a          	im 10
+     81c:	3d          	pushspadd
+     81d:	fc          	im -4
+     81e:	05          	add
+     81f:	53          	storesp 12
+     820:	90          	im 16
+     821:	52          	storesp 8
+     822:	83          	im 3
+     823:	e2          	im -30
+     824:	e8          	im -24
+     825:	51          	storesp 4
+     826:	80          	im 0
+     827:	c1          	im -63
+     828:	cc          	im -52
+     829:	3f          	callpcrel
+
+0000082a <.LM117>:
+     82a:	89          	im 9
+     82b:	3d          	pushspadd
+     82c:	22          	loadh
+     82d:	55          	storesp 20
+     82e:	74          	loadsp 16
+     82f:	90          	im 16
+     830:	2e          	eq
+     831:	8e          	im 14
+     832:	38          	neqbranch
+
+00000833 <.LM118>:
+     833:	0b          	nop
+     834:	0b          	nop
+     835:	80          	im 0
+     836:	f5          	im -11
+     837:	98          	im 24
+     838:	51          	storesp 4
+
+00000839 <.LM119>:
+     839:	80          	im 0
+     83a:	d7          	im -41
+     83b:	b1          	im 49
+     83c:	3f          	callpcrel
+     83d:	fe          	im -2
+     83e:	c1          	im -63
+     83f:	39          	poppcrel
+
+00000840 <.L102>:
+     840:	83          	im 3
+     841:	e2          	im -30
+     842:	e8          	im -24
+     843:	51          	storesp 4
+     844:	fd          	im -3
+     845:	95          	im 21
+     846:	3f          	callpcrel
+
+00000847 <.LM121>:
+     847:	83          	im 3
+     848:	e2          	im -30
+     849:	ea          	im -22
+     84a:	51          	storesp 4
+     84b:	fd          	im -3
+     84c:	8e          	im 14
+     84d:	3f          	callpcrel
+
+0000084e <.LM122>:
+     84e:	83          	im 3
+     84f:	e2          	im -30
+     850:	ec          	im -20
+     851:	51          	storesp 4
+     852:	fd          	im -3
+     853:	87          	im 7
+     854:	3f          	callpcrel
+
+00000855 <.LM123>:
+     855:	80          	im 0
+     856:	0b          	nop
+     857:	83          	im 3
+     858:	e3          	im -29
+     859:	88          	im 8
+     85a:	0c          	store
+
+0000085b <.LM124>:
+     85b:	77          	loadsp 28
+     85c:	81          	im 1
+     85d:	2e          	eq
+     85e:	81          	im 1
+     85f:	8c          	im 12
+     860:	38          	neqbranch
+
+00000861 <.LM125>:
+     861:	83          	im 3
+     862:	e2          	im -30
+     863:	e8          	im -24
+     864:	33          	loadb
+     865:	83          	im 3
+     866:	e2          	im -30
+     867:	e9          	im -23
+     868:	33          	loadb
+     869:	71          	loadsp 4
+     86a:	88          	im 8
+     86b:	2b          	ashiftleft
+     86c:	07          	or
+     86d:	55          	storesp 20
+     86e:	56          	storesp 24
+     86f:	73          	loadsp 12
+     870:	83          	im 3
+     871:	ff          	im -1
+     872:	ff          	im -1
+     873:	2e          	eq
+     874:	82          	im 2
+     875:	ce          	im -50
+     876:	38          	neqbranch
+
+00000877 <.LM126>:
+     877:	73          	loadsp 12
+     878:	85          	im 5
+     879:	96          	im 22
+     87a:	2e          	eq
+     87b:	8e          	im 14
+     87c:	38          	neqbranch
+
+0000087d <.LM127>:
+     87d:	0b          	nop
+     87e:	0b          	nop
+     87f:	80          	im 0
+     880:	f5          	im -11
+     881:	b0          	im 48
+     882:	51          	storesp 4
+
+00000883 <.LM128>:
+     883:	80          	im 0
+     884:	d6          	im -42
+     885:	e7          	im -25
+     886:	3f          	callpcrel
+     887:	fd          	im -3
+     888:	f7          	im -9
+     889:	39          	poppcrel
+
+0000088a <.L131>:
+     88a:	0b          	nop
+     88b:	0b          	nop
+     88c:	80          	im 0
+     88d:	f5          	im -11
+     88e:	c4          	im -60
+     88f:	51          	storesp 4
+     890:	80          	im 0
+     891:	d6          	im -42
+     892:	da          	im -38
+     893:	3f          	callpcrel
+
+00000894 <.LM130>:
+     894:	74          	loadsp 16
+     895:	83          	im 3
+     896:	e3          	im -29
+     897:	90          	im 16
+     898:	0c          	store
+
+00000899 <.L105>:
+     899:	83          	im 3
+     89a:	e2          	im -30
+     89b:	ec          	im -20
+     89c:	33          	loadb
+     89d:	83          	im 3
+     89e:	e2          	im -30
+     89f:	ed          	im -19
+     8a0:	33          	loadb
+     8a1:	71          	loadsp 4
+     8a2:	88          	im 8
+     8a3:	2b          	ashiftleft
+     8a4:	07          	or
+     8a5:	55          	storesp 20
+     8a6:	55          	storesp 20
+     8a7:	73          	loadsp 12
+     8a8:	81          	im 1
+     8a9:	80          	im 0
+     8aa:	2e          	eq
+     8ab:	81          	im 1
+     8ac:	d3          	im -45
+     8ad:	38          	neqbranch
+
+000008ae <.LM132>:
+     8ae:	73          	loadsp 12
+     8af:	82          	im 2
+     8b0:	80          	im 0
+     8b1:	2e          	eq
+     8b2:	84          	im 4
+     8b3:	81          	im 1
+     8b4:	38          	neqbranch
+
+000008b5 <.LM133>:
+     8b5:	73          	loadsp 12
+     8b6:	81          	im 1
+     8b7:	ff          	im -1
+     8b8:	26          	ulessthan
+     8b9:	81          	im 1
+     8ba:	b8          	im 56
+     8bb:	38          	neqbranch
+
+000008bc <.LM134>:
+     8bc:	0b          	nop
+     8bd:	0b          	nop
+     8be:	80          	im 0
+     8bf:	f5          	im -11
+     8c0:	cc          	im -52
+     8c1:	51          	storesp 4
+     8c2:	80          	im 0
+     8c3:	d6          	im -42
+     8c4:	a8          	im 40
+     8c5:	3f          	callpcrel
+
+000008c6 <.LM135>:
+     8c6:	83          	im 3
+     8c7:	e2          	im -30
+     8c8:	ea          	im -22
+     8c9:	33          	loadb
+     8ca:	83          	im 3
+     8cb:	e2          	im -30
+     8cc:	eb          	im -21
+     8cd:	33          	loadb
+     8ce:	71          	loadsp 4
+     8cf:	88          	im 8
+     8d0:	2b          	ashiftleft
+     8d1:	07          	or
+     8d2:	52          	storesp 8
+     8d3:	56          	storesp 24
+     8d4:	80          	im 0
+     8d5:	d7          	im -41
+     8d6:	a5          	im 37
+     8d7:	3f          	callpcrel
+
+000008d8 <.LM136>:
+     8d8:	0b          	nop
+     8d9:	0b          	nop
+     8da:	80          	im 0
+     8db:	f5          	im -11
+     8dc:	d0          	im -48
+     8dd:	51          	storesp 4
+     8de:	80          	im 0
+     8df:	d6          	im -42
+     8e0:	8c          	im 12
+     8e1:	3f          	callpcrel
+
+000008e2 <.LM137>:
+     8e2:	81          	im 1
+     8e3:	0b          	nop
+     8e4:	83          	im 3
+     8e5:	e2          	im -30
+     8e6:	e4          	im -28
+     8e7:	0c          	store
+
+000008e8 <.L135>:
+     8e8:	8a          	im 10
+     8e9:	3d          	pushspadd
+     8ea:	0d          	popsp
+     8eb:	04          	poppc
+
+000008ec <.L129>:
+     8ec:	0b          	nop
+     8ed:	0b          	nop
+     8ee:	80          	im 0
+     8ef:	f5          	im -11
+     8f0:	d4          	im -44
+     8f1:	51          	storesp 4
+     8f2:	80          	im 0
+     8f3:	d5          	im -43
+     8f4:	f8          	im -8
+     8f5:	3f          	callpcrel
+
+000008f6 <.LM140>:
+     8f6:	80          	im 0
+     8f7:	0b          	nop
+     8f8:	83          	im 3
+     8f9:	e3          	im -29
+     8fa:	90          	im 16
+     8fb:	0c          	store
+
+000008fc <.LM141>:
+     8fc:	82          	im 2
+     8fd:	0b          	nop
+     8fe:	83          	im 3
+     8ff:	e2          	im -30
+     900:	e8          	im -24
+     901:	34          	storeb
+     902:	ff          	im -1
+     903:	96          	im 22
+     904:	0b          	nop
+     905:	83          	im 3
+     906:	e2          	im -30
+     907:	e9          	im -23
+     908:	34          	storeb
+
+00000909 <.LM142>:
+     909:	76          	loadsp 24
+     90a:	51          	storesp 4
+     90b:	f7          	im -9
+     90c:	d2          	im -46
+     90d:	3f          	callpcrel
+     90e:	83          	im 3
+     90f:	e0          	im -32
+     910:	80          	im 0
+     911:	08          	load
+     912:	54          	storesp 16
+     913:	80          	im 0
+     914:	0b          	nop
+     915:	83          	im 3
+     916:	e0          	im -32
+     917:	80          	im 0
+     918:	08          	load
+     919:	24          	lessthan
+     91a:	a9          	im 41
+     91b:	38          	neqbranch
+     91c:	73          	loadsp 12
+     91d:	84          	im 4
+     91e:	2c          	ashiftright
+     91f:	70          	loadsp 0
+     920:	83          	im 3
+     921:	ff          	im -1
+     922:	ff          	im -1
+     923:	06          	and
+     924:	70          	loadsp 0
+     925:	88          	im 8
+     926:	2a          	lshiftright
+     927:	57          	storesp 28
+     928:	51          	storesp 4
+     929:	54          	storesp 16
+     92a:	74          	loadsp 16
+     92b:	83          	im 3
+     92c:	e2          	im -30
+     92d:	ea          	im -22
+     92e:	34          	storeb
+     92f:	73          	loadsp 12
+     930:	83          	im 3
+     931:	e2          	im -30
+     932:	eb          	im -21
+     933:	34          	storeb
+
+00000934 <.LM143>:
+     934:	80          	im 0
+     935:	0b          	nop
+     936:	83          	im 3
+     937:	e2          	im -30
+     938:	ec          	im -20
+     939:	34          	storeb
+     93a:	ff          	im -1
+     93b:	80          	im 0
+     93c:	0b          	nop
+     93d:	83          	im 3
+     93e:	e2          	im -30
+     93f:	ed          	im -19
+     940:	34          	storeb
+     941:	fe          	im -2
+     942:	d6          	im -42
+     943:	39          	poppcrel
+
+00000944 <.L134>:
+     944:	83          	im 3
+     945:	e0          	im -32
+     946:	80          	im 0
+     947:	08          	load
+     948:	8f          	im 15
+     949:	05          	add
+     94a:	70          	loadsp 0
+     94b:	84          	im 4
+     94c:	2c          	ashiftright
+     94d:	70          	loadsp 0
+     94e:	83          	im 3
+     94f:	ff          	im -1
+     950:	ff          	im -1
+     951:	06          	and
+     952:	70          	loadsp 0
+     953:	88          	im 8
+     954:	2a          	lshiftright
+     955:	58          	storesp 32
+     956:	51          	storesp 4
+     957:	51          	storesp 4
+     958:	54          	storesp 16
+     959:	74          	loadsp 16
+     95a:	83          	im 3
+     95b:	e2          	im -30
+     95c:	ea          	im -22
+     95d:	34          	storeb
+     95e:	73          	loadsp 12
+     95f:	83          	im 3
+     960:	e2          	im -30
+     961:	eb          	im -21
+     962:	34          	storeb
+
+00000963 <.LM145>:
+     963:	80          	im 0
+     964:	0b          	nop
+     965:	83          	im 3
+     966:	e2          	im -30
+     967:	ec          	im -20
+     968:	34          	storeb
+     969:	ff          	im -1
+     96a:	80          	im 0
+     96b:	0b          	nop
+     96c:	83          	im 3
+     96d:	e2          	im -30
+     96e:	ed          	im -19
+     96f:	34          	storeb
+     970:	fe          	im -2
+     971:	a7          	im 39
+     972:	39          	poppcrel
+
+00000973 <.L121>:
+     973:	0b          	nop
+     974:	0b          	nop
+     975:	80          	im 0
+     976:	f5          	im -11
+     977:	dc          	im -36
+     978:	51          	storesp 4
+     979:	80          	im 0
+     97a:	d4          	im -44
+     97b:	f1          	im -15
+     97c:	3f          	callpcrel
+     97d:	fc          	im -4
+     97e:	81          	im 1
+     97f:	39          	poppcrel
+
+00000980 <.L132>:
+     980:	83          	im 3
+     981:	e2          	im -30
+     982:	ea          	im -22
+     983:	33          	loadb
+     984:	83          	im 3
+     985:	e2          	im -30
+     986:	eb          	im -21
+     987:	33          	loadb
+     988:	71          	loadsp 4
+     989:	88          	im 8
+     98a:	2b          	ashiftleft
+     98b:	07          	or
+     98c:	55          	storesp 20
+     98d:	58          	storesp 32
+     98e:	ad          	im 45
+     98f:	80          	im 0
+     990:	74          	loadsp 16
+     991:	27          	ulessthanorequal
+     992:	81          	im 1
+     993:	f2          	im -14
+     994:	38          	neqbranch
+
+00000995 <.LM148>:
+     995:	0b          	nop
+     996:	0b          	nop
+     997:	80          	im 0
+     998:	f5          	im -11
+     999:	ec          	im -20
+     99a:	51          	storesp 4
+
+0000099b <.LM149>:
+     99b:	80          	im 0
+     99c:	d4          	im -44
+     99d:	cf          	im -49
+     99e:	3f          	callpcrel
+
+0000099f <.LM150>:
+     99f:	83          	im 3
+     9a0:	e2          	im -30
+     9a1:	ea          	im -22
+     9a2:	33          	loadb
+     9a3:	83          	im 3
+     9a4:	e2          	im -30
+     9a5:	eb          	im -21
+     9a6:	33          	loadb
+     9a7:	71          	loadsp 4
+     9a8:	88          	im 8
+     9a9:	2b          	ashiftleft
+     9aa:	07          	or
+     9ab:	52          	storesp 8
+     9ac:	56          	storesp 24
+     9ad:	80          	im 0
+     9ae:	d5          	im -43
+     9af:	cc          	im -52
+     9b0:	3f          	callpcrel
+
+000009b1 <.LM151>:
+     9b1:	0b          	nop
+     9b2:	0b          	nop
+     9b3:	80          	im 0
+     9b4:	f5          	im -11
+     9b5:	d0          	im -48
+     9b6:	51          	storesp 4
+     9b7:	80          	im 0
+     9b8:	d4          	im -44
+     9b9:	b3          	im 51
+     9ba:	3f          	callpcrel
+
+000009bb <.LM152>:
+     9bb:	81          	im 1
+     9bc:	0b          	nop
+     9bd:	83          	im 3
+     9be:	e2          	im -30
+     9bf:	e4          	im -28
+     9c0:	0c          	store
+     9c1:	fe          	im -2
+     9c2:	a5          	im 37
+     9c3:	39          	poppcrel
+
+000009c4 <.L130>:
+     9c4:	0b          	nop
+     9c5:	0b          	nop
+     9c6:	80          	im 0
+     9c7:	f5          	im -11
+     9c8:	f0          	im -16
+     9c9:	51          	storesp 4
+     9ca:	80          	im 0
+     9cb:	d4          	im -44
+     9cc:	a0          	im 32
+     9cd:	3f          	callpcrel
+
+000009ce <.LM154>:
+     9ce:	fe          	im -2
+     9cf:	80          	im 0
+     9d0:	0b          	nop
+     9d1:	83          	im 3
+     9d2:	e3          	im -29
+     9d3:	90          	im 16
+     9d4:	0c          	store
+
+000009d5 <.LM155>:
+     9d5:	81          	im 1
+     9d6:	0b          	nop
+     9d7:	83          	im 3
+     9d8:	e3          	im -29
+     9d9:	88          	im 8
+     9da:	0c          	store
+
+000009db <.LM156>:
+     9db:	ff          	im -1
+     9dc:	0b          	nop
+     9dd:	83          	im 3
+     9de:	e2          	im -30
+     9df:	e8          	im -24
+     9e0:	34          	storeb
+     9e1:	ff          	im -1
+     9e2:	0b          	nop
+     9e3:	83          	im 3
+     9e4:	e2          	im -30
+     9e5:	e9          	im -23
+     9e6:	34          	storeb
+
+000009e7 <.LM157>:
+     9e7:	76          	loadsp 24
+     9e8:	51          	storesp 4
+     9e9:	f5          	im -11
+     9ea:	f4          	im -12
+     9eb:	3f          	callpcrel
+     9ec:	83          	im 3
+     9ed:	e0          	im -32
+     9ee:	80          	im 0
+     9ef:	08          	load
+     9f0:	83          	im 3
+     9f1:	e3          	im -29
+     9f2:	94          	im 20
+     9f3:	0c          	store
+
+000009f4 <.LM158>:
+     9f4:	83          	im 3
+     9f5:	e0          	im -32
+     9f6:	80          	im 0
+     9f7:	08          	load
+     9f8:	54          	storesp 16
+     9f9:	80          	im 0
+     9fa:	0b          	nop
+     9fb:	83          	im 3
+     9fc:	e0          	im -32
+     9fd:	80          	im 0
+     9fe:	08          	load
+     9ff:	24          	lessthan
+     a00:	80          	im 0
+     a01:	d3          	im -45
+     a02:	38          	neqbranch
+     a03:	73          	loadsp 12
+     a04:	84          	im 4
+     a05:	2c          	ashiftright
+     a06:	70          	loadsp 0
+     a07:	83          	im 3
+     a08:	ff          	im -1
+     a09:	ff          	im -1
+     a0a:	06          	and
+     a0b:	70          	loadsp 0
+     a0c:	88          	im 8
+     a0d:	2a          	lshiftright
+     a0e:	57          	storesp 28
+     a0f:	51          	storesp 4
+     a10:	54          	storesp 16
+     a11:	74          	loadsp 16
+     a12:	83          	im 3
+     a13:	e2          	im -30
+     a14:	ea          	im -22
+     a15:	34          	storeb
+     a16:	73          	loadsp 12
+     a17:	83          	im 3
+     a18:	e2          	im -30
+     a19:	eb          	im -21
+     a1a:	34          	storeb
+
+00000a1b <.LM159>:
+     a1b:	80          	im 0
+     a1c:	0b          	nop
+     a1d:	83          	im 3
+     a1e:	e2          	im -30
+     a1f:	ec          	im -20
+     a20:	34          	storeb
+     a21:	ff          	im -1
+     a22:	80          	im 0
+     a23:	0b          	nop
+     a24:	83          	im 3
+     a25:	e2          	im -30
+     a26:	ed          	im -19
+     a27:	34          	storeb
+
+00000a28 <.LM160>:
+     a28:	80          	im 0
+     a29:	55          	storesp 20
+
+00000a2a <.L111>:
+     a2a:	74          	loadsp 16
+     a2b:	17          	addsp 28
+     a2c:	54          	storesp 16
+     a2d:	73          	loadsp 12
+     a2e:	33          	loadb
+     a2f:	83          	im 3
+     a30:	e2          	im -30
+     a31:	d8          	im -40
+     a32:	16          	addsp 24
+     a33:	34          	storeb
+
+00000a34 <.LM162>:
+     a34:	81          	im 1
+     a35:	15          	addsp 20
+     a36:	55          	storesp 20
+     a37:	74          	loadsp 16
+     a38:	8c          	im 12
+     a39:	2e          	eq
+     a3a:	fc          	im -4
+     a3b:	dd          	im -35
+     a3c:	38          	neqbranch
+
+00000a3d <.LM163>:
+     a3d:	74          	loadsp 16
+     a3e:	17          	addsp 28
+     a3f:	54          	storesp 16
+     a40:	73          	loadsp 12
+     a41:	33          	loadb
+     a42:	83          	im 3
+     a43:	e2          	im -30
+     a44:	d8          	im -40
+     a45:	16          	addsp 24
+     a46:	34          	storeb
+
+00000a47 <.LM164>:
+     a47:	81          	im 1
+     a48:	15          	addsp 20
+     a49:	55          	storesp 20
+     a4a:	74          	loadsp 16
+     a4b:	8c          	im 12
+     a4c:	2e          	eq
+     a4d:	09          	not
+     a4e:	81          	im 1
+     a4f:	06          	and
+     a50:	d9          	im -39
+     a51:	38          	neqbranch
+     a52:	fc          	im -4
+     a53:	c5          	im -59
+     a54:	39          	poppcrel
+
+00000a55 <.L136>:
+     a55:	83          	im 3
+     a56:	e0          	im -32
+     a57:	80          	im 0
+     a58:	08          	load
+     a59:	8f          	im 15
+     a5a:	05          	add
+     a5b:	70          	loadsp 0
+     a5c:	84          	im 4
+     a5d:	2c          	ashiftright
+     a5e:	70          	loadsp 0
+     a5f:	83          	im 3
+     a60:	ff          	im -1
+     a61:	ff          	im -1
+     a62:	06          	and
+     a63:	70          	loadsp 0
+     a64:	88          	im 8
+     a65:	2a          	lshiftright
+     a66:	58          	storesp 32
+     a67:	51          	storesp 4
+     a68:	51          	storesp 4
+     a69:	54          	storesp 16
+     a6a:	74          	loadsp 16
+     a6b:	83          	im 3
+     a6c:	e2          	im -30
+     a6d:	ea          	im -22
+     a6e:	34          	storeb
+     a6f:	73          	loadsp 12
+     a70:	83          	im 3
+     a71:	e2          	im -30
+     a72:	eb          	im -21
+     a73:	34          	storeb
+
+00000a74 <.LM166>:
+     a74:	80          	im 0
+     a75:	0b          	nop
+     a76:	83          	im 3
+     a77:	e2          	im -30
+     a78:	ec          	im -20
+     a79:	34          	storeb
+     a7a:	ff          	im -1
+     a7b:	80          	im 0
+     a7c:	0b          	nop
+     a7d:	83          	im 3
+     a7e:	e2          	im -30
+     a7f:	ed          	im -19
+     a80:	34          	storeb
+
+00000a81 <.LM167>:
+     a81:	80          	im 0
+     a82:	55          	storesp 20
+     a83:	ff          	im -1
+     a84:	a5          	im 37
+     a85:	39          	poppcrel
+
+00000a86 <.L116>:
+     a86:	0b          	nop
+     a87:	0b          	nop
+     a88:	80          	im 0
+     a89:	f5          	im -11
+     a8a:	f8          	im -8
+     a8b:	51          	storesp 4
+
+00000a8c <.LM169>:
+     a8c:	80          	im 0
+     a8d:	d2          	im -46
+     a8e:	de          	im -34
+     a8f:	3f          	callpcrel
+
+00000a90 <.LM170>:
+     a90:	83          	im 3
+     a91:	e2          	im -30
+     a92:	ea          	im -22
+     a93:	33          	loadb
+     a94:	83          	im 3
+     a95:	e2          	im -30
+     a96:	eb          	im -21
+     a97:	33          	loadb
+     a98:	71          	loadsp 4
+     a99:	88          	im 8
+     a9a:	2b          	ashiftleft
+     a9b:	07          	or
+     a9c:	52          	storesp 8
+     a9d:	56          	storesp 24
+     a9e:	80          	im 0
+     a9f:	d3          	im -45
+     aa0:	db          	im -37
+     aa1:	3f          	callpcrel
+
+00000aa2 <.LM171>:
+     aa2:	0b          	nop
+     aa3:	0b          	nop
+     aa4:	80          	im 0
+     aa5:	f5          	im -11
+     aa6:	d0          	im -48
+     aa7:	51          	storesp 4
+     aa8:	80          	im 0
+     aa9:	d2          	im -46
+     aaa:	c2          	im -62
+     aab:	3f          	callpcrel
+
+00000aac <.LM172>:
+     aac:	81          	im 1
+     aad:	0b          	nop
+     aae:	83          	im 3
+     aaf:	e2          	im -30
+     ab0:	e4          	im -28
+     ab1:	0c          	store
+     ab2:	fc          	im -4
+     ab3:	b4          	im 52
+     ab4:	39          	poppcrel
+
+00000ab5 <.L133>:
+     ab5:	0b          	nop
+     ab6:	0b          	nop
+     ab7:	80          	im 0
+     ab8:	f5          	im -11
+     ab9:	fc          	im -4
+     aba:	51          	storesp 4
+
+00000abb <.LM174>:
+     abb:	80          	im 0
+     abc:	d2          	im -46
+     abd:	af          	im 47
+     abe:	3f          	callpcrel
+
+00000abf <.LM175>:
+     abf:	83          	im 3
+     ac0:	e2          	im -30
+     ac1:	ea          	im -22
+     ac2:	33          	loadb
+     ac3:	83          	im 3
+     ac4:	e2          	im -30
+     ac5:	eb          	im -21
+     ac6:	33          	loadb
+     ac7:	71          	loadsp 4
+     ac8:	88          	im 8
+     ac9:	2b          	ashiftleft
+     aca:	07          	or
+     acb:	52          	storesp 8
+     acc:	56          	storesp 24
+     acd:	80          	im 0
+     ace:	d3          	im -45
+     acf:	ac          	im 44
+     ad0:	3f          	callpcrel
+
+00000ad1 <.LM176>:
+     ad1:	0b          	nop
+     ad2:	0b          	nop
+     ad3:	80          	im 0
+     ad4:	f5          	im -11
+     ad5:	d0          	im -48
+     ad6:	51          	storesp 4
+     ad7:	80          	im 0
+     ad8:	d2          	im -46
+     ad9:	93          	im 19
+     ada:	3f          	callpcrel
+
+00000adb <.LM177>:
+     adb:	81          	im 1
+     adc:	0b          	nop
+     add:	83          	im 3
+     ade:	e2          	im -30
+     adf:	e4          	im -28
+     ae0:	0c          	store
+     ae1:	fc          	im -4
+     ae2:	85          	im 5
+     ae3:	39          	poppcrel
+
+00000ae4 <selectfile>:
+     ae4:	f7          	im -9
+     ae5:	3d          	pushspadd
+     ae6:	0d          	popsp
+     ae7:	7b          	loadsp 44
+     ae8:	5a          	storesp 40
+
+00000ae9 <.LM179>:
+     ae9:	8c          	im 12
+     aea:	9a          	im 26
+     aeb:	c0          	im -64
+     aec:	51          	storesp 4
+     aed:	f3          	im -13
+     aee:	c4          	im -60
+     aef:	3f          	callpcrel
+
+00000af0 <.LM180>:
+     af0:	80          	im 0
+     af1:	57          	storesp 28
+
+00000af2 <.LM181>:
+     af2:	80          	im 0
+     af3:	cf          	im -49
+     af4:	cf          	im -49
+     af5:	3f          	callpcrel
+
+00000af6 <.LM182>:
+     af6:	76          	loadsp 24
+     af7:	54          	storesp 16
+
+00000af8 <.L143>:
+     af8:	80          	im 0
+     af9:	0b          	nop
+     afa:	86          	im 6
+     afb:	b8          	im 56
+     afc:	c0          	im -64
+     afd:	15          	addsp 20
+     afe:	34          	storeb
+
+00000aff <.LM184>:
+     aff:	81          	im 1
+     b00:	14          	addsp 16
+     b01:	54          	storesp 16
+     b02:	73          	loadsp 12
+     b03:	87          	im 7
+     b04:	c0          	im -64
+     b05:	2e          	eq
+     b06:	09          	not
+     b07:	81          	im 1
+     b08:	06          	and
+     b09:	ee          	im -18
+     b0a:	38          	neqbranch
+
+00000b0b <.LM185>:
+     b0b:	0b          	nop
+     b0c:	0b          	nop
+     b0d:	80          	im 0
+     b0e:	f4          	im -12
+     b0f:	fc          	im -4
+     b10:	52          	storesp 8
+     b11:	83          	im 3
+     b12:	e2          	im -30
+     b13:	f4          	im -12
+     b14:	51          	storesp 4
+     b15:	80          	im 0
+     b16:	c0          	im -64
+     b17:	81          	im 1
+     b18:	3f          	callpcrel
+     b19:	83          	im 3
+     b1a:	e0          	im -32
+     b1b:	80          	im 0
+     b1c:	08          	load
+     b1d:	83          	im 3
+     b1e:	db          	im -37
+     b1f:	38          	neqbranch
+
+00000b20 <.LM186>:
+     b20:	80          	im 0
+
+00000b21 <.LM187>:
+     b21:	70          	loadsp 0
+
+00000b22 <.LM188>:
+     b22:	83          	im 3
+     b23:	e3          	im -29
+     b24:	a8          	im 40
+     b25:	08          	load
+     b26:	55          	storesp 20
+     b27:	59          	storesp 36
+     b28:	59          	storesp 36
+     b29:	94          	im 20
+     b2a:	73          	loadsp 12
+     b2b:	25          	lessthanorequal
+     b2c:	86          	im 6
+     b2d:	38          	neqbranch
+
+00000b2e <.LM189>:
+     b2e:	ec          	im -20
+     b2f:	13          	addsp 12
+     b30:	fe          	im -2
+     b31:	06          	and
+     b32:	58          	storesp 32
+
+00000b33 <.L147>:
+     b33:	80          	im 0
+     b34:	73          	loadsp 12
+     b35:	24          	lessthan
+     b36:	82          	im 2
+     b37:	ff          	im -1
+     b38:	38          	neqbranch
+
+00000b39 <.L192>:
+     b39:	83          	im 3
+     b3a:	e0          	im -32
+     b3b:	94          	im 20
+     b3c:	52          	storesp 8
+     b3d:	83          	im 3
+     b3e:	e2          	im -30
+     b3f:	f4          	im -12
+     b40:	51          	storesp 4
+     b41:	80          	im 0
+     b42:	c0          	im -64
+     b43:	e8          	im -24
+     b44:	3f          	callpcrel
+     b45:	83          	im 3
+     b46:	e0          	im -32
+     b47:	80          	im 0
+     b48:	08          	load
+     b49:	80          	im 0
+     b4a:	db          	im -37
+     b4b:	38          	neqbranch
+
+00000b4c <.L199>:
+     b4c:	83          	im 3
+     b4d:	e0          	im -32
+     b4e:	9d          	im 29
+     b4f:	33          	loadb
+     b50:	53          	storesp 12
+     b51:	72          	loadsp 8
+     b52:	80          	im 0
+     b53:	2e          	eq
+     b54:	80          	im 0
+     b55:	d0          	im -48
+     b56:	38          	neqbranch
+
+00000b57 <.LM192>:
+     b57:	83          	im 3
+     b58:	e0          	im -32
+     b59:	9c          	im 28
+     b5a:	33          	loadb
+     b5b:	70          	loadsp 0
+     b5c:	82          	im 2
+     b5d:	2a          	lshiftright
+     b5e:	70          	loadsp 0
+     b5f:	81          	im 1
+     b60:	06          	and
+     b61:	51          	storesp 4
+     b62:	54          	storesp 16
+     b63:	54          	storesp 16
+     b64:	72          	loadsp 8
+     b65:	d3          	im -45
+     b66:	38          	neqbranch
+
+00000b67 <.LM193>:
+     b67:	73          	loadsp 12
+     b68:	81          	im 1
+     b69:	2a          	lshiftright
+     b6a:	81          	im 1
+     b6b:	06          	and
+     b6c:	55          	storesp 20
+     b6d:	74          	loadsp 16
+     b6e:	ca          	im -54
+     b6f:	38          	neqbranch
+
+00000b70 <.LM194>:
+     b70:	73          	loadsp 12
+     b71:	84          	im 4
+     b72:	2a          	lshiftright
+     b73:	70          	loadsp 0
+     b74:	81          	im 1
+     b75:	06          	and
+     b76:	51          	storesp 4
+     b77:	53          	storesp 12
+     b78:	72          	loadsp 8
+     b79:	82          	im 2
+     b7a:	a3          	im 35
+     b7b:	38          	neqbranch
+
+00000b7c <.LM195>:
+     b7c:	83          	im 3
+     b7d:	e3          	im -29
+     b7e:	a8          	im 40
+     b7f:	08          	load
+     b80:	77          	loadsp 28
+     b81:	2e          	eq
+     b82:	81          	im 1
+     b83:	de          	im -34
+     b84:	38          	neqbranch
+
+00000b85 <.L154>:
+     b85:	ff          	im -1
+     b86:	18          	addsp 32
+     b87:	58          	storesp 32
+     b88:	80          	im 0
+     b89:	78          	loadsp 32
+     b8a:	24          	lessthan
+     b8b:	82          	im 2
+     b8c:	b2          	im 50
+     b8d:	38          	neqbranch
+
+00000b8e <.L160>:
+     b8e:	81          	im 1
+     b8f:	17          	addsp 28
+     b90:	57          	storesp 28
+
+00000b91 <.L201>:
+     b91:	83          	im 3
+     b92:	e0          	im -32
+     b93:	94          	im 20
+     b94:	52          	storesp 8
+     b95:	83          	im 3
+     b96:	e2          	im -30
+     b97:	f4          	im -12
+     b98:	51          	storesp 4
+     b99:	80          	im 0
+     b9a:	c0          	im -64
+     b9b:	90          	im 16
+     b9c:	3f          	callpcrel
+     b9d:	83          	im 3
+     b9e:	e0          	im -32
+     b9f:	80          	im 0
+     ba0:	08          	load
+     ba1:	80          	im 0
+     ba2:	2e          	eq
+     ba3:	ff          	im -1
+     ba4:	a7          	im 39
+     ba5:	38          	neqbranch
+
+00000ba6 <.L150>:
+     ba6:	0b          	nop
+     ba7:	0b          	nop
+     ba8:	80          	im 0
+     ba9:	f9          	im -7
+     baa:	c4          	im -60
+     bab:	51          	storesp 4
+     bac:	80          	im 0
+     bad:	d0          	im -48
+     bae:	be          	im 62
+     baf:	3f          	callpcrel
+
+00000bb0 <.LM199>:
+     bb0:	95          	im 21
+     bb1:	51          	storesp 4
+     bb2:	80          	im 0
+     bb3:	ce          	im -50
+     bb4:	a2          	im 34
+     bb5:	3f          	callpcrel
+
+00000bb6 <.LM200>:
+     bb6:	80          	im 0
+     bb7:	0b          	nop
+     bb8:	83          	im 3
+     bb9:	e0          	im -32
+     bba:	b4          	im 52
+     bbb:	0c          	store
+
+00000bbc <.LM201>:
+     bbc:	79          	loadsp 36
+     bbd:	51          	storesp 4
+     bbe:	f6          	im -10
+     bbf:	fb          	im -5
+     bc0:	3f          	callpcrel
+
+00000bc1 <.LM202>:
+     bc1:	80          	im 0
+     bc2:	fb          	im -5
+     bc3:	c4          	im -60
+     bc4:	08          	load
+     bc5:	70          	loadsp 0
+     bc6:	33          	loadb
+     bc7:	70          	loadsp 0
+     bc8:	81          	im 1
+     bc9:	ff          	im -1
+     bca:	06          	and
+
+00000bcb <.LM203>:
+     bcb:	70          	loadsp 0
+     bcc:	81          	im 1
+     bcd:	2a          	lshiftright
+     bce:	81          	im 1
+     bcf:	32          	xor
+     bd0:	70          	loadsp 0
+     bd1:	81          	im 1
+     bd2:	06          	and
+     bd3:	51          	storesp 4
+     bd4:	52          	storesp 8
+     bd5:	56          	storesp 24
+     bd6:	51          	storesp 4
+     bd7:	53          	storesp 12
+     bd8:	72          	loadsp 8
+     bd9:	80          	im 0
+     bda:	eb          	im -21
+     bdb:	38          	neqbranch
+
+00000bdc <.L200>:
+     bdc:	73          	loadsp 12
+     bdd:	81          	im 1
+     bde:	32          	xor
+     bdf:	70          	loadsp 0
+     be0:	81          	im 1
+     be1:	06          	and
+     be2:	51          	storesp 4
+     be3:	53          	storesp 12
+     be4:	72          	loadsp 8
+     be5:	82          	im 2
+     be6:	e1          	im -31
+     be7:	38          	neqbranch
+
+00000be8 <.LM205>:
+     be8:	73          	loadsp 12
+     be9:	83          	im 3
+     bea:	2a          	lshiftright
+     beb:	81          	im 1
+     bec:	32          	xor
+     bed:	70          	loadsp 0
+     bee:	81          	im 1
+     bef:	06          	and
+     bf0:	51          	storesp 4
+     bf1:	53          	storesp 12
+     bf2:	72          	loadsp 8
+     bf3:	82          	im 2
+     bf4:	c2          	im -62
+     bf5:	38          	neqbranch
+
+00000bf6 <.LM206>:
+     bf6:	73          	loadsp 12
+     bf7:	82          	im 2
+     bf8:	2a          	lshiftright
+     bf9:	81          	im 1
+     bfa:	32          	xor
+     bfb:	70          	loadsp 0
+     bfc:	81          	im 1
+     bfd:	06          	and
+     bfe:	51          	storesp 4
+     bff:	53          	storesp 12
+     c00:	72          	loadsp 8
+     c01:	82          	im 2
+     c02:	a3          	im 35
+     c03:	38          	neqbranch
+
+00000c04 <.LM207>:
+     c04:	80          	im 0
+     c05:	fb          	im -5
+     c06:	bc          	im 60
+     c07:	08          	load
+     c08:	70          	loadsp 0
+     c09:	33          	loadb
+     c0a:	70          	loadsp 0
+     c0b:	81          	im 1
+     c0c:	ff          	im -1
+     c0d:	06          	and
+     c0e:	51          	storesp 4
+     c0f:	54          	storesp 16
+     c10:	54          	storesp 16
+     c11:	72          	loadsp 8
+     c12:	80          	im 0
+     c13:	2e          	eq
+     c14:	81          	im 1
+     c15:	f0          	im -16
+     c16:	38          	neqbranch
+
+00000c17 <.LM208>:
+     c17:	80          	im 0
+     c18:	cd          	im -51
+     c19:	aa          	im 42
+     c1a:	3f          	callpcrel
+
+00000c1b <.LM209>:
+     c1b:	80          	im 0
+     c1c:	fb          	im -5
+     c1d:	c8          	im -56
+     c1e:	08          	load
+     c1f:	80          	im 0
+     c20:	fb          	im -5
+     c21:	d8          	im -40
+     c22:	08          	load
+     c23:	54          	storesp 16
+     c24:	54          	storesp 16
+     c25:	73          	loadsp 12
+     c26:	33          	loadb
+     c27:	73          	loadsp 12
+     c28:	34          	storeb
+
+00000c29 <.LM210>:
+     c29:	80          	im 0
+     c2a:	fb          	im -5
+     c2b:	c4          	im -60
+     c2c:	08          	load
+     c2d:	70          	loadsp 0
+     c2e:	33          	loadb
+     c2f:	70          	loadsp 0
+     c30:	81          	im 1
+     c31:	ff          	im -1
+     c32:	06          	and
+
+00000c33 <.LM211>:
+     c33:	70          	loadsp 0
+     c34:	81          	im 1
+     c35:	2a          	lshiftright
+     c36:	81          	im 1
+     c37:	32          	xor
+     c38:	70          	loadsp 0
+     c39:	81          	im 1
+     c3a:	06          	and
+     c3b:	51          	storesp 4
+     c3c:	52          	storesp 8
+     c3d:	56          	storesp 24
+     c3e:	51          	storesp 4
+     c3f:	53          	storesp 12
+     c40:	72          	loadsp 8
+     c41:	80          	im 0
+     c42:	2e          	eq
+     c43:	ff          	im -1
+     c44:	97          	im 23
+     c45:	38          	neqbranch
+
+00000c46 <.L183>:
+     c46:	83          	im 3
+     c47:	e3          	im -29
+     c48:	a8          	im 40
+     c49:	08          	load
+     c4a:	82          	im 2
+     c4b:	05          	add
+     c4c:	83          	im 3
+     c4d:	e3          	im -29
+     c4e:	a8          	im 40
+     c4f:	0c          	store
+
+00000c50 <.LM213>:
+     c50:	84          	im 4
+     c51:	f1          	im -15
+     c52:	80          	im 0
+     c53:	51          	storesp 4
+
+00000c54 <.L203>:
+     c54:	f0          	im -16
+     c55:	dd          	im -35
+     c56:	3f          	callpcrel
+
+00000c57 <.LM215>:
+     c57:	80          	im 0
+     c58:	57          	storesp 28
+
+00000c59 <.LM216>:
+     c59:	80          	im 0
+     c5a:	cc          	im -52
+     c5b:	e8          	im -24
+     c5c:	3f          	callpcrel
+
+00000c5d <.LM217>:
+     c5d:	76          	loadsp 24
+     c5e:	54          	storesp 16
+     c5f:	fd          	im -3
+     c60:	97          	im 23
+     c61:	39          	poppcrel
+
+00000c62 <.L197>:
+     c62:	74          	loadsp 16
+     c63:	83          	im 3
+     c64:	e0          	im -32
+     c65:	9d          	im 29
+     c66:	57          	storesp 28
+     c67:	54          	storesp 16
+
+00000c68 <.L159>:
+     c68:	73          	loadsp 12
+     c69:	1a          	addsp 40
+     c6a:	53          	storesp 12
+     c6b:	75          	loadsp 20
+     c6c:	33          	loadb
+     c6d:	73          	loadsp 12
+     c6e:	34          	storeb
+
+00000c6f <.LM220>:
+     c6f:	75          	loadsp 20
+     c70:	33          	loadb
+     c71:	70          	loadsp 0
+     c72:	81          	im 1
+     c73:	ff          	im -1
+     c74:	06          	and
+     c75:	54          	storesp 16
+     c76:	55          	storesp 20
+     c77:	72          	loadsp 8
+     c78:	80          	im 0
+     c79:	2e          	eq
+     c7a:	fe          	im -2
+     c7b:	89          	im 9
+     c7c:	38          	neqbranch
+
+00000c7d <.LM221>:
+     c7d:	ff          	im -1
+     c7e:	80          	im 0
+     c7f:	15          	addsp 20
+     c80:	53          	storesp 12
+     c81:	72          	loadsp 8
+     c82:	76          	loadsp 24
+     c83:	70          	loadsp 0
+     c84:	81          	im 1
+     c85:	05          	add
+     c86:	58          	storesp 32
+     c87:	34          	storeb
+
+00000c88 <.LM222>:
+     c88:	81          	im 1
+     c89:	14          	addsp 16
+     c8a:	54          	storesp 16
+     c8b:	73          	loadsp 12
+     c8c:	8f          	im 15
+     c8d:	2e          	eq
+     c8e:	09          	not
+     c8f:	81          	im 1
+     c90:	06          	and
+     c91:	d6          	im -42
+     c92:	38          	neqbranch
+
+00000c93 <.LM223>:
+     c93:	ff          	im -1
+     c94:	18          	addsp 32
+     c95:	58          	storesp 32
+     c96:	77          	loadsp 28
+     c97:	80          	im 0
+     c98:	25          	lessthanorequal
+     c99:	fd          	im -3
+     c9a:	f3          	im -13
+     c9b:	38          	neqbranch
+     c9c:	a2          	im 34
+     c9d:	39          	poppcrel
+
+00000c9e <.L196>:
+     c9e:	0b          	nop
+     c9f:	0b          	nop
+     ca0:	80          	im 0
+     ca1:	f6          	im -10
+     ca2:	80          	im 0
+     ca3:	51          	storesp 4
+     ca4:	80          	im 0
+     ca5:	ce          	im -50
+     ca6:	c6          	im -58
+     ca7:	3f          	callpcrel
+
+00000ca8 <.LM225>:
+     ca8:	83          	im 3
+     ca9:	e3          	im -29
+     caa:	a8          	im 40
+     cab:	08          	load
+     cac:	77          	loadsp 28
+     cad:	2e          	eq
+     cae:	09          	not
+     caf:	81          	im 1
+     cb0:	06          	and
+     cb1:	fd          	im -3
+     cb2:	d2          	im -46
+     cb3:	38          	neqbranch
+     cb4:	ff          	im -1
+     cb5:	ac          	im 44
+     cb6:	39          	poppcrel
+
+00000cb7 <.L195>:
+     cb7:	78          	loadsp 32
+     cb8:	83          	im 3
+     cb9:	e3          	im -29
+     cba:	a8          	im 40
+     cbb:	0c          	store
+     cbc:	fc          	im -4
+     cbd:	fb          	im -5
+     cbe:	39          	poppcrel
+
+00000cbf <.L198>:
+     cbf:	83          	im 3
+     cc0:	e0          	im -32
+     cc1:	9d          	im 29
+     cc2:	51          	storesp 4
+     cc3:	80          	im 0
+     cc4:	ce          	im -50
+     cc5:	a7          	im 39
+     cc6:	3f          	callpcrel
+
+00000cc7 <.LM228>:
+     cc7:	81          	im 1
+     cc8:	19          	addsp 36
+
+00000cc9 <.LM229>:
+     cc9:	70          	loadsp 0
+     cca:	81          	im 1
+     ccb:	06          	and
+     ccc:	54          	storesp 16
+     ccd:	59          	storesp 36
+     cce:	72          	loadsp 8
+     ccf:	80          	im 0
+     cd0:	2e          	eq
+     cd1:	93          	im 19
+     cd2:	38          	neqbranch
+
+00000cd3 <.LM230>:
+     cd3:	94          	im 20
+     cd4:	51          	storesp 4
+     cd5:	80          	im 0
+     cd6:	cb          	im -53
+     cd7:	f9          	im -7
+     cd8:	3f          	callpcrel
+
+00000cd9 <.LM231>:
+     cd9:	78          	loadsp 32
+     cda:	a8          	im 40
+     cdb:	2e          	eq
+     cdc:	fd          	im -3
+     cdd:	c8          	im -56
+     cde:	38          	neqbranch
+
+00000cdf <.L202>:
+     cdf:	81          	im 1
+     ce0:	17          	addsp 28
+     ce1:	57          	storesp 28
+     ce2:	fd          	im -3
+     ce3:	ad          	im 45
+     ce4:	39          	poppcrel
+
+00000ce5 <.L161>:
+     ce5:	0b          	nop
+     ce6:	0b          	nop
+     ce7:	80          	im 0
+     ce8:	f9          	im -7
+     ce9:	c4          	im -60
+     cea:	51          	storesp 4
+     ceb:	80          	im 0
+     cec:	cd          	im -51
+     ced:	ff          	im -1
+     cee:	3f          	callpcrel
+
+00000cef <.LM234>:
+     cef:	78          	loadsp 32
+     cf0:	a8          	im 40
+     cf1:	2e          	eq
+     cf2:	09          	not
+     cf3:	81          	im 1
+     cf4:	06          	and
+     cf5:	e9          	im -23
+     cf6:	38          	neqbranch
+     cf7:	fd          	im -3
+     cf8:	ad          	im 45
+     cf9:	39          	poppcrel
+
+00000cfa <.L194>:
+     cfa:	0b          	nop
+     cfb:	0b          	nop
+     cfc:	80          	im 0
+     cfd:	f6          	im -10
+     cfe:	88          	im 8
+     cff:	51          	storesp 4
+     d00:	80          	im 0
+     d01:	cd          	im -51
+     d02:	ea          	im -22
+     d03:	3f          	callpcrel
+
+00000d04 <.L145>:
+     d04:	ff          	im -1
+     d05:	39          	poppcrel
+
+00000d06 <.L176>:
+     d06:	73          	loadsp 12
+     d07:	33          	loadb
+     d08:	70          	loadsp 0
+     d09:	81          	im 1
+     d0a:	ff          	im -1
+     d0b:	06          	and
+     d0c:	51          	storesp 4
+     d0d:	53          	storesp 12
+     d0e:	72          	loadsp 8
+     d0f:	80          	im 0
+     d10:	2e          	eq
+     d11:	f4          	im -12
+     d12:	38          	neqbranch
+
+00000d13 <.LM237>:
+     d13:	8c          	im 12
+     d14:	9a          	im 26
+     d15:	c0          	im -64
+     d16:	51          	storesp 4
+     d17:	ef          	im -17
+     d18:	9a          	im 26
+     d19:	3f          	callpcrel
+
+00000d1a <.LM238>:
+     d1a:	83          	im 3
+     d1b:	e2          	im -30
+     d1c:	e4          	im -28
+     d1d:	08          	load
+     d1e:	83          	im 3
+     d1f:	e0          	im -32
+     d20:	80          	im 0
+     d21:	0c          	store
+
+00000d22 <.LM239>:
+     d22:	8b          	im 11
+     d23:	3d          	pushspadd
+     d24:	0d          	popsp
+     d25:	04          	poppc
+
+00000d26 <.L186>:
+     d26:	83          	im 3
+     d27:	e3          	im -29
+     d28:	a8          	im 40
+     d29:	08          	load
+     d2a:	fe          	im -2
+     d2b:	06          	and
+     d2c:	83          	im 3
+     d2d:	e3          	im -29
+     d2e:	a8          	im 40
+     d2f:	0c          	store
+
+00000d30 <.LM241>:
+     d30:	84          	im 4
+     d31:	f1          	im -15
+     d32:	80          	im 0
+     d33:	51          	storesp 4
+     d34:	fe          	im -2
+     d35:	9e          	im 30
+     d36:	39          	poppcrel
+
+00000d37 <.L185>:
+     d37:	83          	im 3
+     d38:	e3          	im -29
+     d39:	a8          	im 40
+     d3a:	08          	load
+     d3b:	81          	im 1
+     d3c:	07          	or
+     d3d:	83          	im 3
+     d3e:	e3          	im -29
+     d3f:	a8          	im 40
+     d40:	0c          	store
+
+00000d41 <.LM243>:
+     d41:	84          	im 4
+     d42:	f1          	im -15
+     d43:	80          	im 0
+     d44:	51          	storesp 4
+     d45:	fe          	im -2
+     d46:	8d          	im 13
+     d47:	39          	poppcrel
+
+00000d48 <.L184>:
+     d48:	83          	im 3
+     d49:	e3          	im -29
+     d4a:	a8          	im 40
+     d4b:	08          	load
+     d4c:	fe          	im -2
+     d4d:	05          	add
+     d4e:	83          	im 3
+     d4f:	e3          	im -29
+     d50:	a8          	im 40
+     d51:	0c          	store
+
+00000d52 <.LM245>:
+     d52:	84          	im 4
+     d53:	f1          	im -15
+     d54:	80          	im 0
+     d55:	51          	storesp 4
+     d56:	fd          	im -3
+     d57:	fc          	im -4
+     d58:	39          	poppcrel
+
+00000d59 <actions>:
+     d59:	e2          	im -30
+     d5a:	3d          	pushspadd
+     d5b:	0d          	popsp
+
+00000d5c <.LM247>:
+     d5c:	80          	im 0
+
+00000d5d <.LM248>:
+     d5d:	0b          	nop
+     d5e:	80          	im 0
+     d5f:	fc          	im -4
+     d60:	b8          	im 56
+     d61:	08          	load
+     d62:	70          	loadsp 0
+     d63:	08          	load
+     d64:	70          	loadsp 0
+     d65:	81          	im 1
+     d66:	06          	and
+     d67:	51          	storesp 4
+     d68:	56          	storesp 24
+     d69:	56          	storesp 24
+     d6a:	58          	storesp 32
+     d6b:	73          	loadsp 12
+     d6c:	78          	loadsp 32
+     d6d:	2e          	eq
+     d6e:	09          	not
+     d6f:	81          	im 1
+     d70:	06          	and
+     d71:	82          	im 2
+     d72:	a7          	im 39
+     d73:	38          	neqbranch
+
+00000d74 <.L205>:
+     d74:	74          	loadsp 16
+     d75:	08          	load
+     d76:	70          	loadsp 0
+     d77:	81          	im 1
+     d78:	2a          	lshiftright
+     d79:	70          	loadsp 0
+     d7a:	81          	im 1
+     d7b:	06          	and
+     d7c:	51          	storesp 4
+     d7d:	51          	storesp 4
+     d7e:	54          	storesp 16
+     d7f:	73          	loadsp 12
+     d80:	80          	im 0
+     d81:	c9          	im -55
+     d82:	38          	neqbranch
+
+00000d83 <.L317>:
+     d83:	74          	loadsp 16
+     d84:	08          	load
+     d85:	70          	loadsp 0
+     d86:	82          	im 2
+     d87:	2a          	lshiftright
+     d88:	70          	loadsp 0
+     d89:	81          	im 1
+     d8a:	06          	and
+     d8b:	51          	storesp 4
+     d8c:	51          	storesp 4
+     d8d:	54          	storesp 16
+     d8e:	73          	loadsp 12
+     d8f:	80          	im 0
+     d90:	2e          	eq
+     d91:	90          	im 16
+     d92:	38          	neqbranch
+
+00000d93 <.LM251>:
+     d93:	80          	im 0
+     d94:	51          	storesp 4
+     d95:	f1          	im -15
+     d96:	d3          	im -45
+     d97:	3f          	callpcrel
+
+00000d98 <.LM252>:
+     d98:	81          	im 1
+     d99:	51          	storesp 4
+     d9a:	f1          	im -15
+     d9b:	ce          	im -50
+     d9c:	3f          	callpcrel
+     d9d:	80          	im 0
+     d9e:	fc          	im -4
+     d9f:	b8          	im 56
+     da0:	08          	load
+     da1:	55          	storesp 20
+
+00000da2 <.L323>:
+     da2:	74          	loadsp 16
+     da3:	08          	load
+     da4:	70          	loadsp 0
+     da5:	83          	im 3
+     da6:	2a          	lshiftright
+     da7:	70          	loadsp 0
+     da8:	81          	im 1
+     da9:	06          	and
+     daa:	51          	storesp 4
+     dab:	51          	storesp 4
+     dac:	54          	storesp 16
+     dad:	73          	loadsp 12
+     dae:	80          	im 0
+     daf:	2e          	eq
+     db0:	96          	im 22
+     db1:	38          	neqbranch
+
+00000db2 <.LM254>:
+     db2:	80          	im 0
+     db3:	51          	storesp 4
+     db4:	f1          	im -15
+     db5:	b4          	im 52
+     db6:	3f          	callpcrel
+
+00000db7 <.LM255>:
+     db7:	80          	im 0
+     db8:	fb          	im -5
+     db9:	e4          	im -28
+     dba:	08          	load
+     dbb:	54          	storesp 16
+     dbc:	80          	im 0
+     dbd:	74          	loadsp 16
+     dbe:	34          	storeb
+
+00000dbf <.LM256>:
+     dbf:	f0          	im -16
+     dc0:	af          	im 47
+     dc1:	3f          	callpcrel
+
+00000dc2 <.LM257>:
+     dc2:	81          	im 1
+     dc3:	51          	storesp 4
+     dc4:	f1          	im -15
+     dc5:	a4          	im 36
+     dc6:	3f          	callpcrel
+
+00000dc7 <.L204>:
+     dc7:	a0          	im 32
+     dc8:	3d          	pushspadd
+     dc9:	0d          	popsp
+     dca:	04          	poppc
+
+00000dcb <.L372>:
+     dcb:	81          	im 1
+     dcc:	51          	storesp 4
+     dcd:	f1          	im -15
+     dce:	bf          	im 63
+     dcf:	3f          	callpcrel
+
+00000dd0 <.LM260>:
+     dd0:	f0          	im -16
+     dd1:	9e          	im 30
+     dd2:	3f          	callpcrel
+
+00000dd3 <.LM261>:
+     dd3:	8e          	im 14
+     dd4:	3d          	pushspadd
+     dd5:	57          	storesp 28
+     dd6:	a1          	im 33
+     dd7:	53          	storesp 12
+     dd8:	80          	im 0
+     dd9:	f4          	im -12
+     dda:	b4          	im 52
+     ddb:	52          	storesp 8
+     ddc:	76          	loadsp 24
+     ddd:	51          	storesp 4
+     dde:	80          	im 0
+     ddf:	d7          	im -41
+     de0:	a8          	im 40
+     de1:	3f          	callpcrel
+
+00000de2 <.LM262>:
+     de2:	80          	im 0
+     de3:	56          	storesp 24
+
+00000de4 <.L321>:
+     de4:	84          	im 4
+     de5:	8c          	im 12
+     de6:	80          	im 0
+     de7:	16          	addsp 24
+     de8:	76          	loadsp 24
+     de9:	18          	addsp 32
+     dea:	55          	storesp 20
+     deb:	55          	storesp 20
+     dec:	73          	loadsp 12
+     ded:	33          	loadb
+     dee:	75          	loadsp 20
+     def:	34          	storeb
+
+00000df0 <.LM264>:
+     df0:	81          	im 1
+     df1:	16          	addsp 24
+     df2:	56          	storesp 24
+     df3:	75          	loadsp 20
+     df4:	a1          	im 33
+     df5:	2e          	eq
+     df6:	09          	not
+     df7:	81          	im 1
+     df8:	06          	and
+     df9:	ea          	im -22
+     dfa:	38          	neqbranch
+
+00000dfb <.LM265>:
+     dfb:	80          	im 0
+     dfc:	fb          	im -5
+     dfd:	e0          	im -32
+     dfe:	08          	load
+     dff:	54          	storesp 16
+     e00:	80          	im 0
+     e01:	74          	loadsp 16
+     e02:	34          	storeb
+
+00000e03 <.LM266>:
+     e03:	80          	im 0
+     e04:	fb          	im -5
+     e05:	dc          	im -36
+     e06:	08          	load
+     e07:	54          	storesp 16
+     e08:	86          	im 6
+     e09:	74          	loadsp 16
+     e0a:	34          	storeb
+
+00000e0b <.LM267>:
+     e0b:	80          	im 0
+     e0c:	fb          	im -5
+     e0d:	d8          	im -40
+     e0e:	08          	load
+     e0f:	54          	storesp 16
+     e10:	80          	im 0
+     e11:	74          	loadsp 16
+     e12:	34          	storeb
+
+00000e13 <.LM268>:
+     e13:	80          	im 0
+     e14:	fb          	im -5
+     e15:	d4          	im -44
+     e16:	08          	load
+     e17:	54          	storesp 16
+     e18:	8f          	im 15
+     e19:	74          	loadsp 16
+     e1a:	34          	storeb
+
+00000e1b <.LM269>:
+     e1b:	80          	im 0
+     e1c:	fb          	im -5
+     e1d:	d0          	im -48
+     e1e:	08          	load
+     e1f:	54          	storesp 16
+     e20:	80          	im 0
+     e21:	74          	loadsp 16
+     e22:	34          	storeb
+
+00000e23 <.LM270>:
+     e23:	80          	im 0
+     e24:	fb          	im -5
+     e25:	cc          	im -52
+     e26:	08          	load
+     e27:	54          	storesp 16
+     e28:	80          	im 0
+     e29:	74          	loadsp 16
+     e2a:	34          	storeb
+
+00000e2b <.LM271>:
+     e2b:	80          	im 0
+     e2c:	fb          	im -5
+     e2d:	c0          	im -64
+     e2e:	08          	load
+     e2f:	54          	storesp 16
+     e30:	ff          	im -1
+     e31:	74          	loadsp 16
+     e32:	34          	storeb
+
+00000e33 <.LM272>:
+     e33:	80          	im 0
+     e34:	fb          	im -5
+     e35:	b8          	im 56
+     e36:	08          	load
+     e37:	54          	storesp 16
+     e38:	e0          	im -32
+     e39:	74          	loadsp 16
+     e3a:	34          	storeb
+
+00000e3b <.LM273>:
+     e3b:	80          	im 0
+     e3c:	fb          	im -5
+     e3d:	b0          	im 48
+     e3e:	08          	load
+     e3f:	54          	storesp 16
+     e40:	a2          	im 34
+     e41:	74          	loadsp 16
+     e42:	34          	storeb
+
+00000e43 <.LM274>:
+     e43:	81          	im 1
+     e44:	51          	storesp 4
+     e45:	80          	im 0
+     e46:	c9          	im -55
+     e47:	95          	im 21
+     e48:	3f          	callpcrel
+
+00000e49 <.LM275>:
+     e49:	83          	im 3
+     e4a:	e3          	im -29
+     e4b:	98          	im 24
+     e4c:	51          	storesp 4
+     e4d:	f9          	im -7
+     e4e:	95          	im 21
+     e4f:	3f          	callpcrel
+     e50:	83          	im 3
+     e51:	e0          	im -32
+     e52:	80          	im 0
+     e53:	08          	load
+     e54:	80          	im 0
+     e55:	2e          	eq
+     e56:	ad          	im 45
+     e57:	38          	neqbranch
+
+00000e58 <.LM276>:
+     e58:	81          	im 1
+     e59:	0b          	nop
+     e5a:	83          	im 3
+     e5b:	e0          	im -32
+     e5c:	b4          	im 52
+     e5d:	0c          	store
+
+00000e5e <.LM277>:
+     e5e:	0b          	nop
+     e5f:	0b          	nop
+     e60:	80          	im 0
+     e61:	f6          	im -10
+     e62:	98          	im 24
+     e63:	51          	storesp 4
+     e64:	80          	im 0
+     e65:	cb          	im -53
+     e66:	86          	im 6
+     e67:	3f          	callpcrel
+
+00000e68 <.LM278>:
+     e68:	9e          	im 30
+     e69:	c2          	im -62
+     e6a:	a0          	im 32
+     e6b:	51          	storesp 4
+     e6c:	ec          	im -20
+     e6d:	c5          	im -59
+     e6e:	3f          	callpcrel
+
+00000e6f <.LM279>:
+     e6f:	80          	im 0
+     e70:	51          	storesp 4
+     e71:	ef          	im -17
+     e72:	f7          	im -9
+     e73:	3f          	callpcrel
+
+00000e74 <.LM280>:
+     e74:	80          	im 0
+     e75:	fb          	im -5
+     e76:	e4          	im -28
+     e77:	08          	load
+     e78:	54          	storesp 16
+     e79:	80          	im 0
+     e7a:	74          	loadsp 16
+     e7b:	34          	storeb
+
+00000e7c <.LM281>:
+     e7c:	ee          	im -18
+     e7d:	f2          	im -14
+     e7e:	3f          	callpcrel
+
+00000e7f <.LM282>:
+     e7f:	81          	im 1
+     e80:	51          	storesp 4
+     e81:	ef          	im -17
+     e82:	e7          	im -25
+     e83:	3f          	callpcrel
+
+00000e84 <.L322>:
+     e84:	83          	im 3
+     e85:	e0          	im -32
+     e86:	ac          	im 44
+     e87:	08          	load
+     e88:	51          	storesp 4
+     e89:	80          	im 0
+     e8a:	c8          	im -56
+     e8b:	d1          	im -47
+     e8c:	3f          	callpcrel
+
+00000e8d <.LM284>:
+     e8d:	80          	im 0
+     e8e:	51          	storesp 4
+     e8f:	ef          	im -17
+     e90:	fd          	im -3
+     e91:	3f          	callpcrel
+     e92:	80          	im 0
+     e93:	fc          	im -4
+     e94:	b8          	im 56
+     e95:	08          	load
+     e96:	55          	storesp 20
+     e97:	fd          	im -3
+     e98:	ea          	im -22
+     e99:	39          	poppcrel
+
+00000e9a <.L371>:
+     e9a:	77          	loadsp 28
+
+00000e9b <.LM286>:
+     e9b:	78          	loadsp 32
+
+00000e9c <.LM287>:
+     e9c:	79          	loadsp 36
+
+00000e9d <.LM288>:
+     e9d:	7a          	loadsp 40
+     e9e:	5f          	storesp 60
+     e9f:	59          	storesp 36
+     ea0:	5a          	storesp 40
+     ea1:	5b          	storesp 44
+
+00000ea2 <.LM289>:
+     ea2:	81          	im 1
+     ea3:	51          	storesp 4
+     ea4:	ef          	im -17
+     ea5:	e8          	im -24
+     ea6:	3f          	callpcrel
+
+00000ea7 <.LM290>:
+     ea7:	81          	im 1
+     ea8:	51          	storesp 4
+     ea9:	80          	im 0
+     eaa:	c8          	im -56
+     eab:	b1          	im 49
+     eac:	3f          	callpcrel
+
+00000ead <.L209>:
+     ead:	81          	im 1
+     eae:	9f          	im 31
+     eaf:	e0          	im -32
+     eb0:	80          	im 0
+     eb1:	18          	addsp 32
+     eb2:	86          	im 6
+     eb3:	b8          	im 56
+     eb4:	80          	im 0
+     eb5:	19          	addsp 36
+     eb6:	55          	storesp 20
+     eb7:	55          	storesp 20
+     eb8:	73          	loadsp 12
+     eb9:	33          	loadb
+     eba:	75          	loadsp 20
+     ebb:	34          	storeb
+
+00000ebc <.LM292>:
+     ebc:	81          	im 1
+     ebd:	18          	addsp 32
+     ebe:	58          	storesp 32
+     ebf:	77          	loadsp 28
+     ec0:	88          	im 8
+     ec1:	80          	im 0
+     ec2:	2e          	eq
+     ec3:	09          	not
+     ec4:	81          	im 1
+     ec5:	06          	and
+     ec6:	e6          	im -26
+     ec7:	38          	neqbranch
+
+00000ec8 <.LM293>:
+     ec8:	80          	im 0
+     ec9:	c0          	im -64
+     eca:	58          	storesp 32
+
+00000ecb <.L213>:
+     ecb:	86          	im 6
+     ecc:	b8          	im 56
+     ecd:	80          	im 0
+     ece:	18          	addsp 32
+     ecf:	54          	storesp 16
+     ed0:	80          	im 0
+     ed1:	74          	loadsp 16
+     ed2:	34          	storeb
+
+00000ed3 <.LM295>:
+     ed3:	81          	im 1
+     ed4:	18          	addsp 32
+     ed5:	58          	storesp 32
+     ed6:	77          	loadsp 28
+     ed7:	88          	im 8
+     ed8:	80          	im 0
+     ed9:	2e          	eq
+     eda:	09          	not
+     edb:	81          	im 1
+     edc:	06          	and
+     edd:	ed          	im -19
+     ede:	38          	neqbranch
+
+00000edf <.LM296>:
+     edf:	83          	im 3
+     ee0:	a0          	im 32
+     ee1:	80          	im 0
+     ee2:	58          	storesp 32
+
+00000ee3 <.L217>:
+     ee3:	81          	im 1
+     ee4:	9c          	im 28
+     ee5:	80          	im 0
+     ee6:	80          	im 0
+     ee7:	18          	addsp 32
+     ee8:	88          	im 8
+     ee9:	80          	im 0
+     eea:	80          	im 0
+     eeb:	19          	addsp 36
+     eec:	56          	storesp 24
+     eed:	54          	storesp 16
+     eee:	74          	loadsp 16
+     eef:	33          	loadb
+     ef0:	74          	loadsp 16
+     ef1:	34          	storeb
+
+00000ef2 <.LM298>:
+     ef2:	84          	im 4
+     ef3:	80          	im 0
+     ef4:	80          	im 0
+     ef5:	18          	addsp 32
+     ef6:	54          	storesp 16
+     ef7:	80          	im 0
+     ef8:	74          	loadsp 16
+     ef9:	34          	storeb
+
+00000efa <.LM299>:
+     efa:	81          	im 1
+     efb:	18          	addsp 32
+     efc:	58          	storesp 32
+     efd:	77          	loadsp 28
+     efe:	83          	im 3
+     eff:	a0          	im 32
+     f00:	9f          	im 31
+     f01:	2e          	eq
+     f02:	09          	not
+     f03:	81          	im 1
+     f04:	06          	and
+     f05:	dd          	im -35
+     f06:	38          	neqbranch
+
+00000f07 <.LM300>:
+     f07:	83          	im 3
+     f08:	a4          	im 36
+     f09:	80          	im 0
+     f0a:	58          	storesp 32
+
+00000f0b <.L221>:
+     f0b:	81          	im 1
+     f0c:	9c          	im 28
+     f0d:	80          	im 0
+     f0e:	80          	im 0
+     f0f:	18          	addsp 32
+     f10:	88          	im 8
+     f11:	80          	im 0
+     f12:	80          	im 0
+     f13:	19          	addsp 36
+     f14:	56          	storesp 24
+     f15:	54          	storesp 16
+     f16:	74          	loadsp 16
+     f17:	33          	loadb
+     f18:	74          	loadsp 16
+     f19:	34          	storeb
+
+00000f1a <.LM302>:
+     f1a:	84          	im 4
+     f1b:	80          	im 0
+     f1c:	80          	im 0
+     f1d:	18          	addsp 32
+     f1e:	54          	storesp 16
+     f1f:	80          	im 0
+     f20:	74          	loadsp 16
+     f21:	34          	storeb
+
+00000f22 <.LM303>:
+     f22:	81          	im 1
+     f23:	18          	addsp 32
+     f24:	58          	storesp 32
+     f25:	77          	loadsp 28
+     f26:	83          	im 3
+     f27:	a4          	im 36
+     f28:	9f          	im 31
+     f29:	2e          	eq
+     f2a:	09          	not
+     f2b:	81          	im 1
+     f2c:	06          	and
+     f2d:	dd          	im -35
+     f2e:	38          	neqbranch
+
+00000f2f <.LM304>:
+     f2f:	83          	im 3
+     f30:	a8          	im 40
+     f31:	80          	im 0
+     f32:	58          	storesp 32
+
+00000f33 <.L225>:
+     f33:	81          	im 1
+     f34:	9c          	im 28
+     f35:	80          	im 0
+     f36:	80          	im 0
+     f37:	18          	addsp 32
+     f38:	88          	im 8
+     f39:	80          	im 0
+     f3a:	80          	im 0
+     f3b:	19          	addsp 36
+     f3c:	56          	storesp 24
+     f3d:	54          	storesp 16
+     f3e:	74          	loadsp 16
+     f3f:	33          	loadb
+     f40:	74          	loadsp 16
+     f41:	34          	storeb
+
+00000f42 <.LM306>:
+     f42:	84          	im 4
+     f43:	80          	im 0
+     f44:	80          	im 0
+     f45:	18          	addsp 32
+     f46:	54          	storesp 16
+     f47:	80          	im 0
+     f48:	74          	loadsp 16
+     f49:	34          	storeb
+
+00000f4a <.LM307>:
+     f4a:	81          	im 1
+     f4b:	18          	addsp 32
+     f4c:	58          	storesp 32
+     f4d:	77          	loadsp 28
+     f4e:	83          	im 3
+     f4f:	a8          	im 40
+     f50:	8f          	im 15
+     f51:	2e          	eq
+     f52:	09          	not
+     f53:	81          	im 1
+     f54:	06          	and
+     f55:	dd          	im -35
+     f56:	38          	neqbranch
+
+00000f57 <.LM308>:
+     f57:	80          	im 0
+     f58:	fb          	im -5
+     f59:	c0          	im -64
+     f5a:	08          	load
+     f5b:	70          	loadsp 0
+     f5c:	33          	loadb
+     f5d:	70          	loadsp 0
+     f5e:	81          	im 1
+     f5f:	ff          	im -1
+     f60:	06          	and
+
+00000f61 <.LM309>:
+     f61:	9a          	im 26
+     f62:	3d          	pushspadd
+     f63:	59          	storesp 36
+     f64:	5c          	storesp 48
+     f65:	51          	storesp 4
+     f66:	54          	storesp 16
+     f67:	a1          	im 33
+     f68:	53          	storesp 12
+     f69:	80          	im 0
+     f6a:	f4          	im -12
+     f6b:	d8          	im -40
+     f6c:	52          	storesp 8
+     f6d:	75          	loadsp 20
+     f6e:	51          	storesp 4
+     f6f:	80          	im 0
+     f70:	d4          	im -44
+     f71:	97          	im 23
+     f72:	3f          	callpcrel
+
+00000f73 <.LM310>:
+     f73:	80          	im 0
+     f74:	58          	storesp 32
+
+00000f75 <.L229>:
+     f75:	86          	im 6
+     f76:	b8          	im 56
+     f77:	80          	im 0
+     f78:	18          	addsp 32
+     f79:	78          	loadsp 32
+     f7a:	17          	addsp 28
+     f7b:	55          	storesp 20
+     f7c:	55          	storesp 20
+     f7d:	73          	loadsp 12
+     f7e:	33          	loadb
+     f7f:	75          	loadsp 20
+     f80:	34          	storeb
+
+00000f81 <.LM312>:
+     f81:	81          	im 1
+     f82:	18          	addsp 32
+     f83:	58          	storesp 32
+     f84:	77          	loadsp 28
+     f85:	a1          	im 33
+     f86:	2e          	eq
+     f87:	09          	not
+     f88:	81          	im 1
+     f89:	06          	and
+     f8a:	ea          	im -22
+     f8b:	38          	neqbranch
+
+00000f8c <.LM313>:
+     f8c:	80          	im 0
+     f8d:	fb          	im -5
+     f8e:	e0          	im -32
+     f8f:	08          	load
+     f90:	54          	storesp 16
+     f91:	80          	im 0
+     f92:	74          	loadsp 16
+     f93:	34          	storeb
+
+00000f94 <.LM314>:
+     f94:	80          	im 0
+     f95:	fb          	im -5
+     f96:	dc          	im -36
+     f97:	08          	load
+     f98:	54          	storesp 16
+     f99:	ff          	im -1
+     f9a:	9c          	im 28
+     f9b:	74          	loadsp 16
+     f9c:	34          	storeb
+
+00000f9d <.LM315>:
+     f9d:	80          	im 0
+     f9e:	fb          	im -5
+     f9f:	d8          	im -40
+     fa0:	08          	load
+     fa1:	54          	storesp 16
+     fa2:	80          	im 0
+     fa3:	74          	loadsp 16
+     fa4:	34          	storeb
+
+00000fa5 <.LM316>:
+     fa5:	80          	im 0
+     fa6:	fb          	im -5
+     fa7:	d4          	im -44
+     fa8:	08          	load
+     fa9:	54          	storesp 16
+     faa:	8f          	im 15
+     fab:	74          	loadsp 16
+     fac:	34          	storeb
+
+00000fad <.LM317>:
+     fad:	80          	im 0
+     fae:	fb          	im -5
+     faf:	d0          	im -48
+     fb0:	08          	load
+     fb1:	54          	storesp 16
+     fb2:	80          	im 0
+     fb3:	74          	loadsp 16
+     fb4:	34          	storeb
+
+00000fb5 <.LM318>:
+     fb5:	80          	im 0
+     fb6:	fb          	im -5
+     fb7:	cc          	im -52
+     fb8:	08          	load
+     fb9:	54          	storesp 16
+     fba:	80          	im 0
+     fbb:	74          	loadsp 16
+     fbc:	34          	storeb
+
+00000fbd <.LM319>:
+     fbd:	80          	im 0
+     fbe:	fb          	im -5
+     fbf:	b8          	im 56
+     fc0:	08          	load
+     fc1:	54          	storesp 16
+     fc2:	e0          	im -32
+     fc3:	74          	loadsp 16
+     fc4:	34          	storeb
+
+00000fc5 <.LM320>:
+     fc5:	80          	im 0
+     fc6:	fb          	im -5
+     fc7:	b0          	im 48
+     fc8:	08          	load
+     fc9:	54          	storesp 16
+     fca:	a2          	im 34
+     fcb:	74          	loadsp 16
+     fcc:	34          	storeb
+
+00000fcd <.LM321>:
+     fcd:	80          	im 0
+     fce:	fb          	im -5
+     fcf:	c0          	im -64
+     fd0:	08          	load
+     fd1:	54          	storesp 16
+     fd2:	ff          	im -1
+     fd3:	74          	loadsp 16
+     fd4:	34          	storeb
+
+00000fd5 <.LM322>:
+     fd5:	80          	im 0
+     fd6:	fb          	im -5
+     fd7:	ac          	im 44
+     fd8:	08          	load
+     fd9:	54          	storesp 16
+     fda:	83          	im 3
+     fdb:	74          	loadsp 16
+     fdc:	34          	storeb
+
+00000fdd <.LM323>:
+     fdd:	80          	im 0
+     fde:	fb          	im -5
+     fdf:	b4          	im 52
+     fe0:	08          	load
+     fe1:	54          	storesp 16
+     fe2:	82          	im 2
+     fe3:	74          	loadsp 16
+     fe4:	34          	storeb
+
+00000fe5 <.L360>:
+     fe5:	fd          	im -3
+     fe6:	5d          	storesp 52
+
+00000fe7 <.L366>:
+     fe7:	87          	im 7
+     fe8:	a9          	im 41
+     fe9:	c0          	im -64
+     fea:	51          	storesp 4
+     feb:	e9          	im -23
+     fec:	c6          	im -58
+     fed:	3f          	callpcrel
+
+00000fee <.LM325>:
+     fee:	80          	im 0
+     fef:	c5          	im -59
+     ff0:	d3          	im -45
+     ff1:	3f          	callpcrel
+
+00000ff2 <.LM326>:
+     ff2:	80          	im 0
+     ff3:	58          	storesp 32
+
+00000ff4 <.L235>:
+     ff4:	80          	im 0
+     ff5:	0b          	nop
+     ff6:	86          	im 6
+     ff7:	b8          	im 56
+     ff8:	c0          	im -64
+     ff9:	19          	addsp 36
+     ffa:	34          	storeb
+
+00000ffb <.LM328>:
+     ffb:	81          	im 1
+     ffc:	18          	addsp 32
+     ffd:	58          	storesp 32
+     ffe:	77          	loadsp 28
+     fff:	87          	im 7
+    1000:	c0          	im -64
+    1001:	2e          	eq
+    1002:	09          	not
+    1003:	81          	im 1
+    1004:	06          	and
+    1005:	ee          	im -18
+    1006:	38          	neqbranch
+
+00001007 <.LM329>:
+    1007:	0b          	nop
+    1008:	0b          	nop
+    1009:	80          	im 0
+    100a:	f6          	im -10
+    100b:	a4          	im 36
+    100c:	51          	storesp 4
+    100d:	80          	im 0
+    100e:	c7          	im -57
+    100f:	dd          	im -35
+    1010:	3f          	callpcrel
+
+00001011 <.LM330>:
+    1011:	0b          	nop
+    1012:	0b          	nop
+    1013:	80          	im 0
+    1014:	f6          	im -10
+    1015:	b8          	im 56
+    1016:	51          	storesp 4
+    1017:	80          	im 0
+    1018:	c7          	im -57
+    1019:	d3          	im -45
+    101a:	3f          	callpcrel
+
+0000101b <.LM331>:
+    101b:	0b          	nop
+    101c:	0b          	nop
+    101d:	80          	im 0
+    101e:	f6          	im -10
+    101f:	cc          	im -52
+    1020:	51          	storesp 4
+    1021:	80          	im 0
+    1022:	c7          	im -57
+    1023:	c9          	im -55
+    1024:	3f          	callpcrel
+
+00001025 <.LM332>:
+    1025:	80          	im 0
+    1026:	fc          	im -4
+    1027:	c4          	im -60
+    1028:	08          	load
+    1029:	70          	loadsp 0
+    102a:	08          	load
+    102b:	70          	loadsp 0
+    102c:	88          	im 8
+    102d:	2c          	ashiftright
+    102e:	8f          	im 15
+    102f:	06          	and
+    1030:	57          	storesp 28
+    1031:	55          	storesp 20
+    1032:	56          	storesp 24
+
+00001033 <.LM333>:
+    1033:	78          	loadsp 32
+    1034:	b3          	im 51
+    1035:	38          	neqbranch
+
+00001036 <.LM334>:
+    1036:	76          	loadsp 24
+    1037:	80          	im 0
+    1038:	2e          	eq
+    1039:	a7          	im 39
+    103a:	38          	neqbranch
+
+0000103b <.LM335>:
+    103b:	75          	loadsp 20
+    103c:	08          	load
+    103d:	77          	loadsp 28
+    103e:	16          	addsp 24
+    103f:	83          	im 3
+    1040:	06          	and
+    1041:	71          	loadsp 4
+    1042:	e1          	im -31
+    1043:	ff          	im -1
+    1044:	06          	and
+    1045:	71          	loadsp 4
+    1046:	88          	im 8
+    1047:	2b          	ashiftleft
+    1048:	07          	or
+    1049:	78          	loadsp 32
+    104a:	0c          	store
+
+0000104b <.LM336>:
+    104b:	7a          	loadsp 40
+
+0000104c <.LM337>:
+    104c:	7b          	loadsp 44
+    104d:	5a          	storesp 40
+    104e:	5e          	storesp 56
+    104f:	56          	storesp 24
+    1050:	54          	storesp 16
+
+00001051 <.LM338>:
+    1051:	87          	im 7
+    1052:	a9          	im 41
+    1053:	c0          	im -64
+    1054:	51          	storesp 4
+    1055:	e8          	im -24
+    1056:	dc          	im -36
+    1057:	3f          	callpcrel
+
+00001058 <.LM339>:
+    1058:	80          	im 0
+    1059:	c4          	im -60
+    105a:	e9          	im -23
+    105b:	3f          	callpcrel
+
+0000105c <.LM340>:
+    105c:	80          	im 0
+    105d:	58          	storesp 32
+    105e:	ff          	im -1
+    105f:	94          	im 20
+    1060:	39          	poppcrel
+
+00001061 <.L237>:
+    1061:	81          	im 1
+    1062:	80          	im 0
+    1063:	51          	storesp 4
+    1064:	80          	im 0
+    1065:	c7          	im -57
+    1066:	80          	im 0
+    1067:	3f          	callpcrel
+
+00001068 <.L236>:
+    1068:	74          	loadsp 16
+    1069:	81          	im 1
+    106a:	2e          	eq
+    106b:	89          	im 9
+    106c:	93          	im 19
+    106d:	38          	neqbranch
+    106e:	81          	im 1
+    106f:	75          	loadsp 20
+    1070:	25          	lessthanorequal
+    1071:	88          	im 8
+    1072:	d4          	im -44
+    1073:	38          	neqbranch
+    1074:	74          	loadsp 16
+    1075:	82          	im 2
+    1076:	2e          	eq
+    1077:	88          	im 8
+    1078:	8b          	im 11
+    1079:	38          	neqbranch
+    107a:	74          	loadsp 16
+    107b:	83          	im 3
+    107c:	2e          	eq
+    107d:	86          	im 6
+    107e:	9a          	im 26
+    107f:	38          	neqbranch
+
+00001080 <.L243>:
+    1080:	0b          	nop
+    1081:	0b          	nop
+    1082:	80          	im 0
+    1083:	f6          	im -10
+    1084:	d4          	im -44
+    1085:	51          	storesp 4
+    1086:	80          	im 0
+    1087:	c6          	im -58
+    1088:	e4          	im -28
+    1089:	3f          	callpcrel
+
+0000108a <.LM344>:
+    108a:	0b          	nop
+    108b:	0b          	nop
+    108c:	80          	im 0
+    108d:	f9          	im -7
+    108e:	c4          	im -60
+    108f:	51          	storesp 4
+    1090:	80          	im 0
+    1091:	c6          	im -58
+    1092:	da          	im -38
+    1093:	3f          	callpcrel
+
+00001094 <.LM345>:
+    1094:	0b          	nop
+    1095:	0b          	nop
+    1096:	80          	im 0
+    1097:	f6          	im -10
+    1098:	dc          	im -36
+    1099:	51          	storesp 4
+    109a:	80          	im 0
+    109b:	c6          	im -58
+    109c:	d0          	im -48
+    109d:	3f          	callpcrel
+
+0000109e <.LM346>:
+    109e:	80          	im 0
+    109f:	fc          	im -4
+    10a0:	c4          	im -60
+    10a1:	08          	load
+    10a2:	70          	loadsp 0
+    10a3:	08          	load
+    10a4:	70          	loadsp 0
+    10a5:	8c          	im 12
+    10a6:	2c          	ashiftright
+    10a7:	8f          	im 15
+    10a8:	06          	and
+    10a9:	57          	storesp 28
+    10aa:	55          	storesp 20
+    10ab:	56          	storesp 24
+
+000010ac <.LM347>:
+    10ac:	78          	loadsp 32
+    10ad:	81          	im 1
+    10ae:	2e          	eq
+    10af:	83          	im 3
+    10b0:	a2          	im 34
+    10b1:	38          	neqbranch
+
+000010b2 <.L245>:
+    10b2:	74          	loadsp 16
+    10b3:	81          	im 1
+    10b4:	2e          	eq
+    10b5:	87          	im 7
+    10b6:	9c          	im 28
+    10b7:	38          	neqbranch
+    10b8:	81          	im 1
+    10b9:	75          	loadsp 20
+    10ba:	25          	lessthanorequal
+    10bb:	86          	im 6
+    10bc:	e1          	im -31
+    10bd:	38          	neqbranch
+    10be:	74          	loadsp 16
+    10bf:	82          	im 2
+    10c0:	2e          	eq
+    10c1:	8c          	im 12
+    10c2:	a9          	im 41
+    10c3:	38          	neqbranch
+    10c4:	74          	loadsp 16
+    10c5:	83          	im 3
+    10c6:	2e          	eq
+    10c7:	8c          	im 12
+    10c8:	e2          	im -30
+    10c9:	38          	neqbranch
+
+000010ca <.L252>:
+    10ca:	0b          	nop
+    10cb:	0b          	nop
+    10cc:	80          	im 0
+    10cd:	f6          	im -10
+    10ce:	d4          	im -44
+    10cf:	51          	storesp 4
+    10d0:	80          	im 0
+    10d1:	c6          	im -58
+    10d2:	9a          	im 26
+    10d3:	3f          	callpcrel
+
+000010d4 <.LM350>:
+    10d4:	0b          	nop
+    10d5:	0b          	nop
+    10d6:	80          	im 0
+    10d7:	f9          	im -7
+    10d8:	c4          	im -60
+    10d9:	51          	storesp 4
+    10da:	80          	im 0
+    10db:	c6          	im -58
+    10dc:	90          	im 16
+    10dd:	3f          	callpcrel
+
+000010de <.LM351>:
+    10de:	0b          	nop
+    10df:	0b          	nop
+    10e0:	80          	im 0
+    10e1:	f6          	im -10
+    10e2:	e8          	im -24
+    10e3:	51          	storesp 4
+    10e4:	80          	im 0
+    10e5:	c6          	im -58
+    10e6:	86          	im 6
+    10e7:	3f          	callpcrel
+
+000010e8 <.LM352>:
+    10e8:	80          	im 0
+    10e9:	fc          	im -4
+    10ea:	c4          	im -60
+    10eb:	08          	load
+    10ec:	70          	loadsp 0
+    10ed:	08          	load
+    10ee:	bf          	im 63
+    10ef:	06          	and
+    10f0:	56          	storesp 24
+    10f1:	56          	storesp 24
+
+000010f2 <.LM353>:
+    10f2:	78          	loadsp 32
+    10f3:	82          	im 2
+    10f4:	2e          	eq
+    10f5:	85          	im 5
+    10f6:	ff          	im -1
+    10f7:	38          	neqbranch
+
+000010f8 <.L254>:
+    10f8:	81          	im 1
+    10f9:	15          	addsp 20
+    10fa:	70          	loadsp 0
+    10fb:	83          	im 3
+    10fc:	c1          	im -63
+    10fd:	9c          	im 28
+    10fe:	35          	div
+    10ff:	70          	loadsp 0
+    1100:	83          	im 3
+    1101:	ff          	im -1
+    1102:	ff          	im -1
+    1103:	06          	and
+    1104:	53          	storesp 12
+    1105:	51          	storesp 4
+    1106:	54          	storesp 16
+    1107:	80          	im 0
+    1108:	c6          	im -58
+    1109:	f2          	im -14
+    110a:	3f          	callpcrel
+
+0000110b <.LM355>:
+    110b:	0b          	nop
+    110c:	0b          	nop
+    110d:	80          	im 0
+    110e:	f6          	im -10
+    110f:	f0          	im -16
+    1110:	51          	storesp 4
+    1111:	80          	im 0
+    1112:	c5          	im -59
+    1113:	d9          	im -39
+    1114:	3f          	callpcrel
+
+00001115 <.LM356>:
+    1115:	78          	loadsp 32
+    1116:	83          	im 3
+    1117:	2e          	eq
+    1118:	85          	im 5
+    1119:	b7          	im 55
+    111a:	38          	neqbranch
+
+0000111b <.L257>:
+    111b:	83          	im 3
+    111c:	e3          	im -29
+    111d:	98          	im 24
+    111e:	51          	storesp 4
+    111f:	80          	im 0
+    1120:	c5          	im -59
+    1121:	cb          	im -53
+    1122:	3f          	callpcrel
+
+00001123 <.LM358>:
+    1123:	0b          	nop
+    1124:	0b          	nop
+    1125:	80          	im 0
+    1126:	f6          	im -10
+    1127:	fc          	im -4
+    1128:	51          	storesp 4
+    1129:	80          	im 0
+    112a:	c5          	im -59
+    112b:	c1          	im -63
+    112c:	3f          	callpcrel
+
+0000112d <.LM359>:
+    112d:	78          	loadsp 32
+    112e:	84          	im 4
+    112f:	2e          	eq
+    1130:	84          	im 4
+    1131:	c2          	im -62
+    1132:	38          	neqbranch
+
+00001133 <.L258>:
+    1133:	83          	im 3
+    1134:	e3          	im -29
+    1135:	d8          	im -40
+    1136:	51          	storesp 4
+    1137:	80          	im 0
+    1138:	c5          	im -59
+    1139:	b3          	im 51
+    113a:	3f          	callpcrel
+
+0000113b <.LM361>:
+    113b:	0b          	nop
+    113c:	0b          	nop
+    113d:	80          	im 0
+    113e:	f7          	im -9
+    113f:	84          	im 4
+    1140:	51          	storesp 4
+    1141:	80          	im 0
+    1142:	c5          	im -59
+    1143:	a9          	im 41
+    1144:	3f          	callpcrel
+
+00001145 <.LM362>:
+    1145:	78          	loadsp 32
+    1146:	85          	im 5
+    1147:	2e          	eq
+    1148:	84          	im 4
+    1149:	85          	im 5
+    114a:	38          	neqbranch
+
+0000114b <.L259>:
+    114b:	83          	im 3
+    114c:	e2          	im -30
+    114d:	c8          	im -56
+    114e:	51          	storesp 4
+    114f:	80          	im 0
+    1150:	c5          	im -59
+    1151:	9b          	im 27
+    1152:	3f          	callpcrel
+
+00001153 <.LM364>:
+    1153:	0b          	nop
+    1154:	0b          	nop
+    1155:	80          	im 0
+    1156:	f7          	im -9
+    1157:	8c          	im 12
+    1158:	51          	storesp 4
+    1159:	80          	im 0
+    115a:	c5          	im -59
+    115b:	91          	im 17
+    115c:	3f          	callpcrel
+
+0000115d <.LM365>:
+    115d:	78          	loadsp 32
+    115e:	86          	im 6
+    115f:	2e          	eq
+    1160:	85          	im 5
+    1161:	b3          	im 51
+    1162:	38          	neqbranch
+
+00001163 <.L260>:
+    1163:	83          	im 3
+    1164:	e0          	im -32
+    1165:	b8          	im 56
+    1166:	51          	storesp 4
+    1167:	80          	im 0
+    1168:	c5          	im -59
+    1169:	83          	im 3
+    116a:	3f          	callpcrel
+
+0000116b <.LM367>:
+    116b:	7c          	loadsp 48
+    116c:	83          	im 3
+    116d:	26          	ulessthan
+    116e:	93          	im 19
+    116f:	38          	neqbranch
+
+00001170 <.LM368>:
+    1170:	7b          	loadsp 44
+    1171:	81          	im 1
+    1172:	2e          	eq
+    1173:	87          	im 7
+    1174:	c0          	im -64
+    1175:	38          	neqbranch
+
+00001176 <.LM369>:
+    1176:	76          	loadsp 24
+    1177:	81          	im 1
+    1178:	2e          	eq
+    1179:	8a          	im 10
+    117a:	8b          	im 11
+    117b:	38          	neqbranch
+
+0000117c <.LM370>:
+    117c:	76          	loadsp 24
+    117d:	ff          	im -1
+    117e:	2e          	eq
+    117f:	89          	im 9
+    1180:	9f          	im 31
+    1181:	38          	neqbranch
+
+00001182 <.L261>:
+    1182:	78          	loadsp 32
+    1183:	87          	im 7
+    1184:	2e          	eq
+    1185:	88          	im 8
+    1186:	9b          	im 27
+    1187:	38          	neqbranch
+
+00001188 <.L279>:
+    1188:	0b          	nop
+    1189:	0b          	nop
+    118a:	80          	im 0
+    118b:	f7          	im -9
+    118c:	94          	im 20
+    118d:	51          	storesp 4
+    118e:	80          	im 0
+    118f:	c4          	im -60
+    1190:	dc          	im -36
+    1191:	3f          	callpcrel
+
+00001192 <.LM373>:
+    1192:	78          	loadsp 32
+    1193:	87          	im 7
+    1194:	2e          	eq
+    1195:	86          	im 6
+    1196:	a2          	im 34
+    1197:	38          	neqbranch
+
+00001198 <.LM374>:
+    1198:	78          	loadsp 32
+    1199:	88          	im 8
+    119a:	2e          	eq
+    119b:	88          	im 8
+    119c:	8e          	im 14
+    119d:	38          	neqbranch
+
+0000119e <.L282>:
+    119e:	0b          	nop
+    119f:	0b          	nop
+    11a0:	80          	im 0
+    11a1:	f7          	im -9
+    11a2:	9c          	im 28
+    11a3:	51          	storesp 4
+    11a4:	80          	im 0
+    11a5:	c4          	im -60
+    11a6:	c6          	im -58
+    11a7:	3f          	callpcrel
+
+000011a8 <.LM376>:
+    11a8:	78          	loadsp 32
+    11a9:	88          	im 8
+    11aa:	2e          	eq
+    11ab:	81          	im 1
+    11ac:	d3          	im -45
+    11ad:	38          	neqbranch
+
+000011ae <.L283>:
+    11ae:	80          	im 0
+
+000011af <.LM378>:
+    11af:	70          	loadsp 0
+
+000011b0 <.LM379>:
+    11b0:	80          	im 0
+    11b1:	fb          	im -5
+    11b2:	c4          	im -60
+    11b3:	08          	load
+    11b4:	70          	loadsp 0
+    11b5:	33          	loadb
+    11b6:	70          	loadsp 0
+    11b7:	81          	im 1
+    11b8:	ff          	im -1
+    11b9:	06          	and
+
+000011ba <.LM380>:
+    11ba:	70          	loadsp 0
+    11bb:	81          	im 1
+    11bc:	2a          	lshiftright
+    11bd:	81          	im 1
+    11be:	32          	xor
+    11bf:	81          	im 1
+    11c0:	06          	and
+    11c1:	5b          	storesp 44
+    11c2:	59          	storesp 36
+    11c3:	51          	storesp 4
+    11c4:	56          	storesp 24
+    11c5:	58          	storesp 32
+    11c6:	5c          	storesp 48
+    11c7:	75          	loadsp 20
+    11c8:	80          	im 0
+    11c9:	e9          	im -23
+    11ca:	38          	neqbranch
+
+000011cb <.L287>:
+    11cb:	74          	loadsp 16
+    11cc:	81          	im 1
+    11cd:	32          	xor
+    11ce:	70          	loadsp 0
+    11cf:	81          	im 1
+    11d0:	06          	and
+    11d1:	51          	storesp 4
+    11d2:	54          	storesp 16
+    11d3:	73          	loadsp 12
+    11d4:	88          	im 8
+    11d5:	b0          	im 48
+    11d6:	38          	neqbranch
+
+000011d7 <.LM382>:
+    11d7:	74          	loadsp 16
+    11d8:	83          	im 3
+    11d9:	2a          	lshiftright
+    11da:	81          	im 1
+    11db:	32          	xor
+    11dc:	70          	loadsp 0
+    11dd:	81          	im 1
+    11de:	06          	and
+    11df:	51          	storesp 4
+    11e0:	54          	storesp 16
+    11e1:	73          	loadsp 12
+    11e2:	88          	im 8
+    11e3:	91          	im 17
+    11e4:	38          	neqbranch
+
+000011e5 <.LM383>:
+    11e5:	74          	loadsp 16
+    11e6:	82          	im 2
+    11e7:	2a          	lshiftright
+    11e8:	81          	im 1
+    11e9:	32          	xor
+    11ea:	70          	loadsp 0
+    11eb:	81          	im 1
+    11ec:	06          	and
+    11ed:	51          	storesp 4
+    11ee:	54          	storesp 16
+    11ef:	73          	loadsp 12
+    11f0:	87          	im 7
+    11f1:	f2          	im -14
+    11f2:	38          	neqbranch
+
+000011f3 <.LM384>:
+    11f3:	80          	im 0
+    11f4:	fb          	im -5
+    11f5:	bc          	im 60
+    11f6:	08          	load
+    11f7:	70          	loadsp 0
+    11f8:	33          	loadb
+    11f9:	70          	loadsp 0
+    11fa:	81          	im 1
+    11fb:	ff          	im -1
+    11fc:	06          	and
+    11fd:	51          	storesp 4
+    11fe:	55          	storesp 20
+    11ff:	55          	storesp 20
+    1200:	73          	loadsp 12
+    1201:	80          	im 0
+    1202:	2e          	eq
+    1203:	87          	im 7
+    1204:	c1          	im -63
+    1205:	38          	neqbranch
+
+00001206 <.LM385>:
+    1206:	80          	im 0
+    1207:	c1          	im -63
+    1208:	bb          	im 59
+    1209:	3f          	callpcrel
+
+0000120a <.LM386>:
+    120a:	80          	im 0
+    120b:	fb          	im -5
+    120c:	c8          	im -56
+    120d:	08          	load
+    120e:	80          	im 0
+    120f:	fb          	im -5
+    1210:	d8          	im -40
+    1211:	08          	load
+    1212:	55          	storesp 20
+    1213:	55          	storesp 20
+    1214:	74          	loadsp 16
+    1215:	33          	loadb
+    1216:	74          	loadsp 16
+    1217:	34          	storeb
+
+00001218 <.LM387>:
+    1218:	80          	im 0
+    1219:	fb          	im -5
+    121a:	c4          	im -60
+    121b:	08          	load
+    121c:	70          	loadsp 0
+    121d:	33          	loadb
+    121e:	70          	loadsp 0
+    121f:	81          	im 1
+    1220:	ff          	im -1
+    1221:	06          	and
+
+00001222 <.LM388>:
+    1222:	70          	loadsp 0
+    1223:	81          	im 1
+    1224:	2a          	lshiftright
+    1225:	81          	im 1
+    1226:	32          	xor
+    1227:	81          	im 1
+    1228:	06          	and
+    1229:	59          	storesp 36
+    122a:	57          	storesp 28
+    122b:	51          	storesp 4
+    122c:	54          	storesp 16
+    122d:	75          	loadsp 20
+    122e:	80          	im 0
+    122f:	2e          	eq
+    1230:	ff          	im -1
+    1231:	99          	im 25
+    1232:	38          	neqbranch
+
+00001233 <.L388>:
+    1233:	81          	im 1
+    1234:	19          	addsp 36
+    1235:	fd          	im -3
+    1236:	11          	addsp 4
+    1237:	5e          	storesp 56
+    1238:	59          	storesp 36
+
+00001239 <.LM390>:
+    1239:	88          	im 8
+    123a:	79          	loadsp 36
+    123b:	25          	lessthanorequal
+    123c:	fb          	im -5
+    123d:	a9          	im 41
+    123e:	38          	neqbranch
+    123f:	88          	im 8
+    1240:	59          	storesp 36
+    1241:	85          	im 5
+    1242:	5d          	storesp 52
+
+00001243 <.LM391>:
+    1243:	87          	im 7
+    1244:	a9          	im 41
+    1245:	c0          	im -64
+    1246:	51          	storesp 4
+    1247:	e4          	im -28
+    1248:	ea          	im -22
+    1249:	3f          	callpcrel
+
+0000124a <.LM392>:
+    124a:	80          	im 0
+    124b:	c0          	im -64
+    124c:	f7          	im -9
+    124d:	3f          	callpcrel
+
+0000124e <.LM393>:
+    124e:	80          	im 0
+    124f:	58          	storesp 32
+    1250:	fb          	im -5
+    1251:	a2          	im 34
+    1252:	39          	poppcrel
+
+00001253 <.L374>:
+    1253:	76          	loadsp 24
+    1254:	80          	im 0
+    1255:	2e          	eq
+    1256:	87          	im 7
+    1257:	bf          	im 63
+    1258:	38          	neqbranch
+
+00001259 <.LM395>:
+    1259:	75          	loadsp 20
+    125a:	08          	load
+    125b:	77          	loadsp 28
+    125c:	16          	addsp 24
+    125d:	83          	im 3
+    125e:	06          	and
+    125f:	71          	loadsp 4
+    1260:	fc          	im -4
+    1261:	9f          	im 31
+    1262:	ff          	im -1
+    1263:	06          	and
+    1264:	71          	loadsp 4
+    1265:	8c          	im 12
+    1266:	2b          	ashiftleft
+    1267:	07          	or
+
+00001268 <.LM396>:
+    1268:	78          	loadsp 32
+    1269:	0c          	store
+    126a:	56          	storesp 24
+    126b:	54          	storesp 16
+
+0000126c <.L361>:
+    126c:	80          	im 0
+
+0000126d <.LM398>:
+    126d:	70          	loadsp 0
+    126e:	58          	storesp 32
+    126f:	5c          	storesp 48
+
+00001270 <.L391>:
+    1270:	87          	im 7
+    1271:	a9          	im 41
+    1272:	c0          	im -64
+    1273:	51          	storesp 4
+    1274:	e4          	im -28
+    1275:	bd          	im 61
+    1276:	3f          	callpcrel
+
+00001277 <.LM400>:
+    1277:	80          	im 0
+    1278:	c0          	im -64
+    1279:	ca          	im -54
+    127a:	3f          	callpcrel
+
+0000127b <.LM401>:
+    127b:	80          	im 0
+    127c:	58          	storesp 32
+    127d:	fa          	im -6
+    127e:	f5          	im -11
+    127f:	39          	poppcrel
+
+00001280 <.L387>:
+    1280:	7b          	loadsp 44
+    1281:	81          	im 1
+    1282:	2e          	eq
+    1283:	09          	not
+    1284:	81          	im 1
+    1285:	06          	and
+    1286:	fe          	im -2
+    1287:	a6          	im 38
+    1288:	38          	neqbranch
+
+00001289 <.L231>:
+    1289:	80          	im 0
+    128a:	c0          	im -64
+    128b:	58          	storesp 32
+
+0000128c <.L303>:
+    128c:	86          	im 6
+    128d:	b8          	im 56
+    128e:	80          	im 0
+    128f:	18          	addsp 32
+    1290:	81          	im 1
+    1291:	9f          	im 31
+    1292:	e0          	im -32
+    1293:	80          	im 0
+    1294:	19          	addsp 36
+    1295:	55          	storesp 20
+    1296:	55          	storesp 20
+    1297:	73          	loadsp 12
+    1298:	33          	loadb
+    1299:	75          	loadsp 20
+    129a:	34          	storeb
+
+0000129b <.LM405>:
+    129b:	81          	im 1
+    129c:	18          	addsp 32
+    129d:	58          	storesp 32
+    129e:	77          	loadsp 28
+    129f:	88          	im 8
+    12a0:	80          	im 0
+    12a1:	2e          	eq
+    12a2:	09          	not
+    12a3:	81          	im 1
+    12a4:	06          	and
+    12a5:	e6          	im -26
+    12a6:	38          	neqbranch
+
+000012a7 <.LM406>:
+    12a7:	83          	im 3
+    12a8:	a0          	im 32
+    12a9:	80          	im 0
+    12aa:	58          	storesp 32
+
+000012ab <.L307>:
+    12ab:	84          	im 4
+    12ac:	80          	im 0
+    12ad:	80          	im 0
+    12ae:	18          	addsp 32
+    12af:	81          	im 1
+    12b0:	9c          	im 28
+    12b1:	80          	im 0
+    12b2:	80          	im 0
+    12b3:	19          	addsp 36
+    12b4:	55          	storesp 20
+    12b5:	55          	storesp 20
+    12b6:	73          	loadsp 12
+    12b7:	33          	loadb
+    12b8:	75          	loadsp 20
+    12b9:	34          	storeb
+
+000012ba <.LM408>:
+    12ba:	81          	im 1
+    12bb:	18          	addsp 32
+    12bc:	58          	storesp 32
+    12bd:	77          	loadsp 28
+    12be:	83          	im 3
+    12bf:	a0          	im 32
+    12c0:	9f          	im 31
+    12c1:	2e          	eq
+    12c2:	09          	not
+    12c3:	81          	im 1
+    12c4:	06          	and
+    12c5:	e5          	im -27
+    12c6:	38          	neqbranch
+
+000012c7 <.LM409>:
+    12c7:	83          	im 3
+    12c8:	a4          	im 36
+    12c9:	80          	im 0
+    12ca:	58          	storesp 32
+
+000012cb <.L311>:
+    12cb:	84          	im 4
+    12cc:	80          	im 0
+    12cd:	80          	im 0
+    12ce:	18          	addsp 32
+    12cf:	81          	im 1
+    12d0:	9c          	im 28
+    12d1:	80          	im 0
+    12d2:	80          	im 0
+    12d3:	19          	addsp 36
+    12d4:	55          	storesp 20
+    12d5:	55          	storesp 20
+    12d6:	73          	loadsp 12
+    12d7:	33          	loadb
+    12d8:	75          	loadsp 20
+    12d9:	34          	storeb
+
+000012da <.LM411>:
+    12da:	81          	im 1
+    12db:	18          	addsp 32
+    12dc:	58          	storesp 32
+    12dd:	77          	loadsp 28
+    12de:	83          	im 3
+    12df:	a4          	im 36
+    12e0:	9f          	im 31
+    12e1:	2e          	eq
+    12e2:	09          	not
+    12e3:	81          	im 1
+    12e4:	06          	and
+    12e5:	e5          	im -27
+    12e6:	38          	neqbranch
+
+000012e7 <.LM412>:
+    12e7:	83          	im 3
+    12e8:	a8          	im 40
+    12e9:	80          	im 0
+    12ea:	58          	storesp 32
+
+000012eb <.L315>:
+    12eb:	84          	im 4
+    12ec:	80          	im 0
+    12ed:	80          	im 0
+    12ee:	18          	addsp 32
+    12ef:	81          	im 1
+    12f0:	9c          	im 28
+    12f1:	80          	im 0
+    12f2:	80          	im 0
+    12f3:	19          	addsp 36
+    12f4:	55          	storesp 20
+    12f5:	55          	storesp 20
+    12f6:	73          	loadsp 12
+    12f7:	33          	loadb
+    12f8:	75          	loadsp 20
+    12f9:	34          	storeb
+
+000012fa <.LM414>:
+    12fa:	81          	im 1
+    12fb:	18          	addsp 32
+    12fc:	58          	storesp 32
+    12fd:	77          	loadsp 28
+    12fe:	83          	im 3
+    12ff:	a8          	im 40
+    1300:	8f          	im 15
+    1301:	2e          	eq
+    1302:	09          	not
+    1303:	81          	im 1
+    1304:	06          	and
+    1305:	e5          	im -27
+    1306:	38          	neqbranch
+
+00001307 <.LM415>:
+    1307:	80          	im 0
+    1308:	fb          	im -5
+    1309:	c0          	im -64
+    130a:	08          	load
+    130b:	54          	storesp 16
+    130c:	79          	loadsp 36
+    130d:	74          	loadsp 16
+    130e:	34          	storeb
+
+0000130f <.LM416>:
+    130f:	83          	im 3
+    1310:	e0          	im -32
+    1311:	ac          	im 44
+    1312:	08          	load
+    1313:	51          	storesp 4
+    1314:	bf          	im 63
+    1315:	c7          	im -57
+    1316:	3f          	callpcrel
+
+00001317 <.LM417>:
+    1317:	7a          	loadsp 40
+    1318:	80          	im 0
+    1319:	2e          	eq
+    131a:	a7          	im 39
+    131b:	38          	neqbranch
+
+0000131c <.LM418>:
+    131c:	0b          	nop
+    131d:	0b          	nop
+    131e:	80          	im 0
+    131f:	f6          	im -10
+    1320:	98          	im 24
+    1321:	51          	storesp 4
+    1322:	80          	im 0
+    1323:	c1          	im -63
+    1324:	c8          	im -56
+    1325:	3f          	callpcrel
+
+00001326 <.LM419>:
+    1326:	9e          	im 30
+    1327:	c2          	im -62
+    1328:	a0          	im 32
+    1329:	51          	storesp 4
+    132a:	e3          	im -29
+    132b:	87          	im 7
+    132c:	3f          	callpcrel
+
+0000132d <.LM420>:
+    132d:	80          	im 0
+    132e:	51          	storesp 4
+    132f:	e6          	im -26
+    1330:	b9          	im 57
+    1331:	3f          	callpcrel
+
+00001332 <.LM421>:
+    1332:	80          	im 0
+    1333:	fb          	im -5
+    1334:	e4          	im -28
+    1335:	08          	load
+    1336:	54          	storesp 16
+    1337:	80          	im 0
+    1338:	74          	loadsp 16
+    1339:	34          	storeb
+
+0000133a <.LM422>:
+    133a:	e5          	im -27
+    133b:	b4          	im 52
+    133c:	3f          	callpcrel
+
+0000133d <.LM423>:
+    133d:	81          	im 1
+    133e:	51          	storesp 4
+    133f:	e6          	im -26
+    1340:	a9          	im 41
+    1341:	3f          	callpcrel
+
+00001342 <.L316>:
+    1342:	80          	im 0
+    1343:	51          	storesp 4
+    1344:	e6          	im -26
+    1345:	c8          	im -56
+    1346:	3f          	callpcrel
+    1347:	80          	im 0
+    1348:	fc          	im -4
+    1349:	b8          	im 56
+    134a:	08          	load
+    134b:	55          	storesp 20
+    134c:	f4          	im -12
+    134d:	a6          	im 38
+    134e:	39          	poppcrel
+
+0000134f <.L379>:
+    134f:	81          	im 1
+    1350:	80          	im 0
+    1351:	51          	storesp 4
+    1352:	80          	im 0
+    1353:	c1          	im -63
+    1354:	92          	im 18
+    1355:	3f          	callpcrel
+
+00001356 <.LM426>:
+    1356:	83          	im 3
+    1357:	e2          	im -30
+    1358:	c8          	im -56
+    1359:	51          	storesp 4
+    135a:	80          	im 0
+    135b:	c1          	im -63
+    135c:	90          	im 16
+    135d:	3f          	callpcrel
+
+0000135e <.LM427>:
+    135e:	0b          	nop
+    135f:	0b          	nop
+    1360:	80          	im 0
+    1361:	f7          	im -9
+    1362:	8c          	im 12
+    1363:	51          	storesp 4
+    1364:	80          	im 0
+    1365:	c1          	im -63
+    1366:	86          	im 6
+    1367:	3f          	callpcrel
+
+00001368 <.LM428>:
+    1368:	78          	loadsp 32
+    1369:	86          	im 6
+    136a:	2e          	eq
+    136b:	09          	not
+    136c:	81          	im 1
+    136d:	06          	and
+    136e:	fb          	im -5
+    136f:	f3          	im -13
+    1370:	38          	neqbranch
+    1371:	81          	im 1
+    1372:	a2          	im 34
+    1373:	39          	poppcrel
+
+00001374 <.L378>:
+    1374:	81          	im 1
+    1375:	80          	im 0
+    1376:	51          	storesp 4
+    1377:	80          	im 0
+    1378:	c0          	im -64
+    1379:	ed          	im -19
+    137a:	3f          	callpcrel
+
+0000137b <.LM430>:
+    137b:	83          	im 3
+    137c:	e3          	im -29
+    137d:	d8          	im -40
+    137e:	51          	storesp 4
+    137f:	80          	im 0
+    1380:	c0          	im -64
+    1381:	eb          	im -21
+    1382:	3f          	callpcrel
+
+00001383 <.LM431>:
+    1383:	0b          	nop
+    1384:	0b          	nop
+    1385:	80          	im 0
+    1386:	f7          	im -9
+    1387:	84          	im 4
+    1388:	51          	storesp 4
+    1389:	80          	im 0
+    138a:	c0          	im -64
+    138b:	e1          	im -31
+    138c:	3f          	callpcrel
+
+0000138d <.LM432>:
+    138d:	78          	loadsp 32
+    138e:	85          	im 5
+    138f:	2e          	eq
+    1390:	09          	not
+    1391:	81          	im 1
+    1392:	06          	and
+    1393:	fb          	im -5
+    1394:	b6          	im 54
+    1395:	38          	neqbranch
+    1396:	ff          	im -1
+    1397:	b7          	im 55
+    1398:	39          	poppcrel
+
+00001399 <.L242>:
+    1399:	0b          	nop
+    139a:	0b          	nop
+    139b:	80          	im 0
+    139c:	f7          	im -9
+    139d:	a4          	im 36
+    139e:	51          	storesp 4
+
+0000139f <.LM434>:
+    139f:	80          	im 0
+    13a0:	c0          	im -64
+    13a1:	cb          	im -53
+    13a2:	3f          	callpcrel
+
+000013a3 <.LM435>:
+    13a3:	0b          	nop
+    13a4:	0b          	nop
+    13a5:	80          	im 0
+    13a6:	f9          	im -7
+    13a7:	c4          	im -60
+    13a8:	51          	storesp 4
+    13a9:	80          	im 0
+    13aa:	c0          	im -64
+    13ab:	c1          	im -63
+    13ac:	3f          	callpcrel
+
+000013ad <.LM436>:
+    13ad:	0b          	nop
+    13ae:	0b          	nop
+    13af:	80          	im 0
+    13b0:	f6          	im -10
+    13b1:	dc          	im -36
+    13b2:	51          	storesp 4
+    13b3:	80          	im 0
+    13b4:	c0          	im -64
+    13b5:	b7          	im 55
+    13b6:	3f          	callpcrel
+
+000013b7 <.LM437>:
+    13b7:	80          	im 0
+    13b8:	fc          	im -4
+    13b9:	c4          	im -60
+    13ba:	08          	load
+    13bb:	70          	loadsp 0
+    13bc:	08          	load
+    13bd:	70          	loadsp 0
+    13be:	8c          	im 12
+    13bf:	2c          	ashiftright
+    13c0:	8f          	im 15
+    13c1:	06          	and
+    13c2:	57          	storesp 28
+    13c3:	55          	storesp 20
+    13c4:	56          	storesp 24
+
+000013c5 <.LM438>:
+    13c5:	78          	loadsp 32
+    13c6:	81          	im 1
+    13c7:	2e          	eq
+    13c8:	09          	not
+    13c9:	81          	im 1
+    13ca:	06          	and
+    13cb:	f9          	im -7
+    13cc:	e5          	im -27
+    13cd:	38          	neqbranch
+    13ce:	fd          	im -3
+    13cf:	83          	im 3
+    13d0:	39          	poppcrel
+
+000013d1 <.L377>:
+    13d1:	81          	im 1
+    13d2:	80          	im 0
+    13d3:	51          	storesp 4
+    13d4:	80          	im 0
+    13d5:	c0          	im -64
+    13d6:	90          	im 16
+    13d7:	3f          	callpcrel
+
+000013d8 <.LM440>:
+    13d8:	83          	im 3
+    13d9:	e3          	im -29
+    13da:	98          	im 24
+    13db:	51          	storesp 4
+    13dc:	80          	im 0
+    13dd:	c0          	im -64
+    13de:	8e          	im 14
+    13df:	3f          	callpcrel
+
+000013e0 <.LM441>:
+    13e0:	0b          	nop
+    13e1:	0b          	nop
+    13e2:	80          	im 0
+    13e3:	f6          	im -10
+    13e4:	fc          	im -4
+    13e5:	51          	storesp 4
+    13e6:	80          	im 0
+    13e7:	c0          	im -64
+    13e8:	84          	im 4
+    13e9:	3f          	callpcrel
+
+000013ea <.LM442>:
+    13ea:	78          	loadsp 32
+    13eb:	84          	im 4
+    13ec:	2e          	eq
+    13ed:	09          	not
+    13ee:	81          	im 1
+    13ef:	06          	and
+    13f0:	fa          	im -6
+    13f1:	c1          	im -63
+    13f2:	38          	neqbranch
+    13f3:	fe          	im -2
+    13f4:	ff          	im -1
+    13f5:	39          	poppcrel
+
+000013f6 <.L376>:
+    13f6:	76          	loadsp 24
+    13f7:	80          	im 0
+    13f8:	2e          	eq
+    13f9:	82          	im 2
+    13fa:	fa          	im -6
+    13fb:	38          	neqbranch
+
+000013fc <.LM444>:
+    13fc:	76          	loadsp 24
+    13fd:	15          	addsp 20
+
+000013fe <.LM445>:
+    13fe:	70          	loadsp 0
+    13ff:	09          	not
+    1400:	70          	loadsp 0
+    1401:	9f          	im 31
+    1402:	2c          	ashiftright
+    1403:	72          	loadsp 8
+    1404:	06          	and
+
+00001405 <.LM446>:
+    1405:	78          	loadsp 32
+    1406:	08          	load
+    1407:	52          	storesp 8
+    1408:	bf          	im 63
+    1409:	06          	and
+    140a:	71          	loadsp 4
+    140b:	c0          	im -64
+    140c:	06          	and
+    140d:	07          	or
+    140e:	78          	loadsp 32
+    140f:	0c          	store
+    1410:	55          	storesp 20
+    1411:	55          	storesp 20
+    1412:	fc          	im -4
+    1413:	d8          	im -40
+    1414:	39          	poppcrel
+
+00001415 <.L380>:
+    1415:	81          	im 1
+    1416:	80          	im 0
+    1417:	51          	storesp 4
+    1418:	bf          	im 63
+    1419:	cd          	im -51
+    141a:	3f          	callpcrel
+    141b:	fa          	im -6
+    141c:	c6          	im -58
+    141d:	39          	poppcrel
+
+0000141e <.L375>:
+    141e:	74          	loadsp 16
+    141f:	f9          	im -7
+    1420:	a9          	im 41
+    1421:	38          	neqbranch
+
+00001422 <.LM449>:
+    1422:	0b          	nop
+    1423:	0b          	nop
+    1424:	80          	im 0
+    1425:	f7          	im -9
+    1426:	b4          	im 52
+    1427:	51          	storesp 4
+
+00001428 <.LM450>:
+    1428:	bf          	im 63
+    1429:	c3          	im -61
+    142a:	3f          	callpcrel
+
+0000142b <.LM451>:
+    142b:	0b          	nop
+    142c:	0b          	nop
+    142d:	80          	im 0
+    142e:	f9          	im -7
+    142f:	c4          	im -60
+    1430:	51          	storesp 4
+    1431:	bf          	im 63
+    1432:	ba          	im 58
+    1433:	3f          	callpcrel
+
+00001434 <.LM452>:
+    1434:	0b          	nop
+    1435:	0b          	nop
+    1436:	80          	im 0
+    1437:	f6          	im -10
+    1438:	e8          	im -24
+    1439:	51          	storesp 4
+    143a:	bf          	im 63
+    143b:	b1          	im 49
+    143c:	3f          	callpcrel
+
+0000143d <.LM453>:
+    143d:	80          	im 0
+    143e:	fc          	im -4
+    143f:	c4          	im -60
+    1440:	08          	load
+    1441:	70          	loadsp 0
+    1442:	08          	load
+    1443:	bf          	im 63
+    1444:	06          	and
+    1445:	56          	storesp 24
+    1446:	56          	storesp 24
+
+00001447 <.LM454>:
+    1447:	78          	loadsp 32
+    1448:	82          	im 2
+    1449:	2e          	eq
+    144a:	09          	not
+    144b:	81          	im 1
+    144c:	06          	and
+    144d:	f9          	im -7
+    144e:	a9          	im 41
+    144f:	38          	neqbranch
+    1450:	ff          	im -1
+    1451:	a4          	im 36
+    1452:	39          	poppcrel
+
+00001453 <.L249>:
+    1453:	0b          	nop
+    1454:	0b          	nop
+    1455:	80          	im 0
+    1456:	f7          	im -9
+    1457:	c4          	im -60
+    1458:	51          	storesp 4
+
+00001459 <.LM456>:
+    1459:	bf          	im 63
+    145a:	92          	im 18
+    145b:	3f          	callpcrel
+
+0000145c <.LM457>:
+    145c:	0b          	nop
+    145d:	0b          	nop
+    145e:	80          	im 0
+    145f:	f9          	im -7
+    1460:	c4          	im -60
+    1461:	51          	storesp 4
+    1462:	bf          	im 63
+    1463:	89          	im 9
+    1464:	3f          	callpcrel
+
+00001465 <.LM458>:
+    1465:	0b          	nop
+    1466:	0b          	nop
+    1467:	80          	im 0
+    1468:	f6          	im -10
+    1469:	e8          	im -24
+    146a:	51          	storesp 4
+    146b:	bf          	im 63
+    146c:	80          	im 0
+    146d:	3f          	callpcrel
+
+0000146e <.LM459>:
+    146e:	80          	im 0
+    146f:	fc          	im -4
+    1470:	c4          	im -60
+    1471:	08          	load
+    1472:	70          	loadsp 0
+    1473:	08          	load
+    1474:	bf          	im 63
+    1475:	06          	and
+    1476:	56          	storesp 24
+    1477:	56          	storesp 24
+
+00001478 <.LM460>:
+    1478:	78          	loadsp 32
+    1479:	82          	im 2
+    147a:	2e          	eq
+    147b:	09          	not
+    147c:	81          	im 1
+    147d:	06          	and
+    147e:	f8          	im -8
+    147f:	f8          	im -8
+    1480:	38          	neqbranch
+    1481:	fe          	im -2
+    1482:	f3          	im -13
+    1483:	39          	poppcrel
+
+00001484 <.L241>:
+    1484:	0b          	nop
+    1485:	0b          	nop
+    1486:	80          	im 0
+    1487:	f7          	im -9
+    1488:	e0          	im -32
+    1489:	51          	storesp 4
+
+0000148a <.LM462>:
+    148a:	be          	im 62
+    148b:	e1          	im -31
+    148c:	3f          	callpcrel
+
+0000148d <.LM463>:
+    148d:	0b          	nop
+    148e:	0b          	nop
+    148f:	80          	im 0
+    1490:	f9          	im -7
+    1491:	c4          	im -60
+    1492:	51          	storesp 4
+    1493:	be          	im 62
+    1494:	d8          	im -40
+    1495:	3f          	callpcrel
+
+00001496 <.LM464>:
+    1496:	0b          	nop
+    1497:	0b          	nop
+    1498:	80          	im 0
+    1499:	f6          	im -10
+    149a:	dc          	im -36
+    149b:	51          	storesp 4
+    149c:	be          	im 62
+    149d:	cf          	im -49
+    149e:	3f          	callpcrel
+
+0000149f <.LM465>:
+    149f:	80          	im 0
+    14a0:	fc          	im -4
+    14a1:	c4          	im -60
+    14a2:	08          	load
+    14a3:	70          	loadsp 0
+    14a4:	08          	load
+    14a5:	70          	loadsp 0
+    14a6:	8c          	im 12
+    14a7:	2c          	ashiftright
+    14a8:	8f          	im 15
+    14a9:	06          	and
+    14aa:	57          	storesp 28
+    14ab:	55          	storesp 20
+    14ac:	56          	storesp 24
+
+000014ad <.LM466>:
+    14ad:	78          	loadsp 32
+    14ae:	81          	im 1
+    14af:	2e          	eq
+    14b0:	09          	not
+    14b1:	81          	im 1
+    14b2:	06          	and
+    14b3:	f7          	im -9
+    14b4:	fd          	im -3
+    14b5:	38          	neqbranch
+    14b6:	fb          	im -5
+    14b7:	9b          	im 27
+    14b8:	39          	poppcrel
+
+000014b9 <.L385>:
+    14b9:	7b          	loadsp 44
+    14ba:	81          	im 1
+    14bb:	2e          	eq
+    14bc:	09          	not
+    14bd:	81          	im 1
+    14be:	06          	and
+    14bf:	f9          	im -7
+    14c0:	dd          	im -35
+    14c1:	38          	neqbranch
+
+000014c2 <.LM468>:
+    14c2:	7b          	loadsp 44
+    14c3:	5b          	storesp 44
+    14c4:	fb          	im -5
+    14c5:	c3          	im -61
+    14c6:	39          	poppcrel
+
+000014c7 <.L373>:
+    14c7:	74          	loadsp 16
+    14c8:	f7          	im -9
+    14c9:	b6          	im 54
+    14ca:	38          	neqbranch
+
+000014cb <.LM470>:
+    14cb:	0b          	nop
+    14cc:	0b          	nop
+    14cd:	80          	im 0
+    14ce:	f7          	im -9
+    14cf:	f4          	im -12
+    14d0:	51          	storesp 4
+
+000014d1 <.LM471>:
+    14d1:	be          	im 62
+    14d2:	9a          	im 26
+    14d3:	3f          	callpcrel
+
+000014d4 <.LM472>:
+    14d4:	0b          	nop
+    14d5:	0b          	nop
+    14d6:	80          	im 0
+    14d7:	f9          	im -7
+    14d8:	c4          	im -60
+    14d9:	51          	storesp 4
+    14da:	be          	im 62
+    14db:	91          	im 17
+    14dc:	3f          	callpcrel
+
+000014dd <.LM473>:
+    14dd:	0b          	nop
+    14de:	0b          	nop
+    14df:	80          	im 0
+    14e0:	f6          	im -10
+    14e1:	dc          	im -36
+    14e2:	51          	storesp 4
+    14e3:	be          	im 62
+    14e4:	88          	im 8
+    14e5:	3f          	callpcrel
+
+000014e6 <.LM474>:
+    14e6:	80          	im 0
+    14e7:	fc          	im -4
+    14e8:	c4          	im -60
+    14e9:	08          	load
+    14ea:	70          	loadsp 0
+    14eb:	08          	load
+    14ec:	70          	loadsp 0
+    14ed:	8c          	im 12
+    14ee:	2c          	ashiftright
+    14ef:	8f          	im 15
+    14f0:	06          	and
+    14f1:	57          	storesp 28
+    14f2:	55          	storesp 20
+    14f3:	56          	storesp 24
+
+000014f4 <.LM475>:
+    14f4:	78          	loadsp 32
+    14f5:	81          	im 1
+    14f6:	2e          	eq
+    14f7:	09          	not
+    14f8:	81          	im 1
+    14f9:	06          	and
+    14fa:	f7          	im -9
+    14fb:	b6          	im 54
+    14fc:	38          	neqbranch
+    14fd:	fa          	im -6
+    14fe:	d4          	im -44
+    14ff:	39          	poppcrel
+
+00001500 <.L240>:
+    1500:	0b          	nop
+    1501:	0b          	nop
+    1502:	80          	im 0
+    1503:	f7          	im -9
+    1504:	fc          	im -4
+    1505:	51          	storesp 4
+
+00001506 <.LM477>:
+    1506:	bd          	im 61
+    1507:	e5          	im -27
+    1508:	3f          	callpcrel
+
+00001509 <.LM478>:
+    1509:	0b          	nop
+    150a:	0b          	nop
+    150b:	80          	im 0
+    150c:	f9          	im -7
+    150d:	c4          	im -60
+    150e:	51          	storesp 4
+    150f:	bd          	im 61
+    1510:	dc          	im -36
+    1511:	3f          	callpcrel
+
+00001512 <.LM479>:
+    1512:	0b          	nop
+    1513:	0b          	nop
+    1514:	80          	im 0
+    1515:	f6          	im -10
+    1516:	dc          	im -36
+    1517:	51          	storesp 4
+    1518:	bd          	im 61
+    1519:	d3          	im -45
+    151a:	3f          	callpcrel
+
+0000151b <.LM480>:
+    151b:	80          	im 0
+    151c:	fc          	im -4
+    151d:	c4          	im -60
+    151e:	08          	load
+    151f:	70          	loadsp 0
+    1520:	08          	load
+    1521:	70          	loadsp 0
+    1522:	8c          	im 12
+    1523:	2c          	ashiftright
+    1524:	8f          	im 15
+    1525:	06          	and
+    1526:	57          	storesp 28
+    1527:	55          	storesp 20
+    1528:	56          	storesp 24
+
+00001529 <.LM481>:
+    1529:	78          	loadsp 32
+    152a:	81          	im 1
+    152b:	2e          	eq
+    152c:	09          	not
+    152d:	81          	im 1
+    152e:	06          	and
+    152f:	f7          	im -9
+    1530:	81          	im 1
+    1531:	38          	neqbranch
+    1532:	fa          	im -6
+    1533:	9f          	im 31
+    1534:	39          	poppcrel
+
+00001535 <.L381>:
+    1535:	78          	loadsp 32
+    1536:	84          	im 4
+    1537:	2e          	eq
+    1538:	b6          	im 54
+    1539:	38          	neqbranch
+    153a:	78          	loadsp 32
+    153b:	84          	im 4
+    153c:	24          	lessthan
+    153d:	94          	im 20
+    153e:	38          	neqbranch
+    153f:	78          	loadsp 32
+    1540:	83          	im 3
+    1541:	2e          	eq
+    1542:	83          	im 3
+    1543:	d9          	im -39
+    1544:	38          	neqbranch
+
+00001545 <.L263>:
+    1545:	fe          	im -2
+    1546:	19          	addsp 36
+    1547:	83          	im 3
+    1548:	e0          	im -32
+    1549:	b4          	im 52
+    154a:	0c          	store
+
+0000154b <.L392>:
+    154b:	80          	im 0
+
+0000154c <.LM485>:
+    154c:	70          	loadsp 0
+    154d:	58          	storesp 32
+    154e:	5c          	storesp 48
+    154f:	fa          	im -6
+    1550:	9f          	im 31
+    1551:	39          	poppcrel
+
+00001552 <.L268>:
+    1552:	78          	loadsp 32
+    1553:	85          	im 5
+    1554:	2e          	eq
+    1555:	83          	im 3
+    1556:	cd          	im -51
+    1557:	38          	neqbranch
+    1558:	78          	loadsp 32
+    1559:	86          	im 6
+    155a:	2e          	eq
+    155b:	09          	not
+    155c:	81          	im 1
+    155d:	06          	and
+    155e:	e6          	im -26
+    155f:	38          	neqbranch
+
+00001560 <.LM487>:
+    1560:	83          	im 3
+    1561:	e0          	im -32
+    1562:	b8          	im 56
+    1563:	51          	storesp 4
+
+00001564 <.L364>:
+    1564:	ea          	im -22
+    1565:	fe          	im -2
+    1566:	3f          	callpcrel
+
+00001567 <.LM488>:
+    1567:	fe          	im -2
+    1568:	19          	addsp 36
+    1569:	83          	im 3
+    156a:	e0          	im -32
+    156b:	b4          	im 52
+    156c:	0c          	store
+    156d:	dd          	im -35
+    156e:	39          	poppcrel
+
+0000156f <.L265>:
+    156f:	83          	im 3
+    1570:	e3          	im -29
+    1571:	d8          	im -40
+    1572:	51          	storesp 4
+    1573:	f0          	im -16
+    1574:	39          	poppcrel
+
+00001575 <.L255>:
+    1575:	81          	im 1
+    1576:	80          	im 0
+    1577:	51          	storesp 4
+    1578:	bc          	im 60
+    1579:	ed          	im -19
+    157a:	3f          	callpcrel
+
+0000157b <.LM491>:
+    157b:	81          	im 1
+    157c:	15          	addsp 20
+    157d:	70          	loadsp 0
+    157e:	83          	im 3
+    157f:	c1          	im -63
+    1580:	9c          	im 28
+    1581:	35          	div
+    1582:	70          	loadsp 0
+    1583:	83          	im 3
+    1584:	ff          	im -1
+    1585:	ff          	im -1
+    1586:	06          	and
+    1587:	53          	storesp 12
+    1588:	51          	storesp 4
+    1589:	54          	storesp 16
+    158a:	bd          	im 61
+    158b:	f0          	im -16
+    158c:	3f          	callpcrel
+
+0000158d <.LM492>:
+    158d:	0b          	nop
+    158e:	0b          	nop
+    158f:	80          	im 0
+    1590:	f6          	im -10
+    1591:	f0          	im -16
+    1592:	51          	storesp 4
+    1593:	bc          	im 60
+    1594:	d8          	im -40
+    1595:	3f          	callpcrel
+
+00001596 <.LM493>:
+    1596:	78          	loadsp 32
+    1597:	83          	im 3
+    1598:	2e          	eq
+    1599:	09          	not
+    159a:	81          	im 1
+    159b:	06          	and
+    159c:	f6          	im -10
+    159d:	fd          	im -3
+    159e:	38          	neqbranch
+    159f:	fc          	im -4
+    15a0:	b0          	im 48
+    15a1:	39          	poppcrel
+
+000015a2 <.L384>:
+    15a2:	81          	im 1
+    15a3:	80          	im 0
+    15a4:	51          	storesp 4
+    15a5:	bc          	im 60
+    15a6:	c0          	im -64
+    15a7:	3f          	callpcrel
+    15a8:	f7          	im -9
+    15a9:	de          	im -34
+    15aa:	39          	poppcrel
+
+000015ab <.L386>:
+    15ab:	81          	im 1
+    15ac:	80          	im 0
+    15ad:	51          	storesp 4
+    15ae:	bc          	im 60
+    15af:	b7          	im 55
+    15b0:	3f          	callpcrel
+
+000015b1 <.LM496>:
+    15b1:	0b          	nop
+    15b2:	0b          	nop
+    15b3:	80          	im 0
+    15b4:	f7          	im -9
+    15b5:	9c          	im 28
+    15b6:	51          	storesp 4
+    15b7:	bc          	im 60
+    15b8:	b4          	im 52
+    15b9:	3f          	callpcrel
+
+000015ba <.LM497>:
+    15ba:	78          	loadsp 32
+    15bb:	88          	im 8
+    15bc:	2e          	eq
+    15bd:	09          	not
+    15be:	81          	im 1
+    15bf:	06          	and
+    15c0:	f7          	im -9
+    15c1:	ec          	im -20
+    15c2:	38          	neqbranch
+    15c3:	f9          	im -7
+    15c4:	bb          	im 59
+    15c5:	39          	poppcrel
+
+000015c6 <.L390>:
+    15c6:	81          	im 1
+    15c7:	5c          	storesp 48
+
+000015c8 <.L298>:
+    15c8:	74          	loadsp 16
+    15c9:	33          	loadb
+    15ca:	70          	loadsp 0
+    15cb:	81          	im 1
+    15cc:	ff          	im -1
+    15cd:	06          	and
+    15ce:	51          	storesp 4
+    15cf:	54          	storesp 16
+    15d0:	73          	loadsp 12
+    15d1:	f4          	im -12
+    15d2:	94          	im 20
+    15d3:	38          	neqbranch
+    15d4:	74          	loadsp 16
+    15d5:	33          	loadb
+    15d6:	70          	loadsp 0
+    15d7:	81          	im 1
+    15d8:	ff          	im -1
+    15d9:	06          	and
+    15da:	51          	storesp 4
+    15db:	54          	storesp 16
+    15dc:	73          	loadsp 12
+    15dd:	80          	im 0
+    15de:	2e          	eq
+    15df:	e8          	im -24
+    15e0:	38          	neqbranch
+    15e1:	f4          	im -12
+    15e2:	84          	im 4
+    15e3:	39          	poppcrel
+
+000015e4 <.L356>:
+    15e4:	ff          	im -1
+    15e5:	57          	storesp 28
+
+000015e6 <.LM501>:
+    15e6:	87          	im 7
+    15e7:	a9          	im 41
+    15e8:	c0          	im -64
+    15e9:	51          	storesp 4
+    15ea:	dd          	im -35
+    15eb:	c7          	im -57
+    15ec:	3f          	callpcrel
+
+000015ed <.LM502>:
+    15ed:	b9          	im 57
+    15ee:	d5          	im -43
+    15ef:	3f          	callpcrel
+
+000015f0 <.LM503>:
+    15f0:	80          	im 0
+    15f1:	58          	storesp 32
+    15f2:	f4          	im -12
+    15f3:	80          	im 0
+    15f4:	39          	poppcrel
+
+000015f5 <.L355>:
+    15f5:	81          	im 1
+    15f6:	57          	storesp 28
+
+000015f7 <.LM505>:
+    15f7:	87          	im 7
+    15f8:	a9          	im 41
+    15f9:	c0          	im -64
+    15fa:	51          	storesp 4
+    15fb:	dd          	im -35
+    15fc:	b6          	im 54
+    15fd:	3f          	callpcrel
+
+000015fe <.LM506>:
+    15fe:	b9          	im 57
+    15ff:	c4          	im -60
+    1600:	3f          	callpcrel
+
+00001601 <.LM507>:
+    1601:	80          	im 0
+    1602:	58          	storesp 32
+    1603:	f3          	im -13
+    1604:	ef          	im -17
+    1605:	39          	poppcrel
+
+00001606 <.L389>:
+    1606:	ff          	im -1
+    1607:	19          	addsp 36
+    1608:	fd          	im -3
+    1609:	11          	addsp 4
+    160a:	5e          	storesp 56
+    160b:	59          	storesp 36
+
+0000160c <.LM509>:
+    160c:	78          	loadsp 32
+    160d:	80          	im 0
+    160e:	25          	lessthanorequal
+    160f:	f3          	im -13
+    1610:	d6          	im -42
+    1611:	38          	neqbranch
+    1612:	75          	loadsp 20
+    1613:	59          	storesp 36
+    1614:	f3          	im -13
+    1615:	cf          	im -49
+    1616:	39          	poppcrel
+
+00001617 <.L246>:
+    1617:	81          	im 1
+    1618:	80          	im 0
+    1619:	51          	storesp 4
+    161a:	bb          	im 59
+    161b:	cb          	im -53
+    161c:	3f          	callpcrel
+    161d:	f5          	im -11
+    161e:	93          	im 19
+    161f:	39          	poppcrel
+
+00001620 <.L383>:
+    1620:	80          	im 0
+    1621:	58          	storesp 32
+
+00001622 <.L278>:
+    1622:	83          	im 3
+    1623:	e3          	im -29
+    1624:	98          	im 24
+    1625:	18          	addsp 32
+    1626:	70          	loadsp 0
+    1627:	33          	loadb
+
+00001628 <.LM513>:
+    1628:	83          	im 3
+    1629:	e3          	im -29
+    162a:	d8          	im -40
+    162b:	1a          	addsp 40
+    162c:	57          	storesp 28
+    162d:	58          	storesp 32
+    162e:	54          	storesp 16
+    162f:	74          	loadsp 16
+    1630:	33          	loadb
+    1631:	74          	loadsp 16
+    1632:	34          	storeb
+
+00001633 <.LM514>:
+    1633:	83          	im 3
+    1634:	e2          	im -30
+    1635:	c8          	im -56
+    1636:	18          	addsp 32
+    1637:	56          	storesp 24
+    1638:	75          	loadsp 20
+    1639:	33          	loadb
+    163a:	75          	loadsp 20
+    163b:	34          	storeb
+
+0000163c <.LM515>:
+    163c:	83          	im 3
+    163d:	e0          	im -32
+    163e:	b8          	im 56
+    163f:	18          	addsp 32
+    1640:	54          	storesp 16
+    1641:	73          	loadsp 12
+    1642:	33          	loadb
+    1643:	76          	loadsp 24
+    1644:	34          	storeb
+
+00001645 <.LM516>:
+    1645:	76          	loadsp 24
+    1646:	74          	loadsp 16
+    1647:	34          	storeb
+
+00001648 <.LM517>:
+    1648:	81          	im 1
+    1649:	18          	addsp 32
+    164a:	58          	storesp 32
+    164b:	77          	loadsp 28
+    164c:	8f          	im 15
+    164d:	2e          	eq
+    164e:	f8          	im -8
+    164f:	9c          	im 28
+    1650:	38          	neqbranch
+
+00001651 <.LM518>:
+    1651:	83          	im 3
+    1652:	e3          	im -29
+    1653:	98          	im 24
+    1654:	18          	addsp 32
+    1655:	70          	loadsp 0
+    1656:	33          	loadb
+
+00001657 <.LM519>:
+    1657:	83          	im 3
+    1658:	e3          	im -29
+    1659:	d8          	im -40
+    165a:	1a          	addsp 40
+    165b:	57          	storesp 28
+    165c:	58          	storesp 32
+    165d:	54          	storesp 16
+    165e:	74          	loadsp 16
+    165f:	33          	loadb
+    1660:	74          	loadsp 16
+    1661:	34          	storeb
+
+00001662 <.LM520>:
+    1662:	83          	im 3
+    1663:	e2          	im -30
+    1664:	c8          	im -56
+    1665:	18          	addsp 32
+    1666:	56          	storesp 24
+    1667:	75          	loadsp 20
+    1668:	33          	loadb
+    1669:	75          	loadsp 20
+    166a:	34          	storeb
+
+0000166b <.LM521>:
+    166b:	83          	im 3
+    166c:	e0          	im -32
+    166d:	b8          	im 56
+    166e:	18          	addsp 32
+    166f:	54          	storesp 16
+    1670:	73          	loadsp 12
+    1671:	33          	loadb
+    1672:	76          	loadsp 24
+    1673:	34          	storeb
+
+00001674 <.LM522>:
+    1674:	76          	loadsp 24
+    1675:	74          	loadsp 16
+    1676:	34          	storeb
+
+00001677 <.LM523>:
+    1677:	81          	im 1
+    1678:	18          	addsp 32
+    1679:	58          	storesp 32
+    167a:	77          	loadsp 28
+    167b:	8f          	im 15
+    167c:	2e          	eq
+    167d:	09          	not
+    167e:	81          	im 1
+    167f:	06          	and
+    1680:	ff          	im -1
+    1681:	a0          	im 32
+    1682:	38          	neqbranch
+    1683:	f7          	im -9
+    1684:	e7          	im -25
+    1685:	39          	poppcrel
+
+00001686 <.L382>:
+    1686:	80          	im 0
+    1687:	58          	storesp 32
+
+00001688 <.L273>:
+    1688:	83          	im 3
+    1689:	e0          	im -32
+    168a:	b8          	im 56
+    168b:	18          	addsp 32
+    168c:	70          	loadsp 0
+    168d:	33          	loadb
+
+0000168e <.LM526>:
+    168e:	83          	im 3
+    168f:	e2          	im -30
+    1690:	c8          	im -56
+    1691:	1a          	addsp 40
+    1692:	57          	storesp 28
+    1693:	58          	storesp 32
+    1694:	54          	storesp 16
+    1695:	74          	loadsp 16
+    1696:	33          	loadb
+    1697:	74          	loadsp 16
+    1698:	34          	storeb
+
+00001699 <.LM527>:
+    1699:	83          	im 3
+    169a:	e3          	im -29
+    169b:	d8          	im -40
+    169c:	18          	addsp 32
+    169d:	56          	storesp 24
+    169e:	75          	loadsp 20
+    169f:	33          	loadb
+    16a0:	75          	loadsp 20
+    16a1:	34          	storeb
+
+000016a2 <.LM528>:
+    16a2:	83          	im 3
+    16a3:	e3          	im -29
+    16a4:	98          	im 24
+    16a5:	18          	addsp 32
+    16a6:	54          	storesp 16
+    16a7:	73          	loadsp 12
+    16a8:	33          	loadb
+    16a9:	76          	loadsp 24
+    16aa:	34          	storeb
+
+000016ab <.LM529>:
+    16ab:	76          	loadsp 24
+    16ac:	74          	loadsp 16
+    16ad:	34          	storeb
+
+000016ae <.LM530>:
+    16ae:	81          	im 1
+    16af:	18          	addsp 32
+    16b0:	58          	storesp 32
+    16b1:	77          	loadsp 28
+    16b2:	8f          	im 15
+    16b3:	2e          	eq
+    16b4:	f7          	im -9
+    16b5:	b6          	im 54
+    16b6:	38          	neqbranch
+
+000016b7 <.LM531>:
+    16b7:	83          	im 3
+    16b8:	e0          	im -32
+    16b9:	b8          	im 56
+    16ba:	18          	addsp 32
+    16bb:	70          	loadsp 0
+    16bc:	33          	loadb
+
+000016bd <.LM532>:
+    16bd:	83          	im 3
+    16be:	e2          	im -30
+    16bf:	c8          	im -56
+    16c0:	1a          	addsp 40
+    16c1:	57          	storesp 28
+    16c2:	58          	storesp 32
+    16c3:	54          	storesp 16
+    16c4:	74          	loadsp 16
+    16c5:	33          	loadb
+    16c6:	74          	loadsp 16
+    16c7:	34          	storeb
+
+000016c8 <.LM533>:
+    16c8:	83          	im 3
+    16c9:	e3          	im -29
+    16ca:	d8          	im -40
+    16cb:	18          	addsp 32
+    16cc:	56          	storesp 24
+    16cd:	75          	loadsp 20
+    16ce:	33          	loadb
+    16cf:	75          	loadsp 20
+    16d0:	34          	storeb
+
+000016d1 <.LM534>:
+    16d1:	83          	im 3
+    16d2:	e3          	im -29
+    16d3:	98          	im 24
+    16d4:	18          	addsp 32
+    16d5:	54          	storesp 16
+    16d6:	73          	loadsp 12
+    16d7:	33          	loadb
+    16d8:	76          	loadsp 24
+    16d9:	34          	storeb
+
+000016da <.LM535>:
+    16da:	76          	loadsp 24
+    16db:	74          	loadsp 16
+    16dc:	34          	storeb
+
+000016dd <.LM536>:
+    16dd:	81          	im 1
+    16de:	18          	addsp 32
+    16df:	58          	storesp 32
+    16e0:	77          	loadsp 28
+    16e1:	8f          	im 15
+    16e2:	2e          	eq
+    16e3:	09          	not
+    16e4:	81          	im 1
+    16e5:	06          	and
+    16e6:	ff          	im -1
+    16e7:	a0          	im 32
+    16e8:	38          	neqbranch
+    16e9:	f7          	im -9
+    16ea:	81          	im 1
+    16eb:	39          	poppcrel
+
+000016ec <.L250>:
+    16ec:	0b          	nop
+    16ed:	0b          	nop
+    16ee:	80          	im 0
+    16ef:	f8          	im -8
+    16f0:	84          	im 4
+    16f1:	51          	storesp 4
+
+000016f2 <.LM538>:
+    16f2:	b9          	im 57
+    16f3:	f9          	im -7
+    16f4:	3f          	callpcrel
+
+000016f5 <.LM539>:
+    16f5:	0b          	nop
+    16f6:	0b          	nop
+    16f7:	80          	im 0
+    16f8:	f9          	im -7
+    16f9:	c4          	im -60
+    16fa:	51          	storesp 4
+    16fb:	b9          	im 57
+    16fc:	f0          	im -16
+    16fd:	3f          	callpcrel
+
+000016fe <.LM540>:
+    16fe:	0b          	nop
+    16ff:	0b          	nop
+    1700:	80          	im 0
+    1701:	f6          	im -10
+    1702:	e8          	im -24
+    1703:	51          	storesp 4
+    1704:	b9          	im 57
+    1705:	e7          	im -25
+    1706:	3f          	callpcrel
+
+00001707 <.LM541>:
+    1707:	80          	im 0
+    1708:	fc          	im -4
+    1709:	c4          	im -60
+    170a:	08          	load
+    170b:	70          	loadsp 0
+    170c:	08          	load
+    170d:	bf          	im 63
+    170e:	06          	and
+    170f:	56          	storesp 24
+    1710:	56          	storesp 24
+
+00001711 <.LM542>:
+    1711:	78          	loadsp 32
+    1712:	82          	im 2
+    1713:	2e          	eq
+    1714:	09          	not
+    1715:	81          	im 1
+    1716:	06          	and
+    1717:	f3          	im -13
+    1718:	df          	im -33
+    1719:	38          	neqbranch
+    171a:	f9          	im -7
+    171b:	da          	im -38
+    171c:	39          	poppcrel
+
+0000171d <.L264>:
+    171d:	83          	im 3
+    171e:	e3          	im -29
+    171f:	98          	im 24
+    1720:	51          	storesp 4
+    1721:	fc          	im -4
+    1722:	c1          	im -63
+    1723:	39          	poppcrel
+
+00001724 <.L266>:
+    1724:	83          	im 3
+    1725:	e2          	im -30
+    1726:	c8          	im -56
+    1727:	51          	storesp 4
+    1728:	fc          	im -4
+    1729:	ba          	im 58
+    172a:	39          	poppcrel
+
+0000172b <.L251>:
+    172b:	0b          	nop
+    172c:	0b          	nop
+    172d:	80          	im 0
+    172e:	f8          	im -8
+    172f:	98          	im 24
+    1730:	51          	storesp 4
+
+00001731 <.LM546>:
+    1731:	b9          	im 57
+    1732:	ba          	im 58
+    1733:	3f          	callpcrel
+
+00001734 <.LM547>:
+    1734:	0b          	nop
+    1735:	0b          	nop
+    1736:	80          	im 0
+    1737:	f9          	im -7
+    1738:	c4          	im -60
+    1739:	51          	storesp 4
+    173a:	b9          	im 57
+    173b:	b1          	im 49
+    173c:	3f          	callpcrel
+
+0000173d <.LM548>:
+    173d:	0b          	nop
+    173e:	0b          	nop
+    173f:	80          	im 0
+    1740:	f6          	im -10
+    1741:	e8          	im -24
+    1742:	51          	storesp 4
+    1743:	b9          	im 57
+    1744:	a8          	im 40
+    1745:	3f          	callpcrel
+
+00001746 <.LM549>:
+    1746:	80          	im 0
+    1747:	fc          	im -4
+    1748:	c4          	im -60
+    1749:	08          	load
+    174a:	70          	loadsp 0
+    174b:	08          	load
+    174c:	bf          	im 63
+    174d:	06          	and
+    174e:	56          	storesp 24
+    174f:	56          	storesp 24
+
+00001750 <.LM550>:
+    1750:	78          	loadsp 32
+    1751:	82          	im 2
+    1752:	2e          	eq
+    1753:	09          	not
+    1754:	81          	im 1
+    1755:	06          	and
+    1756:	f3          	im -13
+    1757:	a0          	im 32
+    1758:	38          	neqbranch
+    1759:	f9          	im -7
+    175a:	9b          	im 27
+    175b:	39          	poppcrel
+
+0000175c <getCommand>:
+    175c:	fc          	im -4
+    175d:	3d          	pushspadd
+    175e:	0d          	popsp
+    175f:	76          	loadsp 24
+    1760:	80          	im 0
+    1761:	fc          	im -4
+    1762:	a4          	im 36
+    1763:	08          	load
+    1764:	55          	storesp 20
+    1765:	55          	storesp 20
+
+00001766 <.L394>:
+    1766:	73          	loadsp 12
+    1767:	08          	load
+    1768:	70          	loadsp 0
+    1769:	81          	im 1
+    176a:	32          	xor
+    176b:	70          	loadsp 0
+    176c:	81          	im 1
+    176d:	06          	and
+    176e:	51          	storesp 4
+    176f:	51          	storesp 4
+    1770:	53          	storesp 12
+    1771:	72          	loadsp 8
+    1772:	f3          	im -13
+    1773:	38          	neqbranch
+
+00001774 <.LM553>:
+    1774:	83          	im 3
+    1775:	e3          	im -29
+    1776:	8c          	im 12
+    1777:	08          	load
+    1778:	86          	im 6
+    1779:	05          	add
+    177a:	51          	storesp 4
+    177b:	b3          	im 51
+    177c:	f2          	im -14
+    177d:	3f          	callpcrel
+
+0000177e <.LM554>:
+    177e:	80          	im 0
+    177f:	fc          	im -4
+    1780:	a4          	im 36
+    1781:	08          	load
+    1782:	70          	loadsp 0
+    1783:	08          	load
+    1784:	70          	loadsp 0
+    1785:	81          	im 1
+    1786:	06          	and
+    1787:	51          	storesp 4
+    1788:	51          	storesp 4
+    1789:	53          	storesp 12
+    178a:	72          	loadsp 8
+    178b:	80          	im 0
+    178c:	2e          	eq
+    178d:	93          	im 19
+    178e:	38          	neqbranch
+
+0000178f <.L410>:
+    178f:	eb          	im -21
+    1790:	c8          	im -56
+    1791:	3f          	callpcrel
+    1792:	80          	im 0
+    1793:	fc          	im -4
+    1794:	a4          	im 36
+    1795:	08          	load
+    1796:	70          	loadsp 0
+    1797:	08          	load
+    1798:	70          	loadsp 0
+    1799:	81          	im 1
+    179a:	06          	and
+    179b:	51          	storesp 4
+    179c:	51          	storesp 4
+    179d:	53          	storesp 12
+    179e:	72          	loadsp 8
+    179f:	ef          	im -17
+    17a0:	38          	neqbranch
+
+000017a1 <.L406>:
+    17a1:	b4          	im 52
+    17a2:	c3          	im -61
+    17a3:	3f          	callpcrel
+    17a4:	83          	im 3
+    17a5:	e0          	im -32
+    17a6:	80          	im 0
+    17a7:	08          	load
+    17a8:	75          	loadsp 20
+    17a9:	34          	storeb
+
+000017aa <.LM556>:
+    17aa:	b4          	im 52
+    17ab:	ba          	im 58
+    17ac:	3f          	callpcrel
+    17ad:	83          	im 3
+    17ae:	e0          	im -32
+    17af:	80          	im 0
+    17b0:	08          	load
+    17b1:	81          	im 1
+    17b2:	16          	addsp 24
+    17b3:	34          	storeb
+
+000017b4 <.LM557>:
+    17b4:	b4          	im 52
+    17b5:	b0          	im 48
+    17b6:	3f          	callpcrel
+    17b7:	83          	im 3
+    17b8:	e0          	im -32
+    17b9:	80          	im 0
+    17ba:	08          	load
+    17bb:	82          	im 2
+    17bc:	16          	addsp 24
+    17bd:	34          	storeb
+
+000017be <.LM558>:
+    17be:	b4          	im 52
+    17bf:	a6          	im 38
+    17c0:	3f          	callpcrel
+    17c1:	83          	im 3
+    17c2:	e0          	im -32
+    17c3:	80          	im 0
+    17c4:	08          	load
+    17c5:	83          	im 3
+    17c6:	16          	addsp 24
+    17c7:	34          	storeb
+
+000017c8 <.LM559>:
+    17c8:	b4          	im 52
+    17c9:	9c          	im 28
+    17ca:	3f          	callpcrel
+    17cb:	83          	im 3
+    17cc:	e0          	im -32
+    17cd:	80          	im 0
+    17ce:	08          	load
+    17cf:	84          	im 4
+    17d0:	16          	addsp 24
+    17d1:	34          	storeb
+    17d2:	80          	im 0
+    17d3:	fc          	im -4
+    17d4:	a4          	im 36
+    17d5:	08          	load
+    17d6:	54          	storesp 16
+
+000017d7 <.L399>:
+    17d7:	73          	loadsp 12
+    17d8:	08          	load
+    17d9:	70          	loadsp 0
+    17da:	81          	im 1
+    17db:	32          	xor
+    17dc:	70          	loadsp 0
+    17dd:	81          	im 1
+    17de:	06          	and
+    17df:	51          	storesp 4
+    17e0:	51          	storesp 4
+    17e1:	53          	storesp 12
+    17e2:	72          	loadsp 8
+    17e3:	f3          	im -13
+    17e4:	38          	neqbranch
+
+000017e5 <.LM561>:
+    17e5:	0b          	nop
+    17e6:	0b          	nop
+    17e7:	80          	im 0
+    17e8:	f8          	im -8
+    17e9:	b4          	im 52
+    17ea:	51          	storesp 4
+    17eb:	b8          	im 56
+    17ec:	80          	im 0
+    17ed:	3f          	callpcrel
+
+000017ee <.LM562>:
+    17ee:	74          	loadsp 16
+    17ef:	33          	loadb
+    17f0:	83          	im 3
+    17f1:	e0          	im -32
+    17f2:	c8          	im -56
+    17f3:	34          	storeb
+
+000017f4 <.LM563>:
+    17f4:	81          	im 1
+    17f5:	15          	addsp 20
+    17f6:	33          	loadb
+    17f7:	83          	im 3
+    17f8:	e0          	im -32
+    17f9:	c9          	im -55
+    17fa:	34          	storeb
+
+000017fb <.LM564>:
+    17fb:	82          	im 2
+    17fc:	15          	addsp 20
+    17fd:	33          	loadb
+    17fe:	83          	im 3
+    17ff:	e0          	im -32
+    1800:	ca          	im -54
+    1801:	34          	storeb
+
+00001802 <.LM565>:
+    1802:	83          	im 3
+    1803:	15          	addsp 20
+    1804:	33          	loadb
+    1805:	83          	im 3
+    1806:	e0          	im -32
+    1807:	cb          	im -53
+    1808:	34          	storeb
+
+00001809 <.LM566>:
+    1809:	84          	im 4
+    180a:	52          	storesp 8
+    180b:	83          	im 3
+    180c:	e0          	im -32
+    180d:	c8          	im -56
+    180e:	51          	storesp 4
+    180f:	dd          	im -35
+    1810:	df          	im -33
+    1811:	3f          	callpcrel
+    1812:	83          	im 3
+    1813:	e0          	im -32
+    1814:	80          	im 0
+    1815:	08          	load
+    1816:	81          	im 1
+    1817:	ff          	im -1
+    1818:	06          	and
+
+00001819 <.LM567>:
+    1819:	75          	loadsp 20
+    181a:	33          	loadb
+    181b:	52          	storesp 8
+    181c:	53          	storesp 12
+    181d:	b8          	im 56
+    181e:	dd          	im -35
+    181f:	3f          	callpcrel
+
+00001820 <.LM568>:
+    1820:	81          	im 1
+    1821:	15          	addsp 20
+    1822:	33          	loadb
+    1823:	51          	storesp 4
+    1824:	b8          	im 56
+    1825:	d6          	im -42
+    1826:	3f          	callpcrel
+
+00001827 <.LM569>:
+    1827:	82          	im 2
+    1828:	15          	addsp 20
+    1829:	33          	loadb
+    182a:	51          	storesp 4
+    182b:	b8          	im 56
+    182c:	cf          	im -49
+    182d:	3f          	callpcrel
+
+0000182e <.LM570>:
+    182e:	83          	im 3
+    182f:	15          	addsp 20
+    1830:	33          	loadb
+    1831:	51          	storesp 4
+    1832:	b8          	im 56
+    1833:	c8          	im -56
+    1834:	3f          	callpcrel
+
+00001835 <.LM571>:
+    1835:	84          	im 4
+    1836:	15          	addsp 20
+    1837:	33          	loadb
+    1838:	51          	storesp 4
+    1839:	b8          	im 56
+    183a:	c1          	im -63
+    183b:	3f          	callpcrel
+
+0000183c <.LM572>:
+    183c:	72          	loadsp 8
+    183d:	51          	storesp 4
+    183e:	b8          	im 56
+    183f:	bc          	im 60
+    1840:	3f          	callpcrel
+
+00001841 <.LM573>:
+    1841:	84          	im 4
+    1842:	15          	addsp 20
+    1843:	33          	loadb
+    1844:	55          	storesp 20
+    1845:	72          	loadsp 8
+    1846:	75          	loadsp 20
+    1847:	2e          	eq
+    1848:	bd          	im 61
+    1849:	38          	neqbranch
+
+0000184a <.LM574>:
+    184a:	0b          	nop
+    184b:	0b          	nop
+    184c:	80          	im 0
+    184d:	f8          	im -8
+    184e:	bc          	im 60
+    184f:	51          	storesp 4
+    1850:	b7          	im 55
+    1851:	9b          	im 27
+    1852:	3f          	callpcrel
+
+00001853 <.LM575>:
+    1853:	83          	im 3
+    1854:	e3          	im -29
+    1855:	8c          	im 12
+    1856:	08          	load
+    1857:	a8          	im 40
+    1858:	2e          	eq
+    1859:	80          	im 0
+    185a:	cb          	im -53
+    185b:	38          	neqbranch
+
+0000185c <.L403>:
+    185c:	a8          	im 40
+    185d:	0b          	nop
+    185e:	83          	im 3
+    185f:	e3          	im -29
+    1860:	8c          	im 12
+    1861:	0c          	store
+
+00001862 <.LM577>:
+    1862:	0b          	nop
+    1863:	0b          	nop
+    1864:	80          	im 0
+    1865:	f8          	im -8
+    1866:	c4          	im -60
+    1867:	51          	storesp 4
+    1868:	b7          	im 55
+    1869:	83          	im 3
+    186a:	3f          	callpcrel
+
+0000186b <.LM578>:
+    186b:	83          	im 3
+    186c:	e3          	im -29
+    186d:	8e          	im 14
+    186e:	22          	loadh
+    186f:	51          	storesp 4
+    1870:	b8          	im 56
+    1871:	8a          	im 10
+    1872:	3f          	callpcrel
+
+00001873 <.L401>:
+    1873:	0b          	nop
+    1874:	0b          	nop
+    1875:	80          	im 0
+    1876:	f9          	im -7
+    1877:	c4          	im -60
+    1878:	51          	storesp 4
+    1879:	b6          	im 54
+    187a:	f2          	im -14
+    187b:	3f          	callpcrel
+
+0000187c <.LM580>:
+    187c:	80          	im 0
+    187d:	e4          	im -28
+    187e:	51          	storesp 4
+    187f:	d8          	im -40
+    1880:	b2          	im 50
+    1881:	3f          	callpcrel
+    1882:	86          	im 6
+    1883:	3d          	pushspadd
+    1884:	0d          	popsp
+    1885:	04          	poppc
+
+00001886 <.L411>:
+    1886:	b3          	im 51
+    1887:	b4          	im 52
+    1888:	3f          	callpcrel
+    1889:	83          	im 3
+    188a:	e0          	im -32
+    188b:	80          	im 0
+    188c:	08          	load
+    188d:	80          	im 0
+    188e:	2e          	eq
+    188f:	e3          	im -29
+    1890:	38          	neqbranch
+
+00001891 <.LM582>:
+    1891:	0b          	nop
+    1892:	0b          	nop
+    1893:	80          	im 0
+    1894:	f8          	im -8
+    1895:	bc          	im 60
+    1896:	51          	storesp 4
+    1897:	b6          	im 54
+    1898:	d4          	im -44
+    1899:	3f          	callpcrel
+
+0000189a <.LM583>:
+    189a:	83          	im 3
+    189b:	e3          	im -29
+    189c:	8c          	im 12
+    189d:	08          	load
+    189e:	a8          	im 40
+    189f:	2e          	eq
+    18a0:	09          	not
+    18a1:	81          	im 1
+    18a2:	06          	and
+    18a3:	ff          	im -1
+    18a4:	b7          	im 55
+    18a5:	38          	neqbranch
+
+000018a6 <.L412>:
+    18a6:	86          	im 6
+    18a7:	0b          	nop
+    18a8:	83          	im 3
+    18a9:	e3          	im -29
+    18aa:	8c          	im 12
+    18ab:	0c          	store
+
+000018ac <.LM585>:
+    18ac:	0b          	nop
+    18ad:	0b          	nop
+    18ae:	80          	im 0
+    18af:	f8          	im -8
+    18b0:	cc          	im -52
+    18b1:	51          	storesp 4
+
+000018b2 <.LM586>:
+    18b2:	b6          	im 54
+    18b3:	b9          	im 57
+    18b4:	3f          	callpcrel
+
+000018b5 <.LM587>:
+    18b5:	83          	im 3
+    18b6:	e3          	im -29
+    18b7:	8e          	im 14
+    18b8:	22          	loadh
+    18b9:	51          	storesp 4
+    18ba:	b7          	im 55
+    18bb:	c0          	im -64
+    18bc:	3f          	callpcrel
+    18bd:	ff          	im -1
+    18be:	b4          	im 52
+    18bf:	39          	poppcrel
+
+000018c0 <mmcReadCached>:
+    18c0:	fc          	im -4
+    18c1:	3d          	pushspadd
+    18c2:	0d          	popsp
+    18c3:	76          	loadsp 24
+    18c4:	55          	storesp 20
+
+000018c5 <.LM589>:
+    18c5:	74          	loadsp 16
+    18c6:	83          	im 3
+    18c7:	e0          	im -32
+    18c8:	b0          	im 48
+    18c9:	08          	load
+    18ca:	2e          	eq
+    18cb:	af          	im 47
+    18cc:	38          	neqbranch
+
+000018cd <.LM590>:
+    18cd:	80          	im 0
+    18ce:	54          	storesp 16
+
+000018cf <.L415>:
+    18cf:	74          	loadsp 16
+    18d0:	51          	storesp 4
+    18d1:	ab          	im 43
+    18d2:	a9          	im 41
+    18d3:	3f          	callpcrel
+    18d4:	83          	im 3
+    18d5:	e0          	im -32
+    18d6:	80          	im 0
+    18d7:	08          	load
+    18d8:	81          	im 1
+    18d9:	ff          	im -1
+    18da:	06          	and
+
+000018db <.LM592>:
+    18db:	ff          	im -1
+    18dc:	15          	addsp 20
+    18dd:	70          	loadsp 0
+    18de:	81          	im 1
+    18df:	ff          	im -1
+    18e0:	06          	and
+
+000018e1 <.LBE22>:
+    18e1:	72          	loadsp 8
+    18e2:	30          	neg
+    18e3:	70          	loadsp 0
+    18e4:	9f          	im 31
+    18e5:	2a          	lshiftright
+    18e6:	51          	storesp 4
+    18e7:	52          	storesp 8
+    18e8:	56          	storesp 24
+    18e9:	53          	storesp 12
+    18ea:	53          	storesp 12
+    18eb:	73          	loadsp 12
+    18ec:	80          	im 0
+    18ed:	2e          	eq
+    18ee:	84          	im 4
+    18ef:	38          	neqbranch
+    18f0:	71          	loadsp 4
+    18f1:	dd          	im -35
+    18f2:	38          	neqbranch
+
+000018f3 <.L420>:
+    18f3:	72          	loadsp 8
+    18f4:	fe          	im -2
+    18f5:	38          	neqbranch
+
+000018f6 <.LM595>:
+    18f6:	74          	loadsp 16
+    18f7:	83          	im 3
+    18f8:	e0          	im -32
+    18f9:	b0          	im 48
+    18fa:	0c          	store
+
+000018fb <.L413>:
+    18fb:	86          	im 6
+    18fc:	3d          	pushspadd
+    18fd:	0d          	popsp
+    18fe:	04          	poppc
+
+000018ff <disk_readp>:
+    18ff:	fc          	im -4
+    1900:	3d          	pushspadd
+    1901:	0d          	popsp
+    1902:	76          	loadsp 24
+    1903:	02          	pushsp
+    1904:	84          	im 4
+    1905:	05          	add
+    1906:	a2          	im 34
+    1907:	05          	add
+    1908:	22          	loadh
+    1909:	02          	pushsp
+    190a:	88          	im 8
+    190b:	05          	add
+    190c:	a6          	im 38
+    190d:	05          	add
+    190e:	22          	loadh
+
+0000190f <.LM598>:
+    190f:	7a          	loadsp 40
+    1910:	54          	storesp 16
+    1911:	55          	storesp 20
+    1912:	55          	storesp 20
+    1913:	55          	storesp 20
+    1914:	ff          	im -1
+    1915:	aa          	im 42
+    1916:	3f          	callpcrel
+
+00001917 <.LM599>:
+    1917:	72          	loadsp 8
+    1918:	80          	im 0
+    1919:	2e          	eq
+    191a:	a1          	im 33
+    191b:	38          	neqbranch
+
+0000191c <.L433>:
+    191c:	83          	im 3
+    191d:	e3          	im -29
+    191e:	e8          	im -24
+    191f:	14          	addsp 16
+    1920:	33          	loadb
+    1921:	75          	loadsp 20
+    1922:	70          	loadsp 0
+    1923:	81          	im 1
+    1924:	05          	add
+    1925:	57          	storesp 28
+    1926:	34          	storeb
+
+00001927 <.LBE23>:
+    1927:	81          	im 1
+    1928:	14          	addsp 16
+    1929:	70          	loadsp 0
+    192a:	83          	im 3
+    192b:	ff          	im -1
+    192c:	ff          	im -1
+    192d:	06          	and
+    192e:	ff          	im -1
+    192f:	15          	addsp 20
+    1930:	70          	loadsp 0
+    1931:	83          	im 3
+    1932:	ff          	im -1
+    1933:	ff          	im -1
+    1934:	06          	and
+    1935:	56          	storesp 24
+    1936:	52          	storesp 8
+    1937:	55          	storesp 20
+    1938:	52          	storesp 8
+    1939:	72          	loadsp 8
+    193a:	e1          	im -31
+    193b:	38          	neqbranch
+
+0000193c <.L430>:
+    193c:	80          	im 0
+    193d:	0b          	nop
+    193e:	83          	im 3
+    193f:	e0          	im -32
+    1940:	80          	im 0
+    1941:	0c          	store
+    1942:	86          	im 6
+    1943:	3d          	pushspadd
+    1944:	0d          	popsp
+    1945:	04          	poppc
+
+00001946 <USART_Send_Buffer>:
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+    1946:	fe          	im -2
+    1947:	3d          	pushspadd
+    1948:	0d          	popsp
+    1949:	74          	loadsp 16
+    194a:	02          	pushsp
+    194b:	84          	im 4
+    194c:	05          	add
+    194d:	96          	im 22
+    194e:	05          	add
+    194f:	22          	loadh
+    1950:	53          	storesp 12
+    1951:	53          	storesp 12
+
+00001952 <.LM604>:
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+    1952:	71          	loadsp 4
+    1953:	80          	im 0
+    1954:	2e          	eq
+    1955:	97          	im 23
+    1956:	38          	neqbranch
+
+00001957 <.L442>:
+    1957:	72          	loadsp 8
+    1958:	70          	loadsp 0
+    1959:	81          	im 1
+    195a:	05          	add
+    195b:	54          	storesp 16
+    195c:	33          	loadb
+    195d:	51          	storesp 4
+    195e:	b0          	im 48
+    195f:	e7          	im -25
+    1960:	3f          	callpcrel
+    1961:	ff          	im -1
+    1962:	12          	addsp 8
+    1963:	70          	loadsp 0
+    1964:	83          	im 3
+    1965:	ff          	im -1
+    1966:	ff          	im -1
+    1967:	06          	and
+    1968:	51          	storesp 4
+    1969:	52          	storesp 8
+
+0000196a <.LBE24>:
+    196a:	71          	loadsp 4
+    196b:	eb          	im -21
+    196c:	38          	neqbranch
+
+0000196d <.L439>:
+    196d:	84          	im 4
+    196e:	3d          	pushspadd
+    196f:	0d          	popsp
+    1970:	04          	poppc
+
+00001971 <USART_Send_cmpl_and_atari_sector_buffer_and_check_sum>:
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+    1971:	fe          	im -2
+    1972:	3d          	pushspadd
+    1973:	0d          	popsp
+    1974:	02          	pushsp
+    1975:	92          	im 18
+    1976:	05          	add
+    1977:	22          	loadh
+
+00001978 <.LM606>:
+	u08 check_sum;
+	debug("(send:");
+    1978:	0b          	nop
+    1979:	0b          	nop
+    197a:	80          	im 0
+    197b:	f8          	im -8
+    197c:	d4          	im -44
+    197d:	52          	storesp 8
+    197e:	53          	storesp 12
+    197f:	b4          	im 52
+    1980:	ec          	im -20
+    1981:	3f          	callpcrel
+
+00001982 <.LM607>:
+	plotnextnumber(len);
+    1982:	72          	loadsp 8
+    1983:	51          	storesp 4
+    1984:	b5          	im 53
+    1985:	f6          	im -10
+    1986:	3f          	callpcrel
+
+00001987 <.LM608>:
+
+	DELAY_T5_MIN;
+    1987:	82          	im 2
+    1988:	ac          	im 44
+    1989:	51          	storesp 4
+    198a:	d6          	im -42
+    198b:	a7          	im 39
+    198c:	3f          	callpcrel
+
+0000198d <.LM609>:
+	send_CMPL();
+    198d:	80          	im 0
+    198e:	c3          	im -61
+    198f:	51          	storesp 4
+    1990:	b0          	im 48
+    1991:	b5          	im 53
+    1992:	3f          	callpcrel
+
+00001993 <.LM610>:
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+    1993:	81          	im 1
+    1994:	96          	im 22
+    1995:	51          	storesp 4
+    1996:	d6          	im -42
+    1997:	9b          	im 27
+    1998:	3f          	callpcrel
+
+00001999 <.LM611>:
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+    1999:	72          	loadsp 8
+    199a:	52          	storesp 8
+    199b:	83          	im 3
+    199c:	e0          	im -32
+    199d:	c8          	im -56
+    199e:	51          	storesp 4
+    199f:	ff          	im -1
+    19a0:	a5          	im 37
+    19a1:	3f          	callpcrel
+
+000019a2 <.LM612>:
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+    19a2:	72          	loadsp 8
+    19a3:	52          	storesp 8
+    19a4:	83          	im 3
+    19a5:	e0          	im -32
+    19a6:	c8          	im -56
+    19a7:	51          	storesp 4
+    19a8:	da          	im -38
+    19a9:	c6          	im -58
+    19aa:	3f          	callpcrel
+    19ab:	83          	im 3
+    19ac:	e0          	im -32
+    19ad:	80          	im 0
+    19ae:	08          	load
+    19af:	81          	im 1
+    19b0:	ff          	im -1
+    19b1:	06          	and
+
+000019b2 <.LM613>:
+	USART_Transmit_Byte(check_sum);
+    19b2:	70          	loadsp 0
+    19b3:	52          	storesp 8
+    19b4:	53          	storesp 12
+    19b5:	b0          	im 48
+    19b6:	90          	im 16
+    19b7:	3f          	callpcrel
+
+000019b8 <.LM614>:
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+    19b8:	0b          	nop
+    19b9:	0b          	nop
+    19ba:	80          	im 0
+    19bb:	f8          	im -8
+    19bc:	dc          	im -36
+    19bd:	51          	storesp 4
+    19be:	b4          	im 52
+    19bf:	ad          	im 45
+    19c0:	3f          	callpcrel
+
+000019c1 <.LM615>:
+	plotnextnumber(check_sum);
+    19c1:	72          	loadsp 8
+    19c2:	51          	storesp 4
+    19c3:	b5          	im 53
+    19c4:	b7          	im 55
+    19c5:	3f          	callpcrel
+
+000019c6 <.LM616>:
+	debug(")");
+    19c6:	0b          	nop
+    19c7:	0b          	nop
+    19c8:	80          	im 0
+    19c9:	f7          	im -9
+    19ca:	dc          	im -36
+    19cb:	51          	storesp 4
+    19cc:	b4          	im 52
+    19cd:	9f          	im 31
+    19ce:	3f          	callpcrel
+    19cf:	84          	im 4
+    19d0:	3d          	pushspadd
+    19d1:	0d          	popsp
+    19d2:	04          	poppc
+
+000019d3 <sdcard>:
+    19d3:	f1          	im -15
+    19d4:	3d          	pushspadd
+    19d5:	0d          	popsp
+
+000019d6 <.LM618>:
+    19d6:	0b          	nop
+    19d7:	0b          	nop
+    19d8:	80          	im 0
+    19d9:	f8          	im -8
+    19da:	e4          	im -28
+    19db:	51          	storesp 4
+    19dc:	b4          	im 52
+    19dd:	8f          	im 15
+    19de:	3f          	callpcrel
+
+000019df <.LM619>:
+    19df:	0b          	nop
+    19e0:	0b          	nop
+    19e1:	80          	im 0
+    19e2:	f8          	im -8
+    19e3:	ec          	im -20
+    19e4:	51          	storesp 4
+    19e5:	b4          	im 52
+    19e6:	86          	im 6
+    19e7:	3f          	callpcrel
+
+000019e8 <.LM620>:
+    19e8:	d9          	im -39
+    19e9:	c6          	im -58
+    19ea:	3f          	callpcrel
+    19eb:	83          	im 3
+    19ec:	e0          	im -32
+    19ed:	80          	im 0
+    19ee:	08          	load
+    19ef:	81          	im 1
+    19f0:	ff          	im -1
+    19f1:	06          	and
+    19f2:	54          	storesp 16
+    19f3:	73          	loadsp 12
+    19f4:	82          	im 2
+    19f5:	d2          	im -46
+    19f6:	38          	neqbranch
+
+000019f7 <.LM621>:
+    19f7:	0b          	nop
+    19f8:	0b          	nop
+    19f9:	80          	im 0
+    19fa:	f5          	im -11
+    19fb:	94          	im 20
+    19fc:	51          	storesp 4
+    19fd:	b3          	im 51
+    19fe:	ee          	im -18
+    19ff:	3f          	callpcrel
+
+00001a00 <.LM622>:
+    1a00:	0b          	nop
+    1a01:	0b          	nop
+    1a02:	80          	im 0
+    1a03:	f8          	im -8
+    1a04:	f8          	im -8
+    1a05:	51          	storesp 4
+    1a06:	b3          	im 51
+    1a07:	e5          	im -27
+    1a08:	3f          	callpcrel
+
+00001a09 <.LM623>:
+    1a09:	83          	im 3
+    1a0a:	e3          	im -29
+    1a0b:	ac          	im 44
+    1a0c:	51          	storesp 4
+    1a0d:	98          	im 24
+    1a0e:	80          	im 0
+    1a0f:	3f          	callpcrel
+    1a10:	83          	im 3
+    1a11:	e0          	im -32
+    1a12:	80          	im 0
+    1a13:	08          	load
+    1a14:	82          	im 2
+    1a15:	b2          	im 50
+    1a16:	38          	neqbranch
+
+00001a17 <.LM624>:
+    1a17:	0b          	nop
+    1a18:	0b          	nop
+    1a19:	80          	im 0
+    1a1a:	f5          	im -11
+    1a1b:	94          	im 20
+    1a1c:	51          	storesp 4
+    1a1d:	b3          	im 51
+    1a1e:	ce          	im -50
+    1a1f:	3f          	callpcrel
+
+00001a20 <.LM625>:
+    1a20:	0b          	nop
+    1a21:	0b          	nop
+    1a22:	80          	im 0
+    1a23:	f9          	im -7
+    1a24:	80          	im 0
+    1a25:	51          	storesp 4
+    1a26:	b3          	im 51
+    1a27:	c5          	im -59
+    1a28:	3f          	callpcrel
+
+00001a29 <.LM626>:
+    1a29:	0b          	nop
+    1a2a:	0b          	nop
+    1a2b:	80          	im 0
+    1a2c:	f4          	im -12
+    1a2d:	fc          	im -4
+    1a2e:	52          	storesp 8
+    1a2f:	83          	im 3
+    1a30:	e2          	im -30
+    1a31:	f4          	im -12
+    1a32:	51          	storesp 4
+    1a33:	a1          	im 33
+    1a34:	e4          	im -28
+    1a35:	3f          	callpcrel
+    1a36:	83          	im 3
+    1a37:	e0          	im -32
+    1a38:	80          	im 0
+    1a39:	08          	load
+    1a3a:	82          	im 2
+    1a3b:	8c          	im 12
+    1a3c:	38          	neqbranch
+
+00001a3d <.LM627>:
+    1a3d:	0b          	nop
+    1a3e:	0b          	nop
+    1a3f:	80          	im 0
+    1a40:	f5          	im -11
+    1a41:	94          	im 20
+    1a42:	51          	storesp 4
+
+00001a43 <.LM628>:
+    1a43:	b3          	im 51
+    1a44:	a8          	im 40
+    1a45:	3f          	callpcrel
+    1a46:	83          	im 3
+    1a47:	e0          	im -32
+    1a48:	94          	im 20
+    1a49:	52          	storesp 8
+    1a4a:	83          	im 3
+    1a4b:	e2          	im -30
+    1a4c:	f4          	im -12
+    1a4d:	51          	storesp 4
+    1a4e:	a2          	im 34
+    1a4f:	dc          	im -36
+    1a50:	3f          	callpcrel
+    1a51:	83          	im 3
+    1a52:	e0          	im -32
+    1a53:	80          	im 0
+    1a54:	08          	load
+    1a55:	a5          	im 37
+    1a56:	38          	neqbranch
+
+00001a57 <.L544>:
+    1a57:	83          	im 3
+    1a58:	e0          	im -32
+    1a59:	9d          	im 29
+    1a5a:	33          	loadb
+    1a5b:	54          	storesp 16
+    1a5c:	73          	loadsp 12
+    1a5d:	80          	im 0
+    1a5e:	2e          	eq
+    1a5f:	9b          	im 27
+    1a60:	38          	neqbranch
+    1a61:	83          	im 3
+    1a62:	e0          	im -32
+    1a63:	9d          	im 29
+    1a64:	51          	storesp 4
+    1a65:	b3          	im 51
+    1a66:	86          	im 6
+    1a67:	3f          	callpcrel
+    1a68:	83          	im 3
+    1a69:	e0          	im -32
+    1a6a:	94          	im 20
+    1a6b:	52          	storesp 8
+    1a6c:	83          	im 3
+    1a6d:	e2          	im -30
+    1a6e:	f4          	im -12
+    1a6f:	51          	storesp 4
+    1a70:	a2          	im 34
+    1a71:	ba          	im 58
+    1a72:	3f          	callpcrel
+    1a73:	83          	im 3
+    1a74:	e0          	im -32
+    1a75:	80          	im 0
+    1a76:	08          	load
+    1a77:	80          	im 0
+    1a78:	2e          	eq
+    1a79:	dd          	im -35
+    1a7a:	38          	neqbranch
+
+00001a7b <.L449>:
+    1a7b:	80          	im 0
+    1a7c:	55          	storesp 20
+
+00001a7d <.L455>:
+    1a7d:	0b          	nop
+    1a7e:	0b          	nop
+    1a7f:	80          	im 0
+    1a80:	f9          	im -7
+    1a81:	8c          	im 12
+    1a82:	15          	addsp 20
+    1a83:	54          	storesp 16
+    1a84:	73          	loadsp 12
+    1a85:	33          	loadb
+    1a86:	83          	im 3
+    1a87:	e3          	im -29
+    1a88:	98          	im 24
+    1a89:	16          	addsp 24
+    1a8a:	34          	storeb
+
+00001a8b <.LM631>:
+    1a8b:	73          	loadsp 12
+    1a8c:	33          	loadb
+    1a8d:	83          	im 3
+    1a8e:	e3          	im -29
+    1a8f:	d8          	im -40
+    1a90:	16          	addsp 24
+    1a91:	34          	storeb
+
+00001a92 <.LM632>:
+    1a92:	73          	loadsp 12
+    1a93:	33          	loadb
+    1a94:	83          	im 3
+    1a95:	e2          	im -30
+    1a96:	c8          	im -56
+    1a97:	16          	addsp 24
+    1a98:	34          	storeb
+
+00001a99 <.LM633>:
+    1a99:	73          	loadsp 12
+    1a9a:	33          	loadb
+    1a9b:	83          	im 3
+    1a9c:	e0          	im -32
+    1a9d:	b8          	im 56
+    1a9e:	16          	addsp 24
+    1a9f:	34          	storeb
+
+00001aa0 <.LM634>:
+    1aa0:	73          	loadsp 12
+    1aa1:	33          	loadb
+    1aa2:	54          	storesp 16
+    1aa3:	73          	loadsp 12
+    1aa4:	80          	im 0
+    1aa5:	2e          	eq
+    1aa6:	8c          	im 12
+    1aa7:	38          	neqbranch
+
+00001aa8 <.LM635>:
+    1aa8:	81          	im 1
+    1aa9:	15          	addsp 20
+    1aaa:	55          	storesp 20
+    1aab:	74          	loadsp 16
+    1aac:	8f          	im 15
+    1aad:	2e          	eq
+    1aae:	09          	not
+    1aaf:	81          	im 1
+    1ab0:	06          	and
+    1ab1:	cb          	im -53
+    1ab2:	38          	neqbranch
+
+00001ab3 <.L452>:
+    1ab3:	81          	im 1
+    1ab4:	0b          	nop
+    1ab5:	83          	im 3
+    1ab6:	e0          	im -32
+    1ab7:	b4          	im 52
+    1ab8:	0c          	store
+
+00001ab9 <.LM637>:
+    1ab9:	83          	im 3
+    1aba:	e3          	im -29
+    1abb:	98          	im 24
+    1abc:	51          	storesp 4
+    1abd:	d8          	im -40
+    1abe:	fc          	im -4
+    1abf:	3f          	callpcrel
+
+00001ac0 <.LM638>:
+    1ac0:	80          	im 0
+    1ac1:	51          	storesp 4
+    1ac2:	d7          	im -41
+    1ac3:	a6          	im 38
+    1ac4:	3f          	callpcrel
+
+00001ac5 <.LM639>:
+    1ac5:	80          	im 0
+    1ac6:	fb          	im -5
+    1ac7:	e4          	im -28
+    1ac8:	08          	load
+    1ac9:	54          	storesp 16
+    1aca:	80          	im 0
+    1acb:	74          	loadsp 16
+    1acc:	34          	storeb
+
+00001acd <.LM640>:
+    1acd:	d6          	im -42
+    1ace:	a1          	im 33
+    1acf:	3f          	callpcrel
+
+00001ad0 <.LM641>:
+    1ad0:	81          	im 1
+    1ad1:	51          	storesp 4
+    1ad2:	d7          	im -41
+    1ad3:	96          	im 22
+    1ad4:	3f          	callpcrel
+
+00001ad5 <.LM642>:
+    1ad5:	80          	im 0
+    1ad6:	51          	storesp 4
+    1ad7:	d7          	im -41
+    1ad8:	b5          	im 53
+    1ad9:	3f          	callpcrel
+
+00001ada <.LM643>:
+    1ada:	83          	im 3
+    1adb:	e3          	im -29
+    1adc:	8c          	im 12
+    1add:	08          	load
+    1ade:	86          	im 6
+    1adf:	05          	add
+    1ae0:	51          	storesp 4
+    1ae1:	ad          	im 45
+    1ae2:	8c          	im 12
+    1ae3:	3f          	callpcrel
+    1ae4:	8e          	im 14
+    1ae5:	3d          	pushspadd
+    1ae6:	91          	im 17
+    1ae7:	3d          	pushspadd
+    1ae8:	5e          	storesp 56
+    1ae9:	59          	storesp 36
+
+00001aea <.L541>:
+    1aea:	78          	loadsp 32
+    1aeb:	51          	storesp 4
+    1aec:	f8          	im -8
+    1aed:	ee          	im -18
+    1aee:	3f          	callpcrel
+
+00001aef <.LM645>:
+    1aef:	8e          	im 14
+    1af0:	3d          	pushspadd
+    1af1:	33          	loadb
+    1af2:	cf          	im -49
+    1af3:	11          	addsp 4
+    1af4:	70          	loadsp 0
+    1af5:	81          	im 1
+    1af6:	ff          	im -1
+    1af7:	06          	and
+    1af8:	51          	storesp 4
+    1af9:	55          	storesp 20
+    1afa:	55          	storesp 20
+    1afb:	73          	loadsp 12
+    1afc:	82          	im 2
+    1afd:	26          	ulessthan
+    1afe:	eb          	im -21
+    1aff:	38          	neqbranch
+
+00001b00 <.LM646>:
+    1b00:	74          	loadsp 16
+    1b01:	8f          	im 15
+    1b02:	06          	and
+    1b03:	54          	storesp 16
+
+00001b04 <.LM647>:
+    1b04:	73          	loadsp 12
+    1b05:	83          	im 3
+    1b06:	e0          	im -32
+    1b07:	b4          	im 52
+    1b08:	08          	load
+    1b09:	2e          	eq
+    1b0a:	97          	im 23
+    1b0b:	38          	neqbranch
+
+00001b0c <.LM648>:
+    1b0c:	73          	loadsp 12
+    1b0d:	83          	im 3
+    1b0e:	e0          	im -32
+    1b0f:	b4          	im 52
+    1b10:	0c          	store
+
+00001b11 <.LM649>:
+    1b11:	73          	loadsp 12
+    1b12:	82          	im 2
+    1b13:	2e          	eq
+    1b14:	82          	im 2
+    1b15:	b6          	im 54
+    1b16:	38          	neqbranch
+    1b17:	73          	loadsp 12
+    1b18:	82          	im 2
+    1b19:	24          	lessthan
+    1b1a:	82          	im 2
+    1b1b:	8a          	im 10
+    1b1c:	38          	neqbranch
+    1b1d:	73          	loadsp 12
+    1b1e:	81          	im 1
+    1b1f:	2e          	eq
+    1b20:	b4          	im 52
+    1b21:	38          	neqbranch
+
+00001b22 <.L459>:
+    1b22:	83          	im 3
+    1b23:	e2          	im -30
+    1b24:	e4          	im -28
+    1b25:	08          	load
+    1b26:	80          	im 0
+    1b27:	2e          	eq
+    1b28:	c1          	im -63
+    1b29:	38          	neqbranch
+
+00001b2a <.LM651>:
+    1b2a:	02          	pushsp
+    1b2b:	b5          	im 53
+    1b2c:	05          	add
+    1b2d:	33          	loadb
+    1b2e:	54          	storesp 16
+    1b2f:	73          	loadsp 12
+    1b30:	80          	im 0
+    1b31:	d2          	im -46
+    1b32:	2e          	eq
+    1b33:	82          	im 2
+    1b34:	a1          	im 33
+    1b35:	38          	neqbranch
+    1b36:	73          	loadsp 12
+    1b37:	80          	im 0
+    1b38:	d2          	im -46
+    1b39:	24          	lessthan
+    1b3a:	82          	im 2
+    1b3b:	83          	im 3
+    1b3c:	38          	neqbranch
+    1b3d:	73          	loadsp 12
+    1b3e:	bf          	im 63
+    1b3f:	2e          	eq
+    1b40:	9d          	im 29
+    1b41:	38          	neqbranch
+
+00001b42 <.LM652>:
+    1b42:	ac          	im 44
+    1b43:	94          	im 20
+    1b44:	3f          	callpcrel
+    1b45:	ff          	im -1
+    1b46:	a3          	im 35
+    1b47:	39          	poppcrel
+
+00001b48 <.L540>:
+    1b48:	0b          	nop
+    1b49:	0b          	nop
+    1b4a:	80          	im 0
+    1b4b:	f5          	im -11
+    1b4c:	8c          	im 12
+    1b4d:	51          	storesp 4
+    1b4e:	b1          	im 49
+    1b4f:	9d          	im 29
+    1b50:	3f          	callpcrel
+
+00001b51 <.LM654>:
+    1b51:	91          	im 17
+    1b52:	3d          	pushspadd
+    1b53:	0d          	popsp
+    1b54:	04          	poppc
+
+00001b55 <.L461>:
+    1b55:	83          	im 3
+    1b56:	e3          	im -29
+    1b57:	98          	im 24
+    1b58:	51          	storesp 4
+
+00001b59 <.LM656>:
+    1b59:	d7          	im -41
+    1b5a:	e0          	im -32
+    1b5b:	3f          	callpcrel
+    1b5c:	c5          	im -59
+    1b5d:	39          	poppcrel
+
+00001b5e <.L468>:
+    1b5e:	0b          	nop
+    1b5f:	0b          	nop
+    1b60:	80          	im 0
+    1b61:	f6          	im -10
+    1b62:	e8          	im -24
+    1b63:	51          	storesp 4
+    1b64:	b1          	im 49
+    1b65:	87          	im 7
+    1b66:	3f          	callpcrel
+
+00001b67 <.LM658>:
+    1b67:	02          	pushsp
+    1b68:	b7          	im 55
+    1b69:	05          	add
+    1b6a:	33          	loadb
+    1b6b:	70          	loadsp 0
+    1b6c:	88          	im 8
+    1b6d:	2b          	ashiftleft
+    1b6e:	81          	im 1
+    1b6f:	fe          	im -2
+    1b70:	80          	im 0
+    1b71:	06          	and
+    1b72:	02          	pushsp
+    1b73:	88          	im 8
+    1b74:	05          	add
+    1b75:	b6          	im 54
+    1b76:	05          	add
+    1b77:	33          	loadb
+    1b78:	71          	loadsp 4
+    1b79:	05          	add
+    1b7a:	51          	storesp 4
+    1b7b:	55          	storesp 20
+    1b7c:	55          	storesp 20
+
+00001b7d <.LM659>:
+    1b7d:	ad          	im 45
+    1b7e:	96          	im 22
+    1b7f:	3f          	callpcrel
+
+00001b80 <.LM660>:
+    1b80:	80          	im 0
+    1b81:	c1          	im -63
+    1b82:	51          	storesp 4
+    1b83:	ac          	im 44
+    1b84:	c2          	im -62
+    1b85:	3f          	callpcrel
+
+00001b86 <.LM661>:
+    1b86:	d2          	im -46
+    1b87:	c0          	im -64
+    1b88:	3f          	callpcrel
+
+00001b89 <.LM662>:
+    1b89:	86          	im 6
+    1b8a:	0b          	nop
+    1b8b:	83          	im 3
+    1b8c:	e0          	im -32
+    1b8d:	c8          	im -56
+    1b8e:	34          	storeb
+
+00001b8f <.LM663>:
+    1b8f:	81          	im 1
+    1b90:	52          	storesp 8
+    1b91:	83          	im 3
+    1b92:	e0          	im -32
+    1b93:	c8          	im -56
+    1b94:	51          	storesp 4
+    1b95:	b3          	im 51
+    1b96:	e2          	im -30
+    1b97:	3f          	callpcrel
+
+00001b98 <.LM664>:
+    1b98:	81          	im 1
+    1b99:	51          	storesp 4
+    1b9a:	fb          	im -5
+    1b9b:	d5          	im -43
+    1b9c:	3f          	callpcrel
+
+00001b9d <.LM665>:
+    1b9d:	73          	loadsp 12
+    1b9e:	85          	im 5
+    1b9f:	d4          	im -44
+    1ba0:	38          	neqbranch
+
+00001ba1 <.LM666>:
+    1ba1:	86          	im 6
+    1ba2:	0b          	nop
+    1ba3:	83          	im 3
+    1ba4:	e3          	im -29
+    1ba5:	8c          	im 12
+    1ba6:	0c          	store
+
+00001ba7 <.LM667>:
+    1ba7:	0b          	nop
+    1ba8:	0b          	nop
+    1ba9:	80          	im 0
+    1baa:	f8          	im -8
+    1bab:	cc          	im -52
+    1bac:	51          	storesp 4
+
+00001bad <.LM668>:
+    1bad:	b0          	im 48
+    1bae:	be          	im 62
+    1baf:	3f          	callpcrel
+
+00001bb0 <.LM669>:
+    1bb0:	83          	im 3
+    1bb1:	e3          	im -29
+    1bb2:	8e          	im 14
+    1bb3:	22          	loadh
+    1bb4:	51          	storesp 4
+    1bb5:	b1          	im 49
+    1bb6:	c5          	im -59
+    1bb7:	3f          	callpcrel
+
+00001bb8 <.L471>:
+    1bb8:	0b          	nop
+    1bb9:	0b          	nop
+    1bba:	80          	im 0
+    1bbb:	f9          	im -7
+    1bbc:	98          	im 24
+    1bbd:	51          	storesp 4
+    1bbe:	b0          	im 48
+    1bbf:	ad          	im 45
+    1bc0:	3f          	callpcrel
+
+00001bc1 <.LM671>:
+    1bc1:	ac          	im 44
+    1bc2:	d2          	im -46
+    1bc3:	3f          	callpcrel
+
+00001bc4 <.LM672>:
+    1bc4:	80          	im 0
+    1bc5:	c1          	im -63
+    1bc6:	51          	storesp 4
+    1bc7:	ab          	im 43
+    1bc8:	fe          	im -2
+    1bc9:	3f          	callpcrel
+
+00001bca <.LM673>:
+    1bca:	d1          	im -47
+    1bcb:	fc          	im -4
+    1bcc:	3f          	callpcrel
+
+00001bcd <.LM674>:
+    1bcd:	98          	im 24
+
+00001bce <.LM675>:
+    1bce:	0b          	nop
+    1bcf:	83          	im 3
+    1bd0:	e2          	im -30
+    1bd1:	ec          	im -20
+    1bd2:	33          	loadb
+    1bd3:	83          	im 3
+    1bd4:	e2          	im -30
+    1bd5:	ed          	im -19
+    1bd6:	33          	loadb
+    1bd7:	71          	loadsp 4
+    1bd8:	88          	im 8
+    1bd9:	2b          	ashiftleft
+    1bda:	07          	or
+    1bdb:	56          	storesp 24
+    1bdc:	58          	storesp 32
+    1bdd:	55          	storesp 20
+    1bde:	73          	loadsp 12
+    1bdf:	81          	im 1
+    1be0:	80          	im 0
+    1be1:	2e          	eq
+    1be2:	82          	im 2
+    1be3:	c2          	im -62
+    1be4:	38          	neqbranch
+
+00001be5 <.LM676>:
+    1be5:	b8          	im 56
+    1be6:	55          	storesp 20
+
+00001be7 <.L474>:
+    1be7:	74          	loadsp 16
+    1be8:	83          	im 3
+    1be9:	e0          	im -32
+    1bea:	c8          	im -56
+    1beb:	34          	storeb
+
+00001bec <.LM678>:
+    1bec:	ff          	im -1
+    1bed:	0b          	nop
+    1bee:	83          	im 3
+    1bef:	e0          	im -32
+    1bf0:	c9          	im -55
+    1bf1:	34          	storeb
+
+00001bf2 <.LM679>:
+    1bf2:	e0          	im -32
+    1bf3:	0b          	nop
+    1bf4:	83          	im 3
+    1bf5:	e0          	im -32
+    1bf6:	ca          	im -54
+    1bf7:	34          	storeb
+
+00001bf8 <.LM680>:
+    1bf8:	80          	im 0
+    1bf9:	0b          	nop
+    1bfa:	83          	im 3
+    1bfb:	e0          	im -32
+    1bfc:	cb          	im -53
+    1bfd:	34          	storeb
+
+00001bfe <.LM681>:
+    1bfe:	84          	im 4
+    1bff:	52          	storesp 8
+    1c00:	83          	im 3
+    1c01:	e0          	im -32
+    1c02:	c8          	im -56
+    1c03:	51          	storesp 4
+    1c04:	b2          	im 50
+    1c05:	f3          	im -13
+    1c06:	3f          	callpcrel
+
+00001c07 <.LM682>:
+    1c07:	84          	im 4
+    1c08:	51          	storesp 4
+    1c09:	fa          	im -6
+    1c0a:	e6          	im -26
+    1c0b:	3f          	callpcrel
+
+00001c0c <.LM683>:
+    1c0c:	83          	im 3
+    1c0d:	e0          	im -32
+    1c0e:	c8          	im -56
+    1c0f:	33          	loadb
+    1c10:	51          	storesp 4
+    1c11:	b0          	im 48
+    1c12:	e9          	im -23
+    1c13:	3f          	callpcrel
+
+00001c14 <.LM684>:
+    1c14:	0b          	nop
+    1c15:	0b          	nop
+    1c16:	80          	im 0
+    1c17:	f9          	im -7
+    1c18:	a0          	im 32
+    1c19:	51          	storesp 4
+
+00001c1a <.L539>:
+    1c1a:	af          	im 47
+    1c1b:	d1          	im -47
+    1c1c:	3f          	callpcrel
+
+00001c1d <.LM686>:
+    1c1d:	ac          	im 44
+    1c1e:	bb          	im 59
+    1c1f:	3f          	callpcrel
+
+00001c20 <.L547>:
+    1c20:	aa          	im 42
+    1c21:	b6          	im 54
+    1c22:	3f          	callpcrel
+    1c23:	fd          	im -3
+    1c24:	c5          	im -59
+    1c25:	39          	poppcrel
+
+00001c26 <.L465>:
+    1c26:	73          	loadsp 12
+    1c27:	83          	im 3
+    1c28:	2e          	eq
+    1c29:	81          	im 1
+    1c2a:	f1          	im -15
+    1c2b:	38          	neqbranch
+    1c2c:	73          	loadsp 12
+    1c2d:	84          	im 4
+    1c2e:	2e          	eq
+    1c2f:	09          	not
+    1c30:	81          	im 1
+    1c31:	06          	and
+    1c32:	fd          	im -3
+    1c33:	ee          	im -18
+    1c34:	38          	neqbranch
+
+00001c35 <.LM689>:
+    1c35:	83          	im 3
+    1c36:	e0          	im -32
+    1c37:	b8          	im 56
+    1c38:	51          	storesp 4
+    1c39:	d6          	im -42
+    1c3a:	80          	im 0
+    1c3b:	3f          	callpcrel
+    1c3c:	fd          	im -3
+    1c3d:	e4          	im -28
+    1c3e:	39          	poppcrel
+
+00001c3f <.L520>:
+    1c3f:	73          	loadsp 12
+    1c40:	80          	im 0
+    1c41:	d3          	im -45
+    1c42:	2e          	eq
+    1c43:	fe          	im -2
+    1c44:	f3          	im -13
+    1c45:	38          	neqbranch
+
+00001c46 <.LM691>:
+    1c46:	aa          	im 42
+    1c47:	90          	im 16
+    1c48:	3f          	callpcrel
+    1c49:	fd          	im -3
+    1c4a:	9f          	im 31
+    1c4b:	39          	poppcrel
+
+00001c4c <.L462>:
+    1c4c:	83          	im 3
+    1c4d:	e3          	im -29
+    1c4e:	d8          	im -40
+    1c4f:	51          	storesp 4
+
+00001c50 <.LM693>:
+    1c50:	d5          	im -43
+    1c51:	e9          	im -23
+    1c52:	3f          	callpcrel
+    1c53:	fd          	im -3
+    1c54:	cd          	im -51
+    1c55:	39          	poppcrel
+
+00001c56 <.L478>:
+    1c56:	02          	pushsp
+    1c57:	b7          	im 55
+    1c58:	05          	add
+    1c59:	33          	loadb
+    1c5a:	70          	loadsp 0
+    1c5b:	88          	im 8
+    1c5c:	2b          	ashiftleft
+    1c5d:	81          	im 1
+    1c5e:	fe          	im -2
+    1c5f:	80          	im 0
+    1c60:	06          	and
+    1c61:	02          	pushsp
+    1c62:	88          	im 8
+    1c63:	05          	add
+    1c64:	b6          	im 54
+    1c65:	05          	add
+    1c66:	33          	loadb
+    1c67:	57          	storesp 28
+    1c68:	76          	loadsp 24
+    1c69:	05          	add
+    1c6a:	58          	storesp 32
+    1c6b:	58          	storesp 32
+
+00001c6c <.LM695>:
+    1c6c:	80          	im 0
+    1c6d:	55          	storesp 20
+
+00001c6e <.LM696>:
+    1c6e:	ab          	im 43
+    1c6f:	a5          	im 37
+    1c70:	3f          	callpcrel
+
+00001c71 <.LM697>:
+    1c71:	80          	im 0
+    1c72:	c1          	im -63
+    1c73:	51          	storesp 4
+    1c74:	aa          	im 42
+    1c75:	d1          	im -47
+    1c76:	3f          	callpcrel
+
+00001c77 <.LM698>:
+    1c77:	74          	loadsp 16
+    1c78:	91          	im 17
+    1c79:	3d          	pushspadd
+    1c7a:	23          	storeh
+
+00001c7b <.LM699>:
+    1c7b:	0b          	nop
+    1c7c:	0b          	nop
+    1c7d:	80          	im 0
+    1c7e:	f9          	im -7
+    1c7f:	a8          	im 40
+    1c80:	51          	storesp 4
+    1c81:	ae          	im 46
+    1c82:	ea          	im -22
+    1c83:	3f          	callpcrel
+
+00001c84 <.LM700>:
+    1c84:	76          	loadsp 24
+    1c85:	51          	storesp 4
+    1c86:	af          	im 47
+    1c87:	f4          	im -12
+    1c88:	3f          	callpcrel
+
+00001c89 <.LM701>:
+    1c89:	0b          	nop
+    1c8a:	0b          	nop
+    1c8b:	80          	im 0
+    1c8c:	f9          	im -7
+    1c8d:	b8          	im 56
+    1c8e:	51          	storesp 4
+    1c8f:	ae          	im 46
+    1c90:	dc          	im -36
+    1c91:	3f          	callpcrel
+
+00001c92 <.LM702>:
+    1c92:	83          	im 3
+    1c93:	e3          	im -29
+    1c94:	88          	im 8
+    1c95:	08          	load
+    1c96:	75          	loadsp 20
+    1c97:	2e          	eq
+    1c98:	09          	not
+    1c99:	81          	im 1
+    1c9a:	06          	and
+    1c9b:	82          	im 2
+    1c9c:	8e          	im 14
+    1c9d:	38          	neqbranch
+
+00001c9e <.LM703>:
+    1c9e:	83          	im 3
+    1c9f:	e3          	im -29
+    1ca0:	90          	im 16
+    1ca1:	08          	load
+    1ca2:	56          	storesp 24
+
+00001ca3 <.LM704>:
+    1ca3:	83          	im 3
+    1ca4:	77          	loadsp 28
+    1ca5:	25          	lessthanorequal
+    1ca6:	81          	im 1
+    1ca7:	cc          	im -52
+    1ca8:	38          	neqbranch
+
+00001ca9 <.LM705>:
+    1ca9:	83          	im 3
+    1caa:	e2          	im -30
+    1cab:	ec          	im -20
+    1cac:	33          	loadb
+    1cad:	83          	im 3
+    1cae:	e2          	im -30
+    1caf:	ed          	im -19
+    1cb0:	33          	loadb
+    1cb1:	71          	loadsp 4
+    1cb2:	88          	im 8
+    1cb3:	2b          	ashiftleft
+    1cb4:	07          	or
+    1cb5:	fc          	im -4
+    1cb6:	19          	addsp 36
+    1cb7:	71          	loadsp 4
+    1cb8:	29          	mult
+    1cb9:	78          	loadsp 32
+    1cba:	05          	add
+    1cbb:	83          	im 3
+    1cbc:	80          	im 0
+    1cbd:	05          	add
+
+00001cbe <.LM706>:
+    1cbe:	70          	loadsp 0
+    1cbf:	83          	im 3
+    1cc0:	ff          	im -1
+    1cc1:	ff          	im -1
+    1cc2:	06          	and
+    1cc3:	54          	storesp 16
+    1cc4:	58          	storesp 32
+    1cc5:	56          	storesp 24
+    1cc6:	58          	storesp 32
+    1cc7:	af          	im 47
+    1cc8:	b3          	im 51
+    1cc9:	3f          	callpcrel
+
+00001cca <.LM707>:
+    1cca:	0b          	nop
+    1ccb:	0b          	nop
+    1ccc:	80          	im 0
+    1ccd:	f9          	im -7
+    1cce:	c4          	im -60
+    1ccf:	51          	storesp 4
+    1cd0:	ae          	im 46
+    1cd1:	9b          	im 27
+    1cd2:	3f          	callpcrel
+
+00001cd3 <.LM708>:
+    1cd3:	75          	loadsp 20
+    1cd4:	51          	storesp 4
+    1cd5:	9a          	im 26
+    1cd6:	bc          	im 60
+    1cd7:	3f          	callpcrel
+
+00001cd8 <.LM709>:
+    1cd8:	7c          	loadsp 48
+    1cd9:	53          	storesp 12
+    1cda:	74          	loadsp 16
+    1cdb:	83          	im 3
+    1cdc:	ff          	im -1
+    1cdd:	ff          	im -1
+    1cde:	06          	and
+    1cdf:	70          	loadsp 0
+    1ce0:	53          	storesp 12
+    1ce1:	83          	im 3
+    1ce2:	e0          	im -32
+    1ce3:	c8          	im -56
+    1ce4:	52          	storesp 8
+    1ce5:	54          	storesp 16
+    1ce6:	98          	im 24
+    1ce7:	8d          	im 13
+    1ce8:	3f          	callpcrel
+
+00001ce9 <.L517>:
+    1ce9:	73          	loadsp 12
+    1cea:	51          	storesp 4
+    1ceb:	f9          	im -7
+    1cec:	84          	im 4
+    1ced:	3f          	callpcrel
+
+00001cee <.LM711>:
+    1cee:	73          	loadsp 12
+    1cef:	52          	storesp 8
+    1cf0:	84          	im 4
+    1cf1:	88          	im 8
+    1cf2:	80          	im 0
+    1cf3:	51          	storesp 4
+    1cf4:	d3          	im -45
+    1cf5:	fa          	im -6
+    1cf6:	3f          	callpcrel
+    1cf7:	83          	im 3
+    1cf8:	e0          	im -32
+    1cf9:	80          	im 0
+    1cfa:	08          	load
+    1cfb:	81          	im 1
+    1cfc:	ff          	im -1
+    1cfd:	06          	and
+
+00001cfe <.LM712>:
+    1cfe:	0b          	nop
+    1cff:	0b          	nop
+    1d00:	80          	im 0
+    1d01:	f9          	im -7
+    1d02:	b0          	im 48
+    1d03:	52          	storesp 8
+    1d04:	54          	storesp 16
+    1d05:	ad          	im 45
+    1d06:	e6          	im -26
+    1d07:	3f          	callpcrel
+
+00001d08 <.LM713>:
+    1d08:	73          	loadsp 12
+    1d09:	51          	storesp 4
+    1d0a:	ae          	im 46
+    1d0b:	f0          	im -16
+    1d0c:	3f          	callpcrel
+
+00001d0d <.LM714>:
+    1d0d:	0b          	nop
+    1d0e:	0b          	nop
+    1d0f:	80          	im 0
+    1d10:	f9          	im -7
+    1d11:	c4          	im -60
+    1d12:	51          	storesp 4
+
+00001d13 <.L552>:
+    1d13:	ad          	im 45
+    1d14:	d8          	im -40
+    1d15:	3f          	callpcrel
+
+00001d16 <.LM715>:
+    1d16:	aa          	im 42
+    1d17:	c2          	im -62
+    1d18:	3f          	callpcrel
+    1d19:	fe          	im -2
+    1d1a:	85          	im 5
+    1d1b:	39          	poppcrel
+
+00001d1c <.L463>:
+    1d1c:	83          	im 3
+    1d1d:	e2          	im -30
+    1d1e:	c8          	im -56
+    1d1f:	51          	storesp 4
+
+00001d20 <.LM717>:
+    1d20:	d4          	im -44
+    1d21:	99          	im 25
+    1d22:	3f          	callpcrel
+    1d23:	fb          	im -5
+    1d24:	fd          	im -3
+    1d25:	39          	poppcrel
+
+00001d26 <.L545>:
+    1d26:	83          	im 3
+    1d27:	e2          	im -30
+    1d28:	ea          	im -22
+    1d29:	33          	loadb
+    1d2a:	83          	im 3
+    1d2b:	e2          	im -30
+    1d2c:	eb          	im -21
+    1d2d:	33          	loadb
+    1d2e:	71          	loadsp 4
+    1d2f:	88          	im 8
+    1d30:	2b          	ashiftleft
+    1d31:	07          	or
+    1d32:	55          	storesp 20
+    1d33:	56          	storesp 24
+    1d34:	ad          	im 45
+    1d35:	80          	im 0
+    1d36:	74          	loadsp 16
+    1d37:	27          	ulessthanorequal
+    1d38:	fd          	im -3
+    1d39:	ad          	im 45
+    1d3a:	38          	neqbranch
+
+00001d3b <.LM719>:
+    1d3b:	81          	im 1
+    1d3c:	98          	im 24
+    1d3d:	55          	storesp 20
+
+00001d3e <.LM720>:
+    1d3e:	74          	loadsp 16
+    1d3f:	83          	im 3
+    1d40:	e0          	im -32
+    1d41:	c8          	im -56
+    1d42:	34          	storeb
+
+00001d43 <.LM721>:
+    1d43:	ff          	im -1
+    1d44:	0b          	nop
+    1d45:	83          	im 3
+    1d46:	e0          	im -32
+    1d47:	c9          	im -55
+    1d48:	34          	storeb
+
+00001d49 <.LM722>:
+    1d49:	e0          	im -32
+    1d4a:	0b          	nop
+    1d4b:	83          	im 3
+    1d4c:	e0          	im -32
+    1d4d:	ca          	im -54
+    1d4e:	34          	storeb
+
+00001d4f <.LM723>:
+    1d4f:	80          	im 0
+    1d50:	0b          	nop
+    1d51:	83          	im 3
+    1d52:	e0          	im -32
+    1d53:	cb          	im -53
+    1d54:	34          	storeb
+
+00001d55 <.LM724>:
+    1d55:	84          	im 4
+    1d56:	52          	storesp 8
+    1d57:	83          	im 3
+    1d58:	e0          	im -32
+    1d59:	c8          	im -56
+    1d5a:	51          	storesp 4
+    1d5b:	b0          	im 48
+    1d5c:	9c          	im 28
+    1d5d:	3f          	callpcrel
+
+00001d5e <.LM725>:
+    1d5e:	84          	im 4
+    1d5f:	51          	storesp 4
+    1d60:	f8          	im -8
+    1d61:	8f          	im 15
+    1d62:	3f          	callpcrel
+
+00001d63 <.LM726>:
+    1d63:	83          	im 3
+    1d64:	e0          	im -32
+    1d65:	c8          	im -56
+    1d66:	33          	loadb
+    1d67:	51          	storesp 4
+    1d68:	ae          	im 46
+    1d69:	92          	im 18
+    1d6a:	3f          	callpcrel
+
+00001d6b <.LM727>:
+    1d6b:	0b          	nop
+    1d6c:	0b          	nop
+    1d6d:	80          	im 0
+    1d6e:	f9          	im -7
+    1d6f:	a0          	im 32
+    1d70:	51          	storesp 4
+    1d71:	fd          	im -3
+    1d72:	a7          	im 39
+    1d73:	39          	poppcrel
+
+00001d74 <.L518>:
+    1d74:	76          	loadsp 24
+    1d75:	81          	im 1
+    1d76:	80          	im 0
+    1d77:	29          	mult
+    1d78:	16          	addsp 24
+    1d79:	ff          	im -1
+    1d7a:	80          	im 0
+    1d7b:	05          	add
+    1d7c:	56          	storesp 24
+
+00001d7d <.LM729>:
+    1d7d:	81          	im 1
+    1d7e:	80          	im 0
+
+00001d7f <.LM730>:
+    1d7f:	76          	loadsp 24
+    1d80:	83          	im 3
+    1d81:	ff          	im -1
+    1d82:	ff          	im -1
+    1d83:	06          	and
+    1d84:	52          	storesp 8
+    1d85:	55          	storesp 20
+    1d86:	ad          	im 45
+    1d87:	f4          	im -12
+    1d88:	3f          	callpcrel
+
+00001d89 <.LM731>:
+    1d89:	0b          	nop
+    1d8a:	0b          	nop
+    1d8b:	80          	im 0
+    1d8c:	f9          	im -7
+    1d8d:	c4          	im -60
+    1d8e:	51          	storesp 4
+    1d8f:	ac          	im 44
+    1d90:	dc          	im -36
+    1d91:	3f          	callpcrel
+
+00001d92 <.LM732>:
+    1d92:	75          	loadsp 20
+    1d93:	51          	storesp 4
+    1d94:	98          	im 24
+    1d95:	fd          	im -3
+    1d96:	3f          	callpcrel
+
+00001d97 <.LM733>:
+    1d97:	7c          	loadsp 48
+    1d98:	53          	storesp 12
+    1d99:	74          	loadsp 16
+    1d9a:	83          	im 3
+    1d9b:	ff          	im -1
+    1d9c:	ff          	im -1
+    1d9d:	06          	and
+    1d9e:	70          	loadsp 0
+    1d9f:	53          	storesp 12
+    1da0:	83          	im 3
+    1da1:	e0          	im -32
+    1da2:	c8          	im -56
+    1da3:	52          	storesp 8
+    1da4:	54          	storesp 16
+    1da5:	96          	im 22
+    1da6:	ce          	im -50
+    1da7:	3f          	callpcrel
+    1da8:	fe          	im -2
+    1da9:	bf          	im 63
+    1daa:	39          	poppcrel
+
+00001dab <.L546>:
+    1dab:	83          	im 3
+    1dac:	e3          	im -29
+    1dad:	94          	im 20
+    1dae:	08          	load
+    1daf:	80          	im 0
+    1db0:	fc          	im -4
+    1db1:	05          	add
+    1db2:	54          	storesp 16
+    1db3:	80          	im 0
+    1db4:	fd          	im -3
+    1db5:	52          	storesp 8
+    1db6:	73          	loadsp 12
+    1db7:	51          	storesp 4
+    1db8:	b0          	im 48
+    1db9:	c8          	im -56
+    1dba:	3f          	callpcrel
+    1dbb:	83          	im 3
+    1dbc:	e0          	im -32
+    1dbd:	80          	im 0
+    1dbe:	08          	load
+
+00001dbf <.LM735>:
+    1dbf:	0b          	nop
+    1dc0:	0b          	nop
+    1dc1:	80          	im 0
+    1dc2:	f5          	im -11
+    1dc3:	f0          	im -16
+    1dc4:	52          	storesp 8
+    1dc5:	5c          	storesp 48
+    1dc6:	ac          	im 44
+    1dc7:	a5          	im 37
+    1dc8:	3f          	callpcrel
+
+00001dc9 <.LM736>:
+    1dc9:	82          	im 2
+    1dca:	77          	loadsp 28
+    1dcb:	25          	lessthanorequal
+    1dcc:	81          	im 1
+    1dcd:	c0          	im -64
+    1dce:	38          	neqbranch
+
+00001dcf <.LM737>:
+    1dcf:	76          	loadsp 24
+    1dd0:	82          	im 2
+    1dd1:	e8          	im -24
+    1dd2:	2e          	eq
+    1dd3:	84          	im 4
+    1dd4:	8d          	im 13
+    1dd5:	38          	neqbranch
+
+00001dd6 <.LM738>:
+    1dd6:	76          	loadsp 24
+    1dd7:	82          	im 2
+    1dd8:	e9          	im -23
+    1dd9:	2e          	eq
+    1dda:	82          	im 2
+    1ddb:	86          	im 6
+    1ddc:	38          	neqbranch
+
+00001ddd <.LM739>:
+    1ddd:	76          	loadsp 24
+    1dde:	82          	im 2
+    1ddf:	f0          	im -16
+    1de0:	24          	lessthan
+    1de1:	ba          	im 58
+    1de2:	38          	neqbranch
+
+00001de3 <.L484>:
+    1de3:	0b          	nop
+    1de4:	0b          	nop
+    1de5:	80          	im 0
+    1de6:	f9          	im -7
+    1de7:	bc          	im 60
+    1de8:	51          	storesp 4
+    1de9:	ac          	im 44
+    1dea:	82          	im 2
+    1deb:	3f          	callpcrel
+
+00001dec <.LM741>:
+    1dec:	81          	im 1
+    1ded:	80          	im 0
+    1dee:	54          	storesp 16
+
+00001def <.L553>:
+    1def:	73          	loadsp 12
+    1df0:	51          	storesp 4
+    1df1:	f6          	im -10
+    1df2:	fe          	im -2
+    1df3:	3f          	callpcrel
+
+00001df4 <.LM743>:
+    1df4:	73          	loadsp 12
+    1df5:	52          	storesp 8
+    1df6:	84          	im 4
+    1df7:	88          	im 8
+    1df8:	80          	im 0
+    1df9:	51          	storesp 4
+    1dfa:	d1          	im -47
+    1dfb:	f4          	im -12
+    1dfc:	3f          	callpcrel
+    1dfd:	83          	im 3
+    1dfe:	e0          	im -32
+    1dff:	80          	im 0
+    1e00:	08          	load
+    1e01:	81          	im 1
+    1e02:	ff          	im -1
+    1e03:	06          	and
+
+00001e04 <.LM744>:
+    1e04:	0b          	nop
+    1e05:	0b          	nop
+    1e06:	80          	im 0
+    1e07:	f9          	im -7
+    1e08:	b0          	im 48
+    1e09:	52          	storesp 8
+    1e0a:	54          	storesp 16
+    1e0b:	ab          	im 43
+    1e0c:	e0          	im -32
+    1e0d:	3f          	callpcrel
+
+00001e0e <.LM745>:
+    1e0e:	73          	loadsp 12
+    1e0f:	51          	storesp 4
+    1e10:	ac          	im 44
+    1e11:	ea          	im -22
+    1e12:	3f          	callpcrel
+
+00001e13 <.LM746>:
+    1e13:	0b          	nop
+    1e14:	0b          	nop
+    1e15:	80          	im 0
+    1e16:	f9          	im -7
+    1e17:	c4          	im -60
+    1e18:	51          	storesp 4
+    1e19:	fd          	im -3
+    1e1a:	f8          	im -8
+    1e1b:	39          	poppcrel
+
+00001e1c <.L551>:
+    1e1c:	0b          	nop
+    1e1d:	0b          	nop
+    1e1e:	80          	im 0
+    1e1f:	f9          	im -7
+    1e20:	c8          	im -56
+    1e21:	51          	storesp 4
+    1e22:	ab          	im 43
+    1e23:	c9          	im -55
+    1e24:	3f          	callpcrel
+
+00001e25 <.LM748>:
+    1e25:	76          	loadsp 24
+    1e26:	80          	im 0
+    1e27:	fd          	im -3
+    1e28:	29          	mult
+    1e29:	fd          	im -3
+    1e2a:	97          	im 23
+    1e2b:	d3          	im -45
+    1e2c:	05          	add
+    1e2d:	51          	storesp 4
+    1e2e:	97          	im 23
+    1e2f:	e3          	im -29
+    1e30:	3f          	callpcrel
+
+00001e31 <.LM749>:
+    1e31:	7c          	loadsp 48
+    1e32:	53          	storesp 12
+    1e33:	80          	im 0
+    1e34:	fd          	im -3
+    1e35:	52          	storesp 8
+    1e36:	83          	im 3
+    1e37:	e0          	im -32
+    1e38:	c8          	im -56
+    1e39:	51          	storesp 4
+    1e3a:	95          	im 21
+    1e3b:	b9          	im 57
+    1e3c:	3f          	callpcrel
+
+00001e3d <.LM750>:
+    1e3d:	90          	im 16
+    1e3e:	3d          	pushspadd
+    1e3f:	22          	loadh
+    1e40:	70          	loadsp 0
+    1e41:	83          	im 3
+    1e42:	ff          	im -1
+    1e43:	ff          	im -1
+    1e44:	06          	and
+
+00001e45 <.LM751>:
+    1e45:	81          	im 1
+    1e46:	19          	addsp 36
+    1e47:	59          	storesp 36
+    1e48:	55          	storesp 20
+    1e49:	56          	storesp 24
+
+00001e4a <.LM752>:
+    1e4a:	73          	loadsp 12
+    1e4b:	80          	im 0
+    1e4c:	fc          	im -4
+    1e4d:	26          	ulessthan
+    1e4e:	83          	im 3
+    1e4f:	38          	neqbranch
+
+00001e50 <.LM753>:
+    1e50:	74          	loadsp 16
+    1e51:	57          	storesp 28
+
+00001e52 <.L516>:
+    1e52:	76          	loadsp 24
+    1e53:	88          	im 8
+    1e54:	2c          	ashiftright
+    1e55:	54          	storesp 16
+    1e56:	73          	loadsp 12
+    1e57:	83          	im 3
+    1e58:	e1          	im -31
+    1e59:	c5          	im -59
+    1e5a:	34          	storeb
+
+00001e5b <.LM755>:
+    1e5b:	76          	loadsp 24
+    1e5c:	83          	im 3
+    1e5d:	e1          	im -31
+    1e5e:	c6          	im -58
+    1e5f:	34          	storeb
+
+00001e60 <.LM756>:
+    1e60:	75          	loadsp 20
+    1e61:	83          	im 3
+    1e62:	e1          	im -31
+    1e63:	c7          	im -57
+    1e64:	34          	storeb
+
+00001e65 <.LM757>:
+    1e65:	0b          	nop
+    1e66:	0b          	nop
+    1e67:	80          	im 0
+    1e68:	f9          	im -7
+    1e69:	bc          	im 60
+    1e6a:	51          	storesp 4
+    1e6b:	ab          	im 43
+    1e6c:	80          	im 0
+    1e6d:	3f          	callpcrel
+
+00001e6e <.LM758>:
+    1e6e:	81          	im 1
+    1e6f:	80          	im 0
+    1e70:	54          	storesp 16
+    1e71:	fe          	im -2
+    1e72:	fc          	im -4
+    1e73:	39          	poppcrel
+
+00001e74 <.L469>:
+    1e74:	a8          	im 40
+    1e75:	0b          	nop
+    1e76:	83          	im 3
+    1e77:	e3          	im -29
+    1e78:	8c          	im 12
+    1e79:	0c          	store
+
+00001e7a <.LM760>:
+    1e7a:	0b          	nop
+    1e7b:	0b          	nop
+    1e7c:	80          	im 0
+    1e7d:	f8          	im -8
+    1e7e:	c4          	im -60
+    1e7f:	51          	storesp 4
+    1e80:	aa          	im 42
+    1e81:	eb          	im -21
+    1e82:	3f          	callpcrel
+
+00001e83 <.LM761>:
+    1e83:	83          	im 3
+    1e84:	e3          	im -29
+    1e85:	8e          	im 14
+    1e86:	22          	loadh
+    1e87:	51          	storesp 4
+    1e88:	ab          	im 43
+    1e89:	f2          	im -14
+    1e8a:	3f          	callpcrel
+    1e8b:	fa          	im -6
+    1e8c:	ab          	im 43
+    1e8d:	39          	poppcrel
+
+00001e8e <.L548>:
+    1e8e:	0b          	nop
+    1e8f:	0b          	nop
+    1e90:	80          	im 0
+    1e91:	f9          	im -7
+    1e92:	d0          	im -48
+    1e93:	51          	storesp 4
+    1e94:	aa          	im 42
+    1e95:	d7          	im -41
+    1e96:	3f          	callpcrel
+
+00001e97 <.LM763>:
+    1e97:	ff          	im -1
+    1e98:	17          	addsp 28
+    1e99:	70          	loadsp 0
+    1e9a:	87          	im 7
+    1e9b:	2b          	ashiftleft
+    1e9c:	83          	im 3
+    1e9d:	ff          	im -1
+    1e9e:	ff          	im -1
+    1e9f:	80          	im 0
+    1ea0:	06          	and
+    1ea1:	80          	im 0
+    1ea2:	f9          	im -7
+    1ea3:	f8          	im -8
+    1ea4:	05          	add
+
+00001ea5 <.LM764>:
+    1ea5:	83          	im 3
+    1ea6:	e0          	im -32
+    1ea7:	c8          	im -56
+    1ea8:	58          	storesp 32
+    1ea9:	56          	storesp 24
+    1eaa:	54          	storesp 16
+
+00001eab <.LM765>:
+    1eab:	81          	im 1
+    1eac:	80          	im 0
+    1ead:	54          	storesp 16
+
+00001eae <.L481>:
+    1eae:	74          	loadsp 16
+    1eaf:	70          	loadsp 0
+    1eb0:	81          	im 1
+    1eb1:	05          	add
+    1eb2:	56          	storesp 24
+    1eb3:	33          	loadb
+    1eb4:	76          	loadsp 24
+    1eb5:	70          	loadsp 0
+    1eb6:	81          	im 1
+    1eb7:	05          	add
+    1eb8:	58          	storesp 32
+    1eb9:	34          	storeb
+
+00001eba <.LM767>:
+    1eba:	ff          	im -1
+    1ebb:	14          	addsp 16
+    1ebc:	70          	loadsp 0
+    1ebd:	81          	im 1
+    1ebe:	ff          	im -1
+    1ebf:	06          	and
+    1ec0:	51          	storesp 4
+    1ec1:	54          	storesp 16
+
+00001ec2 <.LM768>:
+    1ec2:	73          	loadsp 12
+    1ec3:	80          	im 0
+    1ec4:	2e          	eq
+    1ec5:	fe          	im -2
+    1ec6:	9c          	im 28
+    1ec7:	38          	neqbranch
+
+00001ec8 <.LM769>:
+    1ec8:	74          	loadsp 16
+    1ec9:	70          	loadsp 0
+    1eca:	81          	im 1
+    1ecb:	05          	add
+    1ecc:	56          	storesp 24
+    1ecd:	33          	loadb
+    1ece:	76          	loadsp 24
+    1ecf:	70          	loadsp 0
+    1ed0:	81          	im 1
+    1ed1:	05          	add
+    1ed2:	58          	storesp 32
+    1ed3:	34          	storeb
+
+00001ed4 <.LM770>:
+    1ed4:	ff          	im -1
+    1ed5:	14          	addsp 16
+    1ed6:	70          	loadsp 0
+    1ed7:	81          	im 1
+    1ed8:	ff          	im -1
+    1ed9:	06          	and
+    1eda:	51          	storesp 4
+    1edb:	54          	storesp 16
+
+00001edc <.LM771>:
+    1edc:	73          	loadsp 12
+    1edd:	d0          	im -48
+    1ede:	38          	neqbranch
+    1edf:	fe          	im -2
+    1ee0:	82          	im 2
+    1ee1:	39          	poppcrel
+
+00001ee2 <.L550>:
+    1ee2:	0b          	nop
+    1ee3:	0b          	nop
+    1ee4:	80          	im 0
+    1ee5:	f9          	im -7
+    1ee6:	d8          	im -40
+    1ee7:	51          	storesp 4
+    1ee8:	aa          	im 42
+    1ee9:	83          	im 3
+    1eea:	3f          	callpcrel
+
+00001eeb <.LBB38>:
+    1eeb:	74          	loadsp 16
+    1eec:	75          	loadsp 20
+    1eed:	59          	storesp 36
+    1eee:	57          	storesp 28
+
+00001eef <.L502>:
+    1eef:	80          	im 0
+    1ef0:	0b          	nop
+    1ef1:	83          	im 3
+    1ef2:	e2          	im -30
+    1ef3:	d8          	im -40
+    1ef4:	18          	addsp 32
+    1ef5:	33          	loadb
+    1ef6:	70          	loadsp 0
+    1ef7:	81          	im 1
+    1ef8:	ff          	im -1
+    1ef9:	06          	and
+    1efa:	ff          	im -1
+    1efb:	bf          	im 63
+    1efc:	11          	addsp 4
+    1efd:	57          	storesp 28
+    1efe:	57          	storesp 28
+    1eff:	5b          	storesp 44
+    1f00:	5b          	storesp 44
+    1f01:	73          	loadsp 12
+    1f02:	99          	im 25
+    1f03:	26          	ulessthan
+    1f04:	83          	im 3
+    1f05:	38          	neqbranch
+    1f06:	81          	im 1
+    1f07:	5b          	storesp 44
+
+00001f08 <.L493>:
+    1f08:	80          	im 0
+    1f09:	0b          	nop
+    1f0a:	d0          	im -48
+    1f0b:	16          	addsp 24
+    1f0c:	55          	storesp 20
+    1f0d:	56          	storesp 24
+    1f0e:	73          	loadsp 12
+    1f0f:	89          	im 9
+    1f10:	26          	ulessthan
+    1f11:	83          	im 3
+    1f12:	38          	neqbranch
+    1f13:	81          	im 1
+    1f14:	56          	storesp 24
+
+00001f15 <.L494>:
+    1f15:	7a          	loadsp 40
+    1f16:	76          	loadsp 24
+    1f17:	07          	or
+    1f18:	54          	storesp 16
+    1f19:	73          	loadsp 12
+    1f1a:	80          	im 0
+    1f1b:	2e          	eq
+    1f1c:	8f          	im 15
+    1f1d:	38          	neqbranch
+
+00001f1e <.LM775>:
+    1f1e:	79          	loadsp 36
+    1f1f:	83          	im 3
+    1f20:	e0          	im -32
+    1f21:	c8          	im -56
+    1f22:	19          	addsp 36
+    1f23:	34          	storeb
+
+00001f24 <.LM776>:
+    1f24:	81          	im 1
+    1f25:	18          	addsp 32
+    1f26:	70          	loadsp 0
+    1f27:	81          	im 1
+    1f28:	ff          	im -1
+    1f29:	06          	and
+    1f2a:	59          	storesp 36
+    1f2b:	54          	storesp 16
+
+00001f2c <.L492>:
+    1f2c:	76          	loadsp 24
+    1f2d:	87          	im 7
+    1f2e:	32          	xor
+    1f2f:	70          	loadsp 0
+    1f30:	30          	neg
+    1f31:	70          	loadsp 0
+    1f32:	72          	loadsp 8
+    1f33:	07          	or
+    1f34:	80          	im 0
+    1f35:	25          	lessthanorequal
+    1f36:	79          	loadsp 36
+    1f37:	8a          	im 10
+    1f38:	32          	xor
+    1f39:	70          	loadsp 0
+    1f3a:	30          	neg
+    1f3b:	70          	loadsp 0
+    1f3c:	72          	loadsp 8
+    1f3d:	07          	or
+    1f3e:	80          	im 0
+    1f3f:	25          	lessthanorequal
+    1f40:	73          	loadsp 12
+    1f41:	07          	or
+    1f42:	53          	storesp 12
+    1f43:	54          	storesp 16
+    1f44:	59          	storesp 36
+    1f45:	51          	storesp 4
+    1f46:	56          	storesp 24
+    1f47:	54          	storesp 16
+    1f48:	74          	loadsp 16
+    1f49:	80          	im 0
+    1f4a:	2e          	eq
+    1f4b:	9a          	im 26
+    1f4c:	38          	neqbranch
+
+00001f4d <.LM778>:
+    1f4d:	77          	loadsp 28
+    1f4e:	77          	loadsp 28
+    1f4f:	26          	ulessthan
+    1f50:	95          	im 21
+    1f51:	38          	neqbranch
+
+00001f52 <.L554>:
+    1f52:	a0          	im 32
+    1f53:	0b          	nop
+    1f54:	83          	im 3
+    1f55:	e0          	im -32
+    1f56:	c8          	im -56
+    1f57:	19          	addsp 36
+    1f58:	34          	storeb
+    1f59:	81          	im 1
+    1f5a:	18          	addsp 32
+    1f5b:	70          	loadsp 0
+    1f5c:	81          	im 1
+    1f5d:	ff          	im -1
+    1f5e:	06          	and
+    1f5f:	59          	storesp 36
+    1f60:	54          	storesp 16
+    1f61:	76          	loadsp 24
+    1f62:	78          	loadsp 32
+    1f63:	27          	ulessthanorequal
+    1f64:	ed          	im -19
+    1f65:	38          	neqbranch
+
+00001f66 <.L491>:
+    1f66:	81          	im 1
+    1f67:	17          	addsp 28
+    1f68:	70          	loadsp 0
+    1f69:	81          	im 1
+    1f6a:	ff          	im -1
+    1f6b:	06          	and
+    1f6c:	58          	storesp 32
+    1f6d:	54          	storesp 16
+    1f6e:	8a          	im 10
+    1f6f:	77          	loadsp 28
+    1f70:	27          	ulessthanorequal
+    1f71:	fe          	im -2
+    1f72:	fc          	im -4
+    1f73:	38          	neqbranch
+
+00001f74 <.LM780>:
+    1f74:	8f          	im 15
+    1f75:	57          	storesp 28
+
+00001f76 <.L506>:
+    1f76:	83          	im 3
+    1f77:	e0          	im -32
+    1f78:	c3          	im -61
+    1f79:	17          	addsp 28
+    1f7a:	33          	loadb
+    1f7b:	83          	im 3
+    1f7c:	e0          	im -32
+    1f7d:	c8          	im -56
+    1f7e:	18          	addsp 32
+    1f7f:	34          	storeb
+    1f80:	ff          	im -1
+    1f81:	17          	addsp 28
+    1f82:	70          	loadsp 0
+    1f83:	81          	im 1
+    1f84:	ff          	im -1
+    1f85:	06          	and
+    1f86:	58          	storesp 32
+    1f87:	54          	storesp 16
+    1f88:	76          	loadsp 24
+    1f89:	84          	im 4
+    1f8a:	26          	ulessthan
+    1f8b:	ea          	im -22
+    1f8c:	38          	neqbranch
+
+00001f8d <.LM781>:
+    1f8d:	90          	im 16
+    1f8e:	57          	storesp 28
+
+00001f8f <.L510>:
+    1f8f:	80          	im 0
+    1f90:	0b          	nop
+    1f91:	83          	im 3
+    1f92:	e0          	im -32
+    1f93:	c8          	im -56
+    1f94:	18          	addsp 32
+    1f95:	34          	storeb
+
+00001f96 <.LM783>:
+    1f96:	81          	im 1
+    1f97:	17          	addsp 28
+    1f98:	70          	loadsp 0
+    1f99:	81          	im 1
+    1f9a:	ff          	im -1
+    1f9b:	06          	and
+    1f9c:	70          	loadsp 0
+    1f9d:	98          	im 24
+    1f9e:	2b          	ashiftleft
+    1f9f:	52          	storesp 8
+    1fa0:	58          	storesp 32
+    1fa1:	54          	storesp 16
+    1fa2:	73          	loadsp 12
+    1fa3:	80          	im 0
+    1fa4:	25          	lessthanorequal
+    1fa5:	e9          	im -23
+    1fa6:	38          	neqbranch
+
+00001fa7 <.LBE38>:
+    1fa7:	80          	im 0
+    1fa8:	c6          	im -58
+    1fa9:	54          	storesp 16
+    1faa:	7b          	loadsp 44
+    1fab:	85          	im 5
+    1fac:	8f          	im 15
+    1fad:	24          	lessthan
+    1fae:	84          	im 4
+    1faf:	38          	neqbranch
+    1fb0:	80          	im 0
+    1fb1:	c2          	im -62
+    1fb2:	54          	storesp 16
+
+00001fb3 <.L512>:
+    1fb3:	73          	loadsp 12
+    1fb4:	83          	im 3
+    1fb5:	e0          	im -32
+    1fb6:	c8          	im -56
+    1fb7:	34          	storeb
+
+00001fb8 <.LM785>:
+    1fb8:	80          	im 0
+    1fb9:	f1          	im -15
+    1fba:	0b          	nop
+    1fbb:	83          	im 3
+    1fbc:	e0          	im -32
+    1fbd:	cb          	im -53
+    1fbe:	34          	storeb
+    1fbf:	81          	im 1
+    1fc0:	0b          	nop
+    1fc1:	83          	im 3
+    1fc2:	e0          	im -32
+    1fc3:	cc          	im -52
+    1fc4:	34          	storeb
+
+00001fc5 <.L486>:
+    1fc5:	7b          	loadsp 44
+    1fc6:	83          	im 3
+    1fc7:	e0          	im -32
+    1fc8:	c9          	im -55
+    1fc9:	34          	storeb
+    1fca:	7b          	loadsp 44
+    1fcb:	88          	im 8
+    1fcc:	2c          	ashiftright
+    1fcd:	54          	storesp 16
+    1fce:	73          	loadsp 12
+    1fcf:	83          	im 3
+    1fd0:	e0          	im -32
+    1fd1:	ca          	im -54
+    1fd2:	34          	storeb
+
+00001fd3 <.L555>:
+    1fd3:	0b          	nop
+    1fd4:	0b          	nop
+    1fd5:	80          	im 0
+    1fd6:	f9          	im -7
+    1fd7:	bc          	im 60
+    1fd8:	51          	storesp 4
+    1fd9:	a8          	im 40
+    1fda:	92          	im 18
+    1fdb:	3f          	callpcrel
+
+00001fdc <.LM788>:
+    1fdc:	81          	im 1
+    1fdd:	80          	im 0
+    1fde:	54          	storesp 16
+    1fdf:	fc          	im -4
+    1fe0:	8e          	im 14
+    1fe1:	39          	poppcrel
+
+00001fe2 <.L549>:
+    1fe2:	0b          	nop
+    1fe3:	0b          	nop
+    1fe4:	80          	im 0
+    1fe5:	f9          	im -7
+    1fe6:	e0          	im -32
+    1fe7:	51          	storesp 4
+    1fe8:	a8          	im 40
+    1fe9:	83          	im 3
+    1fea:	3f          	callpcrel
+
+00001feb <.LM790>:
+    1feb:	7b          	loadsp 44
+    1fec:	83          	im 3
+    1fed:	e0          	im -32
+    1fee:	c9          	im -55
+    1fef:	34          	storeb
+    1ff0:	7b          	loadsp 44
+    1ff1:	88          	im 8
+    1ff2:	2c          	ashiftright
+    1ff3:	54          	storesp 16
+    1ff4:	73          	loadsp 12
+    1ff5:	83          	im 3
+    1ff6:	e0          	im -32
+    1ff7:	ca          	im -54
+    1ff8:	34          	storeb
+    1ff9:	d9          	im -39
+    1ffa:	39          	poppcrel
+
+00001ffb <main>:
+    1ffb:	ff          	im -1
+    1ffc:	3d          	pushspadd
+    1ffd:	0d          	popsp
+
+00001ffe <.LM792>:
+    1ffe:	80          	im 0
+    1fff:	0b          	nop
+    2000:	83          	im 3
+    2001:	e0          	im -32
+    2002:	ac          	im 44
+    2003:	0c          	store
+
+00002004 <.LM793>:
+    2004:	80          	im 0
+    2005:	0b          	nop
+    2006:	83          	im 3
+    2007:	e3          	im -29
+    2008:	a8          	im 40
+    2009:	0c          	store
+
+0000200a <.LM794>:
+    200a:	80          	im 0
+    200b:	0b          	nop
+    200c:	83          	im 3
+    200d:	e0          	im -32
+    200e:	b4          	im 52
+    200f:	0c          	store
+
+00002010 <.LM795>:
+    2010:	81          	im 1
+    2011:	51          	storesp 4
+    2012:	cc          	im -52
+    2013:	fa          	im -6
+    2014:	3f          	callpcrel
+
+00002015 <.LM796>:
+    2015:	a8          	im 40
+    2016:	0b          	nop
+    2017:	83          	im 3
+    2018:	e3          	im -29
+    2019:	8c          	im 12
+    201a:	0c          	store
+
+0000201b <.LM797>:
+    201b:	83          	im 3
+    201c:	e0          	im -32
+    201d:	ac          	im 44
+    201e:	08          	load
+    201f:	51          	storesp 4
+    2020:	a5          	im 37
+    2021:	bb          	im 59
+    2022:	3f          	callpcrel
+
+00002023 <.LM798>:
+    2023:	83          	im 3
+    2024:	e0          	im -32
+    2025:	ac          	im 44
+    2026:	08          	load
+    2027:	ab          	im 43
+    2028:	38          	neqbranch
+
+00002029 <.LM799>:
+    2029:	f3          	im -13
+    202a:	a8          	im 40
+    202b:	3f          	callpcrel
+
+0000202c <.LM800>:
+    202c:	81          	im 1
+    202d:	51          	storesp 4
+    202e:	cc          	im -52
+    202f:	de          	im -34
+    2030:	3f          	callpcrel
+
+00002031 <.LM801>:
+    2031:	80          	im 0
+    2032:	51          	storesp 4
+    2033:	cc          	im -52
+    2034:	b5          	im 53
+    2035:	3f          	callpcrel
+
+00002036 <.LM802>:
+    2036:	80          	im 0
+    2037:	fb          	im -5
+    2038:	e4          	im -28
+    2039:	08          	load
+    203a:	52          	storesp 8
+    203b:	80          	im 0
+    203c:	72          	loadsp 8
+    203d:	34          	storeb
+
+0000203e <.LM803>:
+    203e:	cb          	im -53
+    203f:	b0          	im 48
+    2040:	3f          	callpcrel
+
+00002041 <.LM804>:
+    2041:	81          	im 1
+    2042:	51          	storesp 4
+    2043:	cc          	im -52
+    2044:	a5          	im 37
+    2045:	3f          	callpcrel
+
+00002046 <.LM805>:
+    2046:	80          	im 0
+    2047:	51          	storesp 4
+    2048:	cc          	im -52
+    2049:	c4          	im -60
+    204a:	3f          	callpcrel
+
+0000204b <.L559>:
+    204b:	da          	im -38
+    204c:	8c          	im 12
+    204d:	3f          	callpcrel
+    204e:	da          	im -38
+    204f:	89          	im 9
+    2050:	3f          	callpcrel
+    2051:	f9          	im -7
+    2052:	39          	poppcrel
+
+00002053 <.L562>:
+    2053:	80          	im 0
+    2054:	51          	storesp 4
+    2055:	cc          	im -52
+    2056:	93          	im 19
+    2057:	3f          	callpcrel
+
+00002058 <.LM808>:
+    2058:	80          	im 0
+    2059:	fb          	im -5
+    205a:	e4          	im -28
+    205b:	08          	load
+    205c:	52          	storesp 8
+    205d:	80          	im 0
+    205e:	72          	loadsp 8
+    205f:	34          	storeb
+
+00002060 <.LM809>:
+    2060:	cb          	im -53
+    2061:	8e          	im 14
+    2062:	3f          	callpcrel
+
+00002063 <.LM810>:
+    2063:	81          	im 1
+    2064:	51          	storesp 4
+    2065:	cc          	im -52
+    2066:	83          	im 3
+    2067:	3f          	callpcrel
+
+00002068 <.LM811>:
+    2068:	80          	im 0
+    2069:	51          	storesp 4
+    206a:	cc          	im -52
+    206b:	a2          	im 34
+    206c:	3f          	callpcrel
+
+0000206d <.LM812>:
+    206d:	80          	im 0
+    206e:	fa          	im -6
+    206f:	89          	im 9
+    2070:	80          	im 0
+    2071:	51          	storesp 4
+    2072:	c8          	im -56
+    2073:	bf          	im 63
+    2074:	3f          	callpcrel
+
+00002075 <.LM813>:
+    2075:	f2          	im -14
+    2076:	dc          	im -36
+    2077:	3f          	callpcrel
+
+00002078 <.LM814>:
+    2078:	81          	im 1
+    2079:	51          	storesp 4
+    207a:	cc          	im -52
+    207b:	92          	im 18
+    207c:	3f          	callpcrel
+
+0000207d <.LM815>:
+    207d:	80          	im 0
+    207e:	51          	storesp 4
+    207f:	cb          	im -53
+    2080:	e9          	im -23
+    2081:	3f          	callpcrel
+
+00002082 <.LM816>:
+    2082:	80          	im 0
+    2083:	fb          	im -5
+    2084:	e4          	im -28
+    2085:	08          	load
+    2086:	52          	storesp 8
+    2087:	80          	im 0
+    2088:	72          	loadsp 8
+    2089:	34          	storeb
+
+0000208a <.LM817>:
+    208a:	ca          	im -54
+    208b:	e4          	im -28
+    208c:	3f          	callpcrel
+
+0000208d <.LM818>:
+    208d:	81          	im 1
+    208e:	51          	storesp 4
+    208f:	cb          	im -53
+    2090:	d9          	im -39
+    2091:	3f          	callpcrel
+
+00002092 <.LM819>:
+    2092:	80          	im 0
+    2093:	51          	storesp 4
+    2094:	cb          	im -53
+    2095:	f8          	im -8
+    2096:	3f          	callpcrel
+    2097:	ff          	im -1
+    2098:	b2          	im 50
+    2099:	39          	poppcrel
+
+0000209a <get_fat>:
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+    209a:	f7          	im -9
+    209b:	3d          	pushspadd
+    209c:	0d          	popsp
+    209d:	7b          	loadsp 44
+
+0000209e <.LM2>:
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+    209e:	83          	im 3
+    209f:	e0          	im -32
+    20a0:	90          	im 16
+    20a1:	08          	load
+    20a2:	57          	storesp 28
+    20a3:	58          	storesp 32
+
+000020a4 <.LM3>:
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+    20a4:	81          	im 1
+    20a5:	78          	loadsp 32
+    20a6:	27          	ulessthanorequal
+    20a7:	9c          	im 28
+    20a8:	38          	neqbranch
+    20a9:	77          	loadsp 28
+    20aa:	88          	im 8
+    20ab:	17          	addsp 28
+    20ac:	08          	load
+    20ad:	27          	ulessthanorequal
+    20ae:	95          	im 21
+    20af:	38          	neqbranch
+
+000020b0 <.LM4>:
+		return 1;
+
+	switch (fs->fs_type) {
+    20b0:	75          	loadsp 20
+    20b1:	33          	loadb
+    20b2:	57          	storesp 28
+    20b3:	76          	loadsp 24
+    20b4:	82          	im 2
+    20b5:	2e          	eq
+    20b6:	81          	im 1
+    20b7:	d0          	im -48
+    20b8:	38          	neqbranch
+    20b9:	76          	loadsp 24
+    20ba:	82          	im 2
+    20bb:	24          	lessthan
+    20bc:	91          	im 17
+    20bd:	38          	neqbranch
+    20be:	76          	loadsp 24
+    20bf:	81          	im 1
+    20c0:	2e          	eq
+    20c1:	80          	im 0
+    20c2:	e6          	im -26
+    20c3:	38          	neqbranch
+
+000020c4 <.L4>:
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+    20c4:	81          	im 1
+
+000020c5 <.LM6>:
+}
+    20c5:	0b          	nop
+    20c6:	83          	im 3
+    20c7:	e0          	im -32
+    20c8:	80          	im 0
+    20c9:	0c          	store
+    20ca:	8b          	im 11
+    20cb:	3d          	pushspadd
+    20cc:	0d          	popsp
+    20cd:	04          	poppc
+
+000020ce <.L17>:
+    20ce:	76          	loadsp 24
+    20cf:	83          	im 3
+    20d0:	2e          	eq
+    20d1:	09          	not
+    20d2:	81          	im 1
+    20d3:	06          	and
+    20d4:	ef          	im -17
+    20d5:	38          	neqbranch
+
+000020d6 <.LM8>:
+    20d6:	84          	im 4
+    20d7:	54          	storesp 16
+    20d8:	77          	loadsp 28
+    20d9:	82          	im 2
+    20da:	2b          	ashiftleft
+    20db:	83          	im 3
+    20dc:	fc          	im -4
+    20dd:	06          	and
+    20de:	53          	storesp 12
+    20df:	77          	loadsp 28
+    20e0:	87          	im 7
+    20e1:	2a          	lshiftright
+    20e2:	8c          	im 12
+    20e3:	17          	addsp 28
+    20e4:	08          	load
+    20e5:	05          	add
+    20e6:	52          	storesp 8
+    20e7:	8b          	im 11
+    20e8:	3d          	pushspadd
+    20e9:	fc          	im -4
+    20ea:	05          	add
+    20eb:	51          	storesp 4
+    20ec:	f0          	im -16
+    20ed:	91          	im 17
+    20ee:	3f          	callpcrel
+    20ef:	83          	im 3
+    20f0:	e0          	im -32
+    20f1:	80          	im 0
+    20f2:	08          	load
+    20f3:	d0          	im -48
+    20f4:	38          	neqbranch
+
+000020f5 <.LM9>:
+    20f5:	02          	pushsp
+    20f6:	a7          	im 39
+    20f7:	05          	add
+    20f8:	33          	loadb
+    20f9:	02          	pushsp
+    20fa:	84          	im 4
+    20fb:	05          	add
+    20fc:	a6          	im 38
+    20fd:	05          	add
+    20fe:	33          	loadb
+    20ff:	71          	loadsp 4
+    2100:	98          	im 24
+    2101:	2b          	ashiftleft
+    2102:	71          	loadsp 4
+    2103:	90          	im 16
+    2104:	2b          	ashiftleft
+    2105:	07          	or
+    2106:	02          	pushsp
+    2107:	8c          	im 12
+    2108:	05          	add
+    2109:	a5          	im 37
+    210a:	05          	add
+    210b:	33          	loadb
+    210c:	70          	loadsp 0
+    210d:	88          	im 8
+    210e:	2b          	ashiftleft
+    210f:	72          	loadsp 8
+    2110:	07          	or
+    2111:	8f          	im 15
+    2112:	3d          	pushspadd
+    2113:	33          	loadb
+    2114:	71          	loadsp 4
+    2115:	80          	im 0
+    2116:	ff          	im -1
+    2117:	ff          	im -1
+    2118:	fe          	im -2
+    2119:	80          	im 0
+    211a:	06          	and
+    211b:	07          	or
+
+0000211c <.LM10>:
+    211c:	83          	im 3
+    211d:	e0          	im -32
+    211e:	80          	im 0
+    211f:	0c          	store
+    2120:	52          	storesp 8
+    2121:	5c          	storesp 48
+    2122:	57          	storesp 28
+    2123:	58          	storesp 32
+    2124:	56          	storesp 24
+    2125:	8b          	im 11
+    2126:	3d          	pushspadd
+    2127:	0d          	popsp
+    2128:	04          	poppc
+
+00002129 <.L5>:
+    2129:	77          	loadsp 28
+    212a:	83          	im 3
+    212b:	ff          	im -1
+    212c:	ff          	im -1
+    212d:	06          	and
+    212e:	70          	loadsp 0
+    212f:	81          	im 1
+    2130:	2a          	lshiftright
+    2131:	11          	addsp 4
+    2132:	70          	loadsp 0
+    2133:	83          	im 3
+    2134:	ff          	im -1
+    2135:	ff          	im -1
+    2136:	06          	and
+
+00002137 <.LM12>:
+    2137:	70          	loadsp 0
+    2138:	83          	im 3
+    2139:	ff          	im -1
+    213a:	06          	and
+    213b:	71          	loadsp 4
+    213c:	89          	im 9
+    213d:	2a          	lshiftright
+    213e:	52          	storesp 8
+    213f:	5c          	storesp 48
+    2140:	51          	storesp 4
+    2141:	51          	storesp 4
+    2142:	55          	storesp 20
+
+00002143 <.LM13>:
+    2143:	78          	loadsp 32
+    2144:	83          	im 3
+    2145:	ff          	im -1
+    2146:	2e          	eq
+    2147:	80          	im 0
+    2148:	f2          	im -14
+    2149:	38          	neqbranch
+
+0000214a <.LM14>:
+    214a:	82          	im 2
+    214b:	54          	storesp 16
+    214c:	78          	loadsp 32
+    214d:	53          	storesp 12
+    214e:	8c          	im 12
+    214f:	16          	addsp 24
+    2150:	08          	load
+    2151:	15          	addsp 20
+    2152:	52          	storesp 8
+    2153:	8b          	im 11
+    2154:	3d          	pushspadd
+    2155:	fc          	im -4
+    2156:	05          	add
+    2157:	51          	storesp 4
+
+00002158 <.L18>:
+    2158:	ef          	im -17
+    2159:	a5          	im 37
+    215a:	3f          	callpcrel
+    215b:	83          	im 3
+    215c:	e0          	im -32
+    215d:	80          	im 0
+    215e:	08          	load
+    215f:	fe          	im -2
+    2160:	e3          	im -29
+    2161:	38          	neqbranch
+
+00002162 <.LM16>:
+    2162:	02          	pushsp
+    2163:	a5          	im 37
+    2164:	05          	add
+    2165:	33          	loadb
+    2166:	8b          	im 11
+    2167:	3d          	pushspadd
+    2168:	33          	loadb
+    2169:	71          	loadsp 4
+    216a:	88          	im 8
+    216b:	2b          	ashiftleft
+    216c:	07          	or
+
+0000216d <.LM17>:
+    216d:	79          	loadsp 36
+    216e:	81          	im 1
+    216f:	06          	and
+    2170:	71          	loadsp 4
+    2171:	84          	im 4
+    2172:	2a          	lshiftright
+    2173:	53          	storesp 12
+    2174:	57          	storesp 28
+    2175:	58          	storesp 32
+    2176:	56          	storesp 24
+    2177:	74          	loadsp 16
+    2178:	86          	im 6
+    2179:	38          	neqbranch
+    217a:	76          	loadsp 24
+    217b:	9f          	im 31
+    217c:	ff          	im -1
+    217d:	06          	and
+    217e:	56          	storesp 24
+
+0000217f <.L12>:
+    217f:	75          	loadsp 20
+
+00002180 <.LM18>:
+    2180:	83          	im 3
+    2181:	e0          	im -32
+    2182:	80          	im 0
+    2183:	0c          	store
+    2184:	8b          	im 11
+    2185:	3d          	pushspadd
+    2186:	0d          	popsp
+    2187:	04          	poppc
+
+00002188 <.L13>:
+    2188:	76          	loadsp 24
+    2189:	54          	storesp 16
+    218a:	77          	loadsp 28
+    218b:	10          	addsp 0
+    218c:	83          	im 3
+    218d:	fe          	im -2
+    218e:	06          	and
+    218f:	53          	storesp 12
+    2190:	77          	loadsp 28
+    2191:	88          	im 8
+    2192:	2a          	lshiftright
+    2193:	8c          	im 12
+    2194:	17          	addsp 28
+    2195:	08          	load
+    2196:	05          	add
+    2197:	52          	storesp 8
+    2198:	8b          	im 11
+    2199:	3d          	pushspadd
+    219a:	fc          	im -4
+    219b:	05          	add
+    219c:	51          	storesp 4
+    219d:	ee          	im -18
+    219e:	e0          	im -32
+    219f:	3f          	callpcrel
+    21a0:	83          	im 3
+    21a1:	e0          	im -32
+    21a2:	80          	im 0
+    21a3:	08          	load
+    21a4:	fe          	im -2
+    21a5:	9e          	im 30
+    21a6:	38          	neqbranch
+
+000021a7 <.LM20>:
+    21a7:	02          	pushsp
+    21a8:	a5          	im 37
+    21a9:	05          	add
+    21aa:	33          	loadb
+    21ab:	8b          	im 11
+    21ac:	3d          	pushspadd
+    21ad:	33          	loadb
+    21ae:	71          	loadsp 4
+    21af:	88          	im 8
+    21b0:	2b          	ashiftleft
+    21b1:	07          	or
+
+000021b2 <.LM21>:
+    21b2:	83          	im 3
+    21b3:	e0          	im -32
+    21b4:	80          	im 0
+    21b5:	0c          	store
+    21b6:	56          	storesp 24
+    21b7:	8b          	im 11
+    21b8:	3d          	pushspadd
+    21b9:	0d          	popsp
+    21ba:	04          	poppc
+
+000021bb <.L6>:
+    21bb:	76          	loadsp 24
+    21bc:	54          	storesp 16
+    21bd:	78          	loadsp 32
+    21be:	53          	storesp 12
+    21bf:	8c          	im 12
+    21c0:	16          	addsp 24
+    21c1:	08          	load
+    21c2:	15          	addsp 20
+    21c3:	52          	storesp 8
+    21c4:	8b          	im 11
+    21c5:	3d          	pushspadd
+    21c6:	fc          	im -4
+    21c7:	05          	add
+    21c8:	51          	storesp 4
+    21c9:	ee          	im -18
+    21ca:	b4          	im 52
+    21cb:	3f          	callpcrel
+    21cc:	83          	im 3
+    21cd:	e0          	im -32
+    21ce:	80          	im 0
+    21cf:	08          	load
+    21d0:	fd          	im -3
+    21d1:	f2          	im -14
+    21d2:	38          	neqbranch
+
+000021d3 <.LM23>:
+    21d3:	76          	loadsp 24
+    21d4:	54          	storesp 16
+    21d5:	83          	im 3
+    21d6:	e0          	im -32
+    21d7:	80          	im 0
+    21d8:	08          	load
+    21d9:	53          	storesp 12
+    21da:	8c          	im 12
+    21db:	16          	addsp 24
+    21dc:	08          	load
+    21dd:	15          	addsp 20
+    21de:	81          	im 1
+    21df:	05          	add
+    21e0:	52          	storesp 8
+    21e1:	8b          	im 11
+    21e2:	3d          	pushspadd
+    21e3:	fd          	im -3
+    21e4:	05          	add
+    21e5:	51          	storesp 4
+    21e6:	fe          	im -2
+    21e7:	f0          	im -16
+    21e8:	39          	poppcrel
+
+000021e9 <clust2sect>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+    21e9:	fb          	im -5
+    21ea:	3d          	pushspadd
+    21eb:	0d          	popsp
+
+000021ec <.LM25>:
+	FATFS *fs = FatFs;
+    21ec:	83          	im 3
+    21ed:	e0          	im -32
+    21ee:	90          	im 16
+    21ef:	08          	load
+
+000021f0 <.LM26>:
+
+
+	clst -= 2;
+    21f0:	fe          	im -2
+    21f1:	19          	addsp 36
+
+000021f2 <.LM27>:
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+    21f2:	88          	im 8
+    21f3:	12          	addsp 8
+    21f4:	08          	load
+    21f5:	fe          	im -2
+    21f6:	05          	add
+    21f7:	55          	storesp 20
+    21f8:	56          	storesp 24
+    21f9:	54          	storesp 16
+    21fa:	80          	im 0
+    21fb:	56          	storesp 24
+    21fc:	74          	loadsp 16
+    21fd:	73          	loadsp 12
+    21fe:	27          	ulessthanorequal
+    21ff:	8d          	im 13
+    2200:	38          	neqbranch
+
+00002201 <.LM28>:
+	return (DWORD)clst * fs->csize + fs->database;
+    2201:	82          	im 2
+    2202:	14          	addsp 16
+    2203:	33          	loadb
+    2204:	75          	loadsp 20
+    2205:	71          	loadsp 4
+    2206:	29          	mult
+    2207:	94          	im 20
+    2208:	16          	addsp 24
+    2209:	08          	load
+    220a:	05          	add
+    220b:	57          	storesp 28
+    220c:	53          	storesp 12
+
+0000220d <.L20>:
+}
+    220d:	75          	loadsp 20
+    220e:	83          	im 3
+    220f:	e0          	im -32
+    2210:	80          	im 0
+    2211:	0c          	store
+    2212:	87          	im 7
+    2213:	3d          	pushspadd
+    2214:	0d          	popsp
+    2215:	04          	poppc
+
+00002216 <dir_rewind>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+    2216:	fc          	im -4
+    2217:	3d          	pushspadd
+    2218:	0d          	popsp
+    2219:	76          	loadsp 24
+
+0000221a <.LM31>:
+	CLUST clst;
+	FATFS *fs = FatFs;
+    221a:	83          	im 3
+    221b:	e0          	im -32
+    221c:	90          	im 16
+    221d:	08          	load
+    221e:	55          	storesp 20
+    221f:	55          	storesp 20
+
+00002220 <.LM32>:
+
+
+	dj->index = 0;
+    2220:	80          	im 0
+    2221:	75          	loadsp 20
+    2222:	23          	storeh
+
+00002223 <.LM33>:
+	clst = dj->sclust;
+    2223:	88          	im 8
+    2224:	15          	addsp 20
+    2225:	08          	load
+    2226:	53          	storesp 12
+
+00002227 <.LM34>:
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+    2227:	72          	loadsp 8
+    2228:	81          	im 1
+    2229:	2e          	eq
+    222a:	88          	im 8
+    222b:	38          	neqbranch
+    222c:	88          	im 8
+    222d:	14          	addsp 16
+    222e:	08          	load
+    222f:	73          	loadsp 12
+    2230:	26          	ulessthan
+    2231:	8b          	im 11
+    2232:	38          	neqbranch
+
+00002233 <.L25>:
+		return FR_DISK_ERR;
+    2233:	81          	im 1
+
+00002234 <.LM36>:
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+    2234:	0b          	nop
+    2235:	83          	im 3
+    2236:	e0          	im -32
+    2237:	80          	im 0
+    2238:	0c          	store
+    2239:	86          	im 6
+    223a:	3d          	pushspadd
+    223b:	0d          	popsp
+    223c:	04          	poppc
+
+0000223d <.L24>:
+    223d:	72          	loadsp 8
+    223e:	90          	im 16
+    223f:	38          	neqbranch
+    2240:	73          	loadsp 12
+    2241:	33          	loadb
+    2242:	52          	storesp 8
+    2243:	71          	loadsp 4
+    2244:	83          	im 3
+    2245:	2e          	eq
+    2246:	09          	not
+    2247:	81          	im 1
+    2248:	06          	and
+    2249:	85          	im 5
+    224a:	38          	neqbranch
+
+0000224b <.LM38>:
+    224b:	90          	im 16
+    224c:	14          	addsp 16
+    224d:	08          	load
+    224e:	53          	storesp 12
+
+0000224f <.L26>:
+    224f:	72          	loadsp 8
+    2250:	8c          	im 12
+    2251:	16          	addsp 24
+    2252:	0c          	store
+
+00002253 <.LM40>:
+    2253:	72          	loadsp 8
+    2254:	80          	im 0
+    2255:	2e          	eq
+    2256:	98          	im 24
+    2257:	38          	neqbranch
+    2258:	72          	loadsp 8
+    2259:	51          	storesp 4
+    225a:	ff          	im -1
+    225b:	8d          	im 13
+    225c:	3f          	callpcrel
+    225d:	83          	im 3
+    225e:	e0          	im -32
+    225f:	80          	im 0
+    2260:	08          	load
+    2261:	90          	im 16
+    2262:	16          	addsp 24
+    2263:	0c          	store
+
+00002264 <.LM41>:
+    2264:	80          	im 0
+    2265:	52          	storesp 8
+
+00002266 <.L30>:
+    2266:	71          	loadsp 4
+    2267:	83          	im 3
+    2268:	e0          	im -32
+    2269:	80          	im 0
+    226a:	0c          	store
+    226b:	86          	im 6
+    226c:	3d          	pushspadd
+    226d:	0d          	popsp
+    226e:	04          	poppc
+
+0000226f <.L27>:
+    226f:	90          	im 16
+    2270:	14          	addsp 16
+    2271:	08          	load
+    2272:	90          	im 16
+    2273:	16          	addsp 24
+    2274:	0c          	store
+
+00002275 <.LM44>:
+    2275:	80          	im 0
+    2276:	52          	storesp 8
+    2277:	ee          	im -18
+    2278:	39          	poppcrel
+
+00002279 <dir_next>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+    2279:	fa          	im -6
+    227a:	3d          	pushspadd
+    227b:	0d          	popsp
+    227c:	78          	loadsp 32
+
+0000227d <.LM46>:
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+    227d:	83          	im 3
+    227e:	e0          	im -32
+    227f:	90          	im 16
+    2280:	08          	load
+
+00002281 <.LM47>:
+
+
+	i = dj->index + 1;
+    2281:	71          	loadsp 4
+    2282:	22          	loadh
+    2283:	81          	im 1
+    2284:	05          	add
+    2285:	70          	loadsp 0
+    2286:	83          	im 3
+    2287:	ff          	im -1
+    2288:	ff          	im -1
+    2289:	06          	and
+    228a:	57          	storesp 28
+    228b:	54          	storesp 16
+    228c:	57          	storesp 28
+    228d:	55          	storesp 20
+
+0000228e <.LM48>:
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+    228e:	73          	loadsp 12
+    228f:	80          	im 0
+    2290:	2e          	eq
+    2291:	b7          	im 55
+    2292:	38          	neqbranch
+    2293:	90          	im 16
+    2294:	15          	addsp 20
+    2295:	08          	load
+    2296:	53          	storesp 12
+    2297:	72          	loadsp 8
+    2298:	80          	im 0
+    2299:	2e          	eq
+    229a:	ae          	im 46
+    229b:	38          	neqbranch
+
+0000229c <.LM49>:
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+    229c:	73          	loadsp 12
+    229d:	8f          	im 15
+    229e:	06          	and
+    229f:	52          	storesp 8
+    22a0:	71          	loadsp 4
+    22a1:	99          	im 25
+    22a2:	38          	neqbranch
+
+000022a3 <.LM50>:
+		dj->sect++;			/* Next sector */
+    22a3:	81          	im 1
+    22a4:	13          	addsp 12
+    22a5:	90          	im 16
+    22a6:	16          	addsp 24
+    22a7:	0c          	store
+
+000022a8 <.LM51>:
+
+		if (dj->clust == 0) {	/* Static table */
+    22a8:	8c          	im 12
+    22a9:	15          	addsp 20
+    22aa:	08          	load
+    22ab:	53          	storesp 12
+    22ac:	72          	loadsp 8
+    22ad:	a5          	im 37
+    22ae:	38          	neqbranch
+
+000022af <.LM52>:
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+    22af:	83          	im 3
+
+000022b0 <.LM53>:
+    22b0:	0b          	nop
+    22b1:	84          	im 4
+    22b2:	17          	addsp 28
+    22b3:	22          	loadh
+    22b4:	57          	storesp 28
+    22b5:	52          	storesp 8
+    22b6:	73          	loadsp 12
+    22b7:	76          	loadsp 24
+    22b8:	27          	ulessthanorequal
+    22b9:	86          	im 6
+    22ba:	38          	neqbranch
+
+000022bb <.L34>:
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+    22bb:	73          	loadsp 12
+    22bc:	75          	loadsp 20
+    22bd:	23          	storeh
+
+000022be <.LM55>:
+
+	return FR_OK;
+    22be:	80          	im 0
+    22bf:	52          	storesp 8
+
+000022c0 <.L31>:
+}
+    22c0:	71          	loadsp 4
+    22c1:	83          	im 3
+    22c2:	e0          	im -32
+    22c3:	80          	im 0
+    22c4:	0c          	store
+    22c5:	88          	im 8
+    22c6:	3d          	pushspadd
+    22c7:	0d          	popsp
+    22c8:	04          	poppc
+
+000022c9 <.L33>:
+    22c9:	83          	im 3
+
+000022ca <.LM58>:
+    22ca:	0b          	nop
+    22cb:	83          	im 3
+    22cc:	e0          	im -32
+    22cd:	80          	im 0
+    22ce:	0c          	store
+    22cf:	88          	im 8
+    22d0:	3d          	pushspadd
+    22d1:	0d          	popsp
+    22d2:	04          	poppc
+
+000022d3 <.L35>:
+    22d3:	82          	im 2
+    22d4:	16          	addsp 24
+    22d5:	33          	loadb
+    22d6:	ff          	im -1
+    22d7:	05          	add
+    22d8:	74          	loadsp 16
+    22d9:	84          	im 4
+    22da:	2a          	lshiftright
+    22db:	06          	and
+    22dc:	52          	storesp 8
+    22dd:	71          	loadsp 4
+    22de:	dc          	im -36
+    22df:	38          	neqbranch
+
+000022e0 <.LM60>:
+    22e0:	72          	loadsp 8
+    22e1:	51          	storesp 4
+    22e2:	fb          	im -5
+    22e3:	b6          	im 54
+    22e4:	3f          	callpcrel
+
+000022e5 <.LM61>:
+    22e5:	81          	im 1
+    22e6:	52          	storesp 8
+    22e7:	71          	loadsp 4
+    22e8:	83          	im 3
+    22e9:	e0          	im -32
+    22ea:	80          	im 0
+    22eb:	08          	load
+    22ec:	27          	ulessthanorequal
+    22ed:	d2          	im -46
+    22ee:	38          	neqbranch
+
+000022ef <.LM62>:
+    22ef:	83          	im 3
+    22f0:	52          	storesp 8
+
+000022f1 <.LM63>:
+    22f1:	83          	im 3
+    22f2:	e0          	im -32
+    22f3:	80          	im 0
+    22f4:	08          	load
+    22f5:	88          	im 8
+    22f6:	17          	addsp 28
+    22f7:	08          	load
+    22f8:	27          	ulessthanorequal
+    22f9:	c6          	im -58
+    22fa:	38          	neqbranch
+
+000022fb <.LM64>:
+    22fb:	83          	im 3
+    22fc:	e0          	im -32
+    22fd:	80          	im 0
+    22fe:	08          	load
+    22ff:	8c          	im 12
+    2300:	16          	addsp 24
+    2301:	0c          	store
+
+00002302 <.LM65>:
+    2302:	83          	im 3
+    2303:	e0          	im -32
+    2304:	80          	im 0
+    2305:	08          	load
+    2306:	51          	storesp 4
+    2307:	fd          	im -3
+    2308:	e0          	im -32
+    2309:	3f          	callpcrel
+    230a:	83          	im 3
+    230b:	e0          	im -32
+    230c:	80          	im 0
+    230d:	08          	load
+    230e:	90          	im 16
+    230f:	16          	addsp 24
+    2310:	0c          	store
+
+00002311 <.LM66>:
+    2311:	73          	loadsp 12
+    2312:	75          	loadsp 20
+    2313:	23          	storeh
+
+00002314 <.LM67>:
+    2314:	80          	im 0
+    2315:	52          	storesp 8
+    2316:	ff          	im -1
+    2317:	a8          	im 40
+    2318:	39          	poppcrel
+
+00002319 <follow_path>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+    2319:	f2          	im -14
+    231a:	3d          	pushspadd
+    231b:	0d          	popsp
+    231c:	60          	loadsp 64
+    231d:	62          	loadsp 72
+
+0000231e <.LM69>:
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+    231e:	64          	loadsp 80
+    231f:	70          	loadsp 0
+    2320:	33          	loadb
+    2321:	58          	storesp 32
+    2322:	58          	storesp 32
+    2323:	5e          	storesp 56
+    2324:	5e          	storesp 56
+    2325:	74          	loadsp 16
+    2326:	a0          	im 32
+    2327:	2e          	eq
+    2328:	09          	not
+    2329:	81          	im 1
+    232a:	06          	and
+    232b:	8e          	im 14
+    232c:	38          	neqbranch
+
+0000232d <.L105>:
+    232d:	81          	im 1
+    232e:	16          	addsp 24
+    232f:	70          	loadsp 0
+    2330:	44          	storesp 80
+    2331:	70          	loadsp 0
+    2332:	33          	loadb
+    2333:	56          	storesp 24
+    2334:	56          	storesp 24
+    2335:	74          	loadsp 16
+    2336:	a0          	im 32
+    2337:	2e          	eq
+    2338:	f4          	im -12
+    2339:	38          	neqbranch
+
+0000233a <.L89>:
+	if (*path == '/') path++;			/* Strip heading separator */
+    233a:	75          	loadsp 20
+    233b:	33          	loadb
+    233c:	55          	storesp 20
+    233d:	74          	loadsp 16
+    233e:	af          	im 47
+    233f:	2e          	eq
+    2340:	82          	im 2
+    2341:	9c          	im 28
+    2342:	38          	neqbranch
+
+00002343 <.LM71>:
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+    2343:	80          	im 0
+    2344:	0b          	nop
+    2345:	88          	im 8
+    2346:	1f          	addsp 60
+    2347:	0c          	store
+
+00002348 <.LM72>:
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+    2348:	75          	loadsp 20
+    2349:	33          	loadb
+    234a:	55          	storesp 20
+    234b:	a0          	im 32
+    234c:	75          	loadsp 20
+    234d:	27          	ulessthanorequal
+    234e:	82          	im 2
+    234f:	a1          	im 33
+    2350:	38          	neqbranch
+
+00002351 <.L47>:
+    2351:	93          	im 19
+    2352:	3d          	pushspadd
+    2353:	84          	im 4
+    2354:	1f          	addsp 60
+    2355:	08          	load
+
+00002356 <.LBB2>:
+    2356:	70          	loadsp 0
+    2357:	58          	storesp 32
+    2358:	5c          	storesp 48
+    2359:	5f          	storesp 60
+
+0000235a <.LM74>:
+    235a:	8a          	im 10
+    235b:	55          	storesp 20
+
+0000235c <.L53>:
+    235c:	a0          	im 32
+    235d:	76          	loadsp 24
+    235e:	70          	loadsp 0
+    235f:	81          	im 1
+    2360:	05          	add
+    2361:	58          	storesp 32
+    2362:	34          	storeb
+    2363:	ff          	im -1
+    2364:	15          	addsp 20
+    2365:	55          	storesp 20
+    2366:	74          	loadsp 16
+    2367:	ff          	im -1
+    2368:	2e          	eq
+    2369:	09          	not
+    236a:	81          	im 1
+    236b:	06          	and
+    236c:	ef          	im -17
+    236d:	38          	neqbranch
+
+0000236e <.LBE4>:
+    236e:	80          	im 0
+    236f:	70          	loadsp 0
+    2370:	59          	storesp 36
+    2371:	59          	storesp 36
+    2372:	88          	im 8
+
+00002373 <.LM76>:
+    2373:	7f          	loadsp 60
+    2374:	08          	load
+    2375:	5d          	storesp 52
+    2376:	5a          	storesp 40
+
+00002377 <.L103>:
+    2377:	78          	loadsp 32
+    2378:	81          	im 1
+    2379:	1a          	addsp 40
+    237a:	70          	loadsp 0
+    237b:	81          	im 1
+    237c:	ff          	im -1
+    237d:	06          	and
+    237e:	7e          	loadsp 56
+    237f:	13          	addsp 12
+    2380:	70          	loadsp 0
+    2381:	33          	loadb
+
+00002382 <.LM78>:
+    2382:	70          	loadsp 0
+    2383:	af          	im 47
+    2384:	32          	xor
+    2385:	70          	loadsp 0
+    2386:	30          	neg
+    2387:	a0          	im 32
+    2388:	73          	loadsp 12
+    2389:	27          	ulessthanorequal
+    238a:	71          	loadsp 4
+    238b:	80          	im 0
+    238c:	25          	lessthanorequal
+    238d:	07          	or
+    238e:	51          	storesp 4
+    238f:	51          	storesp 4
+    2390:	52          	storesp 8
+    2391:	5b          	storesp 44
+    2392:	53          	storesp 12
+    2393:	5b          	storesp 44
+    2394:	57          	storesp 28
+    2395:	55          	storesp 20
+    2396:	74          	loadsp 16
+    2397:	80          	im 0
+    2398:	d3          	im -45
+    2399:	38          	neqbranch
+
+0000239a <.L109>:
+    239a:	76          	loadsp 24
+    239b:	ae          	im 46
+    239c:	2e          	eq
+    239d:	81          	im 1
+    239e:	e8          	im -24
+    239f:	38          	neqbranch
+    23a0:	77          	loadsp 28
+    23a1:	7a          	loadsp 40
+    23a2:	27          	ulessthanorequal
+    23a3:	75          	loadsp 20
+    23a4:	07          	or
+    23a5:	55          	storesp 20
+    23a6:	74          	loadsp 16
+    23a7:	80          	im 0
+    23a8:	2e          	eq
+    23a9:	81          	im 1
+    23aa:	e8          	im -24
+    23ab:	38          	neqbranch
+
+000023ac <.L111>:
+    23ac:	79          	loadsp 36
+    23ad:	88          	im 8
+    23ae:	32          	xor
+    23af:	70          	loadsp 0
+    23b0:	30          	neg
+    23b1:	78          	loadsp 32
+    23b2:	ae          	im 46
+    23b3:	32          	xor
+    23b4:	70          	loadsp 0
+    23b5:	30          	neg
+    23b6:	70          	loadsp 0
+    23b7:	73          	loadsp 12
+    23b8:	07          	or
+    23b9:	9f          	im 31
+    23ba:	2a          	lshiftright
+    23bb:	53          	storesp 12
+    23bc:	51          	storesp 4
+    23bd:	57          	storesp 28
+    23be:	51          	storesp 4
+    23bf:	56          	storesp 24
+    23c0:	75          	loadsp 20
+    23c1:	aa          	im 42
+    23c2:	38          	neqbranch
+
+000023c3 <.LM81>:
+    23c3:	88          	im 8
+    23c4:	58          	storesp 32
+    23c5:	8b          	im 11
+
+000023c6 <.LM82>:
+    23c6:	79          	loadsp 36
+    23c7:	81          	im 1
+    23c8:	1b          	addsp 44
+    23c9:	70          	loadsp 0
+    23ca:	81          	im 1
+    23cb:	ff          	im -1
+    23cc:	06          	and
+    23cd:	7f          	loadsp 60
+    23ce:	13          	addsp 12
+    23cf:	70          	loadsp 0
+    23d0:	33          	loadb
+
+000023d1 <.LM83>:
+    23d1:	70          	loadsp 0
+    23d2:	af          	im 47
+    23d3:	32          	xor
+    23d4:	70          	loadsp 0
+    23d5:	30          	neg
+    23d6:	a0          	im 32
+    23d7:	73          	loadsp 12
+    23d8:	27          	ulessthanorequal
+    23d9:	71          	loadsp 4
+    23da:	80          	im 0
+    23db:	25          	lessthanorequal
+    23dc:	07          	or
+    23dd:	51          	storesp 4
+    23de:	51          	storesp 4
+    23df:	52          	storesp 8
+    23e0:	5c          	storesp 48
+    23e1:	53          	storesp 12
+    23e2:	5c          	storesp 48
+    23e3:	58          	storesp 32
+    23e4:	56          	storesp 24
+    23e5:	5a          	storesp 40
+    23e6:	74          	loadsp 16
+    23e7:	80          	im 0
+    23e8:	2e          	eq
+    23e9:	ff          	im -1
+    23ea:	af          	im 47
+    23eb:	38          	neqbranch
+
+000023ec <.L56>:
+    23ec:	7b          	loadsp 44
+    23ed:	19          	addsp 36
+    23ee:	7f          	loadsp 60
+    23ef:	0c          	store
+
+000023f0 <.LM85>:
+    23f0:	80          	im 0
+    23f1:	55          	storesp 20
+    23f2:	76          	loadsp 24
+    23f3:	a0          	im 32
+    23f4:	26          	ulessthan
+    23f5:	83          	im 3
+    23f6:	38          	neqbranch
+    23f7:	81          	im 1
+    23f8:	55          	storesp 20
+
+000023f9 <.L69>:
+    23f9:	74          	loadsp 16
+    23fa:	8b          	im 11
+    23fb:	1c          	addsp 48
+    23fc:	34          	storeb
+
+000023fd <.LBB6>:
+    23fd:	7d          	loadsp 52
+    23fe:	51          	storesp 4
+    23ff:	fc          	im -4
+    2400:	95          	im 21
+    2401:	3f          	callpcrel
+    2402:	83          	im 3
+    2403:	e0          	im -32
+    2404:	80          	im 0
+    2405:	08          	load
+    2406:	5a          	storesp 40
+
+00002407 <.LM87>:
+    2407:	83          	im 3
+    2408:	e0          	im -32
+    2409:	80          	im 0
+    240a:	08          	load
+    240b:	80          	im 0
+    240c:	2e          	eq
+    240d:	81          	im 1
+    240e:	d9          	im -39
+    240f:	38          	neqbranch
+
+00002410 <.L73>:
+    2410:	79          	loadsp 36
+    2411:	56          	storesp 24
+
+00002412 <.LM89>:
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+    2412:	79          	loadsp 36
+    2413:	82          	im 2
+    2414:	b0          	im 48
+    2415:	38          	neqbranch
+
+00002416 <.L84>:
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+    2416:	84          	im 4
+    2417:	1e          	addsp 56
+    2418:	08          	load
+    2419:	8b          	im 11
+    241a:	11          	addsp 4
+    241b:	33          	loadb
+    241c:	56          	storesp 24
+    241d:	5b          	storesp 44
+    241e:	74          	loadsp 16
+    241f:	80          	im 0
+    2420:	dd          	im -35
+    2421:	38          	neqbranch
+
+00002422 <.LM91>:
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+    2422:	8b          	im 11
+    2423:	1d          	addsp 52
+    2424:	33          	loadb
+    2425:	70          	loadsp 0
+    2426:	84          	im 4
+    2427:	2a          	lshiftright
+    2428:	70          	loadsp 0
+    2429:	81          	im 1
+    242a:	06          	and
+    242b:	51          	storesp 4
+    242c:	56          	storesp 24
+    242d:	57          	storesp 28
+    242e:	74          	loadsp 16
+    242f:	80          	im 0
+    2430:	2e          	eq
+    2431:	82          	im 2
+    2432:	a7          	im 39
+    2433:	38          	neqbranch
+
+00002434 <.LM92>:
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+    2434:	95          	im 21
+    2435:	1d          	addsp 52
+    2436:	33          	loadb
+    2437:	94          	im 20
+    2438:	1e          	addsp 56
+    2439:	33          	loadb
+    243a:	71          	loadsp 4
+    243b:	98          	im 24
+    243c:	2b          	ashiftleft
+    243d:	71          	loadsp 4
+    243e:	90          	im 16
+    243f:	2b          	ashiftleft
+    2440:	07          	or
+    2441:	7f          	loadsp 60
+    2442:	9b          	im 27
+    2443:	05          	add
+    2444:	33          	loadb
+    2445:	60          	loadsp 64
+    2446:	9a          	im 26
+    2447:	05          	add
+    2448:	33          	loadb
+    2449:	71          	loadsp 4
+    244a:	88          	im 8
+    244b:	2b          	ashiftleft
+    244c:	07          	or
+    244d:	72          	loadsp 8
+    244e:	07          	or
+    244f:	62          	loadsp 72
+    2450:	88          	im 8
+    2451:	05          	add
+    2452:	0c          	store
+
+00002453 <.LM93>:
+    2453:	7e          	loadsp 56
+    2454:	52          	storesp 8
+    2455:	5a          	storesp 40
+    2456:	58          	storesp 32
+    2457:	56          	storesp 24
+    2458:	58          	storesp 32
+
+00002459 <.LM94>:
+    2459:	8a          	im 10
+    245a:	55          	storesp 20
+    245b:	fd          	im -3
+    245c:	ff          	im -1
+    245d:	39          	poppcrel
+
+0000245e <.L106>:
+    245e:	81          	im 1
+    245f:	16          	addsp 24
+    2460:	70          	loadsp 0
+    2461:	44          	storesp 80
+    2462:	56          	storesp 24
+
+00002463 <.LM96>:
+    2463:	80          	im 0
+    2464:	0b          	nop
+    2465:	88          	im 8
+    2466:	1f          	addsp 60
+    2467:	0c          	store
+
+00002468 <.LM97>:
+    2468:	75          	loadsp 20
+    2469:	33          	loadb
+    246a:	55          	storesp 20
+    246b:	74          	loadsp 16
+    246c:	a0          	im 32
+    246d:	26          	ulessthan
+    246e:	fd          	im -3
+    246f:	e1          	im -31
+    2470:	38          	neqbranch
+
+00002471 <.L107>:
+    2471:	7d          	loadsp 52
+    2472:	51          	storesp 4
+    2473:	fb          	im -5
+    2474:	a1          	im 33
+    2475:	3f          	callpcrel
+    2476:	83          	im 3
+    2477:	e0          	im -32
+    2478:	80          	im 0
+    2479:	08          	load
+    247a:	56          	storesp 24
+
+0000247b <.LM99>:
+    247b:	80          	im 0
+    247c:	7d          	loadsp 52
+    247d:	34          	storeb
+
+0000247e <.L48>:
+		}
+	}
+
+	return res;
+}
+    247e:	75          	loadsp 20
+    247f:	83          	im 3
+    2480:	e0          	im -32
+    2481:	80          	im 0
+    2482:	0c          	store
+    2483:	90          	im 16
+    2484:	3d          	pushspadd
+    2485:	0d          	popsp
+    2486:	04          	poppc
+
+00002487 <.L108>:
+    2487:	81          	im 1
+    2488:	70          	loadsp 0
+    2489:	79          	loadsp 36
+    248a:	7c          	loadsp 48
+    248b:	27          	ulessthanorequal
+    248c:	07          	or
+    248d:	51          	storesp 4
+    248e:	55          	storesp 20
+    248f:	74          	loadsp 16
+    2490:	fe          	im -2
+    2491:	9a          	im 26
+    2492:	38          	neqbranch
+
+00002493 <.L66>:
+    2493:	ff          	im -1
+    2494:	9f          	im 31
+    2495:	17          	addsp 28
+    2496:	55          	storesp 20
+    2497:	74          	loadsp 16
+    2498:	99          	im 25
+    2499:	26          	ulessthan
+    249a:	89          	im 9
+    249b:	38          	neqbranch
+    249c:	e0          	im -32
+    249d:	17          	addsp 28
+    249e:	70          	loadsp 0
+    249f:	81          	im 1
+    24a0:	ff          	im -1
+    24a1:	06          	and
+    24a2:	58          	storesp 32
+    24a3:	55          	storesp 20
+
+000024a4 <.L68>:
+    24a4:	77          	loadsp 28
+    24a5:	81          	im 1
+    24a6:	19          	addsp 36
+    24a7:	70          	loadsp 0
+    24a8:	81          	im 1
+    24a9:	ff          	im -1
+    24aa:	06          	and
+    24ab:	7d          	loadsp 52
+    24ac:	13          	addsp 12
+    24ad:	53          	storesp 12
+    24ae:	5a          	storesp 40
+    24af:	57          	storesp 28
+    24b0:	55          	storesp 20
+    24b1:	76          	loadsp 24
+    24b2:	75          	loadsp 20
+    24b3:	34          	storeb
+    24b4:	fd          	im -3
+    24b5:	c1          	im -63
+    24b6:	39          	poppcrel
+
+000024b7 <.L81>:
+    24b7:	ff          	im -1
+    24b8:	17          	addsp 28
+    24b9:	57          	storesp 28
+    24ba:	76          	loadsp 24
+    24bb:	ff          	im -1
+    24bc:	2e          	eq
+    24bd:	80          	im 0
+    24be:	fd          	im -3
+    24bf:	38          	neqbranch
+
+000024c0 <.L112>:
+    24c0:	78          	loadsp 32
+    24c1:	70          	loadsp 0
+    24c2:	81          	im 1
+    24c3:	05          	add
+    24c4:	5a          	storesp 40
+    24c5:	33          	loadb
+    24c6:	78          	loadsp 32
+    24c7:	70          	loadsp 0
+    24c8:	81          	im 1
+    24c9:	05          	add
+    24ca:	5a          	storesp 40
+    24cb:	33          	loadb
+    24cc:	71          	loadsp 4
+    24cd:	71          	loadsp 4
+    24ce:	31          	sub
+    24cf:	52          	storesp 8
+    24d0:	56          	storesp 24
+    24d1:	56          	storesp 24
+    24d2:	75          	loadsp 20
+    24d3:	80          	im 0
+    24d4:	2e          	eq
+    24d5:	e1          	im -31
+    24d6:	38          	neqbranch
+
+000024d7 <.L80>:
+    24d7:	7d          	loadsp 52
+    24d8:	51          	storesp 4
+    24d9:	fb          	im -5
+    24da:	9e          	im 30
+    24db:	3f          	callpcrel
+    24dc:	83          	im 3
+    24dd:	e0          	im -32
+    24de:	80          	im 0
+    24df:	08          	load
+    24e0:	5a          	storesp 40
+
+000024e1 <.LM106>:
+    24e1:	83          	im 3
+    24e2:	e0          	im -32
+    24e3:	80          	im 0
+    24e4:	08          	load
+    24e5:	fe          	im -2
+    24e6:	a9          	im 41
+    24e7:	38          	neqbranch
+
+000024e8 <.L74>:
+    24e8:	a0          	im 32
+    24e9:	54          	storesp 16
+    24ea:	7d          	loadsp 52
+    24eb:	22          	loadh
+    24ec:	70          	loadsp 0
+    24ed:	85          	im 5
+    24ee:	2b          	ashiftleft
+    24ef:	83          	im 3
+    24f0:	e0          	im -32
+    24f1:	06          	and
+    24f2:	54          	storesp 16
+    24f3:	55          	storesp 20
+    24f4:	90          	im 16
+    24f5:	1e          	addsp 56
+    24f6:	08          	load
+    24f7:	52          	storesp 8
+    24f8:	7c          	loadsp 48
+    24f9:	51          	storesp 4
+    24fa:	e8          	im -24
+    24fb:	83          	im 3
+    24fc:	3f          	callpcrel
+    24fd:	83          	im 3
+    24fe:	e0          	im -32
+    24ff:	80          	im 0
+    2500:	08          	load
+    2501:	5a          	storesp 40
+    2502:	83          	im 3
+    2503:	e0          	im -32
+    2504:	80          	im 0
+    2505:	08          	load
+    2506:	80          	im 0
+    2507:	dc          	im -36
+    2508:	38          	neqbranch
+
+00002509 <.LM108>:
+    2509:	7c          	loadsp 48
+    250a:	33          	loadb
+    250b:	55          	storesp 20
+
+0000250c <.LM109>:
+    250c:	74          	loadsp 16
+    250d:	80          	im 0
+    250e:	2e          	eq
+    250f:	80          	im 0
+    2510:	dd          	im -35
+    2511:	38          	neqbranch
+
+00002512 <.LM110>:
+    2512:	8b          	im 11
+    2513:	1d          	addsp 52
+    2514:	33          	loadb
+    2515:	70          	loadsp 0
+    2516:	83          	im 3
+    2517:	2a          	lshiftright
+    2518:	70          	loadsp 0
+    2519:	81          	im 1
+    251a:	06          	and
+    251b:	51          	storesp 4
+    251c:	56          	storesp 24
+    251d:	56          	storesp 24
+    251e:	74          	loadsp 16
+    251f:	ff          	im -1
+    2520:	b6          	im 54
+    2521:	38          	neqbranch
+
+00002522 <.LM111>:
+    2522:	8b          	im 11
+
+00002523 <.LM112>:
+    2523:	7d          	loadsp 52
+    2524:	7f          	loadsp 60
+    2525:	84          	im 4
+    2526:	05          	add
+    2527:	08          	load
+
+00002528 <.LM113>:
+    2528:	83          	im 3
+    2529:	e0          	im -32
+    252a:	80          	im 0
+    252b:	08          	load
+
+0000252c <.LM114>:
+    252c:	ff          	im -1
+    252d:	14          	addsp 16
+    252e:	54          	storesp 16
+    252f:	59          	storesp 36
+    2530:	5a          	storesp 40
+    2531:	5a          	storesp 40
+    2532:	57          	storesp 28
+    2533:	76          	loadsp 24
+    2534:	ff          	im -1
+    2535:	2e          	eq
+    2536:	09          	not
+    2537:	81          	im 1
+    2538:	06          	and
+    2539:	ff          	im -1
+    253a:	85          	im 5
+    253b:	38          	neqbranch
+
+0000253c <.L82>:
+    253c:	75          	loadsp 20
+    253d:	ff          	im -1
+    253e:	98          	im 24
+    253f:	38          	neqbranch
+    2540:	79          	loadsp 36
+    2541:	56          	storesp 24
+    2542:	fd          	im -3
+    2543:	d2          	im -46
+    2544:	39          	poppcrel
+
+00002545 <.L110>:
+    2545:	79          	loadsp 36
+    2546:	83          	im 3
+    2547:	2e          	eq
+    2548:	09          	not
+    2549:	81          	im 1
+    254a:	06          	and
+    254b:	fe          	im -2
+    254c:	b1          	im 49
+    254d:	38          	neqbranch
+    254e:	84          	im 4
+    254f:	1e          	addsp 56
+    2550:	08          	load
+    2551:	8b          	im 11
+    2552:	11          	addsp 4
+    2553:	33          	loadb
+    2554:	51          	storesp 4
+    2555:	55          	storesp 20
+    2556:	74          	loadsp 16
+    2557:	fe          	im -2
+    2558:	a5          	im 37
+    2559:	38          	neqbranch
+
+0000255a <.L102>:
+    255a:	84          	im 4
+
+0000255b <.LM118>:
+    255b:	0b          	nop
+    255c:	83          	im 3
+    255d:	e0          	im -32
+    255e:	80          	im 0
+    255f:	0c          	store
+    2560:	90          	im 16
+    2561:	3d          	pushspadd
+    2562:	0d          	popsp
+    2563:	04          	poppc
+
+00002564 <.L92>:
+    2564:	81          	im 1
+
+00002565 <.LM120>:
+    2565:	0b          	nop
+    2566:	83          	im 3
+    2567:	e0          	im -32
+    2568:	80          	im 0
+    2569:	0c          	store
+    256a:	90          	im 16
+    256b:	3d          	pushspadd
+    256c:	0d          	popsp
+    256d:	04          	poppc
+
+0000256e <.L93>:
+    256e:	83          	im 3
+
+0000256f <.LM122>:
+    256f:	0b          	nop
+    2570:	84          	im 4
+    2571:	1f          	addsp 60
+    2572:	08          	load
+    2573:	8b          	im 11
+    2574:	11          	addsp 4
+    2575:	33          	loadb
+    2576:	51          	storesp 4
+    2577:	56          	storesp 24
+    2578:	56          	storesp 24
+    2579:	74          	loadsp 16
+    257a:	fe          	im -2
+    257b:	82          	im 2
+    257c:	38          	neqbranch
+    257d:	dc          	im -36
+    257e:	39          	poppcrel
+
+0000257f <check_fs>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+    257f:	f8          	im -8
+    2580:	3d          	pushspadd
+    2581:	0d          	popsp
+    2582:	7a          	loadsp 40
+    2583:	7c          	loadsp 48
+    2584:	59          	storesp 36
+    2585:	57          	storesp 28
+
+00002586 <.LM124>:
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+    2586:	82          	im 2
+    2587:	54          	storesp 16
+    2588:	83          	im 3
+    2589:	fe          	im -2
+    258a:	53          	storesp 12
+    258b:	77          	loadsp 28
+    258c:	52          	storesp 8
+    258d:	76          	loadsp 24
+    258e:	51          	storesp 4
+    258f:	e6          	im -26
+    2590:	ee          	im -18
+    2591:	3f          	callpcrel
+
+00002592 <.LM125>:
+		return 3;
+    2592:	83          	im 3
+    2593:	56          	storesp 24
+
+00002594 <.LM126>:
+    2594:	83          	im 3
+    2595:	e0          	im -32
+    2596:	80          	im 0
+    2597:	08          	load
+    2598:	80          	im 0
+    2599:	ec          	im -20
+    259a:	38          	neqbranch
+
+0000259b <.LM127>:
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+    259b:	81          	im 1
+    259c:	17          	addsp 28
+    259d:	33          	loadb
+    259e:	77          	loadsp 28
+    259f:	33          	loadb
+    25a0:	71          	loadsp 4
+    25a1:	88          	im 8
+    25a2:	2b          	ashiftleft
+    25a3:	07          	or
+    25a4:	56          	storesp 24
+    25a5:	56          	storesp 24
+
+000025a6 <.LM128>:
+		return 2;
+    25a6:	82          	im 2
+    25a7:	56          	storesp 24
+
+000025a8 <.LM129>:
+    25a8:	74          	loadsp 16
+    25a9:	82          	im 2
+    25aa:	d4          	im -44
+    25ab:	d5          	im -43
+    25ac:	2e          	eq
+    25ad:	09          	not
+    25ae:	81          	im 1
+    25af:	06          	and
+    25b0:	80          	im 0
+    25b1:	d4          	im -44
+    25b2:	38          	neqbranch
+
+000025b3 <.LM130>:
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+    25b3:	75          	loadsp 20
+    25b4:	54          	storesp 16
+    25b5:	b6          	im 54
+    25b6:	53          	storesp 12
+    25b7:	77          	loadsp 28
+    25b8:	52          	storesp 8
+    25b9:	76          	loadsp 24
+    25ba:	51          	storesp 4
+    25bb:	e6          	im -26
+    25bc:	c2          	im -62
+    25bd:	3f          	callpcrel
+    25be:	83          	im 3
+    25bf:	e0          	im -32
+    25c0:	80          	im 0
+    25c1:	08          	load
+    25c2:	98          	im 24
+    25c3:	38          	neqbranch
+    25c4:	81          	im 1
+    25c5:	17          	addsp 28
+    25c6:	33          	loadb
+    25c7:	77          	loadsp 28
+    25c8:	33          	loadb
+    25c9:	71          	loadsp 4
+    25ca:	88          	im 8
+    25cb:	2b          	ashiftleft
+    25cc:	07          	or
+
+000025cd <.LM131>:
+		return 0;
+    25cd:	83          	im 3
+    25ce:	e0          	im -32
+    25cf:	80          	im 0
+    25d0:	08          	load
+    25d1:	52          	storesp 8
+    25d2:	56          	storesp 24
+    25d3:	56          	storesp 24
+
+000025d4 <.LM132>:
+    25d4:	74          	loadsp 16
+    25d5:	81          	im 1
+    25d6:	82          	im 2
+    25d7:	c6          	im -58
+    25d8:	2e          	eq
+    25d9:	ac          	im 44
+    25da:	38          	neqbranch
+
+000025db <.L116>:
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+    25db:	82          	im 2
+    25dc:	54          	storesp 16
+    25dd:	80          	im 0
+    25de:	d2          	im -46
+    25df:	53          	storesp 12
+    25e0:	77          	loadsp 28
+    25e1:	52          	storesp 8
+    25e2:	76          	loadsp 24
+    25e3:	51          	storesp 4
+    25e4:	e6          	im -26
+    25e5:	99          	im 25
+    25e6:	3f          	callpcrel
+    25e7:	83          	im 3
+    25e8:	e0          	im -32
+    25e9:	80          	im 0
+    25ea:	08          	load
+    25eb:	98          	im 24
+    25ec:	38          	neqbranch
+    25ed:	81          	im 1
+    25ee:	17          	addsp 28
+    25ef:	33          	loadb
+    25f0:	77          	loadsp 28
+    25f1:	33          	loadb
+    25f2:	71          	loadsp 4
+    25f3:	88          	im 8
+    25f4:	2b          	ashiftleft
+    25f5:	07          	or
+
+000025f6 <.LM134>:
+		return 0;
+    25f6:	83          	im 3
+    25f7:	e0          	im -32
+    25f8:	80          	im 0
+    25f9:	08          	load
+    25fa:	52          	storesp 8
+    25fb:	56          	storesp 24
+    25fc:	56          	storesp 24
+
+000025fd <.LM135>:
+    25fd:	74          	loadsp 16
+    25fe:	81          	im 1
+    25ff:	82          	im 2
+    2600:	c6          	im -58
+    2601:	2e          	eq
+    2602:	83          	im 3
+    2603:	38          	neqbranch
+
+00002604 <.L117>:
+	return 1;
+    2604:	81          	im 1
+    2605:	56          	storesp 24
+
+00002606 <.L113>:
+}
+    2606:	75          	loadsp 20
+    2607:	83          	im 3
+    2608:	e0          	im -32
+    2609:	80          	im 0
+    260a:	0c          	store
+    260b:	8a          	im 10
+    260c:	3d          	pushspadd
+    260d:	0d          	popsp
+    260e:	04          	poppc
+
+0000260f <pf_mount>:
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+    260f:	ec          	im -20
+    2610:	3d          	pushspadd
+    2611:	0d          	popsp
+    2612:	66          	loadsp 88
+    2613:	58          	storesp 32
+
+00002614 <.LM139>:
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+    2614:	80          	im 0
+    2615:	0b          	nop
+    2616:	83          	im 3
+    2617:	e0          	im -32
+    2618:	90          	im 16
+    2619:	0c          	store
+
+0000261a <.LM140>:
+	if (!fs) return FR_OK;				/* Unregister fs object */
+    261a:	77          	loadsp 28
+    261b:	56          	storesp 24
+    261c:	77          	loadsp 28
+    261d:	80          	im 0
+    261e:	2e          	eq
+    261f:	82          	im 2
+    2620:	d3          	im -45
+    2621:	38          	neqbranch
+
+00002622 <.LM141>:
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+    2622:	c1          	im -63
+    2623:	8c          	im 12
+    2624:	3f          	callpcrel
+    2625:	83          	im 3
+    2626:	e0          	im -32
+    2627:	80          	im 0
+    2628:	08          	load
+    2629:	81          	im 1
+    262a:	06          	and
+    262b:	55          	storesp 20
+
+0000262c <.LM142>:
+		return FR_NOT_READY;
+    262c:	82          	im 2
+    262d:	56          	storesp 24
+
+0000262e <.LM143>:
+    262e:	74          	loadsp 16
+    262f:	82          	im 2
+    2630:	c3          	im -61
+    2631:	38          	neqbranch
+
+00002632 <.LM144>:
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+    2632:	74          	loadsp 16
+
+00002633 <.LM145>:
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+    2633:	75          	loadsp 20
+    2634:	53          	storesp 12
+    2635:	8e          	im 14
+    2636:	3d          	pushspadd
+    2637:	70          	loadsp 0
+    2638:	53          	storesp 12
+    2639:	58          	storesp 32
+    263a:	59          	storesp 36
+    263b:	fe          	im -2
+    263c:	c2          	im -62
+    263d:	3f          	callpcrel
+    263e:	83          	im 3
+    263f:	e0          	im -32
+    2640:	80          	im 0
+    2641:	08          	load
+    2642:	81          	im 1
+    2643:	ff          	im -1
+    2644:	06          	and
+    2645:	56          	storesp 24
+
+00002646 <.LM146>:
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+    2646:	75          	loadsp 20
+    2647:	81          	im 1
+    2648:	2e          	eq
+    2649:	82          	im 2
+    264a:	b2          	im 50
+    264b:	38          	neqbranch
+
+0000264c <.LM147>:
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+    264c:	75          	loadsp 20
+    264d:	83          	im 3
+    264e:	2e          	eq
+    264f:	83          	im 3
+    2650:	88          	im 8
+    2651:	38          	neqbranch
+
+00002652 <.L126>:
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+    2652:	75          	loadsp 20
+    2653:	83          	im 3
+    2654:	8e          	im 14
+    2655:	38          	neqbranch
+
+00002656 <.LM149>:
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+    2656:	a4          	im 36
+    2657:	54          	storesp 16
+    2658:	8d          	im 13
+    2659:	53          	storesp 12
+    265a:	78          	loadsp 32
+    265b:	52          	storesp 8
+    265c:	76          	loadsp 24
+    265d:	51          	storesp 4
+    265e:	e5          	im -27
+    265f:	9f          	im 31
+    2660:	3f          	callpcrel
+    2661:	81          	im 1
+    2662:	56          	storesp 24
+    2663:	83          	im 3
+    2664:	e0          	im -32
+    2665:	80          	im 0
+    2666:	08          	load
+    2667:	82          	im 2
+    2668:	8b          	im 11
+    2669:	38          	neqbranch
+
+0000266a <.LM150>:
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+    266a:	02          	pushsp
+    266b:	ba          	im 58
+    266c:	05          	add
+    266d:	33          	loadb
+    266e:	02          	pushsp
+    266f:	84          	im 4
+    2670:	05          	add
+    2671:	b9          	im 57
+    2672:	05          	add
+    2673:	33          	loadb
+    2674:	71          	loadsp 4
+    2675:	88          	im 8
+    2676:	2b          	ashiftleft
+    2677:	07          	or
+    2678:	58          	storesp 32
+    2679:	5c          	storesp 48
+
+0000267a <.LM151>:
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+    267a:	76          	loadsp 24
+    267b:	ab          	im 43
+    267c:	38          	neqbranch
+    267d:	02          	pushsp
+    267e:	80          	im 0
+    267f:	ca          	im -54
+    2680:	05          	add
+    2681:	33          	loadb
+    2682:	02          	pushsp
+    2683:	84          	im 4
+    2684:	05          	add
+    2685:	80          	im 0
+    2686:	c9          	im -55
+    2687:	05          	add
+    2688:	33          	loadb
+    2689:	71          	loadsp 4
+    268a:	98          	im 24
+    268b:	2b          	ashiftleft
+    268c:	71          	loadsp 4
+    268d:	90          	im 16
+    268e:	2b          	ashiftleft
+    268f:	07          	or
+    2690:	96          	im 22
+    2691:	3d          	pushspadd
+    2692:	33          	loadb
+    2693:	70          	loadsp 0
+    2694:	88          	im 8
+    2695:	2b          	ashiftleft
+    2696:	72          	loadsp 8
+    2697:	07          	or
+    2698:	02          	pushsp
+    2699:	94          	im 20
+    269a:	05          	add
+    269b:	80          	im 0
+    269c:	c7          	im -57
+    269d:	05          	add
+    269e:	33          	loadb
+    269f:	71          	loadsp 4
+    26a0:	07          	or
+    26a1:	54          	storesp 16
+    26a2:	52          	storesp 8
+    26a3:	5d          	storesp 52
+    26a4:	57          	storesp 28
+    26a5:	58          	storesp 32
+    26a6:	56          	storesp 24
+
+000026a7 <.L129>:
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+    26a7:	02          	pushsp
+    26a8:	b3          	im 51
+    26a9:	05          	add
+    26aa:	33          	loadb
+    26ab:	77          	loadsp 28
+    26ac:	71          	loadsp 4
+    26ad:	29          	mult
+
+000026ae <.LM153>:
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+    26ae:	02          	pushsp
+    26af:	88          	im 8
+    26b0:	05          	add
+    26b1:	b2          	im 50
+    26b2:	05          	add
+    26b3:	33          	loadb
+    26b4:	02          	pushsp
+    26b5:	8c          	im 12
+    26b6:	05          	add
+    26b7:	b1          	im 49
+    26b8:	05          	add
+    26b9:	33          	loadb
+    26ba:	71          	loadsp 4
+    26bb:	88          	im 8
+    26bc:	2b          	ashiftleft
+    26bd:	07          	or
+    26be:	7c          	loadsp 48
+    26bf:	11          	addsp 4
+    26c0:	70          	loadsp 0
+    26c1:	8c          	im 12
+    26c2:	1e          	addsp 56
+    26c3:	0c          	store
+    26c4:	5e          	storesp 56
+    26c5:	59          	storesp 36
+    26c6:	57          	storesp 28
+    26c7:	58          	storesp 32
+    26c8:	5c          	storesp 48
+
+000026c9 <.LM154>:
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+    26c9:	8d          	im 13
+    26ca:	3d          	pushspadd
+    26cb:	33          	loadb
+    26cc:	82          	im 2
+    26cd:	19          	addsp 36
+    26ce:	34          	storeb
+
+000026cf <.LM155>:
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+    26cf:	02          	pushsp
+    26d0:	b5          	im 53
+    26d1:	05          	add
+    26d2:	33          	loadb
+    26d3:	8f          	im 15
+    26d4:	3d          	pushspadd
+    26d5:	33          	loadb
+    26d6:	71          	loadsp 4
+    26d7:	88          	im 8
+    26d8:	2b          	ashiftleft
+    26d9:	07          	or
+    26da:	5a          	storesp 40
+    26db:	5b          	storesp 44
+    26dc:	78          	loadsp 32
+    26dd:	84          	im 4
+    26de:	19          	addsp 36
+    26df:	23          	storeh
+
+000026e0 <.LM156>:
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+    26e0:	02          	pushsp
+    26e1:	b7          	im 55
+    26e2:	05          	add
+    26e3:	33          	loadb
+    26e4:	02          	pushsp
+    26e5:	84          	im 4
+    26e6:	05          	add
+    26e7:	b6          	im 54
+    26e8:	05          	add
+    26e9:	33          	loadb
+    26ea:	71          	loadsp 4
+    26eb:	88          	im 8
+    26ec:	2b          	ashiftleft
+    26ed:	07          	or
+    26ee:	56          	storesp 24
+    26ef:	5b          	storesp 44
+
+000026f0 <.LM157>:
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+    26f0:	74          	loadsp 16
+    26f1:	ab          	im 43
+    26f2:	38          	neqbranch
+    26f3:	02          	pushsp
+    26f4:	80          	im 0
+    26f5:	c6          	im -58
+    26f6:	05          	add
+    26f7:	33          	loadb
+    26f8:	02          	pushsp
+    26f9:	84          	im 4
+    26fa:	05          	add
+    26fb:	80          	im 0
+    26fc:	c5          	im -59
+    26fd:	05          	add
+    26fe:	33          	loadb
+    26ff:	71          	loadsp 4
+    2700:	98          	im 24
+    2701:	2b          	ashiftleft
+    2702:	71          	loadsp 4
+    2703:	90          	im 16
+    2704:	2b          	ashiftleft
+    2705:	07          	or
+    2706:	95          	im 21
+    2707:	3d          	pushspadd
+    2708:	33          	loadb
+    2709:	70          	loadsp 0
+    270a:	88          	im 8
+    270b:	2b          	ashiftleft
+    270c:	72          	loadsp 8
+    270d:	07          	or
+    270e:	02          	pushsp
+    270f:	94          	im 20
+    2710:	05          	add
+    2711:	80          	im 0
+    2712:	c3          	im -61
+    2713:	05          	add
+    2714:	33          	loadb
+    2715:	71          	loadsp 4
+    2716:	07          	or
+    2717:	51          	storesp 4
+    2718:	52          	storesp 8
+    2719:	53          	storesp 12
+    271a:	57          	storesp 28
+    271b:	5d          	storesp 52
+    271c:	5b          	storesp 44
+
+0000271d <.L130>:
+	mclst = (tsect						/* Last cluster# + 1 */
+    271d:	74          	loadsp 16
+    271e:	76          	loadsp 24
+    271f:	31          	sub
+    2720:	77          	loadsp 28
+    2721:	31          	sub
+    2722:	79          	loadsp 36
+    2723:	84          	im 4
+    2724:	2a          	lshiftright
+    2725:	8f          	im 15
+    2726:	3d          	pushspadd
+    2727:	33          	loadb
+    2728:	54          	storesp 16
+    2729:	71          	loadsp 4
+    272a:	71          	loadsp 4
+    272b:	31          	sub
+    272c:	53          	storesp 12
+    272d:	56          	storesp 24
+    272e:	56          	storesp 24
+    272f:	9d          	im 29
+    2730:	d1          	im -47
+    2731:	3f          	callpcrel
+    2732:	83          	im 3
+    2733:	e0          	im -32
+    2734:	80          	im 0
+    2735:	08          	load
+    2736:	82          	im 2
+    2737:	05          	add
+
+00002738 <.LM159>:
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+    2738:	70          	loadsp 0
+    2739:	88          	im 8
+    273a:	1a          	addsp 40
+    273b:	0c          	store
+
+0000273c <.LM160>:
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+    273c:	70          	loadsp 0
+    273d:	9f          	im 31
+    273e:	f6          	im -10
+    273f:	26          	ulessthan
+    2740:	81          	im 1
+    2741:	05          	add
+    2742:	57          	storesp 28
+    2743:	55          	storesp 20
+
+00002744 <.LM161>:
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+    2744:	83          	im 3
+    2745:	ff          	im -1
+    2746:	f6          	im -10
+    2747:	75          	loadsp 20
+    2748:	27          	ulessthanorequal
+    2749:	83          	im 3
+    274a:	38          	neqbranch
+
+0000274b <.LM162>:
+#if _FS_FAT32
+		fmt = FS_FAT32;
+    274b:	83          	im 3
+    274c:	56          	storesp 24
+
+0000274d <.L132>:
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+    274d:	75          	loadsp 20
+    274e:	78          	loadsp 32
+    274f:	34          	storeb
+
+00002750 <.LM164>:
+	if (_FS_FAT32 && fmt == FS_FAT32)
+    2750:	75          	loadsp 20
+    2751:	83          	im 3
+    2752:	2e          	eq
+    2753:	81          	im 1
+    2754:	98          	im 24
+    2755:	38          	neqbranch
+
+00002756 <.LM165>:
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+    2756:	76          	loadsp 24
+    2757:	1a          	addsp 40
+    2758:	90          	im 16
+    2759:	19          	addsp 36
+    275a:	0c          	store
+
+0000275b <.LM166>:
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+    275b:	84          	im 4
+    275c:	18          	addsp 32
+    275d:	22          	loadh
+    275e:	77          	loadsp 28
+    275f:	1b          	addsp 44
+    2760:	71          	loadsp 4
+    2761:	84          	im 4
+    2762:	2a          	lshiftright
+    2763:	05          	add
+    2764:	94          	im 20
+    2765:	1a          	addsp 40
+    2766:	0c          	store
+    2767:	55          	storesp 20
+
+00002768 <.LM167>:
+
+	fs->flag = 0;
+    2768:	80          	im 0
+    2769:	0b          	nop
+    276a:	81          	im 1
+    276b:	19          	addsp 36
+    276c:	34          	storeb
+
+0000276d <.LM168>:
+	FatFs = fs;
+    276d:	77          	loadsp 28
+    276e:	83          	im 3
+    276f:	e0          	im -32
+    2770:	90          	im 16
+    2771:	0c          	store
+
+00002772 <.LM169>:
+
+	return FR_OK;
+    2772:	80          	im 0
+    2773:	56          	storesp 24
+
+00002774 <.L119>:
+}
+    2774:	75          	loadsp 20
+    2775:	83          	im 3
+    2776:	e0          	im -32
+    2777:	80          	im 0
+    2778:	0c          	store
+    2779:	96          	im 22
+    277a:	3d          	pushspadd
+    277b:	0d          	popsp
+    277c:	04          	poppc
+
+0000277d <.L138>:
+    277d:	90          	im 16
+    277e:	54          	storesp 16
+    277f:	83          	im 3
+    2780:	be          	im 62
+    2781:	53          	storesp 12
+    2782:	74          	loadsp 16
+    2783:	52          	storesp 8
+    2784:	76          	loadsp 24
+    2785:	51          	storesp 4
+    2786:	e2          	im -30
+    2787:	f7          	im -9
+    2788:	3f          	callpcrel
+    2789:	83          	im 3
+    278a:	e0          	im -32
+    278b:	80          	im 0
+    278c:	08          	load
+    278d:	80          	im 0
+    278e:	ca          	im -54
+    278f:	38          	neqbranch
+
+00002790 <.LM172>:
+    2790:	8e          	im 14
+    2791:	3d          	pushspadd
+    2792:	33          	loadb
+    2793:	55          	storesp 20
+    2794:	74          	loadsp 16
+    2795:	80          	im 0
+    2796:	2e          	eq
+    2797:	80          	im 0
+    2798:	ca          	im -54
+    2799:	38          	neqbranch
+
+0000279a <.LM173>:
+    279a:	02          	pushsp
+    279b:	bb          	im 59
+    279c:	05          	add
+    279d:	33          	loadb
+    279e:	02          	pushsp
+    279f:	84          	im 4
+    27a0:	05          	add
+    27a1:	ba          	im 58
+    27a2:	05          	add
+    27a3:	33          	loadb
+    27a4:	71          	loadsp 4
+    27a5:	98          	im 24
+    27a6:	2b          	ashiftleft
+    27a7:	71          	loadsp 4
+    27a8:	90          	im 16
+    27a9:	2b          	ashiftleft
+    27aa:	07          	or
+    27ab:	02          	pushsp
+    27ac:	8c          	im 12
+    27ad:	05          	add
+    27ae:	b9          	im 57
+    27af:	05          	add
+    27b0:	33          	loadb
+    27b1:	70          	loadsp 0
+    27b2:	88          	im 8
+    27b3:	2b          	ashiftleft
+    27b4:	72          	loadsp 8
+    27b5:	07          	or
+    27b6:	94          	im 20
+    27b7:	3d          	pushspadd
+    27b8:	33          	loadb
+    27b9:	71          	loadsp 4
+    27ba:	07          	or
+
+000027bb <.LM174>:
+    27bb:	70          	loadsp 0
+    27bc:	58          	storesp 32
+    27bd:	7c          	loadsp 48
+    27be:	57          	storesp 28
+    27bf:	54          	storesp 16
+    27c0:	52          	storesp 8
+    27c1:	5d          	storesp 52
+    27c2:	57          	storesp 28
+    27c3:	5a          	storesp 40
+    27c4:	56          	storesp 24
+    27c5:	fb          	im -5
+    27c6:	b8          	im 56
+    27c7:	3f          	callpcrel
+    27c8:	83          	im 3
+    27c9:	e0          	im -32
+    27ca:	80          	im 0
+    27cb:	08          	load
+    27cc:	81          	im 1
+    27cd:	ff          	im -1
+    27ce:	06          	and
+    27cf:	56          	storesp 24
+
+000027d0 <.LM175>:
+    27d0:	75          	loadsp 20
+    27d1:	83          	im 3
+    27d2:	2e          	eq
+    27d3:	09          	not
+    27d4:	81          	im 1
+    27d5:	06          	and
+    27d6:	fc          	im -4
+    27d7:	fa          	im -6
+    27d8:	38          	neqbranch
+
+000027d9 <.L135>:
+    27d9:	81          	im 1
+
+000027da <.LM176>:
+    27da:	0b          	nop
+    27db:	83          	im 3
+    27dc:	e0          	im -32
+    27dd:	80          	im 0
+    27de:	0c          	store
+    27df:	96          	im 22
+    27e0:	3d          	pushspadd
+    27e1:	0d          	popsp
+    27e2:	04          	poppc
+
+000027e3 <.L136>:
+    27e3:	87          	im 7
+
+000027e4 <.LM178>:
+    27e4:	0b          	nop
+    27e5:	83          	im 3
+    27e6:	e0          	im -32
+    27e7:	80          	im 0
+    27e8:	0c          	store
+    27e9:	96          	im 22
+    27ea:	3d          	pushspadd
+    27eb:	0d          	popsp
+    27ec:	04          	poppc
+
+000027ed <.L139>:
+    27ed:	02          	pushsp
+    27ee:	80          	im 0
+    27ef:	d2          	im -46
+    27f0:	05          	add
+    27f1:	33          	loadb
+    27f2:	02          	pushsp
+    27f3:	84          	im 4
+    27f4:	05          	add
+    27f5:	80          	im 0
+    27f6:	d1          	im -47
+    27f7:	05          	add
+    27f8:	33          	loadb
+    27f9:	71          	loadsp 4
+    27fa:	98          	im 24
+    27fb:	2b          	ashiftleft
+    27fc:	71          	loadsp 4
+    27fd:	90          	im 16
+    27fe:	2b          	ashiftleft
+    27ff:	07          	or
+    2800:	98          	im 24
+    2801:	3d          	pushspadd
+    2802:	33          	loadb
+    2803:	70          	loadsp 0
+    2804:	88          	im 8
+    2805:	2b          	ashiftleft
+    2806:	72          	loadsp 8
+    2807:	07          	or
+    2808:	02          	pushsp
+    2809:	94          	im 20
+    280a:	05          	add
+    280b:	80          	im 0
+    280c:	cf          	im -49
+    280d:	05          	add
+    280e:	33          	loadb
+    280f:	71          	loadsp 4
+    2810:	07          	or
+    2811:	90          	im 16
+    2812:	1e          	addsp 56
+    2813:	0c          	store
+    2814:	52          	storesp 8
+
+00002815 <.LM180>:
+    2815:	84          	im 4
+    2816:	1c          	addsp 48
+    2817:	22          	loadh
+    2818:	7b          	loadsp 44
+    2819:	1f          	addsp 60
+    281a:	71          	loadsp 4
+    281b:	84          	im 4
+    281c:	2a          	lshiftright
+    281d:	05          	add
+    281e:	94          	im 20
+    281f:	1e          	addsp 56
+    2820:	0c          	store
+    2821:	52          	storesp 8
+    2822:	5e          	storesp 56
+    2823:	57          	storesp 28
+    2824:	5a          	storesp 40
+    2825:	56          	storesp 24
+
+00002826 <.LM181>:
+    2826:	80          	im 0
+    2827:	0b          	nop
+    2828:	81          	im 1
+    2829:	19          	addsp 36
+    282a:	34          	storeb
+
+0000282b <.LM182>:
+    282b:	77          	loadsp 28
+    282c:	83          	im 3
+    282d:	e0          	im -32
+    282e:	90          	im 16
+    282f:	0c          	store
+
+00002830 <.LM183>:
+    2830:	80          	im 0
+    2831:	56          	storesp 24
+    2832:	fe          	im -2
+    2833:	c0          	im -64
+    2834:	39          	poppcrel
+
+00002835 <pf_open>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+    2835:	e9          	im -23
+    2836:	3d          	pushspadd
+    2837:	0d          	popsp
+
+00002838 <.LM185>:
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+    2838:	83          	im 3
+    2839:	e0          	im -32
+    283a:	90          	im 16
+    283b:	08          	load
+    283c:	56          	storesp 24
+
+0000283d <.LM186>:
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+    283d:	86          	im 6
+    283e:	54          	storesp 16
+
+0000283f <.LM187>:
+    283f:	75          	loadsp 20
+    2840:	80          	im 0
+    2841:	2e          	eq
+    2842:	be          	im 62
+    2843:	38          	neqbranch
+
+00002844 <.LM188>:
+
+	fs->flag = 0;
+    2844:	80          	im 0
+    2845:	0b          	nop
+    2846:	81          	im 1
+    2847:	17          	addsp 28
+    2848:	34          	storeb
+
+00002849 <.LM189>:
+	dj.fn = sp;
+    2849:	99          	im 25
+    284a:	3d          	pushspadd
+    284b:	e0          	im -32
+    284c:	11          	addsp 4
+    284d:	46          	storesp 88
+
+0000284e <.LM190>:
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+    284e:	6a          	loadsp 104
+    284f:	54          	storesp 16
+    2850:	c0          	im -64
+    2851:	11          	addsp 4
+    2852:	53          	storesp 12
+    2853:	ec          	im -20
+    2854:	05          	add
+    2855:	51          	storesp 4
+    2856:	f5          	im -11
+    2857:	c1          	im -63
+    2858:	3f          	callpcrel
+
+00002859 <.LM191>:
+	if (res != FR_OK) return res;		/* Follow failed */
+    2859:	83          	im 3
+    285a:	e0          	im -32
+    285b:	80          	im 0
+    285c:	08          	load
+    285d:	54          	storesp 16
+    285e:	83          	im 3
+    285f:	e0          	im -32
+    2860:	80          	im 0
+    2861:	08          	load
+    2862:	9e          	im 30
+    2863:	38          	neqbranch
+
+00002864 <.LM192>:
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+    2864:	89          	im 9
+    2865:	3d          	pushspadd
+    2866:	33          	loadb
+    2867:	54          	storesp 16
+    2868:	73          	loadsp 12
+    2869:	80          	im 0
+    286a:	2e          	eq
+    286b:	93          	im 19
+    286c:	38          	neqbranch
+    286d:	02          	pushsp
+    286e:	ab          	im 43
+    286f:	05          	add
+    2870:	33          	loadb
+    2871:	70          	loadsp 0
+    2872:	84          	im 4
+    2873:	2a          	lshiftright
+    2874:	70          	loadsp 0
+    2875:	81          	im 1
+    2876:	06          	and
+    2877:	51          	storesp 4
+    2878:	55          	storesp 20
+    2879:	55          	storesp 20
+    287a:	73          	loadsp 12
+    287b:	80          	im 0
+    287c:	2e          	eq
+    287d:	8c          	im 12
+    287e:	38          	neqbranch
+
+0000287f <.L144>:
+		return FR_NO_FILE;
+    287f:	83          	im 3
+    2880:	54          	storesp 16
+
+00002881 <.L140>:
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+    2881:	73          	loadsp 12
+    2882:	83          	im 3
+    2883:	e0          	im -32
+    2884:	80          	im 0
+    2885:	0c          	store
+    2886:	99          	im 25
+    2887:	3d          	pushspadd
+    2888:	0d          	popsp
+    2889:	04          	poppc
+
+0000288a <.L143>:
+    288a:	02          	pushsp
+    288b:	b5          	im 53
+    288c:	05          	add
+    288d:	33          	loadb
+    288e:	8f          	im 15
+    288f:	3d          	pushspadd
+    2890:	33          	loadb
+    2891:	71          	loadsp 4
+    2892:	98          	im 24
+    2893:	2b          	ashiftleft
+    2894:	71          	loadsp 4
+    2895:	90          	im 16
+    2896:	2b          	ashiftleft
+    2897:	07          	or
+    2898:	02          	pushsp
+    2899:	8c          	im 12
+    289a:	05          	add
+    289b:	bb          	im 59
+    289c:	05          	add
+    289d:	33          	loadb
+    289e:	02          	pushsp
+    289f:	90          	im 16
+    28a0:	05          	add
+    28a1:	ba          	im 58
+    28a2:	05          	add
+    28a3:	33          	loadb
+    28a4:	71          	loadsp 4
+    28a5:	88          	im 8
+    28a6:	2b          	ashiftleft
+    28a7:	07          	or
+    28a8:	72          	loadsp 8
+    28a9:	07          	or
+    28aa:	a0          	im 32
+    28ab:	1b          	addsp 44
+    28ac:	0c          	store
+
+000028ad <.LM196>:
+    28ad:	02          	pushsp
+    28ae:	90          	im 16
+    28af:	05          	add
+    28b0:	bf          	im 63
+    28b1:	05          	add
+    28b2:	33          	loadb
+    28b3:	02          	pushsp
+    28b4:	94          	im 20
+    28b5:	05          	add
+    28b6:	be          	im 62
+    28b7:	05          	add
+    28b8:	33          	loadb
+    28b9:	71          	loadsp 4
+    28ba:	98          	im 24
+    28bb:	2b          	ashiftleft
+    28bc:	71          	loadsp 4
+    28bd:	90          	im 16
+    28be:	2b          	ashiftleft
+    28bf:	07          	or
+    28c0:	02          	pushsp
+    28c1:	9c          	im 28
+    28c2:	05          	add
+    28c3:	bd          	im 61
+    28c4:	05          	add
+    28c5:	33          	loadb
+    28c6:	70          	loadsp 0
+    28c7:	88          	im 8
+    28c8:	2b          	ashiftleft
+    28c9:	72          	loadsp 8
+    28ca:	07          	or
+    28cb:	99          	im 25
+    28cc:	3d          	pushspadd
+    28cd:	33          	loadb
+    28ce:	71          	loadsp 4
+    28cf:	07          	or
+    28d0:	7f          	loadsp 60
+    28d1:	9c          	im 28
+    28d2:	05          	add
+    28d3:	0c          	store
+    28d4:	52          	storesp 8
+
+000028d5 <.LM197>:
+    28d5:	83          	im 3
+    28d6:	e0          	im -32
+    28d7:	80          	im 0
+    28d8:	08          	load
+    28d9:	98          	im 24
+    28da:	1f          	addsp 60
+    28db:	0c          	store
+    28dc:	56          	storesp 24
+    28dd:	5a          	storesp 40
+    28de:	52          	storesp 8
+    28df:	52          	storesp 8
+    28e0:	53          	storesp 12
+    28e1:	57          	storesp 28
+    28e2:	59          	storesp 36
+    28e3:	57          	storesp 28
+
+000028e4 <.LM198>:
+    28e4:	81          	im 1
+    28e5:	0b          	nop
+    28e6:	81          	im 1
+    28e7:	17          	addsp 28
+    28e8:	34          	storeb
+
+000028e9 <.LM199>:
+    28e9:	83          	im 3
+    28ea:	e0          	im -32
+    28eb:	80          	im 0
+    28ec:	08          	load
+
+000028ed <.LM200>:
+    28ed:	83          	im 3
+    28ee:	e0          	im -32
+    28ef:	80          	im 0
+    28f0:	0c          	store
+    28f1:	99          	im 25
+    28f2:	3d          	pushspadd
+    28f3:	0d          	popsp
+    28f4:	04          	poppc
+
+000028f5 <pf_read>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+    28f5:	f4          	im -12
+    28f6:	3d          	pushspadd
+    28f7:	0d          	popsp
+    28f8:	7e          	loadsp 56
+    28f9:	61          	loadsp 68
+    28fa:	02          	pushsp
+    28fb:	88          	im 8
+    28fc:	05          	add
+    28fd:	be          	im 62
+    28fe:	05          	add
+    28ff:	22          	loadh
+
+00002900 <.LM202>:
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+    2900:	72          	loadsp 8
+
+00002901 <.LM203>:
+	FATFS *fs = FatFs;
+    2901:	83          	im 3
+    2902:	e0          	im -32
+    2903:	90          	im 16
+    2904:	08          	load
+    2905:	5c          	storesp 48
+    2906:	5d          	storesp 52
+    2907:	5b          	storesp 44
+    2908:	5c          	storesp 48
+    2909:	5c          	storesp 48
+
+0000290a <.LM204>:
+
+
+	*br = 0;
+    290a:	80          	im 0
+    290b:	7b          	loadsp 44
+    290c:	23          	storeh
+
+0000290d <.LM205>:
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+    290d:	86          	im 6
+    290e:	56          	storesp 24
+    290f:	77          	loadsp 28
+    2910:	80          	im 0
+    2911:	2e          	eq
+    2912:	81          	im 1
+    2913:	ca          	im -54
+    2914:	38          	neqbranch
+
+00002915 <.LM206>:
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+    2915:	81          	im 1
+    2916:	18          	addsp 32
+    2917:	33          	loadb
+    2918:	81          	im 1
+    2919:	06          	and
+    291a:	55          	storesp 20
+
+0000291b <.LM207>:
+		return FR_NOT_OPENED;
+    291b:	85          	im 5
+    291c:	56          	storesp 24
+
+0000291d <.LM208>:
+    291d:	74          	loadsp 16
+    291e:	80          	im 0
+    291f:	2e          	eq
+    2920:	81          	im 1
+    2921:	bc          	im 60
+    2922:	38          	neqbranch
+
+00002923 <.LM209>:
+
+	remain = fs->fsize - fs->fptr;
+    2923:	98          	im 24
+    2924:	18          	addsp 32
+    2925:	08          	load
+    2926:	9c          	im 28
+    2927:	19          	addsp 36
+    2928:	08          	load
+    2929:	71          	loadsp 4
+    292a:	31          	sub
+    292b:	56          	storesp 24
+    292c:	57          	storesp 28
+
+0000292d <.LM210>:
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+    292d:	78          	loadsp 32
+    292e:	75          	loadsp 20
+    292f:	26          	ulessthan
+    2930:	81          	im 1
+    2931:	b5          	im 53
+    2932:	38          	neqbranch
+
+00002933 <.L149>:
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+    2933:	78          	loadsp 32
+    2934:	80          	im 0
+    2935:	2e          	eq
+    2936:	81          	im 1
+    2937:	a4          	im 36
+    2938:	38          	neqbranch
+
+00002939 <.L169>:
+    2939:	76          	loadsp 24
+    293a:	83          	im 3
+    293b:	ff          	im -1
+    293c:	06          	and
+    293d:	55          	storesp 20
+    293e:	74          	loadsp 16
+    293f:	80          	im 0
+    2940:	c1          	im -63
+    2941:	38          	neqbranch
+
+00002942 <.LM213>:
+    2942:	82          	im 2
+    2943:	18          	addsp 32
+    2944:	33          	loadb
+    2945:	ff          	im -1
+    2946:	05          	add
+    2947:	77          	loadsp 28
+    2948:	89          	im 9
+    2949:	2a          	lshiftright
+    294a:	06          	and
+    294b:	70          	loadsp 0
+    294c:	81          	im 1
+    294d:	ff          	im -1
+    294e:	06          	and
+    294f:	51          	storesp 4
+    2950:	55          	storesp 20
+
+00002951 <.LM214>:
+    2951:	74          	loadsp 16
+    2952:	93          	im 19
+    2953:	38          	neqbranch
+
+00002954 <.LM215>:
+    2954:	76          	loadsp 24
+    2955:	81          	im 1
+    2956:	99          	im 25
+    2957:	38          	neqbranch
+    2958:	a0          	im 32
+    2959:	18          	addsp 32
+    295a:	08          	load
+    295b:	56          	storesp 24
+
+0000295c <.L155>:
+    295c:	81          	im 1
+    295d:	76          	loadsp 24
+    295e:	27          	ulessthanorequal
+    295f:	81          	im 1
+    2960:	a3          	im 35
+    2961:	38          	neqbranch
+
+00002962 <.LM217>:
+    2962:	75          	loadsp 20
+    2963:	a4          	im 36
+    2964:	19          	addsp 36
+    2965:	0c          	store
+
+00002966 <.L153>:
+    2966:	a4          	im 36
+    2967:	18          	addsp 32
+    2968:	08          	load
+    2969:	51          	storesp 4
+    296a:	f0          	im -16
+    296b:	fd          	im -3
+    296c:	3f          	callpcrel
+
+0000296d <.LM219>:
+    296d:	83          	im 3
+    296e:	e0          	im -32
+    296f:	80          	im 0
+    2970:	08          	load
+    2971:	80          	im 0
+    2972:	2e          	eq
+    2973:	81          	im 1
+    2974:	8f          	im 15
+    2975:	38          	neqbranch
+
+00002976 <.LM220>:
+    2976:	83          	im 3
+    2977:	e0          	im -32
+    2978:	80          	im 0
+    2979:	08          	load
+    297a:	15          	addsp 20
+    297b:	a8          	im 40
+    297c:	19          	addsp 36
+    297d:	0c          	store
+    297e:	98          	im 24
+    297f:	18          	addsp 32
+    2980:	08          	load
+    2981:	57          	storesp 28
+
+00002982 <.L152>:
+    2982:	76          	loadsp 24
+    2983:	83          	im 3
+    2984:	ff          	im -1
+    2985:	06          	and
+    2986:	84          	im 4
+    2987:	80          	im 0
+    2988:	71          	loadsp 4
+    2989:	31          	sub
+    298a:	70          	loadsp 0
+    298b:	83          	im 3
+    298c:	ff          	im -1
+    298d:	ff          	im -1
+    298e:	06          	and
+    298f:	58          	storesp 32
+    2990:	51          	storesp 4
+    2991:	55          	storesp 20
+
+00002992 <.LM222>:
+    2992:	78          	loadsp 32
+    2993:	76          	loadsp 24
+    2994:	27          	ulessthanorequal
+    2995:	83          	im 3
+    2996:	38          	neqbranch
+    2997:	78          	loadsp 32
+    2998:	56          	storesp 24
+
+00002999 <.L159>:
+    2999:	75          	loadsp 20
+    299a:	54          	storesp 16
+    299b:	98          	im 24
+    299c:	18          	addsp 32
+    299d:	08          	load
+    299e:	83          	im 3
+    299f:	ff          	im -1
+    29a0:	06          	and
+    29a1:	53          	storesp 12
+    29a2:	a8          	im 40
+    29a3:	18          	addsp 32
+    29a4:	08          	load
+    29a5:	52          	storesp 8
+    29a6:	79          	loadsp 36
+    29a7:	55          	storesp 20
+    29a8:	7b          	loadsp 44
+    29a9:	80          	im 0
+    29aa:	2e          	eq
+    29ab:	80          	im 0
+    29ac:	d2          	im -46
+    29ad:	38          	neqbranch
+
+000029ae <.L161>:
+    29ae:	74          	loadsp 16
+    29af:	51          	storesp 4
+    29b0:	de          	im -34
+    29b1:	cd          	im -51
+    29b2:	3f          	callpcrel
+
+000029b3 <.LM224>:
+    29b3:	83          	im 3
+    29b4:	e0          	im -32
+    29b5:	80          	im 0
+    29b6:	08          	load
+    29b7:	80          	im 0
+    29b8:	cb          	im -53
+    29b9:	38          	neqbranch
+
+000029ba <.LM225>:
+    29ba:	98          	im 24
+    29bb:	18          	addsp 32
+    29bc:	08          	load
+    29bd:	16          	addsp 24
+    29be:	70          	loadsp 0
+    29bf:	58          	storesp 32
+    29c0:	98          	im 24
+    29c1:	19          	addsp 36
+    29c2:	0c          	store
+    29c3:	75          	loadsp 20
+    29c4:	1a          	addsp 40
+
+000029c5 <.LM226>:
+    29c5:	79          	loadsp 36
+    29c6:	77          	loadsp 28
+    29c7:	31          	sub
+    29c8:	70          	loadsp 0
+    29c9:	83          	im 3
+    29ca:	ff          	im -1
+    29cb:	ff          	im -1
+    29cc:	06          	and
+    29cd:	7d          	loadsp 52
+    29ce:	22          	loadh
+    29cf:	79          	loadsp 36
+    29d0:	05          	add
+    29d1:	52          	storesp 8
+    29d2:	5b          	storesp 44
+    29d3:	56          	storesp 24
+    29d4:	5a          	storesp 40
+    29d5:	74          	loadsp 16
+    29d6:	7b          	loadsp 44
+    29d7:	23          	storeh
+    29d8:	78          	loadsp 32
+    29d9:	fe          	im -2
+    29da:	de          	im -34
+    29db:	38          	neqbranch
+
+000029dc <.L165>:
+	}
+
+	return FR_OK;
+    29dc:	80          	im 0
+    29dd:	56          	storesp 24
+
+000029de <.L146>:
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+    29de:	75          	loadsp 20
+    29df:	83          	im 3
+    29e0:	e0          	im -32
+    29e1:	80          	im 0
+    29e2:	0c          	store
+    29e3:	8e          	im 14
+    29e4:	3d          	pushspadd
+    29e5:	0d          	popsp
+    29e6:	04          	poppc
+
+000029e7 <.L167>:
+    29e7:	74          	loadsp 16
+    29e8:	83          	im 3
+    29e9:	ff          	im -1
+    29ea:	ff          	im -1
+    29eb:	06          	and
+    29ec:	59          	storesp 36
+    29ed:	fe          	im -2
+    29ee:	c4          	im -60
+    29ef:	39          	poppcrel
+
+000029f0 <.L154>:
+    29f0:	a4          	im 36
+    29f1:	18          	addsp 32
+    29f2:	08          	load
+    29f3:	51          	storesp 4
+    29f4:	ed          	im -19
+    29f5:	a4          	im 36
+    29f6:	3f          	callpcrel
+    29f7:	83          	im 3
+    29f8:	e0          	im -32
+    29f9:	80          	im 0
+    29fa:	08          	load
+    29fb:	56          	storesp 24
+    29fc:	fe          	im -2
+    29fd:	de          	im -34
+    29fe:	39          	poppcrel
+
+000029ff <.L168>:
+    29ff:	7b          	loadsp 44
+    2a00:	55          	storesp 20
+    2a01:	ff          	im -1
+    2a02:	ab          	im 43
+    2a03:	39          	poppcrel
+
+00002a04 <.L157>:
+    2a04:	80          	im 0
+    2a05:	0b          	nop
+    2a06:	81          	im 1
+    2a07:	19          	addsp 36
+    2a08:	34          	storeb
+
+00002a09 <.LM233>:
+    2a09:	81          	im 1
+
+00002a0a <.LM234>:
+    2a0a:	0b          	nop
+    2a0b:	83          	im 3
+    2a0c:	e0          	im -32
+    2a0d:	80          	im 0
+    2a0e:	0c          	store
+    2a0f:	8e          	im 14
+    2a10:	3d          	pushspadd
+    2a11:	0d          	popsp
+    2a12:	04          	poppc
+
+00002a13 <pf_lseek>:
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+    2a13:	fa          	im -6
+    2a14:	3d          	pushspadd
+    2a15:	0d          	popsp
+    2a16:	78          	loadsp 32
+
+00002a17 <.LM236>:
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+    2a17:	83          	im 3
+    2a18:	e0          	im -32
+    2a19:	90          	im 16
+    2a1a:	08          	load
+    2a1b:	55          	storesp 20
+    2a1c:	55          	storesp 20
+
+00002a1d <.LM237>:
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+    2a1d:	86          	im 6
+    2a1e:	56          	storesp 24
+    2a1f:	73          	loadsp 12
+    2a20:	80          	im 0
+    2a21:	2e          	eq
+    2a22:	81          	im 1
+    2a23:	cd          	im -51
+    2a24:	38          	neqbranch
+
+00002a25 <.LM238>:
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+    2a25:	81          	im 1
+    2a26:	14          	addsp 16
+    2a27:	33          	loadb
+    2a28:	81          	im 1
+    2a29:	06          	and
+    2a2a:	53          	storesp 12
+
+00002a2b <.LM239>:
+			return FR_NOT_OPENED;
+    2a2b:	85          	im 5
+    2a2c:	56          	storesp 24
+
+00002a2d <.LM240>:
+    2a2d:	72          	loadsp 8
+    2a2e:	80          	im 0
+    2a2f:	2e          	eq
+    2a30:	81          	im 1
+    2a31:	bf          	im 63
+    2a32:	38          	neqbranch
+
+00002a33 <.LM241>:
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+    2a33:	9c          	im 28
+    2a34:	14          	addsp 16
+    2a35:	08          	load
+    2a36:	53          	storesp 12
+    2a37:	74          	loadsp 16
+    2a38:	73          	loadsp 12
+    2a39:	26          	ulessthan
+    2a3a:	81          	im 1
+    2a3b:	be          	im 62
+    2a3c:	38          	neqbranch
+
+00002a3d <.L173>:
+	ifptr = fs->fptr;
+    2a3d:	98          	im 24
+    2a3e:	14          	addsp 16
+    2a3f:	08          	load
+    2a40:	57          	storesp 28
+
+00002a41 <.LM243>:
+	fs->fptr = 0;
+    2a41:	80          	im 0
+    2a42:	0b          	nop
+    2a43:	98          	im 24
+    2a44:	15          	addsp 20
+    2a45:	0c          	store
+
+00002a46 <.LM244>:
+	if (ofs > 0) {
+    2a46:	74          	loadsp 16
+    2a47:	80          	im 0
+    2a48:	2e          	eq
+    2a49:	81          	im 1
+    2a4a:	a4          	im 36
+    2a4b:	38          	neqbranch
+
+00002a4c <.LM245>:
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+    2a4c:	82          	im 2
+    2a4d:	14          	addsp 16
+    2a4e:	33          	loadb
+    2a4f:	70          	loadsp 0
+    2a50:	89          	im 9
+    2a51:	2b          	ashiftleft
+    2a52:	57          	storesp 28
+    2a53:	53          	storesp 12
+
+00002a54 <.LM246>:
+		if (ifptr > 0 &&
+    2a54:	76          	loadsp 24
+    2a55:	80          	im 0
+    2a56:	2e          	eq
+    2a57:	81          	im 1
+    2a58:	a6          	im 38
+    2a59:	38          	neqbranch
+    2a5a:	75          	loadsp 20
+    2a5b:	52          	storesp 8
+    2a5c:	ff          	im -1
+    2a5d:	15          	addsp 20
+    2a5e:	51          	storesp 4
+    2a5f:	97          	im 23
+    2a60:	a1          	im 33
+    2a61:	3f          	callpcrel
+    2a62:	83          	im 3
+    2a63:	e0          	im -32
+    2a64:	80          	im 0
+    2a65:	08          	load
+    2a66:	ff          	im -1
+    2a67:	18          	addsp 32
+    2a68:	77          	loadsp 28
+    2a69:	54          	storesp 16
+    2a6a:	70          	loadsp 0
+    2a6b:	53          	storesp 12
+    2a6c:	58          	storesp 32
+    2a6d:	53          	storesp 12
+    2a6e:	97          	im 23
+    2a6f:	92          	im 18
+    2a70:	3f          	callpcrel
+    2a71:	83          	im 3
+    2a72:	e0          	im -32
+    2a73:	80          	im 0
+    2a74:	08          	load
+    2a75:	73          	loadsp 12
+    2a76:	26          	ulessthan
+    2a77:	81          	im 1
+    2a78:	86          	im 6
+    2a79:	38          	neqbranch
+
+00002a7a <.LM247>:
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+    2a7a:	75          	loadsp 20
+    2a7b:	30          	neg
+    2a7c:	70          	loadsp 0
+    2a7d:	78          	loadsp 32
+    2a7e:	06          	and
+    2a7f:	70          	loadsp 0
+    2a80:	98          	im 24
+    2a81:	17          	addsp 28
+    2a82:	0c          	store
+
+00002a83 <.LM248>:
+			ofs -= fs->fptr;
+    2a83:	76          	loadsp 24
+    2a84:	71          	loadsp 4
+    2a85:	31          	sub
+
+00002a86 <.LM249>:
+			clst = fs->curr_clust;
+    2a86:	a4          	im 36
+    2a87:	17          	addsp 28
+    2a88:	08          	load
+    2a89:	52          	storesp 8
+    2a8a:	57          	storesp 28
+    2a8b:	51          	storesp 4
+    2a8c:	53          	storesp 12
+
+00002a8d <.L176>:
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+    2a8d:	75          	loadsp 20
+    2a8e:	75          	loadsp 20
+    2a8f:	27          	ulessthanorequal
+    2a90:	b7          	im 55
+    2a91:	38          	neqbranch
+
+00002a92 <.L188>:
+    2a92:	72          	loadsp 8
+    2a93:	51          	storesp 4
+    2a94:	ec          	im -20
+    2a95:	84          	im 4
+    2a96:	3f          	callpcrel
+    2a97:	83          	im 3
+    2a98:	e0          	im -32
+    2a99:	80          	im 0
+    2a9a:	08          	load
+    2a9b:	53          	storesp 12
+
+00002a9c <.LM252>:
+    2a9c:	81          	im 1
+    2a9d:	0b          	nop
+    2a9e:	83          	im 3
+    2a9f:	e0          	im -32
+    2aa0:	80          	im 0
+    2aa1:	08          	load
+    2aa2:	27          	ulessthanorequal
+    2aa3:	80          	im 0
+    2aa4:	e5          	im -27
+    2aa5:	38          	neqbranch
+    2aa6:	83          	im 3
+    2aa7:	e0          	im -32
+    2aa8:	80          	im 0
+    2aa9:	08          	load
+    2aaa:	88          	im 8
+    2aab:	15          	addsp 20
+    2aac:	08          	load
+    2aad:	27          	ulessthanorequal
+    2aae:	80          	im 0
+    2aaf:	da          	im -38
+    2ab0:	38          	neqbranch
+
+00002ab1 <.LM253>:
+    2ab1:	83          	im 3
+    2ab2:	e0          	im -32
+    2ab3:	80          	im 0
+    2ab4:	08          	load
+    2ab5:	a4          	im 36
+    2ab6:	15          	addsp 20
+    2ab7:	0c          	store
+
+00002ab8 <.LM254>:
+    2ab8:	98          	im 24
+    2ab9:	14          	addsp 16
+    2aba:	08          	load
+    2abb:	16          	addsp 24
+    2abc:	98          	im 24
+    2abd:	15          	addsp 20
+    2abe:	0c          	store
+
+00002abf <.LM255>:
+    2abf:	74          	loadsp 16
+    2ac0:	76          	loadsp 24
+    2ac1:	31          	sub
+    2ac2:	55          	storesp 20
+    2ac3:	74          	loadsp 16
+    2ac4:	76          	loadsp 24
+    2ac5:	26          	ulessthan
+    2ac6:	cb          	im -53
+    2ac7:	38          	neqbranch
+
+00002ac8 <.L185>:
+		}
+		fs->fptr += ofs;
+    2ac8:	98          	im 24
+    2ac9:	14          	addsp 16
+    2aca:	08          	load
+    2acb:	15          	addsp 20
+    2acc:	70          	loadsp 0
+    2acd:	98          	im 24
+    2ace:	16          	addsp 24
+    2acf:	0c          	store
+
+00002ad0 <.LM257>:
+		sect = clust2sect(clst);		/* Current sector */
+    2ad0:	73          	loadsp 12
+    2ad1:	52          	storesp 8
+    2ad2:	56          	storesp 24
+    2ad3:	ee          	im -18
+    2ad4:	94          	im 20
+    2ad5:	3f          	callpcrel
+
+00002ad6 <.LM258>:
+		if (!sect) goto fe_abort;
+    2ad6:	83          	im 3
+    2ad7:	e0          	im -32
+    2ad8:	80          	im 0
+    2ad9:	08          	load
+    2ada:	80          	im 0
+    2adb:	2e          	eq
+    2adc:	ad          	im 45
+    2add:	38          	neqbranch
+
+00002ade <.LM259>:
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+    2ade:	82          	im 2
+    2adf:	14          	addsp 16
+    2ae0:	33          	loadb
+    2ae1:	ff          	im -1
+    2ae2:	05          	add
+    2ae3:	76          	loadsp 24
+    2ae4:	89          	im 9
+    2ae5:	2a          	lshiftright
+    2ae6:	06          	and
+    2ae7:	83          	im 3
+    2ae8:	e0          	im -32
+    2ae9:	80          	im 0
+    2aea:	08          	load
+    2aeb:	05          	add
+    2aec:	a8          	im 40
+    2aed:	15          	addsp 20
+    2aee:	0c          	store
+
+00002aef <.L174>:
+	}
+
+	return FR_OK;
+    2aef:	80          	im 0
+    2af0:	56          	storesp 24
+
+00002af1 <.L170>:
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+    2af1:	75          	loadsp 20
+    2af2:	83          	im 3
+    2af3:	e0          	im -32
+    2af4:	80          	im 0
+    2af5:	0c          	store
+    2af6:	88          	im 8
+    2af7:	3d          	pushspadd
+    2af8:	0d          	popsp
+    2af9:	04          	poppc
+
+00002afa <.L187>:
+    2afa:	72          	loadsp 8
+    2afb:	55          	storesp 20
+    2afc:	fe          	im -2
+    2afd:	bf          	im 63
+    2afe:	39          	poppcrel
+
+00002aff <.L175>:
+    2aff:	a0          	im 32
+    2b00:	14          	addsp 16
+    2b01:	08          	load
+
+00002b02 <.LM264>:
+    2b02:	70          	loadsp 0
+    2b03:	a4          	im 36
+    2b04:	16          	addsp 24
+    2b05:	0c          	store
+    2b06:	53          	storesp 12
+    2b07:	ff          	im -1
+    2b08:	84          	im 4
+    2b09:	39          	poppcrel
+
+00002b0a <.L181>:
+    2b0a:	80          	im 0
+    2b0b:	0b          	nop
+    2b0c:	81          	im 1
+    2b0d:	15          	addsp 20
+    2b0e:	34          	storeb
+
+00002b0f <.LM266>:
+    2b0f:	81          	im 1
+
+00002b10 <.LM267>:
+    2b10:	0b          	nop
+    2b11:	83          	im 3
+    2b12:	e0          	im -32
+    2b13:	80          	im 0
+    2b14:	0c          	store
+    2b15:	88          	im 8
+    2b16:	3d          	pushspadd
+    2b17:	0d          	popsp
+    2b18:	04          	poppc
+
+00002b19 <pf_opendir>:
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+    2b19:	ee          	im -18
+    2b1a:	3d          	pushspadd
+    2b1b:	0d          	popsp
+    2b1c:	64          	loadsp 80
+    2b1d:	56          	storesp 24
+
+00002b1e <.LM269>:
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+    2b1e:	86          	im 6
+    2b1f:	55          	storesp 20
+
+00002b20 <.LM270>:
+    2b20:	83          	im 3
+    2b21:	e0          	im -32
+    2b22:	90          	im 16
+    2b23:	08          	load
+    2b24:	80          	im 0
+    2b25:	2e          	eq
+    2b26:	80          	im 0
+    2b27:	f1          	im -15
+    2b28:	38          	neqbranch
+
+00002b29 <.LM271>:
+	} else {
+		dj->fn = sp;
+    2b29:	94          	im 20
+    2b2a:	3d          	pushspadd
+    2b2b:	f4          	im -12
+    2b2c:	11          	addsp 4
+    2b2d:	84          	im 4
+    2b2e:	18          	addsp 32
+    2b2f:	0c          	store
+
+00002b30 <.LM272>:
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+    2b30:	66          	loadsp 88
+    2b31:	54          	storesp 16
+    2b32:	d4          	im -44
+    2b33:	05          	add
+    2b34:	52          	storesp 8
+    2b35:	75          	loadsp 20
+    2b36:	51          	storesp 4
+    2b37:	ef          	im -17
+    2b38:	e0          	im -32
+    2b39:	3f          	callpcrel
+    2b3a:	83          	im 3
+    2b3b:	e0          	im -32
+    2b3c:	80          	im 0
+    2b3d:	08          	load
+    2b3e:	55          	storesp 20
+
+00002b3f <.LM273>:
+		if (res == FR_OK) {						/* Follow completed */
+    2b3f:	83          	im 3
+    2b40:	e0          	im -32
+    2b41:	80          	im 0
+    2b42:	08          	load
+    2b43:	80          	im 0
+    2b44:	cf          	im -49
+    2b45:	38          	neqbranch
+
+00002b46 <.LM274>:
+			if (dir[0]) {						/* It is not the root dir */
+    2b46:	89          	im 9
+    2b47:	3d          	pushspadd
+    2b48:	33          	loadb
+    2b49:	54          	storesp 16
+    2b4a:	73          	loadsp 12
+    2b4b:	80          	im 0
+    2b4c:	2e          	eq
+    2b4d:	bc          	im 60
+    2b4e:	38          	neqbranch
+
+00002b4f <.LM275>:
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+    2b4f:	02          	pushsp
+    2b50:	ab          	im 43
+    2b51:	05          	add
+    2b52:	33          	loadb
+    2b53:	70          	loadsp 0
+    2b54:	84          	im 4
+    2b55:	2a          	lshiftright
+    2b56:	70          	loadsp 0
+    2b57:	81          	im 1
+    2b58:	06          	and
+    2b59:	51          	storesp 4
+    2b5a:	55          	storesp 20
+    2b5b:	55          	storesp 20
+
+00002b5c <.LM276>:
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+    2b5c:	84          	im 4
+    2b5d:	55          	storesp 20
+
+00002b5e <.LM277>:
+    2b5e:	73          	loadsp 12
+    2b5f:	80          	im 0
+    2b60:	2e          	eq
+    2b61:	b7          	im 55
+    2b62:	38          	neqbranch
+
+00002b63 <.LM278>:
+    2b63:	02          	pushsp
+    2b64:	b5          	im 53
+    2b65:	05          	add
+    2b66:	33          	loadb
+    2b67:	8f          	im 15
+    2b68:	3d          	pushspadd
+    2b69:	33          	loadb
+    2b6a:	71          	loadsp 4
+    2b6b:	98          	im 24
+    2b6c:	2b          	ashiftleft
+    2b6d:	71          	loadsp 4
+    2b6e:	90          	im 16
+    2b6f:	2b          	ashiftleft
+    2b70:	07          	or
+    2b71:	02          	pushsp
+    2b72:	8c          	im 12
+    2b73:	05          	add
+    2b74:	bb          	im 59
+    2b75:	05          	add
+    2b76:	33          	loadb
+    2b77:	02          	pushsp
+    2b78:	90          	im 16
+    2b79:	05          	add
+    2b7a:	ba          	im 58
+    2b7b:	05          	add
+    2b7c:	33          	loadb
+    2b7d:	71          	loadsp 4
+    2b7e:	88          	im 8
+    2b7f:	2b          	ashiftleft
+    2b80:	07          	or
+    2b81:	72          	loadsp 8
+    2b82:	07          	or
+    2b83:	88          	im 8
+    2b84:	1b          	addsp 44
+    2b85:	0c          	store
+    2b86:	53          	storesp 12
+    2b87:	57          	storesp 28
+    2b88:	59          	storesp 36
+    2b89:	57          	storesp 28
+
+00002b8a <.L198>:
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+    2b8a:	75          	loadsp 20
+    2b8b:	51          	storesp 4
+    2b8c:	ed          	im -19
+    2b8d:	88          	im 8
+    2b8e:	3f          	callpcrel
+    2b8f:	83          	im 3
+    2b90:	e0          	im -32
+    2b91:	80          	im 0
+    2b92:	08          	load
+    2b93:	55          	storesp 20
+
+00002b94 <.L192>:
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+    2b94:	74          	loadsp 16
+    2b95:	83          	im 3
+    2b96:	2e          	eq
+    2b97:	8a          	im 10
+    2b98:	38          	neqbranch
+
+00002b99 <.L191>:
+	}
+
+	return res;
+}
+    2b99:	74          	loadsp 16
+    2b9a:	83          	im 3
+    2b9b:	e0          	im -32
+    2b9c:	80          	im 0
+    2b9d:	0c          	store
+    2b9e:	94          	im 20
+    2b9f:	3d          	pushspadd
+    2ba0:	0d          	popsp
+    2ba1:	04          	poppc
+
+00002ba2 <.L200>:
+    2ba2:	84          	im 4
+
+00002ba3 <.LM283>:
+    2ba3:	0b          	nop
+    2ba4:	83          	im 3
+    2ba5:	e0          	im -32
+    2ba6:	80          	im 0
+    2ba7:	0c          	store
+    2ba8:	94          	im 20
+    2ba9:	3d          	pushspadd
+    2baa:	0d          	popsp
+    2bab:	04          	poppc
+
+00002bac <pf_readdir>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+    2bac:	eb          	im -21
+    2bad:	3d          	pushspadd
+    2bae:	0d          	popsp
+    2baf:	67          	loadsp 92
+    2bb0:	69          	loadsp 100
+    2bb1:	5b          	storesp 44
+    2bb2:	59          	storesp 36
+
+00002bb3 <.LM285>:
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+    2bb3:	86          	im 6
+    2bb4:	55          	storesp 20
+
+00002bb5 <.LM286>:
+    2bb5:	83          	im 3
+    2bb6:	e0          	im -32
+    2bb7:	90          	im 16
+    2bb8:	08          	load
+    2bb9:	80          	im 0
+    2bba:	2e          	eq
+    2bbb:	81          	im 1
+    2bbc:	f1          	im -15
+    2bbd:	38          	neqbranch
+
+00002bbe <.LM287>:
+	} else {
+		dj->fn = sp;
+    2bbe:	97          	im 23
+    2bbf:	3d          	pushspadd
+    2bc0:	f4          	im -12
+    2bc1:	05          	add
+    2bc2:	84          	im 4
+    2bc3:	1a          	addsp 40
+    2bc4:	0c          	store
+
+00002bc5 <.LM288>:
+		if (!fno) {
+    2bc5:	79          	loadsp 36
+    2bc6:	80          	im 0
+    2bc7:	2e          	eq
+    2bc8:	83          	im 3
+    2bc9:	84          	im 4
+    2bca:	38          	neqbranch
+
+00002bcb <.LBB24>:
+    2bcb:	8c          	im 12
+    2bcc:	3d          	pushspadd
+    2bcd:	58          	storesp 32
+
+00002bce <.LM290>:
+    2bce:	83          	im 3
+    2bcf:	55          	storesp 20
+
+00002bd0 <.LM291>:
+    2bd0:	90          	im 16
+    2bd1:	19          	addsp 36
+    2bd2:	08          	load
+    2bd3:	81          	im 1
+    2bd4:	fb          	im -5
+    2bd5:	38          	neqbranch
+
+00002bd6 <.L240>:
+    2bd6:	80          	im 0
+    2bd7:	0b          	nop
+    2bd8:	90          	im 16
+    2bd9:	1a          	addsp 40
+    2bda:	0c          	store
+
+00002bdb <.L216>:
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+    2bdb:	74          	loadsp 16
+    2bdc:	83          	im 3
+    2bdd:	2e          	eq
+    2bde:	82          	im 2
+    2bdf:	e6          	im -26
+    2be0:	38          	neqbranch
+
+00002be1 <.LM294>:
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+    2be1:	74          	loadsp 16
+    2be2:	81          	im 1
+    2be3:	ca          	im -54
+    2be4:	38          	neqbranch
+
+00002be5 <.L241>:
+    2be5:	89          	im 9
+    2be6:	1a          	addsp 40
+    2be7:	57          	storesp 28
+
+00002be8 <.LM296>:
+    2be8:	90          	im 16
+    2be9:	19          	addsp 36
+    2bea:	08          	load
+    2beb:	80          	im 0
+    2bec:	2e          	eq
+    2bed:	81          	im 1
+    2bee:	a0          	im 32
+    2bef:	38          	neqbranch
+
+00002bf0 <.LM297>:
+    2bf0:	80          	im 0
+    2bf1:	56          	storesp 24
+
+00002bf2 <.L226>:
+    2bf2:	77          	loadsp 28
+    2bf3:	16          	addsp 24
+    2bf4:	70          	loadsp 0
+    2bf5:	33          	loadb
+    2bf6:	51          	storesp 4
+    2bf7:	55          	storesp 20
+
+00002bf8 <.LM299>:
+    2bf8:	74          	loadsp 16
+    2bf9:	a0          	im 32
+    2bfa:	2e          	eq
+    2bfb:	9b          	im 27
+    2bfc:	38          	neqbranch
+
+00002bfd <.LM300>:
+    2bfd:	74          	loadsp 16
+    2bfe:	85          	im 5
+    2bff:	2e          	eq
+    2c00:	82          	im 2
+    2c01:	a9          	im 41
+    2c02:	38          	neqbranch
+
+00002c03 <.LM301>:
+    2c03:	74          	loadsp 16
+    2c04:	77          	loadsp 28
+    2c05:	70          	loadsp 0
+    2c06:	81          	im 1
+    2c07:	05          	add
+    2c08:	59          	storesp 36
+    2c09:	34          	storeb
+
+00002c0a <.LM302>:
+    2c0a:	81          	im 1
+    2c0b:	16          	addsp 24
+    2c0c:	70          	loadsp 0
+    2c0d:	81          	im 1
+    2c0e:	ff          	im -1
+    2c0f:	06          	and
+    2c10:	57          	storesp 28
+    2c11:	55          	storesp 20
+    2c12:	87          	im 7
+    2c13:	76          	loadsp 24
+    2c14:	27          	ulessthanorequal
+    2c15:	dc          	im -36
+    2c16:	38          	neqbranch
+
+00002c17 <.L222>:
+    2c17:	88          	im 8
+    2c18:	18          	addsp 32
+    2c19:	33          	loadb
+    2c1a:	55          	storesp 20
+    2c1b:	74          	loadsp 16
+    2c1c:	a0          	im 32
+    2c1d:	2e          	eq
+    2c1e:	a9          	im 41
+    2c1f:	38          	neqbranch
+
+00002c20 <.LM304>:
+    2c20:	ae          	im 46
+    2c21:	77          	loadsp 28
+    2c22:	70          	loadsp 0
+    2c23:	81          	im 1
+    2c24:	05          	add
+    2c25:	59          	storesp 36
+    2c26:	34          	storeb
+
+00002c27 <.LM305>:
+    2c27:	88          	im 8
+    2c28:	56          	storesp 24
+
+00002c29 <.L232>:
+    2c29:	77          	loadsp 28
+    2c2a:	16          	addsp 24
+    2c2b:	70          	loadsp 0
+    2c2c:	33          	loadb
+    2c2d:	51          	storesp 4
+    2c2e:	55          	storesp 20
+
+00002c2f <.LM307>:
+    2c2f:	74          	loadsp 16
+    2c30:	a0          	im 32
+    2c31:	2e          	eq
+    2c32:	95          	im 21
+    2c33:	38          	neqbranch
+
+00002c34 <.LM308>:
+    2c34:	74          	loadsp 16
+    2c35:	77          	loadsp 28
+    2c36:	70          	loadsp 0
+    2c37:	81          	im 1
+    2c38:	05          	add
+    2c39:	59          	storesp 36
+    2c3a:	34          	storeb
+
+00002c3b <.LM309>:
+    2c3b:	81          	im 1
+    2c3c:	16          	addsp 24
+    2c3d:	70          	loadsp 0
+    2c3e:	81          	im 1
+    2c3f:	ff          	im -1
+    2c40:	06          	and
+    2c41:	57          	storesp 28
+    2c42:	55          	storesp 20
+    2c43:	8a          	im 10
+    2c44:	76          	loadsp 24
+    2c45:	27          	ulessthanorequal
+    2c46:	e2          	im -30
+    2c47:	38          	neqbranch
+
+00002c48 <.L227>:
+    2c48:	8b          	im 11
+    2c49:	18          	addsp 32
+    2c4a:	33          	loadb
+    2c4b:	88          	im 8
+    2c4c:	1b          	addsp 44
+    2c4d:	34          	storeb
+
+00002c4e <.LM311>:
+    2c4e:	9f          	im 31
+    2c4f:	18          	addsp 32
+    2c50:	33          	loadb
+    2c51:	9e          	im 30
+    2c52:	19          	addsp 36
+    2c53:	33          	loadb
+    2c54:	71          	loadsp 4
+    2c55:	98          	im 24
+    2c56:	2b          	ashiftleft
+    2c57:	71          	loadsp 4
+    2c58:	90          	im 16
+    2c59:	2b          	ashiftleft
+    2c5a:	07          	or
+    2c5b:	9d          	im 29
+    2c5c:	1b          	addsp 44
+    2c5d:	33          	loadb
+    2c5e:	70          	loadsp 0
+    2c5f:	88          	im 8
+    2c60:	2b          	ashiftleft
+    2c61:	72          	loadsp 8
+    2c62:	07          	or
+    2c63:	9c          	im 28
+    2c64:	1d          	addsp 52
+    2c65:	33          	loadb
+    2c66:	71          	loadsp 4
+    2c67:	07          	or
+    2c68:	7f          	loadsp 60
+    2c69:	0c          	store
+    2c6a:	52          	storesp 8
+
+00002c6b <.LM312>:
+    2c6b:	99          	im 25
+    2c6c:	1c          	addsp 48
+    2c6d:	33          	loadb
+    2c6e:	98          	im 24
+    2c6f:	1d          	addsp 52
+    2c70:	33          	loadb
+    2c71:	71          	loadsp 4
+    2c72:	88          	im 8
+    2c73:	2b          	ashiftleft
+    2c74:	07          	or
+    2c75:	53          	storesp 12
+    2c76:	51          	storesp 4
+    2c77:	53          	storesp 12
+    2c78:	57          	storesp 28
+    2c79:	5c          	storesp 48
+    2c7a:	56          	storesp 24
+    2c7b:	74          	loadsp 16
+    2c7c:	84          	im 4
+    2c7d:	1b          	addsp 44
+    2c7e:	23          	storeh
+
+00002c7f <.LM313>:
+    2c7f:	97          	im 23
+    2c80:	18          	addsp 32
+    2c81:	33          	loadb
+    2c82:	96          	im 22
+    2c83:	19          	addsp 36
+    2c84:	33          	loadb
+    2c85:	71          	loadsp 4
+    2c86:	88          	im 8
+    2c87:	2b          	ashiftleft
+    2c88:	07          	or
+    2c89:	56          	storesp 24
+    2c8a:	56          	storesp 24
+    2c8b:	74          	loadsp 16
+    2c8c:	86          	im 6
+    2c8d:	1b          	addsp 44
+    2c8e:	23          	storeh
+
+00002c8f <.L220>:
+    2c8f:	80          	im 0
+    2c90:	77          	loadsp 28
+    2c91:	34          	storeb
+
+00002c92 <.LBE26>:
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+    2c92:	78          	loadsp 32
+    2c93:	51          	storesp 4
+    2c94:	eb          	im -21
+    2c95:	e3          	im -29
+    2c96:	3f          	callpcrel
+    2c97:	83          	im 3
+    2c98:	e0          	im -32
+    2c99:	80          	im 0
+    2c9a:	08          	load
+    2c9b:	55          	storesp 20
+
+00002c9c <.LM316>:
+				if (res == FR_NO_FILE) {
+    2c9c:	83          	im 3
+    2c9d:	e0          	im -32
+    2c9e:	80          	im 0
+    2c9f:	08          	load
+    2ca0:	83          	im 3
+    2ca1:	2e          	eq
+    2ca2:	09          	not
+    2ca3:	81          	im 1
+    2ca4:	06          	and
+    2ca5:	88          	im 8
+    2ca6:	38          	neqbranch
+
+00002ca7 <.LM317>:
+					dj->sect = 0;
+    2ca7:	80          	im 0
+    2ca8:	0b          	nop
+    2ca9:	90          	im 16
+    2caa:	1a          	addsp 40
+    2cab:	0c          	store
+
+00002cac <.LM318>:
+					res = FR_OK;
+    2cac:	80          	im 0
+    2cad:	55          	storesp 20
+
+00002cae <.L203>:
+				}
+			}
+		}
+	}
+
+	return res;
+}
+    2cae:	74          	loadsp 16
+    2caf:	83          	im 3
+    2cb0:	e0          	im -32
+    2cb1:	80          	im 0
+    2cb2:	0c          	store
+    2cb3:	97          	im 23
+    2cb4:	3d          	pushspadd
+    2cb5:	0d          	popsp
+    2cb6:	04          	poppc
+
+00002cb7 <.L211>:
+    2cb7:	78          	loadsp 32
+    2cb8:	51          	storesp 4
+    2cb9:	eb          	im -21
+    2cba:	be          	im 62
+    2cbb:	3f          	callpcrel
+    2cbc:	83          	im 3
+    2cbd:	e0          	im -32
+    2cbe:	80          	im 0
+    2cbf:	08          	load
+    2cc0:	55          	storesp 20
+
+00002cc1 <.LM321>:
+    2cc1:	83          	im 3
+    2cc2:	e0          	im -32
+    2cc3:	80          	im 0
+    2cc4:	08          	load
+    2cc5:	fe          	im -2
+    2cc6:	8f          	im 15
+    2cc7:	38          	neqbranch
+    2cc8:	90          	im 16
+    2cc9:	19          	addsp 36
+    2cca:	08          	load
+    2ccb:	80          	im 0
+    2ccc:	2e          	eq
+    2ccd:	fe          	im -2
+    2cce:	8c          	im 12
+    2ccf:	38          	neqbranch
+
+00002cd0 <.L215>:
+    2cd0:	a0          	im 32
+    2cd1:	54          	storesp 16
+    2cd2:	78          	loadsp 32
+    2cd3:	22          	loadh
+    2cd4:	70          	loadsp 0
+    2cd5:	85          	im 5
+    2cd6:	2b          	ashiftleft
+    2cd7:	83          	im 3
+    2cd8:	e0          	im -32
+    2cd9:	06          	and
+    2cda:	54          	storesp 16
+    2cdb:	56          	storesp 24
+    2cdc:	90          	im 16
+    2cdd:	19          	addsp 36
+    2cde:	08          	load
+    2cdf:	52          	storesp 8
+    2ce0:	77          	loadsp 28
+    2ce1:	51          	storesp 4
+    2ce2:	d8          	im -40
+    2ce3:	9b          	im 27
+    2ce4:	3f          	callpcrel
+    2ce5:	83          	im 3
+    2ce6:	e0          	im -32
+    2ce7:	80          	im 0
+    2ce8:	08          	load
+    2ce9:	80          	im 0
+    2cea:	f4          	im -12
+    2ceb:	38          	neqbranch
+
+00002cec <.LM323>:
+    2cec:	77          	loadsp 28
+    2ced:	33          	loadb
+    2cee:	56          	storesp 24
+
+00002cef <.LM324>:
+    2cef:	75          	loadsp 20
+    2cf0:	80          	im 0
+    2cf1:	2e          	eq
+    2cf2:	80          	im 0
+    2cf3:	f5          	im -11
+    2cf4:	38          	neqbranch
+
+00002cf5 <.LM325>:
+    2cf5:	8b          	im 11
+    2cf6:	18          	addsp 32
+    2cf7:	33          	loadb
+    2cf8:	bf          	im 63
+    2cf9:	06          	and
+
+00002cfa <.LM326>:
+    2cfa:	76          	loadsp 24
+    2cfb:	81          	im 1
+    2cfc:	e5          	im -27
+    2cfd:	32          	xor
+    2cfe:	70          	loadsp 0
+    2cff:	30          	neg
+    2d00:	70          	loadsp 0
+    2d01:	9f          	im 31
+    2d02:	2a          	lshiftright
+    2d03:	51          	storesp 4
+    2d04:	51          	storesp 4
+    2d05:	56          	storesp 24
+    2d06:	57          	storesp 28
+    2d07:	75          	loadsp 20
+    2d08:	ae          	im 46
+    2d09:	2e          	eq
+    2d0a:	ff          	im -1
+    2d0b:	ab          	im 43
+    2d0c:	38          	neqbranch
+    2d0d:	74          	loadsp 16
+    2d0e:	80          	im 0
+    2d0f:	2e          	eq
+    2d10:	ff          	im -1
+    2d11:	a5          	im 37
+    2d12:	38          	neqbranch
+    2d13:	76          	loadsp 24
+    2d14:	83          	im 3
+    2d15:	2a          	lshiftright
+    2d16:	70          	loadsp 0
+    2d17:	81          	im 1
+    2d18:	06          	and
+    2d19:	51          	storesp 4
+    2d1a:	55          	storesp 20
+    2d1b:	74          	loadsp 16
+    2d1c:	ff          	im -1
+    2d1d:	99          	im 25
+    2d1e:	38          	neqbranch
+    2d1f:	83          	im 3
+    2d20:	e0          	im -32
+    2d21:	80          	im 0
+    2d22:	08          	load
+    2d23:	55          	storesp 20
+
+00002d24 <.LM327>:
+    2d24:	74          	loadsp 16
+    2d25:	ff          	im -1
+    2d26:	87          	im 7
+    2d27:	38          	neqbranch
+    2d28:	fd          	im -3
+    2d29:	bb          	im 59
+    2d2a:	39          	poppcrel
+
+00002d2b <.L247>:
+    2d2b:	81          	im 1
+    2d2c:	e5          	im -27
+    2d2d:	55          	storesp 20
+
+00002d2e <.LM329>:
+    2d2e:	74          	loadsp 16
+    2d2f:	77          	loadsp 28
+    2d30:	70          	loadsp 0
+    2d31:	81          	im 1
+    2d32:	05          	add
+    2d33:	59          	storesp 36
+    2d34:	34          	storeb
+
+00002d35 <.LM330>:
+    2d35:	81          	im 1
+    2d36:	16          	addsp 24
+    2d37:	70          	loadsp 0
+    2d38:	81          	im 1
+    2d39:	ff          	im -1
+    2d3a:	06          	and
+    2d3b:	57          	storesp 28
+    2d3c:	55          	storesp 20
+    2d3d:	87          	im 7
+    2d3e:	76          	loadsp 24
+    2d3f:	27          	ulessthanorequal
+    2d40:	fd          	im -3
+    2d41:	b0          	im 48
+    2d42:	38          	neqbranch
+    2d43:	fd          	im -3
+    2d44:	d2          	im -46
+    2d45:	39          	poppcrel
+
+00002d46 <.L246>:
+    2d46:	80          	im 0
+    2d47:	0b          	nop
+    2d48:	90          	im 16
+    2d49:	1a          	addsp 40
+    2d4a:	0c          	store
+    2d4b:	fd          	im -3
+    2d4c:	98          	im 24
+    2d4d:	39          	poppcrel
+
+00002d4e <.L245>:
+    2d4e:	78          	loadsp 32
+    2d4f:	51          	storesp 4
+    2d50:	e9          	im -23
+    2d51:	c4          	im -60
+    2d52:	3f          	callpcrel
+    2d53:	83          	im 3
+    2d54:	e0          	im -32
+    2d55:	80          	im 0
+    2d56:	08          	load
+
+00002d57 <.LM333>:
+    2d57:	83          	im 3
+    2d58:	e0          	im -32
+    2d59:	80          	im 0
+    2d5a:	0c          	store
+    2d5b:	97          	im 23
+    2d5c:	3d          	pushspadd
+    2d5d:	0d          	popsp
+    2d5e:	04          	poppc
+
+00002d5f <.L238>:
+    2d5f:	81          	im 1
+    2d60:	55          	storesp 20
+
+00002d61 <.LM335>:
+    2d61:	80          	im 0
+    2d62:	0b          	nop
+    2d63:	90          	im 16
+    2d64:	1a          	addsp 40
+    2d65:	0c          	store
+    2d66:	fc          	im -4
+    2d67:	f3          	im -13
+    2d68:	39          	poppcrel
+
+00002d69 <.L239>:
+    2d69:	83          	im 3
+    2d6a:	55          	storesp 20
+
+00002d6b <.LM337>:
+    2d6b:	80          	im 0
+    2d6c:	0b          	nop
+    2d6d:	90          	im 16
+    2d6e:	1a          	addsp 40
+    2d6f:	0c          	store
+    2d70:	fc          	im -4
+    2d71:	e9          	im -23
+    2d72:	39          	poppcrel
+
+00002d73 <mmcInit>:
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+    2d73:	80          	im 0
+    2d74:	3d          	pushspadd
+    2d75:	0d          	popsp
+
+00002d76 <.LM2>:
+	// initialize SPI interface
+	spiInit();
+    2d76:	85          	im 5
+    2d77:	db          	im -37
+    2d78:	3f          	callpcrel
+
+00002d79 <.LM3>:
+	// release chip select
+	mmcChipSelect(0);
+    2d79:	80          	im 0
+    2d7a:	51          	storesp 4
+    2d7b:	85          	im 5
+    2d7c:	f0          	im -16
+    2d7d:	3f          	callpcrel
+    2d7e:	82          	im 2
+    2d7f:	3d          	pushspadd
+    2d80:	0d          	popsp
+    2d81:	04          	poppc
+
+00002d82 <mmcReadLoop>:
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+    2d82:	ff          	im -1
+    2d83:	3d          	pushspadd
+    2d84:	0d          	popsp
+
+00002d85 <.LM5>:
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+    2d85:	83          	im 3
+    2d86:	e3          	im -29
+    2d87:	e8          	im -24
+    2d88:	52          	storesp 8
+
+00002d89 <.LM6>:
+
+	i=0x80;	//512
+    2d89:	81          	im 1
+    2d8a:	80          	im 0
+    2d8b:	51          	storesp 4
+
+00002d8c <.L3>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2d8c:	86          	im 6
+    2d8d:	d0          	im -48
+    2d8e:	3f          	callpcrel
+    2d8f:	83          	im 3
+    2d90:	e0          	im -32
+    2d91:	80          	im 0
+    2d92:	08          	load
+    2d93:	72          	loadsp 8
+    2d94:	70          	loadsp 0
+    2d95:	81          	im 1
+    2d96:	05          	add
+    2d97:	54          	storesp 16
+    2d98:	34          	storeb
+    2d99:	ff          	im -1
+    2d9a:	11          	addsp 4
+    2d9b:	70          	loadsp 0
+    2d9c:	83          	im 3
+    2d9d:	ff          	im -1
+    2d9e:	ff          	im -1
+    2d9f:	06          	and
+    2da0:	51          	storesp 4
+    2da1:	51          	storesp 4
+    2da2:	70          	loadsp 0
+    2da3:	e8          	im -24
+    2da4:	38          	neqbranch
+
+00002da5 <.LM8>:
+
+	//spiDisplay(1);
+	i=0x80;	//512
+    2da5:	81          	im 1
+    2da6:	80          	im 0
+    2da7:	51          	storesp 4
+
+00002da8 <.L6>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2da8:	86          	im 6
+    2da9:	b4          	im 52
+    2daa:	3f          	callpcrel
+    2dab:	83          	im 3
+    2dac:	e0          	im -32
+    2dad:	80          	im 0
+    2dae:	08          	load
+    2daf:	72          	loadsp 8
+    2db0:	70          	loadsp 0
+    2db1:	81          	im 1
+    2db2:	05          	add
+    2db3:	54          	storesp 16
+    2db4:	34          	storeb
+    2db5:	ff          	im -1
+    2db6:	11          	addsp 4
+    2db7:	70          	loadsp 0
+    2db8:	83          	im 3
+    2db9:	ff          	im -1
+    2dba:	ff          	im -1
+    2dbb:	06          	and
+    2dbc:	51          	storesp 4
+    2dbd:	51          	storesp 4
+    2dbe:	70          	loadsp 0
+    2dbf:	e8          	im -24
+    2dc0:	38          	neqbranch
+
+00002dc1 <.LM10>:
+
+	i=0x80;	//512
+    2dc1:	81          	im 1
+    2dc2:	80          	im 0
+    2dc3:	51          	storesp 4
+
+00002dc4 <.L9>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2dc4:	86          	im 6
+    2dc5:	98          	im 24
+    2dc6:	3f          	callpcrel
+    2dc7:	83          	im 3
+    2dc8:	e0          	im -32
+    2dc9:	80          	im 0
+    2dca:	08          	load
+    2dcb:	72          	loadsp 8
+    2dcc:	70          	loadsp 0
+    2dcd:	81          	im 1
+    2dce:	05          	add
+    2dcf:	54          	storesp 16
+    2dd0:	34          	storeb
+    2dd1:	ff          	im -1
+    2dd2:	11          	addsp 4
+    2dd3:	70          	loadsp 0
+    2dd4:	83          	im 3
+    2dd5:	ff          	im -1
+    2dd6:	ff          	im -1
+    2dd7:	06          	and
+    2dd8:	51          	storesp 4
+    2dd9:	51          	storesp 4
+    2dda:	70          	loadsp 0
+    2ddb:	e8          	im -24
+    2ddc:	38          	neqbranch
+
+00002ddd <.LM12>:
+
+	i=0x80;	//512
+    2ddd:	81          	im 1
+    2dde:	80          	im 0
+    2ddf:	51          	storesp 4
+
+00002de0 <.L12>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2de0:	85          	im 5
+    2de1:	fc          	im -4
+    2de2:	3f          	callpcrel
+    2de3:	83          	im 3
+    2de4:	e0          	im -32
+    2de5:	80          	im 0
+    2de6:	08          	load
+    2de7:	72          	loadsp 8
+    2de8:	70          	loadsp 0
+    2de9:	81          	im 1
+    2dea:	05          	add
+    2deb:	54          	storesp 16
+    2dec:	34          	storeb
+    2ded:	ff          	im -1
+    2dee:	11          	addsp 4
+    2def:	70          	loadsp 0
+    2df0:	83          	im 3
+    2df1:	ff          	im -1
+    2df2:	ff          	im -1
+    2df3:	06          	and
+    2df4:	51          	storesp 4
+    2df5:	51          	storesp 4
+    2df6:	70          	loadsp 0
+    2df7:	e8          	im -24
+    2df8:	38          	neqbranch
+    2df9:	83          	im 3
+    2dfa:	3d          	pushspadd
+    2dfb:	0d          	popsp
+    2dfc:	04          	poppc
+
+00002dfd <mmcCommand>:
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+    2dfd:	fd          	im -3
+    2dfe:	3d          	pushspadd
+    2dff:	0d          	popsp
+    2e00:	76          	loadsp 24
+    2e01:	02          	pushsp
+    2e02:	84          	im 4
+    2e03:	05          	add
+    2e04:	97          	im 23
+    2e05:	05          	add
+    2e06:	33          	loadb
+    2e07:	53          	storesp 12
+    2e08:	53          	storesp 12
+
+00002e09 <.LM15>:
+	u08 r1;
+	u08 retry=0xff;	//255x
+    2e09:	81          	im 1
+    2e0a:	ff          	im -1
+    2e0b:	54          	storesp 16
+
+00002e0c <.LM16>:
+	//
+
+	spiTransferFF();
+    2e0c:	85          	im 5
+    2e0d:	d0          	im -48
+    2e0e:	3f          	callpcrel
+
+00002e0f <.LM17>:
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+    2e0f:	85          	im 5
+    2e10:	cd          	im -51
+    2e11:	3f          	callpcrel
+
+00002e12 <.LM18>:
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+    2e12:	85          	im 5
+    2e13:	ca          	im -54
+    2e14:	3f          	callpcrel
+
+00002e15 <.LM19>:
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+    2e15:	85          	im 5
+    2e16:	c7          	im -57
+    2e17:	3f          	callpcrel
+
+00002e18 <.LM20>:
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+    2e18:	71          	loadsp 4
+    2e19:	80          	im 0
+    2e1a:	c0          	im -64
+    2e1b:	07          	or
+    2e1c:	51          	storesp 4
+    2e1d:	84          	im 4
+    2e1e:	e4          	im -28
+    2e1f:	3f          	callpcrel
+
+00002e20 <.LM21>:
+	//
+	spiTransferByte(arg>>24);
+    2e20:	72          	loadsp 8
+    2e21:	98          	im 24
+    2e22:	2a          	lshiftright
+    2e23:	51          	storesp 4
+    2e24:	84          	im 4
+    2e25:	dd          	im -35
+    2e26:	3f          	callpcrel
+
+00002e27 <.LM22>:
+	spiTransferByte(arg>>16);
+    2e27:	72          	loadsp 8
+    2e28:	90          	im 16
+    2e29:	2a          	lshiftright
+    2e2a:	70          	loadsp 0
+    2e2b:	81          	im 1
+    2e2c:	ff          	im -1
+    2e2d:	06          	and
+    2e2e:	52          	storesp 8
+    2e2f:	52          	storesp 8
+    2e30:	84          	im 4
+    2e31:	d1          	im -47
+    2e32:	3f          	callpcrel
+
+00002e33 <.LM23>:
+	spiTransferByte(arg>>8);
+    2e33:	72          	loadsp 8
+    2e34:	88          	im 8
+    2e35:	2a          	lshiftright
+    2e36:	70          	loadsp 0
+    2e37:	81          	im 1
+    2e38:	ff          	im -1
+    2e39:	06          	and
+    2e3a:	52          	storesp 8
+    2e3b:	52          	storesp 8
+    2e3c:	84          	im 4
+    2e3d:	c5          	im -59
+    2e3e:	3f          	callpcrel
+
+00002e3f <.LM24>:
+	spiTransferByte(arg);
+    2e3f:	72          	loadsp 8
+    2e40:	81          	im 1
+    2e41:	ff          	im -1
+    2e42:	06          	and
+    2e43:	51          	storesp 4
+    2e44:	84          	im 4
+    2e45:	bd          	im 61
+    2e46:	3f          	callpcrel
+
+00002e47 <.LM25>:
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+    2e47:	81          	im 1
+    2e48:	95          	im 21
+    2e49:	51          	storesp 4
+    2e4a:	84          	im 4
+    2e4b:	b7          	im 55
+    2e4c:	3f          	callpcrel
+
+00002e4d <.L17>:
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+    2e4d:	85          	im 5
+    2e4e:	8f          	im 15
+    2e4f:	3f          	callpcrel
+    2e50:	83          	im 3
+    2e51:	e0          	im -32
+    2e52:	80          	im 0
+    2e53:	08          	load
+    2e54:	81          	im 1
+    2e55:	ff          	im -1
+    2e56:	06          	and
+
+00002e57 <.LM27>:
+		retry--;
+    2e57:	ff          	im -1
+    2e58:	15          	addsp 20
+    2e59:	70          	loadsp 0
+    2e5a:	81          	im 1
+    2e5b:	ff          	im -1
+    2e5c:	06          	and
+
+00002e5d <.LM28>:
+	}
+    2e5d:	70          	loadsp 0
+    2e5e:	30          	neg
+    2e5f:	70          	loadsp 0
+    2e60:	9f          	im 31
+    2e61:	2a          	lshiftright
+    2e62:	51          	storesp 4
+    2e63:	52          	storesp 8
+    2e64:	56          	storesp 24
+    2e65:	53          	storesp 12
+    2e66:	53          	storesp 12
+    2e67:	72          	loadsp 8
+    2e68:	81          	im 1
+    2e69:	ff          	im -1
+    2e6a:	2e          	eq
+    2e6b:	09          	not
+    2e6c:	81          	im 1
+    2e6d:	06          	and
+    2e6e:	84          	im 4
+    2e6f:	38          	neqbranch
+    2e70:	71          	loadsp 4
+    2e71:	db          	im -37
+    2e72:	38          	neqbranch
+
+00002e73 <.L22>:
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
+    2e73:	72          	loadsp 8
+    2e74:	83          	im 3
+    2e75:	e0          	im -32
+    2e76:	80          	im 0
+    2e77:	0c          	store
+    2e78:	85          	im 5
+    2e79:	3d          	pushspadd
+    2e7a:	0d          	popsp
+    2e7b:	04          	poppc
+
+00002e7c <mmcRead>:
+    2e7c:	fd          	im -3
+    2e7d:	3d          	pushspadd
+    2e7e:	0d          	popsp
+
+00002e7f <.LM31>:
+    2e7f:	81          	im 1
+    2e80:	51          	storesp 4
+    2e81:	83          	im 3
+    2e82:	ea          	im -22
+    2e83:	3f          	callpcrel
+
+00002e84 <.LM32>:
+    2e84:	75          	loadsp 20
+    2e85:	89          	im 9
+    2e86:	2b          	ashiftleft
+    2e87:	52          	storesp 8
+    2e88:	91          	im 17
+    2e89:	51          	storesp 4
+    2e8a:	fe          	im -2
+    2e8b:	f1          	im -15
+    2e8c:	3f          	callpcrel
+    2e8d:	83          	im 3
+    2e8e:	e0          	im -32
+    2e8f:	80          	im 0
+    2e90:	08          	load
+    2e91:	81          	im 1
+    2e92:	ff          	im -1
+    2e93:	06          	and
+
+00002e94 <.LM33>:
+    2e94:	70          	loadsp 0
+    2e95:	55          	storesp 20
+    2e96:	53          	storesp 12
+    2e97:	72          	loadsp 8
+    2e98:	80          	im 0
+    2e99:	2e          	eq
+    2e9a:	8a          	im 10
+    2e9b:	38          	neqbranch
+
+00002e9c <.LM34>:
+    2e9c:	73          	loadsp 12
+    2e9d:	83          	im 3
+    2e9e:	e0          	im -32
+    2e9f:	80          	im 0
+    2ea0:	0c          	store
+    2ea1:	85          	im 5
+    2ea2:	3d          	pushspadd
+    2ea3:	0d          	popsp
+    2ea4:	04          	poppc
+
+00002ea5 <.L27>:
+    2ea5:	84          	im 4
+    2ea6:	b7          	im 55
+    2ea7:	3f          	callpcrel
+    2ea8:	83          	im 3
+    2ea9:	e0          	im -32
+    2eaa:	80          	im 0
+    2eab:	08          	load
+    2eac:	81          	im 1
+    2ead:	ff          	im -1
+    2eae:	06          	and
+    2eaf:	53          	storesp 12
+    2eb0:	72          	loadsp 8
+    2eb1:	81          	im 1
+    2eb2:	fe          	im -2
+    2eb3:	2e          	eq
+    2eb4:	09          	not
+    2eb5:	81          	im 1
+    2eb6:	06          	and
+    2eb7:	ed          	im -19
+    2eb8:	38          	neqbranch
+
+00002eb9 <.LM36>:
+    2eb9:	fd          	im -3
+    2eba:	c7          	im -57
+    2ebb:	3f          	callpcrel
+
+00002ebc <.LM37>:
+    2ebc:	84          	im 4
+    2ebd:	a0          	im 32
+    2ebe:	3f          	callpcrel
+
+00002ebf <.LM38>:
+    2ebf:	84          	im 4
+    2ec0:	9d          	im 29
+    2ec1:	3f          	callpcrel
+
+00002ec2 <.LM39>:
+    2ec2:	80          	im 0
+    2ec3:	51          	storesp 4
+    2ec4:	83          	im 3
+    2ec5:	a7          	im 39
+    2ec6:	3f          	callpcrel
+
+00002ec7 <.LM40>:
+    2ec7:	80          	im 0
+
+00002ec8 <.LM41>:
+    2ec8:	0b          	nop
+    2ec9:	83          	im 3
+    2eca:	e0          	im -32
+    2ecb:	80          	im 0
+    2ecc:	0c          	store
+    2ecd:	85          	im 5
+    2ece:	3d          	pushspadd
+    2ecf:	0d          	popsp
+    2ed0:	04          	poppc
+
+00002ed1 <mmcSendCommand>:
+    2ed1:	fe          	im -2
+    2ed2:	3d          	pushspadd
+    2ed3:	0d          	popsp
+    2ed4:	02          	pushsp
+    2ed5:	93          	im 19
+    2ed6:	05          	add
+    2ed7:	33          	loadb
+    2ed8:	53          	storesp 12
+
+00002ed9 <.LM43>:
+    2ed9:	81          	im 1
+    2eda:	51          	storesp 4
+    2edb:	83          	im 3
+    2edc:	90          	im 16
+    2edd:	3f          	callpcrel
+
+00002ede <.LM44>:
+    2ede:	75          	loadsp 20
+    2edf:	52          	storesp 8
+    2ee0:	72          	loadsp 8
+    2ee1:	51          	storesp 4
+    2ee2:	fe          	im -2
+    2ee3:	99          	im 25
+    2ee4:	3f          	callpcrel
+    2ee5:	83          	im 3
+    2ee6:	e0          	im -32
+    2ee7:	80          	im 0
+    2ee8:	08          	load
+    2ee9:	81          	im 1
+    2eea:	ff          	im -1
+    2eeb:	06          	and
+    2eec:	53          	storesp 12
+
+00002eed <.LM45>:
+    2eed:	80          	im 0
+    2eee:	51          	storesp 4
+    2eef:	82          	im 2
+    2ef0:	fc          	im -4
+    2ef1:	3f          	callpcrel
+
+00002ef2 <.LM46>:
+    2ef2:	72          	loadsp 8
+    2ef3:	83          	im 3
+    2ef4:	e0          	im -32
+    2ef5:	80          	im 0
+    2ef6:	0c          	store
+    2ef7:	84          	im 4
+    2ef8:	3d          	pushspadd
+    2ef9:	0d          	popsp
+    2efa:	04          	poppc
+
+00002efb <mmcReset>:
+    2efb:	fd          	im -3
+    2efc:	3d          	pushspadd
+    2efd:	0d          	popsp
+
+00002efe <.LM48>:
+    2efe:	81          	im 1
+    2eff:	ff          	im -1
+    2f00:	53          	storesp 12
+
+00002f01 <.L32>:
+    2f01:	83          	im 3
+    2f02:	db          	im -37
+    2f03:	3f          	callpcrel
+    2f04:	ff          	im -1
+    2f05:	13          	addsp 12
+    2f06:	70          	loadsp 0
+    2f07:	81          	im 1
+    2f08:	ff          	im -1
+    2f09:	06          	and
+    2f0a:	51          	storesp 4
+    2f0b:	53          	storesp 12
+    2f0c:	72          	loadsp 8
+    2f0d:	f3          	im -13
+    2f0e:	38          	neqbranch
+
+00002f0f <.LM50>:
+    2f0f:	72          	loadsp 8
+    2f10:	52          	storesp 8
+    2f11:	72          	loadsp 8
+    2f12:	51          	storesp 4
+    2f13:	ff          	im -1
+    2f14:	bc          	im 60
+    2f15:	3f          	callpcrel
+    2f16:	83          	im 3
+    2f17:	e0          	im -32
+    2f18:	80          	im 0
+    2f19:	08          	load
+    2f1a:	81          	im 1
+    2f1b:	ff          	im -1
+    2f1c:	06          	and
+    2f1d:	53          	storesp 12
+
+00002f1e <.LM51>:
+    2f1e:	81          	im 1
+    2f1f:	ff          	im -1
+    2f20:	54          	storesp 16
+    2f21:	72          	loadsp 8
+    2f22:	81          	im 1
+    2f23:	2e          	eq
+    2f24:	09          	not
+    2f25:	81          	im 1
+    2f26:	06          	and
+    2f27:	80          	im 0
+    2f28:	e2          	im -30
+    2f29:	38          	neqbranch
+
+00002f2a <.LM52>:
+    2f2a:	83          	im 3
+    2f2b:	ff          	im -1
+    2f2c:	ff          	im -1
+    2f2d:	54          	storesp 16
+
+00002f2e <.L36>:
+    2f2e:	80          	im 0
+    2f2f:	52          	storesp 8
+    2f30:	b7          	im 55
+    2f31:	51          	storesp 4
+    2f32:	ff          	im -1
+    2f33:	9d          	im 29
+    2f34:	3f          	callpcrel
+    2f35:	83          	im 3
+    2f36:	e0          	im -32
+    2f37:	80          	im 0
+    2f38:	08          	load
+    2f39:	81          	im 1
+    2f3a:	ff          	im -1
+    2f3b:	06          	and
+    2f3c:	53          	storesp 12
+
+00002f3d <.LM54>:
+    2f3d:	72          	loadsp 8
+    2f3e:	81          	im 1
+    2f3f:	2e          	eq
+    2f40:	09          	not
+    2f41:	81          	im 1
+    2f42:	06          	and
+    2f43:	a1          	im 33
+    2f44:	38          	neqbranch
+
+00002f45 <.LM55>:
+    2f45:	80          	im 0
+    2f46:	52          	storesp 8
+    2f47:	a9          	im 41
+    2f48:	51          	storesp 4
+    2f49:	ff          	im -1
+    2f4a:	86          	im 6
+    2f4b:	3f          	callpcrel
+    2f4c:	83          	im 3
+    2f4d:	e0          	im -32
+    2f4e:	80          	im 0
+    2f4f:	08          	load
+    2f50:	81          	im 1
+    2f51:	ff          	im -1
+    2f52:	06          	and
+    2f53:	53          	storesp 12
+
+00002f54 <.LM56>:
+    2f54:	72          	loadsp 8
+    2f55:	80          	im 0
+    2f56:	2e          	eq
+    2f57:	8d          	im 13
+    2f58:	38          	neqbranch
+
+00002f59 <.LM57>:
+    2f59:	ff          	im -1
+    2f5a:	14          	addsp 16
+    2f5b:	70          	loadsp 0
+    2f5c:	83          	im 3
+    2f5d:	ff          	im -1
+    2f5e:	ff          	im -1
+    2f5f:	06          	and
+    2f60:	55          	storesp 20
+    2f61:	53          	storesp 12
+
+00002f62 <.LM58>:
+    2f62:	73          	loadsp 12
+    2f63:	ca          	im -54
+    2f64:	38          	neqbranch
+
+00002f65 <.L37>:
+    2f65:	80          	im 0
+    2f66:	52          	storesp 8
+    2f67:	81          	im 1
+    2f68:	51          	storesp 4
+    2f69:	fe          	im -2
+    2f6a:	e6          	im -26
+    2f6b:	3f          	callpcrel
+    2f6c:	83          	im 3
+    2f6d:	e0          	im -32
+    2f6e:	80          	im 0
+    2f6f:	08          	load
+    2f70:	81          	im 1
+    2f71:	ff          	im -1
+    2f72:	06          	and
+    2f73:	53          	storesp 12
+
+00002f74 <.LM60>:
+    2f74:	81          	im 1
+    2f75:	ff          	im -1
+    2f76:	54          	storesp 16
+    2f77:	72          	loadsp 8
+    2f78:	92          	im 18
+    2f79:	38          	neqbranch
+
+00002f7a <.LM61>:
+    2f7a:	72          	loadsp 8
+    2f7b:	52          	storesp 8
+    2f7c:	bb          	im 59
+    2f7d:	51          	storesp 4
+    2f7e:	fe          	im -2
+    2f7f:	d1          	im -47
+    2f80:	3f          	callpcrel
+
+00002f81 <.LM62>:
+    2f81:	84          	im 4
+    2f82:	80          	im 0
+    2f83:	52          	storesp 8
+    2f84:	90          	im 16
+    2f85:	51          	storesp 4
+    2f86:	fe          	im -2
+    2f87:	c9          	im -55
+    2f88:	3f          	callpcrel
+
+00002f89 <.LM63>:
+    2f89:	72          	loadsp 8
+    2f8a:	54          	storesp 16
+
+00002f8b <.L31>:
+    2f8b:	73          	loadsp 12
+    2f8c:	83          	im 3
+    2f8d:	e0          	im -32
+    2f8e:	80          	im 0
+    2f8f:	0c          	store
+    2f90:	85          	im 5
+    2f91:	3d          	pushspadd
+    2f92:	0d          	popsp
+    2f93:	04          	poppc
+
+00002f94 <mmcWrite>:
+    2f94:	fb          	im -5
+    2f95:	3d          	pushspadd
+    2f96:	0d          	popsp
+
+00002f97 <.LM66>:
+    2f97:	83          	im 3
+    2f98:	e3          	im -29
+    2f99:	e8          	im -24
+    2f9a:	56          	storesp 24
+
+00002f9b <.LM67>:
+    2f9b:	81          	im 1
+    2f9c:	51          	storesp 4
+    2f9d:	81          	im 1
+    2f9e:	ce          	im -50
+    2f9f:	3f          	callpcrel
+
+00002fa0 <.LM68>:
+    2fa0:	77          	loadsp 28
+    2fa1:	89          	im 9
+    2fa2:	2b          	ashiftleft
+    2fa3:	52          	storesp 8
+    2fa4:	98          	im 24
+    2fa5:	51          	storesp 4
+    2fa6:	fc          	im -4
+    2fa7:	d5          	im -43
+    2fa8:	3f          	callpcrel
+    2fa9:	83          	im 3
+    2faa:	e0          	im -32
+    2fab:	80          	im 0
+    2fac:	08          	load
+    2fad:	81          	im 1
+    2fae:	ff          	im -1
+    2faf:	06          	and
+
+00002fb0 <.LM69>:
+    2fb0:	70          	loadsp 0
+    2fb1:	56          	storesp 24
+    2fb2:	54          	storesp 16
+
+00002fb3 <.LM70>:
+    2fb3:	73          	loadsp 12
+    2fb4:	80          	im 0
+    2fb5:	2e          	eq
+    2fb6:	8a          	im 10
+    2fb7:	38          	neqbranch
+
+00002fb8 <.L43>:
+    2fb8:	74          	loadsp 16
+    2fb9:	83          	im 3
+    2fba:	e0          	im -32
+    2fbb:	80          	im 0
+    2fbc:	0c          	store
+    2fbd:	87          	im 7
+    2fbe:	3d          	pushspadd
+    2fbf:	0d          	popsp
+    2fc0:	04          	poppc
+
+00002fc1 <.L52>:
+    2fc1:	82          	im 2
+    2fc2:	9b          	im 27
+    2fc3:	3f          	callpcrel
+
+00002fc4 <.LM73>:
+    2fc4:	81          	im 1
+    2fc5:	fe          	im -2
+    2fc6:	51          	storesp 4
+    2fc7:	81          	im 1
+    2fc8:	ba          	im 58
+    2fc9:	3f          	callpcrel
+
+00002fca <.LM74>:
+    2fca:	84          	im 4
+    2fcb:	80          	im 0
+    2fcc:	53          	storesp 12
+
+00002fcd <.L45>:
+    2fcd:	75          	loadsp 20
+    2fce:	70          	loadsp 0
+    2fcf:	81          	im 1
+    2fd0:	05          	add
+    2fd1:	57          	storesp 28
+    2fd2:	33          	loadb
+    2fd3:	51          	storesp 4
+    2fd4:	81          	im 1
+    2fd5:	ad          	im 45
+    2fd6:	3f          	callpcrel
+    2fd7:	ff          	im -1
+    2fd8:	13          	addsp 12
+    2fd9:	70          	loadsp 0
+    2fda:	83          	im 3
+    2fdb:	ff          	im -1
+    2fdc:	ff          	im -1
+    2fdd:	06          	and
+    2fde:	51          	storesp 4
+    2fdf:	53          	storesp 12
+    2fe0:	72          	loadsp 8
+    2fe1:	eb          	im -21
+    2fe2:	38          	neqbranch
+
+00002fe3 <.LM76>:
+    2fe3:	81          	im 1
+    2fe4:	f9          	im -7
+    2fe5:	3f          	callpcrel
+
+00002fe6 <.LM77>:
+    2fe6:	81          	im 1
+    2fe7:	f6          	im -10
+    2fe8:	3f          	callpcrel
+
+00002fe9 <.LM78>:
+    2fe9:	81          	im 1
+    2fea:	f3          	im -13
+    2feb:	3f          	callpcrel
+    2fec:	83          	im 3
+    2fed:	e0          	im -32
+    2fee:	80          	im 0
+    2fef:	08          	load
+    2ff0:	81          	im 1
+    2ff1:	ff          	im -1
+    2ff2:	06          	and
+
+00002ff3 <.LM79>:
+    2ff3:	70          	loadsp 0
+    2ff4:	9f          	im 31
+    2ff5:	06          	and
+
+00002ff6 <.LM80>:
+    2ff6:	54          	storesp 16
+    2ff7:	55          	storesp 20
+
+00002ff8 <.LM81>:
+    2ff8:	72          	loadsp 8
+    2ff9:	85          	im 5
+    2ffa:	2e          	eq
+    2ffb:	09          	not
+    2ffc:	81          	im 1
+    2ffd:	06          	and
+    2ffe:	ff          	im -1
+    2fff:	b8          	im 56
+    3000:	38          	neqbranch
+
+00003001 <.L49>:
+    3001:	81          	im 1
+    3002:	db          	im -37
+    3003:	3f          	callpcrel
+    3004:	83          	im 3
+    3005:	e0          	im -32
+    3006:	80          	im 0
+    3007:	08          	load
+    3008:	81          	im 1
+    3009:	ff          	im -1
+    300a:	06          	and
+    300b:	53          	storesp 12
+    300c:	72          	loadsp 8
+    300d:	80          	im 0
+    300e:	2e          	eq
+    300f:	f1          	im -15
+    3010:	38          	neqbranch
+
+00003011 <.LM83>:
+    3011:	80          	im 0
+    3012:	51          	storesp 4
+    3013:	80          	im 0
+    3014:	d8          	im -40
+    3015:	3f          	callpcrel
+
+00003016 <.LM84>:
+    3016:	80          	im 0
+
+00003017 <.LM85>:
+    3017:	0b          	nop
+    3018:	83          	im 3
+    3019:	e0          	im -32
+    301a:	80          	im 0
+    301b:	0c          	store
+    301c:	87          	im 7
+    301d:	3d          	pushspadd
+    301e:	0d          	popsp
+    301f:	04          	poppc
+
+00003020 <updateSpiState>:
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+    3020:	ff          	im -1
+    3021:	3d          	pushspadd
+    3022:	0d          	popsp
+
+00003023 <.LM2>:
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+    3023:	83          	im 3
+    3024:	e7          	im -25
+    3025:	f0          	im -16
+    3026:	08          	load
+    3027:	10          	addsp 0
+    3028:	83          	im 3
+    3029:	e7          	im -25
+    302a:	e8          	im -24
+    302b:	08          	load
+    302c:	07          	or
+    302d:	80          	im 0
+    302e:	fc          	im -4
+    302f:	a8          	im 40
+    3030:	08          	load
+    3031:	52          	storesp 8
+    3032:	71          	loadsp 4
+    3033:	0c          	store
+    3034:	83          	im 3
+    3035:	3d          	pushspadd
+    3036:	0d          	popsp
+    3037:	04          	poppc
+
+00003038 <setSpiFast>:
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+    3038:	80          	im 0
+    3039:	0b          	nop
+    303a:	83          	im 3
+    303b:	e7          	im -25
+    303c:	f0          	im -16
+    303d:	0c          	store
+
+0000303e <.LM5>:
+	updateSpiState();
+    303e:	e1          	im -31
+    303f:	3f          	callpcrel
+    3040:	04          	poppc
+
+00003041 <setSpiSlow>:
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+    3041:	81          	im 1
+    3042:	0b          	nop
+    3043:	83          	im 3
+    3044:	e7          	im -25
+    3045:	f0          	im -16
+    3046:	0c          	store
+
+00003047 <.LM8>:
+	updateSpiState();
+    3047:	d8          	im -40
+    3048:	3f          	callpcrel
+    3049:	04          	poppc
+
+0000304a <set_spi_clock_freq>:
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+    304a:	ed          	im -19
+    304b:	3f          	callpcrel
+    304c:	04          	poppc
+
+0000304d <spiDisplay>:
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+    304d:	71          	loadsp 4
+    304e:	83          	im 3
+    304f:	e7          	im -25
+    3050:	ec          	im -20
+    3051:	0c          	store
+    3052:	04          	poppc
+
+00003053 <spiInit>:
+    3053:	80          	im 0
+    3054:	3d          	pushspadd
+    3055:	0d          	popsp
+
+00003056 <.LM14>:
+    3056:	80          	im 0
+    3057:	51          	storesp 4
+    3058:	f4          	im -12
+    3059:	3f          	callpcrel
+
+0000305a <.LM15>:
+    305a:	81          	im 1
+    305b:	0b          	nop
+    305c:	83          	im 3
+    305d:	e7          	im -25
+    305e:	f0          	im -16
+    305f:	0c          	store
+
+00003060 <.LM16>:
+    3060:	81          	im 1
+    3061:	0b          	nop
+    3062:	83          	im 3
+    3063:	e7          	im -25
+    3064:	e8          	im -24
+    3065:	0c          	store
+
+00003066 <.LM17>:
+    3066:	ff          	im -1
+    3067:	b8          	im 56
+    3068:	3f          	callpcrel
+    3069:	82          	im 2
+    306a:	3d          	pushspadd
+    306b:	0d          	popsp
+    306c:	04          	poppc
+
+0000306d <mmcChipSelect>:
+    306d:	80          	im 0
+    306e:	3d          	pushspadd
+    306f:	0d          	popsp
+
+00003070 <.LM19>:
+    3070:	72          	loadsp 8
+    3071:	30          	neg
+    3072:	70          	loadsp 0
+    3073:	74          	loadsp 16
+    3074:	07          	or
+    3075:	80          	im 0
+    3076:	25          	lessthanorequal
+    3077:	83          	im 3
+    3078:	e7          	im -25
+    3079:	e8          	im -24
+    307a:	0c          	store
+    307b:	51          	storesp 4
+
+0000307c <.LM20>:
+    307c:	ff          	im -1
+    307d:	a2          	im 34
+    307e:	3f          	callpcrel
+    307f:	82          	im 2
+    3080:	3d          	pushspadd
+    3081:	0d          	popsp
+    3082:	04          	poppc
+
+00003083 <spiTransferByte>:
+    3083:	fd          	im -3
+    3084:	3d          	pushspadd
+    3085:	0d          	popsp
+    3086:	02          	pushsp
+    3087:	97          	im 23
+    3088:	05          	add
+    3089:	33          	loadb
+
+0000308a <.LM22>:
+    308a:	80          	im 0
+    308b:	fc          	im -4
+    308c:	ac          	im 44
+    308d:	08          	load
+    308e:	55          	storesp 20
+    308f:	74          	loadsp 16
+    3090:	0c          	store
+    3091:	80          	im 0
+    3092:	fc          	im -4
+    3093:	a8          	im 40
+    3094:	08          	load
+    3095:	53          	storesp 12
+
+00003096 <.L10>:
+    3096:	72          	loadsp 8
+    3097:	08          	load
+    3098:	70          	loadsp 0
+    3099:	81          	im 1
+    309a:	06          	and
+    309b:	51          	storesp 4
+    309c:	52          	storesp 8
+    309d:	71          	loadsp 4
+    309e:	f7          	im -9
+    309f:	38          	neqbranch
+
+000030a0 <.LM24>:
+    30a0:	73          	loadsp 12
+    30a1:	08          	load
+    30a2:	70          	loadsp 0
+    30a3:	81          	im 1
+    30a4:	ff          	im -1
+    30a5:	06          	and
+    30a6:	51          	storesp 4
+    30a7:	52          	storesp 8
+
+000030a8 <.LM25>:
+    30a8:	83          	im 3
+    30a9:	e7          	im -25
+    30aa:	ec          	im -20
+    30ab:	08          	load
+    30ac:	8a          	im 10
+    30ad:	38          	neqbranch
+
+000030ae <.LM26>:
+    30ae:	71          	loadsp 4
+    30af:	83          	im 3
+    30b0:	e0          	im -32
+    30b1:	80          	im 0
+    30b2:	0c          	store
+    30b3:	85          	im 5
+    30b4:	3d          	pushspadd
+    30b5:	0d          	popsp
+    30b6:	04          	poppc
+
+000030b7 <.L14>:
+    30b7:	71          	loadsp 4
+    30b8:	84          	im 4
+    30b9:	2a          	lshiftright
+    30ba:	51          	storesp 4
+    30bb:	85          	im 5
+    30bc:	fa          	im -6
+    30bd:	3f          	callpcrel
+    30be:	83          	im 3
+    30bf:	e0          	im -32
+    30c0:	80          	im 0
+    30c1:	08          	load
+    30c2:	51          	storesp 4
+    30c3:	87          	im 7
+    30c4:	85          	im 5
+    30c5:	3f          	callpcrel
+
+000030c6 <.LM28>:
+    30c6:	71          	loadsp 4
+    30c7:	8f          	im 15
+    30c8:	06          	and
+    30c9:	51          	storesp 4
+    30ca:	85          	im 5
+    30cb:	eb          	im -21
+    30cc:	3f          	callpcrel
+    30cd:	83          	im 3
+    30ce:	e0          	im -32
+    30cf:	80          	im 0
+    30d0:	08          	load
+    30d1:	51          	storesp 4
+    30d2:	86          	im 6
+    30d3:	f6          	im -10
+    30d4:	3f          	callpcrel
+
+000030d5 <.LBE2>:
+    30d5:	71          	loadsp 4
+    30d6:	83          	im 3
+    30d7:	e0          	im -32
+    30d8:	80          	im 0
+    30d9:	0c          	store
+    30da:	85          	im 5
+    30db:	3d          	pushspadd
+    30dc:	0d          	popsp
+    30dd:	04          	poppc
+
+000030de <spiTransferFF>:
+    30de:	80          	im 0
+    30df:	3d          	pushspadd
+    30e0:	0d          	popsp
+
+000030e1 <.LM31>:
+    30e1:	81          	im 1
+    30e2:	ff          	im -1
+    30e3:	51          	storesp 4
+    30e4:	ff          	im -1
+    30e5:	9d          	im 29
+    30e6:	3f          	callpcrel
+    30e7:	83          	im 3
+    30e8:	e0          	im -32
+    30e9:	80          	im 0
+    30ea:	08          	load
+    30eb:	81          	im 1
+    30ec:	ff          	im -1
+    30ed:	06          	and
+    30ee:	83          	im 3
+    30ef:	e0          	im -32
+    30f0:	80          	im 0
+    30f1:	0c          	store
+
+000030f2 <.LM32>:
+    30f2:	82          	im 2
+    30f3:	3d          	pushspadd
+    30f4:	0d          	popsp
+    30f5:	04          	poppc
+
+000030f6 <USART_Data_Needed>:
+
+void actions();
+
+int USART_Data_Needed()
+{
+    30f6:	fe          	im -2
+    30f7:	3d          	pushspadd
+    30f8:	0d          	popsp
+
+000030f9 <.LM2>:
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+    30f9:	80          	im 0
+    30fa:	fb          	im -5
+    30fb:	ec          	im -20
+    30fc:	08          	load
+    30fd:	70          	loadsp 0
+    30fe:	33          	loadb
+    30ff:	70          	loadsp 0
+    3100:	81          	im 1
+    3101:	ff          	im -1
+    3102:	06          	and
+    3103:	70          	loadsp 0
+    3104:	84          	im 4
+    3105:	2a          	lshiftright
+    3106:	81          	im 1
+    3107:	32          	xor
+    3108:	81          	im 1
+    3109:	06          	and
+    310a:	55          	storesp 20
+    310b:	51          	storesp 4
+    310c:	52          	storesp 8
+    310d:	53          	storesp 12
+
+0000310e <.LM3>:
+	if (needed)
+    310e:	71          	loadsp 4
+    310f:	80          	im 0
+    3110:	2e          	eq
+    3111:	8c          	im 12
+    3112:	38          	neqbranch
+
+00003113 <.LM4>:
+	{
+		*zpu_pokey_irqen = 0x28;
+    3113:	a8          	im 40
+    3114:	73          	loadsp 12
+    3115:	34          	storeb
+
+00003116 <.LM5>:
+		*zpu_pokey_irqen = 0x38;
+    3116:	80          	im 0
+    3117:	fb          	im -5
+    3118:	ec          	im -20
+    3119:	08          	load
+    311a:	51          	storesp 4
+    311b:	b8          	im 56
+    311c:	71          	loadsp 4
+    311d:	34          	storeb
+
+0000311e <.L2>:
+	}
+	return needed;
+}
+    311e:	71          	loadsp 4
+    311f:	83          	im 3
+    3120:	e0          	im -32
+    3121:	80          	im 0
+    3122:	0c          	store
+    3123:	84          	im 4
+    3124:	3d          	pushspadd
+    3125:	0d          	popsp
+    3126:	04          	poppc
+
+00003127 <USART_Data_Ready>:
+
+int USART_Data_Ready()
+{
+    3127:	fe          	im -2
+    3128:	3d          	pushspadd
+    3129:	0d          	popsp
+
+0000312a <.LM8>:
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+    312a:	80          	im 0
+    312b:	fb          	im -5
+    312c:	ec          	im -20
+    312d:	08          	load
+    312e:	70          	loadsp 0
+    312f:	33          	loadb
+    3130:	70          	loadsp 0
+    3131:	81          	im 1
+    3132:	ff          	im -1
+    3133:	06          	and
+    3134:	70          	loadsp 0
+    3135:	85          	im 5
+    3136:	2a          	lshiftright
+    3137:	81          	im 1
+    3138:	32          	xor
+    3139:	81          	im 1
+    313a:	06          	and
+    313b:	55          	storesp 20
+    313c:	51          	storesp 4
+    313d:	52          	storesp 8
+    313e:	53          	storesp 12
+
+0000313f <.LM9>:
+	if (ready)
+    313f:	71          	loadsp 4
+    3140:	80          	im 0
+    3141:	2e          	eq
+    3142:	8c          	im 12
+    3143:	38          	neqbranch
+
+00003144 <.LM10>:
+	{
+		*zpu_pokey_irqen = 0x18;
+    3144:	98          	im 24
+    3145:	73          	loadsp 12
+    3146:	34          	storeb
+
+00003147 <.LM11>:
+		*zpu_pokey_irqen = 0x38;
+    3147:	80          	im 0
+    3148:	fb          	im -5
+    3149:	ec          	im -20
+    314a:	08          	load
+    314b:	51          	storesp 4
+    314c:	b8          	im 56
+    314d:	71          	loadsp 4
+    314e:	34          	storeb
+
+0000314f <.L5>:
+	}
+	return ready;
+}
+    314f:	71          	loadsp 4
+    3150:	83          	im 3
+    3151:	e0          	im -32
+    3152:	80          	im 0
+    3153:	0c          	store
+    3154:	84          	im 4
+    3155:	3d          	pushspadd
+    3156:	0d          	popsp
+    3157:	04          	poppc
+
+00003158 <USART_Receive_Mode>:
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+    3158:	80          	im 0
+    3159:	3d          	pushspadd
+    315a:	0d          	popsp
+
+0000315b <.LM14>:
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+    315b:	80          	im 0
+    315c:	fb          	im -5
+    315d:	e8          	im -24
+    315e:	08          	load
+    315f:	51          	storesp 4
+    3160:	93          	im 19
+    3161:	71          	loadsp 4
+    3162:	34          	storeb
+
+00003163 <.LM15>:
+	*zpu_pokey_skrest = 0xff;
+    3163:	80          	im 0
+    3164:	fb          	im -5
+    3165:	f4          	im -12
+    3166:	08          	load
+    3167:	51          	storesp 4
+    3168:	ff          	im -1
+    3169:	71          	loadsp 4
+    316a:	34          	storeb
+    316b:	82          	im 2
+    316c:	3d          	pushspadd
+    316d:	0d          	popsp
+    316e:	04          	poppc
+
+0000316f <USART_Init>:
+    316f:	fe          	im -2
+    3170:	3d          	pushspadd
+    3171:	0d          	popsp
+    3172:	02          	pushsp
+    3173:	93          	im 19
+    3174:	05          	add
+    3175:	33          	loadb
+
+00003176 <.LM17>:
+    3176:	80          	im 0
+    3177:	fb          	im -5
+    3178:	e8          	im -24
+    3179:	08          	load
+    317a:	53          	storesp 12
+    317b:	53          	storesp 12
+    317c:	80          	im 0
+    317d:	72          	loadsp 8
+    317e:	34          	storeb
+
+0000317f <.LM18>:
+    317f:	8a          	im 10
+    3180:	51          	storesp 4
+    3181:	ff          	im -1
+    3182:	a6          	im 38
+    3183:	af          	im 47
+    3184:	3f          	callpcrel
+
+00003185 <.LM19>:
+    3185:	d2          	im -46
+    3186:	3f          	callpcrel
+
+00003187 <.LM20>:
+    3187:	80          	im 0
+    3188:	fb          	im -5
+    3189:	f8          	im -8
+    318a:	08          	load
+    318b:	52          	storesp 8
+    318c:	80          	im 0
+    318d:	f8          	im -8
+    318e:	72          	loadsp 8
+    318f:	34          	storeb
+
+00003190 <.LM21>:
+    3190:	80          	im 0
+    3191:	fc          	im -4
+    3192:	90          	im 16
+    3193:	08          	load
+    3194:	52          	storesp 8
+    3195:	80          	im 0
+    3196:	72          	loadsp 8
+    3197:	34          	storeb
+
+00003198 <.LM22>:
+    3198:	fa          	im -6
+    3199:	13          	addsp 12
+    319a:	80          	im 0
+    319b:	fc          	im -4
+    319c:	98          	im 24
+    319d:	08          	load
+    319e:	53          	storesp 12
+    319f:	53          	storesp 12
+    31a0:	72          	loadsp 8
+    31a1:	72          	loadsp 8
+    31a2:	34          	storeb
+
+000031a3 <.LM23>:
+    31a3:	80          	im 0
+    31a4:	fc          	im -4
+    31a5:	80          	im 0
+    31a6:	08          	load
+    31a7:	52          	storesp 8
+    31a8:	80          	im 0
+    31a9:	72          	loadsp 8
+    31aa:	34          	storeb
+
+000031ab <.LM24>:
+    31ab:	80          	im 0
+    31ac:	fc          	im -4
+    31ad:	88          	im 8
+    31ae:	08          	load
+    31af:	52          	storesp 8
+    31b0:	72          	loadsp 8
+    31b1:	72          	loadsp 8
+    31b2:	34          	storeb
+
+000031b3 <.LM25>:
+    31b3:	80          	im 0
+    31b4:	fb          	im -5
+    31b5:	ec          	im -20
+    31b6:	08          	load
+    31b7:	52          	storesp 8
+    31b8:	80          	im 0
+    31b9:	72          	loadsp 8
+    31ba:	34          	storeb
+
+000031bb <.LM26>:
+    31bb:	80          	im 0
+    31bc:	fb          	im -5
+    31bd:	ec          	im -20
+    31be:	08          	load
+    31bf:	52          	storesp 8
+    31c0:	b8          	im 56
+    31c1:	72          	loadsp 8
+    31c2:	34          	storeb
+    31c3:	84          	im 4
+    31c4:	3d          	pushspadd
+    31c5:	0d          	popsp
+    31c6:	04          	poppc
+
+000031c7 <USART_Transmit_Byte>:
+    31c7:	ff          	im -1
+    31c8:	3d          	pushspadd
+    31c9:	0d          	popsp
+    31ca:	02          	pushsp
+    31cb:	8f          	im 15
+    31cc:	05          	add
+    31cd:	33          	loadb
+
+000031ce <.LM28>:
+    31ce:	80          	im 0
+    31cf:	fb          	im -5
+    31d0:	f0          	im -16
+    31d1:	08          	load
+    31d2:	52          	storesp 8
+    31d3:	52          	storesp 8
+    31d4:	71          	loadsp 4
+    31d5:	71          	loadsp 4
+    31d6:	34          	storeb
+
+000031d7 <.L10>:
+    31d7:	fe          	im -2
+    31d8:	9d          	im 29
+    31d9:	3f          	callpcrel
+    31da:	83          	im 3
+    31db:	e0          	im -32
+    31dc:	80          	im 0
+    31dd:	08          	load
+    31de:	80          	im 0
+    31df:	2e          	eq
+    31e0:	f6          	im -10
+    31e1:	38          	neqbranch
+    31e2:	83          	im 3
+    31e3:	3d          	pushspadd
+    31e4:	0d          	popsp
+    31e5:	04          	poppc
+
+000031e6 <USART_Receive_Byte>:
+    31e6:	80          	im 0
+    31e7:	3d          	pushspadd
+    31e8:	0d          	popsp
+
+000031e9 <.LM31>:
+    31e9:	fe          	im -2
+    31ea:	bc          	im 60
+    31eb:	3f          	callpcrel
+    31ec:	83          	im 3
+    31ed:	e0          	im -32
+    31ee:	80          	im 0
+    31ef:	08          	load
+    31f0:	90          	im 16
+    31f1:	38          	neqbranch
+
+000031f2 <.L16>:
+    31f2:	ff          	im -1
+    31f3:	b6          	im 54
+    31f4:	e4          	im -28
+    31f5:	3f          	callpcrel
+    31f6:	fe          	im -2
+    31f7:	af          	im 47
+    31f8:	3f          	callpcrel
+    31f9:	83          	im 3
+    31fa:	e0          	im -32
+    31fb:	80          	im 0
+    31fc:	08          	load
+    31fd:	80          	im 0
+    31fe:	2e          	eq
+    31ff:	f2          	im -14
+    3200:	38          	neqbranch
+
+00003201 <.L18>:
+    3201:	80          	im 0
+    3202:	fb          	im -5
+    3203:	f0          	im -16
+    3204:	08          	load
+    3205:	70          	loadsp 0
+    3206:	33          	loadb
+    3207:	70          	loadsp 0
+    3208:	81          	im 1
+    3209:	ff          	im -1
+    320a:	06          	and
+    320b:	83          	im 3
+    320c:	e0          	im -32
+    320d:	80          	im 0
+    320e:	0c          	store
+    320f:	51          	storesp 4
+    3210:	51          	storesp 4
+
+00003211 <.LM33>:
+    3211:	82          	im 2
+    3212:	3d          	pushspadd
+    3213:	0d          	popsp
+    3214:	04          	poppc
+
+00003215 <USART_Transmit_Mode>:
+    3215:	80          	im 0
+    3216:	3d          	pushspadd
+    3217:	0d          	popsp
+
+00003218 <.LM35>:
+    3218:	80          	im 0
+    3219:	fb          	im -5
+    321a:	e8          	im -24
+    321b:	08          	load
+    321c:	51          	storesp 4
+    321d:	a3          	im 35
+    321e:	71          	loadsp 4
+    321f:	34          	storeb
+
+00003220 <.LM36>:
+    3220:	80          	im 0
+    3221:	fb          	im -5
+    3222:	f4          	im -12
+    3223:	08          	load
+    3224:	51          	storesp 4
+    3225:	ff          	im -1
+    3226:	71          	loadsp 4
+    3227:	34          	storeb
+
+00003228 <.LM37>:
+    3228:	80          	im 0
+    3229:	fb          	im -5
+    322a:	ec          	im -20
+    322b:	08          	load
+    322c:	51          	storesp 4
+    322d:	a8          	im 40
+    322e:	71          	loadsp 4
+    322f:	34          	storeb
+
+00003230 <.LM38>:
+    3230:	80          	im 0
+    3231:	fb          	im -5
+    3232:	ec          	im -20
+    3233:	08          	load
+    3234:	51          	storesp 4
+    3235:	b8          	im 56
+    3236:	71          	loadsp 4
+    3237:	34          	storeb
+    3238:	82          	im 2
+    3239:	3d          	pushspadd
+    323a:	0d          	popsp
+    323b:	04          	poppc
+
+0000323c <USART_Framing_Error>:
+}
+
+int USART_Framing_Error()
+{
+    323c:	80          	im 0
+    323d:	3d          	pushspadd
+    323e:	0d          	popsp
+
+0000323f <.LM40>:
+	if (0xc0&(*zpu_pokey_skctl))
+    323f:	80          	im 0
+    3240:	fb          	im -5
+    3241:	e8          	im -24
+    3242:	08          	load
+    3243:	70          	loadsp 0
+    3244:	33          	loadb
+    3245:	70          	loadsp 0
+    3246:	81          	im 1
+    3247:	c0          	im -64
+    3248:	06          	and
+
+00003249 <.LM41>:
+	{
+		return 0;
+    3249:	70          	loadsp 0
+    324a:	30          	neg
+
+0000324b <.LM42>:
+	}
+	else
+	{
+		return 1;
+	}
+}
+    324b:	70          	loadsp 0
+    324c:	80          	im 0
+    324d:	25          	lessthanorequal
+    324e:	83          	im 3
+    324f:	e0          	im -32
+    3250:	80          	im 0
+    3251:	0c          	store
+    3252:	51          	storesp 4
+    3253:	51          	storesp 4
+    3254:	51          	storesp 4
+    3255:	51          	storesp 4
+    3256:	82          	im 2
+    3257:	3d          	pushspadd
+    3258:	0d          	popsp
+    3259:	04          	poppc
+
+0000325a <USART_Wait_Transmit_Complete>:
+
+void USART_Wait_Transmit_Complete()
+{
+    325a:	ff          	im -1
+    325b:	3d          	pushspadd
+    325c:	0d          	popsp
+    325d:	80          	im 0
+    325e:	fb          	im -5
+    325f:	ec          	im -20
+    3260:	08          	load
+    3261:	52          	storesp 8
+
+00003262 <.L24>:
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+    3262:	71          	loadsp 4
+    3263:	33          	loadb
+    3264:	70          	loadsp 0
+    3265:	81          	im 1
+    3266:	ff          	im -1
+    3267:	06          	and
+    3268:	70          	loadsp 0
+    3269:	83          	im 3
+    326a:	2a          	lshiftright
+    326b:	81          	im 1
+    326c:	32          	xor
+    326d:	70          	loadsp 0
+    326e:	81          	im 1
+    326f:	06          	and
+    3270:	51          	storesp 4
+    3271:	51          	storesp 4
+    3272:	51          	storesp 4
+    3273:	51          	storesp 4
+
+00003274 <.LM45>:
+		if (ready)
+    3274:	70          	loadsp 0
+    3275:	80          	im 0
+    3276:	2e          	eq
+    3277:	ea          	im -22
+    3278:	38          	neqbranch
+
+00003279 <.LM46>:
+		{
+			*zpu_pokey_irqen = 0x30;
+    3279:	b0          	im 48
+    327a:	72          	loadsp 8
+    327b:	34          	storeb
+
+0000327c <.LM47>:
+			*zpu_pokey_irqen = 0x38;
+    327c:	80          	im 0
+    327d:	fb          	im -5
+    327e:	ec          	im -20
+    327f:	08          	load
+    3280:	51          	storesp 4
+    3281:	b8          	im 56
+    3282:	71          	loadsp 4
+    3283:	34          	storeb
+
+00003284 <.LBE2>:
+    3284:	83          	im 3
+    3285:	3d          	pushspadd
+    3286:	0d          	popsp
+    3287:	04          	poppc
+
+00003288 <set_green_led>:
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+    3288:	80          	im 0
+    3289:	3d          	pushspadd
+    328a:	0d          	popsp
+
+0000328b <.LM2>:
+	*zpu_ledg = i;
+    328b:	80          	im 0
+    328c:	fc          	im -4
+    328d:	b4          	im 52
+    328e:	08          	load
+    328f:	73          	loadsp 12
+    3290:	71          	loadsp 4
+    3291:	0c          	store
+    3292:	51          	storesp 4
+    3293:	82          	im 2
+    3294:	3d          	pushspadd
+    3295:	0d          	popsp
+    3296:	04          	poppc
+
+00003297 <set_red_led>:
+}
+void set_red_led(int i)
+{
+    3297:	80          	im 0
+    3298:	3d          	pushspadd
+    3299:	0d          	popsp
+
+0000329a <.LM4>:
+	*zpu_ledr = i;
+    329a:	80          	im 0
+    329b:	fc          	im -4
+    329c:	b0          	im 48
+    329d:	08          	load
+    329e:	73          	loadsp 12
+    329f:	71          	loadsp 4
+    32a0:	0c          	store
+    32a1:	51          	storesp 4
+    32a2:	82          	im 2
+    32a3:	3d          	pushspadd
+    32a4:	0d          	popsp
+    32a5:	04          	poppc
+
+000032a6 <set_drive_number>:
+}
+void set_drive_number(int i)
+{
+    32a6:	80          	im 0
+    32a7:	3d          	pushspadd
+    32a8:	0d          	popsp
+
+000032a9 <.LM6>:
+	*zpu_hex = i;
+    32a9:	80          	im 0
+    32aa:	fc          	im -4
+    32ab:	9c          	im 28
+    32ac:	08          	load
+    32ad:	73          	loadsp 12
+    32ae:	71          	loadsp 4
+    32af:	0c          	store
+    32b0:	51          	storesp 4
+    32b1:	82          	im 2
+    32b2:	3d          	pushspadd
+    32b3:	0d          	popsp
+    32b4:	04          	poppc
+
+000032b5 <init_display>:
+}
+void init_display()
+{
+    32b5:	80          	im 0
+    32b6:	3d          	pushspadd
+    32b7:	0d          	popsp
+
+000032b8 <.LM8>:
+	*zpu_hex = 0;
+    32b8:	80          	im 0
+    32b9:	fc          	im -4
+    32ba:	9c          	im 28
+    32bb:	08          	load
+    32bc:	51          	storesp 4
+    32bd:	80          	im 0
+    32be:	71          	loadsp 4
+    32bf:	0c          	store
+    32c0:	82          	im 2
+    32c1:	3d          	pushspadd
+    32c2:	0d          	popsp
+    32c3:	04          	poppc
+
+000032c4 <topofscreen>:
+int debugoffsetval;
+
+void topofscreen()
+{
+	xpos = 0;
+    32c4:	80          	im 0
+    32c5:	0b          	nop
+    32c6:	83          	im 3
+    32c7:	e7          	im -25
+    32c8:	f4          	im -12
+    32c9:	0c          	store
+
+000032ca <.LM3>:
+	ypos = 0;
+    32ca:	80          	im 0
+    32cb:	0b          	nop
+    32cc:	83          	im 3
+    32cd:	e8          	im -24
+    32ce:	80          	im 0
+    32cf:	0c          	store
+    32d0:	04          	poppc
+
+000032d1 <setxpos>:
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+    32d1:	71          	loadsp 4
+    32d2:	83          	im 3
+    32d3:	e7          	im -25
+    32d4:	f4          	im -12
+    32d5:	0c          	store
+    32d6:	04          	poppc
+
+000032d7 <setypos>:
+}
+
+void setypos(int val)
+{
+	ypos = val;
+    32d7:	71          	loadsp 4
+    32d8:	83          	im 3
+    32d9:	e8          	im -24
+    32da:	80          	im 0
+    32db:	0c          	store
+    32dc:	04          	poppc
+
+000032dd <initdebug>:
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+    32dd:	80          	im 0
+    32de:	0b          	nop
+    32df:	83          	im 3
+    32e0:	e7          	im -25
+    32e1:	f4          	im -12
+    32e2:	0c          	store
+
+000032e3 <.LM10>:
+	ypos = 0;
+    32e3:	80          	im 0
+    32e4:	0b          	nop
+    32e5:	83          	im 3
+    32e6:	e8          	im -24
+    32e7:	80          	im 0
+    32e8:	0c          	store
+
+000032e9 <.LM11>:
+	onoff = onoff_in;
+    32e9:	71          	loadsp 4
+    32ea:	83          	im 3
+    32eb:	e7          	im -25
+    32ec:	fc          	im -4
+    32ed:	0c          	store
+    32ee:	04          	poppc
+
+000032ef <plot>:
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+    32ef:	ff          	im -1
+    32f0:	3d          	pushspadd
+    32f1:	0d          	popsp
+    32f2:	75          	loadsp 20
+    32f3:	02          	pushsp
+    32f4:	84          	im 4
+    32f5:	05          	add
+    32f6:	8f          	im 15
+    32f7:	05          	add
+    32f8:	33          	loadb
+    32f9:	53          	storesp 12
+    32fa:	51          	storesp 4
+
+000032fb <.LM13>:
+	if (onoff == 0) return;
+    32fb:	83          	im 3
+    32fc:	e7          	im -25
+    32fd:	fc          	im -4
+    32fe:	08          	load
+    32ff:	80          	im 0
+    3300:	2e          	eq
+    3301:	9a          	im 26
+    3302:	38          	neqbranch
+
+00003303 <.LM14>:
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val+debugoffsetval;
+    3303:	70          	loadsp 0
+    3304:	10          	addsp 0
+    3305:	10          	addsp 0
+    3306:	11          	addsp 4
+    3307:	70          	loadsp 0
+    3308:	10          	addsp 0
+    3309:	10          	addsp 0
+    330a:	10          	addsp 0
+    330b:	16          	addsp 24
+    330c:	86          	im 6
+    330d:	b8          	im 56
+    330e:	c0          	im -64
+    330f:	11          	addsp 4
+    3310:	83          	im 3
+    3311:	e7          	im -25
+    3312:	f8          	im -8
+    3313:	08          	load
+    3314:	15          	addsp 20
+    3315:	55          	storesp 20
+    3316:	51          	storesp 4
+    3317:	51          	storesp 4
+    3318:	51          	storesp 4
+    3319:	71          	loadsp 4
+    331a:	71          	loadsp 4
+    331b:	34          	storeb
+
+0000331c <.L5>:
+}
+    331c:	83          	im 3
+    331d:	3d          	pushspadd
+    331e:	0d          	popsp
+    331f:	04          	poppc
+
+00003320 <nextline>:
+    3320:	fd          	im -3
+    3321:	3d          	pushspadd
+    3322:	0d          	popsp
+
+00003323 <.LM17>:
+    3323:	80          	im 0
+    3324:	0b          	nop
+    3325:	83          	im 3
+    3326:	e7          	im -25
+    3327:	f4          	im -12
+    3328:	0c          	store
+
+00003329 <.LM18>:
+    3329:	83          	im 3
+    332a:	e8          	im -24
+    332b:	80          	im 0
+    332c:	08          	load
+    332d:	81          	im 1
+    332e:	05          	add
+    332f:	54          	storesp 16
+
+00003330 <.LM19>:
+    3330:	73          	loadsp 12
+    3331:	98          	im 24
+    3332:	2e          	eq
+    3333:	a3          	im 35
+    3334:	38          	neqbranch
+    3335:	73          	loadsp 12
+    3336:	83          	im 3
+    3337:	e8          	im -24
+    3338:	80          	im 0
+    3339:	0c          	store
+
+0000333a <.LM20>:
+    333a:	80          	im 0
+    333b:	54          	storesp 16
+
+0000333c <.L13>:
+    333c:	83          	im 3
+    333d:	e8          	im -24
+    333e:	80          	im 0
+    333f:	08          	load
+    3340:	53          	storesp 12
+    3341:	73          	loadsp 12
+    3342:	52          	storesp 8
+    3343:	80          	im 0
+    3344:	51          	storesp 4
+    3345:	ff          	im -1
+    3346:	a8          	im 40
+    3347:	3f          	callpcrel
+
+00003348 <.LM22>:
+    3348:	81          	im 1
+    3349:	14          	addsp 16
+    334a:	54          	storesp 16
+    334b:	73          	loadsp 12
+    334c:	a8          	im 40
+    334d:	2e          	eq
+    334e:	09          	not
+    334f:	81          	im 1
+    3350:	06          	and
+    3351:	ea          	im -22
+    3352:	38          	neqbranch
+    3353:	85          	im 5
+    3354:	3d          	pushspadd
+    3355:	0d          	popsp
+    3356:	04          	poppc
+
+00003357 <.L18>:
+    3357:	80          	im 0
+    3358:	0b          	nop
+    3359:	83          	im 3
+    335a:	e8          	im -24
+    335b:	80          	im 0
+    335c:	0c          	store
+
+0000335d <.LM24>:
+    335d:	80          	im 0
+    335e:	54          	storesp 16
+    335f:	dc          	im -36
+    3360:	39          	poppcrel
+
+00003361 <toatarichar>:
+    3361:	fe          	im -2
+    3362:	3d          	pushspadd
+    3363:	0d          	popsp
+    3364:	74          	loadsp 16
+    3365:	52          	storesp 8
+
+00003366 <.LM26>:
+    3366:	80          	im 0
+    3367:	53          	storesp 12
+    3368:	80          	im 0
+    3369:	ff          	im -1
+    336a:	72          	loadsp 8
+    336b:	25          	lessthanorequal
+    336c:	88          	im 8
+    336d:	38          	neqbranch
+    336e:	81          	im 1
+
+0000336f <.LM27>:
+    336f:	0b          	nop
+    3370:	ff          	im -1
+    3371:	80          	im 0
+    3372:	13          	addsp 12
+    3373:	53          	storesp 12
+    3374:	53          	storesp 12
+
+00003375 <.L21>:
+    3375:	ff          	im -1
+    3376:	bf          	im 63
+    3377:	12          	addsp 8
+    3378:	51          	storesp 4
+    3379:	99          	im 25
+    337a:	71          	loadsp 4
+    337b:	27          	ulessthanorequal
+    337c:	a7          	im 39
+    337d:	38          	neqbranch
+
+0000337e <.LM29>:
+    337e:	ff          	im -1
+    337f:	9f          	im 31
+    3380:	12          	addsp 8
+    3381:	51          	storesp 4
+    3382:	70          	loadsp 0
+    3383:	99          	im 25
+    3384:	26          	ulessthan
+    3385:	96          	im 22
+    3386:	38          	neqbranch
+
+00003387 <.L23>:
+    3387:	72          	loadsp 8
+    3388:	80          	im 0
+    3389:	2e          	eq
+    338a:	85          	im 5
+    338b:	38          	neqbranch
+
+0000338c <.LM31>:
+    338c:	81          	im 1
+    338d:	80          	im 0
+    338e:	12          	addsp 8
+    338f:	52          	storesp 8
+
+00003390 <.L30>:
+    3390:	71          	loadsp 4
+    3391:	81          	im 1
+    3392:	ff          	im -1
+    3393:	06          	and
+    3394:	83          	im 3
+    3395:	e0          	im -32
+    3396:	80          	im 0
+    3397:	0c          	store
+
+00003398 <.LM33>:
+    3398:	84          	im 4
+    3399:	3d          	pushspadd
+    339a:	0d          	popsp
+    339b:	04          	poppc
+
+0000339c <.L34>:
+    339c:	d0          	im -48
+    339d:	12          	addsp 8
+    339e:	51          	storesp 4
+    339f:	70          	loadsp 0
+    33a0:	89          	im 9
+    33a1:	26          	ulessthan
+    33a2:	86          	im 6
+    33a3:	38          	neqbranch
+
+000033a4 <.L32>:
+    33a4:	e0          	im -32
+    33a5:	12          	addsp 8
+    33a6:	52          	storesp 8
+    33a7:	df          	im -33
+    33a8:	39          	poppcrel
+
+000033a9 <.L26>:
+    33a9:	e0          	im -32
+    33aa:	12          	addsp 8
+
+000033ab <.LM37>:
+    33ab:	70          	loadsp 0
+    33ac:	53          	storesp 12
+    33ad:	51          	storesp 4
+
+000033ae <.LM38>:
+    33ae:	8f          	im 15
+    33af:	71          	loadsp 4
+    33b0:	27          	ulessthanorequal
+    33b1:	d5          	im -43
+    33b2:	38          	neqbranch
+
+000033b3 <.LM39>:
+    33b3:	80          	im 0
+    33b4:	52          	storesp 8
+    33b5:	d1          	im -47
+    33b6:	39          	poppcrel
+
+000033b7 <hextoatarichar>:
+    33b7:	ff          	im -1
+    33b8:	3d          	pushspadd
+    33b9:	0d          	popsp
+    33ba:	73          	loadsp 12
+    33bb:	52          	storesp 8
+
+000033bc <.LM41>:
+    33bc:	71          	loadsp 4
+    33bd:	89          	im 9
+    33be:	26          	ulessthan
+    33bf:	90          	im 16
+    33c0:	38          	neqbranch
+
+000033c1 <.LM42>:
+    33c1:	90          	im 16
+    33c2:	12          	addsp 8
+    33c3:	52          	storesp 8
+
+000033c4 <.L37>:
+    33c4:	71          	loadsp 4
+    33c5:	81          	im 1
+    33c6:	ff          	im -1
+    33c7:	06          	and
+    33c8:	83          	im 3
+    33c9:	e0          	im -32
+    33ca:	80          	im 0
+    33cb:	0c          	store
+
+000033cc <.LM44>:
+    33cc:	83          	im 3
+    33cd:	3d          	pushspadd
+    33ce:	0d          	popsp
+    33cf:	04          	poppc
+
+000033d0 <.L36>:
+    33d0:	f6          	im -10
+    33d1:	12          	addsp 8
+    33d2:	51          	storesp 4
+    33d3:	70          	loadsp 0
+    33d4:	85          	im 5
+    33d5:	26          	ulessthan
+    33d6:	ed          	im -19
+    33d7:	38          	neqbranch
+
+000033d8 <.LM46>:
+    33d8:	97          	im 23
+    33d9:	12          	addsp 8
+
+000033da <.LM47>:
+    33da:	70          	loadsp 0
+    33db:	81          	im 1
+    33dc:	ff          	im -1
+    33dd:	06          	and
+    33de:	83          	im 3
+    33df:	e0          	im -32
+    33e0:	80          	im 0
+    33e1:	0c          	store
+    33e2:	52          	storesp 8
+
+000033e3 <.LM48>:
+    33e3:	83          	im 3
+    33e4:	3d          	pushspadd
+    33e5:	0d          	popsp
+    33e6:	04          	poppc
+
+000033e7 <debugoffset>:
+void debugoffset(int x)
+{
+	debugoffsetval = x;
+    33e7:	71          	loadsp 4
+    33e8:	83          	im 3
+    33e9:	e7          	im -25
+    33ea:	f8          	im -8
+    33eb:	0c          	store
+    33ec:	04          	poppc
+
+000033ed <debug>:
+}
+void debug(char const * str)
+{
+    33ed:	fc          	im -4
+    33ee:	3d          	pushspadd
+    33ef:	0d          	popsp
+    33f0:	76          	loadsp 24
+    33f1:	55          	storesp 20
+
+000033f2 <.L51>:
+	while (1)
+	{
+		int val = *str++;
+    33f2:	74          	loadsp 16
+    33f3:	70          	loadsp 0
+    33f4:	81          	im 1
+    33f5:	05          	add
+    33f6:	56          	storesp 24
+    33f7:	33          	loadb
+    33f8:	54          	storesp 16
+
+000033f9 <.LM53>:
+		if (val==0) break;
+    33f9:	73          	loadsp 12
+    33fa:	80          	im 0
+    33fb:	2e          	eq
+    33fc:	80          	im 0
+    33fd:	c2          	im -62
+    33fe:	38          	neqbranch
+
+000033ff <.L53>:
+		if (val=='\n') {nextline();continue;};
+    33ff:	73          	loadsp 12
+    3400:	8a          	im 10
+    3401:	2e          	eq
+    3402:	b0          	im 48
+    3403:	38          	neqbranch
+
+00003404 <.LM55>:
+
+		plot(toatarichar(val),xpos,ypos);
+    3404:	73          	loadsp 12
+    3405:	51          	storesp 4
+    3406:	fe          	im -2
+    3407:	d9          	im -39
+    3408:	3f          	callpcrel
+    3409:	83          	im 3
+    340a:	e8          	im -24
+    340b:	80          	im 0
+    340c:	08          	load
+    340d:	53          	storesp 12
+    340e:	83          	im 3
+    340f:	e7          	im -25
+    3410:	f4          	im -12
+    3411:	08          	load
+    3412:	52          	storesp 8
+    3413:	83          	im 3
+    3414:	e0          	im -32
+    3415:	80          	im 0
+    3416:	08          	load
+    3417:	81          	im 1
+    3418:	ff          	im -1
+    3419:	06          	and
+    341a:	51          	storesp 4
+    341b:	fd          	im -3
+    341c:	d2          	im -46
+    341d:	3f          	callpcrel
+
+0000341e <.LM56>:
+		++xpos;
+    341e:	83          	im 3
+    341f:	e7          	im -25
+    3420:	f4          	im -12
+    3421:	08          	load
+    3422:	81          	im 1
+    3423:	05          	add
+    3424:	83          	im 3
+    3425:	e7          	im -25
+    3426:	f4          	im -12
+    3427:	0c          	store
+
+00003428 <.LM57>:
+		if (xpos==40)
+    3428:	83          	im 3
+    3429:	e7          	im -25
+    342a:	f4          	im -12
+    342b:	08          	load
+    342c:	a8          	im 40
+    342d:	2e          	eq
+    342e:	09          	not
+    342f:	81          	im 1
+    3430:	06          	and
+    3431:	c0          	im -64
+    3432:	38          	neqbranch
+
+00003433 <.L50>:
+		{
+			nextline();
+    3433:	fd          	im -3
+    3434:	eb          	im -21
+    3435:	3f          	callpcrel
+
+00003436 <.LM59>:
+    3436:	74          	loadsp 16
+    3437:	70          	loadsp 0
+    3438:	81          	im 1
+    3439:	05          	add
+    343a:	56          	storesp 24
+    343b:	33          	loadb
+    343c:	54          	storesp 16
+
+0000343d <.LM60>:
+    343d:	73          	loadsp 12
+    343e:	c0          	im -64
+    343f:	38          	neqbranch
+
+00003440 <.L43>:
+		}
+	}
+	debugoffsetval = 0;
+    3440:	80          	im 0
+    3441:	0b          	nop
+    3442:	83          	im 3
+    3443:	e7          	im -25
+    3444:	f8          	im -8
+    3445:	0c          	store
+    3446:	86          	im 6
+    3447:	3d          	pushspadd
+    3448:	0d          	popsp
+    3449:	04          	poppc
+
+0000344a <plotnext>:
+}
+
+void plotnext(unsigned char val)
+{
+    344a:	fd          	im -3
+    344b:	3d          	pushspadd
+    344c:	0d          	popsp
+    344d:	02          	pushsp
+    344e:	97          	im 23
+    344f:	05          	add
+    3450:	33          	loadb
+
+00003451 <.LM63>:
+	plot(val,xpos,ypos);
+    3451:	83          	im 3
+    3452:	e8          	im -24
+    3453:	80          	im 0
+    3454:	08          	load
+    3455:	54          	storesp 16
+    3456:	83          	im 3
+    3457:	e7          	im -25
+    3458:	f4          	im -12
+    3459:	08          	load
+    345a:	53          	storesp 12
+    345b:	51          	storesp 4
+    345c:	fd          	im -3
+    345d:	91          	im 17
+    345e:	3f          	callpcrel
+
+0000345f <.LM64>:
+
+	++xpos;
+    345f:	83          	im 3
+    3460:	e7          	im -25
+    3461:	f4          	im -12
+    3462:	08          	load
+    3463:	81          	im 1
+    3464:	05          	add
+    3465:	83          	im 3
+    3466:	e7          	im -25
+    3467:	f4          	im -12
+    3468:	0c          	store
+
+00003469 <.LM65>:
+	if (xpos==40) nextline();
+    3469:	83          	im 3
+    346a:	e7          	im -25
+    346b:	f4          	im -12
+    346c:	08          	load
+    346d:	a8          	im 40
+    346e:	2e          	eq
+    346f:	85          	im 5
+    3470:	38          	neqbranch
+
+00003471 <.LM66>:
+}
+    3471:	85          	im 5
+    3472:	3d          	pushspadd
+    3473:	0d          	popsp
+    3474:	04          	poppc
+
+00003475 <.L57>:
+    3475:	fd          	im -3
+    3476:	a9          	im 41
+    3477:	3f          	callpcrel
+
+00003478 <.LM68>:
+    3478:	85          	im 5
+    3479:	3d          	pushspadd
+    347a:	0d          	popsp
+    347b:	04          	poppc
+
+0000347c <plotnextnumber>:
+
+void plotnextnumber(unsigned short val)
+{
+    347c:	fe          	im -2
+    347d:	3d          	pushspadd
+    347e:	0d          	popsp
+    347f:	02          	pushsp
+    3480:	92          	im 18
+    3481:	05          	add
+    3482:	22          	loadh
+
+00003483 <.LM70>:
+	plotnext(hextoatarichar((val&0xf000)>>12));
+    3483:	70          	loadsp 0
+    3484:	8c          	im 12
+    3485:	2a          	lshiftright
+    3486:	52          	storesp 8
+    3487:	52          	storesp 8
+    3488:	fe          	im -2
+    3489:	ad          	im 45
+    348a:	3f          	callpcrel
+    348b:	83          	im 3
+    348c:	e0          	im -32
+    348d:	80          	im 0
+    348e:	08          	load
+    348f:	81          	im 1
+    3490:	ff          	im -1
+    3491:	06          	and
+    3492:	51          	storesp 4
+    3493:	ff          	im -1
+    3494:	b5          	im 53
+    3495:	3f          	callpcrel
+
+00003496 <.LM71>:
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+    3496:	71          	loadsp 4
+    3497:	9e          	im 30
+    3498:	80          	im 0
+    3499:	06          	and
+    349a:	70          	loadsp 0
+    349b:	88          	im 8
+    349c:	2a          	lshiftright
+    349d:	52          	storesp 8
+    349e:	53          	storesp 12
+    349f:	fe          	im -2
+    34a0:	96          	im 22
+    34a1:	3f          	callpcrel
+    34a2:	83          	im 3
+    34a3:	e0          	im -32
+    34a4:	80          	im 0
+    34a5:	08          	load
+    34a6:	81          	im 1
+    34a7:	ff          	im -1
+    34a8:	06          	and
+    34a9:	51          	storesp 4
+    34aa:	ff          	im -1
+    34ab:	9e          	im 30
+    34ac:	3f          	callpcrel
+
+000034ad <.LM72>:
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+    34ad:	71          	loadsp 4
+    34ae:	81          	im 1
+    34af:	f0          	im -16
+    34b0:	06          	and
+    34b1:	70          	loadsp 0
+    34b2:	84          	im 4
+    34b3:	2a          	lshiftright
+    34b4:	52          	storesp 8
+    34b5:	53          	storesp 12
+    34b6:	fd          	im -3
+    34b7:	ff          	im -1
+    34b8:	3f          	callpcrel
+    34b9:	83          	im 3
+    34ba:	e0          	im -32
+    34bb:	80          	im 0
+    34bc:	08          	load
+    34bd:	81          	im 1
+    34be:	ff          	im -1
+    34bf:	06          	and
+    34c0:	51          	storesp 4
+    34c1:	ff          	im -1
+    34c2:	87          	im 7
+    34c3:	3f          	callpcrel
+
+000034c4 <.LM73>:
+	plotnext(hextoatarichar((val&0x000f)>>0));
+    34c4:	71          	loadsp 4
+    34c5:	8f          	im 15
+    34c6:	06          	and
+    34c7:	51          	storesp 4
+    34c8:	fd          	im -3
+    34c9:	ed          	im -19
+    34ca:	3f          	callpcrel
+    34cb:	83          	im 3
+    34cc:	e0          	im -32
+    34cd:	80          	im 0
+    34ce:	08          	load
+    34cf:	81          	im 1
+    34d0:	ff          	im -1
+    34d1:	06          	and
+    34d2:	51          	storesp 4
+    34d3:	fe          	im -2
+    34d4:	f5          	im -11
+    34d5:	3f          	callpcrel
+
+000034d6 <.LM74>:
+	debugoffsetval = 0;
+    34d6:	80          	im 0
+    34d7:	0b          	nop
+    34d8:	83          	im 3
+    34d9:	e7          	im -25
+    34da:	f8          	im -8
+    34db:	0c          	store
+    34dc:	84          	im 4
+    34dd:	3d          	pushspadd
+    34de:	0d          	popsp
+    34df:	04          	poppc
+
+000034e0 <hexdump>:
+}
+
+void hexdump(char const * str, int length)
+{
+    34e0:	fb          	im -5
+    34e1:	3d          	pushspadd
+    34e2:	0d          	popsp
+    34e3:	77          	loadsp 28
+    34e4:	79          	loadsp 36
+    34e5:	56          	storesp 24
+    34e6:	56          	storesp 24
+
+000034e7 <.LM76>:
+	nextline();
+    34e7:	fc          	im -4
+    34e8:	b7          	im 55
+    34e9:	3f          	callpcrel
+
+000034ea <.LM77>:
+
+	for (;length>0;--length)
+    34ea:	80          	im 0
+    34eb:	75          	loadsp 20
+    34ec:	25          	lessthanorequal
+    34ed:	80          	im 0
+    34ee:	fb          	im -5
+    34ef:	38          	neqbranch
+
+000034f0 <.L70>:
+	{
+		unsigned char val= *str++;
+    34f0:	75          	loadsp 20
+    34f1:	70          	loadsp 0
+    34f2:	81          	im 1
+    34f3:	05          	add
+    34f4:	57          	storesp 28
+    34f5:	33          	loadb
+
+000034f6 <.LM79>:
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+    34f6:	70          	loadsp 0
+    34f7:	52          	storesp 8
+    34f8:	54          	storesp 16
+    34f9:	fc          	im -4
+    34fa:	e6          	im -26
+    34fb:	3f          	callpcrel
+    34fc:	83          	im 3
+    34fd:	e8          	im -24
+    34fe:	80          	im 0
+    34ff:	08          	load
+    3500:	53          	storesp 12
+    3501:	83          	im 3
+    3502:	e7          	im -25
+    3503:	f4          	im -12
+    3504:	08          	load
+    3505:	52          	storesp 8
+    3506:	83          	im 3
+    3507:	e0          	im -32
+    3508:	80          	im 0
+    3509:	08          	load
+    350a:	81          	im 1
+    350b:	ff          	im -1
+    350c:	06          	and
+    350d:	51          	storesp 4
+    350e:	fb          	im -5
+    350f:	df          	im -33
+    3510:	3f          	callpcrel
+
+00003511 <.LM80>:
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+    3511:	73          	loadsp 12
+    3512:	84          	im 4
+    3513:	2a          	lshiftright
+    3514:	51          	storesp 4
+    3515:	fd          	im -3
+    3516:	a0          	im 32
+    3517:	3f          	callpcrel
+    3518:	83          	im 3
+    3519:	e8          	im -24
+    351a:	80          	im 0
+    351b:	08          	load
+    351c:	53          	storesp 12
+    351d:	83          	im 3
+    351e:	e7          	im -25
+    351f:	f4          	im -12
+    3520:	08          	load
+    3521:	10          	addsp 0
+    3522:	94          	im 20
+    3523:	05          	add
+    3524:	52          	storesp 8
+    3525:	83          	im 3
+    3526:	e0          	im -32
+    3527:	80          	im 0
+    3528:	08          	load
+    3529:	81          	im 1
+    352a:	ff          	im -1
+    352b:	06          	and
+    352c:	51          	storesp 4
+    352d:	fb          	im -5
+    352e:	c0          	im -64
+    352f:	3f          	callpcrel
+
+00003530 <.LM81>:
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+    3530:	73          	loadsp 12
+    3531:	8f          	im 15
+    3532:	06          	and
+    3533:	51          	storesp 4
+    3534:	fd          	im -3
+    3535:	81          	im 1
+    3536:	3f          	callpcrel
+    3537:	83          	im 3
+    3538:	e8          	im -24
+    3539:	80          	im 0
+    353a:	08          	load
+    353b:	53          	storesp 12
+    353c:	83          	im 3
+    353d:	e7          	im -25
+    353e:	f4          	im -12
+    353f:	08          	load
+    3540:	10          	addsp 0
+    3541:	95          	im 21
+    3542:	05          	add
+    3543:	52          	storesp 8
+    3544:	83          	im 3
+    3545:	e0          	im -32
+    3546:	80          	im 0
+    3547:	08          	load
+    3548:	81          	im 1
+    3549:	ff          	im -1
+    354a:	06          	and
+    354b:	51          	storesp 4
+    354c:	fb          	im -5
+    354d:	a1          	im 33
+    354e:	3f          	callpcrel
+
+0000354f <.LM82>:
+
+		++xpos;
+    354f:	83          	im 3
+    3550:	e7          	im -25
+    3551:	f4          	im -12
+    3552:	08          	load
+    3553:	81          	im 1
+    3554:	05          	add
+    3555:	83          	im 3
+    3556:	e7          	im -25
+    3557:	f4          	im -12
+    3558:	0c          	store
+
+00003559 <.LM83>:
+		if (xpos==10)
+    3559:	83          	im 3
+    355a:	e7          	im -25
+    355b:	f4          	im -12
+    355c:	08          	load
+    355d:	8a          	im 10
+    355e:	2e          	eq
+    355f:	91          	im 17
+    3560:	38          	neqbranch
+
+00003561 <.LM84>:
+    3561:	ff          	im -1
+    3562:	15          	addsp 20
+    3563:	55          	storesp 20
+
+00003564 <.L71>:
+    3564:	74          	loadsp 16
+    3565:	80          	im 0
+    3566:	24          	lessthan
+    3567:	ff          	im -1
+    3568:	87          	im 7
+    3569:	38          	neqbranch
+
+0000356a <.L66>:
+		{
+			nextline();
+		}
+	}
+	nextline();
+    356a:	fb          	im -5
+    356b:	b4          	im 52
+    356c:	3f          	callpcrel
+    356d:	87          	im 7
+    356e:	3d          	pushspadd
+    356f:	0d          	popsp
+    3570:	04          	poppc
+
+00003571 <.L69>:
+    3571:	fb          	im -5
+    3572:	ad          	im 45
+    3573:	3f          	callpcrel
+
+00003574 <.LM87>:
+    3574:	ff          	im -1
+    3575:	15          	addsp 20
+    3576:	55          	storesp 20
+    3577:	ec          	im -20
+    3578:	39          	poppcrel
+
+00003579 <hexdump_pure>:
+}
+
+void hexdump_pure(char const * str, int length)
+{
+    3579:	fb          	im -5
+    357a:	3d          	pushspadd
+    357b:	0d          	popsp
+    357c:	77          	loadsp 28
+    357d:	79          	loadsp 36
+
+0000357e <.LM89>:
+	xpos = xpos&0xfffe;
+    357e:	83          	im 3
+    357f:	e7          	im -25
+    3580:	f4          	im -12
+    3581:	08          	load
+    3582:	83          	im 3
+    3583:	ff          	im -1
+    3584:	fe          	im -2
+    3585:	06          	and
+    3586:	83          	im 3
+    3587:	e7          	im -25
+    3588:	f4          	im -12
+    3589:	0c          	store
+    358a:	56          	storesp 24
+    358b:	56          	storesp 24
+
+0000358c <.LM90>:
+	for (;length>0;--length)
+    358c:	80          	im 0
+    358d:	75          	loadsp 20
+    358e:	25          	lessthanorequal
+    358f:	80          	im 0
+    3590:	e5          	im -27
+    3591:	38          	neqbranch
+
+00003592 <.L83>:
+	{
+		unsigned char val= *str++;
+    3592:	75          	loadsp 20
+    3593:	70          	loadsp 0
+    3594:	81          	im 1
+    3595:	05          	add
+    3596:	57          	storesp 28
+    3597:	33          	loadb
+
+00003598 <.LM92>:
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+    3598:	70          	loadsp 0
+    3599:	84          	im 4
+    359a:	2a          	lshiftright
+    359b:	52          	storesp 8
+    359c:	54          	storesp 16
+    359d:	fc          	im -4
+    359e:	98          	im 24
+    359f:	3f          	callpcrel
+    35a0:	83          	im 3
+    35a1:	e8          	im -24
+    35a2:	80          	im 0
+    35a3:	08          	load
+    35a4:	53          	storesp 12
+    35a5:	83          	im 3
+    35a6:	e7          	im -25
+    35a7:	f4          	im -12
+    35a8:	08          	load
+    35a9:	52          	storesp 8
+    35aa:	83          	im 3
+    35ab:	e7          	im -25
+    35ac:	f4          	im -12
+    35ad:	08          	load
+    35ae:	81          	im 1
+    35af:	05          	add
+    35b0:	83          	im 3
+    35b1:	e7          	im -25
+    35b2:	f4          	im -12
+    35b3:	0c          	store
+    35b4:	83          	im 3
+    35b5:	e0          	im -32
+    35b6:	80          	im 0
+    35b7:	08          	load
+    35b8:	81          	im 1
+    35b9:	ff          	im -1
+    35ba:	06          	and
+    35bb:	51          	storesp 4
+    35bc:	fa          	im -6
+    35bd:	b1          	im 49
+    35be:	3f          	callpcrel
+
+000035bf <.LM93>:
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+    35bf:	73          	loadsp 12
+    35c0:	8f          	im 15
+    35c1:	06          	and
+    35c2:	51          	storesp 4
+    35c3:	fb          	im -5
+    35c4:	f2          	im -14
+    35c5:	3f          	callpcrel
+    35c6:	83          	im 3
+    35c7:	e8          	im -24
+    35c8:	80          	im 0
+    35c9:	08          	load
+    35ca:	53          	storesp 12
+    35cb:	83          	im 3
+    35cc:	e7          	im -25
+    35cd:	f4          	im -12
+    35ce:	08          	load
+    35cf:	52          	storesp 8
+    35d0:	83          	im 3
+    35d1:	e7          	im -25
+    35d2:	f4          	im -12
+    35d3:	08          	load
+    35d4:	81          	im 1
+    35d5:	05          	add
+    35d6:	83          	im 3
+    35d7:	e7          	im -25
+    35d8:	f4          	im -12
+    35d9:	0c          	store
+    35da:	83          	im 3
+    35db:	e0          	im -32
+    35dc:	80          	im 0
+    35dd:	08          	load
+    35de:	81          	im 1
+    35df:	ff          	im -1
+    35e0:	06          	and
+    35e1:	51          	storesp 4
+    35e2:	fa          	im -6
+    35e3:	8b          	im 11
+    35e4:	3f          	callpcrel
+
+000035e5 <.LM94>:
+
+		if (xpos==40)
+    35e5:	83          	im 3
+    35e6:	e7          	im -25
+    35e7:	f4          	im -12
+    35e8:	08          	load
+    35e9:	a8          	im 40
+    35ea:	2e          	eq
+    35eb:	8e          	im 14
+    35ec:	38          	neqbranch
+
+000035ed <.LM95>:
+    35ed:	ff          	im -1
+    35ee:	15          	addsp 20
+    35ef:	55          	storesp 20
+
+000035f0 <.L84>:
+    35f0:	74          	loadsp 16
+    35f1:	80          	im 0
+    35f2:	24          	lessthan
+    35f3:	ff          	im -1
+    35f4:	9d          	im 29
+    35f5:	38          	neqbranch
+
+000035f6 <.L79>:
+    35f6:	87          	im 7
+    35f7:	3d          	pushspadd
+    35f8:	0d          	popsp
+    35f9:	04          	poppc
+
+000035fa <.L82>:
+		{
+			nextline();
+    35fa:	fa          	im -6
+    35fb:	a4          	im 36
+    35fc:	3f          	callpcrel
+
+000035fd <.LM97>:
+    35fd:	ff          	im -1
+    35fe:	15          	addsp 20
+    35ff:	55          	storesp 20
+    3600:	ef          	im -17
+    3601:	39          	poppcrel
+
+00003602 <__udivsi3>:
+    3602:	83          	im 3
+    3603:	e0          	im -32
+    3604:	8c          	im 12
+    3605:	08          	load
+    3606:	02          	pushsp
+    3607:	83          	im 3
+    3608:	e0          	im -32
+    3609:	8c          	im 12
+    360a:	0c          	store
+    360b:	fd          	im -3
+    360c:	3d          	pushspadd
+    360d:	0d          	popsp
+    360e:	80          	im 0
+    360f:	53          	storesp 12
+    3610:	83          	im 3
+    3611:	e0          	im -32
+    3612:	8c          	im 12
+    3613:	08          	load
+    3614:	8c          	im 12
+    3615:	05          	add
+    3616:	08          	load
+    3617:	52          	storesp 8
+    3618:	83          	im 3
+    3619:	e0          	im -32
+    361a:	8c          	im 12
+    361b:	08          	load
+    361c:	88          	im 8
+    361d:	05          	add
+    361e:	08          	load
+    361f:	51          	storesp 4
+    3620:	83          	im 3
+    3621:	d4          	im -44
+    3622:	3f          	callpcrel
+    3623:	83          	im 3
+    3624:	e0          	im -32
+    3625:	80          	im 0
+    3626:	08          	load
+    3627:	70          	loadsp 0
+    3628:	83          	im 3
+    3629:	e0          	im -32
+    362a:	80          	im 0
+    362b:	0c          	store
+    362c:	54          	storesp 16
+    362d:	85          	im 5
+    362e:	3d          	pushspadd
+    362f:	0d          	popsp
+    3630:	83          	im 3
+    3631:	e0          	im -32
+    3632:	8c          	im 12
+    3633:	0c          	store
+    3634:	04          	poppc
+
+00003635 <__umodsi3>:
+    3635:	83          	im 3
+    3636:	e0          	im -32
+    3637:	8c          	im 12
+    3638:	08          	load
+    3639:	02          	pushsp
+    363a:	83          	im 3
+    363b:	e0          	im -32
+    363c:	8c          	im 12
+    363d:	0c          	store
+    363e:	fd          	im -3
+    363f:	3d          	pushspadd
+    3640:	0d          	popsp
+    3641:	81          	im 1
+    3642:	53          	storesp 12
+    3643:	83          	im 3
+    3644:	e0          	im -32
+    3645:	8c          	im 12
+    3646:	08          	load
+    3647:	8c          	im 12
+    3648:	05          	add
+    3649:	08          	load
+    364a:	52          	storesp 8
+    364b:	83          	im 3
+    364c:	e0          	im -32
+    364d:	8c          	im 12
+    364e:	08          	load
+    364f:	88          	im 8
+    3650:	05          	add
+    3651:	08          	load
+    3652:	51          	storesp 4
+    3653:	83          	im 3
+    3654:	a1          	im 33
+    3655:	3f          	callpcrel
+    3656:	83          	im 3
+    3657:	e0          	im -32
+    3658:	80          	im 0
+    3659:	08          	load
+    365a:	70          	loadsp 0
+    365b:	83          	im 3
+    365c:	e0          	im -32
+    365d:	80          	im 0
+    365e:	0c          	store
+    365f:	54          	storesp 16
+    3660:	85          	im 5
+    3661:	3d          	pushspadd
+    3662:	0d          	popsp
+    3663:	83          	im 3
+    3664:	e0          	im -32
+    3665:	8c          	im 12
+    3666:	0c          	store
+    3667:	04          	poppc
+
+00003668 <__divsi3>:
+    3668:	83          	im 3
+    3669:	e0          	im -32
+    366a:	8c          	im 12
+    366b:	08          	load
+    366c:	02          	pushsp
+    366d:	83          	im 3
+    366e:	e0          	im -32
+    366f:	8c          	im 12
+    3670:	0c          	store
+    3671:	f9          	im -7
+    3672:	3d          	pushspadd
+    3673:	0d          	popsp
+    3674:	80          	im 0
+    3675:	0b          	nop
+    3676:	83          	im 3
+    3677:	e0          	im -32
+    3678:	8c          	im 12
+    3679:	08          	load
+    367a:	fc          	im -4
+    367b:	05          	add
+    367c:	0c          	store
+    367d:	83          	im 3
+    367e:	e0          	im -32
+    367f:	8c          	im 12
+    3680:	08          	load
+    3681:	88          	im 8
+    3682:	05          	add
+    3683:	08          	load
+    3684:	80          	im 0
+    3685:	25          	lessthanorequal
+    3686:	b9          	im 57
+    3687:	38          	neqbranch
+    3688:	83          	im 3
+    3689:	e0          	im -32
+    368a:	8c          	im 12
+    368b:	08          	load
+    368c:	88          	im 8
+    368d:	05          	add
+    368e:	08          	load
+    368f:	30          	neg
+    3690:	83          	im 3
+    3691:	e0          	im -32
+    3692:	8c          	im 12
+    3693:	08          	load
+    3694:	88          	im 8
+    3695:	05          	add
+    3696:	0c          	store
+    3697:	80          	im 0
+    3698:	0b          	nop
+    3699:	83          	im 3
+    369a:	e0          	im -32
+    369b:	8c          	im 12
+    369c:	08          	load
+    369d:	f4          	im -12
+    369e:	05          	add
+    369f:	0c          	store
+    36a0:	83          	im 3
+    36a1:	e0          	im -32
+    36a2:	8c          	im 12
+    36a3:	08          	load
+    36a4:	fc          	im -4
+    36a5:	05          	add
+    36a6:	08          	load
+    36a7:	8a          	im 10
+    36a8:	38          	neqbranch
+    36a9:	81          	im 1
+    36aa:	0b          	nop
+    36ab:	83          	im 3
+    36ac:	e0          	im -32
+    36ad:	8c          	im 12
+    36ae:	08          	load
+    36af:	f4          	im -12
+    36b0:	05          	add
+    36b1:	0c          	store
+
+000036b2 <.L3>:
+    36b2:	83          	im 3
+    36b3:	e0          	im -32
+    36b4:	8c          	im 12
+    36b5:	08          	load
+    36b6:	f4          	im -12
+    36b7:	05          	add
+    36b8:	08          	load
+    36b9:	83          	im 3
+    36ba:	e0          	im -32
+    36bb:	8c          	im 12
+    36bc:	08          	load
+    36bd:	fc          	im -4
+    36be:	05          	add
+    36bf:	0c          	store
+
+000036c0 <.L2>:
+    36c0:	83          	im 3
+    36c1:	e0          	im -32
+    36c2:	8c          	im 12
+    36c3:	08          	load
+    36c4:	8c          	im 12
+    36c5:	05          	add
+    36c6:	08          	load
+    36c7:	80          	im 0
+    36c8:	25          	lessthanorequal
+    36c9:	b9          	im 57
+    36ca:	38          	neqbranch
+    36cb:	83          	im 3
+    36cc:	e0          	im -32
+    36cd:	8c          	im 12
+    36ce:	08          	load
+    36cf:	8c          	im 12
+    36d0:	05          	add
+    36d1:	08          	load
+    36d2:	30          	neg
+    36d3:	83          	im 3
+    36d4:	e0          	im -32
+    36d5:	8c          	im 12
+    36d6:	08          	load
+    36d7:	8c          	im 12
+    36d8:	05          	add
+    36d9:	0c          	store
+    36da:	80          	im 0
+    36db:	0b          	nop
+    36dc:	83          	im 3
+    36dd:	e0          	im -32
+    36de:	8c          	im 12
+    36df:	08          	load
+    36e0:	f0          	im -16
+    36e1:	05          	add
+    36e2:	0c          	store
+    36e3:	83          	im 3
+    36e4:	e0          	im -32
+    36e5:	8c          	im 12
+    36e6:	08          	load
+    36e7:	fc          	im -4
+    36e8:	05          	add
+    36e9:	08          	load
+    36ea:	8a          	im 10
+    36eb:	38          	neqbranch
+    36ec:	81          	im 1
+    36ed:	0b          	nop
+    36ee:	83          	im 3
+    36ef:	e0          	im -32
+    36f0:	8c          	im 12
+    36f1:	08          	load
+    36f2:	f0          	im -16
+    36f3:	05          	add
+    36f4:	0c          	store
+
+000036f5 <.L5>:
+    36f5:	83          	im 3
+    36f6:	e0          	im -32
+    36f7:	8c          	im 12
+    36f8:	08          	load
+    36f9:	f0          	im -16
+    36fa:	05          	add
+    36fb:	08          	load
+    36fc:	83          	im 3
+    36fd:	e0          	im -32
+    36fe:	8c          	im 12
+    36ff:	08          	load
+    3700:	fc          	im -4
+    3701:	05          	add
+    3702:	0c          	store
+
+00003703 <.L4>:
+    3703:	80          	im 0
+    3704:	53          	storesp 12
+    3705:	83          	im 3
+    3706:	e0          	im -32
+    3707:	8c          	im 12
+    3708:	08          	load
+    3709:	8c          	im 12
+    370a:	05          	add
+    370b:	08          	load
+    370c:	52          	storesp 8
+    370d:	83          	im 3
+    370e:	e0          	im -32
+    370f:	8c          	im 12
+    3710:	08          	load
+    3711:	88          	im 8
+    3712:	05          	add
+    3713:	08          	load
+    3714:	51          	storesp 4
+    3715:	81          	im 1
+    3716:	df          	im -33
+    3717:	3f          	callpcrel
+    3718:	83          	im 3
+    3719:	e0          	im -32
+    371a:	80          	im 0
+    371b:	08          	load
+    371c:	70          	loadsp 0
+    371d:	83          	im 3
+    371e:	e0          	im -32
+    371f:	8c          	im 12
+    3720:	08          	load
+    3721:	f8          	im -8
+    3722:	05          	add
+    3723:	0c          	store
+    3724:	54          	storesp 16
+    3725:	83          	im 3
+    3726:	e0          	im -32
+    3727:	8c          	im 12
+    3728:	08          	load
+    3729:	fc          	im -4
+    372a:	05          	add
+    372b:	08          	load
+    372c:	80          	im 0
+    372d:	2e          	eq
+    372e:	90          	im 16
+    372f:	38          	neqbranch
+    3730:	83          	im 3
+    3731:	e0          	im -32
+    3732:	8c          	im 12
+    3733:	08          	load
+    3734:	f8          	im -8
+    3735:	05          	add
+    3736:	08          	load
+    3737:	30          	neg
+    3738:	83          	im 3
+    3739:	e0          	im -32
+    373a:	8c          	im 12
+    373b:	08          	load
+    373c:	f8          	im -8
+    373d:	05          	add
+    373e:	0c          	store
+
+0000373f <.L6>:
+    373f:	83          	im 3
+    3740:	e0          	im -32
+    3741:	8c          	im 12
+    3742:	08          	load
+    3743:	f8          	im -8
+    3744:	05          	add
+    3745:	08          	load
+    3746:	70          	loadsp 0
+    3747:	83          	im 3
+    3748:	e0          	im -32
+    3749:	80          	im 0
+    374a:	0c          	store
+    374b:	54          	storesp 16
+    374c:	89          	im 9
+    374d:	3d          	pushspadd
+    374e:	0d          	popsp
+    374f:	83          	im 3
+    3750:	e0          	im -32
+    3751:	8c          	im 12
+    3752:	0c          	store
+    3753:	04          	poppc
+
+00003754 <__modsi3>:
+    3754:	83          	im 3
+    3755:	e0          	im -32
+    3756:	8c          	im 12
+    3757:	08          	load
+    3758:	02          	pushsp
+    3759:	83          	im 3
+    375a:	e0          	im -32
+    375b:	8c          	im 12
+    375c:	0c          	store
+    375d:	fb          	im -5
+    375e:	3d          	pushspadd
+    375f:	0d          	popsp
+    3760:	80          	im 0
+    3761:	0b          	nop
+    3762:	83          	im 3
+    3763:	e0          	im -32
+    3764:	8c          	im 12
+    3765:	08          	load
+    3766:	fc          	im -4
+    3767:	05          	add
+    3768:	0c          	store
+    3769:	83          	im 3
+    376a:	e0          	im -32
+    376b:	8c          	im 12
+    376c:	08          	load
+    376d:	88          	im 8
+    376e:	05          	add
+    376f:	08          	load
+    3770:	80          	im 0
+    3771:	25          	lessthanorequal
+    3772:	99          	im 25
+    3773:	38          	neqbranch
+    3774:	83          	im 3
+    3775:	e0          	im -32
+    3776:	8c          	im 12
+    3777:	08          	load
+    3778:	88          	im 8
+    3779:	05          	add
+    377a:	08          	load
+    377b:	30          	neg
+    377c:	83          	im 3
+    377d:	e0          	im -32
+    377e:	8c          	im 12
+    377f:	08          	load
+    3780:	88          	im 8
+    3781:	05          	add
+    3782:	0c          	store
+    3783:	81          	im 1
+    3784:	0b          	nop
+    3785:	83          	im 3
+    3786:	e0          	im -32
+    3787:	8c          	im 12
+    3788:	08          	load
+    3789:	fc          	im -4
+    378a:	05          	add
+    378b:	0c          	store
+
+0000378c <.L8>:
+    378c:	83          	im 3
+    378d:	e0          	im -32
+    378e:	8c          	im 12
+    378f:	08          	load
+    3790:	8c          	im 12
+    3791:	05          	add
+    3792:	08          	load
+    3793:	80          	im 0
+    3794:	25          	lessthanorequal
+    3795:	90          	im 16
+    3796:	38          	neqbranch
+    3797:	83          	im 3
+    3798:	e0          	im -32
+    3799:	8c          	im 12
+    379a:	08          	load
+    379b:	8c          	im 12
+    379c:	05          	add
+    379d:	08          	load
+    379e:	30          	neg
+    379f:	83          	im 3
+    37a0:	e0          	im -32
+    37a1:	8c          	im 12
+    37a2:	08          	load
+    37a3:	8c          	im 12
+    37a4:	05          	add
+    37a5:	0c          	store
+
+000037a6 <.L9>:
+    37a6:	81          	im 1
+    37a7:	53          	storesp 12
+    37a8:	83          	im 3
+    37a9:	e0          	im -32
+    37aa:	8c          	im 12
+    37ab:	08          	load
+    37ac:	8c          	im 12
+    37ad:	05          	add
+    37ae:	08          	load
+    37af:	52          	storesp 8
+    37b0:	83          	im 3
+    37b1:	e0          	im -32
+    37b2:	8c          	im 12
+    37b3:	08          	load
+    37b4:	88          	im 8
+    37b5:	05          	add
+    37b6:	08          	load
+    37b7:	51          	storesp 4
+    37b8:	bd          	im 61
+    37b9:	3f          	callpcrel
+    37ba:	83          	im 3
+    37bb:	e0          	im -32
+    37bc:	80          	im 0
+    37bd:	08          	load
+    37be:	70          	loadsp 0
+    37bf:	83          	im 3
+    37c0:	e0          	im -32
+    37c1:	8c          	im 12
+    37c2:	08          	load
+    37c3:	f8          	im -8
+    37c4:	05          	add
+    37c5:	0c          	store
+    37c6:	54          	storesp 16
+    37c7:	83          	im 3
+    37c8:	e0          	im -32
+    37c9:	8c          	im 12
+    37ca:	08          	load
+    37cb:	fc          	im -4
+    37cc:	05          	add
+    37cd:	08          	load
+    37ce:	80          	im 0
+    37cf:	2e          	eq
+    37d0:	90          	im 16
+    37d1:	38          	neqbranch
+    37d2:	83          	im 3
+    37d3:	e0          	im -32
+    37d4:	8c          	im 12
+    37d5:	08          	load
+    37d6:	f8          	im -8
+    37d7:	05          	add
+    37d8:	08          	load
+    37d9:	30          	neg
+    37da:	83          	im 3
+    37db:	e0          	im -32
+    37dc:	8c          	im 12
+    37dd:	08          	load
+    37de:	f8          	im -8
+    37df:	05          	add
+    37e0:	0c          	store
+
+000037e1 <.L10>:
+    37e1:	83          	im 3
+    37e2:	e0          	im -32
+    37e3:	8c          	im 12
+    37e4:	08          	load
+    37e5:	f8          	im -8
+    37e6:	05          	add
+    37e7:	08          	load
+    37e8:	70          	loadsp 0
+    37e9:	83          	im 3
+    37ea:	e0          	im -32
+    37eb:	80          	im 0
+    37ec:	0c          	store
+    37ed:	54          	storesp 16
+    37ee:	87          	im 7
+    37ef:	3d          	pushspadd
+    37f0:	0d          	popsp
+    37f1:	83          	im 3
+    37f2:	e0          	im -32
+    37f3:	8c          	im 12
+    37f4:	0c          	store
+    37f5:	04          	poppc
+
+000037f6 <udivmodsi4>:
+    37f6:	83          	im 3
+    37f7:	e0          	im -32
+    37f8:	8c          	im 12
+    37f9:	08          	load
+    37fa:	02          	pushsp
+    37fb:	83          	im 3
+    37fc:	e0          	im -32
+    37fd:	8c          	im 12
+    37fe:	0c          	store
+    37ff:	fd          	im -3
+    3800:	3d          	pushspadd
+    3801:	0d          	popsp
+    3802:	81          	im 1
+    3803:	0b          	nop
+    3804:	83          	im 3
+    3805:	e0          	im -32
+    3806:	8c          	im 12
+    3807:	08          	load
+    3808:	fc          	im -4
+    3809:	05          	add
+    380a:	0c          	store
+    380b:	80          	im 0
+    380c:	0b          	nop
+    380d:	83          	im 3
+    380e:	e0          	im -32
+    380f:	8c          	im 12
+    3810:	08          	load
+    3811:	f8          	im -8
+    3812:	05          	add
+    3813:	0c          	store
+
+00003814 <.L2>:
+    3814:	83          	im 3
+    3815:	e0          	im -32
+    3816:	8c          	im 12
+    3817:	08          	load
+    3818:	8c          	im 12
+    3819:	05          	add
+    381a:	08          	load
+    381b:	83          	im 3
+    381c:	e0          	im -32
+    381d:	8c          	im 12
+    381e:	08          	load
+    381f:	88          	im 8
+    3820:	05          	add
+    3821:	08          	load
+    3822:	27          	ulessthanorequal
+    3823:	b9          	im 57
+    3824:	38          	neqbranch
+    3825:	83          	im 3
+    3826:	e0          	im -32
+    3827:	8c          	im 12
+    3828:	08          	load
+    3829:	fc          	im -4
+    382a:	05          	add
+    382b:	08          	load
+    382c:	80          	im 0
+    382d:	2e          	eq
+    382e:	ae          	im 46
+    382f:	38          	neqbranch
+    3830:	80          	im 0
+    3831:	0b          	nop
+    3832:	83          	im 3
+    3833:	e0          	im -32
+    3834:	8c          	im 12
+    3835:	08          	load
+    3836:	8c          	im 12
+    3837:	05          	add
+    3838:	08          	load
+    3839:	24          	lessthan
+    383a:	a2          	im 34
+    383b:	38          	neqbranch
+    383c:	83          	im 3
+    383d:	e0          	im -32
+    383e:	8c          	im 12
+    383f:	08          	load
+    3840:	8c          	im 12
+    3841:	05          	add
+    3842:	08          	load
+    3843:	10          	addsp 0
+    3844:	83          	im 3
+    3845:	e0          	im -32
+    3846:	8c          	im 12
+    3847:	08          	load
+    3848:	8c          	im 12
+    3849:	05          	add
+    384a:	0c          	store
+    384b:	83          	im 3
+    384c:	e0          	im -32
+    384d:	8c          	im 12
+    384e:	08          	load
+    384f:	fc          	im -4
+    3850:	05          	add
+    3851:	08          	load
+    3852:	10          	addsp 0
+    3853:	83          	im 3
+    3854:	e0          	im -32
+    3855:	8c          	im 12
+    3856:	08          	load
+    3857:	fc          	im -4
+    3858:	05          	add
+    3859:	0c          	store
+    385a:	ff          	im -1
+    385b:	b8          	im 56
+    385c:	39          	poppcrel
+
+0000385d <.L4>:
+    385d:	83          	im 3
+    385e:	e0          	im -32
+    385f:	8c          	im 12
+    3860:	08          	load
+    3861:	fc          	im -4
+    3862:	05          	add
+    3863:	08          	load
+    3864:	80          	im 0
+    3865:	2e          	eq
+    3866:	80          	im 0
+    3867:	e1          	im -31
+    3868:	38          	neqbranch
+    3869:	83          	im 3
+    386a:	e0          	im -32
+    386b:	8c          	im 12
+    386c:	08          	load
+    386d:	8c          	im 12
+    386e:	05          	add
+    386f:	08          	load
+    3870:	83          	im 3
+    3871:	e0          	im -32
+    3872:	8c          	im 12
+    3873:	08          	load
+    3874:	88          	im 8
+    3875:	05          	add
+    3876:	08          	load
+    3877:	26          	ulessthan
+    3878:	ad          	im 45
+    3879:	38          	neqbranch
+    387a:	83          	im 3
+    387b:	e0          	im -32
+    387c:	8c          	im 12
+    387d:	08          	load
+    387e:	88          	im 8
+    387f:	05          	add
+    3880:	08          	load
+    3881:	83          	im 3
+    3882:	e0          	im -32
+    3883:	8c          	im 12
+    3884:	08          	load
+    3885:	8c          	im 12
+    3886:	05          	add
+    3887:	08          	load
+    3888:	31          	sub
+    3889:	83          	im 3
+    388a:	e0          	im -32
+    388b:	8c          	im 12
+    388c:	08          	load
+    388d:	88          	im 8
+    388e:	05          	add
+    388f:	0c          	store
+    3890:	83          	im 3
+    3891:	e0          	im -32
+    3892:	8c          	im 12
+    3893:	08          	load
+    3894:	f8          	im -8
+    3895:	05          	add
+    3896:	08          	load
+    3897:	83          	im 3
+    3898:	e0          	im -32
+    3899:	8c          	im 12
+    389a:	08          	load
+    389b:	fc          	im -4
+    389c:	05          	add
+    389d:	08          	load
+    389e:	07          	or
+    389f:	83          	im 3
+    38a0:	e0          	im -32
+    38a1:	8c          	im 12
+    38a2:	08          	load
+    38a3:	f8          	im -8
+    38a4:	05          	add
+    38a5:	0c          	store
+
+000038a6 <.L6>:
+    38a6:	83          	im 3
+    38a7:	e0          	im -32
+    38a8:	8c          	im 12
+    38a9:	08          	load
+    38aa:	fc          	im -4
+    38ab:	05          	add
+    38ac:	08          	load
+    38ad:	81          	im 1
+    38ae:	2a          	lshiftright
+    38af:	83          	im 3
+    38b0:	e0          	im -32
+    38b1:	8c          	im 12
+    38b2:	08          	load
+    38b3:	fc          	im -4
+    38b4:	05          	add
+    38b5:	0c          	store
+    38b6:	83          	im 3
+    38b7:	e0          	im -32
+    38b8:	8c          	im 12
+    38b9:	08          	load
+    38ba:	8c          	im 12
+    38bb:	05          	add
+    38bc:	08          	load
+    38bd:	81          	im 1
+    38be:	2a          	lshiftright
+    38bf:	83          	im 3
+    38c0:	e0          	im -32
+    38c1:	8c          	im 12
+    38c2:	08          	load
+    38c3:	8c          	im 12
+    38c4:	05          	add
+    38c5:	0c          	store
+    38c6:	ff          	im -1
+    38c7:	95          	im 21
+    38c8:	39          	poppcrel
+
+000038c9 <.L5>:
+    38c9:	83          	im 3
+    38ca:	e0          	im -32
+    38cb:	8c          	im 12
+    38cc:	08          	load
+    38cd:	90          	im 16
+    38ce:	05          	add
+    38cf:	08          	load
+    38d0:	80          	im 0
+    38d1:	2e          	eq
+    38d2:	93          	im 19
+    38d3:	38          	neqbranch
+    38d4:	83          	im 3
+    38d5:	e0          	im -32
+    38d6:	8c          	im 12
+    38d7:	08          	load
+    38d8:	88          	im 8
+    38d9:	05          	add
+    38da:	08          	load
+    38db:	70          	loadsp 0
+    38dc:	83          	im 3
+    38dd:	e0          	im -32
+    38de:	8c          	im 12
+    38df:	08          	load
+    38e0:	f4          	im -12
+    38e1:	05          	add
+    38e2:	0c          	store
+    38e3:	51          	storesp 4
+    38e4:	91          	im 17
+    38e5:	39          	poppcrel
+
+000038e6 <.L7>:
+    38e6:	83          	im 3
+    38e7:	e0          	im -32
+    38e8:	8c          	im 12
+    38e9:	08          	load
+    38ea:	f8          	im -8
+    38eb:	05          	add
+    38ec:	08          	load
+    38ed:	70          	loadsp 0
+    38ee:	83          	im 3
+    38ef:	e0          	im -32
+    38f0:	8c          	im 12
+    38f1:	08          	load
+    38f2:	f4          	im -12
+    38f3:	05          	add
+    38f4:	0c          	store
+    38f5:	51          	storesp 4
+
+000038f6 <.L1>:
+    38f6:	83          	im 3
+    38f7:	e0          	im -32
+    38f8:	8c          	im 12
+    38f9:	08          	load
+    38fa:	f4          	im -12
+    38fb:	05          	add
+    38fc:	08          	load
+    38fd:	83          	im 3
+    38fe:	e0          	im -32
+    38ff:	80          	im 0
+    3900:	0c          	store
+    3901:	85          	im 5
+    3902:	3d          	pushspadd
+    3903:	0d          	popsp
+    3904:	83          	im 3
+    3905:	e0          	im -32
+    3906:	8c          	im 12
+    3907:	0c          	store
+    3908:	04          	poppc
+
+00003909 <__mulsi3>:
+    3909:	83          	im 3
+    390a:	e0          	im -32
+    390b:	8c          	im 12
+    390c:	08          	load
+    390d:	02          	pushsp
+    390e:	83          	im 3
+    390f:	e0          	im -32
+    3910:	8c          	im 12
+    3911:	0c          	store
+    3912:	ff          	im -1
+    3913:	3d          	pushspadd
+    3914:	0d          	popsp
+    3915:	80          	im 0
+    3916:	0b          	nop
+    3917:	83          	im 3
+    3918:	e0          	im -32
+    3919:	8c          	im 12
+    391a:	08          	load
+    391b:	fc          	im -4
+    391c:	05          	add
+    391d:	0c          	store
+
+0000391e <.L2>:
+    391e:	83          	im 3
+    391f:	e0          	im -32
+    3920:	8c          	im 12
+    3921:	08          	load
+    3922:	88          	im 8
+    3923:	05          	add
+    3924:	08          	load
+    3925:	81          	im 1
+    3926:	06          	and
+    3927:	ff          	im -1
+    3928:	11          	addsp 4
+    3929:	70          	loadsp 0
+    392a:	09          	not
+    392b:	70          	loadsp 0
+    392c:	83          	im 3
+    392d:	e0          	im -32
+    392e:	8c          	im 12
+    392f:	08          	load
+    3930:	8c          	im 12
+    3931:	05          	add
+    3932:	08          	load
+    3933:	06          	and
+    3934:	83          	im 3
+    3935:	e0          	im -32
+    3936:	8c          	im 12
+    3937:	08          	load
+    3938:	fc          	im -4
+    3939:	05          	add
+    393a:	08          	load
+    393b:	11          	addsp 4
+    393c:	83          	im 3
+    393d:	e0          	im -32
+    393e:	8c          	im 12
+    393f:	08          	load
+    3940:	fc          	im -4
+    3941:	05          	add
+    3942:	0c          	store
+    3943:	83          	im 3
+    3944:	e0          	im -32
+    3945:	8c          	im 12
+    3946:	08          	load
+    3947:	88          	im 8
+    3948:	05          	add
+    3949:	08          	load
+    394a:	81          	im 1
+    394b:	2a          	lshiftright
+    394c:	83          	im 3
+    394d:	e0          	im -32
+    394e:	8c          	im 12
+    394f:	08          	load
+    3950:	88          	im 8
+    3951:	05          	add
+    3952:	0c          	store
+    3953:	83          	im 3
+    3954:	e0          	im -32
+    3955:	8c          	im 12
+    3956:	08          	load
+    3957:	8c          	im 12
+    3958:	05          	add
+    3959:	08          	load
+    395a:	10          	addsp 0
+    395b:	83          	im 3
+    395c:	e0          	im -32
+    395d:	8c          	im 12
+    395e:	08          	load
+    395f:	8c          	im 12
+    3960:	05          	add
+    3961:	0c          	store
+    3962:	51          	storesp 4
+    3963:	51          	storesp 4
+    3964:	51          	storesp 4
+    3965:	51          	storesp 4
+    3966:	83          	im 3
+    3967:	e0          	im -32
+    3968:	8c          	im 12
+    3969:	08          	load
+    396a:	88          	im 8
+    396b:	05          	add
+    396c:	08          	load
+    396d:	80          	im 0
+    396e:	2e          	eq
+    396f:	84          	im 4
+    3970:	38          	neqbranch
+    3971:	ff          	im -1
+    3972:	ab          	im 43
+    3973:	39          	poppcrel
+
+00003974 <.L3>:
+    3974:	83          	im 3
+    3975:	e0          	im -32
+    3976:	8c          	im 12
+    3977:	08          	load
+    3978:	fc          	im -4
+    3979:	05          	add
+    397a:	08          	load
+    397b:	70          	loadsp 0
+    397c:	83          	im 3
+    397d:	e0          	im -32
+    397e:	80          	im 0
+    397f:	0c          	store
+    3980:	51          	storesp 4
+    3981:	83          	im 3
+    3982:	3d          	pushspadd
+    3983:	0d          	popsp
+    3984:	83          	im 3
+    3985:	e0          	im -32
+    3986:	8c          	im 12
+    3987:	0c          	store
+    3988:	04          	poppc
+
+00003989 <memcpy>:
+    3989:	fc          	im -4
+    398a:	3d          	pushspadd
+    398b:	0d          	popsp
+    398c:	76          	loadsp 24
+
+0000398d <.LM2>:
+    398d:	70          	loadsp 0
+
+0000398e <.LM3>:
+    398e:	79          	loadsp 36
+
+0000398f <.LM4>:
+    398f:	7b          	loadsp 44
+    3990:	55          	storesp 20
+    3991:	55          	storesp 20
+    3992:	55          	storesp 20
+    3993:	55          	storesp 20
+
+00003994 <.LM5>:
+    3994:	8f          	im 15
+    3995:	72          	loadsp 8
+    3996:	27          	ulessthanorequal
+    3997:	8c          	im 12
+    3998:	38          	neqbranch
+    3999:	72          	loadsp 8
+    399a:	75          	loadsp 20
+    399b:	07          	or
+    399c:	83          	im 3
+    399d:	06          	and
+    399e:	51          	storesp 4
+    399f:	70          	loadsp 0
+    39a0:	80          	im 0
+    39a1:	2e          	eq
+    39a2:	a9          	im 41
+    39a3:	38          	neqbranch
+
+000039a4 <.L2>:
+    39a4:	ff          	im -1
+    39a5:	12          	addsp 8
+    39a6:	52          	storesp 8
+    39a7:	71          	loadsp 4
+    39a8:	ff          	im -1
+    39a9:	2e          	eq
+    39aa:	98          	im 24
+    39ab:	38          	neqbranch
+
+000039ac <.L21>:
+    39ac:	72          	loadsp 8
+    39ad:	70          	loadsp 0
+    39ae:	81          	im 1
+    39af:	05          	add
+    39b0:	54          	storesp 16
+    39b1:	33          	loadb
+    39b2:	74          	loadsp 16
+    39b3:	70          	loadsp 0
+    39b4:	81          	im 1
+    39b5:	05          	add
+    39b6:	56          	storesp 24
+    39b7:	34          	storeb
+    39b8:	ff          	im -1
+    39b9:	12          	addsp 8
+    39ba:	52          	storesp 8
+    39bb:	71          	loadsp 4
+    39bc:	ff          	im -1
+    39bd:	2e          	eq
+    39be:	09          	not
+    39bf:	81          	im 1
+    39c0:	06          	and
+    39c1:	ea          	im -22
+    39c2:	38          	neqbranch
+
+000039c3 <.L17>:
+    39c3:	74          	loadsp 16
+    39c4:	83          	im 3
+    39c5:	e0          	im -32
+    39c6:	80          	im 0
+    39c7:	0c          	store
+    39c8:	86          	im 6
+    39c9:	3d          	pushspadd
+    39ca:	0d          	popsp
+    39cb:	04          	poppc
+
+000039cc <.L20>:
+    39cc:	74          	loadsp 16
+    39cd:	51          	storesp 4
+
+000039ce <.L5>:
+    39ce:	72          	loadsp 8
+    39cf:	70          	loadsp 0
+    39d0:	84          	im 4
+    39d1:	05          	add
+    39d2:	54          	storesp 16
+    39d3:	08          	load
+    39d4:	71          	loadsp 4
+    39d5:	70          	loadsp 0
+    39d6:	84          	im 4
+    39d7:	05          	add
+    39d8:	53          	storesp 12
+    39d9:	0c          	store
+
+000039da <.LM10>:
+    39da:	72          	loadsp 8
+    39db:	70          	loadsp 0
+    39dc:	84          	im 4
+    39dd:	05          	add
+    39de:	54          	storesp 16
+    39df:	08          	load
+    39e0:	71          	loadsp 4
+    39e1:	70          	loadsp 0
+    39e2:	84          	im 4
+    39e3:	05          	add
+    39e4:	53          	storesp 12
+    39e5:	0c          	store
+
+000039e6 <.LM11>:
+    39e6:	72          	loadsp 8
+    39e7:	70          	loadsp 0
+    39e8:	84          	im 4
+    39e9:	05          	add
+    39ea:	54          	storesp 16
+    39eb:	08          	load
+    39ec:	71          	loadsp 4
+    39ed:	70          	loadsp 0
+    39ee:	84          	im 4
+    39ef:	05          	add
+    39f0:	53          	storesp 12
+    39f1:	0c          	store
+
+000039f2 <.LM12>:
+    39f2:	72          	loadsp 8
+    39f3:	70          	loadsp 0
+    39f4:	84          	im 4
+    39f5:	05          	add
+    39f6:	54          	storesp 16
+    39f7:	08          	load
+    39f8:	71          	loadsp 4
+    39f9:	70          	loadsp 0
+    39fa:	84          	im 4
+    39fb:	05          	add
+    39fc:	53          	storesp 12
+    39fd:	0c          	store
+
+000039fe <.LM13>:
+    39fe:	f0          	im -16
+    39ff:	12          	addsp 8
+    3a00:	52          	storesp 8
+    3a01:	71          	loadsp 4
+    3a02:	8f          	im 15
+    3a03:	26          	ulessthan
+    3a04:	c9          	im -55
+    3a05:	38          	neqbranch
+
+00003a06 <.LM14>:
+    3a06:	83          	im 3
+    3a07:	72          	loadsp 8
+    3a08:	27          	ulessthanorequal
+    3a09:	95          	im 21
+    3a0a:	38          	neqbranch
+
+00003a0b <.L22>:
+    3a0b:	72          	loadsp 8
+    3a0c:	70          	loadsp 0
+    3a0d:	84          	im 4
+    3a0e:	05          	add
+    3a0f:	54          	storesp 16
+    3a10:	08          	load
+    3a11:	71          	loadsp 4
+    3a12:	70          	loadsp 0
+    3a13:	84          	im 4
+    3a14:	05          	add
+    3a15:	53          	storesp 12
+    3a16:	0c          	store
+
+00003a17 <.LM16>:
+    3a17:	fc          	im -4
+    3a18:	12          	addsp 8
+    3a19:	52          	storesp 8
+    3a1a:	71          	loadsp 4
+    3a1b:	83          	im 3
+    3a1c:	26          	ulessthan
+    3a1d:	ed          	im -19
+    3a1e:	38          	neqbranch
+
+00003a1f <.L15>:
+    3a1f:	70          	loadsp 0
+    3a20:	54          	storesp 16
+    3a21:	ff          	im -1
+    3a22:	81          	im 1
+    3a23:	39          	poppcrel
Index: unmerged/zpu_firmware/mist/pff.c
===================================================================
--- unmerged/zpu_firmware/mist/pff.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/zpu_firmware/mist/rom_epilogue.vhd
===================================================================
--- unmerged/zpu_firmware/mist/rom_epilogue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/mist/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/zpu_firmware/mist/stuff.c
===================================================================
--- unmerged/zpu_firmware/mist/stuff.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/stuff.c	(revision 1)
@@ -0,0 +1,13 @@
+#include "regs.h"
+#include "regs.c"
+#include "main.c"
+#include "fat.c" 
+#include "SDrive.c"
+#include "mmc.c"
+#include "spi.c"
+#include "uart.c"
+#include "led.c"
+#include "pind.c" 
+#include "eeprom.c"
+#include "pause.c"
+
Index: unmerged/zpu_firmware/mist/uart.h
===================================================================
--- unmerged/zpu_firmware/mist/uart.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/zpu_firmware/replay/HelloTinyROM.bin
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/HelloTinyROM.bin
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/HelloTinyROM_ROM.mif
===================================================================
--- unmerged/zpu_firmware/replay/HelloTinyROM_ROM.mif	(nonexistent)
+++ unmerged/zpu_firmware/replay/HelloTinyROM_ROM.mif	(revision 1)
@@ -0,0 +1,647 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
+0000 : 0b0b0b89;
+0001 : ab040b0b;
+0002 : 0b0b0b0b;
+0003 : 0b0b0b0b;
+0004 : 0b0b0b0b;
+0005 : 0b0b0b0b;
+0006 : 0b0b0b0b;
+0007 : 0b0b0b0b;
+0008 : 0b0b0b0b;
+0009 : 00000000;
+000a : 00000000;
+000b : 00000000;
+000c : 00000000;
+000d : 00000000;
+000e : 00000000;
+000f : 00000000;
+0010 : 71fd0608;
+0011 : 72830609;
+0012 : 81058205;
+0013 : 832b2a83;
+0014 : ffff0652;
+0015 : 04000000;
+0016 : 00000000;
+0017 : 00000000;
+0018 : 71fd0608;
+0019 : 83ffff73;
+001a : 83060981;
+001b : 05820583;
+001c : 2b2b0906;
+001d : 7383ffff;
+001e : 0b0b0b0b;
+001f : 83a70400;
+0020 : 72098105;
+0021 : 72057373;
+0022 : 09060906;
+0023 : 73097306;
+0024 : 070a8106;
+0025 : 53510400;
+0026 : 00000000;
+0027 : 00000000;
+0028 : 72722473;
+0029 : 732e0753;
+002a : 51040000;
+002b : 00000000;
+002c : 00000000;
+002d : 00000000;
+002e : 00000000;
+002f : 00000000;
+0030 : 71737109;
+0031 : 71068106;
+0032 : 30720a10;
+0033 : 0a720a10;
+0034 : 0a31050a;
+0035 : 81065151;
+0036 : 53510400;
+0037 : 00000000;
+0038 : 72722673;
+0039 : 732e0753;
+003a : 51040000;
+003b : 00000000;
+003c : 00000000;
+003d : 00000000;
+003e : 00000000;
+003f : 00000000;
+0040 : 00000000;
+0041 : 00000000;
+0042 : 00000000;
+0043 : 00000000;
+0044 : 00000000;
+0045 : 00000000;
+0046 : 00000000;
+0047 : 00000000;
+0048 : 0b0b0b88;
+0049 : bc040000;
+004a : 00000000;
+004b : 00000000;
+004c : 00000000;
+004d : 00000000;
+004e : 00000000;
+004f : 00000000;
+0050 : 720a722b;
+0051 : 0a535104;
+0052 : 00000000;
+0053 : 00000000;
+0054 : 00000000;
+0055 : 00000000;
+0056 : 00000000;
+0057 : 00000000;
+0058 : 72729f06;
+0059 : 0981050b;
+005a : 0b0b889f;
+005b : 05040000;
+005c : 00000000;
+005d : 00000000;
+005e : 00000000;
+005f : 00000000;
+0060 : 72722aff;
+0061 : 739f062a;
+0062 : 0974090a;
+0063 : 8106ff05;
+0064 : 06075351;
+0065 : 04000000;
+0066 : 00000000;
+0067 : 00000000;
+0068 : 71715351;
+0069 : 020d0406;
+006a : 73830609;
+006b : 81058205;
+006c : 832b0b2b;
+006d : 0772fc06;
+006e : 0c515104;
+006f : 00000000;
+0070 : 72098105;
+0071 : 72050970;
+0072 : 81050906;
+0073 : 0a810653;
+0074 : 51040000;
+0075 : 00000000;
+0076 : 00000000;
+0077 : 00000000;
+0078 : 72098105;
+0079 : 72050970;
+007a : 81050906;
+007b : 0a098106;
+007c : 53510400;
+007d : 00000000;
+007e : 00000000;
+007f : 00000000;
+0080 : 71098105;
+0081 : 52040000;
+0082 : 00000000;
+0083 : 00000000;
+0084 : 00000000;
+0085 : 00000000;
+0086 : 00000000;
+0087 : 00000000;
+0088 : 72720981;
+0089 : 05055351;
+008a : 04000000;
+008b : 00000000;
+008c : 00000000;
+008d : 00000000;
+008e : 00000000;
+008f : 00000000;
+0090 : 72097206;
+0091 : 73730906;
+0092 : 07535104;
+0093 : 00000000;
+0094 : 00000000;
+0095 : 00000000;
+0096 : 00000000;
+0097 : 00000000;
+0098 : 71fc0608;
+0099 : 72830609;
+009a : 81058305;
+009b : 1010102a;
+009c : 81ff0652;
+009d : 04000000;
+009e : 00000000;
+009f : 00000000;
+00a0 : 71fc0608;
+00a1 : 0b0b0b92;
+00a2 : b8738306;
+00a3 : 10100508;
+00a4 : 060b0b0b;
+00a5 : 88a20400;
+00a6 : 00000000;
+00a7 : 00000000;
+00a8 : 0b0b0b88;
+00a9 : fe040000;
+00aa : 00000000;
+00ab : 00000000;
+00ac : 00000000;
+00ad : 00000000;
+00ae : 00000000;
+00af : 00000000;
+00b0 : 0b0b0b88;
+00b1 : d8040000;
+00b2 : 00000000;
+00b3 : 00000000;
+00b4 : 00000000;
+00b5 : 00000000;
+00b6 : 00000000;
+00b7 : 00000000;
+00b8 : 72097081;
+00b9 : 0509060a;
+00ba : 8106ff05;
+00bb : 70547106;
+00bc : 73097274;
+00bd : 05ff0506;
+00be : 07515151;
+00bf : 04000000;
+00c0 : 72097081;
+00c1 : 0509060a;
+00c2 : 098106ff;
+00c3 : 05705471;
+00c4 : 06730972;
+00c5 : 7405ff05;
+00c6 : 06075151;
+00c7 : 51040000;
+00c8 : 05ff0504;
+00c9 : 00000000;
+00ca : 00000000;
+00cb : 00000000;
+00cc : 00000000;
+00cd : 00000000;
+00ce : 00000000;
+00cf : 00000000;
+00d0 : 810b92c8;
+00d1 : 0c510400;
+00d2 : 00000000;
+00d3 : 00000000;
+00d4 : 00000000;
+00d5 : 00000000;
+00d6 : 00000000;
+00d7 : 00718105;
+00d8 : 52040000;
+00d9 : 00000000;
+00da : 00000000;
+00db : 00000000;
+00dc : 00000000;
+00dd : 00000000;
+00de : 00000000;
+00df : 00000000;
+00e0 : 00000000;
+00e1 : 00000000;
+00e2 : 00000000;
+00e3 : 00000000;
+00e4 : 00000000;
+00e5 : 00000000;
+00e6 : 00000000;
+00e7 : 00028405;
+00e8 : 72101005;
+00e9 : 52040000;
+00ea : 00000000;
+00eb : 00000000;
+00ec : 00000000;
+00ed : 00000000;
+00ee : 00000000;
+00ef : 00000000;
+00f0 : 00000000;
+00f1 : 00000000;
+00f2 : 00000000;
+00f3 : 00000000;
+00f4 : 00000000;
+00f5 : 00000000;
+00f6 : 00000000;
+00f7 : 00717105;
+00f8 : ff057153;
+00f9 : 51020d04;
+00fa : 00000000;
+00fb : 00000000;
+00fc : 00000000;
+00fd : 00000000;
+00fe : 00000000;
+00ff : 00000000;
+0100 : 10101010;
+0101 : 10101010;
+0102 : 10101010;
+0103 : 10101010;
+0104 : 10101010;
+0105 : 10101010;
+0106 : 10101010;
+0107 : 10101053;
+0108 : 51047381;
+0109 : ff067383;
+010a : 06098105;
+010b : 83051010;
+010c : 102b0772;
+010d : fc060c51;
+010e : 51043c04;
+010f : 72728072;
+0110 : 8106ff05;
+0111 : 09720605;
+0112 : 71105272;
+0113 : 0a100a53;
+0114 : 72ed3851;
+0115 : 51535104;
+0116 : 83e08008;
+0117 : 83e08408;
+0118 : 83e08808;
+0119 : 75758f82;
+011a : 2d505083;
+011b : e0800856;
+011c : 83e0880c;
+011d : 83e0840c;
+011e : 83e0800c;
+011f : 510483e0;
+0120 : 800883e0;
+0121 : 840883e0;
+0122 : 88087575;
+0123 : 8d962d50;
+0124 : 5083e080;
+0125 : 085683e0;
+0126 : 880c83e0;
+0127 : 840c83e0;
+0128 : 800c5104;
+0129 : 00008004;
+012a : 89a80489;
+012b : a80b8cd8;
+012c : 0483e08c;
+012d : 080283e0;
+012e : 8c0cfe3d;
+012f : 0d83e08c;
+0130 : 08880508;
+0131 : 7070832b;
+0132 : 70733170;
+0133 : 822b7083;
+0134 : e08c08fc;
+0135 : 050c92d4;
+0136 : 0883e08c;
+0137 : 08fc0508;
+0138 : 710c5151;
+0139 : 51515252;
+013a : 843d0d83;
+013b : e08c0c04;
+013c : 83e08c08;
+013d : 0283e08c;
+013e : 0cff3d0d;
+013f : 800b83e0;
+0140 : 8c08fc05;
+0141 : 0c92e408;
+0142 : 51ff87c3;
+0143 : e1f0710c;
+0144 : 92e00851;
+0145 : 80710c88;
+0146 : 800a0b83;
+0147 : e08c08fc;
+0148 : 050c83e0;
+0149 : 8c08fc05;
+014a : 08818480;
+014b : 802e9e38;
+014c : 83e08c08;
+014d : fc050851;
+014e : 80713483;
+014f : e08c08fc;
+0150 : 05088105;
+0151 : 83e08c08;
+0152 : fc050cd6;
+0153 : 3992e408;
+0154 : 5185aad5;
+0155 : aad5710c;
+0156 : 92e00851;
+0157 : 85aad5aa;
+0158 : d5710c82;
+0159 : 800a0b83;
+015a : e08c08fc;
+015b : 050c83e0;
+015c : 8c08fc05;
+015d : 08848480;
+015e : 802e9e38;
+015f : 83e08c08;
+0160 : fc050851;
+0161 : 80710c83;
+0162 : e08c08fc;
+0163 : 05088405;
+0164 : 83e08c08;
+0165 : fc050cd6;
+0166 : 3992e408;
+0167 : 5180710c;
+0168 : 92e00851;
+0169 : ff87c3e1;
+016a : f0710c83;
+016b : 3d0d83e0;
+016c : 8c0c0483;
+016d : e08c0802;
+016e : 83e08c0c;
+016f : fe3d0d92;
+0170 : d0087008;
+0171 : 83e08c08;
+0172 : fc050c51;
+0173 : 83e08c08;
+0174 : 88050881;
+0175 : 2e098106;
+0176 : 953892d0;
+0177 : 0883e08c;
+0178 : 08fc0508;
+0179 : feff0670;
+017a : 720c5252;
+017b : 933992d0;
+017c : 0883e08c;
+017d : 08fc0508;
+017e : 81800770;
+017f : 720c5252;
+0180 : 843d0d83;
+0181 : e08c0c04;
+0182 : 83e08c08;
+0183 : 0283e08c;
+0184 : 0cfe3d0d;
+0185 : 92d00870;
+0186 : 0883e08c;
+0187 : 08fc050c;
+0188 : 5183e08c;
+0189 : 08880508;
+018a : 953892d0;
+018b : 0883e08c;
+018c : 08fc0508;
+018d : ffbf0670;
+018e : 720c5252;
+018f : 933992d0;
+0190 : 0883e08c;
+0191 : 08fc0508;
+0192 : 80c00770;
+0193 : 720c5252;
+0194 : 843d0d83;
+0195 : e08c0c04;
+0196 : 83e08c08;
+0197 : 0283e08c;
+0198 : 0cfd3d0d;
+0199 : 800b83e0;
+019a : 8c08fc05;
+019b : 0c800b83;
+019c : e08c08f8;
+019d : 05348151;
+019e : ff8e3f80;
+019f : 51feb43f;
+01a0 : 93b40852;
+01a1 : 807234fc;
+01a2 : e73f8151;
+01a3 : fea53f80;
+01a4 : 51fef53f;
+01a5 : ff3983e0;
+01a6 : 8c080283;
+01a7 : e08c0cf9;
+01a8 : 3d0d800b;
+01a9 : 83e08c08;
+01aa : fc050c83;
+01ab : e08c0888;
+01ac : 05088025;
+01ad : b93883e0;
+01ae : 8c088805;
+01af : 083083e0;
+01b0 : 8c088805;
+01b1 : 0c800b83;
+01b2 : e08c08f4;
+01b3 : 050c83e0;
+01b4 : 8c08fc05;
+01b5 : 088a3881;
+01b6 : 0b83e08c;
+01b7 : 08f4050c;
+01b8 : 83e08c08;
+01b9 : f4050883;
+01ba : e08c08fc;
+01bb : 050c83e0;
+01bc : 8c088c05;
+01bd : 088025b9;
+01be : 3883e08c;
+01bf : 088c0508;
+01c0 : 3083e08c;
+01c1 : 088c050c;
+01c2 : 800b83e0;
+01c3 : 8c08f005;
+01c4 : 0c83e08c;
+01c5 : 08fc0508;
+01c6 : 8a38810b;
+01c7 : 83e08c08;
+01c8 : f0050c83;
+01c9 : e08c08f0;
+01ca : 050883e0;
+01cb : 8c08fc05;
+01cc : 0c805383;
+01cd : e08c088c;
+01ce : 05085283;
+01cf : e08c0888;
+01d0 : 05085181;
+01d1 : df3f83e0;
+01d2 : 80087083;
+01d3 : e08c08f8;
+01d4 : 050c5483;
+01d5 : e08c08fc;
+01d6 : 0508802e;
+01d7 : 903883e0;
+01d8 : 8c08f805;
+01d9 : 083083e0;
+01da : 8c08f805;
+01db : 0c83e08c;
+01dc : 08f80508;
+01dd : 7083e080;
+01de : 0c54893d;
+01df : 0d83e08c;
+01e0 : 0c0483e0;
+01e1 : 8c080283;
+01e2 : e08c0cfb;
+01e3 : 3d0d800b;
+01e4 : 83e08c08;
+01e5 : fc050c83;
+01e6 : e08c0888;
+01e7 : 05088025;
+01e8 : 993883e0;
+01e9 : 8c088805;
+01ea : 083083e0;
+01eb : 8c088805;
+01ec : 0c810b83;
+01ed : e08c08fc;
+01ee : 050c83e0;
+01ef : 8c088c05;
+01f0 : 08802590;
+01f1 : 3883e08c;
+01f2 : 088c0508;
+01f3 : 3083e08c;
+01f4 : 088c050c;
+01f5 : 815383e0;
+01f6 : 8c088c05;
+01f7 : 085283e0;
+01f8 : 8c088805;
+01f9 : 0851bd3f;
+01fa : 83e08008;
+01fb : 7083e08c;
+01fc : 08f8050c;
+01fd : 5483e08c;
+01fe : 08fc0508;
+01ff : 802e9038;
+0200 : 83e08c08;
+0201 : f8050830;
+0202 : 83e08c08;
+0203 : f8050c83;
+0204 : e08c08f8;
+0205 : 05087083;
+0206 : e0800c54;
+0207 : 873d0d83;
+0208 : e08c0c04;
+0209 : 83e08c08;
+020a : 0283e08c;
+020b : 0cfd3d0d;
+020c : 810b83e0;
+020d : 8c08fc05;
+020e : 0c800b83;
+020f : e08c08f8;
+0210 : 050c83e0;
+0211 : 8c088c05;
+0212 : 0883e08c;
+0213 : 08880508;
+0214 : 27b93883;
+0215 : e08c08fc;
+0216 : 0508802e;
+0217 : ae38800b;
+0218 : 83e08c08;
+0219 : 8c050824;
+021a : a23883e0;
+021b : 8c088c05;
+021c : 081083e0;
+021d : 8c088c05;
+021e : 0c83e08c;
+021f : 08fc0508;
+0220 : 1083e08c;
+0221 : 08fc050c;
+0222 : ffb83983;
+0223 : e08c08fc;
+0224 : 0508802e;
+0225 : 80e13883;
+0226 : e08c088c;
+0227 : 050883e0;
+0228 : 8c088805;
+0229 : 0826ad38;
+022a : 83e08c08;
+022b : 88050883;
+022c : e08c088c;
+022d : 05083183;
+022e : e08c0888;
+022f : 050c83e0;
+0230 : 8c08f805;
+0231 : 0883e08c;
+0232 : 08fc0508;
+0233 : 0783e08c;
+0234 : 08f8050c;
+0235 : 83e08c08;
+0236 : fc050881;
+0237 : 2a83e08c;
+0238 : 08fc050c;
+0239 : 83e08c08;
+023a : 8c050881;
+023b : 2a83e08c;
+023c : 088c050c;
+023d : ff953983;
+023e : e08c0890;
+023f : 0508802e;
+0240 : 933883e0;
+0241 : 8c088805;
+0242 : 087083e0;
+0243 : 8c08f405;
+0244 : 0c519139;
+0245 : 83e08c08;
+0246 : f8050870;
+0247 : 83e08c08;
+0248 : f4050c51;
+0249 : 83e08c08;
+024a : f4050883;
+024b : e0800c85;
+024c : 3d0d83e0;
+024d : 8c0c0400;
+024e : 00ffffff;
+024f : ff00ffff;
+0250 : ffff00ff;
+0251 : ffffff00;
+0252 : 00000000;
+0253 : 00000000;
+0254 : 00040000;
+0255 : 00040004;
+0256 : 00040008;
+0257 : 0004000c;
+0258 : 00040010;
+0259 : 00040014;
+025a : 00040018;
+025b : 0004001c;
+025c : 00040020;
+025d : 00040024;
+025e : 00040028;
+025f : 0004002c;
+0260 : 00040040;
+0261 : 00040044;
+0262 : 00040048;
+0263 : 0004004c;
+0264 : 00040050;
+0265 : 00040054;
+0266 : 00040058;
+0267 : 0004005c;
+0268 : 00040060;
+0269 : 00040068;
+026a : 00040074;
+026b : 00040078;
+026c : 0004007c;
+026d : 0001d40e;
+026e : 0001d402;
+026f : 0001d403;
+0270 : 0001d01a;
+0271 : 0001d017;
+0272 : 0001d018;
+0273 : 0001d01b;
+0274 : 0001d20a;
+0275 : 0001d300;
+0276 : 0001d301;
+0277 : 0001d010;
+0278 : 0001d409;
+0279 : 0001d401;
+027a : 0001d400;
+027b : 0001d20f;
+END; 
Index: unmerged/zpu_firmware/replay/bootdump.c
===================================================================
--- unmerged/zpu_firmware/replay/bootdump.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/bootdump.c	(revision 1)
@@ -0,0 +1,23 @@
+unsigned char boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+
+int main(void)
+{
+	for (int i=0;i!=sizeof(boot_xex_loader);++i)
+	{
+		printf("%c",boot_xex_loader[i]);
+	}
+	return 0;
+}
+
Index: unmerged/zpu_firmware/replay/crt0.S
===================================================================
--- unmerged/zpu_firmware/replay/crt0.S	(nonexistent)
+++ unmerged/zpu_firmware/replay/crt0.S	(revision 1)
@@ -0,0 +1,974 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"crt0.S"
+	
+	
+	
+	
+;	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+; DANGER!!!! 
+; we need to align these code sections to 32 bytes, which
+; means we must not use any assembler instructions that are relaxed
+; at linker time
+; DANGER!!!! 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jsr address
+			im _memreg     	; save R0
+			load
+			im _memreg+4	; save R1
+			load
+			im _memreg+8	; save R2
+			load
+			fixedim \address
+			call
+			im _memreg+8
+			store		; restore R2
+			im _memreg+4
+			store		; restore R1
+			im _memreg
+			store		; restore R0
+	.endm
+
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+		
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+	
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+
+
+/* vectors */
+        .balign 32,0
+# offset 0x0000 0000
+		.globl _start
+_start:
+		; intSp must be 0 when we jump to _premain
+		
+		im ZPU_ID
+		loadsp 0
+		im _cpu_config
+		store
+		config
+		jmp _premain
+
+
+
+        .balign 32,0
+# offset 0x0000 0020
+		.globl _zpu_interrupt_vector
+_zpu_interrupt_vector:
+		jmp ___zpu_interrupt_vector
+
+
+        .balign 16,0
+# offset 0x0000 0030
+		.globl _memreg
+		.weak _memreg
+_memreg:
+
+
+/* instruction emulation code */
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+        .globl ___zpu_interrupt_vector
+        .weak ___zpu_interrupt_vector
+
+___zpu_interrupt_vector:
+	jsr _zpu_interrupt
+	poppc
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+

Property changes on: unmerged/zpu_firmware/replay/crt0.S
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/fat.c
===================================================================
--- unmerged/zpu_firmware/replay/fat.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/fat.c	(revision 1)
@@ -0,0 +1,445 @@
+/*! \file fat.c \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.c'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// This code is based in part on work done by Jesper Hansen for his
+//		YAMPP MP3 player project.
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#include <stdio.h>
+#include <string.h>
+
+#include "fat.h"
+#include "mmc.h"
+#include "spi.h"
+
+void USART_SendString(char *buff);
+void mmcReadCached(u32 sector);
+
+
+#define FileNameBuffer atari_sector_buffer
+extern unsigned char atari_sector_buffer[256];
+extern unsigned char mmc_sector_buffer[512];	// one sector
+extern struct GlobalSystemValues GS;
+extern struct FileInfoStruct FileInfo;			//< file information for last file accessed
+
+
+unsigned long fatClustToSect(unsigned short clust)
+{
+	u32 ret;
+	if(clust==MSDOSFSROOT)
+	{
+		debug("fatClustToSect:");
+		u32 res = (u32)((u32)(FirstDataSector) - (u32)(RootDirSectors));
+		plotnextnumber(res);
+		debug(" ");
+		plotnextnumber(FirstDataSector);
+		debug(" ");
+		plotnextnumber(RootDirSectors);
+		debug("\n");
+		return res;
+	}
+	
+	ret = (u32)(clust-2);
+	ret *= (u32)SectorsPerCluster;
+	ret += (u32)FirstDataSector;
+	return ((unsigned long)ret);
+}
+
+
+//POZOR - DEBUG !!!
+//prvne definovana promenna
+u32 debug_endofvariables;		//promenna co je v pameti jako posledni (za ni je uz jen stack)
+//POZOR - DEBUG !!!
+
+unsigned short last_dir_start_cluster;
+unsigned char last_dir_valid;
+unsigned short last_dir_entry;
+unsigned long last_dir_sector;
+unsigned char last_dir_sector_count;
+unsigned short last_dir_cluster;
+unsigned char last_dir_index;
+
+
+unsigned char fatInit()
+{
+	struct partrecord PartInfo;
+	struct bpb710 *bpb;
+
+	// Moved here since init vars are in ROM!
+	last_dir_entry=0x0;
+	last_dir_sector=0;
+	last_dir_sector_count=0;
+	last_dir_cluster=0;
+	last_dir_index=0;
+
+	// read partition table
+	// TODO.... error checking
+	debug("FAT INIT:");
+	mmcReadCached(0);
+	// map first partition record	
+	// save partition information to global PartInfo
+	PartInfo = *((struct partrecord *) ((struct partsector *) (char*)mmc_sector_buffer)->psPart);
+
+	if(mmc_sector_buffer[0x36]=='F' && mmc_sector_buffer[0x37]=='A' && mmc_sector_buffer[0x38]=='T' && mmc_sector_buffer[0x39]=='1' && mmc_sector_buffer[0x3a]=='6')
+	{
+		PartInfo.prPartType = PART_TYPE_FAT16LBA; //0x04
+		PartInfo.prStartLBA = 0x00;
+	}
+	
+	// Read the Partition BootSector
+	// **first sector of partition in PartInfo.prStartLBA
+	mmcReadCached(PartInfo.prStartLBA);
+	bpb = (struct bpb710 *) ((struct bootsector710 *) (char*)mmc_sector_buffer)->bsBPB;
+
+	// setup global disk constants
+	PartInfo.prStartLBA = 0x1e8; // FIXME
+	FirstDataSector	= PartInfo.prStartLBA;
+
+	RootDirSectors = bpb->bpbRootDirEnts>>4; // /16 ; 512/16 = 32  (sector size / max entries in one sector = number of sectors)
+
+	debug("PartInto ");
+	plotnextnumber(PartInfo.prStartLBA);
+	debug(" ");
+	plotnextnumber(bpb->bpbRootDirEnts>>4);
+	debug("\n");
+
+	// bpbFATsecs is non-zero and is therefore valid
+	FirstDataSector	+= bpb->bpbResSectors + bpb->bpbFATs * bpb->bpbFATsecs + RootDirSectors;
+
+	SectorsPerCluster	= bpb->bpbSecPerClust;
+	BytesPerSector		= bpb->bpbBytesPerSec;
+	FirstFATSector		= bpb->bpbResSectors + PartInfo.prStartLBA;
+
+	// set current directory to root (\)
+	FileInfo.vDisk.dir_cluster = MSDOSFSROOT; //RootDirStartCluster;
+
+    last_dir_start_cluster=0xffff;
+	//last_dir_valid=0;		//<-- neni potreba, protoze na zacatku fatGetDirEntry se pri zjisteni
+							//ze je (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+							//vynuluje last_dir_valid=0;
+
+	if (   PartInfo.prPartType==PART_TYPE_DOSFAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16
+		|| PartInfo.prPartType==PART_TYPE_FAT16LBA
+	   )
+	{
+		return 1; //je to ok
+		debug("OK\n");
+	}
+	else
+	{
+		return 0; //neni to zadny filesystem co umime
+		debug("FAIL\n");
+	}
+}
+
+//////////////////////////////////////////////////////////////
+
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names)
+{
+	unsigned long sector;
+	struct direntry *de = 0;	// avoid compiler warning by initializing
+	struct winentry *we;
+	unsigned char haveLongNameEntry;
+	unsigned char gotEntry;
+	unsigned short b;
+	u08 index;
+	unsigned short entrycount = 0;
+	unsigned short actual_cluster = FileInfo.vDisk.dir_cluster;
+	unsigned char seccount=0;
+
+	haveLongNameEntry = 0;
+	gotEntry = 0;
+
+	if (FileInfo.vDisk.dir_cluster!=last_dir_start_cluster)
+	{
+		//zmenil se adresar, takze musi pracovat s nim
+		//a zneplatnit last_dir polozky
+		last_dir_start_cluster=FileInfo.vDisk.dir_cluster;
+		last_dir_valid=0;
+
+		debug("LastDirStartCluster:");
+		plotnextnumber(last_dir_start_cluster);
+		plotnextnumber(last_dir_valid);
+		debug("\n");
+	}
+
+	if ( !last_dir_valid
+		 || (entry<=last_dir_entry && (entry!=last_dir_entry || last_dir_valid!=1 || use_long_names!=0))
+	   )
+	{
+		//musi zacit od zacatku
+		sector = fatClustToSect(FileInfo.vDisk.dir_cluster);
+		//index = 0;
+		debug("ReadFromBegin:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_begin;
+	}
+	else
+	{
+		//muze zacit od posledne pouzite
+		entrycount=last_dir_entry;
+		index = last_dir_index;
+		sector=last_dir_sector;
+		actual_cluster=last_dir_cluster;
+		seccount = last_dir_sector_count;
+		debug("ReadFromLastEntry:");
+		plotnextnumber(sector);
+		debug("\n");
+		goto fat_read_from_last_entry;
+	}
+
+	while(1)
+	{
+		debug("Index:");
+		plotnextnumber(index);
+		debug("\n");
+		if(index==16)	// time for next sector ?
+		{
+			if ( actual_cluster==MSDOSFSROOT )
+			{
+				//v MSDOSFSROOT se nerozlisuji clustery
+				//protoze MSDOSFSROOT ma sektory stale dal za sebou bez clusterovani
+				if (seccount>=RootDirSectors) return 0; //prekrocil maximalni pocet polozek v MSDOSFSROOT
+			}
+			else //MUSI BYT!!! (aby neporovnaval seccount je-li actual_cluster==MSDOSFSROOT)
+			if( seccount>=SectorsPerCluster )
+			{
+				//next cluster
+				//pri prechodu pres pocet sektoru v clusteru
+				actual_cluster = nextCluster(actual_cluster);
+				sector=fatClustToSect(actual_cluster);
+				seccount=0;
+			}
+fat_read_from_begin:
+			index = 0;
+			seccount++;		//ted bude nacitat dalsi sektor (musi ho zapocitat)
+fat_read_from_last_entry:
+			mmcReadCached( sector++ ); 	//prave ho nacetl
+			de = (struct direntry *) (char*)mmc_sector_buffer;
+			de+=index;
+		}
+		
+		// check the status of this directory entry slot
+		if(de->deName[0] == 0x00) //SLOT_EMPTY
+		{
+			// slot is empty and this is the end of directory
+			gotEntry = 0;
+			break;
+		}
+		else if(de->deName[0] == 0xE5)	//SLOT_DELETED
+		{
+			// this is an empty slot
+			// do nothing and move to the next one
+		}
+		else
+		{
+			// this is a valid and occupied entry
+			// is it a part of a long file/dir name?
+			if( de->deAttributes==ATTR_LONG_FILENAME )
+			{
+				// we have a long name entry
+				// cast this directory entry as a "windows" (LFN: LongFileName) entry
+				u08 i;
+				unsigned char *fnbPtr;
+
+				//pokud nechceme longname, NESMI je vubec kompletovat
+				//a preskoci na dalsi polozku
+				//( takze ani haveLongNameEntry nikdy nebude nastaveno na 1)
+				//Jinak by totiz preplacaval dalsi kusy atari_sector_bufferu 12-255 ! BACHA!!!
+				if (!use_long_names) goto fat_next_dir_entry;
+
+				we = (struct winentry *) de;
+				
+				b = WIN_ENTRY_CHARS*( (unsigned short)((we->weCnt-1) & 0x0f));		// index into string
+				fnbPtr = &FileNameBuffer[b];
+
+				for (i=0;i<5;i++)	*fnbPtr++ = we->wePart1[i*2];	// copy first part
+				for (i=0;i<6;i++)	*fnbPtr++ = we->wePart2[i*2];	// second part
+				for (i=0;i<2;i++)	*fnbPtr++ = we->wePart3[i*2];	// and third part
+
+				/*
+				{
+				//unsigned char * sptr;
+				//sptr=we->wePart1;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart1+10)); // copy first part
+				//^-- pouziti jen tohoto prvniho a druhe dva pres normalni for(..) uspori 10 bajtu,
+				//pri pouziti i dalsich dvou timto stylem uz se to ale zase prodlouzi - nechaaaaaapu!
+				//sptr=we->wePart2;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart2+12)); // second part
+				//sptr=we->wePart3;
+				//do { *fnbPtr++ = *sptr++; sptr++; } while (sptr<(we->wePart3+4));  // and third part
+				}
+				*/
+
+				if (we->weCnt & WIN_LAST) *fnbPtr = 0;				// in case dirnamelength is multiple of 13, add termination
+				if ((we->weCnt & 0x0f) == 1) haveLongNameEntry = 1;	// flag that we have a complete long name entry set
+			}
+			else
+			{
+				// we have a short name entry
+				
+				// check if this is the short name entry corresponding
+				// to the end of a multi-part long name entry
+				if(haveLongNameEntry)
+				{
+					// a long entry name has been collected
+					if(entrycount == entry)		
+					{
+						// desired entry has been found, break out
+						gotEntry = 2;
+						break;
+					}
+					// otherwise
+					haveLongNameEntry = 0;	// clear long name flag
+					entrycount++;			// increment entry counter		
+				}
+				else
+				{
+					// entry is a short name (8.3 format) without a
+					// corresponding multi-part long name entry
+
+					//Zcela vynecha adresar "." a disk label
+					if( (de->deName[0]=='.' && de->deName[1]==' ' && (de->deAttributes & ATTR_DIRECTORY) ) //je to "." adresar
+						|| (de->deAttributes & ATTR_VOLUME) ) goto fat_next_dir_entry;
+
+					if(entrycount == entry)
+					{
+						/*
+						fnbPtr = &FileNameBuffer[string_offset];
+						for (i=0;i<8;i++)	*fnbPtr++ = de->deName[i];		// copy name
+						for (i=0;i<3;i++)	*fnbPtr++ = de->deExtension[i];	// copy extension
+						*fnbPtr = 0;										// null-terminate
+						*/
+						u08 i;
+						unsigned char *dptr;
+
+						dptr = &FileNameBuffer;
+						for (i=0;i<11;i++)	*dptr++ = de->deName[i];		// copy name+ext
+						*dptr=0;	//ukonceni za nazvem
+
+						// desired entry has been found, break out
+						//pokud chtel longname, tak to neni a proto upravi 8+3 jmeno na nazev.ext
+						//aby to melo formatovani jako longname
+						if (use_long_names)
+						{
+							//upravi 'NAME    EXT' na 'NAME.EXT'
+							//(vyhazi mezery a prida tecku)
+							//krome nazvu '.          ', a '..         ', tam jen vyhaze mezery
+							unsigned char *sptr;
+							//EXT => .EXT   (posune vcetne 0x00 za koncem extenderu)
+							dptr=(FileNameBuffer+12);
+							i=4; do { sptr=dptr-1; *dptr=*sptr; dptr=sptr; i--; } while(i>0);
+							if (FileNameBuffer[0]!='.') *dptr='.'; //jen pro jine nez '.' a '..'
+							//NAME    .EXT => NAME.EXT
+							sptr=dptr=&FileNameBuffer;
+							do
+							{
+							 if ((*sptr)!=' ') *dptr++=*sptr;
+							 sptr++;
+							} while (*sptr);
+							*dptr=0; //ukonceni
+						}
+						//
+						gotEntry = 1;
+						break;
+					}
+					// otherwise
+					entrycount++;			// increment entry counter		
+				}
+			}
+		}
+fat_next_dir_entry:
+		// next directory entry
+		de++;
+		// next index
+		index++;
+	}
+	
+	// we have a file/dir to return
+	// store file/dir starting cluster (start of data)
+	FileInfo.vDisk.start_cluster = (unsigned short) (de->deStartCluster);
+	// fileindex
+	FileInfo.vDisk.file_index = entry;	//fileindex teto polozky
+	// store file/dir size (note: size field for subdirectory entries is always zero)
+	FileInfo.vDisk.size = de->deFileSize;
+	// store file/dir attributes
+	FileInfo.Attr = de->deAttributes;
+	// store file/dir last update time
+	FileInfo.Time = (unsigned short) (de->deMTime[0] | de->deMTime[1]<<8);
+	// store file/dir last update date
+	FileInfo.Date = (unsigned short) (de->deMDate[0] | de->deMDate[1]<<8);
+
+	if(gotEntry)
+	{
+		debug(" gotEntry ");
+		last_dir_entry = entrycount;
+		last_dir_index = index;
+		last_dir_sector = sector-1; //protoze ihned po nacteni se posune
+		last_dir_cluster = actual_cluster;
+		last_dir_sector_count = seccount; //skace se az za inkrementaci seccount, takze tady se 1 neodecita!
+		last_dir_valid=gotEntry;
+	}
+	else
+	{
+		debug(" not gotEntry ");
+	}
+
+	return gotEntry;
+}
+
+
+unsigned short nextCluster(unsigned short cluster)
+{
+	  unsigned short nextCluster;
+	  unsigned long fatOffset;
+	  unsigned long sector;
+	  unsigned long offset;
+
+	  // two FAT bytes (16 bits) for every cluster
+	  fatOffset = ((u32)cluster) << 1;
+
+	  // calculate the FAT sector that we're interested in
+	  sector = FirstFATSector + (fatOffset / ((u32)BytesPerSector));
+	  // calculate offset of the our entry within that FAT sector
+	  offset = fatOffset % ((u32)BytesPerSector);
+
+	  // if we don't already have this FAT chunk loaded, go get it
+	  // read sector of FAT table
+  	  mmcReadCached( sector );
+
+	  // read the nextCluster value
+	  nextCluster = (*((unsigned short*) &((char*)mmc_sector_buffer)[offset])) & FAT16_MASK;
+
+	  // check to see if we're at the end of the chain
+	  if (nextCluster == (CLUST_EOFE & FAT16_MASK))
+		nextCluster = 0;
+
+	return (nextCluster&0xFFFF);
+}
Index: unmerged/zpu_firmware/replay/HelloTinyROM.elf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/HelloTinyROM.elf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/a.out
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/a.out
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/changes
===================================================================
--- unmerged/zpu_firmware/replay/changes	(nonexistent)
+++ unmerged/zpu_firmware/replay/changes	(revision 1)
@@ -0,0 +1,32 @@
+Only in .: ¬
+Only in .: ¬!
+Only in .: 1
+Only in .: a.out
+Only in .: bootdump
+Only in .: bootloader
+Only in .: changes
+Only in .: chksum.c
+Only in .: crt0.S
+Only in .: defunct
+Only in .: DOCS
+Only in .: ._.DS_Store
+Only in .: fat.c
+Only in .: fat.h
+Only in .: HelloTinyROM.bin
+Only in .: HelloTinyROM.elf
+Only in .: HelloTinyROM.rpt
+Only in .: mt6502dis
+Only in .: SDrive081012
+Only in .: SDrive081012.zip
+Only in .: SDrive20090403
+Only in .: SDrive20090403.zip
+Only in .: sdrive_hias
+Only in .: sdrive-hias-090705.zip
+Only in .: stuff.c
+Only in ../../../replay/src/hw/replay/cores/atari_800/zpu/: .svn
+Only in .: SW
+Only in .: test
+Only in .: test2
+Only in .: test.c
+Only in .: zpu_obj
+Only in .: zpuromgen
Index: unmerged/zpu_firmware/replay/debug.h
===================================================================
--- unmerged/zpu_firmware/replay/debug.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/debug.h	(revision 1)
@@ -0,0 +1,20 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debugoffset(int x);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/zpu_firmware/replay/integer.h
===================================================================
--- unmerged/zpu_firmware/replay/integer.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/zpu_firmware/mist/HelloTinyROM.elf
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/HelloTinyROM.elf
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/a.out
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/a.out
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/changes
===================================================================
--- unmerged/zpu_firmware/mist/changes	(nonexistent)
+++ unmerged/zpu_firmware/mist/changes	(revision 1)
@@ -0,0 +1,32 @@
+Only in .: ¬
+Only in .: ¬!
+Only in .: 1
+Only in .: a.out
+Only in .: bootdump
+Only in .: bootloader
+Only in .: changes
+Only in .: chksum.c
+Only in .: crt0.S
+Only in .: defunct
+Only in .: DOCS
+Only in .: ._.DS_Store
+Only in .: fat.c
+Only in .: fat.h
+Only in .: HelloTinyROM.bin
+Only in .: HelloTinyROM.elf
+Only in .: HelloTinyROM.rpt
+Only in .: mt6502dis
+Only in .: SDrive081012
+Only in .: SDrive081012.zip
+Only in .: SDrive20090403
+Only in .: SDrive20090403.zip
+Only in .: sdrive_hias
+Only in .: sdrive-hias-090705.zip
+Only in .: stuff.c
+Only in ../../../replay/src/hw/replay/cores/atari_800/zpu/: .svn
+Only in .: SW
+Only in .: test
+Only in .: test2
+Only in .: test.c
+Only in .: zpu_obj
+Only in .: zpuromgen
Index: unmerged/zpu_firmware/mist/debug.h
===================================================================
--- unmerged/zpu_firmware/mist/debug.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/debug.h	(revision 1)
@@ -0,0 +1,20 @@
+#ifndef debug_h
+#define debug_h
+
+void topofscreen();
+void setxpos(int val);
+void setypos(int val);
+unsigned char toatarichar(int val);
+unsigned char hextoatarichar(int val);
+void plot(unsigned char val, int x, int y);
+void plotnext(unsigned char val);
+void plotnextnumber(unsigned short val);
+void debugoffset(int x);
+void debug(char const * str);
+
+void hexdump(char const * str, int length);
+void hexdump_pure(char const * str, int length);
+
+void initdebug(int onoff_in);
+
+#endif //debug_h
Index: unmerged/zpu_firmware/mist/integer.h
===================================================================
--- unmerged/zpu_firmware/mist/integer.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/integer.h	(revision 1)
@@ -0,0 +1,37 @@
+/*-------------------------------------------*/
+/* Integer type definitions for FatFs module */
+/*-------------------------------------------*/
+
+#ifndef _INTEGER
+#define _INTEGER
+
+#ifdef _WIN32	/* FatFs development platform */
+
+#include <windows.h>
+#include <tchar.h>
+
+#else			/* Embedded platform */
+
+/* These types must be 16-bit, 32-bit or larger integer */
+typedef int				INT;
+typedef unsigned int	UINT;
+
+/* These types must be 8-bit integer */
+typedef char			CHAR;
+typedef unsigned char	UCHAR;
+typedef unsigned char	BYTE;
+
+/* These types must be 16-bit integer */
+typedef short			SHORT;
+typedef unsigned short	USHORT;
+typedef unsigned short	WORD;
+typedef unsigned short	WCHAR;
+
+/* These types must be 32-bit integer */
+typedef long			LONG;
+typedef unsigned long	ULONG;
+typedef unsigned long	DWORD;
+
+#endif
+
+#endif
Index: unmerged/zpu_firmware/mist/uart.c
===================================================================
--- unmerged/zpu_firmware/mist/uart.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/mist/zpuromgen.c
===================================================================
--- unmerged/zpu_firmware/mist/zpuromgen.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/zpu_firmware/replay/HelloTinyROM.rpt
===================================================================
--- unmerged/zpu_firmware/replay/HelloTinyROM.rpt	(nonexistent)
+++ unmerged/zpu_firmware/replay/HelloTinyROM.rpt	(revision 1)
@@ -0,0 +1,3 @@
+End of code:	000009f0 g       *ABS*	00000000 _romend
+Start of BSS:	0000f000 g       .bss	00000000 __bss_start__
+End of BSS:	0000f010 g       *ABS*	00000000 __bss_end__
Index: unmerged/zpu_firmware/replay/bootdump
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/bootdump
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/chksum.c
===================================================================
--- unmerged/zpu_firmware/replay/chksum.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/chksum.c	(revision 1)
@@ -0,0 +1,40 @@
+unsigned char abuffer[] = {
+0x00,0x03,0x00,0x07,0x14,0x07,0x4c,0x14,0x07,0x74,0x0d,0x00,0x00,0xa9,0x46,0x8d
+,0xc6,0x02,0xd0,0xfe,0xa0,0x00,0xa9,0x6b,0x91,0x58,0x20,0xd9,0x07,0xb0,0xee,0x20
+,0xc4,0x07,0xad,0x7a,0x08,0x0d,0x76,0x08,0xd0,0xe3,0xa5,0x80,0x8d,0xe0,0x02,0xa5
+,0x81,0x8d,0xe1,0x02,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20,0xeb,0x07,0xb0
+,0xcc,0xa0,0x00,0x91,0x80,0xa5,0x80,0xc5,0x82,0xd0,0x06,0xa5,0x81,0xc5,0x83,0xf0
+,0x08,0xe6,0x80,0xd0,0x02,0xe6,0x81,0xd0,0xe3,0xad,0x76,0x08,0xd0,0xaf,0xad,0xe2
+,0x02,0x8d,0x70,0x07,0x0d,0xe3,0x02,0xf0,0x0e,0xad,0xe3,0x02,0x8d,0x71,0x07,0x20
+,0xff,0xff,0xad,0x7a,0x08,0xd0,0x13,0xa9,0x00,0x8d,0xe2,0x02,0x8d,0xe3,0x02,0x20
+};
+
+
+unsigned char buffer[] = {
+0x98,0xff,0xe0,0x00
+};
+
+typedef unsigned short u16;
+typedef unsigned char u08;
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+        u16 i;
+        u08 sumo,sum;
+        sum=sumo=0;
+        for(i=0;i<len;i++)
+        {
+                sum+=buffer[i];
+                if(sum<sumo) sum++;
+                sumo = sum;
+        }
+        return sum;
+}
+
+int main(void)
+{
+	int res = get_checksum(buffer,sizeof(buffer));
+	printf("%x %d\n",res,sizeof(buffer));
+	return 0;
+}
+
Index: unmerged/zpu_firmware/replay/diskio.h
===================================================================
--- unmerged/zpu_firmware/replay/diskio.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/diskio.h	(revision 1)
@@ -0,0 +1,41 @@
+/*-----------------------------------------------------------------------
+/  PFF - Low level disk interface modlue include file    (C)ChaN, 2009
+/-----------------------------------------------------------------------*/
+
+#ifndef _DISKIO
+
+#include "integer.h"
+
+
+/* Status of Disk Functions */
+typedef BYTE	DSTATUS;
+
+
+/* Results of Disk Functions */
+typedef enum {
+	RES_OK = 0,		/* 0: Function succeeded */
+	RES_ERROR,		/* 1: Disk error */
+	RES_NOTRDY,		/* 2: Not ready */
+	RES_PARERR		/* 3: Invalid parameter */
+} DRESULT;
+
+
+/*---------------------------------------*/
+/* Prototypes for disk control functions */
+
+DSTATUS disk_initialize (void);
+DRESULT disk_readp (BYTE*, DWORD, WORD, WORD);
+DRESULT disk_writep (const BYTE*, DWORD);
+
+#define STA_NOINIT		0x01	/* Drive not initialized */
+#define STA_NODISK		0x02	/* No medium in the drive */
+
+/* Card type flags (CardType) */
+#define CT_MMC				0x01	/* MMC ver 3 */
+#define CT_SD1				0x02	/* SD ver 1 */
+#define CT_SD2				0x04	/* SD ver 2 */
+#define CT_SDC				(CT_SD1|CT_SD2)	/* SD */
+#define CT_BLOCK			0x08	/* Block addressing */
+
+#define _DISKIO
+#endif
Index: unmerged/zpu_firmware/replay/mt6502dis
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/mt6502dis
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/led.c
===================================================================
--- unmerged/zpu_firmware/replay/led.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/led.c	(revision 1)
@@ -0,0 +1,20 @@
+#include "led.h"
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+	*zpu_ledg = i;
+}
+void set_red_led(int i)
+{
+	*zpu_ledr = i;
+}
+void set_drive_number(int i)
+{
+	*zpu_hex = i;
+}
+void init_display()
+{
+	*zpu_hex = 0;
+}
Index: unmerged/zpu_firmware/replay/mycrt0.s
===================================================================
--- unmerged/zpu_firmware/replay/mycrt0.s	(nonexistent)
+++ unmerged/zpu_firmware/replay/mycrt0.s	(revision 1)
@@ -0,0 +1,976 @@
+/* Startup code for ZPU
+   Copyright (C) 2005 Free Software Foundation, Inc.
+
+This file is free software; you can redistribute it and/or modify it
+under the terms of the GNU General Public License as published by the
+Free Software Foundation; either version 2, or (at your option) any
+later version.
+
+In addition to the permissions in the GNU General Public License, the
+Free Software Foundation gives you unlimited permission to link the
+compiled version of this file with other programs, and to distribute
+those programs without any restriction coming from the use of this
+file.  (The General Public License restrictions do apply in other
+respects; for example, they cover modification of the file, and
+distribution when not linked into another program.)
+
+This file is distributed in the hope that it will be useful, but
+WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+	.file	"mincrt0.S"
+
+
+/* Minimal startup code, usable where the core is complete enough not to require emulated instructions */
+	
+
+	.section ".fixed_vectors","ax"
+; KLUDGE!!! we remove the executable bit to avoid relaxation 
+	.section ".fixed_vectors","a" 
+
+	.macro fixedim value
+			im \value
+	.endm
+
+	.macro  jmp address
+			fixedim \address
+			poppc
+	.endm
+
+	.macro fast_neg
+	not
+	im 1
+	add
+	.endm
+
+	.macro mult1bit
+	; create mask of lowest bit in A
+	loadsp 8 ; A
+	im 1
+	and
+	im -1
+	add
+	not
+	loadsp 8 ; B
+	and 
+	add ; accumulate in C
+	
+	; shift B left 1 bit
+	loadsp 4 ; B
+	addsp 0
+	storesp 8 ; B
+	
+	; shift A right 1 bit
+	loadsp 8 ; A
+	flip
+	addsp 0
+	flip
+	storesp 12 ; A
+	.endm
+
+	.macro cimpl funcname
+	; save R0
+	im _memreg
+	load
+	
+	; save R1
+	im _memreg+4
+	load
+	
+	; save R2
+	im _memreg+8
+	load
+	
+	loadsp 20
+	loadsp 20
+	
+	fixedim \funcname
+	call
+
+	; destroy arguments on stack
+	storesp 0
+	storesp 0	
+	 
+	im _memreg
+	load
+	
+	; poke the result into the right slot
+	storesp 24
+
+	; restore R2
+	im _memreg+8
+	store
+	
+	; restore R1
+	im _memreg+4
+	store
+	
+	; restore r0
+	im _memreg
+	store
+	
+	
+	storesp 4
+	poppc
+	.endm
+
+
+		.globl _start
+_start:
+		jmp _premain
+
+/* vectors */
+/* instruction emulation code */
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+        nop
+        nop
+	nop
+        nop
+        nop
+        nop
+
+# opcode 34
+# offset 0x0000 0040
+	.balign 32,0
+_loadh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mult 8	
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	; shift right addr&3 * 8
+	lshiftright
+	im 0xffff
+	and
+	storesp 8
+	
+	poppc
+
+# opcode 35
+# offset 0x0000 0060
+	.balign 32,0
+_storeh:
+	loadsp 4
+	; by not masking out bit 0, we cause a memory access error 
+	; on unaligned access
+	im ~0x2
+	and
+	load
+
+	; mask
+	im 0xffff
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	ashiftleft
+	not
+
+	and
+
+	loadsp 12
+	im 0xffff
+
+	nop
+		
+	fixedim _storehtail
+	poppc
+
+
+# opcode 36
+# offset 0x0000 0080
+	.balign 32,0
+_lessthan:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+
+	; DANGER!!!!
+	; 0x80000000 will overflow when negated, so we need to mask
+	; the result above with the compare positive to negative
+	; number case
+	loadsp 12
+	loadsp 12
+	not
+	and
+	not
+	and
+
+
+	; handle case where we are comparing a negative number
+	; and positve number. This can underflow. E.g. consider 0x8000000 < 0x1000
+	loadsp 12
+	not
+	loadsp 12
+	and
+	
+	or
+
+
+
+	flip
+	im 1
+	and	
+
+	
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 37
+# offset 0x0000 00a0
+	.balign 32,0
+_lessthanorequal:
+	loadsp 8
+	loadsp 8
+	lessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+	
+# opcode 38
+# offset 0x0000 00c0
+	.balign 32,0
+_ulessthan:
+	; fish up arguments 
+	loadsp 4
+	loadsp 12
+	
+	/* low: -1 if low bit dif is negative 0 otherwise:  neg (not x&1 and (y&1))
+		x&1		y&1		neg (not x&1 and (y&1))
+		1		1		0
+		1		0 		0
+		0		1		-1
+		0		0		0
+	
+	*/
+	loadsp 4 
+	not
+	loadsp 4
+	and
+	im 1
+	and
+	neg
+	
+	
+	/* high: upper 31-bit diff is only wrong when diff is 0 and low=-1
+		high=x>>1 - y>>1 + low
+		
+		extremes
+		
+		0000 - 1111:
+		low= neg(not 0 and 1) = 1111 (-1)
+		high=000+ neg(111) +low = 000 + 1001 + low = 1000 
+		OK
+		
+		1111 - 0000
+		low=neg(not 1 and 0) = 0
+		high=111+neg(000) + low = 0111
+		OK
+		 
+		
+	 */
+	loadsp 8
+	
+	flip 
+	addsp 0
+	flip
+	
+	loadsp 8
+	
+	flip	
+	addsp 0
+	flip
+
+	sub
+
+	; if they are equal, then the last bit decides...	
+	add
+	
+	/* test if negative: result = flip(diff) & 1 */
+	flip
+	im 1
+	and
+
+	; destroy a&b which are on stack	
+	storesp 4
+	storesp 4
+	
+	storesp 12
+	storesp 4
+	poppc			
+
+# opcode 39
+# offset 0x0000 00e0
+	.balign 32,0
+_ulessthanorequal:
+	loadsp 8
+	loadsp 8
+	ulessthan
+	loadsp 12
+	loadsp 12
+	eq
+	or
+	
+	storesp 12
+	storesp 4
+	poppc
+
+
+# opcode 40
+# offset 0x0000 0100
+	.balign 32,0
+	.globl _swap
+_swap:
+	breakpoint ; tbd
+
+# opcode 41
+# offset 0x0000 0120
+	.balign 32,0
+_slowmult:
+	im _slowmultImpl
+	poppc
+
+# opcode 42
+# offset 0x0000 0140
+	.balign 32,0
+_lshiftright:
+	loadsp 8
+	flip
+
+	loadsp 8
+	ashiftleft
+	flip
+	
+	storesp 12
+	storesp 4
+
+	poppc
+	
+
+# opcode 43
+# offset 0x0000 0160
+	.balign 32,0
+_ashiftleft:
+	loadsp 8
+	
+	loadsp 8
+	im 0x1f
+	and
+	fast_neg
+	im _ashiftleftEnd
+	add
+	poppc
+	
+	
+	
+# opcode 44
+# offset 0x0000 0180
+	.balign 32,0
+_ashiftright:
+	loadsp 8
+	loadsp 8
+	lshiftright
+	
+	; handle signed value
+	im -1
+	loadsp 12
+	im 0x1f
+	and
+	lshiftright
+	not	; now we have an integer on the stack with the signed 
+		; bits in the right position
+
+	; mask these bits with the signed bit.
+	loadsp 16
+	not
+	flip
+	im 1
+	and
+	im -1
+	add
+	
+	and	
+	
+	; stuff in the signed bits...
+	or
+	
+	; store result into correct stack slot	
+	storesp 12
+	
+	; move up return value 
+	storesp 4
+	poppc
+
+# opcode 45
+# offset 0x0000 01a0
+	.balign 32,0
+_call:
+	; fn
+	loadsp 4
+	
+	; return address
+	loadsp 4
+
+	; store return address
+	storesp 12
+	
+	; fn to call
+	storesp 4
+	
+	pushsp	; flush internal stack
+	popsp
+		
+	poppc
+
+_storehtail:
+
+	and
+	loadsp 12
+	im 3
+	and
+	fast_neg
+	im 2
+	add
+	im 3
+	ashiftleft
+	nop
+	ashiftleft
+	
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+
+
+# opcode 46
+# offset 0x0000 01c0
+	.balign 32,0
+_eq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+	
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 47
+# offset 0x0000 01e0
+	.balign 32,0
+_neq:
+	loadsp 8
+	fast_neg
+	loadsp 8
+	add
+	
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+
+	not
+
+	im 1
+	and
+		
+	storesp 12
+	storesp 4
+	poppc
+	
+
+# opcode 48
+# offset 0x0000 0200
+	.balign 32,0
+_neg:
+	loadsp 4
+	not
+	im 1
+	add
+	storesp 8
+	
+	poppc
+	
+
+# opcode 49
+# offset 0x0000 0220
+	.balign 32,0
+_sub:
+	loadsp 8
+	loadsp 8
+	fast_neg
+	add
+	storesp 12
+
+	storesp 4
+
+	poppc
+
+
+# opcode 50
+# offset 0x0000 0240
+	.balign 32,0
+_xor:
+	loadsp 8
+	not
+	loadsp 8
+	and
+	
+	loadsp 12
+	loadsp 12
+	not
+	and
+
+	or
+
+	storesp 12
+	storesp 4
+	poppc
+
+# opcode 51
+# offset 0x0000 0260
+	.balign 32,0
+_loadb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	loadsp 8
+	im 3
+	and
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	lshiftright
+
+	im 0xff
+	and
+	storesp 8
+	
+	poppc
+
+
+# opcode 52
+# offset 0x0000 0280
+	.balign 32,0
+_storeb:
+	loadsp 4
+	im ~0x3
+	and
+	load
+
+	; mask away destination
+	im _mask
+	loadsp 12
+	im 3
+	and
+	addsp 0
+	addsp 0
+	add
+	load
+
+	and
+
+
+	im _storebtail
+	poppc
+	
+# opcode 53
+# offset 0x0000 02a0
+	.balign 32,0
+_div:
+	jmp ___div
+	
+# opcode 54
+# offset 0x0000 02c0
+	.balign 32,0
+_mod:
+	jmp ___mod
+
+# opcode 55
+# offset 0x0000 02e0
+	.balign 32,0
+	.globl _eqbranch
+_eqbranch:
+	loadsp 8
+	
+	; eq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; subtract 1 to find PC of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+
+# opcode 56
+# offset 0x0000 0300
+	.balign 32,0
+	.globl _neqbranch
+_neqbranch:
+	loadsp 8
+	
+	; neq
+
+	not 
+	loadsp 0
+	im 1
+	add
+	not
+	and
+	flip
+	
+	not
+	
+	im 1
+	and
+
+	; mask
+	im -1
+	add
+	loadsp 0
+	storesp 16
+
+	; no branch address
+	loadsp 4
+	
+	and
+
+	; fetch boolean & neg mask
+	loadsp 12
+	not
+	
+	; calc address & mask for branch
+	loadsp 8
+	loadsp 16
+	add
+	; find address of branch instruction
+	im -1
+	add
+	
+	and
+
+	or	
+	
+	storesp 4
+	storesp 4
+	storesp 4
+	poppc	
+
+# opcode 57
+# offset 0x0000 0320
+	.balign 32,0
+	.globl _poppcrel
+_poppcrel:
+	add
+	; address of poppcrel
+	im -1
+	add
+	poppc
+		
+# opcode 58
+# offset 0x0000 0340
+	.balign 32,0
+	.globl _config
+_config:
+	im 1 
+	nop
+	im _hardware
+	store
+	storesp 4
+	poppc
+
+# opcode 59
+# offset 0x0000 0360
+	.balign 32,0
+_pushpc:
+	loadsp 4
+	im 1
+	add 
+	storesp 8
+	poppc
+	
+# opcode 60
+# offset 0x0000 0380
+	.balign 32,0
+_syscall_emulate:
+	.byte 0
+	
+# opcode 61
+# offset 0x0000 03a0
+	.balign 32,0
+_pushspadd:
+	pushsp
+	im 4
+	add
+	loadsp 8
+	addsp 0
+	addsp 0
+	add
+	storesp 8
+	
+	poppc
+
+# opcode 62
+# offset 0x0000 03c0
+	.balign 32,0
+_halfmult:
+	breakpoint
+	
+# opcode 63
+# offset 0x0000 03e0
+	.balign 32,0
+_callpcrel:
+	loadsp 4
+	loadsp 4
+	add
+	im -1
+	add
+	loadsp 4
+	
+	storesp 12	; return address
+	storesp 4 
+	pushsp		; this will flush the internal stack.
+	popsp
+	poppc
+
+	.text
+
+	
+
+
+_ashiftleftBegin:
+	.rept 0x1f
+	addsp 0
+	.endr
+_ashiftleftEnd:
+	storesp 12
+	storesp 4
+	poppc
+	
+_storebtail:
+	loadsp 12
+	im 0xff
+	and
+	loadsp 12
+	im 3
+	and
+
+	fast_neg
+	im 3
+	add
+	; x8
+	addsp 0
+	addsp 0
+	addsp 0
+
+	ashiftleft
+	 
+	or
+	
+	loadsp 8
+	im  ~0x3
+	and
+
+	store
+	
+	storesp 4
+	storesp 4
+	poppc
+	
+
+
+
+; NB! this is not an EMULATE instruction. It is a varargs fn.
+	.globl _syscall	
+_syscall:
+	syscall
+	poppc
+	
+_slowmultImpl:
+	
+	loadsp 8 ; A
+	loadsp 8 ; B
+	im 0 ; C
+
+.LmoreMult:
+	mult1bit
+	
+	; cutoff
+	loadsp 8
+	.byte (.LmoreMult-.Lbranch)&0x7f+0x80
+.Lbranch:
+	neqbranch
+
+	storesp 4
+	storesp 4
+	storesp 12
+	storesp 4
+	poppc
+
+___mod:
+	cimpl __modsi3
+___div:
+	cimpl __divsi3
+
+	.section ".rodata"
+	.balign 4,0
+_mask:
+	.long 0x00ffffff
+	.long 0xff00ffff
+	.long 0xffff00ff
+	.long 0xffffff00
+
+	.section ".text","ax"
+	.global _boot
+	.balign 4,0
+_boot:
+	im 0
+	poppc
+
+	.global _break;
+_break:
+	im	_break
+	poppc ; infinite loop
+
+_premain:
+	im _break
+	nop
+	fixedim main
+	poppc
+
+
+	.data
+	.balign 4,0
+	
+	.globl _hardware
+_hardware:
+	.long 0
+	.globl _cpu_config
+_cpu_config:
+	.long 0
+
+
+	.section ".bss"
+    .balign 4,0
+	.globl _memreg
+_memreg:
+		.long 0
+		.long 0
+		.long 0
+		.long 0
+
Index: unmerged/zpu_firmware/replay/led.h
===================================================================
--- unmerged/zpu_firmware/replay/led.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/led.h	(revision 1)
@@ -0,0 +1,10 @@
+#ifndef LEDS_H
+#define LEDS_H
+
+void set_green_led(int i);
+void set_red_led(int i);
+void set_drive_number(int i);
+void init_display();
+
+#endif
+
Index: unmerged/zpu_firmware/replay/pff.h
===================================================================
--- unmerged/zpu_firmware/replay/pff.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/zpu_firmware/mist/mt6502dis
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/mist/mt6502dis
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/mist/pff.h
===================================================================
--- unmerged/zpu_firmware/mist/pff.h	(nonexistent)
+++ unmerged/zpu_firmware/mist/pff.h	(revision 1)
@@ -0,0 +1,192 @@
+/*---------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module include file  R0.02a   (C)ChaN, 2010
+/----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/----------------------------------------------------------------------------*/
+
+#include "integer.h"
+
+/*---------------------------------------------------------------------------/
+/ Petit FatFs Configuration Options
+/
+/ CAUTION! Do not forget to make clean the project after any changes to
+/ the configuration options.
+/
+/----------------------------------------------------------------------------*/
+#ifndef _FATFS
+#define _FATFS
+
+#define	_USE_READ	1	/* 1:Enable pf_read() */
+
+#define	_USE_DIR	1	/* 1:Enable pf_opendir() and pf_readdir() */
+
+#define	_USE_LSEEK	1	/* 1:Enable pf_lseek() */
+
+#define	_USE_WRITE	0	/* 1:Enable pf_write() */
+
+#define _FS_FAT12	1	/* 1:Enable FAT12 support */
+#define _FS_FAT32	1	/* 1:Enable FAT32 support */
+
+
+#define	_CODE_PAGE	1
+/* Defines which code page is used for path name. Supported code pages are:
+/  932, 936, 949, 950, 437, 720, 737, 775, 850, 852, 855, 857, 858, 862, 866,
+/  874, 1250, 1251, 1252, 1253, 1254, 1255, 1257, 1258 and 1 (ASCII only).
+/  SBCS code pages except for 1 requiers a case conversion table. This
+/  might occupy 128 bytes on the RAM on some platforms, e.g. avr-gcc. */
+
+
+#define _WORD_ACCESS	0
+/* The _WORD_ACCESS option defines which access method is used to the word
+/  data in the FAT structure.
+/
+/   0: Byte-by-byte access. Always compatible with all platforms.
+/   1: Word access. Do not choose this unless following condition is met.
+/
+/  When the byte order on the memory is big-endian or address miss-aligned
+/  word access results incorrect behavior, the _WORD_ACCESS must be set to 0.
+/  If it is not the case, the value can also be set to 1 to improve the
+/  performance and code efficiency. */
+
+
+/* End of configuration options. Do not change followings without care.     */
+/*--------------------------------------------------------------------------*/
+
+
+
+#if _FS_FAT32
+#define	CLUST	DWORD
+#else
+#define	CLUST	WORD
+#endif
+
+
+/* File system object structure */
+
+typedef struct {
+	BYTE	fs_type;	/* FAT sub type */
+	BYTE	flag;		/* File status flags */
+	BYTE	csize;		/* Number of sectors per cluster */
+	BYTE	pad1;
+	WORD	n_rootdir;	/* Number of root directory entries (0 on FAT32) */
+	CLUST	n_fatent;	/* Number of FAT entries (= number of clusters + 2) */
+	DWORD	fatbase;	/* FAT start sector */
+	DWORD	dirbase;	/* Root directory start sector (Cluster# on FAT32) */
+	DWORD	database;	/* Data start sector */
+	DWORD	fptr;		/* File R/W pointer */
+	DWORD	fsize;		/* File size */
+	CLUST	org_clust;	/* File start cluster */
+	CLUST	curr_clust;	/* File current cluster */
+	DWORD	dsect;		/* File current data sector */
+} FATFS;
+
+
+
+/* Directory object structure */
+
+typedef struct {
+	WORD	index;		/* Current read/write index number */
+	BYTE*	fn;			/* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
+	CLUST	sclust;		/* Table start cluster (0:Static table) */
+	CLUST	clust;		/* Current cluster */
+	DWORD	sect;		/* Current sector */
+} DIR;
+
+
+
+/* File status structure */
+
+typedef struct {
+	DWORD	fsize;		/* File size */
+	WORD	fdate;		/* Last modified date */
+	WORD	ftime;		/* Last modified time */
+	BYTE	fattrib;	/* Attribute */
+	char	fname[13];	/* File name */
+} FILINFO;
+
+
+
+/* File function return code (FRESULT) */
+
+typedef enum {
+	FR_OK = 0,			/* 0 */
+	FR_DISK_ERR,		/* 1 */
+	FR_NOT_READY,		/* 2 */
+	FR_NO_FILE,			/* 3 */
+	FR_NO_PATH,			/* 4 */
+	FR_NOT_OPENED,		/* 5 */
+	FR_NOT_ENABLED,		/* 6 */
+	FR_NO_FILESYSTEM	/* 7 */
+} FRESULT;
+
+
+
+/*--------------------------------------------------------------*/
+/* Petit FatFs module application interface                     */
+
+FRESULT pf_mount (FATFS*);						/* Mount/Unmount a logical drive */
+FRESULT pf_open (const char*);					/* Open a file */
+FRESULT pf_read (void*, WORD, WORD*);			/* Read data from the open file */
+FRESULT pf_write (const void*, WORD, WORD*);	/* Write data to the open file */
+FRESULT pf_lseek (DWORD);						/* Move file pointer of the open file */
+FRESULT pf_opendir (DIR*, const char*);			/* Open a directory */
+FRESULT pf_readdir (DIR*, FILINFO*);			/* Read a directory item from the open directory */
+
+
+
+/*--------------------------------------------------------------*/
+/* Flags and offset address                                     */
+
+/* File status flag (FATFS.flag) */
+
+#define	FA_OPENED	0x01
+#define	FA_WPRT		0x02
+#define	FA__WIP		0x40
+
+
+/* FAT sub type (FATFS.fs_type) */
+
+#define FS_FAT12	1
+#define FS_FAT16	2
+#define FS_FAT32	3
+
+
+/* File attribute bits for directory entry */
+
+#define	AM_RDO	0x01	/* Read only */
+#define	AM_HID	0x02	/* Hidden */
+#define	AM_SYS	0x04	/* System */
+#define	AM_VOL	0x08	/* Volume label */
+#define AM_LFN	0x0F	/* LFN entry */
+#define AM_DIR	0x10	/* Directory */
+#define AM_ARC	0x20	/* Archive */
+#define AM_MASK	0x3F	/* Mask of defined bits */
+
+
+/*--------------------------------*/
+/* Multi-byte word access macros  */
+
+#if _WORD_ACCESS == 1	/* Enable word access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(*(WORD*)(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(*(DWORD*)(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(WORD*)(BYTE*)(ptr)=(WORD)(val)
+#define	ST_DWORD(ptr,val)	*(DWORD*)(BYTE*)(ptr)=(DWORD)(val)
+#else					/* Use byte-by-byte access to the FAT structure */
+#define	LD_WORD(ptr)		(WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr))
+#define	LD_DWORD(ptr)		(DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr))
+#define	ST_WORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8)
+#define	ST_DWORD(ptr,val)	*(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24)
+#endif
+
+
+#endif /* _FATFS */
Index: unmerged/zpu_firmware/mist/rom_prologue.vhd
===================================================================
--- unmerged/zpu_firmware/mist/rom_prologue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/mist/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/zpu_firmware/mist/test.c
===================================================================
--- unmerged/zpu_firmware/mist/test.c	(nonexistent)
+++ unmerged/zpu_firmware/mist/test.c	(revision 1)
@@ -0,0 +1,71 @@
+
+
+unsigned char toatarichar(int val)
+{
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else
+	{
+		val = 0;
+	}
+	return val;
+}
+
+int xpos = 0;
+int ypos = 0;
+
+void nextline()
+{
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+}
+void plot(unsigned char a, int x, int y)
+{
+	printf("%d %d %d\n",a,x,y);
+}
+
+void debug(char const * str)
+{
+//        char buffer[256];
+//        buffer[0] = 'W';
+//        buffer[1] = 'T';
+//        buffer[2] = 'F';
+//        buffer[3] = 0;
+//        str = buffer;
+
+        while (1)
+        {
+                int val = *str++;
+                if (val==0) break;
+
+                plot(toatarichar(val),xpos,ypos);
+                ++xpos;
+                if (xpos==40)
+                {
+                        nextline();
+                }
+        }
+        nextline();
+        //Delay100usX(10000);
+}
+
+
+int main(void)
+{
+	printf("%d %d\n", 'H', toatarichar('H'));
+	debug("Goodbye sweet world!");
+	return 0;
+}
+
Index: unmerged/zpu_firmware/replay/rom_prologue.vhd
===================================================================
--- unmerged/zpu_firmware/replay/rom_prologue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/replay/rom_prologue.vhd	(revision 1)
@@ -0,0 +1,10 @@
+DEPTH = 4096; % Memory depth and width are required % 
+ % DEPTH is the number of addresses % 
+WIDTH = 32; % WIDTH is the number of bits of data per word % 
+% DEPTH and WIDTH should be entered as decimal numbers % 
+ADDRESS_RADIX = HEX; % Address and value radixes are required % 
+DATA_RADIX = HEX; % Enter BIN, DEC, HEX, OCT, or UNS; unless % 
+ % otherwise specified, radixes = HEX % 
+-- Specify values for addresses, which can be single address or range 
+CONTENT 
+BEGIN 
Index: unmerged/zpu_firmware/replay/pause.h
===================================================================
--- unmerged/zpu_firmware/replay/pause.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/pause.h	(revision 1)
@@ -0,0 +1,6 @@
+#ifndef PAUSE_H
+#define PAUSE_H
+
+void wait_us(int unsigned num);
+
+#endif
Index: unmerged/zpu_firmware/replay/regs.h
===================================================================
--- unmerged/zpu_firmware/replay/regs.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/regs.h	(revision 1)
@@ -0,0 +1,50 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x40000
+extern int volatile * zpu_config;
+extern int volatile * zpu_pause;
+extern int volatile * zpu_switches;
+extern int volatile * zpu_key;
+extern int volatile * zpu_ledg;
+extern int volatile * zpu_ledr;
+extern int volatile * zpu_spi_data;
+extern int volatile * zpu_spi_state;
+extern int volatile * zpu_sio;
+extern int volatile * zpu_board;
+extern int volatile * zpu_hex;
+extern int volatile * zpu_sector;
+ 
+extern unsigned char volatile * zpu_pokey_audf0;
+extern unsigned char volatile * zpu_pokey_audc0;
+extern unsigned char volatile * zpu_pokey_audf1;
+extern unsigned char volatile * zpu_pokey_audc1;
+extern unsigned char volatile * zpu_pokey_audf2;
+extern unsigned char volatile * zpu_pokey_audc2;
+extern unsigned char volatile * zpu_pokey_audf3;
+extern unsigned char volatile * zpu_pokey_audc3;
+ 
+extern unsigned char volatile * zpu_pokey_audctl;
+ 
+extern unsigned char volatile * zpu_pokey_skrest;
+extern unsigned char volatile * zpu_pokey_serout;
+extern unsigned char volatile * zpu_pokey_irqen;
+extern unsigned char volatile * zpu_pokey_skctl;
+
+extern unsigned char volatile * atari_nmien;
+extern unsigned char volatile * atari_dlistl;
+extern unsigned char volatile * atari_dlisth;
+extern unsigned char volatile * atari_colbk;
+extern unsigned char volatile * atari_colpf1;
+extern unsigned char volatile * atari_colpf2;
+extern unsigned char volatile * atari_prior;
+extern unsigned char volatile * atari_random;
+extern unsigned char volatile * atari_porta;
+extern unsigned char volatile * atari_portb;
+extern unsigned char volatile * atari_trig0;
+extern unsigned char volatile * atari_chbase;
+extern unsigned char volatile * atari_chactl;
+extern unsigned char volatile * atari_dmactl;
+extern unsigned char volatile * atari_skctl;
+
+#endif // regs_h
Index: unmerged/zpu_firmware/replay/standalone_simple.ld
===================================================================
--- unmerged/zpu_firmware/replay/standalone_simple.ld	(nonexistent)
+++ unmerged/zpu_firmware/replay/standalone_simple.ld	(revision 1)
@@ -0,0 +1,59 @@
+
+/* Memory Definitions for a ZPU program running either from external RAM (up to 8 meg).
+   or from unremapped Boot ROM / Stack RAM. */
+
+MEMORY
+{
+  CODE (rx) : ORIGIN = 0x00000000, LENGTH = 0x04000 /* 16k */
+  RAM (rx) : ORIGIN = 0x0000f000, LENGTH = 0x500 /* 32 bytes */
+}
+
+
+/* Section Definitions */
+
+SECTIONS
+{
+  /* first section is .fixed_vectors which is used for startup code */
+  . = 0x0000000;
+  .fixed_vectors :
+  {
+    *(.fixed_vectors)
+  }>CODE
+
+  /* Remaining code sections */
+  . = ALIGN(4);
+  .text :
+  {
+    *(.text)                   /* remaining code */
+  } >CODE
+
+  /* .rodata section which is used for read-only data (constants) */
+  . = ALIGN(4);
+  .rodata :
+  {
+    *(.rodata)
+  } >CODE
+  . = ALIGN(4);
+
+  /* .data section which is used for initialized data. */
+  . = ALIGN(4);
+  .data :
+  {
+    _data = . ;
+    *(.data)
+    SORT(CONSTRUCTORS)
+    . = ALIGN(4);
+  } >CODE
+  _romend = . ;
+
+  /* .bss section which is used for uninitialized data */
+  . = ALIGN(4);
+  .bss :
+  {
+    __bss_start = . ;
+    __bss_start__ = . ;
+    *(.bss)
+    *(COMMON)
+  } >RAM
+  __bss_end__ = . ;
+}
Index: unmerged/zpu_firmware/replay/regs.c
===================================================================
--- unmerged/zpu_firmware/replay/regs.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/regs.c	(revision 1)
@@ -0,0 +1,50 @@
+#ifndef regs_h
+#define regs_h
+
+#define regbase	0x40000
+int volatile * zpu_config = (int *)(0*4+regbase);
+int volatile * zpu_pause = (int *)(1*4+regbase);
+int volatile * zpu_switches = (int *)(2*4+regbase);
+int volatile * zpu_key = (int *)(3*4+regbase);
+int volatile * zpu_ledg = (int *)(4*4+regbase);
+int volatile * zpu_ledr = (int *)(5*4+regbase);
+int volatile * zpu_spi_data = (int *)(6*4+regbase);
+int volatile * zpu_spi_state = (int *)(7*4+regbase);
+int volatile * zpu_sio = (int *)(8*4+regbase);
+int volatile * zpu_board = (int *)(9*4+regbase);
+int volatile * zpu_hex = (int *)(10*4+regbase);
+int volatile * zpu_sector = (int *)(11*4+regbase);
+
+unsigned char volatile * zpu_pokey_audf0 = (unsigned char *)(0x10*4+regbase);
+unsigned char volatile * zpu_pokey_audc0 = (unsigned char *)(0x11*4+regbase);
+unsigned char volatile * zpu_pokey_audf1 = (unsigned char *)(0x12*4+regbase);
+unsigned char volatile * zpu_pokey_audc1 = (unsigned char *)(0x13*4+regbase);
+unsigned char volatile * zpu_pokey_audf2 = (unsigned char *)(0x14*4+regbase);
+unsigned char volatile * zpu_pokey_audc2 = (unsigned char *)(0x15*4+regbase);
+unsigned char volatile * zpu_pokey_audf3 = (unsigned char *)(0x16*4+regbase);
+unsigned char volatile * zpu_pokey_audc3 = (unsigned char *)(0x17*4+regbase);
+
+unsigned char volatile * zpu_pokey_audctl = (unsigned char *)(0x18*4+regbase);
+
+unsigned char volatile * zpu_pokey_skrest = (unsigned char *)(0x1a*4+regbase);
+unsigned char volatile * zpu_pokey_serout = (unsigned char *)(0x1d*4+regbase);
+unsigned char volatile * zpu_pokey_irqen = (unsigned char *)(0x1e*4+regbase);
+unsigned char volatile * zpu_pokey_skctl = (unsigned char *)(0x1f*4+regbase);
+
+unsigned char volatile * atari_nmien = (unsigned char *)(0xd40e + 0x10000);
+unsigned char volatile * atari_dlistl = (unsigned char *)(0xd402 + 0x10000);
+unsigned char volatile * atari_dlisth = (unsigned char *)(0xd403 + 0x10000);
+unsigned char volatile * atari_colbk = (unsigned char *)(0xd01a + 0x10000);
+unsigned char volatile * atari_colpf1 = (unsigned char *)(0xd017 + 0x10000);
+unsigned char volatile * atari_colpf2 = (unsigned char *)(0xd018 + 0x10000);
+unsigned char volatile * atari_prior = (unsigned char *)(0xd01b + 0x10000);
+unsigned char volatile * atari_random = (unsigned char *)(0xd20a + 0x10000);
+unsigned char volatile * atari_porta = (unsigned char *)(0xd300 + 0x10000);
+unsigned char volatile * atari_portb = (unsigned char *)(0xd301 + 0x10000);
+unsigned char volatile * atari_trig0 = (unsigned char *)(0xd010 + 0x10000);
+unsigned char volatile * atari_chbase = (unsigned char *)(0xd409 + 0x10000);
+unsigned char volatile * atari_chactl = (unsigned char *)(0xd401 + 0x10000);
+unsigned char volatile * atari_dmactl = (unsigned char *)(0xd400 + 0x10000);
+unsigned char volatile * atari_skctl = (unsigned char *)(0xd20f + 0x10000);
+
+#endif // regs_h
Index: unmerged/zpu_firmware/replay/setup
===================================================================
--- unmerged/zpu_firmware/replay/setup	(nonexistent)
+++ unmerged/zpu_firmware/replay/setup	(revision 1)
@@ -0,0 +1 @@
+export PATH=${PATH}:/home/markw/altera/atari_xe_fpga/zpu/zpugcc/toolchain/install/bin
Index: unmerged/zpu_firmware/mist/x
===================================================================
--- unmerged/zpu_firmware/mist/x	(nonexistent)
+++ unmerged/zpu_firmware/mist/x	(revision 1)
@@ -0,0 +1,20289 @@
+
+HelloTinyROM.elf:     file format elf32-zpu
+
+Disassembly of section .fixed_vectors:
+
+00000000 <_start>:
+   0:	0b          	nop
+   1:	0b          	nop
+   2:	0b          	nop
+   3:	89          	im 9
+   4:	ad          	im 45
+   5:	04          	poppc
+   6:	0b          	nop
+   7:	0b          	nop
+   8:	0b          	nop
+   9:	0b          	nop
+   a:	0b          	nop
+   b:	0b          	nop
+   c:	0b          	nop
+   d:	0b          	nop
+   e:	0b          	nop
+   f:	0b          	nop
+  10:	0b          	nop
+  11:	0b          	nop
+  12:	0b          	nop
+  13:	0b          	nop
+  14:	0b          	nop
+  15:	0b          	nop
+  16:	0b          	nop
+  17:	0b          	nop
+  18:	0b          	nop
+  19:	0b          	nop
+  1a:	0b          	nop
+  1b:	0b          	nop
+  1c:	0b          	nop
+  1d:	0b          	nop
+  1e:	0b          	nop
+  1f:	0b          	nop
+  20:	0b          	nop
+  21:	0b          	nop
+  22:	0b          	nop
+  23:	0b          	nop
+	...
+
+00000040 <_loadh>:
+  40:	71          	loadsp 4
+  41:	fd          	im -3
+  42:	06          	and
+  43:	08          	load
+  44:	72          	loadsp 8
+  45:	83          	im 3
+  46:	06          	and
+  47:	09          	not
+  48:	81          	im 1
+  49:	05          	add
+  4a:	82          	im 2
+  4b:	05          	add
+  4c:	83          	im 3
+  4d:	2b          	ashiftleft
+  4e:	2a          	lshiftright
+  4f:	83          	im 3
+  50:	ff          	im -1
+  51:	ff          	im -1
+  52:	06          	and
+  53:	52          	storesp 8
+  54:	04          	poppc
+	...
+
+00000060 <_storeh>:
+  60:	71          	loadsp 4
+  61:	fd          	im -3
+  62:	06          	and
+  63:	08          	load
+  64:	83          	im 3
+  65:	ff          	im -1
+  66:	ff          	im -1
+  67:	73          	loadsp 12
+  68:	83          	im 3
+  69:	06          	and
+  6a:	09          	not
+  6b:	81          	im 1
+  6c:	05          	add
+  6d:	82          	im 2
+  6e:	05          	add
+  6f:	83          	im 3
+  70:	2b          	ashiftleft
+  71:	2b          	ashiftleft
+  72:	09          	not
+  73:	06          	and
+  74:	73          	loadsp 12
+  75:	83          	im 3
+  76:	ff          	im -1
+  77:	ff          	im -1
+  78:	0b          	nop
+  79:	0b          	nop
+  7a:	0b          	nop
+  7b:	0b          	nop
+  7c:	83          	im 3
+  7d:	a7          	im 39
+  7e:	04          	poppc
+	...
+
+00000080 <_lessthan>:
+  80:	72          	loadsp 8
+  81:	09          	not
+  82:	81          	im 1
+  83:	05          	add
+  84:	72          	loadsp 8
+  85:	05          	add
+  86:	73          	loadsp 12
+  87:	73          	loadsp 12
+  88:	09          	not
+  89:	06          	and
+  8a:	09          	not
+  8b:	06          	and
+  8c:	73          	loadsp 12
+  8d:	09          	not
+  8e:	73          	loadsp 12
+  8f:	06          	and
+  90:	07          	or
+  91:	0a          	flip
+  92:	81          	im 1
+  93:	06          	and
+  94:	53          	storesp 12
+  95:	51          	storesp 4
+  96:	04          	poppc
+	...
+
+000000a0 <_lessthanorequal>:
+  a0:	72          	loadsp 8
+  a1:	72          	loadsp 8
+  a2:	24          	lessthan
+  a3:	73          	loadsp 12
+  a4:	73          	loadsp 12
+  a5:	2e          	eq
+  a6:	07          	or
+  a7:	53          	storesp 12
+  a8:	51          	storesp 4
+  a9:	04          	poppc
+	...
+
+000000c0 <_ulessthan>:
+  c0:	71          	loadsp 4
+  c1:	73          	loadsp 12
+  c2:	71          	loadsp 4
+  c3:	09          	not
+  c4:	71          	loadsp 4
+  c5:	06          	and
+  c6:	81          	im 1
+  c7:	06          	and
+  c8:	30          	neg
+  c9:	72          	loadsp 8
+  ca:	0a          	flip
+  cb:	10          	addsp 0
+  cc:	0a          	flip
+  cd:	72          	loadsp 8
+  ce:	0a          	flip
+  cf:	10          	addsp 0
+  d0:	0a          	flip
+  d1:	31          	sub
+  d2:	05          	add
+  d3:	0a          	flip
+  d4:	81          	im 1
+  d5:	06          	and
+  d6:	51          	storesp 4
+  d7:	51          	storesp 4
+  d8:	53          	storesp 12
+  d9:	51          	storesp 4
+  da:	04          	poppc
+  db:	00          	breakpoint
+  dc:	00          	breakpoint
+  dd:	00          	breakpoint
+	...
+
+000000e0 <_ulessthanorequal>:
+  e0:	72          	loadsp 8
+  e1:	72          	loadsp 8
+  e2:	26          	ulessthan
+  e3:	73          	loadsp 12
+  e4:	73          	loadsp 12
+  e5:	2e          	eq
+  e6:	07          	or
+  e7:	53          	storesp 12
+  e8:	51          	storesp 4
+  e9:	04          	poppc
+	...
+
+00000100 <_swap>:
+	...
+
+00000120 <_slowmult>:
+ 120:	0b          	nop
+ 121:	0b          	nop
+ 122:	0b          	nop
+ 123:	88          	im 8
+ 124:	bc          	im 60
+ 125:	04          	poppc
+	...
+
+00000140 <_lshiftright>:
+ 140:	72          	loadsp 8
+ 141:	0a          	flip
+ 142:	72          	loadsp 8
+ 143:	2b          	ashiftleft
+ 144:	0a          	flip
+ 145:	53          	storesp 12
+ 146:	51          	storesp 4
+ 147:	04          	poppc
+	...
+
+00000160 <_ashiftleft>:
+ 160:	72          	loadsp 8
+ 161:	72          	loadsp 8
+ 162:	9f          	im 31
+ 163:	06          	and
+ 164:	09          	not
+ 165:	81          	im 1
+ 166:	05          	add
+ 167:	0b          	nop
+ 168:	0b          	nop
+ 169:	0b          	nop
+ 16a:	88          	im 8
+ 16b:	9f          	im 31
+ 16c:	05          	add
+ 16d:	04          	poppc
+	...
+
+00000180 <_ashiftright>:
+ 180:	72          	loadsp 8
+ 181:	72          	loadsp 8
+ 182:	2a          	lshiftright
+ 183:	ff          	im -1
+ 184:	73          	loadsp 12
+ 185:	9f          	im 31
+ 186:	06          	and
+ 187:	2a          	lshiftright
+ 188:	09          	not
+ 189:	74          	loadsp 16
+ 18a:	09          	not
+ 18b:	0a          	flip
+ 18c:	81          	im 1
+ 18d:	06          	and
+ 18e:	ff          	im -1
+ 18f:	05          	add
+ 190:	06          	and
+ 191:	07          	or
+ 192:	53          	storesp 12
+ 193:	51          	storesp 4
+ 194:	04          	poppc
+	...
+
+000001a0 <_call>:
+ 1a0:	71          	loadsp 4
+ 1a1:	71          	loadsp 4
+ 1a2:	53          	storesp 12
+ 1a3:	51          	storesp 4
+ 1a4:	02          	pushsp
+ 1a5:	0d          	popsp
+ 1a6:	04          	poppc
+
+000001a7 <_storehtail>:
+ 1a7:	06          	and
+ 1a8:	73          	loadsp 12
+ 1a9:	83          	im 3
+ 1aa:	06          	and
+ 1ab:	09          	not
+ 1ac:	81          	im 1
+ 1ad:	05          	add
+ 1ae:	82          	im 2
+ 1af:	05          	add
+ 1b0:	83          	im 3
+ 1b1:	2b          	ashiftleft
+ 1b2:	0b          	nop
+ 1b3:	2b          	ashiftleft
+ 1b4:	07          	or
+ 1b5:	72          	loadsp 8
+ 1b6:	fc          	im -4
+ 1b7:	06          	and
+ 1b8:	0c          	store
+ 1b9:	51          	storesp 4
+ 1ba:	51          	storesp 4
+ 1bb:	04          	poppc
+ 1bc:	00          	breakpoint
+ 1bd:	00          	breakpoint
+	...
+
+000001c0 <_eq>:
+ 1c0:	72          	loadsp 8
+ 1c1:	09          	not
+ 1c2:	81          	im 1
+ 1c3:	05          	add
+ 1c4:	72          	loadsp 8
+ 1c5:	05          	add
+ 1c6:	09          	not
+ 1c7:	70          	loadsp 0
+ 1c8:	81          	im 1
+ 1c9:	05          	add
+ 1ca:	09          	not
+ 1cb:	06          	and
+ 1cc:	0a          	flip
+ 1cd:	81          	im 1
+ 1ce:	06          	and
+ 1cf:	53          	storesp 12
+ 1d0:	51          	storesp 4
+ 1d1:	04          	poppc
+	...
+
+000001e0 <_neq>:
+ 1e0:	72          	loadsp 8
+ 1e1:	09          	not
+ 1e2:	81          	im 1
+ 1e3:	05          	add
+ 1e4:	72          	loadsp 8
+ 1e5:	05          	add
+ 1e6:	09          	not
+ 1e7:	70          	loadsp 0
+ 1e8:	81          	im 1
+ 1e9:	05          	add
+ 1ea:	09          	not
+ 1eb:	06          	and
+ 1ec:	0a          	flip
+ 1ed:	09          	not
+ 1ee:	81          	im 1
+ 1ef:	06          	and
+ 1f0:	53          	storesp 12
+ 1f1:	51          	storesp 4
+ 1f2:	04          	poppc
+	...
+
+00000200 <_neg>:
+ 200:	71          	loadsp 4
+ 201:	09          	not
+ 202:	81          	im 1
+ 203:	05          	add
+ 204:	52          	storesp 8
+ 205:	04          	poppc
+	...
+
+00000220 <_sub>:
+ 220:	72          	loadsp 8
+ 221:	72          	loadsp 8
+ 222:	09          	not
+ 223:	81          	im 1
+ 224:	05          	add
+ 225:	05          	add
+ 226:	53          	storesp 12
+ 227:	51          	storesp 4
+ 228:	04          	poppc
+	...
+
+00000240 <_xor>:
+ 240:	72          	loadsp 8
+ 241:	09          	not
+ 242:	72          	loadsp 8
+ 243:	06          	and
+ 244:	73          	loadsp 12
+ 245:	73          	loadsp 12
+ 246:	09          	not
+ 247:	06          	and
+ 248:	07          	or
+ 249:	53          	storesp 12
+ 24a:	51          	storesp 4
+ 24b:	04          	poppc
+	...
+
+00000260 <_loadb>:
+ 260:	71          	loadsp 4
+ 261:	fc          	im -4
+ 262:	06          	and
+ 263:	08          	load
+ 264:	72          	loadsp 8
+ 265:	83          	im 3
+ 266:	06          	and
+ 267:	09          	not
+ 268:	81          	im 1
+ 269:	05          	add
+ 26a:	83          	im 3
+ 26b:	05          	add
+ 26c:	10          	addsp 0
+ 26d:	10          	addsp 0
+ 26e:	10          	addsp 0
+ 26f:	2a          	lshiftright
+ 270:	81          	im 1
+ 271:	ff          	im -1
+ 272:	06          	and
+ 273:	52          	storesp 8
+ 274:	04          	poppc
+	...
+
+00000280 <_storeb>:
+ 280:	71          	loadsp 4
+ 281:	fc          	im -4
+ 282:	06          	and
+ 283:	08          	load
+ 284:	0b          	nop
+ 285:	0b          	nop
+ 286:	80          	im 0
+ 287:	f4          	im -12
+ 288:	a4          	im 36
+ 289:	73          	loadsp 12
+ 28a:	83          	im 3
+ 28b:	06          	and
+ 28c:	10          	addsp 0
+ 28d:	10          	addsp 0
+ 28e:	05          	add
+ 28f:	08          	load
+ 290:	06          	and
+ 291:	0b          	nop
+ 292:	0b          	nop
+ 293:	0b          	nop
+ 294:	88          	im 8
+ 295:	a2          	im 34
+ 296:	04          	poppc
+	...
+
+000002a0 <_div>:
+ 2a0:	0b          	nop
+ 2a1:	0b          	nop
+ 2a2:	0b          	nop
+ 2a3:	88          	im 8
+ 2a4:	ff          	im -1
+ 2a5:	04          	poppc
+	...
+
+000002c0 <_mod>:
+ 2c0:	0b          	nop
+ 2c1:	0b          	nop
+ 2c2:	0b          	nop
+ 2c3:	88          	im 8
+ 2c4:	d8          	im -40
+ 2c5:	04          	poppc
+	...
+
+000002e0 <_eqbranch>:
+ 2e0:	72          	loadsp 8
+ 2e1:	09          	not
+ 2e2:	70          	loadsp 0
+ 2e3:	81          	im 1
+ 2e4:	05          	add
+ 2e5:	09          	not
+ 2e6:	06          	and
+ 2e7:	0a          	flip
+ 2e8:	81          	im 1
+ 2e9:	06          	and
+ 2ea:	ff          	im -1
+ 2eb:	05          	add
+ 2ec:	70          	loadsp 0
+ 2ed:	54          	storesp 16
+ 2ee:	71          	loadsp 4
+ 2ef:	06          	and
+ 2f0:	73          	loadsp 12
+ 2f1:	09          	not
+ 2f2:	72          	loadsp 8
+ 2f3:	74          	loadsp 16
+ 2f4:	05          	add
+ 2f5:	ff          	im -1
+ 2f6:	05          	add
+ 2f7:	06          	and
+ 2f8:	07          	or
+ 2f9:	51          	storesp 4
+ 2fa:	51          	storesp 4
+ 2fb:	51          	storesp 4
+ 2fc:	04          	poppc
+ 2fd:	00          	breakpoint
+	...
+
+00000300 <_neqbranch>:
+ 300:	72          	loadsp 8
+ 301:	09          	not
+ 302:	70          	loadsp 0
+ 303:	81          	im 1
+ 304:	05          	add
+ 305:	09          	not
+ 306:	06          	and
+ 307:	0a          	flip
+ 308:	09          	not
+ 309:	81          	im 1
+ 30a:	06          	and
+ 30b:	ff          	im -1
+ 30c:	05          	add
+ 30d:	70          	loadsp 0
+ 30e:	54          	storesp 16
+ 30f:	71          	loadsp 4
+ 310:	06          	and
+ 311:	73          	loadsp 12
+ 312:	09          	not
+ 313:	72          	loadsp 8
+ 314:	74          	loadsp 16
+ 315:	05          	add
+ 316:	ff          	im -1
+ 317:	05          	add
+ 318:	06          	and
+ 319:	07          	or
+ 31a:	51          	storesp 4
+ 31b:	51          	storesp 4
+ 31c:	51          	storesp 4
+ 31d:	04          	poppc
+	...
+
+00000320 <_poppcrel>:
+ 320:	05          	add
+ 321:	ff          	im -1
+ 322:	05          	add
+ 323:	04          	poppc
+	...
+
+00000340 <_config>:
+ 340:	81          	im 1
+ 341:	0b          	nop
+ 342:	80          	im 0
+ 343:	f9          	im -7
+ 344:	f0          	im -16
+ 345:	0c          	store
+ 346:	51          	storesp 4
+ 347:	04          	poppc
+	...
+
+0000035e <_pushpc>:
+ 35e:	71          	loadsp 4
+ 35f:	81          	im 1
+ 360:	05          	add
+ 361:	52          	storesp 8
+ 362:	04          	poppc
+	...
+
+0000037e <_syscall_emulate>:
+	...
+
+0000039e <_pushspadd>:
+ 39e:	02          	pushsp
+ 39f:	84          	im 4
+ 3a0:	05          	add
+ 3a1:	72          	loadsp 8
+ 3a2:	10          	addsp 0
+ 3a3:	10          	addsp 0
+ 3a4:	05          	add
+ 3a5:	52          	storesp 8
+ 3a6:	04          	poppc
+	...
+
+000003be <_halfmult>:
+	...
+
+000003de <_callpcrel>:
+ 3de:	71          	loadsp 4
+ 3df:	71          	loadsp 4
+ 3e0:	05          	add
+ 3e1:	ff          	im -1
+ 3e2:	05          	add
+ 3e3:	71          	loadsp 4
+ 3e4:	53          	storesp 12
+ 3e5:	51          	storesp 4
+ 3e6:	02          	pushsp
+ 3e7:	0d          	popsp
+ 3e8:	04          	poppc
+	...
+Disassembly of section .text:
+
+00000400 <_ashiftleftBegin>:
+     400:	10          	addsp 0
+     401:	10          	addsp 0
+     402:	10          	addsp 0
+     403:	10          	addsp 0
+     404:	10          	addsp 0
+     405:	10          	addsp 0
+     406:	10          	addsp 0
+     407:	10          	addsp 0
+     408:	10          	addsp 0
+     409:	10          	addsp 0
+     40a:	10          	addsp 0
+     40b:	10          	addsp 0
+     40c:	10          	addsp 0
+     40d:	10          	addsp 0
+     40e:	10          	addsp 0
+     40f:	10          	addsp 0
+     410:	10          	addsp 0
+     411:	10          	addsp 0
+     412:	10          	addsp 0
+     413:	10          	addsp 0
+     414:	10          	addsp 0
+     415:	10          	addsp 0
+     416:	10          	addsp 0
+     417:	10          	addsp 0
+     418:	10          	addsp 0
+     419:	10          	addsp 0
+     41a:	10          	addsp 0
+     41b:	10          	addsp 0
+     41c:	10          	addsp 0
+     41d:	10          	addsp 0
+     41e:	10          	addsp 0
+
+0000041f <_ashiftleftEnd>:
+     41f:	53          	storesp 12
+     420:	51          	storesp 4
+     421:	04          	poppc
+
+00000422 <_storebtail>:
+     422:	73          	loadsp 12
+     423:	81          	im 1
+     424:	ff          	im -1
+     425:	06          	and
+     426:	73          	loadsp 12
+     427:	83          	im 3
+     428:	06          	and
+     429:	09          	not
+     42a:	81          	im 1
+     42b:	05          	add
+     42c:	83          	im 3
+     42d:	05          	add
+     42e:	10          	addsp 0
+     42f:	10          	addsp 0
+     430:	10          	addsp 0
+     431:	2b          	ashiftleft
+     432:	07          	or
+     433:	72          	loadsp 8
+     434:	fc          	im -4
+     435:	06          	and
+     436:	0c          	store
+     437:	51          	storesp 4
+     438:	51          	storesp 4
+     439:	04          	poppc
+
+0000043a <_syscall>:
+     43a:	3c          	syscall
+     43b:	04          	poppc
+
+0000043c <_slowmultImpl>:
+     43c:	72          	loadsp 8
+     43d:	72          	loadsp 8
+     43e:	80          	im 0
+     43f:	72          	loadsp 8
+     440:	81          	im 1
+     441:	06          	and
+     442:	ff          	im -1
+     443:	05          	add
+     444:	09          	not
+     445:	72          	loadsp 8
+     446:	06          	and
+     447:	05          	add
+     448:	71          	loadsp 4
+     449:	10          	addsp 0
+     44a:	52          	storesp 8
+     44b:	72          	loadsp 8
+     44c:	0a          	flip
+     44d:	10          	addsp 0
+     44e:	0a          	flip
+     44f:	53          	storesp 12
+     450:	72          	loadsp 8
+     451:	ed          	im -19
+     452:	38          	neqbranch
+     453:	51          	storesp 4
+     454:	51          	storesp 4
+     455:	53          	storesp 12
+     456:	51          	storesp 4
+     457:	04          	poppc
+
+00000458 <___mod>:
+     458:	83          	im 3
+     459:	e0          	im -32
+     45a:	80          	im 0
+     45b:	08          	load
+     45c:	83          	im 3
+     45d:	e0          	im -32
+     45e:	84          	im 4
+     45f:	08          	load
+     460:	83          	im 3
+     461:	e0          	im -32
+     462:	88          	im 8
+     463:	08          	load
+     464:	75          	loadsp 20
+     465:	75          	loadsp 20
+     466:	80          	im 0
+     467:	ee          	im -18
+     468:	d4          	im -44
+     469:	2d          	call
+     46a:	50          	storesp 0
+     46b:	50          	storesp 0
+     46c:	83          	im 3
+     46d:	e0          	im -32
+     46e:	80          	im 0
+     46f:	08          	load
+     470:	56          	storesp 24
+     471:	83          	im 3
+     472:	e0          	im -32
+     473:	88          	im 8
+     474:	0c          	store
+     475:	83          	im 3
+     476:	e0          	im -32
+     477:	84          	im 4
+     478:	0c          	store
+     479:	83          	im 3
+     47a:	e0          	im -32
+     47b:	80          	im 0
+     47c:	0c          	store
+     47d:	51          	storesp 4
+     47e:	04          	poppc
+
+0000047f <___div>:
+     47f:	83          	im 3
+     480:	e0          	im -32
+     481:	80          	im 0
+     482:	08          	load
+     483:	83          	im 3
+     484:	e0          	im -32
+     485:	84          	im 4
+     486:	08          	load
+     487:	83          	im 3
+     488:	e0          	im -32
+     489:	88          	im 8
+     48a:	08          	load
+     48b:	75          	loadsp 20
+     48c:	75          	loadsp 20
+     48d:	80          	im 0
+     48e:	ec          	im -20
+     48f:	e8          	im -24
+     490:	2d          	call
+     491:	50          	storesp 0
+     492:	50          	storesp 0
+     493:	83          	im 3
+     494:	e0          	im -32
+     495:	80          	im 0
+     496:	08          	load
+     497:	56          	storesp 24
+     498:	83          	im 3
+     499:	e0          	im -32
+     49a:	88          	im 8
+     49b:	0c          	store
+     49c:	83          	im 3
+     49d:	e0          	im -32
+     49e:	84          	im 4
+     49f:	0c          	store
+     4a0:	83          	im 3
+     4a1:	e0          	im -32
+     4a2:	80          	im 0
+     4a3:	0c          	store
+     4a4:	51          	storesp 4
+     4a5:	04          	poppc
+	...
+
+000004a8 <_boot>:
+     4a8:	80          	im 0
+     4a9:	04          	poppc
+
+000004aa <_break>:
+     4aa:	89          	im 9
+     4ab:	aa          	im 42
+     4ac:	04          	poppc
+
+000004ad <_premain>:
+     4ad:	89          	im 9
+     4ae:	aa          	im 42
+     4af:	0b          	nop
+     4b0:	bf          	im 63
+     4b1:	fb          	im -5
+     4b2:	04          	poppc
+
+000004b3 <wait_us>:
+#define XEX_SECTOR_SIZE 128
+
+void
+wait_us(int unsigned num)
+{
+     4b3:	fd          	im -3
+     4b4:	3d          	pushspadd
+     4b5:	0d          	popsp
+
+000004b6 <.LM2>:
+	// 57.5MHz
+	int unsigned cycles = num*57 + num/2;
+     4b6:	75          	loadsp 20
+     4b7:	b9          	im 57
+     4b8:	29          	mult
+     4b9:	76          	loadsp 24
+     4ba:	81          	im 1
+     4bb:	2a          	lshiftright
+     4bc:	05          	add
+
+000004bd <.LM3>:
+	*zpu_pause = cycles;
+     4bd:	80          	im 0
+     4be:	fc          	im -4
+     4bf:	c0          	im -64
+     4c0:	08          	load
+     4c1:	54          	storesp 16
+     4c2:	73          	loadsp 12
+     4c3:	0c          	store
+     4c4:	85          	im 5
+     4c5:	3d          	pushspadd
+     4c6:	0d          	popsp
+     4c7:	04          	poppc
+
+000004c8 <clearAtariSectorBuffer>:
+}
+
+void openfile(const char * filename);
+void sdcard();
+void mmcReadCached(u32 sector);
+u32 n_actual_mmc_sector;
+extern unsigned char mmc_sector_buffer[512];
+unsigned char atari_sector_buffer[256];
+unsigned char get_checksum(unsigned char* buffer, u16 len);
+
+#define    TWOBYTESTOWORD(ptr,val)           (*((u08*)(ptr)) = val&0xff);(*(1+(u08*)(ptr)) = (val>>8)&0xff);
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len);
+void clearAtariSectorBuffer()
+{
+     4c8:	80          	im 0
+     4c9:	3d          	pushspadd
+     4ca:	0d          	popsp
+
+000004cb <.LM5>:
+	int i=256;
+	while (--i)
+		atari_sector_buffer[i] = 0;
+     4cb:	81          	im 1
+     4cc:	ff          	im -1
+     4cd:	51          	storesp 4
+
+000004ce <.L5>:
+     4ce:	80          	im 0
+     4cf:	0b          	nop
+     4d0:	83          	im 3
+     4d1:	e0          	im -32
+     4d2:	c8          	im -56
+     4d3:	12          	addsp 8
+     4d4:	34          	storeb
+     4d5:	ff          	im -1
+     4d6:	11          	addsp 4
+     4d7:	51          	storesp 4
+     4d8:	70          	loadsp 0
+     4d9:	f4          	im -12
+     4da:	38          	neqbranch
+     4db:	82          	im 2
+     4dc:	3d          	pushspadd
+     4dd:	0d          	popsp
+     4de:	04          	poppc
+
+000004df <filesize>:
+}
+
+int
+filesize(char const * filename)
+{
+     4df:	fa          	im -6
+     4e0:	3d          	pushspadd
+     4e1:	0d          	popsp
+     4e2:	78          	loadsp 32
+
+000004e3 <.LM7>:
+	char const * tmp;
+	char const * tmp2;
+	if (FR_OK != pf_opendir(&dir,"/"))
+     4e3:	0b          	nop
+     4e4:	0b          	nop
+     4e5:	80          	im 0
+     4e6:	f4          	im -12
+     4e7:	fc          	im -4
+     4e8:	53          	storesp 12
+     4e9:	83          	im 3
+     4ea:	e2          	im -30
+     4eb:	f4          	im -12
+     4ec:	52          	storesp 8
+     4ed:	56          	storesp 24
+     4ee:	80          	im 0
+     4ef:	cc          	im -52
+     4f0:	a8          	im 40
+     4f1:	3f          	callpcrel
+
+000004f2 <.LM8>:
+	{
+		return 0;
+     4f2:	80          	im 0
+     4f3:	53          	storesp 12
+
+000004f4 <.LM9>:
+     4f4:	83          	im 3
+     4f5:	e0          	im -32
+     4f6:	80          	im 0
+     4f7:	08          	load
+     4f8:	73          	loadsp 12
+     4f9:	2e          	eq
+     4fa:	8a          	im 10
+     4fb:	38          	neqbranch
+
+000004fc <.LM10>:
+	}
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		if (filinfo.fattrib & AM_SYS)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_HID)
+		{
+			continue;
+		}
+		if (filinfo.fattrib & AM_DIR)
+		{
+			continue;
+		}
+	
+		tmp = filename;
+		tmp2 = filinfo.fname;
+		while (1)
+		{
+			if (*tmp == *tmp2)
+			{
+				if (*tmp == '\0')
+				{
+					return filinfo.fsize;
+				}
+				++tmp;
+				++tmp2;
+			}
+			else
+				break;
+		}
+	}
+	return 0;
+}
+     4fc:	72          	loadsp 8
+     4fd:	83          	im 3
+     4fe:	e0          	im -32
+     4ff:	80          	im 0
+     500:	0c          	store
+     501:	88          	im 8
+     502:	3d          	pushspadd
+     503:	0d          	popsp
+     504:	04          	poppc
+
+00000505 <.L26>:
+     505:	83          	im 3
+     506:	e0          	im -32
+     507:	94          	im 20
+     508:	52          	storesp 8
+     509:	83          	im 3
+     50a:	e2          	im -30
+     50b:	f4          	im -12
+     50c:	51          	storesp 4
+     50d:	80          	im 0
+     50e:	cd          	im -51
+     50f:	9c          	im 28
+     510:	3f          	callpcrel
+     511:	83          	im 3
+     512:	e0          	im -32
+     513:	80          	im 0
+     514:	08          	load
+     515:	80          	im 0
+     516:	d5          	im -43
+     517:	38          	neqbranch
+     518:	83          	im 3
+     519:	e0          	im -32
+     51a:	9d          	im 29
+     51b:	33          	loadb
+     51c:	53          	storesp 12
+     51d:	72          	loadsp 8
+     51e:	80          	im 0
+     51f:	2e          	eq
+     520:	80          	im 0
+     521:	ca          	im -54
+     522:	38          	neqbranch
+
+00000523 <.LM12>:
+     523:	83          	im 3
+     524:	e0          	im -32
+     525:	9c          	im 28
+     526:	33          	loadb
+     527:	70          	loadsp 0
+     528:	82          	im 2
+     529:	2a          	lshiftright
+     52a:	70          	loadsp 0
+     52b:	81          	im 1
+     52c:	06          	and
+     52d:	51          	storesp 4
+     52e:	54          	storesp 16
+     52f:	54          	storesp 16
+     530:	72          	loadsp 8
+     531:	d3          	im -45
+     532:	38          	neqbranch
+
+00000533 <.LM13>:
+     533:	73          	loadsp 12
+     534:	81          	im 1
+     535:	2a          	lshiftright
+     536:	70          	loadsp 0
+     537:	81          	im 1
+     538:	06          	and
+     539:	51          	storesp 4
+     53a:	53          	storesp 12
+     53b:	72          	loadsp 8
+     53c:	c8          	im -56
+     53d:	38          	neqbranch
+
+0000053e <.LM14>:
+     53e:	73          	loadsp 12
+     53f:	84          	im 4
+     540:	2a          	lshiftright
+     541:	70          	loadsp 0
+     542:	81          	im 1
+     543:	06          	and
+     544:	51          	storesp 4
+     545:	53          	storesp 12
+     546:	72          	loadsp 8
+     547:	ff          	im -1
+     548:	bc          	im 60
+     549:	38          	neqbranch
+
+0000054a <.LM15>:
+     54a:	75          	loadsp 20
+
+0000054b <.LM16>:
+     54b:	83          	im 3
+     54c:	e0          	im -32
+     54d:	9d          	im 29
+     54e:	56          	storesp 24
+     54f:	54          	storesp 16
+
+00000550 <.L16>:
+     550:	73          	loadsp 12
+     551:	33          	loadb
+     552:	75          	loadsp 20
+     553:	33          	loadb
+     554:	58          	storesp 32
+     555:	53          	storesp 12
+     556:	72          	loadsp 8
+     557:	77          	loadsp 28
+     558:	2e          	eq
+     559:	09          	not
+     55a:	81          	im 1
+     55b:	06          	and
+     55c:	ff          	im -1
+     55d:	a7          	im 39
+     55e:	38          	neqbranch
+
+0000055f <.LM18>:
+     55f:	72          	loadsp 8
+     560:	80          	im 0
+     561:	2e          	eq
+     562:	93          	im 19
+     563:	38          	neqbranch
+
+00000564 <.LM19>:
+     564:	81          	im 1
+     565:	14          	addsp 16
+
+00000566 <.LM20>:
+     566:	81          	im 1
+     567:	16          	addsp 24
+     568:	56          	storesp 24
+     569:	54          	storesp 16
+     56a:	e5          	im -27
+     56b:	39          	poppcrel
+
+0000056c <.L12>:
+     56c:	80          	im 0
+
+0000056d <.LM22>:
+     56d:	0b          	nop
+     56e:	83          	im 3
+     56f:	e0          	im -32
+     570:	80          	im 0
+     571:	0c          	store
+     572:	88          	im 8
+     573:	3d          	pushspadd
+     574:	0d          	popsp
+     575:	04          	poppc
+
+00000576 <.L22>:
+     576:	83          	im 3
+     577:	e0          	im -32
+     578:	94          	im 20
+     579:	08          	load
+
+0000057a <.LM24>:
+     57a:	83          	im 3
+     57b:	e0          	im -32
+     57c:	80          	im 0
+     57d:	0c          	store
+     57e:	88          	im 8
+     57f:	3d          	pushspadd
+     580:	0d          	popsp
+     581:	04          	poppc
+
+00000582 <clear_ram>:
+
+int
+selectfile(char * filename)
+{
+	int fileno;
+	int skip;
+	int plotted = 0;
+	wait_us(200000);
+	for(;;)
+	{
+		int i = 0;
+		int go = 0;
+		fileno = 0;
+		topofscreen();
+		for (i=0; i!=(24*40); ++i)
+		{
+			*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+		}
+		if (FR_OK != pf_opendir(&dir,"/"))
+		{
+			debug("opendir failed\n");
+			while(1);
+		}
+
+		plotted = 0;
+		skip = 0;
+		if (selfileno>20)
+		{
+			skip = selfileno-20;
+			skip&=0xfffffffe;
+		}
+		if (selfileno<0)
+		{
+			selfileno = 0;
+		}
+		while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+		{
+			if (filinfo.fattrib & AM_SYS)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_HID)
+			{
+				continue;
+			}
+			if (filinfo.fattrib & AM_DIR)
+			{
+				debug("DIR ");
+			}
+			if (selfileno == fileno)
+			{
+				for (i=0;i!=15;++i)
+				{
+					filename[i] = filinfo.fname[i];
+					if (0==filinfo.fname[i]) break;
+					filinfo.fname[i]+=128;
+				}
+			}
+			if (--skip<0)
+			{
+				debug(filinfo.fname);
+				++plotted;
+				if (plotted&1)
+				{
+					setxpos(20);
+				}
+				else
+				{
+					debug("\n");
+				}
+				if (plotted==40)
+				{
+					break;
+				}
+			}
+			fileno++;
+		}
+		debug("\n");
+		setypos(21);
+		opendrive = 0;
+		openfile(filename);
+		for (;;)
+		{
+			unsigned char porta = *atari_porta;
+			if (0==(porta&0x2)) // down
+			{
+				selfileno+=2;
+				break;
+			}
+			else if (0==(porta&0x1)) // up
+			{
+				selfileno-=2;
+				break;
+			}
+			else if (0==(porta&0x8)) // right
+			{
+				selfileno|=1;
+				break;
+			}
+			else if (0==(porta&0x4)) // left
+			{
+				selfileno&=0xfffffffe;
+				break;
+			}
+			else if (0==(*atari_trig0)) // fire
+			{
+				go = 1;
+				while(0==(*atari_trig0));
+				break;
+			}
+			topofscreen();
+			//plotnextnumber(porta);
+			*atari_colbk = *atari_random;
+			//wait_us(200);
+		}
+		if (go == 1)
+		{
+			wait_us(200000);
+			return validfile; // TODO, another way to quit without selecting...
+		}
+		wait_us(80000);
+	}
+	return 0;
+}
+
+void clear_ram()
+{
+     582:	fd          	im -3
+     583:	3d          	pushspadd
+     584:	0d          	popsp
+
+00000585 <.LM26>:
+	int i=0;
+     585:	80          	im 0
+
+00000586 <.LM27>:
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+	*zpu_ledr = 0xffffffff;
+     586:	0b          	nop
+     587:	80          	im 0
+     588:	fc          	im -4
+     589:	b0          	im 48
+     58a:	08          	load
+     58b:	53          	storesp 12
+     58c:	53          	storesp 12
+     58d:	ff          	im -1
+     58e:	72          	loadsp 8
+     58f:	0c          	store
+
+00000590 <.LM28>:
+	*zpu_ledg = 0x0;
+     590:	80          	im 0
+     591:	fc          	im -4
+     592:	b4          	im 52
+     593:	08          	load
+     594:	73          	loadsp 12
+     595:	71          	loadsp 4
+     596:	0c          	store
+     597:	52          	storesp 8
+
+00000598 <.LM29>:
+	wait_us(600);
+     598:	84          	im 4
+     599:	d8          	im -40
+     59a:	51          	storesp 4
+     59b:	fe          	im -2
+     59c:	96          	im 22
+     59d:	3f          	callpcrel
+
+0000059e <.LM30>:
+	
+	for (i=0x200000; i!=0x280000; i+=1)
+     59e:	88          	im 8
+     59f:	80          	im 0
+     5a0:	0a          	flip
+     5a1:	53          	storesp 12
+
+000005a2 <.L32>:
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+     5a2:	80          	im 0
+     5a3:	73          	loadsp 12
+     5a4:	70          	loadsp 0
+     5a5:	81          	im 1
+     5a6:	05          	add
+     5a7:	55          	storesp 20
+     5a8:	34          	storeb
+
+000005a9 <.LM32>:
+     5a9:	72          	loadsp 8
+     5aa:	a8          	im 40
+     5ab:	80          	im 0
+     5ac:	0a          	flip
+     5ad:	2e          	eq
+     5ae:	09          	not
+     5af:	81          	im 1
+     5b0:	06          	and
+     5b1:	f0          	im -16
+     5b2:	38          	neqbranch
+
+000005b3 <.LM33>:
+	}
+
+	*zpu_ledr = 0x55555555;
+     5b3:	80          	im 0
+     5b4:	fc          	im -4
+     5b5:	b0          	im 48
+     5b6:	08          	load
+     5b7:	54          	storesp 16
+     5b8:	85          	im 5
+     5b9:	aa          	im 42
+     5ba:	d5          	im -43
+     5bb:	aa          	im 42
+     5bc:	d5          	im -43
+     5bd:	74          	loadsp 16
+     5be:	0c          	store
+
+000005bf <.LM34>:
+	*zpu_ledg = 0x55555555;
+     5bf:	80          	im 0
+     5c0:	fc          	im -4
+     5c1:	b4          	im 52
+     5c2:	08          	load
+     5c3:	52          	storesp 8
+     5c4:	85          	im 5
+     5c5:	aa          	im 42
+     5c6:	d5          	im -43
+     5c7:	aa          	im 42
+     5c8:	d5          	im -43
+     5c9:	72          	loadsp 8
+     5ca:	0c          	store
+
+000005cb <.LM35>:
+
+	for (i=0x800000; i!=0x1000000; i+=4)
+     5cb:	82          	im 2
+     5cc:	80          	im 0
+     5cd:	0a          	flip
+     5ce:	53          	storesp 12
+
+000005cf <.L36>:
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+     5cf:	80          	im 0
+     5d0:	73          	loadsp 12
+     5d1:	70          	loadsp 0
+     5d2:	84          	im 4
+     5d3:	05          	add
+     5d4:	55          	storesp 20
+     5d5:	0c          	store
+
+000005d6 <.LM37>:
+     5d6:	72          	loadsp 8
+     5d7:	81          	im 1
+     5d8:	80          	im 0
+     5d9:	0a          	flip
+     5da:	2e          	eq
+     5db:	09          	not
+     5dc:	81          	im 1
+     5dd:	06          	and
+     5de:	f0          	im -16
+     5df:	38          	neqbranch
+
+000005e0 <.LM38>:
+	}
+
+	*zpu_ledr = 0;
+     5e0:	80          	im 0
+     5e1:	74          	loadsp 16
+     5e2:	0c          	store
+
+000005e3 <.LM39>:
+	*zpu_ledg = 0xffffffff;
+     5e3:	ff          	im -1
+     5e4:	72          	loadsp 8
+     5e5:	0c          	store
+
+000005e6 <.LM40>:
+	wait_us(600);
+     5e6:	84          	im 4
+     5e7:	d8          	im -40
+     5e8:	51          	storesp 4
+     5e9:	fd          	im -3
+     5ea:	c8          	im -56
+     5eb:	3f          	callpcrel
+
+000005ec <.LM41>:
+	return;
+     5ec:	85          	im 5
+     5ed:	3d          	pushspadd
+     5ee:	0d          	popsp
+     5ef:	04          	poppc
+
+000005f0 <clear_64k_ram>:
+}
+
+void clear_64k_ram()
+{
+     5f0:	fd          	im -3
+     5f1:	3d          	pushspadd
+     5f2:	0d          	popsp
+
+000005f3 <.LM43>:
+	int i=0;
+     5f3:	80          	im 0
+
+000005f4 <.LM44>:
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+     5f4:	0b          	nop
+     5f5:	80          	im 0
+     5f6:	fc          	im -4
+     5f7:	b0          	im 48
+     5f8:	08          	load
+     5f9:	53          	storesp 12
+     5fa:	53          	storesp 12
+     5fb:	ff          	im -1
+     5fc:	87          	im 7
+     5fd:	c3          	im -61
+     5fe:	e1          	im -31
+     5ff:	f0          	im -16
+     600:	72          	loadsp 8
+     601:	0c          	store
+
+00000602 <.LM45>:
+	*zpu_ledg = 0x0;
+     602:	80          	im 0
+     603:	fc          	im -4
+     604:	b4          	im 52
+     605:	08          	load
+     606:	73          	loadsp 12
+     607:	71          	loadsp 4
+     608:	0c          	store
+     609:	52          	storesp 8
+
+0000060a <.LM46>:
+	wait_us(200000);
+     60a:	8c          	im 12
+     60b:	9a          	im 26
+     60c:	c0          	im -64
+     60d:	51          	storesp 4
+     60e:	fd          	im -3
+     60f:	a3          	im 35
+     610:	3f          	callpcrel
+
+00000611 <.LM47>:
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+     611:	88          	im 8
+     612:	80          	im 0
+     613:	0a          	flip
+     614:	53          	storesp 12
+
+00000615 <.L46>:
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+     615:	80          	im 0
+     616:	73          	loadsp 12
+     617:	70          	loadsp 0
+     618:	81          	im 1
+     619:	05          	add
+     61a:	55          	storesp 20
+     61b:	34          	storeb
+
+0000061c <.LM49>:
+     61c:	72          	loadsp 8
+     61d:	81          	im 1
+     61e:	84          	im 4
+     61f:	80          	im 0
+     620:	80          	im 0
+     621:	2e          	eq
+     622:	09          	not
+     623:	81          	im 1
+     624:	06          	and
+     625:	ef          	im -17
+     626:	38          	neqbranch
+
+00000627 <.LM50>:
+	}
+
+	*zpu_ledr = 0x55555555;
+     627:	80          	im 0
+     628:	fc          	im -4
+     629:	b0          	im 48
+     62a:	08          	load
+     62b:	54          	storesp 16
+     62c:	85          	im 5
+     62d:	aa          	im 42
+     62e:	d5          	im -43
+     62f:	aa          	im 42
+     630:	d5          	im -43
+     631:	74          	loadsp 16
+     632:	0c          	store
+
+00000633 <.LM51>:
+	*zpu_ledg = 0x55555555;
+     633:	80          	im 0
+     634:	fc          	im -4
+     635:	b4          	im 52
+     636:	08          	load
+     637:	52          	storesp 8
+     638:	85          	im 5
+     639:	aa          	im 42
+     63a:	d5          	im -43
+     63b:	aa          	im 42
+     63c:	d5          	im -43
+     63d:	72          	loadsp 8
+     63e:	0c          	store
+
+0000063f <.LM52>:
+
+	for (i=0x800000; i!=0x810000; i+=4)
+     63f:	82          	im 2
+     640:	80          	im 0
+     641:	0a          	flip
+     642:	53          	storesp 12
+
+00000643 <.L50>:
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+     643:	80          	im 0
+     644:	73          	loadsp 12
+     645:	70          	loadsp 0
+     646:	84          	im 4
+     647:	05          	add
+     648:	55          	storesp 20
+     649:	0c          	store
+
+0000064a <.LM54>:
+     64a:	72          	loadsp 8
+     64b:	84          	im 4
+     64c:	84          	im 4
+     64d:	80          	im 0
+     64e:	80          	im 0
+     64f:	2e          	eq
+     650:	09          	not
+     651:	81          	im 1
+     652:	06          	and
+     653:	ef          	im -17
+     654:	38          	neqbranch
+
+00000655 <.LM55>:
+	}
+
+	*zpu_ledr = 0;
+     655:	80          	im 0
+     656:	74          	loadsp 16
+     657:	0c          	store
+
+00000658 <.LM56>:
+	*zpu_ledg = 0xf0f0f0f0;
+     658:	ff          	im -1
+     659:	87          	im 7
+     65a:	c3          	im -61
+     65b:	e1          	im -31
+     65c:	f0          	im -16
+     65d:	72          	loadsp 8
+     65e:	0c          	store
+
+0000065f <.LM57>:
+	wait_us(200000);
+     65f:	8c          	im 12
+     660:	9a          	im 26
+     661:	c0          	im -64
+     662:	51          	storesp 4
+     663:	fc          	im -4
+     664:	ce          	im -50
+     665:	3f          	callpcrel
+
+00000666 <.LM58>:
+	return;
+     666:	85          	im 5
+     667:	3d          	pushspadd
+     668:	0d          	popsp
+     669:	04          	poppc
+
+0000066a <reset_6502>:
+}
+
+void reset_6502(unsigned int reset_n)
+{
+     66a:	ff          	im -1
+     66b:	3d          	pushspadd
+     66c:	0d          	popsp
+
+0000066d <.LM60>:
+	int prev = *zpu_config;
+     66d:	80          	im 0
+     66e:	fc          	im -4
+     66f:	c4          	im -60
+     670:	08          	load
+     671:	70          	loadsp 0
+     672:	08          	load
+     673:	52          	storesp 8
+     674:	52          	storesp 8
+
+00000675 <.LM61>:
+	if (reset_n == 1)
+     675:	73          	loadsp 12
+     676:	81          	im 1
+     677:	2e          	eq
+     678:	8b          	im 11
+     679:	38          	neqbranch
+
+0000067a <.LM62>:
+		*zpu_config = prev&~(1<<7);
+	else
+		*zpu_config = prev|(1<<7);
+     67a:	70          	loadsp 0
+     67b:	81          	im 1
+     67c:	80          	im 0
+     67d:	07          	or
+     67e:	72          	loadsp 8
+     67f:	0c          	store
+
+00000680 <.LM63>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+     680:	83          	im 3
+     681:	3d          	pushspadd
+     682:	0d          	popsp
+     683:	04          	poppc
+
+00000684 <.L61>:
+     684:	70          	loadsp 0
+     685:	fe          	im -2
+     686:	ff          	im -1
+     687:	06          	and
+
+00000688 <.LM65>:
+     688:	72          	loadsp 8
+     689:	0c          	store
+
+0000068a <.LM66>:
+     68a:	83          	im 3
+     68b:	3d          	pushspadd
+     68c:	0d          	popsp
+     68d:	04          	poppc
+
+0000068e <pause_6502>:
+
+void pause_6502(unsigned int pause)
+{
+     68e:	ff          	im -1
+     68f:	3d          	pushspadd
+     690:	0d          	popsp
+
+00000691 <.LM68>:
+	int prev = *zpu_config;
+     691:	80          	im 0
+     692:	fc          	im -4
+     693:	c4          	im -60
+     694:	08          	load
+     695:	70          	loadsp 0
+     696:	08          	load
+     697:	52          	storesp 8
+     698:	52          	storesp 8
+
+00000699 <.LM69>:
+	if (pause == 0)
+     699:	73          	loadsp 12
+     69a:	8b          	im 11
+     69b:	38          	neqbranch
+
+0000069c <.LM70>:
+		*zpu_config = prev&~(1<<6);
+     69c:	70          	loadsp 0
+     69d:	ff          	im -1
+     69e:	bf          	im 63
+     69f:	06          	and
+
+000006a0 <.LM71>:
+	else
+		*zpu_config = prev|(1<<6);
+     6a0:	72          	loadsp 8
+     6a1:	0c          	store
+
+000006a2 <.LM72>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+     6a2:	83          	im 3
+     6a3:	3d          	pushspadd
+     6a4:	0d          	popsp
+     6a5:	04          	poppc
+
+000006a6 <.L63>:
+     6a6:	70          	loadsp 0
+     6a7:	80          	im 0
+     6a8:	c0          	im -64
+     6a9:	07          	or
+     6aa:	72          	loadsp 8
+     6ab:	0c          	store
+
+000006ac <.LM74>:
+     6ac:	83          	im 3
+     6ad:	3d          	pushspadd
+     6ae:	0d          	popsp
+     6af:	04          	poppc
+
+000006b0 <disk_initialize>:
+
+void actions()
+{
+	unsigned int i = 0;
+	//unsigned volatile char * store = 0xf00000; // SDRAM - fails!!
+	unsigned volatile char * store = 0x27f000; // SRAM...
+	unsigned volatile char * store2 = 0x270000; // custom chips...
+
+	if ((1&*zpu_key) == 1)
+	{
+		unsigned char volatile * mem;
+		unsigned char volatile * mem2;
+		unsigned char volatile * mem3;
+		unsigned char store_portb;
+		int reboot = 0;
+		int temp;
+		int row = 0;
+		int next = 0;
+		int go = 0;
+
+		// stop 6502
+		pause_6502(1);
+
+		// TODO - 
+		// menu for 64k/128k/320K Compy/320K Rambo
+		// menu for ROM bank
+		// menu for GPIO on/off
+
+		initdebug(1);
+
+		mem = 0x9c00 + 0x10000;
+		// Copy 1k from 0x$9c00 to sdram
+		// 0x200000; sram
+		// 0x800000; sdram (always use...)
+		for (i=0x0; i!=1024; i++)
+		{
+			store[i] = mem[i];
+		}
+		for (i=0x40; i!=1024; i++)
+		{
+			mem[i] = 0;
+		}
+
+		{
+			//gtia
+			mem2 = 0x20000;
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				store2[i] = mem2[i];
+				mem3[i] = 0;
+			}
+		}
+
+		store_portb = *atari_portb;
+
+		// write a display list at 9c00
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x9c
+		};
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x9c;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+		*atari_portb = 0xff;
+		*atari_skctl = 0x3;
+		*atari_chactl = 0x2;
+
+		for (;;)
+		{
+			wait_us(120000);
+			topofscreen();
+			for (i=0; i!=(24*40); ++i)
+			{
+				*(unsigned char volatile *)(i+0x10000+40000) = 0x00;
+			}
+			// 0-5 speed
+			// 6-pause
+			// 7-reset
+			// 8-9-ram
+			// 12-13-rom
+			// 16-gpio_enable
+			debug("System settings\n");
+			debug("---------------\n");
+			debug("Memory:");
+			temp = 0xf&((*zpu_config)>>8);
+			if (row == 0)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xfffff0ff)|((temp&0x3)<<8);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("64KiB");
+				break;
+			case 1:
+				debug("128KiB");
+				break;
+			case 2:
+				debug("320KiB Compy Shop");
+				break;
+			case 3:
+				debug("320KiB Rambo");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("ROM bank:");
+			temp = 0xf&((*zpu_config)>>12);
+			if (row == 1)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					*zpu_config = (*zpu_config&0xffff0fff)|((temp&0x3)<<12);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			switch (temp)
+			{
+			case 0:
+				debug("0 (default:XL)");
+				break;
+			case 1:
+				debug("1 (default:XL + hi speed)");
+				break;
+			case 2:
+				debug("2 (default:Ultimon)");
+				break;
+			case 3:
+				debug("3 (default:OS B + hi speed)");
+				break;
+			default:
+				debug("Unknown");
+				break;
+			}
+			debug("\n");
+			debug("Speed:");
+			temp = 0x3f&((*zpu_config)>>0);
+			if (row == 2)
+			{
+				if (next != 0)
+				{
+					temp = temp+next;
+					if (temp < 0) temp =0;
+					*zpu_config = (*zpu_config&0xffffffc0)|(temp&0x3f);
+					next = 0;
+					go = 0;
+					continue;
+				}
+				debugoffset(128);
+			}
+			plotnextnumber(57500/(temp+1));
+			debug(" KHz\nD1:"); // Bring up selector, instead of booting changes disk image
+			if (row == 3)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d1);
+			debug("\nD2:");
+			if (row == 4)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d2);
+			debug("\nD3:");
+			if (row == 5)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d3);
+			debug("\nD4:");
+			if (row == 6)
+			{
+				debugoffset(128);
+			}
+			debug(filename_d4);
+			if (row>=3 && row<7)
+			{
+				if (go==1)
+				{
+					switch (row)
+					{
+					case 3:
+						selectfile(filename_d1);
+						break;
+					case 4:
+						selectfile(filename_d2);
+						break;
+					case 5:
+						selectfile(filename_d3);
+						break;
+					case 6:
+						selectfile(filename_d4);
+						break;
+					}
+					opendrive = row-2;
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d4[i];
+						filename_d4[i] = filename_d3[i];
+						filename_d3[i] = filename_d2[i];
+						filename_d2[i] = filename_d1[i];
+						filename_d1[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+				if (next==-1)
+				{
+					for (i=0;i!=15;++i)
+					{
+						char temp = filename_d1[i];
+						filename_d1[i] = filename_d2[i];
+						filename_d2[i] = filename_d3[i];
+						filename_d3[i] = filename_d4[i];
+						filename_d4[i] = temp;
+					}
+					next = 0;
+					go = 0;
+					continue;
+				}
+			}
+			if (row == 7)
+			{
+				debugoffset(128);
+			}
+			debug("\nReboot");
+			if (row == 7)
+			{
+				if (go==1)
+				{
+					reboot = 1;
+					break;
+				}
+			}
+			if (row == 8)
+			{
+				debugoffset(128);
+			}
+			debug("\nExit");
+			if (row == 8)
+			{
+				if (go==1)
+					break;
+			}
+
+			next = 0;
+			go = 0;
+
+			for (;;)
+			{
+				unsigned char porta = *atari_porta;
+				if (0==(porta&0x2)) // down
+				{
+					row+=1;
+					if (row>8) row = 8;
+					break;
+				}
+				else if (0==(porta&0x1)) // up
+				{
+					row-=1;
+					if (row<0) row = 0;
+					break;
+				}
+				else if (0==(porta&0x8)) // right
+				{
+					next = 1;
+					break;
+				}
+				else if (0==(porta&0x4)) // left
+				{
+					next = -1;
+					break;
+				}
+				else if (0==(*atari_trig0)) // fire
+				{
+					go = 1;
+					while(0==(*atari_trig0));
+					break;
+				}
+				topofscreen();
+				//plotnextnumber(porta);
+				*atari_colbk = *atari_random;
+				//wait_us(200);
+			}
+		}
+
+		// wait 2 seconds
+		//for (i=0; i!=2000; ++i)
+		//{
+		//	*atari_colbk = *atari_random;
+		//	wait_us(1000);
+		//}
+
+		for (i=0x040; i!=1024; i++)
+		{
+			mem[i] = store[i];
+		}
+
+		{
+			//gtia
+			mem3 = 0x10000;
+			for (i=0xd000; i!=0xd01f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//pokey1/2
+			for (i=0xd200; i!=0xd21f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+			//antic
+			for (i=0xd400; i!=0xd40f; i++)
+			{
+				mem3[i] = store2[i];
+			}
+		}
+		*atari_portb = store_portb;
+		initdebug(debugmode);
+
+
+		if (reboot)
+		{
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		// start 6502
+		pause_6502(0);
+	}
+
+	if ((2&*zpu_key) == 2)
+	{
+		int i;
+		unsigned char volatile * mem;
+
+		// TODO - disk swapping!
+
+		// OSD file selector...
+		// stop 6502
+		pause_6502(1);
+		clear_64k_ram();
+	
+		char dl[] = {
+			0x70,0x70,0x70,
+			0x42,0x40,0x9c,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,0x2,0x2,
+			0x2,0x2,0x2,
+			0x70,
+			0x41,0x00,0x06
+		};
+		mem = 0x600 + 0x10000;
+		for (i=0; i!=sizeof(dl); ++i)
+		{
+			mem[i] = dl[i];
+		}
+
+		// point antic at my display list
+		*atari_dlistl = 0x00;
+		*atari_dlisth = 0x06;
+		*atari_colbk = 0x00;
+		*atari_colpf1 = 0x0f;
+		*atari_colpf2 = 0x00;
+		*atari_prior = 0x00;
+		*atari_portb = 0xff;
+		*atari_chbase = 0xe0;
+		*atari_dmactl = 0x22;
+
+		initdebug(1);
+
+		if (selectfile(filename_d1))
+		{
+			opendrive = 1;
+			debug("Booting...");
+			wait_us(500000);
+
+			// reset process
+			reset_6502(0);
+			*atari_nmien = 0x00;
+			clear_64k_ram();
+			reset_6502(1);
+		}
+
+		initdebug(debugmode);
+		pause_6502(0);
+	}
+	if ((4&*zpu_key) == 4)
+	{
+		// reset process
+		reset_6502(0);
+		reset_6502(1);
+	}
+	if ((8&*zpu_key) == 8)
+	{
+		// reset process
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+	}
+}
+
+int sdrive_main();
+int main(void)
+{
+	unsigned int i=0;
+	debugmode = 0;
+	selfileno = 0;
+	opendrive = 0;
+	pause_6502(1);
+
+	speed = speedslow;
+	//FIXME if (2==(2&(*zpu_switches)))
+	if (0)
+	{
+		debugmode = 1;
+	}
+
+	initdebug(debugmode);
+
+	if (debugmode)
+	{
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+
+		wait_us(2000000);
+	}
+
+	//FIXME if (1==(1&(*zpu_switches)))
+	{
+		sdcard();
+	}
+
+	pause_6502(1);
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+
+	while (1)
+	{
+		actions();
+	}
+	return 0;
+}
+
+/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for Petit FatFs (C)ChaN, 2009      */
+/*-----------------------------------------------------------------------*/
+
+#include "diskio.h"
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Initialize Disk Drive                                                 */
+/*-----------------------------------------------------------------------*/
+
+DSTATUS disk_initialize (void)
+{
+	DSTATUS stat;
+
+	n_actual_mmc_sector = 0xffffffff;
+     6b0:	ff          	im -1
+     6b1:	0b          	nop
+     6b2:	83          	im 3
+     6b3:	e0          	im -32
+     6b4:	b0          	im 48
+     6b5:	0c          	store
+
+000006b6 <.L68>:
+	do
+	{
+		mmcInit();
+     6b6:	80          	im 0
+     6b7:	cd          	im -51
+     6b8:	ba          	im 58
+     6b9:	3f          	callpcrel
+
+000006ba <.LBE2>:
+	}
+     6ba:	80          	im 0
+     6bb:	d0          	im -48
+     6bc:	be          	im 62
+     6bd:	3f          	callpcrel
+     6be:	83          	im 3
+     6bf:	e0          	im -32
+     6c0:	80          	im 0
+     6c1:	08          	load
+     6c2:	f3          	im -13
+     6c3:	38          	neqbranch
+
+000006c4 <.LM79>:
+	while(mmcReset());	//dokud nenulove, tak smycka (return 0 => ok!)
+
+	set_spi_clock_freq();
+     6c4:	80          	im 0
+     6c5:	d3          	im -45
+     6c6:	83          	im 3
+     6c7:	3f          	callpcrel
+
+000006c8 <.LM80>:
+
+	stat = RES_OK;
+
+	return stat;
+}
+     6c8:	80          	im 0
+     6c9:	0b          	nop
+     6ca:	83          	im 3
+     6cb:	e0          	im -32
+     6cc:	80          	im 0
+     6cd:	0c          	store
+     6ce:	04          	poppc
+
+000006cf <disk_writep>:
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Partial Sector                                                   */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_readp (
+	BYTE* dest,			/* Pointer to the destination object */
+	DWORD sector,		/* Sector number (LBA) */
+	WORD sofs,			/* Offset in the sector */
+	WORD count			/* Byte count (bit15:destination) */
+)
+{
+	DRESULT res;
+
+	/*debug("readp:");
+	plotnextnumber(sector);
+	debug(" ");
+	plotnextnumber((int)dest);
+	debug(" ");
+	plotnextnumber(sofs);
+	debug(" ");
+	plotnextnumber(count);
+	debug(" ");
+	plotnextnumber(atari_sector_buffer);
+	debug(" ");
+	plotnextnumber(mmc_sector_buffer);
+	debug("\n");
+	*/
+	// Put your code here
+	mmcReadCached(sector);
+	for(;count>0;++sofs,--count)
+	{
+		unsigned char x = mmc_sector_buffer[sofs];
+		//printf("char:%02x loc:%d", x,sofs);
+		*dest++ = x;
+	}
+
+	res = RES_OK;
+
+	return res;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Partial Sector                                                  */
+/*-----------------------------------------------------------------------*/
+
+DRESULT disk_writep (const BYTE* buff, DWORD sc)
+{
+     6cf:	80          	im 0
+     6d0:	3d          	pushspadd
+     6d1:	0d          	popsp
+
+000006d2 <.LM82>:
+	DRESULT res;
+
+
+	if (!buff) {
+		if (sc) {
+
+			// Initiate write process
+
+		} else {
+
+			// Finalize write process
+
+		}
+	} else {
+
+		// Send data to the disk
+
+	}
+
+	return res;
+}
+     6d2:	70          	loadsp 0
+     6d3:	83          	im 3
+     6d4:	e0          	im -32
+     6d5:	80          	im 0
+     6d6:	0c          	store
+     6d7:	82          	im 2
+     6d8:	3d          	pushspadd
+     6d9:	0d          	popsp
+     6da:	04          	poppc
+
+000006db <byteswap>:
+
+
+struct ATRHeader
+{
+	u16 wMagic;
+	u16 wPars;
+	u16 wSecSize;
+	u08 btParsHigh;
+	u32 dwCRC;
+} __attribute__((packed));
+int offset;
+int xex_loader;
+int xex_size;
+uint8_t xex_name[12];
+uint8_t boot_xex_loader[179] = {
+	0x72,0x02,0x5f,0x07,0xf8,0x07,0xa9,0x00,0x8d,0x04,0x03,0x8d,0x44,0x02,0xa9,0x07,
+	0x8d,0x05,0x03,0xa9,0x70,0x8d,0x0a,0x03,0xa9,0x01,0x8d,0x0b,0x03,0x85,0x09,0x60,
+	0x7d,0x8a,0x48,0x20,0x53,0xe4,0x88,0xd0,0xfa,0x68,0xaa,0x8c,0x8e,0x07,0xad,0x7d,
+	0x07,0xee,0x8e,0x07,0x60,0xa9,0x93,0x8d,0xe2,0x02,0xa9,0x07,0x8d,0xe3,0x02,0xa2,
+	0x02,0x20,0xda,0x07,0x95,0x43,0x20,0xda,0x07,0x95,0x44,0x35,0x43,0xc9,0xff,0xf0,
+	0xf0,0xca,0xca,0x10,0xec,0x30,0x06,0xe6,0x45,0xd0,0x02,0xe6,0x46,0x20,0xda,0x07,
+	0xa2,0x01,0x81,0x44,0xb5,0x45,0xd5,0x43,0xd0,0xed,0xca,0x10,0xf7,0x20,0xd2,0x07,
+	0x4c,0x94,0x07,0xa9,0x03,0x8d,0x0f,0xd2,0x6c,0xe2,0x02,0xad,0x8e,0x07,0xcd,0x7f,
+	0x07,0xd0,0xab,0xee,0x0a,0x03,0xd0,0x03,0xee,0x0b,0x03,0xad,0x7d,0x07,0x0d,0x7e,
+	0x07,0xd0,0x8e,0x20,0xd2,0x07,0x6c,0xe0,0x02,0x20,0xda,0x07,0x8d,0xe0,0x02,0x20,
+	0xda,0x07,0x8d,0xe1,0x02,0x2d,0xe0,0x02,0xc9,0xff,0xf0,0xed,0xa9,0x00,0x8d,0x8e,
+	0x07,0xf0,0x82 };
+//  relokacni tabulka neni potreba, meni se vsechny hodnoty 0x07
+//  (melo by byt PRESNE 20 vyskytu! pokud je jich vic, pak bacha!!!)
+
+void byteswap(WORD * inw)
+{
+     6db:	ff          	im -1
+     6dc:	3d          	pushspadd
+     6dd:	0d          	popsp
+     6de:	73          	loadsp 12
+
+000006df <.LM84>:
+	unsigned char * in = (unsigned char *)inw;
+	unsigned char temp = in[0];
+     6df:	70          	loadsp 0
+     6e0:	33          	loadb
+     6e1:	53          	storesp 12
+     6e2:	51          	storesp 4
+
+000006e3 <.LM85>:
+	in[0] = in[1];
+     6e3:	81          	im 1
+     6e4:	11          	addsp 4
+     6e5:	33          	loadb
+     6e6:	71          	loadsp 4
+     6e7:	34          	storeb
+
+000006e8 <.LM86>:
+	in[1] = temp;
+     6e8:	71          	loadsp 4
+     6e9:	81          	im 1
+     6ea:	12          	addsp 8
+     6eb:	34          	storeb
+     6ec:	83          	im 3
+     6ed:	3d          	pushspadd
+     6ee:	0d          	popsp
+     6ef:	04          	poppc
+
+000006f0 <get_checksum>:
+}
+
+struct command
+{
+	u08 deviceId;
+	u08 command;
+	u08 aux1;
+	u08 aux2;
+	u08 chksum;
+} __attribute__((packed));
+void getCommand(struct command * cmd)
+{
+	int expchk;
+
+	//debug("Waiting for command\n");
+	//USART_Data_Ready();
+	while (0 == (1&(*zpu_sio)));
+	//debug("Init:");
+	//plotnextnumber(*zpu_sio);
+	USART_Init(speed+6);
+	//plotnextnumber(speed);
+	//debug("\n");
+	while (1 == (1&(*zpu_sio)))
+	{
+		actions();
+	}
+	cmd->deviceId = USART_Receive_Byte();
+	cmd->command = USART_Receive_Byte();
+	cmd->aux1 = USART_Receive_Byte();
+	cmd->aux2 = USART_Receive_Byte();
+	cmd->chksum = USART_Receive_Byte();
+	while (0 == (1&(*zpu_sio)));
+	debug("cmd:");
+	//debug("Gone high\n");
+	atari_sector_buffer[0] = cmd->deviceId;
+	atari_sector_buffer[1] = cmd->command;
+	atari_sector_buffer[2] = cmd->aux1;
+	atari_sector_buffer[3] = cmd->aux2;
+	expchk = get_checksum(&atari_sector_buffer[0],4);
+
+	//debug("Device id:");
+	plotnextnumber(cmd->deviceId);
+	//debug("\n");
+	//debug("command:");
+	plotnextnumber(cmd->command);
+	//debug("\n");
+	//debug("aux1:");
+	plotnextnumber(cmd->aux1);
+	//debug("\n");
+	//debug("aux2:");
+	plotnextnumber(cmd->aux2);
+	//debug("\n");
+	//debug("chksum:");
+	plotnextnumber(cmd->chksum);
+	plotnextnumber(expchk);
+
+	if (expchk!=cmd->chksum || USART_Framing_Error())
+	{
+		debug("ERR ");
+		//wait_us(1000000);
+		if (speed == speedslow)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+	}
+	debug("\n");
+
+	DELAY_T2_MIN;
+}
+
+void openfile(const char * filename)
+{
+	WORD read = 0;
+	int dot = 0;
+	int xfd = 0;
+	validfile = 0;
+	debug("Opening:");
+	debug(filename);
+	debug(":");
+	if (FR_OK!=pf_open(filename))
+	{
+		debug("fail\n");
+		return; //while(1);
+		//while(1);
+	}
+	debug("ok\n");
+
+	while (1)
+	{
+		if (filename[dot] == '\0')
+			break;
+		if (filename[dot] != '.')
+		{
+			++dot;
+			continue;
+		}
+		if (filename[dot+1] == 'X' || filename[dot+1] == 'x')
+			if (filename[dot+2] == 'F' || filename[dot+2] == 'f')
+				if (filename[dot+3] == 'D' || filename[dot+3] == 'd')
+				{
+					xfd = 1;
+					break;
+				}
+		break;
+	}
+
+	// Read header
+	read = 0;
+	pf_read(&atr_header, 16, &read);
+	if (read!=16)
+	{
+		debug("Could not read header\n");
+		return; //while(1);
+	}
+	byteswap(&atr_header.wMagic);
+	byteswap(&atr_header.wPars);
+	byteswap(&atr_header.wSecSize);
+	/*debug("\nHeader:");
+	plotnextnumber(atr_header.wMagic);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wPars);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.wSecSize);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.btParsHigh);
+	plotnext(toatarichar(' '));
+	plotnextnumber(atr_header.dwCRC);
+	debug("\n");
+	*/
+
+	xex_loader = 0;
+	if (xfd == 1)
+	{
+		debug("XFD ");
+		// build a fake atr header
+		offset = 0;
+		atr_header.wMagic = 0x296;
+		atr_header.wPars = filesize(filename)/16;
+		atr_header.wSecSize = 0x80;
+	}
+	else if (atr_header.wMagic == 0xFFFF) // XEX
+	{
+		int i;
+		debug("XEX ");
+		offset = -256;
+		xex_loader = 1;
+		atr_header.wMagic = 0xffff;
+		xex_size = filesize(filename);
+		atr_header.wPars = xex_size/16;
+		atr_header.wSecSize = XEX_SECTOR_SIZE;
+		for (i=0;i!=12;++i)
+			xex_name[i] = filename[i];
+	}
+	else if (atr_header.wMagic == 0x296) // ATR
+	{
+		debug("ATR ");
+		offset = 16;
+	}
+	else
+	{
+		debug("Unknown file type");
+		return;
+	}
+
+	if (atr_header.wSecSize == 0x80)
+	{
+		if (atr_header.wPars>(720*128/16))
+			debug("MD ");
+		else
+			debug("SD ");
+	}
+	else if (atr_header.wSecSize == 0x100)
+	{
+		debug("DD ");
+	}
+	else if (atr_header.wSecSize < 0x100)
+	{
+		debug("XD ");
+	}
+	else
+	{
+		debug("BAD sector size");
+		return;
+	}	
+	plotnextnumber(atr_header.wPars);
+	debug("0\n");
+	validfile = 1;
+}
+
+void sdcard()
+{
+	int i;
+	int commandcount = 0;
+	int badcommandcount = 0;
+	WORD read;
+	struct command command;
+	int location;
+	char const * default_filename = "BOOT.ATR";
+
+	debug("sdcard\n");
+	
+	debug("disk_init:");
+	if(disk_initialize()!=RES_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("mount:");
+	if(pf_mount(&fatfs)!=FR_OK)
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	debug("opendir:");
+	if (FR_OK != pf_opendir(&dir,"/"))
+	{
+		debug("fail\n");
+		return;
+	}
+	debug("ok\n");
+
+	while (FR_OK == pf_readdir(&dir,&filinfo) && filinfo.fname[0]!='\0')
+	{
+		debug(filinfo.fname);
+	}
+
+	for (i=0;i!=15;++i)
+	{
+		filename_d1[i] = default_filename[i];
+		filename_d2[i] = default_filename[i];
+		filename_d3[i] = default_filename[i];
+		filename_d4[i] = default_filename[i];
+		if (default_filename[i] == 0) break;
+	}
+	opendrive = 1;
+	openfile(filename_d1);
+
+	reset_6502(0);
+	*atari_nmien = 0x00;
+	clear_64k_ram();
+	reset_6502(1);
+	pause_6502(0);
+	
+	USART_Init(speed+6);
+	while (1)
+	{
+		getCommand(&command);
+		++commandcount;
+		/*FIXME if (commandcount==4 && (4==(4&(*zpu_switches))))
+		{
+			debug("Paused\n");
+			pause_6502(1);
+			while(1);
+		}*/
+		/*if (badcommandcount==8)
+		{
+			debug("Stuck?\n");
+			pause_6502(1);
+			while(1);
+		}*/
+
+  		if (command.deviceId >= 0x31 && command.deviceId < 0x34)
+ 	 	{
+			int sent = 0;
+			int drive = 0;
+
+			drive = command.deviceId&0xf;
+			if (drive!=opendrive)
+			{
+				opendrive = drive;
+				switch(drive)
+				{
+				case 1:
+					openfile(filename_d1);
+					break;
+				case 2:
+					openfile(filename_d2);
+					break;
+				case 3:
+					openfile(filename_d3);
+					break;
+				case 4:
+					openfile(filename_d4);
+					break;
+				}
+			}
+
+			if (!validfile)
+			{
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+				//USART_Receive_Mode();
+				continue;
+			}
+
+			switch (command.command)
+			{
+			case 0x3f:
+				{
+				debug("Speed:");
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+				atari_sector_buffer[0] = speedfast;
+				hexdump_pure(atari_sector_buffer,1);
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(1);
+				sent = 1;
+		if (sector == 0)
+		{
+			speed = speedfast;
+			debug("SPDF");
+			plotnextnumber(speed);
+		}
+		else
+		{
+			speed = speedslow;
+			debug("SPDS");
+			plotnextnumber(speed);
+		}
+				}
+			case 0x53:
+				{
+				unsigned char status;
+				debug("Stat:");
+				USART_Transmit_Mode();
+				send_ACK();
+				clearAtariSectorBuffer();
+
+				status = 0x10; // Motor on;
+				status |= 0x08; // write protected; // no write support yet...
+				if (atr_header.wSecSize == 0x80) // normal sector size
+				{
+					if (atr_header.wPars>(720*128/16))
+					{
+						status |= 0x80; // medium density - or a strange one...
+					}
+				}
+				else
+				{
+					status |= 0x20; // 256 byte sectors
+				}
+				atari_sector_buffer[0] = status;
+				atari_sector_buffer[1] = 0xff;
+				atari_sector_buffer[2] = 0xe0;
+				atari_sector_buffer[3] = 0x0;
+				hexdump_pure(atari_sector_buffer,4); // Somehow with this...
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(4);
+				sent = 1;
+				plotnextnumber(atari_sector_buffer[0]); // and this... The wrong checksum is sent!!
+				debug(":done\n");
+				}
+				break;
+			case 0x50: // write
+			case 0x57: // write with verify
+			default:
+				// TODO
+				//USART_Transmit_Mode();
+				//send_NACK();
+				//USART_Wait_Transmit_Complete();
+				//USART_Receive_Mode();
+				break;
+			case 0x52: // read
+				{
+				int sector = ((int)command.aux1) + (((int)command.aux2&0x7f)<<8);
+				int sectorSize = 0;
+
+				USART_Transmit_Mode();
+				send_ACK();
+				read = 0;
+				debug("Sector:");
+				plotnextnumber(sector);
+				debug(":");
+				if(xex_loader)         //n_sector>0 && //==0 se overuje hned na zacatku
+				{
+					//sektory xex bootloaderu, tj. 1 nebo 2
+					u08 i,b;
+					u08 *spt, *dpt;
+					int file_sectors;
+
+					//file_sectors se pouzije pro sektory $168 i $169 (optimalizace)
+					//zarovnano nahoru, tj. =(size+124)/125
+					file_sectors = ((xex_size+(u32)(XEX_SECTOR_SIZE-3-1))/((u32)XEX_SECTOR_SIZE-3));
+
+					debug("XEX ");
+
+					if (sector<=2)
+					{
+						debug("boot ");
+
+						spt= &boot_xex_loader[(u16)(sector-1)*((u16)XEX_SECTOR_SIZE)];
+						dpt= atari_sector_buffer;
+						i=XEX_SECTOR_SIZE;
+						do
+						{
+							b=*spt++;
+							//relokace bootloaderu z $0700 na jine misto
+							//TODO if (b==0x07) b+=bootloader_relocation;
+							*dpt++=b;
+							i--;
+						} while(i);
+					}
+					else
+					if(sector==0x168)
+					{
+						debug("numtobuffer ");
+						//vrati pocet sektoru diskety
+						//byty 1,2
+						goto set_number_of_sectors_to_buffer_1_2;
+					}
+					else
+					if(sector==0x169)
+					{
+						debug("name ");
+						//fatGetDirEntry(FileInfo.vDisk.file_index,5,0);
+						//fatGetDirEntry(FileInfo.vDisk.file_index,0); //ale musi to posunout o 5 bajtu doprava
+			
+						{
+							u08 i,j;
+							for(i=j=0;i<8+3;i++)
+							{
+								if( ((xex_name[i]>='A' && xex_name[i]<='Z') ||
+									(xex_name[i]>='0' && xex_name[i]<='9')) )
+								{
+								  //znak je pouzitelny na Atari
+								  atari_sector_buffer[j]=xex_name[i];
+								  j++;
+								}
+								if ( (i==7) || (i==8+2) )
+								{
+									for(;j<=i;j++) atari_sector_buffer[j]=' ';
+								}
+							}
+							//posune nazev z 0-10 na 5-15 (0-4 budou systemova adresarova data)
+							//musi pozpatku
+							for(i=15;i>=5;i--) atari_sector_buffer[i]=atari_sector_buffer[i-5];
+							//a pak uklidi cely zbytek tohoto sektoru
+							for(i=5+8+3;i<XEX_SECTOR_SIZE;i++)
+								atari_sector_buffer[i]=0x00;
+						}
+
+						//teprve ted muze pridat prvnich 5 bytu na zacatek nulte adresarove polozky (pred nazev)
+						//atari_sector_buffer[0]=0x42;							//0
+						//jestlize soubor zasahuje do sektoru cislo 1024 a vic,
+						//status souboru je $46 misto standardniho $42
+						atari_sector_buffer[0]=(file_sectors>(0x400-0x171))? 0x46 : 0x42; //0
+
+						TWOBYTESTOWORD(atari_sector_buffer+3,0x0171);			//3,4
+set_number_of_sectors_to_buffer_1_2:
+						TWOBYTESTOWORD(atari_sector_buffer+1,file_sectors);		//1,2
+					}
+					else
+					if(sector>=0x171)
+					{
+						debug("data ");
+						pf_lseek(((u32)sector-0x171)*((u32)XEX_SECTOR_SIZE-3));
+						pf_read(&atari_sector_buffer[0], XEX_SECTOR_SIZE-3, &read);
+
+						if(read<(XEX_SECTOR_SIZE-3))
+							sector=0; //je to posledni sektor
+						else
+							sector++; //ukazatel na dalsi
+
+						atari_sector_buffer[XEX_SECTOR_SIZE-3]=((sector)>>8); //nejdriv HB !!!
+						atari_sector_buffer[XEX_SECTOR_SIZE-2]=((sector)&0xff); //pak DB!!! (je to HB,DB)
+						atari_sector_buffer[XEX_SECTOR_SIZE-1]=read;
+					}
+					debug(" sending\n");
+
+					sectorSize = XEX_SECTOR_SIZE;
+				}
+				else
+				{
+					location = offset;
+					if (sector>3)
+					{
+						sector-=4;
+						location += 128*3;
+						location += sector*atr_header.wSecSize;
+						sectorSize = atr_header.wSecSize;
+					}
+					else
+					{
+						location += 128*(sector-1);
+						sectorSize = 128;
+					}
+					plotnextnumber(location);
+					debug("\n");
+					pf_lseek(location);
+					pf_read(&atari_sector_buffer[0], sectorSize, &read);
+				}
+
+				//topofscreen();
+				//hexdump_pure(atari_sector_buffer,sectorSize);
+				//debug("Sending\n");
+				USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(sectorSize);
+				sent = 1;
+	
+				//pause_6502(1);
+				//hexdump_pure(0x10000+0x400,128);
+				unsigned char chksumreceive = get_checksum(0x10000+0x400, sectorSize);
+				debug(" receive:");
+				plotnextnumber(chksumreceive);
+				debug("\n");
+				//pause_6502(1);
+				//while(1);
+				}
+				
+				break;
+			}
+
+			//wait_us(100); // Wait for transmission to complete - Pokey bug, gets stuck active...
+	
+			if (sent)
+				USART_Wait_Transmit_Complete();
+			USART_Receive_Mode();
+		}
+		else
+		{
+			++badcommandcount;
+		}
+	}
+}
+	
+void mmcReadCached(u32 sector)
+{
+	//debug("mmcReadCached");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+	if(sector==n_actual_mmc_sector) return;
+	//debug("mmcReadREAL");
+	//plotnext(toatarichar(' '));
+	//plotnextnumber(sector);
+	//debug("\n");
+
+	u08 ret,retry;
+	//predtim nez nacte jiny, musi ulozit soucasny
+	// TODO mmcWriteCachedFlush();
+	//az ted nacte novy
+	retry=0; //zkusi to maximalne 256x
+	do
+	{
+		ret = mmcRead(sector);	//vraci 0 kdyz ok
+		retry--;
+	} while (ret && retry);
+	while(ret); //a pokud se vubec nepovedlo, tady zustane zablokovany cely SDrive!
+	n_actual_mmc_sector=sector;
+}
+
+unsigned char get_checksum(unsigned char* buffer, u16 len)
+{
+     6f0:	fb          	im -5
+     6f1:	3d          	pushspadd
+     6f2:	0d          	popsp
+     6f3:	77          	loadsp 28
+     6f4:	02          	pushsp
+     6f5:	84          	im 4
+     6f6:	05          	add
+     6f7:	a2          	im 34
+     6f8:	05          	add
+     6f9:	22          	loadh
+     6fa:	56          	storesp 24
+     6fb:	56          	storesp 24
+
+000006fc <.LM88>:
+	u16 i;
+	u08 sumo,sum;
+	sum=sumo=0;
+     6fc:	80          	im 0
+     6fd:	70          	loadsp 0
+
+000006fe <.LM89>:
+	for(i=0;i<len;i++)
+     6fe:	71          	loadsp 4
+     6ff:	55          	storesp 20
+     700:	55          	storesp 20
+     701:	52          	storesp 8
+     702:	71          	loadsp 4
+     703:	75          	loadsp 20
+     704:	27          	ulessthanorequal
+     705:	ac          	im 44
+     706:	38          	neqbranch
+
+00000707 <.L83>:
+	{
+		sum+=buffer[i];
+     707:	75          	loadsp 20
+     708:	13          	addsp 12
+     709:	70          	loadsp 0
+     70a:	33          	loadb
+     70b:	70          	loadsp 0
+     70c:	14          	addsp 16
+     70d:	70          	loadsp 0
+     70e:	81          	im 1
+     70f:	ff          	im -1
+     710:	06          	and
+     711:	55          	storesp 20
+     712:	51          	storesp 4
+     713:	51          	storesp 4
+     714:	51          	storesp 4
+
+00000715 <.LM91>:
+		if(sum<sumo) sum++;
+     715:	71          	loadsp 4
+     716:	74          	loadsp 16
+     717:	27          	ulessthanorequal
+     718:	89          	im 9
+     719:	38          	neqbranch
+     71a:	81          	im 1
+     71b:	12          	addsp 8
+     71c:	70          	loadsp 0
+     71d:	81          	im 1
+     71e:	ff          	im -1
+     71f:	06          	and
+     720:	53          	storesp 12
+     721:	51          	storesp 4
+
+00000722 <.L82>:
+		sumo = sum;
+     722:	71          	loadsp 4
+
+00000723 <.LM93>:
+     723:	81          	im 1
+     724:	14          	addsp 16
+     725:	70          	loadsp 0
+     726:	83          	im 3
+     727:	ff          	im -1
+     728:	ff          	im -1
+     729:	06          	and
+     72a:	55          	storesp 20
+     72b:	52          	storesp 8
+     72c:	54          	storesp 16
+     72d:	74          	loadsp 16
+     72e:	73          	loadsp 12
+     72f:	26          	ulessthan
+     730:	d6          	im -42
+     731:	38          	neqbranch
+
+00000732 <.L85>:
+	}
+	return sum;
+}
+     732:	71          	loadsp 4
+     733:	83          	im 3
+     734:	e0          	im -32
+     735:	80          	im 0
+     736:	0c          	store
+     737:	87          	im 7
+     738:	3d          	pushspadd
+     739:	0d          	popsp
+     73a:	04          	poppc
+
+0000073b <openfile>:
+     73b:	f8          	im -8
+     73c:	3d          	pushspadd
+     73d:	0d          	popsp
+     73e:	7a          	loadsp 40
+     73f:	57          	storesp 28
+
+00000740 <.LM96>:
+     740:	80          	im 0
+     741:	0b          	nop
+     742:	8a          	im 10
+     743:	3d          	pushspadd
+     744:	23          	storeh
+
+00000745 <.LM97>:
+     745:	80          	im 0
+
+00000746 <.LM98>:
+     746:	70          	loadsp 0
+
+00000747 <.LM99>:
+     747:	71          	loadsp 4
+     748:	83          	im 3
+     749:	e2          	im -30
+     74a:	e4          	im -28
+     74b:	0c          	store
+
+0000074c <.LM100>:
+     74c:	0b          	nop
+     74d:	0b          	nop
+     74e:	80          	im 0
+     74f:	f5          	im -11
+     750:	80          	im 0
+     751:	53          	storesp 12
+     752:	57          	storesp 28
+     753:	58          	storesp 32
+     754:	80          	im 0
+     755:	d9          	im -39
+     756:	96          	im 22
+     757:	3f          	callpcrel
+
+00000758 <.LM101>:
+     758:	76          	loadsp 24
+     759:	51          	storesp 4
+     75a:	80          	im 0
+     75b:	d9          	im -39
+     75c:	90          	im 16
+     75d:	3f          	callpcrel
+
+0000075e <.LM102>:
+     75e:	0b          	nop
+     75f:	0b          	nop
+     760:	80          	im 0
+     761:	f9          	im -7
+     762:	b8          	im 56
+     763:	51          	storesp 4
+     764:	80          	im 0
+     765:	d9          	im -39
+     766:	86          	im 6
+     767:	3f          	callpcrel
+
+00000768 <.LM103>:
+     768:	76          	loadsp 24
+     769:	51          	storesp 4
+     76a:	80          	im 0
+     76b:	c1          	im -63
+     76c:	c8          	im -56
+     76d:	3f          	callpcrel
+     76e:	83          	im 3
+     76f:	e0          	im -32
+     770:	80          	im 0
+     771:	08          	load
+     772:	78          	loadsp 32
+     773:	2e          	eq
+     774:	8f          	im 15
+     775:	38          	neqbranch
+
+00000776 <.LM104>:
+     776:	0b          	nop
+     777:	0b          	nop
+     778:	80          	im 0
+     779:	f5          	im -11
+     77a:	8c          	im 12
+     77b:	51          	storesp 4
+
+0000077c <.LM105>:
+     77c:	80          	im 0
+     77d:	d8          	im -40
+     77e:	ee          	im -18
+     77f:	3f          	callpcrel
+
+00000780 <.L87>:
+     780:	8a          	im 10
+     781:	3d          	pushspadd
+     782:	0d          	popsp
+     783:	04          	poppc
+
+00000784 <.L88>:
+     784:	0b          	nop
+     785:	0b          	nop
+     786:	80          	im 0
+     787:	f5          	im -11
+     788:	94          	im 20
+     789:	51          	storesp 4
+     78a:	80          	im 0
+     78b:	d8          	im -40
+     78c:	e0          	im -32
+     78d:	3f          	callpcrel
+
+0000078e <.L89>:
+     78e:	75          	loadsp 20
+     78f:	17          	addsp 28
+     790:	70          	loadsp 0
+     791:	33          	loadb
+     792:	55          	storesp 20
+     793:	55          	storesp 20
+     794:	73          	loadsp 12
+     795:	80          	im 0
+     796:	2e          	eq
+     797:	80          	im 0
+     798:	fd          	im -3
+     799:	38          	neqbranch
+
+0000079a <.LM109>:
+     79a:	73          	loadsp 12
+     79b:	ae          	im 46
+     79c:	2e          	eq
+     79d:	86          	im 6
+     79e:	38          	neqbranch
+
+0000079f <.LM110>:
+     79f:	81          	im 1
+     7a0:	16          	addsp 24
+     7a1:	56          	storesp 24
+     7a2:	eb          	im -21
+     7a3:	39          	poppcrel
+
+000007a4 <.L92>:
+     7a4:	80          	im 0
+     7a5:	0b          	nop
+     7a6:	81          	im 1
+     7a7:	16          	addsp 24
+     7a8:	33          	loadb
+     7a9:	55          	storesp 20
+     7aa:	56          	storesp 24
+     7ab:	73          	loadsp 12
+     7ac:	80          	im 0
+     7ad:	d8          	im -40
+     7ae:	2e          	eq
+     7af:	09          	not
+     7b0:	81          	im 1
+     7b1:	06          	and
+     7b2:	83          	im 3
+     7b3:	38          	neqbranch
+     7b4:	81          	im 1
+     7b5:	56          	storesp 24
+
+000007b6 <.L94>:
+     7b6:	73          	loadsp 12
+     7b7:	80          	im 0
+     7b8:	f8          	im -8
+     7b9:	32          	xor
+     7ba:	70          	loadsp 0
+     7bb:	30          	neg
+     7bc:	70          	loadsp 0
+     7bd:	80          	im 0
+     7be:	25          	lessthanorequal
+     7bf:	78          	loadsp 32
+     7c0:	07          	or
+     7c1:	51          	storesp 4
+     7c2:	51          	storesp 4
+     7c3:	54          	storesp 16
+     7c4:	73          	loadsp 12
+     7c5:	80          	im 0
+     7c6:	2e          	eq
+     7c7:	80          	im 0
+     7c8:	cd          	im -51
+     7c9:	38          	neqbranch
+
+000007ca <.LM112>:
+     7ca:	80          	im 0
+     7cb:	0b          	nop
+     7cc:	82          	im 2
+     7cd:	16          	addsp 24
+     7ce:	33          	loadb
+     7cf:	55          	storesp 20
+     7d0:	56          	storesp 24
+     7d1:	73          	loadsp 12
+     7d2:	80          	im 0
+     7d3:	c6          	im -58
+     7d4:	2e          	eq
+     7d5:	09          	not
+     7d6:	81          	im 1
+     7d7:	06          	and
+     7d8:	83          	im 3
+     7d9:	38          	neqbranch
+     7da:	81          	im 1
+     7db:	56          	storesp 24
+
+000007dc <.L97>:
+     7dc:	73          	loadsp 12
+     7dd:	80          	im 0
+     7de:	e6          	im -26
+     7df:	32          	xor
+     7e0:	70          	loadsp 0
+     7e1:	30          	neg
+     7e2:	70          	loadsp 0
+     7e3:	80          	im 0
+     7e4:	25          	lessthanorequal
+     7e5:	78          	loadsp 32
+     7e6:	07          	or
+     7e7:	51          	storesp 4
+     7e8:	51          	storesp 4
+     7e9:	54          	storesp 16
+     7ea:	73          	loadsp 12
+     7eb:	80          	im 0
+     7ec:	2e          	eq
+     7ed:	a8          	im 40
+     7ee:	38          	neqbranch
+
+000007ef <.LM113>:
+     7ef:	80          	im 0
+     7f0:	0b          	nop
+     7f1:	83          	im 3
+     7f2:	16          	addsp 24
+     7f3:	33          	loadb
+     7f4:	55          	storesp 20
+     7f5:	56          	storesp 24
+     7f6:	73          	loadsp 12
+     7f7:	80          	im 0
+     7f8:	c4          	im -60
+     7f9:	2e          	eq
+     7fa:	09          	not
+     7fb:	81          	im 1
+     7fc:	06          	and
+     7fd:	83          	im 3
+     7fe:	38          	neqbranch
+     7ff:	81          	im 1
+     800:	56          	storesp 24
+
+00000801 <.L100>:
+     801:	73          	loadsp 12
+     802:	80          	im 0
+     803:	e4          	im -28
+     804:	32          	xor
+     805:	70          	loadsp 0
+     806:	30          	neg
+     807:	70          	loadsp 0
+     808:	80          	im 0
+     809:	25          	lessthanorequal
+     80a:	78          	loadsp 32
+     80b:	07          	or
+     80c:	51          	storesp 4
+     80d:	51          	storesp 4
+     80e:	54          	storesp 16
+     80f:	73          	loadsp 12
+     810:	80          	im 0
+     811:	2e          	eq
+     812:	83          	im 3
+     813:	38          	neqbranch
+
+00000814 <.LM114>:
+     814:	81          	im 1
+     815:	58          	storesp 32
+
+00000816 <.L90>:
+     816:	80          	im 0
+     817:	0b          	nop
+     818:	8a          	im 10
+     819:	3d          	pushspadd
+     81a:	23          	storeh
+
+0000081b <.LM116>:
+     81b:	8a          	im 10
+     81c:	3d          	pushspadd
+     81d:	fc          	im -4
+     81e:	05          	add
+     81f:	53          	storesp 12
+     820:	90          	im 16
+     821:	52          	storesp 8
+     822:	83          	im 3
+     823:	e2          	im -30
+     824:	e8          	im -24
+     825:	51          	storesp 4
+     826:	80          	im 0
+     827:	c1          	im -63
+     828:	cc          	im -52
+     829:	3f          	callpcrel
+
+0000082a <.LM117>:
+     82a:	89          	im 9
+     82b:	3d          	pushspadd
+     82c:	22          	loadh
+     82d:	55          	storesp 20
+     82e:	74          	loadsp 16
+     82f:	90          	im 16
+     830:	2e          	eq
+     831:	8e          	im 14
+     832:	38          	neqbranch
+
+00000833 <.LM118>:
+     833:	0b          	nop
+     834:	0b          	nop
+     835:	80          	im 0
+     836:	f5          	im -11
+     837:	98          	im 24
+     838:	51          	storesp 4
+
+00000839 <.LM119>:
+     839:	80          	im 0
+     83a:	d7          	im -41
+     83b:	b1          	im 49
+     83c:	3f          	callpcrel
+     83d:	fe          	im -2
+     83e:	c1          	im -63
+     83f:	39          	poppcrel
+
+00000840 <.L102>:
+     840:	83          	im 3
+     841:	e2          	im -30
+     842:	e8          	im -24
+     843:	51          	storesp 4
+     844:	fd          	im -3
+     845:	95          	im 21
+     846:	3f          	callpcrel
+
+00000847 <.LM121>:
+     847:	83          	im 3
+     848:	e2          	im -30
+     849:	ea          	im -22
+     84a:	51          	storesp 4
+     84b:	fd          	im -3
+     84c:	8e          	im 14
+     84d:	3f          	callpcrel
+
+0000084e <.LM122>:
+     84e:	83          	im 3
+     84f:	e2          	im -30
+     850:	ec          	im -20
+     851:	51          	storesp 4
+     852:	fd          	im -3
+     853:	87          	im 7
+     854:	3f          	callpcrel
+
+00000855 <.LM123>:
+     855:	80          	im 0
+     856:	0b          	nop
+     857:	83          	im 3
+     858:	e3          	im -29
+     859:	88          	im 8
+     85a:	0c          	store
+
+0000085b <.LM124>:
+     85b:	77          	loadsp 28
+     85c:	81          	im 1
+     85d:	2e          	eq
+     85e:	81          	im 1
+     85f:	8c          	im 12
+     860:	38          	neqbranch
+
+00000861 <.LM125>:
+     861:	83          	im 3
+     862:	e2          	im -30
+     863:	e8          	im -24
+     864:	33          	loadb
+     865:	83          	im 3
+     866:	e2          	im -30
+     867:	e9          	im -23
+     868:	33          	loadb
+     869:	71          	loadsp 4
+     86a:	88          	im 8
+     86b:	2b          	ashiftleft
+     86c:	07          	or
+     86d:	55          	storesp 20
+     86e:	56          	storesp 24
+     86f:	73          	loadsp 12
+     870:	83          	im 3
+     871:	ff          	im -1
+     872:	ff          	im -1
+     873:	2e          	eq
+     874:	82          	im 2
+     875:	ce          	im -50
+     876:	38          	neqbranch
+
+00000877 <.LM126>:
+     877:	73          	loadsp 12
+     878:	85          	im 5
+     879:	96          	im 22
+     87a:	2e          	eq
+     87b:	8e          	im 14
+     87c:	38          	neqbranch
+
+0000087d <.LM127>:
+     87d:	0b          	nop
+     87e:	0b          	nop
+     87f:	80          	im 0
+     880:	f5          	im -11
+     881:	b0          	im 48
+     882:	51          	storesp 4
+
+00000883 <.LM128>:
+     883:	80          	im 0
+     884:	d6          	im -42
+     885:	e7          	im -25
+     886:	3f          	callpcrel
+     887:	fd          	im -3
+     888:	f7          	im -9
+     889:	39          	poppcrel
+
+0000088a <.L131>:
+     88a:	0b          	nop
+     88b:	0b          	nop
+     88c:	80          	im 0
+     88d:	f5          	im -11
+     88e:	c4          	im -60
+     88f:	51          	storesp 4
+     890:	80          	im 0
+     891:	d6          	im -42
+     892:	da          	im -38
+     893:	3f          	callpcrel
+
+00000894 <.LM130>:
+     894:	74          	loadsp 16
+     895:	83          	im 3
+     896:	e3          	im -29
+     897:	90          	im 16
+     898:	0c          	store
+
+00000899 <.L105>:
+     899:	83          	im 3
+     89a:	e2          	im -30
+     89b:	ec          	im -20
+     89c:	33          	loadb
+     89d:	83          	im 3
+     89e:	e2          	im -30
+     89f:	ed          	im -19
+     8a0:	33          	loadb
+     8a1:	71          	loadsp 4
+     8a2:	88          	im 8
+     8a3:	2b          	ashiftleft
+     8a4:	07          	or
+     8a5:	55          	storesp 20
+     8a6:	55          	storesp 20
+     8a7:	73          	loadsp 12
+     8a8:	81          	im 1
+     8a9:	80          	im 0
+     8aa:	2e          	eq
+     8ab:	81          	im 1
+     8ac:	d3          	im -45
+     8ad:	38          	neqbranch
+
+000008ae <.LM132>:
+     8ae:	73          	loadsp 12
+     8af:	82          	im 2
+     8b0:	80          	im 0
+     8b1:	2e          	eq
+     8b2:	84          	im 4
+     8b3:	81          	im 1
+     8b4:	38          	neqbranch
+
+000008b5 <.LM133>:
+     8b5:	73          	loadsp 12
+     8b6:	81          	im 1
+     8b7:	ff          	im -1
+     8b8:	26          	ulessthan
+     8b9:	81          	im 1
+     8ba:	b8          	im 56
+     8bb:	38          	neqbranch
+
+000008bc <.LM134>:
+     8bc:	0b          	nop
+     8bd:	0b          	nop
+     8be:	80          	im 0
+     8bf:	f5          	im -11
+     8c0:	cc          	im -52
+     8c1:	51          	storesp 4
+     8c2:	80          	im 0
+     8c3:	d6          	im -42
+     8c4:	a8          	im 40
+     8c5:	3f          	callpcrel
+
+000008c6 <.LM135>:
+     8c6:	83          	im 3
+     8c7:	e2          	im -30
+     8c8:	ea          	im -22
+     8c9:	33          	loadb
+     8ca:	83          	im 3
+     8cb:	e2          	im -30
+     8cc:	eb          	im -21
+     8cd:	33          	loadb
+     8ce:	71          	loadsp 4
+     8cf:	88          	im 8
+     8d0:	2b          	ashiftleft
+     8d1:	07          	or
+     8d2:	52          	storesp 8
+     8d3:	56          	storesp 24
+     8d4:	80          	im 0
+     8d5:	d7          	im -41
+     8d6:	a5          	im 37
+     8d7:	3f          	callpcrel
+
+000008d8 <.LM136>:
+     8d8:	0b          	nop
+     8d9:	0b          	nop
+     8da:	80          	im 0
+     8db:	f5          	im -11
+     8dc:	d0          	im -48
+     8dd:	51          	storesp 4
+     8de:	80          	im 0
+     8df:	d6          	im -42
+     8e0:	8c          	im 12
+     8e1:	3f          	callpcrel
+
+000008e2 <.LM137>:
+     8e2:	81          	im 1
+     8e3:	0b          	nop
+     8e4:	83          	im 3
+     8e5:	e2          	im -30
+     8e6:	e4          	im -28
+     8e7:	0c          	store
+
+000008e8 <.L135>:
+     8e8:	8a          	im 10
+     8e9:	3d          	pushspadd
+     8ea:	0d          	popsp
+     8eb:	04          	poppc
+
+000008ec <.L129>:
+     8ec:	0b          	nop
+     8ed:	0b          	nop
+     8ee:	80          	im 0
+     8ef:	f5          	im -11
+     8f0:	d4          	im -44
+     8f1:	51          	storesp 4
+     8f2:	80          	im 0
+     8f3:	d5          	im -43
+     8f4:	f8          	im -8
+     8f5:	3f          	callpcrel
+
+000008f6 <.LM140>:
+     8f6:	80          	im 0
+     8f7:	0b          	nop
+     8f8:	83          	im 3
+     8f9:	e3          	im -29
+     8fa:	90          	im 16
+     8fb:	0c          	store
+
+000008fc <.LM141>:
+     8fc:	82          	im 2
+     8fd:	0b          	nop
+     8fe:	83          	im 3
+     8ff:	e2          	im -30
+     900:	e8          	im -24
+     901:	34          	storeb
+     902:	ff          	im -1
+     903:	96          	im 22
+     904:	0b          	nop
+     905:	83          	im 3
+     906:	e2          	im -30
+     907:	e9          	im -23
+     908:	34          	storeb
+
+00000909 <.LM142>:
+     909:	76          	loadsp 24
+     90a:	51          	storesp 4
+     90b:	f7          	im -9
+     90c:	d2          	im -46
+     90d:	3f          	callpcrel
+     90e:	83          	im 3
+     90f:	e0          	im -32
+     910:	80          	im 0
+     911:	08          	load
+     912:	54          	storesp 16
+     913:	80          	im 0
+     914:	0b          	nop
+     915:	83          	im 3
+     916:	e0          	im -32
+     917:	80          	im 0
+     918:	08          	load
+     919:	24          	lessthan
+     91a:	a9          	im 41
+     91b:	38          	neqbranch
+     91c:	73          	loadsp 12
+     91d:	84          	im 4
+     91e:	2c          	ashiftright
+     91f:	70          	loadsp 0
+     920:	83          	im 3
+     921:	ff          	im -1
+     922:	ff          	im -1
+     923:	06          	and
+     924:	70          	loadsp 0
+     925:	88          	im 8
+     926:	2a          	lshiftright
+     927:	57          	storesp 28
+     928:	51          	storesp 4
+     929:	54          	storesp 16
+     92a:	74          	loadsp 16
+     92b:	83          	im 3
+     92c:	e2          	im -30
+     92d:	ea          	im -22
+     92e:	34          	storeb
+     92f:	73          	loadsp 12
+     930:	83          	im 3
+     931:	e2          	im -30
+     932:	eb          	im -21
+     933:	34          	storeb
+
+00000934 <.LM143>:
+     934:	80          	im 0
+     935:	0b          	nop
+     936:	83          	im 3
+     937:	e2          	im -30
+     938:	ec          	im -20
+     939:	34          	storeb
+     93a:	ff          	im -1
+     93b:	80          	im 0
+     93c:	0b          	nop
+     93d:	83          	im 3
+     93e:	e2          	im -30
+     93f:	ed          	im -19
+     940:	34          	storeb
+     941:	fe          	im -2
+     942:	d6          	im -42
+     943:	39          	poppcrel
+
+00000944 <.L134>:
+     944:	83          	im 3
+     945:	e0          	im -32
+     946:	80          	im 0
+     947:	08          	load
+     948:	8f          	im 15
+     949:	05          	add
+     94a:	70          	loadsp 0
+     94b:	84          	im 4
+     94c:	2c          	ashiftright
+     94d:	70          	loadsp 0
+     94e:	83          	im 3
+     94f:	ff          	im -1
+     950:	ff          	im -1
+     951:	06          	and
+     952:	70          	loadsp 0
+     953:	88          	im 8
+     954:	2a          	lshiftright
+     955:	58          	storesp 32
+     956:	51          	storesp 4
+     957:	51          	storesp 4
+     958:	54          	storesp 16
+     959:	74          	loadsp 16
+     95a:	83          	im 3
+     95b:	e2          	im -30
+     95c:	ea          	im -22
+     95d:	34          	storeb
+     95e:	73          	loadsp 12
+     95f:	83          	im 3
+     960:	e2          	im -30
+     961:	eb          	im -21
+     962:	34          	storeb
+
+00000963 <.LM145>:
+     963:	80          	im 0
+     964:	0b          	nop
+     965:	83          	im 3
+     966:	e2          	im -30
+     967:	ec          	im -20
+     968:	34          	storeb
+     969:	ff          	im -1
+     96a:	80          	im 0
+     96b:	0b          	nop
+     96c:	83          	im 3
+     96d:	e2          	im -30
+     96e:	ed          	im -19
+     96f:	34          	storeb
+     970:	fe          	im -2
+     971:	a7          	im 39
+     972:	39          	poppcrel
+
+00000973 <.L121>:
+     973:	0b          	nop
+     974:	0b          	nop
+     975:	80          	im 0
+     976:	f5          	im -11
+     977:	dc          	im -36
+     978:	51          	storesp 4
+     979:	80          	im 0
+     97a:	d4          	im -44
+     97b:	f1          	im -15
+     97c:	3f          	callpcrel
+     97d:	fc          	im -4
+     97e:	81          	im 1
+     97f:	39          	poppcrel
+
+00000980 <.L132>:
+     980:	83          	im 3
+     981:	e2          	im -30
+     982:	ea          	im -22
+     983:	33          	loadb
+     984:	83          	im 3
+     985:	e2          	im -30
+     986:	eb          	im -21
+     987:	33          	loadb
+     988:	71          	loadsp 4
+     989:	88          	im 8
+     98a:	2b          	ashiftleft
+     98b:	07          	or
+     98c:	55          	storesp 20
+     98d:	58          	storesp 32
+     98e:	ad          	im 45
+     98f:	80          	im 0
+     990:	74          	loadsp 16
+     991:	27          	ulessthanorequal
+     992:	81          	im 1
+     993:	f2          	im -14
+     994:	38          	neqbranch
+
+00000995 <.LM148>:
+     995:	0b          	nop
+     996:	0b          	nop
+     997:	80          	im 0
+     998:	f5          	im -11
+     999:	ec          	im -20
+     99a:	51          	storesp 4
+
+0000099b <.LM149>:
+     99b:	80          	im 0
+     99c:	d4          	im -44
+     99d:	cf          	im -49
+     99e:	3f          	callpcrel
+
+0000099f <.LM150>:
+     99f:	83          	im 3
+     9a0:	e2          	im -30
+     9a1:	ea          	im -22
+     9a2:	33          	loadb
+     9a3:	83          	im 3
+     9a4:	e2          	im -30
+     9a5:	eb          	im -21
+     9a6:	33          	loadb
+     9a7:	71          	loadsp 4
+     9a8:	88          	im 8
+     9a9:	2b          	ashiftleft
+     9aa:	07          	or
+     9ab:	52          	storesp 8
+     9ac:	56          	storesp 24
+     9ad:	80          	im 0
+     9ae:	d5          	im -43
+     9af:	cc          	im -52
+     9b0:	3f          	callpcrel
+
+000009b1 <.LM151>:
+     9b1:	0b          	nop
+     9b2:	0b          	nop
+     9b3:	80          	im 0
+     9b4:	f5          	im -11
+     9b5:	d0          	im -48
+     9b6:	51          	storesp 4
+     9b7:	80          	im 0
+     9b8:	d4          	im -44
+     9b9:	b3          	im 51
+     9ba:	3f          	callpcrel
+
+000009bb <.LM152>:
+     9bb:	81          	im 1
+     9bc:	0b          	nop
+     9bd:	83          	im 3
+     9be:	e2          	im -30
+     9bf:	e4          	im -28
+     9c0:	0c          	store
+     9c1:	fe          	im -2
+     9c2:	a5          	im 37
+     9c3:	39          	poppcrel
+
+000009c4 <.L130>:
+     9c4:	0b          	nop
+     9c5:	0b          	nop
+     9c6:	80          	im 0
+     9c7:	f5          	im -11
+     9c8:	f0          	im -16
+     9c9:	51          	storesp 4
+     9ca:	80          	im 0
+     9cb:	d4          	im -44
+     9cc:	a0          	im 32
+     9cd:	3f          	callpcrel
+
+000009ce <.LM154>:
+     9ce:	fe          	im -2
+     9cf:	80          	im 0
+     9d0:	0b          	nop
+     9d1:	83          	im 3
+     9d2:	e3          	im -29
+     9d3:	90          	im 16
+     9d4:	0c          	store
+
+000009d5 <.LM155>:
+     9d5:	81          	im 1
+     9d6:	0b          	nop
+     9d7:	83          	im 3
+     9d8:	e3          	im -29
+     9d9:	88          	im 8
+     9da:	0c          	store
+
+000009db <.LM156>:
+     9db:	ff          	im -1
+     9dc:	0b          	nop
+     9dd:	83          	im 3
+     9de:	e2          	im -30
+     9df:	e8          	im -24
+     9e0:	34          	storeb
+     9e1:	ff          	im -1
+     9e2:	0b          	nop
+     9e3:	83          	im 3
+     9e4:	e2          	im -30
+     9e5:	e9          	im -23
+     9e6:	34          	storeb
+
+000009e7 <.LM157>:
+     9e7:	76          	loadsp 24
+     9e8:	51          	storesp 4
+     9e9:	f5          	im -11
+     9ea:	f4          	im -12
+     9eb:	3f          	callpcrel
+     9ec:	83          	im 3
+     9ed:	e0          	im -32
+     9ee:	80          	im 0
+     9ef:	08          	load
+     9f0:	83          	im 3
+     9f1:	e3          	im -29
+     9f2:	94          	im 20
+     9f3:	0c          	store
+
+000009f4 <.LM158>:
+     9f4:	83          	im 3
+     9f5:	e0          	im -32
+     9f6:	80          	im 0
+     9f7:	08          	load
+     9f8:	54          	storesp 16
+     9f9:	80          	im 0
+     9fa:	0b          	nop
+     9fb:	83          	im 3
+     9fc:	e0          	im -32
+     9fd:	80          	im 0
+     9fe:	08          	load
+     9ff:	24          	lessthan
+     a00:	80          	im 0
+     a01:	d3          	im -45
+     a02:	38          	neqbranch
+     a03:	73          	loadsp 12
+     a04:	84          	im 4
+     a05:	2c          	ashiftright
+     a06:	70          	loadsp 0
+     a07:	83          	im 3
+     a08:	ff          	im -1
+     a09:	ff          	im -1
+     a0a:	06          	and
+     a0b:	70          	loadsp 0
+     a0c:	88          	im 8
+     a0d:	2a          	lshiftright
+     a0e:	57          	storesp 28
+     a0f:	51          	storesp 4
+     a10:	54          	storesp 16
+     a11:	74          	loadsp 16
+     a12:	83          	im 3
+     a13:	e2          	im -30
+     a14:	ea          	im -22
+     a15:	34          	storeb
+     a16:	73          	loadsp 12
+     a17:	83          	im 3
+     a18:	e2          	im -30
+     a19:	eb          	im -21
+     a1a:	34          	storeb
+
+00000a1b <.LM159>:
+     a1b:	80          	im 0
+     a1c:	0b          	nop
+     a1d:	83          	im 3
+     a1e:	e2          	im -30
+     a1f:	ec          	im -20
+     a20:	34          	storeb
+     a21:	ff          	im -1
+     a22:	80          	im 0
+     a23:	0b          	nop
+     a24:	83          	im 3
+     a25:	e2          	im -30
+     a26:	ed          	im -19
+     a27:	34          	storeb
+
+00000a28 <.LM160>:
+     a28:	80          	im 0
+     a29:	55          	storesp 20
+
+00000a2a <.L111>:
+     a2a:	74          	loadsp 16
+     a2b:	17          	addsp 28
+     a2c:	54          	storesp 16
+     a2d:	73          	loadsp 12
+     a2e:	33          	loadb
+     a2f:	83          	im 3
+     a30:	e2          	im -30
+     a31:	d8          	im -40
+     a32:	16          	addsp 24
+     a33:	34          	storeb
+
+00000a34 <.LM162>:
+     a34:	81          	im 1
+     a35:	15          	addsp 20
+     a36:	55          	storesp 20
+     a37:	74          	loadsp 16
+     a38:	8c          	im 12
+     a39:	2e          	eq
+     a3a:	fc          	im -4
+     a3b:	dd          	im -35
+     a3c:	38          	neqbranch
+
+00000a3d <.LM163>:
+     a3d:	74          	loadsp 16
+     a3e:	17          	addsp 28
+     a3f:	54          	storesp 16
+     a40:	73          	loadsp 12
+     a41:	33          	loadb
+     a42:	83          	im 3
+     a43:	e2          	im -30
+     a44:	d8          	im -40
+     a45:	16          	addsp 24
+     a46:	34          	storeb
+
+00000a47 <.LM164>:
+     a47:	81          	im 1
+     a48:	15          	addsp 20
+     a49:	55          	storesp 20
+     a4a:	74          	loadsp 16
+     a4b:	8c          	im 12
+     a4c:	2e          	eq
+     a4d:	09          	not
+     a4e:	81          	im 1
+     a4f:	06          	and
+     a50:	d9          	im -39
+     a51:	38          	neqbranch
+     a52:	fc          	im -4
+     a53:	c5          	im -59
+     a54:	39          	poppcrel
+
+00000a55 <.L136>:
+     a55:	83          	im 3
+     a56:	e0          	im -32
+     a57:	80          	im 0
+     a58:	08          	load
+     a59:	8f          	im 15
+     a5a:	05          	add
+     a5b:	70          	loadsp 0
+     a5c:	84          	im 4
+     a5d:	2c          	ashiftright
+     a5e:	70          	loadsp 0
+     a5f:	83          	im 3
+     a60:	ff          	im -1
+     a61:	ff          	im -1
+     a62:	06          	and
+     a63:	70          	loadsp 0
+     a64:	88          	im 8
+     a65:	2a          	lshiftright
+     a66:	58          	storesp 32
+     a67:	51          	storesp 4
+     a68:	51          	storesp 4
+     a69:	54          	storesp 16
+     a6a:	74          	loadsp 16
+     a6b:	83          	im 3
+     a6c:	e2          	im -30
+     a6d:	ea          	im -22
+     a6e:	34          	storeb
+     a6f:	73          	loadsp 12
+     a70:	83          	im 3
+     a71:	e2          	im -30
+     a72:	eb          	im -21
+     a73:	34          	storeb
+
+00000a74 <.LM166>:
+     a74:	80          	im 0
+     a75:	0b          	nop
+     a76:	83          	im 3
+     a77:	e2          	im -30
+     a78:	ec          	im -20
+     a79:	34          	storeb
+     a7a:	ff          	im -1
+     a7b:	80          	im 0
+     a7c:	0b          	nop
+     a7d:	83          	im 3
+     a7e:	e2          	im -30
+     a7f:	ed          	im -19
+     a80:	34          	storeb
+
+00000a81 <.LM167>:
+     a81:	80          	im 0
+     a82:	55          	storesp 20
+     a83:	ff          	im -1
+     a84:	a5          	im 37
+     a85:	39          	poppcrel
+
+00000a86 <.L116>:
+     a86:	0b          	nop
+     a87:	0b          	nop
+     a88:	80          	im 0
+     a89:	f5          	im -11
+     a8a:	f8          	im -8
+     a8b:	51          	storesp 4
+
+00000a8c <.LM169>:
+     a8c:	80          	im 0
+     a8d:	d2          	im -46
+     a8e:	de          	im -34
+     a8f:	3f          	callpcrel
+
+00000a90 <.LM170>:
+     a90:	83          	im 3
+     a91:	e2          	im -30
+     a92:	ea          	im -22
+     a93:	33          	loadb
+     a94:	83          	im 3
+     a95:	e2          	im -30
+     a96:	eb          	im -21
+     a97:	33          	loadb
+     a98:	71          	loadsp 4
+     a99:	88          	im 8
+     a9a:	2b          	ashiftleft
+     a9b:	07          	or
+     a9c:	52          	storesp 8
+     a9d:	56          	storesp 24
+     a9e:	80          	im 0
+     a9f:	d3          	im -45
+     aa0:	db          	im -37
+     aa1:	3f          	callpcrel
+
+00000aa2 <.LM171>:
+     aa2:	0b          	nop
+     aa3:	0b          	nop
+     aa4:	80          	im 0
+     aa5:	f5          	im -11
+     aa6:	d0          	im -48
+     aa7:	51          	storesp 4
+     aa8:	80          	im 0
+     aa9:	d2          	im -46
+     aaa:	c2          	im -62
+     aab:	3f          	callpcrel
+
+00000aac <.LM172>:
+     aac:	81          	im 1
+     aad:	0b          	nop
+     aae:	83          	im 3
+     aaf:	e2          	im -30
+     ab0:	e4          	im -28
+     ab1:	0c          	store
+     ab2:	fc          	im -4
+     ab3:	b4          	im 52
+     ab4:	39          	poppcrel
+
+00000ab5 <.L133>:
+     ab5:	0b          	nop
+     ab6:	0b          	nop
+     ab7:	80          	im 0
+     ab8:	f5          	im -11
+     ab9:	fc          	im -4
+     aba:	51          	storesp 4
+
+00000abb <.LM174>:
+     abb:	80          	im 0
+     abc:	d2          	im -46
+     abd:	af          	im 47
+     abe:	3f          	callpcrel
+
+00000abf <.LM175>:
+     abf:	83          	im 3
+     ac0:	e2          	im -30
+     ac1:	ea          	im -22
+     ac2:	33          	loadb
+     ac3:	83          	im 3
+     ac4:	e2          	im -30
+     ac5:	eb          	im -21
+     ac6:	33          	loadb
+     ac7:	71          	loadsp 4
+     ac8:	88          	im 8
+     ac9:	2b          	ashiftleft
+     aca:	07          	or
+     acb:	52          	storesp 8
+     acc:	56          	storesp 24
+     acd:	80          	im 0
+     ace:	d3          	im -45
+     acf:	ac          	im 44
+     ad0:	3f          	callpcrel
+
+00000ad1 <.LM176>:
+     ad1:	0b          	nop
+     ad2:	0b          	nop
+     ad3:	80          	im 0
+     ad4:	f5          	im -11
+     ad5:	d0          	im -48
+     ad6:	51          	storesp 4
+     ad7:	80          	im 0
+     ad8:	d2          	im -46
+     ad9:	93          	im 19
+     ada:	3f          	callpcrel
+
+00000adb <.LM177>:
+     adb:	81          	im 1
+     adc:	0b          	nop
+     add:	83          	im 3
+     ade:	e2          	im -30
+     adf:	e4          	im -28
+     ae0:	0c          	store
+     ae1:	fc          	im -4
+     ae2:	85          	im 5
+     ae3:	39          	poppcrel
+
+00000ae4 <selectfile>:
+     ae4:	f7          	im -9
+     ae5:	3d          	pushspadd
+     ae6:	0d          	popsp
+     ae7:	7b          	loadsp 44
+     ae8:	5a          	storesp 40
+
+00000ae9 <.LM179>:
+     ae9:	8c          	im 12
+     aea:	9a          	im 26
+     aeb:	c0          	im -64
+     aec:	51          	storesp 4
+     aed:	f3          	im -13
+     aee:	c4          	im -60
+     aef:	3f          	callpcrel
+
+00000af0 <.LM180>:
+     af0:	80          	im 0
+     af1:	57          	storesp 28
+
+00000af2 <.LM181>:
+     af2:	80          	im 0
+     af3:	cf          	im -49
+     af4:	cf          	im -49
+     af5:	3f          	callpcrel
+
+00000af6 <.LM182>:
+     af6:	76          	loadsp 24
+     af7:	54          	storesp 16
+
+00000af8 <.L143>:
+     af8:	80          	im 0
+     af9:	0b          	nop
+     afa:	86          	im 6
+     afb:	b8          	im 56
+     afc:	c0          	im -64
+     afd:	15          	addsp 20
+     afe:	34          	storeb
+
+00000aff <.LM184>:
+     aff:	81          	im 1
+     b00:	14          	addsp 16
+     b01:	54          	storesp 16
+     b02:	73          	loadsp 12
+     b03:	87          	im 7
+     b04:	c0          	im -64
+     b05:	2e          	eq
+     b06:	09          	not
+     b07:	81          	im 1
+     b08:	06          	and
+     b09:	ee          	im -18
+     b0a:	38          	neqbranch
+
+00000b0b <.LM185>:
+     b0b:	0b          	nop
+     b0c:	0b          	nop
+     b0d:	80          	im 0
+     b0e:	f4          	im -12
+     b0f:	fc          	im -4
+     b10:	52          	storesp 8
+     b11:	83          	im 3
+     b12:	e2          	im -30
+     b13:	f4          	im -12
+     b14:	51          	storesp 4
+     b15:	80          	im 0
+     b16:	c0          	im -64
+     b17:	81          	im 1
+     b18:	3f          	callpcrel
+     b19:	83          	im 3
+     b1a:	e0          	im -32
+     b1b:	80          	im 0
+     b1c:	08          	load
+     b1d:	83          	im 3
+     b1e:	db          	im -37
+     b1f:	38          	neqbranch
+
+00000b20 <.LM186>:
+     b20:	80          	im 0
+
+00000b21 <.LM187>:
+     b21:	70          	loadsp 0
+
+00000b22 <.LM188>:
+     b22:	83          	im 3
+     b23:	e3          	im -29
+     b24:	a8          	im 40
+     b25:	08          	load
+     b26:	55          	storesp 20
+     b27:	59          	storesp 36
+     b28:	59          	storesp 36
+     b29:	94          	im 20
+     b2a:	73          	loadsp 12
+     b2b:	25          	lessthanorequal
+     b2c:	86          	im 6
+     b2d:	38          	neqbranch
+
+00000b2e <.LM189>:
+     b2e:	ec          	im -20
+     b2f:	13          	addsp 12
+     b30:	fe          	im -2
+     b31:	06          	and
+     b32:	58          	storesp 32
+
+00000b33 <.L147>:
+     b33:	80          	im 0
+     b34:	73          	loadsp 12
+     b35:	24          	lessthan
+     b36:	82          	im 2
+     b37:	ff          	im -1
+     b38:	38          	neqbranch
+
+00000b39 <.L192>:
+     b39:	83          	im 3
+     b3a:	e0          	im -32
+     b3b:	94          	im 20
+     b3c:	52          	storesp 8
+     b3d:	83          	im 3
+     b3e:	e2          	im -30
+     b3f:	f4          	im -12
+     b40:	51          	storesp 4
+     b41:	80          	im 0
+     b42:	c0          	im -64
+     b43:	e8          	im -24
+     b44:	3f          	callpcrel
+     b45:	83          	im 3
+     b46:	e0          	im -32
+     b47:	80          	im 0
+     b48:	08          	load
+     b49:	80          	im 0
+     b4a:	db          	im -37
+     b4b:	38          	neqbranch
+
+00000b4c <.L199>:
+     b4c:	83          	im 3
+     b4d:	e0          	im -32
+     b4e:	9d          	im 29
+     b4f:	33          	loadb
+     b50:	53          	storesp 12
+     b51:	72          	loadsp 8
+     b52:	80          	im 0
+     b53:	2e          	eq
+     b54:	80          	im 0
+     b55:	d0          	im -48
+     b56:	38          	neqbranch
+
+00000b57 <.LM192>:
+     b57:	83          	im 3
+     b58:	e0          	im -32
+     b59:	9c          	im 28
+     b5a:	33          	loadb
+     b5b:	70          	loadsp 0
+     b5c:	82          	im 2
+     b5d:	2a          	lshiftright
+     b5e:	70          	loadsp 0
+     b5f:	81          	im 1
+     b60:	06          	and
+     b61:	51          	storesp 4
+     b62:	54          	storesp 16
+     b63:	54          	storesp 16
+     b64:	72          	loadsp 8
+     b65:	d3          	im -45
+     b66:	38          	neqbranch
+
+00000b67 <.LM193>:
+     b67:	73          	loadsp 12
+     b68:	81          	im 1
+     b69:	2a          	lshiftright
+     b6a:	81          	im 1
+     b6b:	06          	and
+     b6c:	55          	storesp 20
+     b6d:	74          	loadsp 16
+     b6e:	ca          	im -54
+     b6f:	38          	neqbranch
+
+00000b70 <.LM194>:
+     b70:	73          	loadsp 12
+     b71:	84          	im 4
+     b72:	2a          	lshiftright
+     b73:	70          	loadsp 0
+     b74:	81          	im 1
+     b75:	06          	and
+     b76:	51          	storesp 4
+     b77:	53          	storesp 12
+     b78:	72          	loadsp 8
+     b79:	82          	im 2
+     b7a:	a3          	im 35
+     b7b:	38          	neqbranch
+
+00000b7c <.LM195>:
+     b7c:	83          	im 3
+     b7d:	e3          	im -29
+     b7e:	a8          	im 40
+     b7f:	08          	load
+     b80:	77          	loadsp 28
+     b81:	2e          	eq
+     b82:	81          	im 1
+     b83:	de          	im -34
+     b84:	38          	neqbranch
+
+00000b85 <.L154>:
+     b85:	ff          	im -1
+     b86:	18          	addsp 32
+     b87:	58          	storesp 32
+     b88:	80          	im 0
+     b89:	78          	loadsp 32
+     b8a:	24          	lessthan
+     b8b:	82          	im 2
+     b8c:	b2          	im 50
+     b8d:	38          	neqbranch
+
+00000b8e <.L160>:
+     b8e:	81          	im 1
+     b8f:	17          	addsp 28
+     b90:	57          	storesp 28
+
+00000b91 <.L201>:
+     b91:	83          	im 3
+     b92:	e0          	im -32
+     b93:	94          	im 20
+     b94:	52          	storesp 8
+     b95:	83          	im 3
+     b96:	e2          	im -30
+     b97:	f4          	im -12
+     b98:	51          	storesp 4
+     b99:	80          	im 0
+     b9a:	c0          	im -64
+     b9b:	90          	im 16
+     b9c:	3f          	callpcrel
+     b9d:	83          	im 3
+     b9e:	e0          	im -32
+     b9f:	80          	im 0
+     ba0:	08          	load
+     ba1:	80          	im 0
+     ba2:	2e          	eq
+     ba3:	ff          	im -1
+     ba4:	a7          	im 39
+     ba5:	38          	neqbranch
+
+00000ba6 <.L150>:
+     ba6:	0b          	nop
+     ba7:	0b          	nop
+     ba8:	80          	im 0
+     ba9:	f9          	im -7
+     baa:	c4          	im -60
+     bab:	51          	storesp 4
+     bac:	80          	im 0
+     bad:	d0          	im -48
+     bae:	be          	im 62
+     baf:	3f          	callpcrel
+
+00000bb0 <.LM199>:
+     bb0:	95          	im 21
+     bb1:	51          	storesp 4
+     bb2:	80          	im 0
+     bb3:	ce          	im -50
+     bb4:	a2          	im 34
+     bb5:	3f          	callpcrel
+
+00000bb6 <.LM200>:
+     bb6:	80          	im 0
+     bb7:	0b          	nop
+     bb8:	83          	im 3
+     bb9:	e0          	im -32
+     bba:	b4          	im 52
+     bbb:	0c          	store
+
+00000bbc <.LM201>:
+     bbc:	79          	loadsp 36
+     bbd:	51          	storesp 4
+     bbe:	f6          	im -10
+     bbf:	fb          	im -5
+     bc0:	3f          	callpcrel
+
+00000bc1 <.LM202>:
+     bc1:	80          	im 0
+     bc2:	fb          	im -5
+     bc3:	c4          	im -60
+     bc4:	08          	load
+     bc5:	70          	loadsp 0
+     bc6:	33          	loadb
+     bc7:	70          	loadsp 0
+     bc8:	81          	im 1
+     bc9:	ff          	im -1
+     bca:	06          	and
+
+00000bcb <.LM203>:
+     bcb:	70          	loadsp 0
+     bcc:	81          	im 1
+     bcd:	2a          	lshiftright
+     bce:	81          	im 1
+     bcf:	32          	xor
+     bd0:	70          	loadsp 0
+     bd1:	81          	im 1
+     bd2:	06          	and
+     bd3:	51          	storesp 4
+     bd4:	52          	storesp 8
+     bd5:	56          	storesp 24
+     bd6:	51          	storesp 4
+     bd7:	53          	storesp 12
+     bd8:	72          	loadsp 8
+     bd9:	80          	im 0
+     bda:	eb          	im -21
+     bdb:	38          	neqbranch
+
+00000bdc <.L200>:
+     bdc:	73          	loadsp 12
+     bdd:	81          	im 1
+     bde:	32          	xor
+     bdf:	70          	loadsp 0
+     be0:	81          	im 1
+     be1:	06          	and
+     be2:	51          	storesp 4
+     be3:	53          	storesp 12
+     be4:	72          	loadsp 8
+     be5:	82          	im 2
+     be6:	e1          	im -31
+     be7:	38          	neqbranch
+
+00000be8 <.LM205>:
+     be8:	73          	loadsp 12
+     be9:	83          	im 3
+     bea:	2a          	lshiftright
+     beb:	81          	im 1
+     bec:	32          	xor
+     bed:	70          	loadsp 0
+     bee:	81          	im 1
+     bef:	06          	and
+     bf0:	51          	storesp 4
+     bf1:	53          	storesp 12
+     bf2:	72          	loadsp 8
+     bf3:	82          	im 2
+     bf4:	c2          	im -62
+     bf5:	38          	neqbranch
+
+00000bf6 <.LM206>:
+     bf6:	73          	loadsp 12
+     bf7:	82          	im 2
+     bf8:	2a          	lshiftright
+     bf9:	81          	im 1
+     bfa:	32          	xor
+     bfb:	70          	loadsp 0
+     bfc:	81          	im 1
+     bfd:	06          	and
+     bfe:	51          	storesp 4
+     bff:	53          	storesp 12
+     c00:	72          	loadsp 8
+     c01:	82          	im 2
+     c02:	a3          	im 35
+     c03:	38          	neqbranch
+
+00000c04 <.LM207>:
+     c04:	80          	im 0
+     c05:	fb          	im -5
+     c06:	bc          	im 60
+     c07:	08          	load
+     c08:	70          	loadsp 0
+     c09:	33          	loadb
+     c0a:	70          	loadsp 0
+     c0b:	81          	im 1
+     c0c:	ff          	im -1
+     c0d:	06          	and
+     c0e:	51          	storesp 4
+     c0f:	54          	storesp 16
+     c10:	54          	storesp 16
+     c11:	72          	loadsp 8
+     c12:	80          	im 0
+     c13:	2e          	eq
+     c14:	81          	im 1
+     c15:	f0          	im -16
+     c16:	38          	neqbranch
+
+00000c17 <.LM208>:
+     c17:	80          	im 0
+     c18:	cd          	im -51
+     c19:	aa          	im 42
+     c1a:	3f          	callpcrel
+
+00000c1b <.LM209>:
+     c1b:	80          	im 0
+     c1c:	fb          	im -5
+     c1d:	c8          	im -56
+     c1e:	08          	load
+     c1f:	80          	im 0
+     c20:	fb          	im -5
+     c21:	d8          	im -40
+     c22:	08          	load
+     c23:	54          	storesp 16
+     c24:	54          	storesp 16
+     c25:	73          	loadsp 12
+     c26:	33          	loadb
+     c27:	73          	loadsp 12
+     c28:	34          	storeb
+
+00000c29 <.LM210>:
+     c29:	80          	im 0
+     c2a:	fb          	im -5
+     c2b:	c4          	im -60
+     c2c:	08          	load
+     c2d:	70          	loadsp 0
+     c2e:	33          	loadb
+     c2f:	70          	loadsp 0
+     c30:	81          	im 1
+     c31:	ff          	im -1
+     c32:	06          	and
+
+00000c33 <.LM211>:
+     c33:	70          	loadsp 0
+     c34:	81          	im 1
+     c35:	2a          	lshiftright
+     c36:	81          	im 1
+     c37:	32          	xor
+     c38:	70          	loadsp 0
+     c39:	81          	im 1
+     c3a:	06          	and
+     c3b:	51          	storesp 4
+     c3c:	52          	storesp 8
+     c3d:	56          	storesp 24
+     c3e:	51          	storesp 4
+     c3f:	53          	storesp 12
+     c40:	72          	loadsp 8
+     c41:	80          	im 0
+     c42:	2e          	eq
+     c43:	ff          	im -1
+     c44:	97          	im 23
+     c45:	38          	neqbranch
+
+00000c46 <.L183>:
+     c46:	83          	im 3
+     c47:	e3          	im -29
+     c48:	a8          	im 40
+     c49:	08          	load
+     c4a:	82          	im 2
+     c4b:	05          	add
+     c4c:	83          	im 3
+     c4d:	e3          	im -29
+     c4e:	a8          	im 40
+     c4f:	0c          	store
+
+00000c50 <.LM213>:
+     c50:	84          	im 4
+     c51:	f1          	im -15
+     c52:	80          	im 0
+     c53:	51          	storesp 4
+
+00000c54 <.L203>:
+     c54:	f0          	im -16
+     c55:	dd          	im -35
+     c56:	3f          	callpcrel
+
+00000c57 <.LM215>:
+     c57:	80          	im 0
+     c58:	57          	storesp 28
+
+00000c59 <.LM216>:
+     c59:	80          	im 0
+     c5a:	cc          	im -52
+     c5b:	e8          	im -24
+     c5c:	3f          	callpcrel
+
+00000c5d <.LM217>:
+     c5d:	76          	loadsp 24
+     c5e:	54          	storesp 16
+     c5f:	fd          	im -3
+     c60:	97          	im 23
+     c61:	39          	poppcrel
+
+00000c62 <.L197>:
+     c62:	74          	loadsp 16
+     c63:	83          	im 3
+     c64:	e0          	im -32
+     c65:	9d          	im 29
+     c66:	57          	storesp 28
+     c67:	54          	storesp 16
+
+00000c68 <.L159>:
+     c68:	73          	loadsp 12
+     c69:	1a          	addsp 40
+     c6a:	53          	storesp 12
+     c6b:	75          	loadsp 20
+     c6c:	33          	loadb
+     c6d:	73          	loadsp 12
+     c6e:	34          	storeb
+
+00000c6f <.LM220>:
+     c6f:	75          	loadsp 20
+     c70:	33          	loadb
+     c71:	70          	loadsp 0
+     c72:	81          	im 1
+     c73:	ff          	im -1
+     c74:	06          	and
+     c75:	54          	storesp 16
+     c76:	55          	storesp 20
+     c77:	72          	loadsp 8
+     c78:	80          	im 0
+     c79:	2e          	eq
+     c7a:	fe          	im -2
+     c7b:	89          	im 9
+     c7c:	38          	neqbranch
+
+00000c7d <.LM221>:
+     c7d:	ff          	im -1
+     c7e:	80          	im 0
+     c7f:	15          	addsp 20
+     c80:	53          	storesp 12
+     c81:	72          	loadsp 8
+     c82:	76          	loadsp 24
+     c83:	70          	loadsp 0
+     c84:	81          	im 1
+     c85:	05          	add
+     c86:	58          	storesp 32
+     c87:	34          	storeb
+
+00000c88 <.LM222>:
+     c88:	81          	im 1
+     c89:	14          	addsp 16
+     c8a:	54          	storesp 16
+     c8b:	73          	loadsp 12
+     c8c:	8f          	im 15
+     c8d:	2e          	eq
+     c8e:	09          	not
+     c8f:	81          	im 1
+     c90:	06          	and
+     c91:	d6          	im -42
+     c92:	38          	neqbranch
+
+00000c93 <.LM223>:
+     c93:	ff          	im -1
+     c94:	18          	addsp 32
+     c95:	58          	storesp 32
+     c96:	77          	loadsp 28
+     c97:	80          	im 0
+     c98:	25          	lessthanorequal
+     c99:	fd          	im -3
+     c9a:	f3          	im -13
+     c9b:	38          	neqbranch
+     c9c:	a2          	im 34
+     c9d:	39          	poppcrel
+
+00000c9e <.L196>:
+     c9e:	0b          	nop
+     c9f:	0b          	nop
+     ca0:	80          	im 0
+     ca1:	f6          	im -10
+     ca2:	80          	im 0
+     ca3:	51          	storesp 4
+     ca4:	80          	im 0
+     ca5:	ce          	im -50
+     ca6:	c6          	im -58
+     ca7:	3f          	callpcrel
+
+00000ca8 <.LM225>:
+     ca8:	83          	im 3
+     ca9:	e3          	im -29
+     caa:	a8          	im 40
+     cab:	08          	load
+     cac:	77          	loadsp 28
+     cad:	2e          	eq
+     cae:	09          	not
+     caf:	81          	im 1
+     cb0:	06          	and
+     cb1:	fd          	im -3
+     cb2:	d2          	im -46
+     cb3:	38          	neqbranch
+     cb4:	ff          	im -1
+     cb5:	ac          	im 44
+     cb6:	39          	poppcrel
+
+00000cb7 <.L195>:
+     cb7:	78          	loadsp 32
+     cb8:	83          	im 3
+     cb9:	e3          	im -29
+     cba:	a8          	im 40
+     cbb:	0c          	store
+     cbc:	fc          	im -4
+     cbd:	fb          	im -5
+     cbe:	39          	poppcrel
+
+00000cbf <.L198>:
+     cbf:	83          	im 3
+     cc0:	e0          	im -32
+     cc1:	9d          	im 29
+     cc2:	51          	storesp 4
+     cc3:	80          	im 0
+     cc4:	ce          	im -50
+     cc5:	a7          	im 39
+     cc6:	3f          	callpcrel
+
+00000cc7 <.LM228>:
+     cc7:	81          	im 1
+     cc8:	19          	addsp 36
+
+00000cc9 <.LM229>:
+     cc9:	70          	loadsp 0
+     cca:	81          	im 1
+     ccb:	06          	and
+     ccc:	54          	storesp 16
+     ccd:	59          	storesp 36
+     cce:	72          	loadsp 8
+     ccf:	80          	im 0
+     cd0:	2e          	eq
+     cd1:	93          	im 19
+     cd2:	38          	neqbranch
+
+00000cd3 <.LM230>:
+     cd3:	94          	im 20
+     cd4:	51          	storesp 4
+     cd5:	80          	im 0
+     cd6:	cb          	im -53
+     cd7:	f9          	im -7
+     cd8:	3f          	callpcrel
+
+00000cd9 <.LM231>:
+     cd9:	78          	loadsp 32
+     cda:	a8          	im 40
+     cdb:	2e          	eq
+     cdc:	fd          	im -3
+     cdd:	c8          	im -56
+     cde:	38          	neqbranch
+
+00000cdf <.L202>:
+     cdf:	81          	im 1
+     ce0:	17          	addsp 28
+     ce1:	57          	storesp 28
+     ce2:	fd          	im -3
+     ce3:	ad          	im 45
+     ce4:	39          	poppcrel
+
+00000ce5 <.L161>:
+     ce5:	0b          	nop
+     ce6:	0b          	nop
+     ce7:	80          	im 0
+     ce8:	f9          	im -7
+     ce9:	c4          	im -60
+     cea:	51          	storesp 4
+     ceb:	80          	im 0
+     cec:	cd          	im -51
+     ced:	ff          	im -1
+     cee:	3f          	callpcrel
+
+00000cef <.LM234>:
+     cef:	78          	loadsp 32
+     cf0:	a8          	im 40
+     cf1:	2e          	eq
+     cf2:	09          	not
+     cf3:	81          	im 1
+     cf4:	06          	and
+     cf5:	e9          	im -23
+     cf6:	38          	neqbranch
+     cf7:	fd          	im -3
+     cf8:	ad          	im 45
+     cf9:	39          	poppcrel
+
+00000cfa <.L194>:
+     cfa:	0b          	nop
+     cfb:	0b          	nop
+     cfc:	80          	im 0
+     cfd:	f6          	im -10
+     cfe:	88          	im 8
+     cff:	51          	storesp 4
+     d00:	80          	im 0
+     d01:	cd          	im -51
+     d02:	ea          	im -22
+     d03:	3f          	callpcrel
+
+00000d04 <.L145>:
+     d04:	ff          	im -1
+     d05:	39          	poppcrel
+
+00000d06 <.L176>:
+     d06:	73          	loadsp 12
+     d07:	33          	loadb
+     d08:	70          	loadsp 0
+     d09:	81          	im 1
+     d0a:	ff          	im -1
+     d0b:	06          	and
+     d0c:	51          	storesp 4
+     d0d:	53          	storesp 12
+     d0e:	72          	loadsp 8
+     d0f:	80          	im 0
+     d10:	2e          	eq
+     d11:	f4          	im -12
+     d12:	38          	neqbranch
+
+00000d13 <.LM237>:
+     d13:	8c          	im 12
+     d14:	9a          	im 26
+     d15:	c0          	im -64
+     d16:	51          	storesp 4
+     d17:	ef          	im -17
+     d18:	9a          	im 26
+     d19:	3f          	callpcrel
+
+00000d1a <.LM238>:
+     d1a:	83          	im 3
+     d1b:	e2          	im -30
+     d1c:	e4          	im -28
+     d1d:	08          	load
+     d1e:	83          	im 3
+     d1f:	e0          	im -32
+     d20:	80          	im 0
+     d21:	0c          	store
+
+00000d22 <.LM239>:
+     d22:	8b          	im 11
+     d23:	3d          	pushspadd
+     d24:	0d          	popsp
+     d25:	04          	poppc
+
+00000d26 <.L186>:
+     d26:	83          	im 3
+     d27:	e3          	im -29
+     d28:	a8          	im 40
+     d29:	08          	load
+     d2a:	fe          	im -2
+     d2b:	06          	and
+     d2c:	83          	im 3
+     d2d:	e3          	im -29
+     d2e:	a8          	im 40
+     d2f:	0c          	store
+
+00000d30 <.LM241>:
+     d30:	84          	im 4
+     d31:	f1          	im -15
+     d32:	80          	im 0
+     d33:	51          	storesp 4
+     d34:	fe          	im -2
+     d35:	9e          	im 30
+     d36:	39          	poppcrel
+
+00000d37 <.L185>:
+     d37:	83          	im 3
+     d38:	e3          	im -29
+     d39:	a8          	im 40
+     d3a:	08          	load
+     d3b:	81          	im 1
+     d3c:	07          	or
+     d3d:	83          	im 3
+     d3e:	e3          	im -29
+     d3f:	a8          	im 40
+     d40:	0c          	store
+
+00000d41 <.LM243>:
+     d41:	84          	im 4
+     d42:	f1          	im -15
+     d43:	80          	im 0
+     d44:	51          	storesp 4
+     d45:	fe          	im -2
+     d46:	8d          	im 13
+     d47:	39          	poppcrel
+
+00000d48 <.L184>:
+     d48:	83          	im 3
+     d49:	e3          	im -29
+     d4a:	a8          	im 40
+     d4b:	08          	load
+     d4c:	fe          	im -2
+     d4d:	05          	add
+     d4e:	83          	im 3
+     d4f:	e3          	im -29
+     d50:	a8          	im 40
+     d51:	0c          	store
+
+00000d52 <.LM245>:
+     d52:	84          	im 4
+     d53:	f1          	im -15
+     d54:	80          	im 0
+     d55:	51          	storesp 4
+     d56:	fd          	im -3
+     d57:	fc          	im -4
+     d58:	39          	poppcrel
+
+00000d59 <actions>:
+     d59:	e2          	im -30
+     d5a:	3d          	pushspadd
+     d5b:	0d          	popsp
+
+00000d5c <.LM247>:
+     d5c:	80          	im 0
+
+00000d5d <.LM248>:
+     d5d:	0b          	nop
+     d5e:	80          	im 0
+     d5f:	fc          	im -4
+     d60:	b8          	im 56
+     d61:	08          	load
+     d62:	70          	loadsp 0
+     d63:	08          	load
+     d64:	70          	loadsp 0
+     d65:	81          	im 1
+     d66:	06          	and
+     d67:	51          	storesp 4
+     d68:	56          	storesp 24
+     d69:	56          	storesp 24
+     d6a:	58          	storesp 32
+     d6b:	73          	loadsp 12
+     d6c:	78          	loadsp 32
+     d6d:	2e          	eq
+     d6e:	09          	not
+     d6f:	81          	im 1
+     d70:	06          	and
+     d71:	82          	im 2
+     d72:	a7          	im 39
+     d73:	38          	neqbranch
+
+00000d74 <.L205>:
+     d74:	74          	loadsp 16
+     d75:	08          	load
+     d76:	70          	loadsp 0
+     d77:	81          	im 1
+     d78:	2a          	lshiftright
+     d79:	70          	loadsp 0
+     d7a:	81          	im 1
+     d7b:	06          	and
+     d7c:	51          	storesp 4
+     d7d:	51          	storesp 4
+     d7e:	54          	storesp 16
+     d7f:	73          	loadsp 12
+     d80:	80          	im 0
+     d81:	c9          	im -55
+     d82:	38          	neqbranch
+
+00000d83 <.L317>:
+     d83:	74          	loadsp 16
+     d84:	08          	load
+     d85:	70          	loadsp 0
+     d86:	82          	im 2
+     d87:	2a          	lshiftright
+     d88:	70          	loadsp 0
+     d89:	81          	im 1
+     d8a:	06          	and
+     d8b:	51          	storesp 4
+     d8c:	51          	storesp 4
+     d8d:	54          	storesp 16
+     d8e:	73          	loadsp 12
+     d8f:	80          	im 0
+     d90:	2e          	eq
+     d91:	90          	im 16
+     d92:	38          	neqbranch
+
+00000d93 <.LM251>:
+     d93:	80          	im 0
+     d94:	51          	storesp 4
+     d95:	f1          	im -15
+     d96:	d3          	im -45
+     d97:	3f          	callpcrel
+
+00000d98 <.LM252>:
+     d98:	81          	im 1
+     d99:	51          	storesp 4
+     d9a:	f1          	im -15
+     d9b:	ce          	im -50
+     d9c:	3f          	callpcrel
+     d9d:	80          	im 0
+     d9e:	fc          	im -4
+     d9f:	b8          	im 56
+     da0:	08          	load
+     da1:	55          	storesp 20
+
+00000da2 <.L323>:
+     da2:	74          	loadsp 16
+     da3:	08          	load
+     da4:	70          	loadsp 0
+     da5:	83          	im 3
+     da6:	2a          	lshiftright
+     da7:	70          	loadsp 0
+     da8:	81          	im 1
+     da9:	06          	and
+     daa:	51          	storesp 4
+     dab:	51          	storesp 4
+     dac:	54          	storesp 16
+     dad:	73          	loadsp 12
+     dae:	80          	im 0
+     daf:	2e          	eq
+     db0:	96          	im 22
+     db1:	38          	neqbranch
+
+00000db2 <.LM254>:
+     db2:	80          	im 0
+     db3:	51          	storesp 4
+     db4:	f1          	im -15
+     db5:	b4          	im 52
+     db6:	3f          	callpcrel
+
+00000db7 <.LM255>:
+     db7:	80          	im 0
+     db8:	fb          	im -5
+     db9:	e4          	im -28
+     dba:	08          	load
+     dbb:	54          	storesp 16
+     dbc:	80          	im 0
+     dbd:	74          	loadsp 16
+     dbe:	34          	storeb
+
+00000dbf <.LM256>:
+     dbf:	f0          	im -16
+     dc0:	af          	im 47
+     dc1:	3f          	callpcrel
+
+00000dc2 <.LM257>:
+     dc2:	81          	im 1
+     dc3:	51          	storesp 4
+     dc4:	f1          	im -15
+     dc5:	a4          	im 36
+     dc6:	3f          	callpcrel
+
+00000dc7 <.L204>:
+     dc7:	a0          	im 32
+     dc8:	3d          	pushspadd
+     dc9:	0d          	popsp
+     dca:	04          	poppc
+
+00000dcb <.L372>:
+     dcb:	81          	im 1
+     dcc:	51          	storesp 4
+     dcd:	f1          	im -15
+     dce:	bf          	im 63
+     dcf:	3f          	callpcrel
+
+00000dd0 <.LM260>:
+     dd0:	f0          	im -16
+     dd1:	9e          	im 30
+     dd2:	3f          	callpcrel
+
+00000dd3 <.LM261>:
+     dd3:	8e          	im 14
+     dd4:	3d          	pushspadd
+     dd5:	57          	storesp 28
+     dd6:	a1          	im 33
+     dd7:	53          	storesp 12
+     dd8:	80          	im 0
+     dd9:	f4          	im -12
+     dda:	b4          	im 52
+     ddb:	52          	storesp 8
+     ddc:	76          	loadsp 24
+     ddd:	51          	storesp 4
+     dde:	80          	im 0
+     ddf:	d7          	im -41
+     de0:	a8          	im 40
+     de1:	3f          	callpcrel
+
+00000de2 <.LM262>:
+     de2:	80          	im 0
+     de3:	56          	storesp 24
+
+00000de4 <.L321>:
+     de4:	84          	im 4
+     de5:	8c          	im 12
+     de6:	80          	im 0
+     de7:	16          	addsp 24
+     de8:	76          	loadsp 24
+     de9:	18          	addsp 32
+     dea:	55          	storesp 20
+     deb:	55          	storesp 20
+     dec:	73          	loadsp 12
+     ded:	33          	loadb
+     dee:	75          	loadsp 20
+     def:	34          	storeb
+
+00000df0 <.LM264>:
+     df0:	81          	im 1
+     df1:	16          	addsp 24
+     df2:	56          	storesp 24
+     df3:	75          	loadsp 20
+     df4:	a1          	im 33
+     df5:	2e          	eq
+     df6:	09          	not
+     df7:	81          	im 1
+     df8:	06          	and
+     df9:	ea          	im -22
+     dfa:	38          	neqbranch
+
+00000dfb <.LM265>:
+     dfb:	80          	im 0
+     dfc:	fb          	im -5
+     dfd:	e0          	im -32
+     dfe:	08          	load
+     dff:	54          	storesp 16
+     e00:	80          	im 0
+     e01:	74          	loadsp 16
+     e02:	34          	storeb
+
+00000e03 <.LM266>:
+     e03:	80          	im 0
+     e04:	fb          	im -5
+     e05:	dc          	im -36
+     e06:	08          	load
+     e07:	54          	storesp 16
+     e08:	86          	im 6
+     e09:	74          	loadsp 16
+     e0a:	34          	storeb
+
+00000e0b <.LM267>:
+     e0b:	80          	im 0
+     e0c:	fb          	im -5
+     e0d:	d8          	im -40
+     e0e:	08          	load
+     e0f:	54          	storesp 16
+     e10:	80          	im 0
+     e11:	74          	loadsp 16
+     e12:	34          	storeb
+
+00000e13 <.LM268>:
+     e13:	80          	im 0
+     e14:	fb          	im -5
+     e15:	d4          	im -44
+     e16:	08          	load
+     e17:	54          	storesp 16
+     e18:	8f          	im 15
+     e19:	74          	loadsp 16
+     e1a:	34          	storeb
+
+00000e1b <.LM269>:
+     e1b:	80          	im 0
+     e1c:	fb          	im -5
+     e1d:	d0          	im -48
+     e1e:	08          	load
+     e1f:	54          	storesp 16
+     e20:	80          	im 0
+     e21:	74          	loadsp 16
+     e22:	34          	storeb
+
+00000e23 <.LM270>:
+     e23:	80          	im 0
+     e24:	fb          	im -5
+     e25:	cc          	im -52
+     e26:	08          	load
+     e27:	54          	storesp 16
+     e28:	80          	im 0
+     e29:	74          	loadsp 16
+     e2a:	34          	storeb
+
+00000e2b <.LM271>:
+     e2b:	80          	im 0
+     e2c:	fb          	im -5
+     e2d:	c0          	im -64
+     e2e:	08          	load
+     e2f:	54          	storesp 16
+     e30:	ff          	im -1
+     e31:	74          	loadsp 16
+     e32:	34          	storeb
+
+00000e33 <.LM272>:
+     e33:	80          	im 0
+     e34:	fb          	im -5
+     e35:	b8          	im 56
+     e36:	08          	load
+     e37:	54          	storesp 16
+     e38:	e0          	im -32
+     e39:	74          	loadsp 16
+     e3a:	34          	storeb
+
+00000e3b <.LM273>:
+     e3b:	80          	im 0
+     e3c:	fb          	im -5
+     e3d:	b0          	im 48
+     e3e:	08          	load
+     e3f:	54          	storesp 16
+     e40:	a2          	im 34
+     e41:	74          	loadsp 16
+     e42:	34          	storeb
+
+00000e43 <.LM274>:
+     e43:	81          	im 1
+     e44:	51          	storesp 4
+     e45:	80          	im 0
+     e46:	c9          	im -55
+     e47:	95          	im 21
+     e48:	3f          	callpcrel
+
+00000e49 <.LM275>:
+     e49:	83          	im 3
+     e4a:	e3          	im -29
+     e4b:	98          	im 24
+     e4c:	51          	storesp 4
+     e4d:	f9          	im -7
+     e4e:	95          	im 21
+     e4f:	3f          	callpcrel
+     e50:	83          	im 3
+     e51:	e0          	im -32
+     e52:	80          	im 0
+     e53:	08          	load
+     e54:	80          	im 0
+     e55:	2e          	eq
+     e56:	ad          	im 45
+     e57:	38          	neqbranch
+
+00000e58 <.LM276>:
+     e58:	81          	im 1
+     e59:	0b          	nop
+     e5a:	83          	im 3
+     e5b:	e0          	im -32
+     e5c:	b4          	im 52
+     e5d:	0c          	store
+
+00000e5e <.LM277>:
+     e5e:	0b          	nop
+     e5f:	0b          	nop
+     e60:	80          	im 0
+     e61:	f6          	im -10
+     e62:	98          	im 24
+     e63:	51          	storesp 4
+     e64:	80          	im 0
+     e65:	cb          	im -53
+     e66:	86          	im 6
+     e67:	3f          	callpcrel
+
+00000e68 <.LM278>:
+     e68:	9e          	im 30
+     e69:	c2          	im -62
+     e6a:	a0          	im 32
+     e6b:	51          	storesp 4
+     e6c:	ec          	im -20
+     e6d:	c5          	im -59
+     e6e:	3f          	callpcrel
+
+00000e6f <.LM279>:
+     e6f:	80          	im 0
+     e70:	51          	storesp 4
+     e71:	ef          	im -17
+     e72:	f7          	im -9
+     e73:	3f          	callpcrel
+
+00000e74 <.LM280>:
+     e74:	80          	im 0
+     e75:	fb          	im -5
+     e76:	e4          	im -28
+     e77:	08          	load
+     e78:	54          	storesp 16
+     e79:	80          	im 0
+     e7a:	74          	loadsp 16
+     e7b:	34          	storeb
+
+00000e7c <.LM281>:
+     e7c:	ee          	im -18
+     e7d:	f2          	im -14
+     e7e:	3f          	callpcrel
+
+00000e7f <.LM282>:
+     e7f:	81          	im 1
+     e80:	51          	storesp 4
+     e81:	ef          	im -17
+     e82:	e7          	im -25
+     e83:	3f          	callpcrel
+
+00000e84 <.L322>:
+     e84:	83          	im 3
+     e85:	e0          	im -32
+     e86:	ac          	im 44
+     e87:	08          	load
+     e88:	51          	storesp 4
+     e89:	80          	im 0
+     e8a:	c8          	im -56
+     e8b:	d1          	im -47
+     e8c:	3f          	callpcrel
+
+00000e8d <.LM284>:
+     e8d:	80          	im 0
+     e8e:	51          	storesp 4
+     e8f:	ef          	im -17
+     e90:	fd          	im -3
+     e91:	3f          	callpcrel
+     e92:	80          	im 0
+     e93:	fc          	im -4
+     e94:	b8          	im 56
+     e95:	08          	load
+     e96:	55          	storesp 20
+     e97:	fd          	im -3
+     e98:	ea          	im -22
+     e99:	39          	poppcrel
+
+00000e9a <.L371>:
+     e9a:	77          	loadsp 28
+
+00000e9b <.LM286>:
+     e9b:	78          	loadsp 32
+
+00000e9c <.LM287>:
+     e9c:	79          	loadsp 36
+
+00000e9d <.LM288>:
+     e9d:	7a          	loadsp 40
+     e9e:	5f          	storesp 60
+     e9f:	59          	storesp 36
+     ea0:	5a          	storesp 40
+     ea1:	5b          	storesp 44
+
+00000ea2 <.LM289>:
+     ea2:	81          	im 1
+     ea3:	51          	storesp 4
+     ea4:	ef          	im -17
+     ea5:	e8          	im -24
+     ea6:	3f          	callpcrel
+
+00000ea7 <.LM290>:
+     ea7:	81          	im 1
+     ea8:	51          	storesp 4
+     ea9:	80          	im 0
+     eaa:	c8          	im -56
+     eab:	b1          	im 49
+     eac:	3f          	callpcrel
+
+00000ead <.L209>:
+     ead:	81          	im 1
+     eae:	9f          	im 31
+     eaf:	e0          	im -32
+     eb0:	80          	im 0
+     eb1:	18          	addsp 32
+     eb2:	86          	im 6
+     eb3:	b8          	im 56
+     eb4:	80          	im 0
+     eb5:	19          	addsp 36
+     eb6:	55          	storesp 20
+     eb7:	55          	storesp 20
+     eb8:	73          	loadsp 12
+     eb9:	33          	loadb
+     eba:	75          	loadsp 20
+     ebb:	34          	storeb
+
+00000ebc <.LM292>:
+     ebc:	81          	im 1
+     ebd:	18          	addsp 32
+     ebe:	58          	storesp 32
+     ebf:	77          	loadsp 28
+     ec0:	88          	im 8
+     ec1:	80          	im 0
+     ec2:	2e          	eq
+     ec3:	09          	not
+     ec4:	81          	im 1
+     ec5:	06          	and
+     ec6:	e6          	im -26
+     ec7:	38          	neqbranch
+
+00000ec8 <.LM293>:
+     ec8:	80          	im 0
+     ec9:	c0          	im -64
+     eca:	58          	storesp 32
+
+00000ecb <.L213>:
+     ecb:	86          	im 6
+     ecc:	b8          	im 56
+     ecd:	80          	im 0
+     ece:	18          	addsp 32
+     ecf:	54          	storesp 16
+     ed0:	80          	im 0
+     ed1:	74          	loadsp 16
+     ed2:	34          	storeb
+
+00000ed3 <.LM295>:
+     ed3:	81          	im 1
+     ed4:	18          	addsp 32
+     ed5:	58          	storesp 32
+     ed6:	77          	loadsp 28
+     ed7:	88          	im 8
+     ed8:	80          	im 0
+     ed9:	2e          	eq
+     eda:	09          	not
+     edb:	81          	im 1
+     edc:	06          	and
+     edd:	ed          	im -19
+     ede:	38          	neqbranch
+
+00000edf <.LM296>:
+     edf:	83          	im 3
+     ee0:	a0          	im 32
+     ee1:	80          	im 0
+     ee2:	58          	storesp 32
+
+00000ee3 <.L217>:
+     ee3:	81          	im 1
+     ee4:	9c          	im 28
+     ee5:	80          	im 0
+     ee6:	80          	im 0
+     ee7:	18          	addsp 32
+     ee8:	88          	im 8
+     ee9:	80          	im 0
+     eea:	80          	im 0
+     eeb:	19          	addsp 36
+     eec:	56          	storesp 24
+     eed:	54          	storesp 16
+     eee:	74          	loadsp 16
+     eef:	33          	loadb
+     ef0:	74          	loadsp 16
+     ef1:	34          	storeb
+
+00000ef2 <.LM298>:
+     ef2:	84          	im 4
+     ef3:	80          	im 0
+     ef4:	80          	im 0
+     ef5:	18          	addsp 32
+     ef6:	54          	storesp 16
+     ef7:	80          	im 0
+     ef8:	74          	loadsp 16
+     ef9:	34          	storeb
+
+00000efa <.LM299>:
+     efa:	81          	im 1
+     efb:	18          	addsp 32
+     efc:	58          	storesp 32
+     efd:	77          	loadsp 28
+     efe:	83          	im 3
+     eff:	a0          	im 32
+     f00:	9f          	im 31
+     f01:	2e          	eq
+     f02:	09          	not
+     f03:	81          	im 1
+     f04:	06          	and
+     f05:	dd          	im -35
+     f06:	38          	neqbranch
+
+00000f07 <.LM300>:
+     f07:	83          	im 3
+     f08:	a4          	im 36
+     f09:	80          	im 0
+     f0a:	58          	storesp 32
+
+00000f0b <.L221>:
+     f0b:	81          	im 1
+     f0c:	9c          	im 28
+     f0d:	80          	im 0
+     f0e:	80          	im 0
+     f0f:	18          	addsp 32
+     f10:	88          	im 8
+     f11:	80          	im 0
+     f12:	80          	im 0
+     f13:	19          	addsp 36
+     f14:	56          	storesp 24
+     f15:	54          	storesp 16
+     f16:	74          	loadsp 16
+     f17:	33          	loadb
+     f18:	74          	loadsp 16
+     f19:	34          	storeb
+
+00000f1a <.LM302>:
+     f1a:	84          	im 4
+     f1b:	80          	im 0
+     f1c:	80          	im 0
+     f1d:	18          	addsp 32
+     f1e:	54          	storesp 16
+     f1f:	80          	im 0
+     f20:	74          	loadsp 16
+     f21:	34          	storeb
+
+00000f22 <.LM303>:
+     f22:	81          	im 1
+     f23:	18          	addsp 32
+     f24:	58          	storesp 32
+     f25:	77          	loadsp 28
+     f26:	83          	im 3
+     f27:	a4          	im 36
+     f28:	9f          	im 31
+     f29:	2e          	eq
+     f2a:	09          	not
+     f2b:	81          	im 1
+     f2c:	06          	and
+     f2d:	dd          	im -35
+     f2e:	38          	neqbranch
+
+00000f2f <.LM304>:
+     f2f:	83          	im 3
+     f30:	a8          	im 40
+     f31:	80          	im 0
+     f32:	58          	storesp 32
+
+00000f33 <.L225>:
+     f33:	81          	im 1
+     f34:	9c          	im 28
+     f35:	80          	im 0
+     f36:	80          	im 0
+     f37:	18          	addsp 32
+     f38:	88          	im 8
+     f39:	80          	im 0
+     f3a:	80          	im 0
+     f3b:	19          	addsp 36
+     f3c:	56          	storesp 24
+     f3d:	54          	storesp 16
+     f3e:	74          	loadsp 16
+     f3f:	33          	loadb
+     f40:	74          	loadsp 16
+     f41:	34          	storeb
+
+00000f42 <.LM306>:
+     f42:	84          	im 4
+     f43:	80          	im 0
+     f44:	80          	im 0
+     f45:	18          	addsp 32
+     f46:	54          	storesp 16
+     f47:	80          	im 0
+     f48:	74          	loadsp 16
+     f49:	34          	storeb
+
+00000f4a <.LM307>:
+     f4a:	81          	im 1
+     f4b:	18          	addsp 32
+     f4c:	58          	storesp 32
+     f4d:	77          	loadsp 28
+     f4e:	83          	im 3
+     f4f:	a8          	im 40
+     f50:	8f          	im 15
+     f51:	2e          	eq
+     f52:	09          	not
+     f53:	81          	im 1
+     f54:	06          	and
+     f55:	dd          	im -35
+     f56:	38          	neqbranch
+
+00000f57 <.LM308>:
+     f57:	80          	im 0
+     f58:	fb          	im -5
+     f59:	c0          	im -64
+     f5a:	08          	load
+     f5b:	70          	loadsp 0
+     f5c:	33          	loadb
+     f5d:	70          	loadsp 0
+     f5e:	81          	im 1
+     f5f:	ff          	im -1
+     f60:	06          	and
+
+00000f61 <.LM309>:
+     f61:	9a          	im 26
+     f62:	3d          	pushspadd
+     f63:	59          	storesp 36
+     f64:	5c          	storesp 48
+     f65:	51          	storesp 4
+     f66:	54          	storesp 16
+     f67:	a1          	im 33
+     f68:	53          	storesp 12
+     f69:	80          	im 0
+     f6a:	f4          	im -12
+     f6b:	d8          	im -40
+     f6c:	52          	storesp 8
+     f6d:	75          	loadsp 20
+     f6e:	51          	storesp 4
+     f6f:	80          	im 0
+     f70:	d4          	im -44
+     f71:	97          	im 23
+     f72:	3f          	callpcrel
+
+00000f73 <.LM310>:
+     f73:	80          	im 0
+     f74:	58          	storesp 32
+
+00000f75 <.L229>:
+     f75:	86          	im 6
+     f76:	b8          	im 56
+     f77:	80          	im 0
+     f78:	18          	addsp 32
+     f79:	78          	loadsp 32
+     f7a:	17          	addsp 28
+     f7b:	55          	storesp 20
+     f7c:	55          	storesp 20
+     f7d:	73          	loadsp 12
+     f7e:	33          	loadb
+     f7f:	75          	loadsp 20
+     f80:	34          	storeb
+
+00000f81 <.LM312>:
+     f81:	81          	im 1
+     f82:	18          	addsp 32
+     f83:	58          	storesp 32
+     f84:	77          	loadsp 28
+     f85:	a1          	im 33
+     f86:	2e          	eq
+     f87:	09          	not
+     f88:	81          	im 1
+     f89:	06          	and
+     f8a:	ea          	im -22
+     f8b:	38          	neqbranch
+
+00000f8c <.LM313>:
+     f8c:	80          	im 0
+     f8d:	fb          	im -5
+     f8e:	e0          	im -32
+     f8f:	08          	load
+     f90:	54          	storesp 16
+     f91:	80          	im 0
+     f92:	74          	loadsp 16
+     f93:	34          	storeb
+
+00000f94 <.LM314>:
+     f94:	80          	im 0
+     f95:	fb          	im -5
+     f96:	dc          	im -36
+     f97:	08          	load
+     f98:	54          	storesp 16
+     f99:	ff          	im -1
+     f9a:	9c          	im 28
+     f9b:	74          	loadsp 16
+     f9c:	34          	storeb
+
+00000f9d <.LM315>:
+     f9d:	80          	im 0
+     f9e:	fb          	im -5
+     f9f:	d8          	im -40
+     fa0:	08          	load
+     fa1:	54          	storesp 16
+     fa2:	80          	im 0
+     fa3:	74          	loadsp 16
+     fa4:	34          	storeb
+
+00000fa5 <.LM316>:
+     fa5:	80          	im 0
+     fa6:	fb          	im -5
+     fa7:	d4          	im -44
+     fa8:	08          	load
+     fa9:	54          	storesp 16
+     faa:	8f          	im 15
+     fab:	74          	loadsp 16
+     fac:	34          	storeb
+
+00000fad <.LM317>:
+     fad:	80          	im 0
+     fae:	fb          	im -5
+     faf:	d0          	im -48
+     fb0:	08          	load
+     fb1:	54          	storesp 16
+     fb2:	80          	im 0
+     fb3:	74          	loadsp 16
+     fb4:	34          	storeb
+
+00000fb5 <.LM318>:
+     fb5:	80          	im 0
+     fb6:	fb          	im -5
+     fb7:	cc          	im -52
+     fb8:	08          	load
+     fb9:	54          	storesp 16
+     fba:	80          	im 0
+     fbb:	74          	loadsp 16
+     fbc:	34          	storeb
+
+00000fbd <.LM319>:
+     fbd:	80          	im 0
+     fbe:	fb          	im -5
+     fbf:	b8          	im 56
+     fc0:	08          	load
+     fc1:	54          	storesp 16
+     fc2:	e0          	im -32
+     fc3:	74          	loadsp 16
+     fc4:	34          	storeb
+
+00000fc5 <.LM320>:
+     fc5:	80          	im 0
+     fc6:	fb          	im -5
+     fc7:	b0          	im 48
+     fc8:	08          	load
+     fc9:	54          	storesp 16
+     fca:	a2          	im 34
+     fcb:	74          	loadsp 16
+     fcc:	34          	storeb
+
+00000fcd <.LM321>:
+     fcd:	80          	im 0
+     fce:	fb          	im -5
+     fcf:	c0          	im -64
+     fd0:	08          	load
+     fd1:	54          	storesp 16
+     fd2:	ff          	im -1
+     fd3:	74          	loadsp 16
+     fd4:	34          	storeb
+
+00000fd5 <.LM322>:
+     fd5:	80          	im 0
+     fd6:	fb          	im -5
+     fd7:	ac          	im 44
+     fd8:	08          	load
+     fd9:	54          	storesp 16
+     fda:	83          	im 3
+     fdb:	74          	loadsp 16
+     fdc:	34          	storeb
+
+00000fdd <.LM323>:
+     fdd:	80          	im 0
+     fde:	fb          	im -5
+     fdf:	b4          	im 52
+     fe0:	08          	load
+     fe1:	54          	storesp 16
+     fe2:	82          	im 2
+     fe3:	74          	loadsp 16
+     fe4:	34          	storeb
+
+00000fe5 <.L360>:
+     fe5:	fd          	im -3
+     fe6:	5d          	storesp 52
+
+00000fe7 <.L366>:
+     fe7:	87          	im 7
+     fe8:	a9          	im 41
+     fe9:	c0          	im -64
+     fea:	51          	storesp 4
+     feb:	e9          	im -23
+     fec:	c6          	im -58
+     fed:	3f          	callpcrel
+
+00000fee <.LM325>:
+     fee:	80          	im 0
+     fef:	c5          	im -59
+     ff0:	d3          	im -45
+     ff1:	3f          	callpcrel
+
+00000ff2 <.LM326>:
+     ff2:	80          	im 0
+     ff3:	58          	storesp 32
+
+00000ff4 <.L235>:
+     ff4:	80          	im 0
+     ff5:	0b          	nop
+     ff6:	86          	im 6
+     ff7:	b8          	im 56
+     ff8:	c0          	im -64
+     ff9:	19          	addsp 36
+     ffa:	34          	storeb
+
+00000ffb <.LM328>:
+     ffb:	81          	im 1
+     ffc:	18          	addsp 32
+     ffd:	58          	storesp 32
+     ffe:	77          	loadsp 28
+     fff:	87          	im 7
+    1000:	c0          	im -64
+    1001:	2e          	eq
+    1002:	09          	not
+    1003:	81          	im 1
+    1004:	06          	and
+    1005:	ee          	im -18
+    1006:	38          	neqbranch
+
+00001007 <.LM329>:
+    1007:	0b          	nop
+    1008:	0b          	nop
+    1009:	80          	im 0
+    100a:	f6          	im -10
+    100b:	a4          	im 36
+    100c:	51          	storesp 4
+    100d:	80          	im 0
+    100e:	c7          	im -57
+    100f:	dd          	im -35
+    1010:	3f          	callpcrel
+
+00001011 <.LM330>:
+    1011:	0b          	nop
+    1012:	0b          	nop
+    1013:	80          	im 0
+    1014:	f6          	im -10
+    1015:	b8          	im 56
+    1016:	51          	storesp 4
+    1017:	80          	im 0
+    1018:	c7          	im -57
+    1019:	d3          	im -45
+    101a:	3f          	callpcrel
+
+0000101b <.LM331>:
+    101b:	0b          	nop
+    101c:	0b          	nop
+    101d:	80          	im 0
+    101e:	f6          	im -10
+    101f:	cc          	im -52
+    1020:	51          	storesp 4
+    1021:	80          	im 0
+    1022:	c7          	im -57
+    1023:	c9          	im -55
+    1024:	3f          	callpcrel
+
+00001025 <.LM332>:
+    1025:	80          	im 0
+    1026:	fc          	im -4
+    1027:	c4          	im -60
+    1028:	08          	load
+    1029:	70          	loadsp 0
+    102a:	08          	load
+    102b:	70          	loadsp 0
+    102c:	88          	im 8
+    102d:	2c          	ashiftright
+    102e:	8f          	im 15
+    102f:	06          	and
+    1030:	57          	storesp 28
+    1031:	55          	storesp 20
+    1032:	56          	storesp 24
+
+00001033 <.LM333>:
+    1033:	78          	loadsp 32
+    1034:	b3          	im 51
+    1035:	38          	neqbranch
+
+00001036 <.LM334>:
+    1036:	76          	loadsp 24
+    1037:	80          	im 0
+    1038:	2e          	eq
+    1039:	a7          	im 39
+    103a:	38          	neqbranch
+
+0000103b <.LM335>:
+    103b:	75          	loadsp 20
+    103c:	08          	load
+    103d:	77          	loadsp 28
+    103e:	16          	addsp 24
+    103f:	83          	im 3
+    1040:	06          	and
+    1041:	71          	loadsp 4
+    1042:	e1          	im -31
+    1043:	ff          	im -1
+    1044:	06          	and
+    1045:	71          	loadsp 4
+    1046:	88          	im 8
+    1047:	2b          	ashiftleft
+    1048:	07          	or
+    1049:	78          	loadsp 32
+    104a:	0c          	store
+
+0000104b <.LM336>:
+    104b:	7a          	loadsp 40
+
+0000104c <.LM337>:
+    104c:	7b          	loadsp 44
+    104d:	5a          	storesp 40
+    104e:	5e          	storesp 56
+    104f:	56          	storesp 24
+    1050:	54          	storesp 16
+
+00001051 <.LM338>:
+    1051:	87          	im 7
+    1052:	a9          	im 41
+    1053:	c0          	im -64
+    1054:	51          	storesp 4
+    1055:	e8          	im -24
+    1056:	dc          	im -36
+    1057:	3f          	callpcrel
+
+00001058 <.LM339>:
+    1058:	80          	im 0
+    1059:	c4          	im -60
+    105a:	e9          	im -23
+    105b:	3f          	callpcrel
+
+0000105c <.LM340>:
+    105c:	80          	im 0
+    105d:	58          	storesp 32
+    105e:	ff          	im -1
+    105f:	94          	im 20
+    1060:	39          	poppcrel
+
+00001061 <.L237>:
+    1061:	81          	im 1
+    1062:	80          	im 0
+    1063:	51          	storesp 4
+    1064:	80          	im 0
+    1065:	c7          	im -57
+    1066:	80          	im 0
+    1067:	3f          	callpcrel
+
+00001068 <.L236>:
+    1068:	74          	loadsp 16
+    1069:	81          	im 1
+    106a:	2e          	eq
+    106b:	89          	im 9
+    106c:	93          	im 19
+    106d:	38          	neqbranch
+    106e:	81          	im 1
+    106f:	75          	loadsp 20
+    1070:	25          	lessthanorequal
+    1071:	88          	im 8
+    1072:	d4          	im -44
+    1073:	38          	neqbranch
+    1074:	74          	loadsp 16
+    1075:	82          	im 2
+    1076:	2e          	eq
+    1077:	88          	im 8
+    1078:	8b          	im 11
+    1079:	38          	neqbranch
+    107a:	74          	loadsp 16
+    107b:	83          	im 3
+    107c:	2e          	eq
+    107d:	86          	im 6
+    107e:	9a          	im 26
+    107f:	38          	neqbranch
+
+00001080 <.L243>:
+    1080:	0b          	nop
+    1081:	0b          	nop
+    1082:	80          	im 0
+    1083:	f6          	im -10
+    1084:	d4          	im -44
+    1085:	51          	storesp 4
+    1086:	80          	im 0
+    1087:	c6          	im -58
+    1088:	e4          	im -28
+    1089:	3f          	callpcrel
+
+0000108a <.LM344>:
+    108a:	0b          	nop
+    108b:	0b          	nop
+    108c:	80          	im 0
+    108d:	f9          	im -7
+    108e:	c4          	im -60
+    108f:	51          	storesp 4
+    1090:	80          	im 0
+    1091:	c6          	im -58
+    1092:	da          	im -38
+    1093:	3f          	callpcrel
+
+00001094 <.LM345>:
+    1094:	0b          	nop
+    1095:	0b          	nop
+    1096:	80          	im 0
+    1097:	f6          	im -10
+    1098:	dc          	im -36
+    1099:	51          	storesp 4
+    109a:	80          	im 0
+    109b:	c6          	im -58
+    109c:	d0          	im -48
+    109d:	3f          	callpcrel
+
+0000109e <.LM346>:
+    109e:	80          	im 0
+    109f:	fc          	im -4
+    10a0:	c4          	im -60
+    10a1:	08          	load
+    10a2:	70          	loadsp 0
+    10a3:	08          	load
+    10a4:	70          	loadsp 0
+    10a5:	8c          	im 12
+    10a6:	2c          	ashiftright
+    10a7:	8f          	im 15
+    10a8:	06          	and
+    10a9:	57          	storesp 28
+    10aa:	55          	storesp 20
+    10ab:	56          	storesp 24
+
+000010ac <.LM347>:
+    10ac:	78          	loadsp 32
+    10ad:	81          	im 1
+    10ae:	2e          	eq
+    10af:	83          	im 3
+    10b0:	a2          	im 34
+    10b1:	38          	neqbranch
+
+000010b2 <.L245>:
+    10b2:	74          	loadsp 16
+    10b3:	81          	im 1
+    10b4:	2e          	eq
+    10b5:	87          	im 7
+    10b6:	9c          	im 28
+    10b7:	38          	neqbranch
+    10b8:	81          	im 1
+    10b9:	75          	loadsp 20
+    10ba:	25          	lessthanorequal
+    10bb:	86          	im 6
+    10bc:	e1          	im -31
+    10bd:	38          	neqbranch
+    10be:	74          	loadsp 16
+    10bf:	82          	im 2
+    10c0:	2e          	eq
+    10c1:	8c          	im 12
+    10c2:	a9          	im 41
+    10c3:	38          	neqbranch
+    10c4:	74          	loadsp 16
+    10c5:	83          	im 3
+    10c6:	2e          	eq
+    10c7:	8c          	im 12
+    10c8:	e2          	im -30
+    10c9:	38          	neqbranch
+
+000010ca <.L252>:
+    10ca:	0b          	nop
+    10cb:	0b          	nop
+    10cc:	80          	im 0
+    10cd:	f6          	im -10
+    10ce:	d4          	im -44
+    10cf:	51          	storesp 4
+    10d0:	80          	im 0
+    10d1:	c6          	im -58
+    10d2:	9a          	im 26
+    10d3:	3f          	callpcrel
+
+000010d4 <.LM350>:
+    10d4:	0b          	nop
+    10d5:	0b          	nop
+    10d6:	80          	im 0
+    10d7:	f9          	im -7
+    10d8:	c4          	im -60
+    10d9:	51          	storesp 4
+    10da:	80          	im 0
+    10db:	c6          	im -58
+    10dc:	90          	im 16
+    10dd:	3f          	callpcrel
+
+000010de <.LM351>:
+    10de:	0b          	nop
+    10df:	0b          	nop
+    10e0:	80          	im 0
+    10e1:	f6          	im -10
+    10e2:	e8          	im -24
+    10e3:	51          	storesp 4
+    10e4:	80          	im 0
+    10e5:	c6          	im -58
+    10e6:	86          	im 6
+    10e7:	3f          	callpcrel
+
+000010e8 <.LM352>:
+    10e8:	80          	im 0
+    10e9:	fc          	im -4
+    10ea:	c4          	im -60
+    10eb:	08          	load
+    10ec:	70          	loadsp 0
+    10ed:	08          	load
+    10ee:	bf          	im 63
+    10ef:	06          	and
+    10f0:	56          	storesp 24
+    10f1:	56          	storesp 24
+
+000010f2 <.LM353>:
+    10f2:	78          	loadsp 32
+    10f3:	82          	im 2
+    10f4:	2e          	eq
+    10f5:	85          	im 5
+    10f6:	ff          	im -1
+    10f7:	38          	neqbranch
+
+000010f8 <.L254>:
+    10f8:	81          	im 1
+    10f9:	15          	addsp 20
+    10fa:	70          	loadsp 0
+    10fb:	83          	im 3
+    10fc:	c1          	im -63
+    10fd:	9c          	im 28
+    10fe:	35          	div
+    10ff:	70          	loadsp 0
+    1100:	83          	im 3
+    1101:	ff          	im -1
+    1102:	ff          	im -1
+    1103:	06          	and
+    1104:	53          	storesp 12
+    1105:	51          	storesp 4
+    1106:	54          	storesp 16
+    1107:	80          	im 0
+    1108:	c6          	im -58
+    1109:	f2          	im -14
+    110a:	3f          	callpcrel
+
+0000110b <.LM355>:
+    110b:	0b          	nop
+    110c:	0b          	nop
+    110d:	80          	im 0
+    110e:	f6          	im -10
+    110f:	f0          	im -16
+    1110:	51          	storesp 4
+    1111:	80          	im 0
+    1112:	c5          	im -59
+    1113:	d9          	im -39
+    1114:	3f          	callpcrel
+
+00001115 <.LM356>:
+    1115:	78          	loadsp 32
+    1116:	83          	im 3
+    1117:	2e          	eq
+    1118:	85          	im 5
+    1119:	b7          	im 55
+    111a:	38          	neqbranch
+
+0000111b <.L257>:
+    111b:	83          	im 3
+    111c:	e3          	im -29
+    111d:	98          	im 24
+    111e:	51          	storesp 4
+    111f:	80          	im 0
+    1120:	c5          	im -59
+    1121:	cb          	im -53
+    1122:	3f          	callpcrel
+
+00001123 <.LM358>:
+    1123:	0b          	nop
+    1124:	0b          	nop
+    1125:	80          	im 0
+    1126:	f6          	im -10
+    1127:	fc          	im -4
+    1128:	51          	storesp 4
+    1129:	80          	im 0
+    112a:	c5          	im -59
+    112b:	c1          	im -63
+    112c:	3f          	callpcrel
+
+0000112d <.LM359>:
+    112d:	78          	loadsp 32
+    112e:	84          	im 4
+    112f:	2e          	eq
+    1130:	84          	im 4
+    1131:	c2          	im -62
+    1132:	38          	neqbranch
+
+00001133 <.L258>:
+    1133:	83          	im 3
+    1134:	e3          	im -29
+    1135:	d8          	im -40
+    1136:	51          	storesp 4
+    1137:	80          	im 0
+    1138:	c5          	im -59
+    1139:	b3          	im 51
+    113a:	3f          	callpcrel
+
+0000113b <.LM361>:
+    113b:	0b          	nop
+    113c:	0b          	nop
+    113d:	80          	im 0
+    113e:	f7          	im -9
+    113f:	84          	im 4
+    1140:	51          	storesp 4
+    1141:	80          	im 0
+    1142:	c5          	im -59
+    1143:	a9          	im 41
+    1144:	3f          	callpcrel
+
+00001145 <.LM362>:
+    1145:	78          	loadsp 32
+    1146:	85          	im 5
+    1147:	2e          	eq
+    1148:	84          	im 4
+    1149:	85          	im 5
+    114a:	38          	neqbranch
+
+0000114b <.L259>:
+    114b:	83          	im 3
+    114c:	e2          	im -30
+    114d:	c8          	im -56
+    114e:	51          	storesp 4
+    114f:	80          	im 0
+    1150:	c5          	im -59
+    1151:	9b          	im 27
+    1152:	3f          	callpcrel
+
+00001153 <.LM364>:
+    1153:	0b          	nop
+    1154:	0b          	nop
+    1155:	80          	im 0
+    1156:	f7          	im -9
+    1157:	8c          	im 12
+    1158:	51          	storesp 4
+    1159:	80          	im 0
+    115a:	c5          	im -59
+    115b:	91          	im 17
+    115c:	3f          	callpcrel
+
+0000115d <.LM365>:
+    115d:	78          	loadsp 32
+    115e:	86          	im 6
+    115f:	2e          	eq
+    1160:	85          	im 5
+    1161:	b3          	im 51
+    1162:	38          	neqbranch
+
+00001163 <.L260>:
+    1163:	83          	im 3
+    1164:	e0          	im -32
+    1165:	b8          	im 56
+    1166:	51          	storesp 4
+    1167:	80          	im 0
+    1168:	c5          	im -59
+    1169:	83          	im 3
+    116a:	3f          	callpcrel
+
+0000116b <.LM367>:
+    116b:	7c          	loadsp 48
+    116c:	83          	im 3
+    116d:	26          	ulessthan
+    116e:	93          	im 19
+    116f:	38          	neqbranch
+
+00001170 <.LM368>:
+    1170:	7b          	loadsp 44
+    1171:	81          	im 1
+    1172:	2e          	eq
+    1173:	87          	im 7
+    1174:	c0          	im -64
+    1175:	38          	neqbranch
+
+00001176 <.LM369>:
+    1176:	76          	loadsp 24
+    1177:	81          	im 1
+    1178:	2e          	eq
+    1179:	8a          	im 10
+    117a:	8b          	im 11
+    117b:	38          	neqbranch
+
+0000117c <.LM370>:
+    117c:	76          	loadsp 24
+    117d:	ff          	im -1
+    117e:	2e          	eq
+    117f:	89          	im 9
+    1180:	9f          	im 31
+    1181:	38          	neqbranch
+
+00001182 <.L261>:
+    1182:	78          	loadsp 32
+    1183:	87          	im 7
+    1184:	2e          	eq
+    1185:	88          	im 8
+    1186:	9b          	im 27
+    1187:	38          	neqbranch
+
+00001188 <.L279>:
+    1188:	0b          	nop
+    1189:	0b          	nop
+    118a:	80          	im 0
+    118b:	f7          	im -9
+    118c:	94          	im 20
+    118d:	51          	storesp 4
+    118e:	80          	im 0
+    118f:	c4          	im -60
+    1190:	dc          	im -36
+    1191:	3f          	callpcrel
+
+00001192 <.LM373>:
+    1192:	78          	loadsp 32
+    1193:	87          	im 7
+    1194:	2e          	eq
+    1195:	86          	im 6
+    1196:	a2          	im 34
+    1197:	38          	neqbranch
+
+00001198 <.LM374>:
+    1198:	78          	loadsp 32
+    1199:	88          	im 8
+    119a:	2e          	eq
+    119b:	88          	im 8
+    119c:	8e          	im 14
+    119d:	38          	neqbranch
+
+0000119e <.L282>:
+    119e:	0b          	nop
+    119f:	0b          	nop
+    11a0:	80          	im 0
+    11a1:	f7          	im -9
+    11a2:	9c          	im 28
+    11a3:	51          	storesp 4
+    11a4:	80          	im 0
+    11a5:	c4          	im -60
+    11a6:	c6          	im -58
+    11a7:	3f          	callpcrel
+
+000011a8 <.LM376>:
+    11a8:	78          	loadsp 32
+    11a9:	88          	im 8
+    11aa:	2e          	eq
+    11ab:	81          	im 1
+    11ac:	d3          	im -45
+    11ad:	38          	neqbranch
+
+000011ae <.L283>:
+    11ae:	80          	im 0
+
+000011af <.LM378>:
+    11af:	70          	loadsp 0
+
+000011b0 <.LM379>:
+    11b0:	80          	im 0
+    11b1:	fb          	im -5
+    11b2:	c4          	im -60
+    11b3:	08          	load
+    11b4:	70          	loadsp 0
+    11b5:	33          	loadb
+    11b6:	70          	loadsp 0
+    11b7:	81          	im 1
+    11b8:	ff          	im -1
+    11b9:	06          	and
+
+000011ba <.LM380>:
+    11ba:	70          	loadsp 0
+    11bb:	81          	im 1
+    11bc:	2a          	lshiftright
+    11bd:	81          	im 1
+    11be:	32          	xor
+    11bf:	81          	im 1
+    11c0:	06          	and
+    11c1:	5b          	storesp 44
+    11c2:	59          	storesp 36
+    11c3:	51          	storesp 4
+    11c4:	56          	storesp 24
+    11c5:	58          	storesp 32
+    11c6:	5c          	storesp 48
+    11c7:	75          	loadsp 20
+    11c8:	80          	im 0
+    11c9:	e9          	im -23
+    11ca:	38          	neqbranch
+
+000011cb <.L287>:
+    11cb:	74          	loadsp 16
+    11cc:	81          	im 1
+    11cd:	32          	xor
+    11ce:	70          	loadsp 0
+    11cf:	81          	im 1
+    11d0:	06          	and
+    11d1:	51          	storesp 4
+    11d2:	54          	storesp 16
+    11d3:	73          	loadsp 12
+    11d4:	88          	im 8
+    11d5:	b0          	im 48
+    11d6:	38          	neqbranch
+
+000011d7 <.LM382>:
+    11d7:	74          	loadsp 16
+    11d8:	83          	im 3
+    11d9:	2a          	lshiftright
+    11da:	81          	im 1
+    11db:	32          	xor
+    11dc:	70          	loadsp 0
+    11dd:	81          	im 1
+    11de:	06          	and
+    11df:	51          	storesp 4
+    11e0:	54          	storesp 16
+    11e1:	73          	loadsp 12
+    11e2:	88          	im 8
+    11e3:	91          	im 17
+    11e4:	38          	neqbranch
+
+000011e5 <.LM383>:
+    11e5:	74          	loadsp 16
+    11e6:	82          	im 2
+    11e7:	2a          	lshiftright
+    11e8:	81          	im 1
+    11e9:	32          	xor
+    11ea:	70          	loadsp 0
+    11eb:	81          	im 1
+    11ec:	06          	and
+    11ed:	51          	storesp 4
+    11ee:	54          	storesp 16
+    11ef:	73          	loadsp 12
+    11f0:	87          	im 7
+    11f1:	f2          	im -14
+    11f2:	38          	neqbranch
+
+000011f3 <.LM384>:
+    11f3:	80          	im 0
+    11f4:	fb          	im -5
+    11f5:	bc          	im 60
+    11f6:	08          	load
+    11f7:	70          	loadsp 0
+    11f8:	33          	loadb
+    11f9:	70          	loadsp 0
+    11fa:	81          	im 1
+    11fb:	ff          	im -1
+    11fc:	06          	and
+    11fd:	51          	storesp 4
+    11fe:	55          	storesp 20
+    11ff:	55          	storesp 20
+    1200:	73          	loadsp 12
+    1201:	80          	im 0
+    1202:	2e          	eq
+    1203:	87          	im 7
+    1204:	c1          	im -63
+    1205:	38          	neqbranch
+
+00001206 <.LM385>:
+    1206:	80          	im 0
+    1207:	c1          	im -63
+    1208:	bb          	im 59
+    1209:	3f          	callpcrel
+
+0000120a <.LM386>:
+    120a:	80          	im 0
+    120b:	fb          	im -5
+    120c:	c8          	im -56
+    120d:	08          	load
+    120e:	80          	im 0
+    120f:	fb          	im -5
+    1210:	d8          	im -40
+    1211:	08          	load
+    1212:	55          	storesp 20
+    1213:	55          	storesp 20
+    1214:	74          	loadsp 16
+    1215:	33          	loadb
+    1216:	74          	loadsp 16
+    1217:	34          	storeb
+
+00001218 <.LM387>:
+    1218:	80          	im 0
+    1219:	fb          	im -5
+    121a:	c4          	im -60
+    121b:	08          	load
+    121c:	70          	loadsp 0
+    121d:	33          	loadb
+    121e:	70          	loadsp 0
+    121f:	81          	im 1
+    1220:	ff          	im -1
+    1221:	06          	and
+
+00001222 <.LM388>:
+    1222:	70          	loadsp 0
+    1223:	81          	im 1
+    1224:	2a          	lshiftright
+    1225:	81          	im 1
+    1226:	32          	xor
+    1227:	81          	im 1
+    1228:	06          	and
+    1229:	59          	storesp 36
+    122a:	57          	storesp 28
+    122b:	51          	storesp 4
+    122c:	54          	storesp 16
+    122d:	75          	loadsp 20
+    122e:	80          	im 0
+    122f:	2e          	eq
+    1230:	ff          	im -1
+    1231:	99          	im 25
+    1232:	38          	neqbranch
+
+00001233 <.L388>:
+    1233:	81          	im 1
+    1234:	19          	addsp 36
+    1235:	fd          	im -3
+    1236:	11          	addsp 4
+    1237:	5e          	storesp 56
+    1238:	59          	storesp 36
+
+00001239 <.LM390>:
+    1239:	88          	im 8
+    123a:	79          	loadsp 36
+    123b:	25          	lessthanorequal
+    123c:	fb          	im -5
+    123d:	a9          	im 41
+    123e:	38          	neqbranch
+    123f:	88          	im 8
+    1240:	59          	storesp 36
+    1241:	85          	im 5
+    1242:	5d          	storesp 52
+
+00001243 <.LM391>:
+    1243:	87          	im 7
+    1244:	a9          	im 41
+    1245:	c0          	im -64
+    1246:	51          	storesp 4
+    1247:	e4          	im -28
+    1248:	ea          	im -22
+    1249:	3f          	callpcrel
+
+0000124a <.LM392>:
+    124a:	80          	im 0
+    124b:	c0          	im -64
+    124c:	f7          	im -9
+    124d:	3f          	callpcrel
+
+0000124e <.LM393>:
+    124e:	80          	im 0
+    124f:	58          	storesp 32
+    1250:	fb          	im -5
+    1251:	a2          	im 34
+    1252:	39          	poppcrel
+
+00001253 <.L374>:
+    1253:	76          	loadsp 24
+    1254:	80          	im 0
+    1255:	2e          	eq
+    1256:	87          	im 7
+    1257:	bf          	im 63
+    1258:	38          	neqbranch
+
+00001259 <.LM395>:
+    1259:	75          	loadsp 20
+    125a:	08          	load
+    125b:	77          	loadsp 28
+    125c:	16          	addsp 24
+    125d:	83          	im 3
+    125e:	06          	and
+    125f:	71          	loadsp 4
+    1260:	fc          	im -4
+    1261:	9f          	im 31
+    1262:	ff          	im -1
+    1263:	06          	and
+    1264:	71          	loadsp 4
+    1265:	8c          	im 12
+    1266:	2b          	ashiftleft
+    1267:	07          	or
+
+00001268 <.LM396>:
+    1268:	78          	loadsp 32
+    1269:	0c          	store
+    126a:	56          	storesp 24
+    126b:	54          	storesp 16
+
+0000126c <.L361>:
+    126c:	80          	im 0
+
+0000126d <.LM398>:
+    126d:	70          	loadsp 0
+    126e:	58          	storesp 32
+    126f:	5c          	storesp 48
+
+00001270 <.L391>:
+    1270:	87          	im 7
+    1271:	a9          	im 41
+    1272:	c0          	im -64
+    1273:	51          	storesp 4
+    1274:	e4          	im -28
+    1275:	bd          	im 61
+    1276:	3f          	callpcrel
+
+00001277 <.LM400>:
+    1277:	80          	im 0
+    1278:	c0          	im -64
+    1279:	ca          	im -54
+    127a:	3f          	callpcrel
+
+0000127b <.LM401>:
+    127b:	80          	im 0
+    127c:	58          	storesp 32
+    127d:	fa          	im -6
+    127e:	f5          	im -11
+    127f:	39          	poppcrel
+
+00001280 <.L387>:
+    1280:	7b          	loadsp 44
+    1281:	81          	im 1
+    1282:	2e          	eq
+    1283:	09          	not
+    1284:	81          	im 1
+    1285:	06          	and
+    1286:	fe          	im -2
+    1287:	a6          	im 38
+    1288:	38          	neqbranch
+
+00001289 <.L231>:
+    1289:	80          	im 0
+    128a:	c0          	im -64
+    128b:	58          	storesp 32
+
+0000128c <.L303>:
+    128c:	86          	im 6
+    128d:	b8          	im 56
+    128e:	80          	im 0
+    128f:	18          	addsp 32
+    1290:	81          	im 1
+    1291:	9f          	im 31
+    1292:	e0          	im -32
+    1293:	80          	im 0
+    1294:	19          	addsp 36
+    1295:	55          	storesp 20
+    1296:	55          	storesp 20
+    1297:	73          	loadsp 12
+    1298:	33          	loadb
+    1299:	75          	loadsp 20
+    129a:	34          	storeb
+
+0000129b <.LM405>:
+    129b:	81          	im 1
+    129c:	18          	addsp 32
+    129d:	58          	storesp 32
+    129e:	77          	loadsp 28
+    129f:	88          	im 8
+    12a0:	80          	im 0
+    12a1:	2e          	eq
+    12a2:	09          	not
+    12a3:	81          	im 1
+    12a4:	06          	and
+    12a5:	e6          	im -26
+    12a6:	38          	neqbranch
+
+000012a7 <.LM406>:
+    12a7:	83          	im 3
+    12a8:	a0          	im 32
+    12a9:	80          	im 0
+    12aa:	58          	storesp 32
+
+000012ab <.L307>:
+    12ab:	84          	im 4
+    12ac:	80          	im 0
+    12ad:	80          	im 0
+    12ae:	18          	addsp 32
+    12af:	81          	im 1
+    12b0:	9c          	im 28
+    12b1:	80          	im 0
+    12b2:	80          	im 0
+    12b3:	19          	addsp 36
+    12b4:	55          	storesp 20
+    12b5:	55          	storesp 20
+    12b6:	73          	loadsp 12
+    12b7:	33          	loadb
+    12b8:	75          	loadsp 20
+    12b9:	34          	storeb
+
+000012ba <.LM408>:
+    12ba:	81          	im 1
+    12bb:	18          	addsp 32
+    12bc:	58          	storesp 32
+    12bd:	77          	loadsp 28
+    12be:	83          	im 3
+    12bf:	a0          	im 32
+    12c0:	9f          	im 31
+    12c1:	2e          	eq
+    12c2:	09          	not
+    12c3:	81          	im 1
+    12c4:	06          	and
+    12c5:	e5          	im -27
+    12c6:	38          	neqbranch
+
+000012c7 <.LM409>:
+    12c7:	83          	im 3
+    12c8:	a4          	im 36
+    12c9:	80          	im 0
+    12ca:	58          	storesp 32
+
+000012cb <.L311>:
+    12cb:	84          	im 4
+    12cc:	80          	im 0
+    12cd:	80          	im 0
+    12ce:	18          	addsp 32
+    12cf:	81          	im 1
+    12d0:	9c          	im 28
+    12d1:	80          	im 0
+    12d2:	80          	im 0
+    12d3:	19          	addsp 36
+    12d4:	55          	storesp 20
+    12d5:	55          	storesp 20
+    12d6:	73          	loadsp 12
+    12d7:	33          	loadb
+    12d8:	75          	loadsp 20
+    12d9:	34          	storeb
+
+000012da <.LM411>:
+    12da:	81          	im 1
+    12db:	18          	addsp 32
+    12dc:	58          	storesp 32
+    12dd:	77          	loadsp 28
+    12de:	83          	im 3
+    12df:	a4          	im 36
+    12e0:	9f          	im 31
+    12e1:	2e          	eq
+    12e2:	09          	not
+    12e3:	81          	im 1
+    12e4:	06          	and
+    12e5:	e5          	im -27
+    12e6:	38          	neqbranch
+
+000012e7 <.LM412>:
+    12e7:	83          	im 3
+    12e8:	a8          	im 40
+    12e9:	80          	im 0
+    12ea:	58          	storesp 32
+
+000012eb <.L315>:
+    12eb:	84          	im 4
+    12ec:	80          	im 0
+    12ed:	80          	im 0
+    12ee:	18          	addsp 32
+    12ef:	81          	im 1
+    12f0:	9c          	im 28
+    12f1:	80          	im 0
+    12f2:	80          	im 0
+    12f3:	19          	addsp 36
+    12f4:	55          	storesp 20
+    12f5:	55          	storesp 20
+    12f6:	73          	loadsp 12
+    12f7:	33          	loadb
+    12f8:	75          	loadsp 20
+    12f9:	34          	storeb
+
+000012fa <.LM414>:
+    12fa:	81          	im 1
+    12fb:	18          	addsp 32
+    12fc:	58          	storesp 32
+    12fd:	77          	loadsp 28
+    12fe:	83          	im 3
+    12ff:	a8          	im 40
+    1300:	8f          	im 15
+    1301:	2e          	eq
+    1302:	09          	not
+    1303:	81          	im 1
+    1304:	06          	and
+    1305:	e5          	im -27
+    1306:	38          	neqbranch
+
+00001307 <.LM415>:
+    1307:	80          	im 0
+    1308:	fb          	im -5
+    1309:	c0          	im -64
+    130a:	08          	load
+    130b:	54          	storesp 16
+    130c:	79          	loadsp 36
+    130d:	74          	loadsp 16
+    130e:	34          	storeb
+
+0000130f <.LM416>:
+    130f:	83          	im 3
+    1310:	e0          	im -32
+    1311:	ac          	im 44
+    1312:	08          	load
+    1313:	51          	storesp 4
+    1314:	bf          	im 63
+    1315:	c7          	im -57
+    1316:	3f          	callpcrel
+
+00001317 <.LM417>:
+    1317:	7a          	loadsp 40
+    1318:	80          	im 0
+    1319:	2e          	eq
+    131a:	a7          	im 39
+    131b:	38          	neqbranch
+
+0000131c <.LM418>:
+    131c:	0b          	nop
+    131d:	0b          	nop
+    131e:	80          	im 0
+    131f:	f6          	im -10
+    1320:	98          	im 24
+    1321:	51          	storesp 4
+    1322:	80          	im 0
+    1323:	c1          	im -63
+    1324:	c8          	im -56
+    1325:	3f          	callpcrel
+
+00001326 <.LM419>:
+    1326:	9e          	im 30
+    1327:	c2          	im -62
+    1328:	a0          	im 32
+    1329:	51          	storesp 4
+    132a:	e3          	im -29
+    132b:	87          	im 7
+    132c:	3f          	callpcrel
+
+0000132d <.LM420>:
+    132d:	80          	im 0
+    132e:	51          	storesp 4
+    132f:	e6          	im -26
+    1330:	b9          	im 57
+    1331:	3f          	callpcrel
+
+00001332 <.LM421>:
+    1332:	80          	im 0
+    1333:	fb          	im -5
+    1334:	e4          	im -28
+    1335:	08          	load
+    1336:	54          	storesp 16
+    1337:	80          	im 0
+    1338:	74          	loadsp 16
+    1339:	34          	storeb
+
+0000133a <.LM422>:
+    133a:	e5          	im -27
+    133b:	b4          	im 52
+    133c:	3f          	callpcrel
+
+0000133d <.LM423>:
+    133d:	81          	im 1
+    133e:	51          	storesp 4
+    133f:	e6          	im -26
+    1340:	a9          	im 41
+    1341:	3f          	callpcrel
+
+00001342 <.L316>:
+    1342:	80          	im 0
+    1343:	51          	storesp 4
+    1344:	e6          	im -26
+    1345:	c8          	im -56
+    1346:	3f          	callpcrel
+    1347:	80          	im 0
+    1348:	fc          	im -4
+    1349:	b8          	im 56
+    134a:	08          	load
+    134b:	55          	storesp 20
+    134c:	f4          	im -12
+    134d:	a6          	im 38
+    134e:	39          	poppcrel
+
+0000134f <.L379>:
+    134f:	81          	im 1
+    1350:	80          	im 0
+    1351:	51          	storesp 4
+    1352:	80          	im 0
+    1353:	c1          	im -63
+    1354:	92          	im 18
+    1355:	3f          	callpcrel
+
+00001356 <.LM426>:
+    1356:	83          	im 3
+    1357:	e2          	im -30
+    1358:	c8          	im -56
+    1359:	51          	storesp 4
+    135a:	80          	im 0
+    135b:	c1          	im -63
+    135c:	90          	im 16
+    135d:	3f          	callpcrel
+
+0000135e <.LM427>:
+    135e:	0b          	nop
+    135f:	0b          	nop
+    1360:	80          	im 0
+    1361:	f7          	im -9
+    1362:	8c          	im 12
+    1363:	51          	storesp 4
+    1364:	80          	im 0
+    1365:	c1          	im -63
+    1366:	86          	im 6
+    1367:	3f          	callpcrel
+
+00001368 <.LM428>:
+    1368:	78          	loadsp 32
+    1369:	86          	im 6
+    136a:	2e          	eq
+    136b:	09          	not
+    136c:	81          	im 1
+    136d:	06          	and
+    136e:	fb          	im -5
+    136f:	f3          	im -13
+    1370:	38          	neqbranch
+    1371:	81          	im 1
+    1372:	a2          	im 34
+    1373:	39          	poppcrel
+
+00001374 <.L378>:
+    1374:	81          	im 1
+    1375:	80          	im 0
+    1376:	51          	storesp 4
+    1377:	80          	im 0
+    1378:	c0          	im -64
+    1379:	ed          	im -19
+    137a:	3f          	callpcrel
+
+0000137b <.LM430>:
+    137b:	83          	im 3
+    137c:	e3          	im -29
+    137d:	d8          	im -40
+    137e:	51          	storesp 4
+    137f:	80          	im 0
+    1380:	c0          	im -64
+    1381:	eb          	im -21
+    1382:	3f          	callpcrel
+
+00001383 <.LM431>:
+    1383:	0b          	nop
+    1384:	0b          	nop
+    1385:	80          	im 0
+    1386:	f7          	im -9
+    1387:	84          	im 4
+    1388:	51          	storesp 4
+    1389:	80          	im 0
+    138a:	c0          	im -64
+    138b:	e1          	im -31
+    138c:	3f          	callpcrel
+
+0000138d <.LM432>:
+    138d:	78          	loadsp 32
+    138e:	85          	im 5
+    138f:	2e          	eq
+    1390:	09          	not
+    1391:	81          	im 1
+    1392:	06          	and
+    1393:	fb          	im -5
+    1394:	b6          	im 54
+    1395:	38          	neqbranch
+    1396:	ff          	im -1
+    1397:	b7          	im 55
+    1398:	39          	poppcrel
+
+00001399 <.L242>:
+    1399:	0b          	nop
+    139a:	0b          	nop
+    139b:	80          	im 0
+    139c:	f7          	im -9
+    139d:	a4          	im 36
+    139e:	51          	storesp 4
+
+0000139f <.LM434>:
+    139f:	80          	im 0
+    13a0:	c0          	im -64
+    13a1:	cb          	im -53
+    13a2:	3f          	callpcrel
+
+000013a3 <.LM435>:
+    13a3:	0b          	nop
+    13a4:	0b          	nop
+    13a5:	80          	im 0
+    13a6:	f9          	im -7
+    13a7:	c4          	im -60
+    13a8:	51          	storesp 4
+    13a9:	80          	im 0
+    13aa:	c0          	im -64
+    13ab:	c1          	im -63
+    13ac:	3f          	callpcrel
+
+000013ad <.LM436>:
+    13ad:	0b          	nop
+    13ae:	0b          	nop
+    13af:	80          	im 0
+    13b0:	f6          	im -10
+    13b1:	dc          	im -36
+    13b2:	51          	storesp 4
+    13b3:	80          	im 0
+    13b4:	c0          	im -64
+    13b5:	b7          	im 55
+    13b6:	3f          	callpcrel
+
+000013b7 <.LM437>:
+    13b7:	80          	im 0
+    13b8:	fc          	im -4
+    13b9:	c4          	im -60
+    13ba:	08          	load
+    13bb:	70          	loadsp 0
+    13bc:	08          	load
+    13bd:	70          	loadsp 0
+    13be:	8c          	im 12
+    13bf:	2c          	ashiftright
+    13c0:	8f          	im 15
+    13c1:	06          	and
+    13c2:	57          	storesp 28
+    13c3:	55          	storesp 20
+    13c4:	56          	storesp 24
+
+000013c5 <.LM438>:
+    13c5:	78          	loadsp 32
+    13c6:	81          	im 1
+    13c7:	2e          	eq
+    13c8:	09          	not
+    13c9:	81          	im 1
+    13ca:	06          	and
+    13cb:	f9          	im -7
+    13cc:	e5          	im -27
+    13cd:	38          	neqbranch
+    13ce:	fd          	im -3
+    13cf:	83          	im 3
+    13d0:	39          	poppcrel
+
+000013d1 <.L377>:
+    13d1:	81          	im 1
+    13d2:	80          	im 0
+    13d3:	51          	storesp 4
+    13d4:	80          	im 0
+    13d5:	c0          	im -64
+    13d6:	90          	im 16
+    13d7:	3f          	callpcrel
+
+000013d8 <.LM440>:
+    13d8:	83          	im 3
+    13d9:	e3          	im -29
+    13da:	98          	im 24
+    13db:	51          	storesp 4
+    13dc:	80          	im 0
+    13dd:	c0          	im -64
+    13de:	8e          	im 14
+    13df:	3f          	callpcrel
+
+000013e0 <.LM441>:
+    13e0:	0b          	nop
+    13e1:	0b          	nop
+    13e2:	80          	im 0
+    13e3:	f6          	im -10
+    13e4:	fc          	im -4
+    13e5:	51          	storesp 4
+    13e6:	80          	im 0
+    13e7:	c0          	im -64
+    13e8:	84          	im 4
+    13e9:	3f          	callpcrel
+
+000013ea <.LM442>:
+    13ea:	78          	loadsp 32
+    13eb:	84          	im 4
+    13ec:	2e          	eq
+    13ed:	09          	not
+    13ee:	81          	im 1
+    13ef:	06          	and
+    13f0:	fa          	im -6
+    13f1:	c1          	im -63
+    13f2:	38          	neqbranch
+    13f3:	fe          	im -2
+    13f4:	ff          	im -1
+    13f5:	39          	poppcrel
+
+000013f6 <.L376>:
+    13f6:	76          	loadsp 24
+    13f7:	80          	im 0
+    13f8:	2e          	eq
+    13f9:	82          	im 2
+    13fa:	fa          	im -6
+    13fb:	38          	neqbranch
+
+000013fc <.LM444>:
+    13fc:	76          	loadsp 24
+    13fd:	15          	addsp 20
+
+000013fe <.LM445>:
+    13fe:	70          	loadsp 0
+    13ff:	09          	not
+    1400:	70          	loadsp 0
+    1401:	9f          	im 31
+    1402:	2c          	ashiftright
+    1403:	72          	loadsp 8
+    1404:	06          	and
+
+00001405 <.LM446>:
+    1405:	78          	loadsp 32
+    1406:	08          	load
+    1407:	52          	storesp 8
+    1408:	bf          	im 63
+    1409:	06          	and
+    140a:	71          	loadsp 4
+    140b:	c0          	im -64
+    140c:	06          	and
+    140d:	07          	or
+    140e:	78          	loadsp 32
+    140f:	0c          	store
+    1410:	55          	storesp 20
+    1411:	55          	storesp 20
+    1412:	fc          	im -4
+    1413:	d8          	im -40
+    1414:	39          	poppcrel
+
+00001415 <.L380>:
+    1415:	81          	im 1
+    1416:	80          	im 0
+    1417:	51          	storesp 4
+    1418:	bf          	im 63
+    1419:	cd          	im -51
+    141a:	3f          	callpcrel
+    141b:	fa          	im -6
+    141c:	c6          	im -58
+    141d:	39          	poppcrel
+
+0000141e <.L375>:
+    141e:	74          	loadsp 16
+    141f:	f9          	im -7
+    1420:	a9          	im 41
+    1421:	38          	neqbranch
+
+00001422 <.LM449>:
+    1422:	0b          	nop
+    1423:	0b          	nop
+    1424:	80          	im 0
+    1425:	f7          	im -9
+    1426:	b4          	im 52
+    1427:	51          	storesp 4
+
+00001428 <.LM450>:
+    1428:	bf          	im 63
+    1429:	c3          	im -61
+    142a:	3f          	callpcrel
+
+0000142b <.LM451>:
+    142b:	0b          	nop
+    142c:	0b          	nop
+    142d:	80          	im 0
+    142e:	f9          	im -7
+    142f:	c4          	im -60
+    1430:	51          	storesp 4
+    1431:	bf          	im 63
+    1432:	ba          	im 58
+    1433:	3f          	callpcrel
+
+00001434 <.LM452>:
+    1434:	0b          	nop
+    1435:	0b          	nop
+    1436:	80          	im 0
+    1437:	f6          	im -10
+    1438:	e8          	im -24
+    1439:	51          	storesp 4
+    143a:	bf          	im 63
+    143b:	b1          	im 49
+    143c:	3f          	callpcrel
+
+0000143d <.LM453>:
+    143d:	80          	im 0
+    143e:	fc          	im -4
+    143f:	c4          	im -60
+    1440:	08          	load
+    1441:	70          	loadsp 0
+    1442:	08          	load
+    1443:	bf          	im 63
+    1444:	06          	and
+    1445:	56          	storesp 24
+    1446:	56          	storesp 24
+
+00001447 <.LM454>:
+    1447:	78          	loadsp 32
+    1448:	82          	im 2
+    1449:	2e          	eq
+    144a:	09          	not
+    144b:	81          	im 1
+    144c:	06          	and
+    144d:	f9          	im -7
+    144e:	a9          	im 41
+    144f:	38          	neqbranch
+    1450:	ff          	im -1
+    1451:	a4          	im 36
+    1452:	39          	poppcrel
+
+00001453 <.L249>:
+    1453:	0b          	nop
+    1454:	0b          	nop
+    1455:	80          	im 0
+    1456:	f7          	im -9
+    1457:	c4          	im -60
+    1458:	51          	storesp 4
+
+00001459 <.LM456>:
+    1459:	bf          	im 63
+    145a:	92          	im 18
+    145b:	3f          	callpcrel
+
+0000145c <.LM457>:
+    145c:	0b          	nop
+    145d:	0b          	nop
+    145e:	80          	im 0
+    145f:	f9          	im -7
+    1460:	c4          	im -60
+    1461:	51          	storesp 4
+    1462:	bf          	im 63
+    1463:	89          	im 9
+    1464:	3f          	callpcrel
+
+00001465 <.LM458>:
+    1465:	0b          	nop
+    1466:	0b          	nop
+    1467:	80          	im 0
+    1468:	f6          	im -10
+    1469:	e8          	im -24
+    146a:	51          	storesp 4
+    146b:	bf          	im 63
+    146c:	80          	im 0
+    146d:	3f          	callpcrel
+
+0000146e <.LM459>:
+    146e:	80          	im 0
+    146f:	fc          	im -4
+    1470:	c4          	im -60
+    1471:	08          	load
+    1472:	70          	loadsp 0
+    1473:	08          	load
+    1474:	bf          	im 63
+    1475:	06          	and
+    1476:	56          	storesp 24
+    1477:	56          	storesp 24
+
+00001478 <.LM460>:
+    1478:	78          	loadsp 32
+    1479:	82          	im 2
+    147a:	2e          	eq
+    147b:	09          	not
+    147c:	81          	im 1
+    147d:	06          	and
+    147e:	f8          	im -8
+    147f:	f8          	im -8
+    1480:	38          	neqbranch
+    1481:	fe          	im -2
+    1482:	f3          	im -13
+    1483:	39          	poppcrel
+
+00001484 <.L241>:
+    1484:	0b          	nop
+    1485:	0b          	nop
+    1486:	80          	im 0
+    1487:	f7          	im -9
+    1488:	e0          	im -32
+    1489:	51          	storesp 4
+
+0000148a <.LM462>:
+    148a:	be          	im 62
+    148b:	e1          	im -31
+    148c:	3f          	callpcrel
+
+0000148d <.LM463>:
+    148d:	0b          	nop
+    148e:	0b          	nop
+    148f:	80          	im 0
+    1490:	f9          	im -7
+    1491:	c4          	im -60
+    1492:	51          	storesp 4
+    1493:	be          	im 62
+    1494:	d8          	im -40
+    1495:	3f          	callpcrel
+
+00001496 <.LM464>:
+    1496:	0b          	nop
+    1497:	0b          	nop
+    1498:	80          	im 0
+    1499:	f6          	im -10
+    149a:	dc          	im -36
+    149b:	51          	storesp 4
+    149c:	be          	im 62
+    149d:	cf          	im -49
+    149e:	3f          	callpcrel
+
+0000149f <.LM465>:
+    149f:	80          	im 0
+    14a0:	fc          	im -4
+    14a1:	c4          	im -60
+    14a2:	08          	load
+    14a3:	70          	loadsp 0
+    14a4:	08          	load
+    14a5:	70          	loadsp 0
+    14a6:	8c          	im 12
+    14a7:	2c          	ashiftright
+    14a8:	8f          	im 15
+    14a9:	06          	and
+    14aa:	57          	storesp 28
+    14ab:	55          	storesp 20
+    14ac:	56          	storesp 24
+
+000014ad <.LM466>:
+    14ad:	78          	loadsp 32
+    14ae:	81          	im 1
+    14af:	2e          	eq
+    14b0:	09          	not
+    14b1:	81          	im 1
+    14b2:	06          	and
+    14b3:	f7          	im -9
+    14b4:	fd          	im -3
+    14b5:	38          	neqbranch
+    14b6:	fb          	im -5
+    14b7:	9b          	im 27
+    14b8:	39          	poppcrel
+
+000014b9 <.L385>:
+    14b9:	7b          	loadsp 44
+    14ba:	81          	im 1
+    14bb:	2e          	eq
+    14bc:	09          	not
+    14bd:	81          	im 1
+    14be:	06          	and
+    14bf:	f9          	im -7
+    14c0:	dd          	im -35
+    14c1:	38          	neqbranch
+
+000014c2 <.LM468>:
+    14c2:	7b          	loadsp 44
+    14c3:	5b          	storesp 44
+    14c4:	fb          	im -5
+    14c5:	c3          	im -61
+    14c6:	39          	poppcrel
+
+000014c7 <.L373>:
+    14c7:	74          	loadsp 16
+    14c8:	f7          	im -9
+    14c9:	b6          	im 54
+    14ca:	38          	neqbranch
+
+000014cb <.LM470>:
+    14cb:	0b          	nop
+    14cc:	0b          	nop
+    14cd:	80          	im 0
+    14ce:	f7          	im -9
+    14cf:	f4          	im -12
+    14d0:	51          	storesp 4
+
+000014d1 <.LM471>:
+    14d1:	be          	im 62
+    14d2:	9a          	im 26
+    14d3:	3f          	callpcrel
+
+000014d4 <.LM472>:
+    14d4:	0b          	nop
+    14d5:	0b          	nop
+    14d6:	80          	im 0
+    14d7:	f9          	im -7
+    14d8:	c4          	im -60
+    14d9:	51          	storesp 4
+    14da:	be          	im 62
+    14db:	91          	im 17
+    14dc:	3f          	callpcrel
+
+000014dd <.LM473>:
+    14dd:	0b          	nop
+    14de:	0b          	nop
+    14df:	80          	im 0
+    14e0:	f6          	im -10
+    14e1:	dc          	im -36
+    14e2:	51          	storesp 4
+    14e3:	be          	im 62
+    14e4:	88          	im 8
+    14e5:	3f          	callpcrel
+
+000014e6 <.LM474>:
+    14e6:	80          	im 0
+    14e7:	fc          	im -4
+    14e8:	c4          	im -60
+    14e9:	08          	load
+    14ea:	70          	loadsp 0
+    14eb:	08          	load
+    14ec:	70          	loadsp 0
+    14ed:	8c          	im 12
+    14ee:	2c          	ashiftright
+    14ef:	8f          	im 15
+    14f0:	06          	and
+    14f1:	57          	storesp 28
+    14f2:	55          	storesp 20
+    14f3:	56          	storesp 24
+
+000014f4 <.LM475>:
+    14f4:	78          	loadsp 32
+    14f5:	81          	im 1
+    14f6:	2e          	eq
+    14f7:	09          	not
+    14f8:	81          	im 1
+    14f9:	06          	and
+    14fa:	f7          	im -9
+    14fb:	b6          	im 54
+    14fc:	38          	neqbranch
+    14fd:	fa          	im -6
+    14fe:	d4          	im -44
+    14ff:	39          	poppcrel
+
+00001500 <.L240>:
+    1500:	0b          	nop
+    1501:	0b          	nop
+    1502:	80          	im 0
+    1503:	f7          	im -9
+    1504:	fc          	im -4
+    1505:	51          	storesp 4
+
+00001506 <.LM477>:
+    1506:	bd          	im 61
+    1507:	e5          	im -27
+    1508:	3f          	callpcrel
+
+00001509 <.LM478>:
+    1509:	0b          	nop
+    150a:	0b          	nop
+    150b:	80          	im 0
+    150c:	f9          	im -7
+    150d:	c4          	im -60
+    150e:	51          	storesp 4
+    150f:	bd          	im 61
+    1510:	dc          	im -36
+    1511:	3f          	callpcrel
+
+00001512 <.LM479>:
+    1512:	0b          	nop
+    1513:	0b          	nop
+    1514:	80          	im 0
+    1515:	f6          	im -10
+    1516:	dc          	im -36
+    1517:	51          	storesp 4
+    1518:	bd          	im 61
+    1519:	d3          	im -45
+    151a:	3f          	callpcrel
+
+0000151b <.LM480>:
+    151b:	80          	im 0
+    151c:	fc          	im -4
+    151d:	c4          	im -60
+    151e:	08          	load
+    151f:	70          	loadsp 0
+    1520:	08          	load
+    1521:	70          	loadsp 0
+    1522:	8c          	im 12
+    1523:	2c          	ashiftright
+    1524:	8f          	im 15
+    1525:	06          	and
+    1526:	57          	storesp 28
+    1527:	55          	storesp 20
+    1528:	56          	storesp 24
+
+00001529 <.LM481>:
+    1529:	78          	loadsp 32
+    152a:	81          	im 1
+    152b:	2e          	eq
+    152c:	09          	not
+    152d:	81          	im 1
+    152e:	06          	and
+    152f:	f7          	im -9
+    1530:	81          	im 1
+    1531:	38          	neqbranch
+    1532:	fa          	im -6
+    1533:	9f          	im 31
+    1534:	39          	poppcrel
+
+00001535 <.L381>:
+    1535:	78          	loadsp 32
+    1536:	84          	im 4
+    1537:	2e          	eq
+    1538:	b6          	im 54
+    1539:	38          	neqbranch
+    153a:	78          	loadsp 32
+    153b:	84          	im 4
+    153c:	24          	lessthan
+    153d:	94          	im 20
+    153e:	38          	neqbranch
+    153f:	78          	loadsp 32
+    1540:	83          	im 3
+    1541:	2e          	eq
+    1542:	83          	im 3
+    1543:	d9          	im -39
+    1544:	38          	neqbranch
+
+00001545 <.L263>:
+    1545:	fe          	im -2
+    1546:	19          	addsp 36
+    1547:	83          	im 3
+    1548:	e0          	im -32
+    1549:	b4          	im 52
+    154a:	0c          	store
+
+0000154b <.L392>:
+    154b:	80          	im 0
+
+0000154c <.LM485>:
+    154c:	70          	loadsp 0
+    154d:	58          	storesp 32
+    154e:	5c          	storesp 48
+    154f:	fa          	im -6
+    1550:	9f          	im 31
+    1551:	39          	poppcrel
+
+00001552 <.L268>:
+    1552:	78          	loadsp 32
+    1553:	85          	im 5
+    1554:	2e          	eq
+    1555:	83          	im 3
+    1556:	cd          	im -51
+    1557:	38          	neqbranch
+    1558:	78          	loadsp 32
+    1559:	86          	im 6
+    155a:	2e          	eq
+    155b:	09          	not
+    155c:	81          	im 1
+    155d:	06          	and
+    155e:	e6          	im -26
+    155f:	38          	neqbranch
+
+00001560 <.LM487>:
+    1560:	83          	im 3
+    1561:	e0          	im -32
+    1562:	b8          	im 56
+    1563:	51          	storesp 4
+
+00001564 <.L364>:
+    1564:	ea          	im -22
+    1565:	fe          	im -2
+    1566:	3f          	callpcrel
+
+00001567 <.LM488>:
+    1567:	fe          	im -2
+    1568:	19          	addsp 36
+    1569:	83          	im 3
+    156a:	e0          	im -32
+    156b:	b4          	im 52
+    156c:	0c          	store
+    156d:	dd          	im -35
+    156e:	39          	poppcrel
+
+0000156f <.L265>:
+    156f:	83          	im 3
+    1570:	e3          	im -29
+    1571:	d8          	im -40
+    1572:	51          	storesp 4
+    1573:	f0          	im -16
+    1574:	39          	poppcrel
+
+00001575 <.L255>:
+    1575:	81          	im 1
+    1576:	80          	im 0
+    1577:	51          	storesp 4
+    1578:	bc          	im 60
+    1579:	ed          	im -19
+    157a:	3f          	callpcrel
+
+0000157b <.LM491>:
+    157b:	81          	im 1
+    157c:	15          	addsp 20
+    157d:	70          	loadsp 0
+    157e:	83          	im 3
+    157f:	c1          	im -63
+    1580:	9c          	im 28
+    1581:	35          	div
+    1582:	70          	loadsp 0
+    1583:	83          	im 3
+    1584:	ff          	im -1
+    1585:	ff          	im -1
+    1586:	06          	and
+    1587:	53          	storesp 12
+    1588:	51          	storesp 4
+    1589:	54          	storesp 16
+    158a:	bd          	im 61
+    158b:	f0          	im -16
+    158c:	3f          	callpcrel
+
+0000158d <.LM492>:
+    158d:	0b          	nop
+    158e:	0b          	nop
+    158f:	80          	im 0
+    1590:	f6          	im -10
+    1591:	f0          	im -16
+    1592:	51          	storesp 4
+    1593:	bc          	im 60
+    1594:	d8          	im -40
+    1595:	3f          	callpcrel
+
+00001596 <.LM493>:
+    1596:	78          	loadsp 32
+    1597:	83          	im 3
+    1598:	2e          	eq
+    1599:	09          	not
+    159a:	81          	im 1
+    159b:	06          	and
+    159c:	f6          	im -10
+    159d:	fd          	im -3
+    159e:	38          	neqbranch
+    159f:	fc          	im -4
+    15a0:	b0          	im 48
+    15a1:	39          	poppcrel
+
+000015a2 <.L384>:
+    15a2:	81          	im 1
+    15a3:	80          	im 0
+    15a4:	51          	storesp 4
+    15a5:	bc          	im 60
+    15a6:	c0          	im -64
+    15a7:	3f          	callpcrel
+    15a8:	f7          	im -9
+    15a9:	de          	im -34
+    15aa:	39          	poppcrel
+
+000015ab <.L386>:
+    15ab:	81          	im 1
+    15ac:	80          	im 0
+    15ad:	51          	storesp 4
+    15ae:	bc          	im 60
+    15af:	b7          	im 55
+    15b0:	3f          	callpcrel
+
+000015b1 <.LM496>:
+    15b1:	0b          	nop
+    15b2:	0b          	nop
+    15b3:	80          	im 0
+    15b4:	f7          	im -9
+    15b5:	9c          	im 28
+    15b6:	51          	storesp 4
+    15b7:	bc          	im 60
+    15b8:	b4          	im 52
+    15b9:	3f          	callpcrel
+
+000015ba <.LM497>:
+    15ba:	78          	loadsp 32
+    15bb:	88          	im 8
+    15bc:	2e          	eq
+    15bd:	09          	not
+    15be:	81          	im 1
+    15bf:	06          	and
+    15c0:	f7          	im -9
+    15c1:	ec          	im -20
+    15c2:	38          	neqbranch
+    15c3:	f9          	im -7
+    15c4:	bb          	im 59
+    15c5:	39          	poppcrel
+
+000015c6 <.L390>:
+    15c6:	81          	im 1
+    15c7:	5c          	storesp 48
+
+000015c8 <.L298>:
+    15c8:	74          	loadsp 16
+    15c9:	33          	loadb
+    15ca:	70          	loadsp 0
+    15cb:	81          	im 1
+    15cc:	ff          	im -1
+    15cd:	06          	and
+    15ce:	51          	storesp 4
+    15cf:	54          	storesp 16
+    15d0:	73          	loadsp 12
+    15d1:	f4          	im -12
+    15d2:	94          	im 20
+    15d3:	38          	neqbranch
+    15d4:	74          	loadsp 16
+    15d5:	33          	loadb
+    15d6:	70          	loadsp 0
+    15d7:	81          	im 1
+    15d8:	ff          	im -1
+    15d9:	06          	and
+    15da:	51          	storesp 4
+    15db:	54          	storesp 16
+    15dc:	73          	loadsp 12
+    15dd:	80          	im 0
+    15de:	2e          	eq
+    15df:	e8          	im -24
+    15e0:	38          	neqbranch
+    15e1:	f4          	im -12
+    15e2:	84          	im 4
+    15e3:	39          	poppcrel
+
+000015e4 <.L356>:
+    15e4:	ff          	im -1
+    15e5:	57          	storesp 28
+
+000015e6 <.LM501>:
+    15e6:	87          	im 7
+    15e7:	a9          	im 41
+    15e8:	c0          	im -64
+    15e9:	51          	storesp 4
+    15ea:	dd          	im -35
+    15eb:	c7          	im -57
+    15ec:	3f          	callpcrel
+
+000015ed <.LM502>:
+    15ed:	b9          	im 57
+    15ee:	d5          	im -43
+    15ef:	3f          	callpcrel
+
+000015f0 <.LM503>:
+    15f0:	80          	im 0
+    15f1:	58          	storesp 32
+    15f2:	f4          	im -12
+    15f3:	80          	im 0
+    15f4:	39          	poppcrel
+
+000015f5 <.L355>:
+    15f5:	81          	im 1
+    15f6:	57          	storesp 28
+
+000015f7 <.LM505>:
+    15f7:	87          	im 7
+    15f8:	a9          	im 41
+    15f9:	c0          	im -64
+    15fa:	51          	storesp 4
+    15fb:	dd          	im -35
+    15fc:	b6          	im 54
+    15fd:	3f          	callpcrel
+
+000015fe <.LM506>:
+    15fe:	b9          	im 57
+    15ff:	c4          	im -60
+    1600:	3f          	callpcrel
+
+00001601 <.LM507>:
+    1601:	80          	im 0
+    1602:	58          	storesp 32
+    1603:	f3          	im -13
+    1604:	ef          	im -17
+    1605:	39          	poppcrel
+
+00001606 <.L389>:
+    1606:	ff          	im -1
+    1607:	19          	addsp 36
+    1608:	fd          	im -3
+    1609:	11          	addsp 4
+    160a:	5e          	storesp 56
+    160b:	59          	storesp 36
+
+0000160c <.LM509>:
+    160c:	78          	loadsp 32
+    160d:	80          	im 0
+    160e:	25          	lessthanorequal
+    160f:	f3          	im -13
+    1610:	d6          	im -42
+    1611:	38          	neqbranch
+    1612:	75          	loadsp 20
+    1613:	59          	storesp 36
+    1614:	f3          	im -13
+    1615:	cf          	im -49
+    1616:	39          	poppcrel
+
+00001617 <.L246>:
+    1617:	81          	im 1
+    1618:	80          	im 0
+    1619:	51          	storesp 4
+    161a:	bb          	im 59
+    161b:	cb          	im -53
+    161c:	3f          	callpcrel
+    161d:	f5          	im -11
+    161e:	93          	im 19
+    161f:	39          	poppcrel
+
+00001620 <.L383>:
+    1620:	80          	im 0
+    1621:	58          	storesp 32
+
+00001622 <.L278>:
+    1622:	83          	im 3
+    1623:	e3          	im -29
+    1624:	98          	im 24
+    1625:	18          	addsp 32
+    1626:	70          	loadsp 0
+    1627:	33          	loadb
+
+00001628 <.LM513>:
+    1628:	83          	im 3
+    1629:	e3          	im -29
+    162a:	d8          	im -40
+    162b:	1a          	addsp 40
+    162c:	57          	storesp 28
+    162d:	58          	storesp 32
+    162e:	54          	storesp 16
+    162f:	74          	loadsp 16
+    1630:	33          	loadb
+    1631:	74          	loadsp 16
+    1632:	34          	storeb
+
+00001633 <.LM514>:
+    1633:	83          	im 3
+    1634:	e2          	im -30
+    1635:	c8          	im -56
+    1636:	18          	addsp 32
+    1637:	56          	storesp 24
+    1638:	75          	loadsp 20
+    1639:	33          	loadb
+    163a:	75          	loadsp 20
+    163b:	34          	storeb
+
+0000163c <.LM515>:
+    163c:	83          	im 3
+    163d:	e0          	im -32
+    163e:	b8          	im 56
+    163f:	18          	addsp 32
+    1640:	54          	storesp 16
+    1641:	73          	loadsp 12
+    1642:	33          	loadb
+    1643:	76          	loadsp 24
+    1644:	34          	storeb
+
+00001645 <.LM516>:
+    1645:	76          	loadsp 24
+    1646:	74          	loadsp 16
+    1647:	34          	storeb
+
+00001648 <.LM517>:
+    1648:	81          	im 1
+    1649:	18          	addsp 32
+    164a:	58          	storesp 32
+    164b:	77          	loadsp 28
+    164c:	8f          	im 15
+    164d:	2e          	eq
+    164e:	f8          	im -8
+    164f:	9c          	im 28
+    1650:	38          	neqbranch
+
+00001651 <.LM518>:
+    1651:	83          	im 3
+    1652:	e3          	im -29
+    1653:	98          	im 24
+    1654:	18          	addsp 32
+    1655:	70          	loadsp 0
+    1656:	33          	loadb
+
+00001657 <.LM519>:
+    1657:	83          	im 3
+    1658:	e3          	im -29
+    1659:	d8          	im -40
+    165a:	1a          	addsp 40
+    165b:	57          	storesp 28
+    165c:	58          	storesp 32
+    165d:	54          	storesp 16
+    165e:	74          	loadsp 16
+    165f:	33          	loadb
+    1660:	74          	loadsp 16
+    1661:	34          	storeb
+
+00001662 <.LM520>:
+    1662:	83          	im 3
+    1663:	e2          	im -30
+    1664:	c8          	im -56
+    1665:	18          	addsp 32
+    1666:	56          	storesp 24
+    1667:	75          	loadsp 20
+    1668:	33          	loadb
+    1669:	75          	loadsp 20
+    166a:	34          	storeb
+
+0000166b <.LM521>:
+    166b:	83          	im 3
+    166c:	e0          	im -32
+    166d:	b8          	im 56
+    166e:	18          	addsp 32
+    166f:	54          	storesp 16
+    1670:	73          	loadsp 12
+    1671:	33          	loadb
+    1672:	76          	loadsp 24
+    1673:	34          	storeb
+
+00001674 <.LM522>:
+    1674:	76          	loadsp 24
+    1675:	74          	loadsp 16
+    1676:	34          	storeb
+
+00001677 <.LM523>:
+    1677:	81          	im 1
+    1678:	18          	addsp 32
+    1679:	58          	storesp 32
+    167a:	77          	loadsp 28
+    167b:	8f          	im 15
+    167c:	2e          	eq
+    167d:	09          	not
+    167e:	81          	im 1
+    167f:	06          	and
+    1680:	ff          	im -1
+    1681:	a0          	im 32
+    1682:	38          	neqbranch
+    1683:	f7          	im -9
+    1684:	e7          	im -25
+    1685:	39          	poppcrel
+
+00001686 <.L382>:
+    1686:	80          	im 0
+    1687:	58          	storesp 32
+
+00001688 <.L273>:
+    1688:	83          	im 3
+    1689:	e0          	im -32
+    168a:	b8          	im 56
+    168b:	18          	addsp 32
+    168c:	70          	loadsp 0
+    168d:	33          	loadb
+
+0000168e <.LM526>:
+    168e:	83          	im 3
+    168f:	e2          	im -30
+    1690:	c8          	im -56
+    1691:	1a          	addsp 40
+    1692:	57          	storesp 28
+    1693:	58          	storesp 32
+    1694:	54          	storesp 16
+    1695:	74          	loadsp 16
+    1696:	33          	loadb
+    1697:	74          	loadsp 16
+    1698:	34          	storeb
+
+00001699 <.LM527>:
+    1699:	83          	im 3
+    169a:	e3          	im -29
+    169b:	d8          	im -40
+    169c:	18          	addsp 32
+    169d:	56          	storesp 24
+    169e:	75          	loadsp 20
+    169f:	33          	loadb
+    16a0:	75          	loadsp 20
+    16a1:	34          	storeb
+
+000016a2 <.LM528>:
+    16a2:	83          	im 3
+    16a3:	e3          	im -29
+    16a4:	98          	im 24
+    16a5:	18          	addsp 32
+    16a6:	54          	storesp 16
+    16a7:	73          	loadsp 12
+    16a8:	33          	loadb
+    16a9:	76          	loadsp 24
+    16aa:	34          	storeb
+
+000016ab <.LM529>:
+    16ab:	76          	loadsp 24
+    16ac:	74          	loadsp 16
+    16ad:	34          	storeb
+
+000016ae <.LM530>:
+    16ae:	81          	im 1
+    16af:	18          	addsp 32
+    16b0:	58          	storesp 32
+    16b1:	77          	loadsp 28
+    16b2:	8f          	im 15
+    16b3:	2e          	eq
+    16b4:	f7          	im -9
+    16b5:	b6          	im 54
+    16b6:	38          	neqbranch
+
+000016b7 <.LM531>:
+    16b7:	83          	im 3
+    16b8:	e0          	im -32
+    16b9:	b8          	im 56
+    16ba:	18          	addsp 32
+    16bb:	70          	loadsp 0
+    16bc:	33          	loadb
+
+000016bd <.LM532>:
+    16bd:	83          	im 3
+    16be:	e2          	im -30
+    16bf:	c8          	im -56
+    16c0:	1a          	addsp 40
+    16c1:	57          	storesp 28
+    16c2:	58          	storesp 32
+    16c3:	54          	storesp 16
+    16c4:	74          	loadsp 16
+    16c5:	33          	loadb
+    16c6:	74          	loadsp 16
+    16c7:	34          	storeb
+
+000016c8 <.LM533>:
+    16c8:	83          	im 3
+    16c9:	e3          	im -29
+    16ca:	d8          	im -40
+    16cb:	18          	addsp 32
+    16cc:	56          	storesp 24
+    16cd:	75          	loadsp 20
+    16ce:	33          	loadb
+    16cf:	75          	loadsp 20
+    16d0:	34          	storeb
+
+000016d1 <.LM534>:
+    16d1:	83          	im 3
+    16d2:	e3          	im -29
+    16d3:	98          	im 24
+    16d4:	18          	addsp 32
+    16d5:	54          	storesp 16
+    16d6:	73          	loadsp 12
+    16d7:	33          	loadb
+    16d8:	76          	loadsp 24
+    16d9:	34          	storeb
+
+000016da <.LM535>:
+    16da:	76          	loadsp 24
+    16db:	74          	loadsp 16
+    16dc:	34          	storeb
+
+000016dd <.LM536>:
+    16dd:	81          	im 1
+    16de:	18          	addsp 32
+    16df:	58          	storesp 32
+    16e0:	77          	loadsp 28
+    16e1:	8f          	im 15
+    16e2:	2e          	eq
+    16e3:	09          	not
+    16e4:	81          	im 1
+    16e5:	06          	and
+    16e6:	ff          	im -1
+    16e7:	a0          	im 32
+    16e8:	38          	neqbranch
+    16e9:	f7          	im -9
+    16ea:	81          	im 1
+    16eb:	39          	poppcrel
+
+000016ec <.L250>:
+    16ec:	0b          	nop
+    16ed:	0b          	nop
+    16ee:	80          	im 0
+    16ef:	f8          	im -8
+    16f0:	84          	im 4
+    16f1:	51          	storesp 4
+
+000016f2 <.LM538>:
+    16f2:	b9          	im 57
+    16f3:	f9          	im -7
+    16f4:	3f          	callpcrel
+
+000016f5 <.LM539>:
+    16f5:	0b          	nop
+    16f6:	0b          	nop
+    16f7:	80          	im 0
+    16f8:	f9          	im -7
+    16f9:	c4          	im -60
+    16fa:	51          	storesp 4
+    16fb:	b9          	im 57
+    16fc:	f0          	im -16
+    16fd:	3f          	callpcrel
+
+000016fe <.LM540>:
+    16fe:	0b          	nop
+    16ff:	0b          	nop
+    1700:	80          	im 0
+    1701:	f6          	im -10
+    1702:	e8          	im -24
+    1703:	51          	storesp 4
+    1704:	b9          	im 57
+    1705:	e7          	im -25
+    1706:	3f          	callpcrel
+
+00001707 <.LM541>:
+    1707:	80          	im 0
+    1708:	fc          	im -4
+    1709:	c4          	im -60
+    170a:	08          	load
+    170b:	70          	loadsp 0
+    170c:	08          	load
+    170d:	bf          	im 63
+    170e:	06          	and
+    170f:	56          	storesp 24
+    1710:	56          	storesp 24
+
+00001711 <.LM542>:
+    1711:	78          	loadsp 32
+    1712:	82          	im 2
+    1713:	2e          	eq
+    1714:	09          	not
+    1715:	81          	im 1
+    1716:	06          	and
+    1717:	f3          	im -13
+    1718:	df          	im -33
+    1719:	38          	neqbranch
+    171a:	f9          	im -7
+    171b:	da          	im -38
+    171c:	39          	poppcrel
+
+0000171d <.L264>:
+    171d:	83          	im 3
+    171e:	e3          	im -29
+    171f:	98          	im 24
+    1720:	51          	storesp 4
+    1721:	fc          	im -4
+    1722:	c1          	im -63
+    1723:	39          	poppcrel
+
+00001724 <.L266>:
+    1724:	83          	im 3
+    1725:	e2          	im -30
+    1726:	c8          	im -56
+    1727:	51          	storesp 4
+    1728:	fc          	im -4
+    1729:	ba          	im 58
+    172a:	39          	poppcrel
+
+0000172b <.L251>:
+    172b:	0b          	nop
+    172c:	0b          	nop
+    172d:	80          	im 0
+    172e:	f8          	im -8
+    172f:	98          	im 24
+    1730:	51          	storesp 4
+
+00001731 <.LM546>:
+    1731:	b9          	im 57
+    1732:	ba          	im 58
+    1733:	3f          	callpcrel
+
+00001734 <.LM547>:
+    1734:	0b          	nop
+    1735:	0b          	nop
+    1736:	80          	im 0
+    1737:	f9          	im -7
+    1738:	c4          	im -60
+    1739:	51          	storesp 4
+    173a:	b9          	im 57
+    173b:	b1          	im 49
+    173c:	3f          	callpcrel
+
+0000173d <.LM548>:
+    173d:	0b          	nop
+    173e:	0b          	nop
+    173f:	80          	im 0
+    1740:	f6          	im -10
+    1741:	e8          	im -24
+    1742:	51          	storesp 4
+    1743:	b9          	im 57
+    1744:	a8          	im 40
+    1745:	3f          	callpcrel
+
+00001746 <.LM549>:
+    1746:	80          	im 0
+    1747:	fc          	im -4
+    1748:	c4          	im -60
+    1749:	08          	load
+    174a:	70          	loadsp 0
+    174b:	08          	load
+    174c:	bf          	im 63
+    174d:	06          	and
+    174e:	56          	storesp 24
+    174f:	56          	storesp 24
+
+00001750 <.LM550>:
+    1750:	78          	loadsp 32
+    1751:	82          	im 2
+    1752:	2e          	eq
+    1753:	09          	not
+    1754:	81          	im 1
+    1755:	06          	and
+    1756:	f3          	im -13
+    1757:	a0          	im 32
+    1758:	38          	neqbranch
+    1759:	f9          	im -7
+    175a:	9b          	im 27
+    175b:	39          	poppcrel
+
+0000175c <getCommand>:
+    175c:	fc          	im -4
+    175d:	3d          	pushspadd
+    175e:	0d          	popsp
+    175f:	76          	loadsp 24
+    1760:	80          	im 0
+    1761:	fc          	im -4
+    1762:	a4          	im 36
+    1763:	08          	load
+    1764:	55          	storesp 20
+    1765:	55          	storesp 20
+
+00001766 <.L394>:
+    1766:	73          	loadsp 12
+    1767:	08          	load
+    1768:	70          	loadsp 0
+    1769:	81          	im 1
+    176a:	32          	xor
+    176b:	70          	loadsp 0
+    176c:	81          	im 1
+    176d:	06          	and
+    176e:	51          	storesp 4
+    176f:	51          	storesp 4
+    1770:	53          	storesp 12
+    1771:	72          	loadsp 8
+    1772:	f3          	im -13
+    1773:	38          	neqbranch
+
+00001774 <.LM553>:
+    1774:	83          	im 3
+    1775:	e3          	im -29
+    1776:	8c          	im 12
+    1777:	08          	load
+    1778:	86          	im 6
+    1779:	05          	add
+    177a:	51          	storesp 4
+    177b:	b3          	im 51
+    177c:	f2          	im -14
+    177d:	3f          	callpcrel
+
+0000177e <.LM554>:
+    177e:	80          	im 0
+    177f:	fc          	im -4
+    1780:	a4          	im 36
+    1781:	08          	load
+    1782:	70          	loadsp 0
+    1783:	08          	load
+    1784:	70          	loadsp 0
+    1785:	81          	im 1
+    1786:	06          	and
+    1787:	51          	storesp 4
+    1788:	51          	storesp 4
+    1789:	53          	storesp 12
+    178a:	72          	loadsp 8
+    178b:	80          	im 0
+    178c:	2e          	eq
+    178d:	93          	im 19
+    178e:	38          	neqbranch
+
+0000178f <.L410>:
+    178f:	eb          	im -21
+    1790:	c8          	im -56
+    1791:	3f          	callpcrel
+    1792:	80          	im 0
+    1793:	fc          	im -4
+    1794:	a4          	im 36
+    1795:	08          	load
+    1796:	70          	loadsp 0
+    1797:	08          	load
+    1798:	70          	loadsp 0
+    1799:	81          	im 1
+    179a:	06          	and
+    179b:	51          	storesp 4
+    179c:	51          	storesp 4
+    179d:	53          	storesp 12
+    179e:	72          	loadsp 8
+    179f:	ef          	im -17
+    17a0:	38          	neqbranch
+
+000017a1 <.L406>:
+    17a1:	b4          	im 52
+    17a2:	c3          	im -61
+    17a3:	3f          	callpcrel
+    17a4:	83          	im 3
+    17a5:	e0          	im -32
+    17a6:	80          	im 0
+    17a7:	08          	load
+    17a8:	75          	loadsp 20
+    17a9:	34          	storeb
+
+000017aa <.LM556>:
+    17aa:	b4          	im 52
+    17ab:	ba          	im 58
+    17ac:	3f          	callpcrel
+    17ad:	83          	im 3
+    17ae:	e0          	im -32
+    17af:	80          	im 0
+    17b0:	08          	load
+    17b1:	81          	im 1
+    17b2:	16          	addsp 24
+    17b3:	34          	storeb
+
+000017b4 <.LM557>:
+    17b4:	b4          	im 52
+    17b5:	b0          	im 48
+    17b6:	3f          	callpcrel
+    17b7:	83          	im 3
+    17b8:	e0          	im -32
+    17b9:	80          	im 0
+    17ba:	08          	load
+    17bb:	82          	im 2
+    17bc:	16          	addsp 24
+    17bd:	34          	storeb
+
+000017be <.LM558>:
+    17be:	b4          	im 52
+    17bf:	a6          	im 38
+    17c0:	3f          	callpcrel
+    17c1:	83          	im 3
+    17c2:	e0          	im -32
+    17c3:	80          	im 0
+    17c4:	08          	load
+    17c5:	83          	im 3
+    17c6:	16          	addsp 24
+    17c7:	34          	storeb
+
+000017c8 <.LM559>:
+    17c8:	b4          	im 52
+    17c9:	9c          	im 28
+    17ca:	3f          	callpcrel
+    17cb:	83          	im 3
+    17cc:	e0          	im -32
+    17cd:	80          	im 0
+    17ce:	08          	load
+    17cf:	84          	im 4
+    17d0:	16          	addsp 24
+    17d1:	34          	storeb
+    17d2:	80          	im 0
+    17d3:	fc          	im -4
+    17d4:	a4          	im 36
+    17d5:	08          	load
+    17d6:	54          	storesp 16
+
+000017d7 <.L399>:
+    17d7:	73          	loadsp 12
+    17d8:	08          	load
+    17d9:	70          	loadsp 0
+    17da:	81          	im 1
+    17db:	32          	xor
+    17dc:	70          	loadsp 0
+    17dd:	81          	im 1
+    17de:	06          	and
+    17df:	51          	storesp 4
+    17e0:	51          	storesp 4
+    17e1:	53          	storesp 12
+    17e2:	72          	loadsp 8
+    17e3:	f3          	im -13
+    17e4:	38          	neqbranch
+
+000017e5 <.LM561>:
+    17e5:	0b          	nop
+    17e6:	0b          	nop
+    17e7:	80          	im 0
+    17e8:	f8          	im -8
+    17e9:	b4          	im 52
+    17ea:	51          	storesp 4
+    17eb:	b8          	im 56
+    17ec:	80          	im 0
+    17ed:	3f          	callpcrel
+
+000017ee <.LM562>:
+    17ee:	74          	loadsp 16
+    17ef:	33          	loadb
+    17f0:	83          	im 3
+    17f1:	e0          	im -32
+    17f2:	c8          	im -56
+    17f3:	34          	storeb
+
+000017f4 <.LM563>:
+    17f4:	81          	im 1
+    17f5:	15          	addsp 20
+    17f6:	33          	loadb
+    17f7:	83          	im 3
+    17f8:	e0          	im -32
+    17f9:	c9          	im -55
+    17fa:	34          	storeb
+
+000017fb <.LM564>:
+    17fb:	82          	im 2
+    17fc:	15          	addsp 20
+    17fd:	33          	loadb
+    17fe:	83          	im 3
+    17ff:	e0          	im -32
+    1800:	ca          	im -54
+    1801:	34          	storeb
+
+00001802 <.LM565>:
+    1802:	83          	im 3
+    1803:	15          	addsp 20
+    1804:	33          	loadb
+    1805:	83          	im 3
+    1806:	e0          	im -32
+    1807:	cb          	im -53
+    1808:	34          	storeb
+
+00001809 <.LM566>:
+    1809:	84          	im 4
+    180a:	52          	storesp 8
+    180b:	83          	im 3
+    180c:	e0          	im -32
+    180d:	c8          	im -56
+    180e:	51          	storesp 4
+    180f:	dd          	im -35
+    1810:	df          	im -33
+    1811:	3f          	callpcrel
+    1812:	83          	im 3
+    1813:	e0          	im -32
+    1814:	80          	im 0
+    1815:	08          	load
+    1816:	81          	im 1
+    1817:	ff          	im -1
+    1818:	06          	and
+
+00001819 <.LM567>:
+    1819:	75          	loadsp 20
+    181a:	33          	loadb
+    181b:	52          	storesp 8
+    181c:	53          	storesp 12
+    181d:	b8          	im 56
+    181e:	dd          	im -35
+    181f:	3f          	callpcrel
+
+00001820 <.LM568>:
+    1820:	81          	im 1
+    1821:	15          	addsp 20
+    1822:	33          	loadb
+    1823:	51          	storesp 4
+    1824:	b8          	im 56
+    1825:	d6          	im -42
+    1826:	3f          	callpcrel
+
+00001827 <.LM569>:
+    1827:	82          	im 2
+    1828:	15          	addsp 20
+    1829:	33          	loadb
+    182a:	51          	storesp 4
+    182b:	b8          	im 56
+    182c:	cf          	im -49
+    182d:	3f          	callpcrel
+
+0000182e <.LM570>:
+    182e:	83          	im 3
+    182f:	15          	addsp 20
+    1830:	33          	loadb
+    1831:	51          	storesp 4
+    1832:	b8          	im 56
+    1833:	c8          	im -56
+    1834:	3f          	callpcrel
+
+00001835 <.LM571>:
+    1835:	84          	im 4
+    1836:	15          	addsp 20
+    1837:	33          	loadb
+    1838:	51          	storesp 4
+    1839:	b8          	im 56
+    183a:	c1          	im -63
+    183b:	3f          	callpcrel
+
+0000183c <.LM572>:
+    183c:	72          	loadsp 8
+    183d:	51          	storesp 4
+    183e:	b8          	im 56
+    183f:	bc          	im 60
+    1840:	3f          	callpcrel
+
+00001841 <.LM573>:
+    1841:	84          	im 4
+    1842:	15          	addsp 20
+    1843:	33          	loadb
+    1844:	55          	storesp 20
+    1845:	72          	loadsp 8
+    1846:	75          	loadsp 20
+    1847:	2e          	eq
+    1848:	bd          	im 61
+    1849:	38          	neqbranch
+
+0000184a <.LM574>:
+    184a:	0b          	nop
+    184b:	0b          	nop
+    184c:	80          	im 0
+    184d:	f8          	im -8
+    184e:	bc          	im 60
+    184f:	51          	storesp 4
+    1850:	b7          	im 55
+    1851:	9b          	im 27
+    1852:	3f          	callpcrel
+
+00001853 <.LM575>:
+    1853:	83          	im 3
+    1854:	e3          	im -29
+    1855:	8c          	im 12
+    1856:	08          	load
+    1857:	a8          	im 40
+    1858:	2e          	eq
+    1859:	80          	im 0
+    185a:	cb          	im -53
+    185b:	38          	neqbranch
+
+0000185c <.L403>:
+    185c:	a8          	im 40
+    185d:	0b          	nop
+    185e:	83          	im 3
+    185f:	e3          	im -29
+    1860:	8c          	im 12
+    1861:	0c          	store
+
+00001862 <.LM577>:
+    1862:	0b          	nop
+    1863:	0b          	nop
+    1864:	80          	im 0
+    1865:	f8          	im -8
+    1866:	c4          	im -60
+    1867:	51          	storesp 4
+    1868:	b7          	im 55
+    1869:	83          	im 3
+    186a:	3f          	callpcrel
+
+0000186b <.LM578>:
+    186b:	83          	im 3
+    186c:	e3          	im -29
+    186d:	8e          	im 14
+    186e:	22          	loadh
+    186f:	51          	storesp 4
+    1870:	b8          	im 56
+    1871:	8a          	im 10
+    1872:	3f          	callpcrel
+
+00001873 <.L401>:
+    1873:	0b          	nop
+    1874:	0b          	nop
+    1875:	80          	im 0
+    1876:	f9          	im -7
+    1877:	c4          	im -60
+    1878:	51          	storesp 4
+    1879:	b6          	im 54
+    187a:	f2          	im -14
+    187b:	3f          	callpcrel
+
+0000187c <.LM580>:
+    187c:	80          	im 0
+    187d:	e4          	im -28
+    187e:	51          	storesp 4
+    187f:	d8          	im -40
+    1880:	b2          	im 50
+    1881:	3f          	callpcrel
+    1882:	86          	im 6
+    1883:	3d          	pushspadd
+    1884:	0d          	popsp
+    1885:	04          	poppc
+
+00001886 <.L411>:
+    1886:	b3          	im 51
+    1887:	b4          	im 52
+    1888:	3f          	callpcrel
+    1889:	83          	im 3
+    188a:	e0          	im -32
+    188b:	80          	im 0
+    188c:	08          	load
+    188d:	80          	im 0
+    188e:	2e          	eq
+    188f:	e3          	im -29
+    1890:	38          	neqbranch
+
+00001891 <.LM582>:
+    1891:	0b          	nop
+    1892:	0b          	nop
+    1893:	80          	im 0
+    1894:	f8          	im -8
+    1895:	bc          	im 60
+    1896:	51          	storesp 4
+    1897:	b6          	im 54
+    1898:	d4          	im -44
+    1899:	3f          	callpcrel
+
+0000189a <.LM583>:
+    189a:	83          	im 3
+    189b:	e3          	im -29
+    189c:	8c          	im 12
+    189d:	08          	load
+    189e:	a8          	im 40
+    189f:	2e          	eq
+    18a0:	09          	not
+    18a1:	81          	im 1
+    18a2:	06          	and
+    18a3:	ff          	im -1
+    18a4:	b7          	im 55
+    18a5:	38          	neqbranch
+
+000018a6 <.L412>:
+    18a6:	86          	im 6
+    18a7:	0b          	nop
+    18a8:	83          	im 3
+    18a9:	e3          	im -29
+    18aa:	8c          	im 12
+    18ab:	0c          	store
+
+000018ac <.LM585>:
+    18ac:	0b          	nop
+    18ad:	0b          	nop
+    18ae:	80          	im 0
+    18af:	f8          	im -8
+    18b0:	cc          	im -52
+    18b1:	51          	storesp 4
+
+000018b2 <.LM586>:
+    18b2:	b6          	im 54
+    18b3:	b9          	im 57
+    18b4:	3f          	callpcrel
+
+000018b5 <.LM587>:
+    18b5:	83          	im 3
+    18b6:	e3          	im -29
+    18b7:	8e          	im 14
+    18b8:	22          	loadh
+    18b9:	51          	storesp 4
+    18ba:	b7          	im 55
+    18bb:	c0          	im -64
+    18bc:	3f          	callpcrel
+    18bd:	ff          	im -1
+    18be:	b4          	im 52
+    18bf:	39          	poppcrel
+
+000018c0 <mmcReadCached>:
+    18c0:	fc          	im -4
+    18c1:	3d          	pushspadd
+    18c2:	0d          	popsp
+    18c3:	76          	loadsp 24
+    18c4:	55          	storesp 20
+
+000018c5 <.LM589>:
+    18c5:	74          	loadsp 16
+    18c6:	83          	im 3
+    18c7:	e0          	im -32
+    18c8:	b0          	im 48
+    18c9:	08          	load
+    18ca:	2e          	eq
+    18cb:	af          	im 47
+    18cc:	38          	neqbranch
+
+000018cd <.LM590>:
+    18cd:	80          	im 0
+    18ce:	54          	storesp 16
+
+000018cf <.L415>:
+    18cf:	74          	loadsp 16
+    18d0:	51          	storesp 4
+    18d1:	ab          	im 43
+    18d2:	a9          	im 41
+    18d3:	3f          	callpcrel
+    18d4:	83          	im 3
+    18d5:	e0          	im -32
+    18d6:	80          	im 0
+    18d7:	08          	load
+    18d8:	81          	im 1
+    18d9:	ff          	im -1
+    18da:	06          	and
+
+000018db <.LM592>:
+    18db:	ff          	im -1
+    18dc:	15          	addsp 20
+    18dd:	70          	loadsp 0
+    18de:	81          	im 1
+    18df:	ff          	im -1
+    18e0:	06          	and
+
+000018e1 <.LBE22>:
+    18e1:	72          	loadsp 8
+    18e2:	30          	neg
+    18e3:	70          	loadsp 0
+    18e4:	9f          	im 31
+    18e5:	2a          	lshiftright
+    18e6:	51          	storesp 4
+    18e7:	52          	storesp 8
+    18e8:	56          	storesp 24
+    18e9:	53          	storesp 12
+    18ea:	53          	storesp 12
+    18eb:	73          	loadsp 12
+    18ec:	80          	im 0
+    18ed:	2e          	eq
+    18ee:	84          	im 4
+    18ef:	38          	neqbranch
+    18f0:	71          	loadsp 4
+    18f1:	dd          	im -35
+    18f2:	38          	neqbranch
+
+000018f3 <.L420>:
+    18f3:	72          	loadsp 8
+    18f4:	fe          	im -2
+    18f5:	38          	neqbranch
+
+000018f6 <.LM595>:
+    18f6:	74          	loadsp 16
+    18f7:	83          	im 3
+    18f8:	e0          	im -32
+    18f9:	b0          	im 48
+    18fa:	0c          	store
+
+000018fb <.L413>:
+    18fb:	86          	im 6
+    18fc:	3d          	pushspadd
+    18fd:	0d          	popsp
+    18fe:	04          	poppc
+
+000018ff <disk_readp>:
+    18ff:	fc          	im -4
+    1900:	3d          	pushspadd
+    1901:	0d          	popsp
+    1902:	76          	loadsp 24
+    1903:	02          	pushsp
+    1904:	84          	im 4
+    1905:	05          	add
+    1906:	a2          	im 34
+    1907:	05          	add
+    1908:	22          	loadh
+    1909:	02          	pushsp
+    190a:	88          	im 8
+    190b:	05          	add
+    190c:	a6          	im 38
+    190d:	05          	add
+    190e:	22          	loadh
+
+0000190f <.LM598>:
+    190f:	7a          	loadsp 40
+    1910:	54          	storesp 16
+    1911:	55          	storesp 20
+    1912:	55          	storesp 20
+    1913:	55          	storesp 20
+    1914:	ff          	im -1
+    1915:	aa          	im 42
+    1916:	3f          	callpcrel
+
+00001917 <.LM599>:
+    1917:	72          	loadsp 8
+    1918:	80          	im 0
+    1919:	2e          	eq
+    191a:	a1          	im 33
+    191b:	38          	neqbranch
+
+0000191c <.L433>:
+    191c:	83          	im 3
+    191d:	e3          	im -29
+    191e:	e8          	im -24
+    191f:	14          	addsp 16
+    1920:	33          	loadb
+    1921:	75          	loadsp 20
+    1922:	70          	loadsp 0
+    1923:	81          	im 1
+    1924:	05          	add
+    1925:	57          	storesp 28
+    1926:	34          	storeb
+
+00001927 <.LBE23>:
+    1927:	81          	im 1
+    1928:	14          	addsp 16
+    1929:	70          	loadsp 0
+    192a:	83          	im 3
+    192b:	ff          	im -1
+    192c:	ff          	im -1
+    192d:	06          	and
+    192e:	ff          	im -1
+    192f:	15          	addsp 20
+    1930:	70          	loadsp 0
+    1931:	83          	im 3
+    1932:	ff          	im -1
+    1933:	ff          	im -1
+    1934:	06          	and
+    1935:	56          	storesp 24
+    1936:	52          	storesp 8
+    1937:	55          	storesp 20
+    1938:	52          	storesp 8
+    1939:	72          	loadsp 8
+    193a:	e1          	im -31
+    193b:	38          	neqbranch
+
+0000193c <.L430>:
+    193c:	80          	im 0
+    193d:	0b          	nop
+    193e:	83          	im 3
+    193f:	e0          	im -32
+    1940:	80          	im 0
+    1941:	0c          	store
+    1942:	86          	im 6
+    1943:	3d          	pushspadd
+    1944:	0d          	popsp
+    1945:	04          	poppc
+
+00001946 <USART_Send_Buffer>:
+
+void USART_Send_Buffer(unsigned char *buff, u16 len)
+{
+    1946:	fe          	im -2
+    1947:	3d          	pushspadd
+    1948:	0d          	popsp
+    1949:	74          	loadsp 16
+    194a:	02          	pushsp
+    194b:	84          	im 4
+    194c:	05          	add
+    194d:	96          	im 22
+    194e:	05          	add
+    194f:	22          	loadh
+    1950:	53          	storesp 12
+    1951:	53          	storesp 12
+
+00001952 <.LM604>:
+	while(len>0) { USART_Transmit_Byte(*buff++); len--; }
+    1952:	71          	loadsp 4
+    1953:	80          	im 0
+    1954:	2e          	eq
+    1955:	97          	im 23
+    1956:	38          	neqbranch
+
+00001957 <.L442>:
+    1957:	72          	loadsp 8
+    1958:	70          	loadsp 0
+    1959:	81          	im 1
+    195a:	05          	add
+    195b:	54          	storesp 16
+    195c:	33          	loadb
+    195d:	51          	storesp 4
+    195e:	b0          	im 48
+    195f:	e7          	im -25
+    1960:	3f          	callpcrel
+    1961:	ff          	im -1
+    1962:	12          	addsp 8
+    1963:	70          	loadsp 0
+    1964:	83          	im 3
+    1965:	ff          	im -1
+    1966:	ff          	im -1
+    1967:	06          	and
+    1968:	51          	storesp 4
+    1969:	52          	storesp 8
+
+0000196a <.LBE24>:
+    196a:	71          	loadsp 4
+    196b:	eb          	im -21
+    196c:	38          	neqbranch
+
+0000196d <.L439>:
+    196d:	84          	im 4
+    196e:	3d          	pushspadd
+    196f:	0d          	popsp
+    1970:	04          	poppc
+
+00001971 <USART_Send_cmpl_and_atari_sector_buffer_and_check_sum>:
+}
+
+void USART_Send_cmpl_and_atari_sector_buffer_and_check_sum(unsigned short len)
+{
+    1971:	fe          	im -2
+    1972:	3d          	pushspadd
+    1973:	0d          	popsp
+    1974:	02          	pushsp
+    1975:	92          	im 18
+    1976:	05          	add
+    1977:	22          	loadh
+
+00001978 <.LM606>:
+	u08 check_sum;
+	debug("(send:");
+    1978:	0b          	nop
+    1979:	0b          	nop
+    197a:	80          	im 0
+    197b:	f8          	im -8
+    197c:	d4          	im -44
+    197d:	52          	storesp 8
+    197e:	53          	storesp 12
+    197f:	b4          	im 52
+    1980:	ec          	im -20
+    1981:	3f          	callpcrel
+
+00001982 <.LM607>:
+	plotnextnumber(len);
+    1982:	72          	loadsp 8
+    1983:	51          	storesp 4
+    1984:	b5          	im 53
+    1985:	f6          	im -10
+    1986:	3f          	callpcrel
+
+00001987 <.LM608>:
+
+	DELAY_T5_MIN;
+    1987:	82          	im 2
+    1988:	ac          	im 44
+    1989:	51          	storesp 4
+    198a:	d6          	im -42
+    198b:	a7          	im 39
+    198c:	3f          	callpcrel
+
+0000198d <.LM609>:
+	send_CMPL();
+    198d:	80          	im 0
+    198e:	c3          	im -61
+    198f:	51          	storesp 4
+    1990:	b0          	im 48
+    1991:	b5          	im 53
+    1992:	3f          	callpcrel
+
+00001993 <.LM610>:
+
+	// Hias: changed to 100us so that Qmeg3 works again with the
+	// new bit-banging transmission code
+	DELAY_T3_PERIPH;
+    1993:	81          	im 1
+    1994:	96          	im 22
+    1995:	51          	storesp 4
+    1996:	d6          	im -42
+    1997:	9b          	im 27
+    1998:	3f          	callpcrel
+
+00001999 <.LM611>:
+
+	check_sum = 0;
+	USART_Send_Buffer(atari_sector_buffer,len);
+    1999:	72          	loadsp 8
+    199a:	52          	storesp 8
+    199b:	83          	im 3
+    199c:	e0          	im -32
+    199d:	c8          	im -56
+    199e:	51          	storesp 4
+    199f:	ff          	im -1
+    19a0:	a5          	im 37
+    19a1:	3f          	callpcrel
+
+000019a2 <.LM612>:
+	// tx_checksum is updated by bit-banging USART_Transmit_Byte,
+	// so we can skip separate calculation
+	check_sum = get_checksum(atari_sector_buffer,len);
+    19a2:	72          	loadsp 8
+    19a3:	52          	storesp 8
+    19a4:	83          	im 3
+    19a5:	e0          	im -32
+    19a6:	c8          	im -56
+    19a7:	51          	storesp 4
+    19a8:	da          	im -38
+    19a9:	c6          	im -58
+    19aa:	3f          	callpcrel
+    19ab:	83          	im 3
+    19ac:	e0          	im -32
+    19ad:	80          	im 0
+    19ae:	08          	load
+    19af:	81          	im 1
+    19b0:	ff          	im -1
+    19b1:	06          	and
+
+000019b2 <.LM613>:
+	USART_Transmit_Byte(check_sum);
+    19b2:	70          	loadsp 0
+    19b3:	52          	storesp 8
+    19b4:	53          	storesp 12
+    19b5:	b0          	im 48
+    19b6:	90          	im 16
+    19b7:	3f          	callpcrel
+
+000019b8 <.LM614>:
+	//hexdump_pure(atari_sector_buffer,len);
+	debug(":chk:");
+    19b8:	0b          	nop
+    19b9:	0b          	nop
+    19ba:	80          	im 0
+    19bb:	f8          	im -8
+    19bc:	dc          	im -36
+    19bd:	51          	storesp 4
+    19be:	b4          	im 52
+    19bf:	ad          	im 45
+    19c0:	3f          	callpcrel
+
+000019c1 <.LM615>:
+	plotnextnumber(check_sum);
+    19c1:	72          	loadsp 8
+    19c2:	51          	storesp 4
+    19c3:	b5          	im 53
+    19c4:	b7          	im 55
+    19c5:	3f          	callpcrel
+
+000019c6 <.LM616>:
+	debug(")");
+    19c6:	0b          	nop
+    19c7:	0b          	nop
+    19c8:	80          	im 0
+    19c9:	f7          	im -9
+    19ca:	dc          	im -36
+    19cb:	51          	storesp 4
+    19cc:	b4          	im 52
+    19cd:	9f          	im 31
+    19ce:	3f          	callpcrel
+    19cf:	84          	im 4
+    19d0:	3d          	pushspadd
+    19d1:	0d          	popsp
+    19d2:	04          	poppc
+
+000019d3 <sdcard>:
+    19d3:	f1          	im -15
+    19d4:	3d          	pushspadd
+    19d5:	0d          	popsp
+
+000019d6 <.LM618>:
+    19d6:	0b          	nop
+    19d7:	0b          	nop
+    19d8:	80          	im 0
+    19d9:	f8          	im -8
+    19da:	e4          	im -28
+    19db:	51          	storesp 4
+    19dc:	b4          	im 52
+    19dd:	8f          	im 15
+    19de:	3f          	callpcrel
+
+000019df <.LM619>:
+    19df:	0b          	nop
+    19e0:	0b          	nop
+    19e1:	80          	im 0
+    19e2:	f8          	im -8
+    19e3:	ec          	im -20
+    19e4:	51          	storesp 4
+    19e5:	b4          	im 52
+    19e6:	86          	im 6
+    19e7:	3f          	callpcrel
+
+000019e8 <.LM620>:
+    19e8:	d9          	im -39
+    19e9:	c6          	im -58
+    19ea:	3f          	callpcrel
+    19eb:	83          	im 3
+    19ec:	e0          	im -32
+    19ed:	80          	im 0
+    19ee:	08          	load
+    19ef:	81          	im 1
+    19f0:	ff          	im -1
+    19f1:	06          	and
+    19f2:	54          	storesp 16
+    19f3:	73          	loadsp 12
+    19f4:	82          	im 2
+    19f5:	d2          	im -46
+    19f6:	38          	neqbranch
+
+000019f7 <.LM621>:
+    19f7:	0b          	nop
+    19f8:	0b          	nop
+    19f9:	80          	im 0
+    19fa:	f5          	im -11
+    19fb:	94          	im 20
+    19fc:	51          	storesp 4
+    19fd:	b3          	im 51
+    19fe:	ee          	im -18
+    19ff:	3f          	callpcrel
+
+00001a00 <.LM622>:
+    1a00:	0b          	nop
+    1a01:	0b          	nop
+    1a02:	80          	im 0
+    1a03:	f8          	im -8
+    1a04:	f8          	im -8
+    1a05:	51          	storesp 4
+    1a06:	b3          	im 51
+    1a07:	e5          	im -27
+    1a08:	3f          	callpcrel
+
+00001a09 <.LM623>:
+    1a09:	83          	im 3
+    1a0a:	e3          	im -29
+    1a0b:	ac          	im 44
+    1a0c:	51          	storesp 4
+    1a0d:	98          	im 24
+    1a0e:	80          	im 0
+    1a0f:	3f          	callpcrel
+    1a10:	83          	im 3
+    1a11:	e0          	im -32
+    1a12:	80          	im 0
+    1a13:	08          	load
+    1a14:	82          	im 2
+    1a15:	b2          	im 50
+    1a16:	38          	neqbranch
+
+00001a17 <.LM624>:
+    1a17:	0b          	nop
+    1a18:	0b          	nop
+    1a19:	80          	im 0
+    1a1a:	f5          	im -11
+    1a1b:	94          	im 20
+    1a1c:	51          	storesp 4
+    1a1d:	b3          	im 51
+    1a1e:	ce          	im -50
+    1a1f:	3f          	callpcrel
+
+00001a20 <.LM625>:
+    1a20:	0b          	nop
+    1a21:	0b          	nop
+    1a22:	80          	im 0
+    1a23:	f9          	im -7
+    1a24:	80          	im 0
+    1a25:	51          	storesp 4
+    1a26:	b3          	im 51
+    1a27:	c5          	im -59
+    1a28:	3f          	callpcrel
+
+00001a29 <.LM626>:
+    1a29:	0b          	nop
+    1a2a:	0b          	nop
+    1a2b:	80          	im 0
+    1a2c:	f4          	im -12
+    1a2d:	fc          	im -4
+    1a2e:	52          	storesp 8
+    1a2f:	83          	im 3
+    1a30:	e2          	im -30
+    1a31:	f4          	im -12
+    1a32:	51          	storesp 4
+    1a33:	a1          	im 33
+    1a34:	e4          	im -28
+    1a35:	3f          	callpcrel
+    1a36:	83          	im 3
+    1a37:	e0          	im -32
+    1a38:	80          	im 0
+    1a39:	08          	load
+    1a3a:	82          	im 2
+    1a3b:	8c          	im 12
+    1a3c:	38          	neqbranch
+
+00001a3d <.LM627>:
+    1a3d:	0b          	nop
+    1a3e:	0b          	nop
+    1a3f:	80          	im 0
+    1a40:	f5          	im -11
+    1a41:	94          	im 20
+    1a42:	51          	storesp 4
+
+00001a43 <.LM628>:
+    1a43:	b3          	im 51
+    1a44:	a8          	im 40
+    1a45:	3f          	callpcrel
+    1a46:	83          	im 3
+    1a47:	e0          	im -32
+    1a48:	94          	im 20
+    1a49:	52          	storesp 8
+    1a4a:	83          	im 3
+    1a4b:	e2          	im -30
+    1a4c:	f4          	im -12
+    1a4d:	51          	storesp 4
+    1a4e:	a2          	im 34
+    1a4f:	dc          	im -36
+    1a50:	3f          	callpcrel
+    1a51:	83          	im 3
+    1a52:	e0          	im -32
+    1a53:	80          	im 0
+    1a54:	08          	load
+    1a55:	a5          	im 37
+    1a56:	38          	neqbranch
+
+00001a57 <.L544>:
+    1a57:	83          	im 3
+    1a58:	e0          	im -32
+    1a59:	9d          	im 29
+    1a5a:	33          	loadb
+    1a5b:	54          	storesp 16
+    1a5c:	73          	loadsp 12
+    1a5d:	80          	im 0
+    1a5e:	2e          	eq
+    1a5f:	9b          	im 27
+    1a60:	38          	neqbranch
+    1a61:	83          	im 3
+    1a62:	e0          	im -32
+    1a63:	9d          	im 29
+    1a64:	51          	storesp 4
+    1a65:	b3          	im 51
+    1a66:	86          	im 6
+    1a67:	3f          	callpcrel
+    1a68:	83          	im 3
+    1a69:	e0          	im -32
+    1a6a:	94          	im 20
+    1a6b:	52          	storesp 8
+    1a6c:	83          	im 3
+    1a6d:	e2          	im -30
+    1a6e:	f4          	im -12
+    1a6f:	51          	storesp 4
+    1a70:	a2          	im 34
+    1a71:	ba          	im 58
+    1a72:	3f          	callpcrel
+    1a73:	83          	im 3
+    1a74:	e0          	im -32
+    1a75:	80          	im 0
+    1a76:	08          	load
+    1a77:	80          	im 0
+    1a78:	2e          	eq
+    1a79:	dd          	im -35
+    1a7a:	38          	neqbranch
+
+00001a7b <.L449>:
+    1a7b:	80          	im 0
+    1a7c:	55          	storesp 20
+
+00001a7d <.L455>:
+    1a7d:	0b          	nop
+    1a7e:	0b          	nop
+    1a7f:	80          	im 0
+    1a80:	f9          	im -7
+    1a81:	8c          	im 12
+    1a82:	15          	addsp 20
+    1a83:	54          	storesp 16
+    1a84:	73          	loadsp 12
+    1a85:	33          	loadb
+    1a86:	83          	im 3
+    1a87:	e3          	im -29
+    1a88:	98          	im 24
+    1a89:	16          	addsp 24
+    1a8a:	34          	storeb
+
+00001a8b <.LM631>:
+    1a8b:	73          	loadsp 12
+    1a8c:	33          	loadb
+    1a8d:	83          	im 3
+    1a8e:	e3          	im -29
+    1a8f:	d8          	im -40
+    1a90:	16          	addsp 24
+    1a91:	34          	storeb
+
+00001a92 <.LM632>:
+    1a92:	73          	loadsp 12
+    1a93:	33          	loadb
+    1a94:	83          	im 3
+    1a95:	e2          	im -30
+    1a96:	c8          	im -56
+    1a97:	16          	addsp 24
+    1a98:	34          	storeb
+
+00001a99 <.LM633>:
+    1a99:	73          	loadsp 12
+    1a9a:	33          	loadb
+    1a9b:	83          	im 3
+    1a9c:	e0          	im -32
+    1a9d:	b8          	im 56
+    1a9e:	16          	addsp 24
+    1a9f:	34          	storeb
+
+00001aa0 <.LM634>:
+    1aa0:	73          	loadsp 12
+    1aa1:	33          	loadb
+    1aa2:	54          	storesp 16
+    1aa3:	73          	loadsp 12
+    1aa4:	80          	im 0
+    1aa5:	2e          	eq
+    1aa6:	8c          	im 12
+    1aa7:	38          	neqbranch
+
+00001aa8 <.LM635>:
+    1aa8:	81          	im 1
+    1aa9:	15          	addsp 20
+    1aaa:	55          	storesp 20
+    1aab:	74          	loadsp 16
+    1aac:	8f          	im 15
+    1aad:	2e          	eq
+    1aae:	09          	not
+    1aaf:	81          	im 1
+    1ab0:	06          	and
+    1ab1:	cb          	im -53
+    1ab2:	38          	neqbranch
+
+00001ab3 <.L452>:
+    1ab3:	81          	im 1
+    1ab4:	0b          	nop
+    1ab5:	83          	im 3
+    1ab6:	e0          	im -32
+    1ab7:	b4          	im 52
+    1ab8:	0c          	store
+
+00001ab9 <.LM637>:
+    1ab9:	83          	im 3
+    1aba:	e3          	im -29
+    1abb:	98          	im 24
+    1abc:	51          	storesp 4
+    1abd:	d8          	im -40
+    1abe:	fc          	im -4
+    1abf:	3f          	callpcrel
+
+00001ac0 <.LM638>:
+    1ac0:	80          	im 0
+    1ac1:	51          	storesp 4
+    1ac2:	d7          	im -41
+    1ac3:	a6          	im 38
+    1ac4:	3f          	callpcrel
+
+00001ac5 <.LM639>:
+    1ac5:	80          	im 0
+    1ac6:	fb          	im -5
+    1ac7:	e4          	im -28
+    1ac8:	08          	load
+    1ac9:	54          	storesp 16
+    1aca:	80          	im 0
+    1acb:	74          	loadsp 16
+    1acc:	34          	storeb
+
+00001acd <.LM640>:
+    1acd:	d6          	im -42
+    1ace:	a1          	im 33
+    1acf:	3f          	callpcrel
+
+00001ad0 <.LM641>:
+    1ad0:	81          	im 1
+    1ad1:	51          	storesp 4
+    1ad2:	d7          	im -41
+    1ad3:	96          	im 22
+    1ad4:	3f          	callpcrel
+
+00001ad5 <.LM642>:
+    1ad5:	80          	im 0
+    1ad6:	51          	storesp 4
+    1ad7:	d7          	im -41
+    1ad8:	b5          	im 53
+    1ad9:	3f          	callpcrel
+
+00001ada <.LM643>:
+    1ada:	83          	im 3
+    1adb:	e3          	im -29
+    1adc:	8c          	im 12
+    1add:	08          	load
+    1ade:	86          	im 6
+    1adf:	05          	add
+    1ae0:	51          	storesp 4
+    1ae1:	ad          	im 45
+    1ae2:	8c          	im 12
+    1ae3:	3f          	callpcrel
+    1ae4:	8e          	im 14
+    1ae5:	3d          	pushspadd
+    1ae6:	91          	im 17
+    1ae7:	3d          	pushspadd
+    1ae8:	5e          	storesp 56
+    1ae9:	59          	storesp 36
+
+00001aea <.L541>:
+    1aea:	78          	loadsp 32
+    1aeb:	51          	storesp 4
+    1aec:	f8          	im -8
+    1aed:	ee          	im -18
+    1aee:	3f          	callpcrel
+
+00001aef <.LM645>:
+    1aef:	8e          	im 14
+    1af0:	3d          	pushspadd
+    1af1:	33          	loadb
+    1af2:	cf          	im -49
+    1af3:	11          	addsp 4
+    1af4:	70          	loadsp 0
+    1af5:	81          	im 1
+    1af6:	ff          	im -1
+    1af7:	06          	and
+    1af8:	51          	storesp 4
+    1af9:	55          	storesp 20
+    1afa:	55          	storesp 20
+    1afb:	73          	loadsp 12
+    1afc:	82          	im 2
+    1afd:	26          	ulessthan
+    1afe:	eb          	im -21
+    1aff:	38          	neqbranch
+
+00001b00 <.LM646>:
+    1b00:	74          	loadsp 16
+    1b01:	8f          	im 15
+    1b02:	06          	and
+    1b03:	54          	storesp 16
+
+00001b04 <.LM647>:
+    1b04:	73          	loadsp 12
+    1b05:	83          	im 3
+    1b06:	e0          	im -32
+    1b07:	b4          	im 52
+    1b08:	08          	load
+    1b09:	2e          	eq
+    1b0a:	97          	im 23
+    1b0b:	38          	neqbranch
+
+00001b0c <.LM648>:
+    1b0c:	73          	loadsp 12
+    1b0d:	83          	im 3
+    1b0e:	e0          	im -32
+    1b0f:	b4          	im 52
+    1b10:	0c          	store
+
+00001b11 <.LM649>:
+    1b11:	73          	loadsp 12
+    1b12:	82          	im 2
+    1b13:	2e          	eq
+    1b14:	82          	im 2
+    1b15:	b6          	im 54
+    1b16:	38          	neqbranch
+    1b17:	73          	loadsp 12
+    1b18:	82          	im 2
+    1b19:	24          	lessthan
+    1b1a:	82          	im 2
+    1b1b:	8a          	im 10
+    1b1c:	38          	neqbranch
+    1b1d:	73          	loadsp 12
+    1b1e:	81          	im 1
+    1b1f:	2e          	eq
+    1b20:	b4          	im 52
+    1b21:	38          	neqbranch
+
+00001b22 <.L459>:
+    1b22:	83          	im 3
+    1b23:	e2          	im -30
+    1b24:	e4          	im -28
+    1b25:	08          	load
+    1b26:	80          	im 0
+    1b27:	2e          	eq
+    1b28:	c1          	im -63
+    1b29:	38          	neqbranch
+
+00001b2a <.LM651>:
+    1b2a:	02          	pushsp
+    1b2b:	b5          	im 53
+    1b2c:	05          	add
+    1b2d:	33          	loadb
+    1b2e:	54          	storesp 16
+    1b2f:	73          	loadsp 12
+    1b30:	80          	im 0
+    1b31:	d2          	im -46
+    1b32:	2e          	eq
+    1b33:	82          	im 2
+    1b34:	a1          	im 33
+    1b35:	38          	neqbranch
+    1b36:	73          	loadsp 12
+    1b37:	80          	im 0
+    1b38:	d2          	im -46
+    1b39:	24          	lessthan
+    1b3a:	82          	im 2
+    1b3b:	83          	im 3
+    1b3c:	38          	neqbranch
+    1b3d:	73          	loadsp 12
+    1b3e:	bf          	im 63
+    1b3f:	2e          	eq
+    1b40:	9d          	im 29
+    1b41:	38          	neqbranch
+
+00001b42 <.LM652>:
+    1b42:	ac          	im 44
+    1b43:	94          	im 20
+    1b44:	3f          	callpcrel
+    1b45:	ff          	im -1
+    1b46:	a3          	im 35
+    1b47:	39          	poppcrel
+
+00001b48 <.L540>:
+    1b48:	0b          	nop
+    1b49:	0b          	nop
+    1b4a:	80          	im 0
+    1b4b:	f5          	im -11
+    1b4c:	8c          	im 12
+    1b4d:	51          	storesp 4
+    1b4e:	b1          	im 49
+    1b4f:	9d          	im 29
+    1b50:	3f          	callpcrel
+
+00001b51 <.LM654>:
+    1b51:	91          	im 17
+    1b52:	3d          	pushspadd
+    1b53:	0d          	popsp
+    1b54:	04          	poppc
+
+00001b55 <.L461>:
+    1b55:	83          	im 3
+    1b56:	e3          	im -29
+    1b57:	98          	im 24
+    1b58:	51          	storesp 4
+
+00001b59 <.LM656>:
+    1b59:	d7          	im -41
+    1b5a:	e0          	im -32
+    1b5b:	3f          	callpcrel
+    1b5c:	c5          	im -59
+    1b5d:	39          	poppcrel
+
+00001b5e <.L468>:
+    1b5e:	0b          	nop
+    1b5f:	0b          	nop
+    1b60:	80          	im 0
+    1b61:	f6          	im -10
+    1b62:	e8          	im -24
+    1b63:	51          	storesp 4
+    1b64:	b1          	im 49
+    1b65:	87          	im 7
+    1b66:	3f          	callpcrel
+
+00001b67 <.LM658>:
+    1b67:	02          	pushsp
+    1b68:	b7          	im 55
+    1b69:	05          	add
+    1b6a:	33          	loadb
+    1b6b:	70          	loadsp 0
+    1b6c:	88          	im 8
+    1b6d:	2b          	ashiftleft
+    1b6e:	81          	im 1
+    1b6f:	fe          	im -2
+    1b70:	80          	im 0
+    1b71:	06          	and
+    1b72:	02          	pushsp
+    1b73:	88          	im 8
+    1b74:	05          	add
+    1b75:	b6          	im 54
+    1b76:	05          	add
+    1b77:	33          	loadb
+    1b78:	71          	loadsp 4
+    1b79:	05          	add
+    1b7a:	51          	storesp 4
+    1b7b:	55          	storesp 20
+    1b7c:	55          	storesp 20
+
+00001b7d <.LM659>:
+    1b7d:	ad          	im 45
+    1b7e:	96          	im 22
+    1b7f:	3f          	callpcrel
+
+00001b80 <.LM660>:
+    1b80:	80          	im 0
+    1b81:	c1          	im -63
+    1b82:	51          	storesp 4
+    1b83:	ac          	im 44
+    1b84:	c2          	im -62
+    1b85:	3f          	callpcrel
+
+00001b86 <.LM661>:
+    1b86:	d2          	im -46
+    1b87:	c0          	im -64
+    1b88:	3f          	callpcrel
+
+00001b89 <.LM662>:
+    1b89:	86          	im 6
+    1b8a:	0b          	nop
+    1b8b:	83          	im 3
+    1b8c:	e0          	im -32
+    1b8d:	c8          	im -56
+    1b8e:	34          	storeb
+
+00001b8f <.LM663>:
+    1b8f:	81          	im 1
+    1b90:	52          	storesp 8
+    1b91:	83          	im 3
+    1b92:	e0          	im -32
+    1b93:	c8          	im -56
+    1b94:	51          	storesp 4
+    1b95:	b3          	im 51
+    1b96:	e2          	im -30
+    1b97:	3f          	callpcrel
+
+00001b98 <.LM664>:
+    1b98:	81          	im 1
+    1b99:	51          	storesp 4
+    1b9a:	fb          	im -5
+    1b9b:	d5          	im -43
+    1b9c:	3f          	callpcrel
+
+00001b9d <.LM665>:
+    1b9d:	73          	loadsp 12
+    1b9e:	85          	im 5
+    1b9f:	d4          	im -44
+    1ba0:	38          	neqbranch
+
+00001ba1 <.LM666>:
+    1ba1:	86          	im 6
+    1ba2:	0b          	nop
+    1ba3:	83          	im 3
+    1ba4:	e3          	im -29
+    1ba5:	8c          	im 12
+    1ba6:	0c          	store
+
+00001ba7 <.LM667>:
+    1ba7:	0b          	nop
+    1ba8:	0b          	nop
+    1ba9:	80          	im 0
+    1baa:	f8          	im -8
+    1bab:	cc          	im -52
+    1bac:	51          	storesp 4
+
+00001bad <.LM668>:
+    1bad:	b0          	im 48
+    1bae:	be          	im 62
+    1baf:	3f          	callpcrel
+
+00001bb0 <.LM669>:
+    1bb0:	83          	im 3
+    1bb1:	e3          	im -29
+    1bb2:	8e          	im 14
+    1bb3:	22          	loadh
+    1bb4:	51          	storesp 4
+    1bb5:	b1          	im 49
+    1bb6:	c5          	im -59
+    1bb7:	3f          	callpcrel
+
+00001bb8 <.L471>:
+    1bb8:	0b          	nop
+    1bb9:	0b          	nop
+    1bba:	80          	im 0
+    1bbb:	f9          	im -7
+    1bbc:	98          	im 24
+    1bbd:	51          	storesp 4
+    1bbe:	b0          	im 48
+    1bbf:	ad          	im 45
+    1bc0:	3f          	callpcrel
+
+00001bc1 <.LM671>:
+    1bc1:	ac          	im 44
+    1bc2:	d2          	im -46
+    1bc3:	3f          	callpcrel
+
+00001bc4 <.LM672>:
+    1bc4:	80          	im 0
+    1bc5:	c1          	im -63
+    1bc6:	51          	storesp 4
+    1bc7:	ab          	im 43
+    1bc8:	fe          	im -2
+    1bc9:	3f          	callpcrel
+
+00001bca <.LM673>:
+    1bca:	d1          	im -47
+    1bcb:	fc          	im -4
+    1bcc:	3f          	callpcrel
+
+00001bcd <.LM674>:
+    1bcd:	98          	im 24
+
+00001bce <.LM675>:
+    1bce:	0b          	nop
+    1bcf:	83          	im 3
+    1bd0:	e2          	im -30
+    1bd1:	ec          	im -20
+    1bd2:	33          	loadb
+    1bd3:	83          	im 3
+    1bd4:	e2          	im -30
+    1bd5:	ed          	im -19
+    1bd6:	33          	loadb
+    1bd7:	71          	loadsp 4
+    1bd8:	88          	im 8
+    1bd9:	2b          	ashiftleft
+    1bda:	07          	or
+    1bdb:	56          	storesp 24
+    1bdc:	58          	storesp 32
+    1bdd:	55          	storesp 20
+    1bde:	73          	loadsp 12
+    1bdf:	81          	im 1
+    1be0:	80          	im 0
+    1be1:	2e          	eq
+    1be2:	82          	im 2
+    1be3:	c2          	im -62
+    1be4:	38          	neqbranch
+
+00001be5 <.LM676>:
+    1be5:	b8          	im 56
+    1be6:	55          	storesp 20
+
+00001be7 <.L474>:
+    1be7:	74          	loadsp 16
+    1be8:	83          	im 3
+    1be9:	e0          	im -32
+    1bea:	c8          	im -56
+    1beb:	34          	storeb
+
+00001bec <.LM678>:
+    1bec:	ff          	im -1
+    1bed:	0b          	nop
+    1bee:	83          	im 3
+    1bef:	e0          	im -32
+    1bf0:	c9          	im -55
+    1bf1:	34          	storeb
+
+00001bf2 <.LM679>:
+    1bf2:	e0          	im -32
+    1bf3:	0b          	nop
+    1bf4:	83          	im 3
+    1bf5:	e0          	im -32
+    1bf6:	ca          	im -54
+    1bf7:	34          	storeb
+
+00001bf8 <.LM680>:
+    1bf8:	80          	im 0
+    1bf9:	0b          	nop
+    1bfa:	83          	im 3
+    1bfb:	e0          	im -32
+    1bfc:	cb          	im -53
+    1bfd:	34          	storeb
+
+00001bfe <.LM681>:
+    1bfe:	84          	im 4
+    1bff:	52          	storesp 8
+    1c00:	83          	im 3
+    1c01:	e0          	im -32
+    1c02:	c8          	im -56
+    1c03:	51          	storesp 4
+    1c04:	b2          	im 50
+    1c05:	f3          	im -13
+    1c06:	3f          	callpcrel
+
+00001c07 <.LM682>:
+    1c07:	84          	im 4
+    1c08:	51          	storesp 4
+    1c09:	fa          	im -6
+    1c0a:	e6          	im -26
+    1c0b:	3f          	callpcrel
+
+00001c0c <.LM683>:
+    1c0c:	83          	im 3
+    1c0d:	e0          	im -32
+    1c0e:	c8          	im -56
+    1c0f:	33          	loadb
+    1c10:	51          	storesp 4
+    1c11:	b0          	im 48
+    1c12:	e9          	im -23
+    1c13:	3f          	callpcrel
+
+00001c14 <.LM684>:
+    1c14:	0b          	nop
+    1c15:	0b          	nop
+    1c16:	80          	im 0
+    1c17:	f9          	im -7
+    1c18:	a0          	im 32
+    1c19:	51          	storesp 4
+
+00001c1a <.L539>:
+    1c1a:	af          	im 47
+    1c1b:	d1          	im -47
+    1c1c:	3f          	callpcrel
+
+00001c1d <.LM686>:
+    1c1d:	ac          	im 44
+    1c1e:	bb          	im 59
+    1c1f:	3f          	callpcrel
+
+00001c20 <.L547>:
+    1c20:	aa          	im 42
+    1c21:	b6          	im 54
+    1c22:	3f          	callpcrel
+    1c23:	fd          	im -3
+    1c24:	c5          	im -59
+    1c25:	39          	poppcrel
+
+00001c26 <.L465>:
+    1c26:	73          	loadsp 12
+    1c27:	83          	im 3
+    1c28:	2e          	eq
+    1c29:	81          	im 1
+    1c2a:	f1          	im -15
+    1c2b:	38          	neqbranch
+    1c2c:	73          	loadsp 12
+    1c2d:	84          	im 4
+    1c2e:	2e          	eq
+    1c2f:	09          	not
+    1c30:	81          	im 1
+    1c31:	06          	and
+    1c32:	fd          	im -3
+    1c33:	ee          	im -18
+    1c34:	38          	neqbranch
+
+00001c35 <.LM689>:
+    1c35:	83          	im 3
+    1c36:	e0          	im -32
+    1c37:	b8          	im 56
+    1c38:	51          	storesp 4
+    1c39:	d6          	im -42
+    1c3a:	80          	im 0
+    1c3b:	3f          	callpcrel
+    1c3c:	fd          	im -3
+    1c3d:	e4          	im -28
+    1c3e:	39          	poppcrel
+
+00001c3f <.L520>:
+    1c3f:	73          	loadsp 12
+    1c40:	80          	im 0
+    1c41:	d3          	im -45
+    1c42:	2e          	eq
+    1c43:	fe          	im -2
+    1c44:	f3          	im -13
+    1c45:	38          	neqbranch
+
+00001c46 <.LM691>:
+    1c46:	aa          	im 42
+    1c47:	90          	im 16
+    1c48:	3f          	callpcrel
+    1c49:	fd          	im -3
+    1c4a:	9f          	im 31
+    1c4b:	39          	poppcrel
+
+00001c4c <.L462>:
+    1c4c:	83          	im 3
+    1c4d:	e3          	im -29
+    1c4e:	d8          	im -40
+    1c4f:	51          	storesp 4
+
+00001c50 <.LM693>:
+    1c50:	d5          	im -43
+    1c51:	e9          	im -23
+    1c52:	3f          	callpcrel
+    1c53:	fd          	im -3
+    1c54:	cd          	im -51
+    1c55:	39          	poppcrel
+
+00001c56 <.L478>:
+    1c56:	02          	pushsp
+    1c57:	b7          	im 55
+    1c58:	05          	add
+    1c59:	33          	loadb
+    1c5a:	70          	loadsp 0
+    1c5b:	88          	im 8
+    1c5c:	2b          	ashiftleft
+    1c5d:	81          	im 1
+    1c5e:	fe          	im -2
+    1c5f:	80          	im 0
+    1c60:	06          	and
+    1c61:	02          	pushsp
+    1c62:	88          	im 8
+    1c63:	05          	add
+    1c64:	b6          	im 54
+    1c65:	05          	add
+    1c66:	33          	loadb
+    1c67:	57          	storesp 28
+    1c68:	76          	loadsp 24
+    1c69:	05          	add
+    1c6a:	58          	storesp 32
+    1c6b:	58          	storesp 32
+
+00001c6c <.LM695>:
+    1c6c:	80          	im 0
+    1c6d:	55          	storesp 20
+
+00001c6e <.LM696>:
+    1c6e:	ab          	im 43
+    1c6f:	a5          	im 37
+    1c70:	3f          	callpcrel
+
+00001c71 <.LM697>:
+    1c71:	80          	im 0
+    1c72:	c1          	im -63
+    1c73:	51          	storesp 4
+    1c74:	aa          	im 42
+    1c75:	d1          	im -47
+    1c76:	3f          	callpcrel
+
+00001c77 <.LM698>:
+    1c77:	74          	loadsp 16
+    1c78:	91          	im 17
+    1c79:	3d          	pushspadd
+    1c7a:	23          	storeh
+
+00001c7b <.LM699>:
+    1c7b:	0b          	nop
+    1c7c:	0b          	nop
+    1c7d:	80          	im 0
+    1c7e:	f9          	im -7
+    1c7f:	a8          	im 40
+    1c80:	51          	storesp 4
+    1c81:	ae          	im 46
+    1c82:	ea          	im -22
+    1c83:	3f          	callpcrel
+
+00001c84 <.LM700>:
+    1c84:	76          	loadsp 24
+    1c85:	51          	storesp 4
+    1c86:	af          	im 47
+    1c87:	f4          	im -12
+    1c88:	3f          	callpcrel
+
+00001c89 <.LM701>:
+    1c89:	0b          	nop
+    1c8a:	0b          	nop
+    1c8b:	80          	im 0
+    1c8c:	f9          	im -7
+    1c8d:	b8          	im 56
+    1c8e:	51          	storesp 4
+    1c8f:	ae          	im 46
+    1c90:	dc          	im -36
+    1c91:	3f          	callpcrel
+
+00001c92 <.LM702>:
+    1c92:	83          	im 3
+    1c93:	e3          	im -29
+    1c94:	88          	im 8
+    1c95:	08          	load
+    1c96:	75          	loadsp 20
+    1c97:	2e          	eq
+    1c98:	09          	not
+    1c99:	81          	im 1
+    1c9a:	06          	and
+    1c9b:	82          	im 2
+    1c9c:	8e          	im 14
+    1c9d:	38          	neqbranch
+
+00001c9e <.LM703>:
+    1c9e:	83          	im 3
+    1c9f:	e3          	im -29
+    1ca0:	90          	im 16
+    1ca1:	08          	load
+    1ca2:	56          	storesp 24
+
+00001ca3 <.LM704>:
+    1ca3:	83          	im 3
+    1ca4:	77          	loadsp 28
+    1ca5:	25          	lessthanorequal
+    1ca6:	81          	im 1
+    1ca7:	cc          	im -52
+    1ca8:	38          	neqbranch
+
+00001ca9 <.LM705>:
+    1ca9:	83          	im 3
+    1caa:	e2          	im -30
+    1cab:	ec          	im -20
+    1cac:	33          	loadb
+    1cad:	83          	im 3
+    1cae:	e2          	im -30
+    1caf:	ed          	im -19
+    1cb0:	33          	loadb
+    1cb1:	71          	loadsp 4
+    1cb2:	88          	im 8
+    1cb3:	2b          	ashiftleft
+    1cb4:	07          	or
+    1cb5:	fc          	im -4
+    1cb6:	19          	addsp 36
+    1cb7:	71          	loadsp 4
+    1cb8:	29          	mult
+    1cb9:	78          	loadsp 32
+    1cba:	05          	add
+    1cbb:	83          	im 3
+    1cbc:	80          	im 0
+    1cbd:	05          	add
+
+00001cbe <.LM706>:
+    1cbe:	70          	loadsp 0
+    1cbf:	83          	im 3
+    1cc0:	ff          	im -1
+    1cc1:	ff          	im -1
+    1cc2:	06          	and
+    1cc3:	54          	storesp 16
+    1cc4:	58          	storesp 32
+    1cc5:	56          	storesp 24
+    1cc6:	58          	storesp 32
+    1cc7:	af          	im 47
+    1cc8:	b3          	im 51
+    1cc9:	3f          	callpcrel
+
+00001cca <.LM707>:
+    1cca:	0b          	nop
+    1ccb:	0b          	nop
+    1ccc:	80          	im 0
+    1ccd:	f9          	im -7
+    1cce:	c4          	im -60
+    1ccf:	51          	storesp 4
+    1cd0:	ae          	im 46
+    1cd1:	9b          	im 27
+    1cd2:	3f          	callpcrel
+
+00001cd3 <.LM708>:
+    1cd3:	75          	loadsp 20
+    1cd4:	51          	storesp 4
+    1cd5:	9a          	im 26
+    1cd6:	bc          	im 60
+    1cd7:	3f          	callpcrel
+
+00001cd8 <.LM709>:
+    1cd8:	7c          	loadsp 48
+    1cd9:	53          	storesp 12
+    1cda:	74          	loadsp 16
+    1cdb:	83          	im 3
+    1cdc:	ff          	im -1
+    1cdd:	ff          	im -1
+    1cde:	06          	and
+    1cdf:	70          	loadsp 0
+    1ce0:	53          	storesp 12
+    1ce1:	83          	im 3
+    1ce2:	e0          	im -32
+    1ce3:	c8          	im -56
+    1ce4:	52          	storesp 8
+    1ce5:	54          	storesp 16
+    1ce6:	98          	im 24
+    1ce7:	8d          	im 13
+    1ce8:	3f          	callpcrel
+
+00001ce9 <.L517>:
+    1ce9:	73          	loadsp 12
+    1cea:	51          	storesp 4
+    1ceb:	f9          	im -7
+    1cec:	84          	im 4
+    1ced:	3f          	callpcrel
+
+00001cee <.LM711>:
+    1cee:	73          	loadsp 12
+    1cef:	52          	storesp 8
+    1cf0:	84          	im 4
+    1cf1:	88          	im 8
+    1cf2:	80          	im 0
+    1cf3:	51          	storesp 4
+    1cf4:	d3          	im -45
+    1cf5:	fa          	im -6
+    1cf6:	3f          	callpcrel
+    1cf7:	83          	im 3
+    1cf8:	e0          	im -32
+    1cf9:	80          	im 0
+    1cfa:	08          	load
+    1cfb:	81          	im 1
+    1cfc:	ff          	im -1
+    1cfd:	06          	and
+
+00001cfe <.LM712>:
+    1cfe:	0b          	nop
+    1cff:	0b          	nop
+    1d00:	80          	im 0
+    1d01:	f9          	im -7
+    1d02:	b0          	im 48
+    1d03:	52          	storesp 8
+    1d04:	54          	storesp 16
+    1d05:	ad          	im 45
+    1d06:	e6          	im -26
+    1d07:	3f          	callpcrel
+
+00001d08 <.LM713>:
+    1d08:	73          	loadsp 12
+    1d09:	51          	storesp 4
+    1d0a:	ae          	im 46
+    1d0b:	f0          	im -16
+    1d0c:	3f          	callpcrel
+
+00001d0d <.LM714>:
+    1d0d:	0b          	nop
+    1d0e:	0b          	nop
+    1d0f:	80          	im 0
+    1d10:	f9          	im -7
+    1d11:	c4          	im -60
+    1d12:	51          	storesp 4
+
+00001d13 <.L552>:
+    1d13:	ad          	im 45
+    1d14:	d8          	im -40
+    1d15:	3f          	callpcrel
+
+00001d16 <.LM715>:
+    1d16:	aa          	im 42
+    1d17:	c2          	im -62
+    1d18:	3f          	callpcrel
+    1d19:	fe          	im -2
+    1d1a:	85          	im 5
+    1d1b:	39          	poppcrel
+
+00001d1c <.L463>:
+    1d1c:	83          	im 3
+    1d1d:	e2          	im -30
+    1d1e:	c8          	im -56
+    1d1f:	51          	storesp 4
+
+00001d20 <.LM717>:
+    1d20:	d4          	im -44
+    1d21:	99          	im 25
+    1d22:	3f          	callpcrel
+    1d23:	fb          	im -5
+    1d24:	fd          	im -3
+    1d25:	39          	poppcrel
+
+00001d26 <.L545>:
+    1d26:	83          	im 3
+    1d27:	e2          	im -30
+    1d28:	ea          	im -22
+    1d29:	33          	loadb
+    1d2a:	83          	im 3
+    1d2b:	e2          	im -30
+    1d2c:	eb          	im -21
+    1d2d:	33          	loadb
+    1d2e:	71          	loadsp 4
+    1d2f:	88          	im 8
+    1d30:	2b          	ashiftleft
+    1d31:	07          	or
+    1d32:	55          	storesp 20
+    1d33:	56          	storesp 24
+    1d34:	ad          	im 45
+    1d35:	80          	im 0
+    1d36:	74          	loadsp 16
+    1d37:	27          	ulessthanorequal
+    1d38:	fd          	im -3
+    1d39:	ad          	im 45
+    1d3a:	38          	neqbranch
+
+00001d3b <.LM719>:
+    1d3b:	81          	im 1
+    1d3c:	98          	im 24
+    1d3d:	55          	storesp 20
+
+00001d3e <.LM720>:
+    1d3e:	74          	loadsp 16
+    1d3f:	83          	im 3
+    1d40:	e0          	im -32
+    1d41:	c8          	im -56
+    1d42:	34          	storeb
+
+00001d43 <.LM721>:
+    1d43:	ff          	im -1
+    1d44:	0b          	nop
+    1d45:	83          	im 3
+    1d46:	e0          	im -32
+    1d47:	c9          	im -55
+    1d48:	34          	storeb
+
+00001d49 <.LM722>:
+    1d49:	e0          	im -32
+    1d4a:	0b          	nop
+    1d4b:	83          	im 3
+    1d4c:	e0          	im -32
+    1d4d:	ca          	im -54
+    1d4e:	34          	storeb
+
+00001d4f <.LM723>:
+    1d4f:	80          	im 0
+    1d50:	0b          	nop
+    1d51:	83          	im 3
+    1d52:	e0          	im -32
+    1d53:	cb          	im -53
+    1d54:	34          	storeb
+
+00001d55 <.LM724>:
+    1d55:	84          	im 4
+    1d56:	52          	storesp 8
+    1d57:	83          	im 3
+    1d58:	e0          	im -32
+    1d59:	c8          	im -56
+    1d5a:	51          	storesp 4
+    1d5b:	b0          	im 48
+    1d5c:	9c          	im 28
+    1d5d:	3f          	callpcrel
+
+00001d5e <.LM725>:
+    1d5e:	84          	im 4
+    1d5f:	51          	storesp 4
+    1d60:	f8          	im -8
+    1d61:	8f          	im 15
+    1d62:	3f          	callpcrel
+
+00001d63 <.LM726>:
+    1d63:	83          	im 3
+    1d64:	e0          	im -32
+    1d65:	c8          	im -56
+    1d66:	33          	loadb
+    1d67:	51          	storesp 4
+    1d68:	ae          	im 46
+    1d69:	92          	im 18
+    1d6a:	3f          	callpcrel
+
+00001d6b <.LM727>:
+    1d6b:	0b          	nop
+    1d6c:	0b          	nop
+    1d6d:	80          	im 0
+    1d6e:	f9          	im -7
+    1d6f:	a0          	im 32
+    1d70:	51          	storesp 4
+    1d71:	fd          	im -3
+    1d72:	a7          	im 39
+    1d73:	39          	poppcrel
+
+00001d74 <.L518>:
+    1d74:	76          	loadsp 24
+    1d75:	81          	im 1
+    1d76:	80          	im 0
+    1d77:	29          	mult
+    1d78:	16          	addsp 24
+    1d79:	ff          	im -1
+    1d7a:	80          	im 0
+    1d7b:	05          	add
+    1d7c:	56          	storesp 24
+
+00001d7d <.LM729>:
+    1d7d:	81          	im 1
+    1d7e:	80          	im 0
+
+00001d7f <.LM730>:
+    1d7f:	76          	loadsp 24
+    1d80:	83          	im 3
+    1d81:	ff          	im -1
+    1d82:	ff          	im -1
+    1d83:	06          	and
+    1d84:	52          	storesp 8
+    1d85:	55          	storesp 20
+    1d86:	ad          	im 45
+    1d87:	f4          	im -12
+    1d88:	3f          	callpcrel
+
+00001d89 <.LM731>:
+    1d89:	0b          	nop
+    1d8a:	0b          	nop
+    1d8b:	80          	im 0
+    1d8c:	f9          	im -7
+    1d8d:	c4          	im -60
+    1d8e:	51          	storesp 4
+    1d8f:	ac          	im 44
+    1d90:	dc          	im -36
+    1d91:	3f          	callpcrel
+
+00001d92 <.LM732>:
+    1d92:	75          	loadsp 20
+    1d93:	51          	storesp 4
+    1d94:	98          	im 24
+    1d95:	fd          	im -3
+    1d96:	3f          	callpcrel
+
+00001d97 <.LM733>:
+    1d97:	7c          	loadsp 48
+    1d98:	53          	storesp 12
+    1d99:	74          	loadsp 16
+    1d9a:	83          	im 3
+    1d9b:	ff          	im -1
+    1d9c:	ff          	im -1
+    1d9d:	06          	and
+    1d9e:	70          	loadsp 0
+    1d9f:	53          	storesp 12
+    1da0:	83          	im 3
+    1da1:	e0          	im -32
+    1da2:	c8          	im -56
+    1da3:	52          	storesp 8
+    1da4:	54          	storesp 16
+    1da5:	96          	im 22
+    1da6:	ce          	im -50
+    1da7:	3f          	callpcrel
+    1da8:	fe          	im -2
+    1da9:	bf          	im 63
+    1daa:	39          	poppcrel
+
+00001dab <.L546>:
+    1dab:	83          	im 3
+    1dac:	e3          	im -29
+    1dad:	94          	im 20
+    1dae:	08          	load
+    1daf:	80          	im 0
+    1db0:	fc          	im -4
+    1db1:	05          	add
+    1db2:	54          	storesp 16
+    1db3:	80          	im 0
+    1db4:	fd          	im -3
+    1db5:	52          	storesp 8
+    1db6:	73          	loadsp 12
+    1db7:	51          	storesp 4
+    1db8:	b0          	im 48
+    1db9:	c8          	im -56
+    1dba:	3f          	callpcrel
+    1dbb:	83          	im 3
+    1dbc:	e0          	im -32
+    1dbd:	80          	im 0
+    1dbe:	08          	load
+
+00001dbf <.LM735>:
+    1dbf:	0b          	nop
+    1dc0:	0b          	nop
+    1dc1:	80          	im 0
+    1dc2:	f5          	im -11
+    1dc3:	f0          	im -16
+    1dc4:	52          	storesp 8
+    1dc5:	5c          	storesp 48
+    1dc6:	ac          	im 44
+    1dc7:	a5          	im 37
+    1dc8:	3f          	callpcrel
+
+00001dc9 <.LM736>:
+    1dc9:	82          	im 2
+    1dca:	77          	loadsp 28
+    1dcb:	25          	lessthanorequal
+    1dcc:	81          	im 1
+    1dcd:	c0          	im -64
+    1dce:	38          	neqbranch
+
+00001dcf <.LM737>:
+    1dcf:	76          	loadsp 24
+    1dd0:	82          	im 2
+    1dd1:	e8          	im -24
+    1dd2:	2e          	eq
+    1dd3:	84          	im 4
+    1dd4:	8d          	im 13
+    1dd5:	38          	neqbranch
+
+00001dd6 <.LM738>:
+    1dd6:	76          	loadsp 24
+    1dd7:	82          	im 2
+    1dd8:	e9          	im -23
+    1dd9:	2e          	eq
+    1dda:	82          	im 2
+    1ddb:	86          	im 6
+    1ddc:	38          	neqbranch
+
+00001ddd <.LM739>:
+    1ddd:	76          	loadsp 24
+    1dde:	82          	im 2
+    1ddf:	f0          	im -16
+    1de0:	24          	lessthan
+    1de1:	ba          	im 58
+    1de2:	38          	neqbranch
+
+00001de3 <.L484>:
+    1de3:	0b          	nop
+    1de4:	0b          	nop
+    1de5:	80          	im 0
+    1de6:	f9          	im -7
+    1de7:	bc          	im 60
+    1de8:	51          	storesp 4
+    1de9:	ac          	im 44
+    1dea:	82          	im 2
+    1deb:	3f          	callpcrel
+
+00001dec <.LM741>:
+    1dec:	81          	im 1
+    1ded:	80          	im 0
+    1dee:	54          	storesp 16
+
+00001def <.L553>:
+    1def:	73          	loadsp 12
+    1df0:	51          	storesp 4
+    1df1:	f6          	im -10
+    1df2:	fe          	im -2
+    1df3:	3f          	callpcrel
+
+00001df4 <.LM743>:
+    1df4:	73          	loadsp 12
+    1df5:	52          	storesp 8
+    1df6:	84          	im 4
+    1df7:	88          	im 8
+    1df8:	80          	im 0
+    1df9:	51          	storesp 4
+    1dfa:	d1          	im -47
+    1dfb:	f4          	im -12
+    1dfc:	3f          	callpcrel
+    1dfd:	83          	im 3
+    1dfe:	e0          	im -32
+    1dff:	80          	im 0
+    1e00:	08          	load
+    1e01:	81          	im 1
+    1e02:	ff          	im -1
+    1e03:	06          	and
+
+00001e04 <.LM744>:
+    1e04:	0b          	nop
+    1e05:	0b          	nop
+    1e06:	80          	im 0
+    1e07:	f9          	im -7
+    1e08:	b0          	im 48
+    1e09:	52          	storesp 8
+    1e0a:	54          	storesp 16
+    1e0b:	ab          	im 43
+    1e0c:	e0          	im -32
+    1e0d:	3f          	callpcrel
+
+00001e0e <.LM745>:
+    1e0e:	73          	loadsp 12
+    1e0f:	51          	storesp 4
+    1e10:	ac          	im 44
+    1e11:	ea          	im -22
+    1e12:	3f          	callpcrel
+
+00001e13 <.LM746>:
+    1e13:	0b          	nop
+    1e14:	0b          	nop
+    1e15:	80          	im 0
+    1e16:	f9          	im -7
+    1e17:	c4          	im -60
+    1e18:	51          	storesp 4
+    1e19:	fd          	im -3
+    1e1a:	f8          	im -8
+    1e1b:	39          	poppcrel
+
+00001e1c <.L551>:
+    1e1c:	0b          	nop
+    1e1d:	0b          	nop
+    1e1e:	80          	im 0
+    1e1f:	f9          	im -7
+    1e20:	c8          	im -56
+    1e21:	51          	storesp 4
+    1e22:	ab          	im 43
+    1e23:	c9          	im -55
+    1e24:	3f          	callpcrel
+
+00001e25 <.LM748>:
+    1e25:	76          	loadsp 24
+    1e26:	80          	im 0
+    1e27:	fd          	im -3
+    1e28:	29          	mult
+    1e29:	fd          	im -3
+    1e2a:	97          	im 23
+    1e2b:	d3          	im -45
+    1e2c:	05          	add
+    1e2d:	51          	storesp 4
+    1e2e:	97          	im 23
+    1e2f:	e3          	im -29
+    1e30:	3f          	callpcrel
+
+00001e31 <.LM749>:
+    1e31:	7c          	loadsp 48
+    1e32:	53          	storesp 12
+    1e33:	80          	im 0
+    1e34:	fd          	im -3
+    1e35:	52          	storesp 8
+    1e36:	83          	im 3
+    1e37:	e0          	im -32
+    1e38:	c8          	im -56
+    1e39:	51          	storesp 4
+    1e3a:	95          	im 21
+    1e3b:	b9          	im 57
+    1e3c:	3f          	callpcrel
+
+00001e3d <.LM750>:
+    1e3d:	90          	im 16
+    1e3e:	3d          	pushspadd
+    1e3f:	22          	loadh
+    1e40:	70          	loadsp 0
+    1e41:	83          	im 3
+    1e42:	ff          	im -1
+    1e43:	ff          	im -1
+    1e44:	06          	and
+
+00001e45 <.LM751>:
+    1e45:	81          	im 1
+    1e46:	19          	addsp 36
+    1e47:	59          	storesp 36
+    1e48:	55          	storesp 20
+    1e49:	56          	storesp 24
+
+00001e4a <.LM752>:
+    1e4a:	73          	loadsp 12
+    1e4b:	80          	im 0
+    1e4c:	fc          	im -4
+    1e4d:	26          	ulessthan
+    1e4e:	83          	im 3
+    1e4f:	38          	neqbranch
+
+00001e50 <.LM753>:
+    1e50:	74          	loadsp 16
+    1e51:	57          	storesp 28
+
+00001e52 <.L516>:
+    1e52:	76          	loadsp 24
+    1e53:	88          	im 8
+    1e54:	2c          	ashiftright
+    1e55:	54          	storesp 16
+    1e56:	73          	loadsp 12
+    1e57:	83          	im 3
+    1e58:	e1          	im -31
+    1e59:	c5          	im -59
+    1e5a:	34          	storeb
+
+00001e5b <.LM755>:
+    1e5b:	76          	loadsp 24
+    1e5c:	83          	im 3
+    1e5d:	e1          	im -31
+    1e5e:	c6          	im -58
+    1e5f:	34          	storeb
+
+00001e60 <.LM756>:
+    1e60:	75          	loadsp 20
+    1e61:	83          	im 3
+    1e62:	e1          	im -31
+    1e63:	c7          	im -57
+    1e64:	34          	storeb
+
+00001e65 <.LM757>:
+    1e65:	0b          	nop
+    1e66:	0b          	nop
+    1e67:	80          	im 0
+    1e68:	f9          	im -7
+    1e69:	bc          	im 60
+    1e6a:	51          	storesp 4
+    1e6b:	ab          	im 43
+    1e6c:	80          	im 0
+    1e6d:	3f          	callpcrel
+
+00001e6e <.LM758>:
+    1e6e:	81          	im 1
+    1e6f:	80          	im 0
+    1e70:	54          	storesp 16
+    1e71:	fe          	im -2
+    1e72:	fc          	im -4
+    1e73:	39          	poppcrel
+
+00001e74 <.L469>:
+    1e74:	a8          	im 40
+    1e75:	0b          	nop
+    1e76:	83          	im 3
+    1e77:	e3          	im -29
+    1e78:	8c          	im 12
+    1e79:	0c          	store
+
+00001e7a <.LM760>:
+    1e7a:	0b          	nop
+    1e7b:	0b          	nop
+    1e7c:	80          	im 0
+    1e7d:	f8          	im -8
+    1e7e:	c4          	im -60
+    1e7f:	51          	storesp 4
+    1e80:	aa          	im 42
+    1e81:	eb          	im -21
+    1e82:	3f          	callpcrel
+
+00001e83 <.LM761>:
+    1e83:	83          	im 3
+    1e84:	e3          	im -29
+    1e85:	8e          	im 14
+    1e86:	22          	loadh
+    1e87:	51          	storesp 4
+    1e88:	ab          	im 43
+    1e89:	f2          	im -14
+    1e8a:	3f          	callpcrel
+    1e8b:	fa          	im -6
+    1e8c:	ab          	im 43
+    1e8d:	39          	poppcrel
+
+00001e8e <.L548>:
+    1e8e:	0b          	nop
+    1e8f:	0b          	nop
+    1e90:	80          	im 0
+    1e91:	f9          	im -7
+    1e92:	d0          	im -48
+    1e93:	51          	storesp 4
+    1e94:	aa          	im 42
+    1e95:	d7          	im -41
+    1e96:	3f          	callpcrel
+
+00001e97 <.LM763>:
+    1e97:	ff          	im -1
+    1e98:	17          	addsp 28
+    1e99:	70          	loadsp 0
+    1e9a:	87          	im 7
+    1e9b:	2b          	ashiftleft
+    1e9c:	83          	im 3
+    1e9d:	ff          	im -1
+    1e9e:	ff          	im -1
+    1e9f:	80          	im 0
+    1ea0:	06          	and
+    1ea1:	80          	im 0
+    1ea2:	f9          	im -7
+    1ea3:	f8          	im -8
+    1ea4:	05          	add
+
+00001ea5 <.LM764>:
+    1ea5:	83          	im 3
+    1ea6:	e0          	im -32
+    1ea7:	c8          	im -56
+    1ea8:	58          	storesp 32
+    1ea9:	56          	storesp 24
+    1eaa:	54          	storesp 16
+
+00001eab <.LM765>:
+    1eab:	81          	im 1
+    1eac:	80          	im 0
+    1ead:	54          	storesp 16
+
+00001eae <.L481>:
+    1eae:	74          	loadsp 16
+    1eaf:	70          	loadsp 0
+    1eb0:	81          	im 1
+    1eb1:	05          	add
+    1eb2:	56          	storesp 24
+    1eb3:	33          	loadb
+    1eb4:	76          	loadsp 24
+    1eb5:	70          	loadsp 0
+    1eb6:	81          	im 1
+    1eb7:	05          	add
+    1eb8:	58          	storesp 32
+    1eb9:	34          	storeb
+
+00001eba <.LM767>:
+    1eba:	ff          	im -1
+    1ebb:	14          	addsp 16
+    1ebc:	70          	loadsp 0
+    1ebd:	81          	im 1
+    1ebe:	ff          	im -1
+    1ebf:	06          	and
+    1ec0:	51          	storesp 4
+    1ec1:	54          	storesp 16
+
+00001ec2 <.LM768>:
+    1ec2:	73          	loadsp 12
+    1ec3:	80          	im 0
+    1ec4:	2e          	eq
+    1ec5:	fe          	im -2
+    1ec6:	9c          	im 28
+    1ec7:	38          	neqbranch
+
+00001ec8 <.LM769>:
+    1ec8:	74          	loadsp 16
+    1ec9:	70          	loadsp 0
+    1eca:	81          	im 1
+    1ecb:	05          	add
+    1ecc:	56          	storesp 24
+    1ecd:	33          	loadb
+    1ece:	76          	loadsp 24
+    1ecf:	70          	loadsp 0
+    1ed0:	81          	im 1
+    1ed1:	05          	add
+    1ed2:	58          	storesp 32
+    1ed3:	34          	storeb
+
+00001ed4 <.LM770>:
+    1ed4:	ff          	im -1
+    1ed5:	14          	addsp 16
+    1ed6:	70          	loadsp 0
+    1ed7:	81          	im 1
+    1ed8:	ff          	im -1
+    1ed9:	06          	and
+    1eda:	51          	storesp 4
+    1edb:	54          	storesp 16
+
+00001edc <.LM771>:
+    1edc:	73          	loadsp 12
+    1edd:	d0          	im -48
+    1ede:	38          	neqbranch
+    1edf:	fe          	im -2
+    1ee0:	82          	im 2
+    1ee1:	39          	poppcrel
+
+00001ee2 <.L550>:
+    1ee2:	0b          	nop
+    1ee3:	0b          	nop
+    1ee4:	80          	im 0
+    1ee5:	f9          	im -7
+    1ee6:	d8          	im -40
+    1ee7:	51          	storesp 4
+    1ee8:	aa          	im 42
+    1ee9:	83          	im 3
+    1eea:	3f          	callpcrel
+
+00001eeb <.LBB38>:
+    1eeb:	74          	loadsp 16
+    1eec:	75          	loadsp 20
+    1eed:	59          	storesp 36
+    1eee:	57          	storesp 28
+
+00001eef <.L502>:
+    1eef:	80          	im 0
+    1ef0:	0b          	nop
+    1ef1:	83          	im 3
+    1ef2:	e2          	im -30
+    1ef3:	d8          	im -40
+    1ef4:	18          	addsp 32
+    1ef5:	33          	loadb
+    1ef6:	70          	loadsp 0
+    1ef7:	81          	im 1
+    1ef8:	ff          	im -1
+    1ef9:	06          	and
+    1efa:	ff          	im -1
+    1efb:	bf          	im 63
+    1efc:	11          	addsp 4
+    1efd:	57          	storesp 28
+    1efe:	57          	storesp 28
+    1eff:	5b          	storesp 44
+    1f00:	5b          	storesp 44
+    1f01:	73          	loadsp 12
+    1f02:	99          	im 25
+    1f03:	26          	ulessthan
+    1f04:	83          	im 3
+    1f05:	38          	neqbranch
+    1f06:	81          	im 1
+    1f07:	5b          	storesp 44
+
+00001f08 <.L493>:
+    1f08:	80          	im 0
+    1f09:	0b          	nop
+    1f0a:	d0          	im -48
+    1f0b:	16          	addsp 24
+    1f0c:	55          	storesp 20
+    1f0d:	56          	storesp 24
+    1f0e:	73          	loadsp 12
+    1f0f:	89          	im 9
+    1f10:	26          	ulessthan
+    1f11:	83          	im 3
+    1f12:	38          	neqbranch
+    1f13:	81          	im 1
+    1f14:	56          	storesp 24
+
+00001f15 <.L494>:
+    1f15:	7a          	loadsp 40
+    1f16:	76          	loadsp 24
+    1f17:	07          	or
+    1f18:	54          	storesp 16
+    1f19:	73          	loadsp 12
+    1f1a:	80          	im 0
+    1f1b:	2e          	eq
+    1f1c:	8f          	im 15
+    1f1d:	38          	neqbranch
+
+00001f1e <.LM775>:
+    1f1e:	79          	loadsp 36
+    1f1f:	83          	im 3
+    1f20:	e0          	im -32
+    1f21:	c8          	im -56
+    1f22:	19          	addsp 36
+    1f23:	34          	storeb
+
+00001f24 <.LM776>:
+    1f24:	81          	im 1
+    1f25:	18          	addsp 32
+    1f26:	70          	loadsp 0
+    1f27:	81          	im 1
+    1f28:	ff          	im -1
+    1f29:	06          	and
+    1f2a:	59          	storesp 36
+    1f2b:	54          	storesp 16
+
+00001f2c <.L492>:
+    1f2c:	76          	loadsp 24
+    1f2d:	87          	im 7
+    1f2e:	32          	xor
+    1f2f:	70          	loadsp 0
+    1f30:	30          	neg
+    1f31:	70          	loadsp 0
+    1f32:	72          	loadsp 8
+    1f33:	07          	or
+    1f34:	80          	im 0
+    1f35:	25          	lessthanorequal
+    1f36:	79          	loadsp 36
+    1f37:	8a          	im 10
+    1f38:	32          	xor
+    1f39:	70          	loadsp 0
+    1f3a:	30          	neg
+    1f3b:	70          	loadsp 0
+    1f3c:	72          	loadsp 8
+    1f3d:	07          	or
+    1f3e:	80          	im 0
+    1f3f:	25          	lessthanorequal
+    1f40:	73          	loadsp 12
+    1f41:	07          	or
+    1f42:	53          	storesp 12
+    1f43:	54          	storesp 16
+    1f44:	59          	storesp 36
+    1f45:	51          	storesp 4
+    1f46:	56          	storesp 24
+    1f47:	54          	storesp 16
+    1f48:	74          	loadsp 16
+    1f49:	80          	im 0
+    1f4a:	2e          	eq
+    1f4b:	9a          	im 26
+    1f4c:	38          	neqbranch
+
+00001f4d <.LM778>:
+    1f4d:	77          	loadsp 28
+    1f4e:	77          	loadsp 28
+    1f4f:	26          	ulessthan
+    1f50:	95          	im 21
+    1f51:	38          	neqbranch
+
+00001f52 <.L554>:
+    1f52:	a0          	im 32
+    1f53:	0b          	nop
+    1f54:	83          	im 3
+    1f55:	e0          	im -32
+    1f56:	c8          	im -56
+    1f57:	19          	addsp 36
+    1f58:	34          	storeb
+    1f59:	81          	im 1
+    1f5a:	18          	addsp 32
+    1f5b:	70          	loadsp 0
+    1f5c:	81          	im 1
+    1f5d:	ff          	im -1
+    1f5e:	06          	and
+    1f5f:	59          	storesp 36
+    1f60:	54          	storesp 16
+    1f61:	76          	loadsp 24
+    1f62:	78          	loadsp 32
+    1f63:	27          	ulessthanorequal
+    1f64:	ed          	im -19
+    1f65:	38          	neqbranch
+
+00001f66 <.L491>:
+    1f66:	81          	im 1
+    1f67:	17          	addsp 28
+    1f68:	70          	loadsp 0
+    1f69:	81          	im 1
+    1f6a:	ff          	im -1
+    1f6b:	06          	and
+    1f6c:	58          	storesp 32
+    1f6d:	54          	storesp 16
+    1f6e:	8a          	im 10
+    1f6f:	77          	loadsp 28
+    1f70:	27          	ulessthanorequal
+    1f71:	fe          	im -2
+    1f72:	fc          	im -4
+    1f73:	38          	neqbranch
+
+00001f74 <.LM780>:
+    1f74:	8f          	im 15
+    1f75:	57          	storesp 28
+
+00001f76 <.L506>:
+    1f76:	83          	im 3
+    1f77:	e0          	im -32
+    1f78:	c3          	im -61
+    1f79:	17          	addsp 28
+    1f7a:	33          	loadb
+    1f7b:	83          	im 3
+    1f7c:	e0          	im -32
+    1f7d:	c8          	im -56
+    1f7e:	18          	addsp 32
+    1f7f:	34          	storeb
+    1f80:	ff          	im -1
+    1f81:	17          	addsp 28
+    1f82:	70          	loadsp 0
+    1f83:	81          	im 1
+    1f84:	ff          	im -1
+    1f85:	06          	and
+    1f86:	58          	storesp 32
+    1f87:	54          	storesp 16
+    1f88:	76          	loadsp 24
+    1f89:	84          	im 4
+    1f8a:	26          	ulessthan
+    1f8b:	ea          	im -22
+    1f8c:	38          	neqbranch
+
+00001f8d <.LM781>:
+    1f8d:	90          	im 16
+    1f8e:	57          	storesp 28
+
+00001f8f <.L510>:
+    1f8f:	80          	im 0
+    1f90:	0b          	nop
+    1f91:	83          	im 3
+    1f92:	e0          	im -32
+    1f93:	c8          	im -56
+    1f94:	18          	addsp 32
+    1f95:	34          	storeb
+
+00001f96 <.LM783>:
+    1f96:	81          	im 1
+    1f97:	17          	addsp 28
+    1f98:	70          	loadsp 0
+    1f99:	81          	im 1
+    1f9a:	ff          	im -1
+    1f9b:	06          	and
+    1f9c:	70          	loadsp 0
+    1f9d:	98          	im 24
+    1f9e:	2b          	ashiftleft
+    1f9f:	52          	storesp 8
+    1fa0:	58          	storesp 32
+    1fa1:	54          	storesp 16
+    1fa2:	73          	loadsp 12
+    1fa3:	80          	im 0
+    1fa4:	25          	lessthanorequal
+    1fa5:	e9          	im -23
+    1fa6:	38          	neqbranch
+
+00001fa7 <.LBE38>:
+    1fa7:	80          	im 0
+    1fa8:	c6          	im -58
+    1fa9:	54          	storesp 16
+    1faa:	7b          	loadsp 44
+    1fab:	85          	im 5
+    1fac:	8f          	im 15
+    1fad:	24          	lessthan
+    1fae:	84          	im 4
+    1faf:	38          	neqbranch
+    1fb0:	80          	im 0
+    1fb1:	c2          	im -62
+    1fb2:	54          	storesp 16
+
+00001fb3 <.L512>:
+    1fb3:	73          	loadsp 12
+    1fb4:	83          	im 3
+    1fb5:	e0          	im -32
+    1fb6:	c8          	im -56
+    1fb7:	34          	storeb
+
+00001fb8 <.LM785>:
+    1fb8:	80          	im 0
+    1fb9:	f1          	im -15
+    1fba:	0b          	nop
+    1fbb:	83          	im 3
+    1fbc:	e0          	im -32
+    1fbd:	cb          	im -53
+    1fbe:	34          	storeb
+    1fbf:	81          	im 1
+    1fc0:	0b          	nop
+    1fc1:	83          	im 3
+    1fc2:	e0          	im -32
+    1fc3:	cc          	im -52
+    1fc4:	34          	storeb
+
+00001fc5 <.L486>:
+    1fc5:	7b          	loadsp 44
+    1fc6:	83          	im 3
+    1fc7:	e0          	im -32
+    1fc8:	c9          	im -55
+    1fc9:	34          	storeb
+    1fca:	7b          	loadsp 44
+    1fcb:	88          	im 8
+    1fcc:	2c          	ashiftright
+    1fcd:	54          	storesp 16
+    1fce:	73          	loadsp 12
+    1fcf:	83          	im 3
+    1fd0:	e0          	im -32
+    1fd1:	ca          	im -54
+    1fd2:	34          	storeb
+
+00001fd3 <.L555>:
+    1fd3:	0b          	nop
+    1fd4:	0b          	nop
+    1fd5:	80          	im 0
+    1fd6:	f9          	im -7
+    1fd7:	bc          	im 60
+    1fd8:	51          	storesp 4
+    1fd9:	a8          	im 40
+    1fda:	92          	im 18
+    1fdb:	3f          	callpcrel
+
+00001fdc <.LM788>:
+    1fdc:	81          	im 1
+    1fdd:	80          	im 0
+    1fde:	54          	storesp 16
+    1fdf:	fc          	im -4
+    1fe0:	8e          	im 14
+    1fe1:	39          	poppcrel
+
+00001fe2 <.L549>:
+    1fe2:	0b          	nop
+    1fe3:	0b          	nop
+    1fe4:	80          	im 0
+    1fe5:	f9          	im -7
+    1fe6:	e0          	im -32
+    1fe7:	51          	storesp 4
+    1fe8:	a8          	im 40
+    1fe9:	83          	im 3
+    1fea:	3f          	callpcrel
+
+00001feb <.LM790>:
+    1feb:	7b          	loadsp 44
+    1fec:	83          	im 3
+    1fed:	e0          	im -32
+    1fee:	c9          	im -55
+    1fef:	34          	storeb
+    1ff0:	7b          	loadsp 44
+    1ff1:	88          	im 8
+    1ff2:	2c          	ashiftright
+    1ff3:	54          	storesp 16
+    1ff4:	73          	loadsp 12
+    1ff5:	83          	im 3
+    1ff6:	e0          	im -32
+    1ff7:	ca          	im -54
+    1ff8:	34          	storeb
+    1ff9:	d9          	im -39
+    1ffa:	39          	poppcrel
+
+00001ffb <main>:
+    1ffb:	ff          	im -1
+    1ffc:	3d          	pushspadd
+    1ffd:	0d          	popsp
+
+00001ffe <.LM792>:
+    1ffe:	80          	im 0
+    1fff:	0b          	nop
+    2000:	83          	im 3
+    2001:	e0          	im -32
+    2002:	ac          	im 44
+    2003:	0c          	store
+
+00002004 <.LM793>:
+    2004:	80          	im 0
+    2005:	0b          	nop
+    2006:	83          	im 3
+    2007:	e3          	im -29
+    2008:	a8          	im 40
+    2009:	0c          	store
+
+0000200a <.LM794>:
+    200a:	80          	im 0
+    200b:	0b          	nop
+    200c:	83          	im 3
+    200d:	e0          	im -32
+    200e:	b4          	im 52
+    200f:	0c          	store
+
+00002010 <.LM795>:
+    2010:	81          	im 1
+    2011:	51          	storesp 4
+    2012:	cc          	im -52
+    2013:	fa          	im -6
+    2014:	3f          	callpcrel
+
+00002015 <.LM796>:
+    2015:	a8          	im 40
+    2016:	0b          	nop
+    2017:	83          	im 3
+    2018:	e3          	im -29
+    2019:	8c          	im 12
+    201a:	0c          	store
+
+0000201b <.LM797>:
+    201b:	83          	im 3
+    201c:	e0          	im -32
+    201d:	ac          	im 44
+    201e:	08          	load
+    201f:	51          	storesp 4
+    2020:	a5          	im 37
+    2021:	bb          	im 59
+    2022:	3f          	callpcrel
+
+00002023 <.LM798>:
+    2023:	83          	im 3
+    2024:	e0          	im -32
+    2025:	ac          	im 44
+    2026:	08          	load
+    2027:	ab          	im 43
+    2028:	38          	neqbranch
+
+00002029 <.LM799>:
+    2029:	f3          	im -13
+    202a:	a8          	im 40
+    202b:	3f          	callpcrel
+
+0000202c <.LM800>:
+    202c:	81          	im 1
+    202d:	51          	storesp 4
+    202e:	cc          	im -52
+    202f:	de          	im -34
+    2030:	3f          	callpcrel
+
+00002031 <.LM801>:
+    2031:	80          	im 0
+    2032:	51          	storesp 4
+    2033:	cc          	im -52
+    2034:	b5          	im 53
+    2035:	3f          	callpcrel
+
+00002036 <.LM802>:
+    2036:	80          	im 0
+    2037:	fb          	im -5
+    2038:	e4          	im -28
+    2039:	08          	load
+    203a:	52          	storesp 8
+    203b:	80          	im 0
+    203c:	72          	loadsp 8
+    203d:	34          	storeb
+
+0000203e <.LM803>:
+    203e:	cb          	im -53
+    203f:	b0          	im 48
+    2040:	3f          	callpcrel
+
+00002041 <.LM804>:
+    2041:	81          	im 1
+    2042:	51          	storesp 4
+    2043:	cc          	im -52
+    2044:	a5          	im 37
+    2045:	3f          	callpcrel
+
+00002046 <.LM805>:
+    2046:	80          	im 0
+    2047:	51          	storesp 4
+    2048:	cc          	im -52
+    2049:	c4          	im -60
+    204a:	3f          	callpcrel
+
+0000204b <.L559>:
+    204b:	da          	im -38
+    204c:	8c          	im 12
+    204d:	3f          	callpcrel
+    204e:	da          	im -38
+    204f:	89          	im 9
+    2050:	3f          	callpcrel
+    2051:	f9          	im -7
+    2052:	39          	poppcrel
+
+00002053 <.L562>:
+    2053:	80          	im 0
+    2054:	51          	storesp 4
+    2055:	cc          	im -52
+    2056:	93          	im 19
+    2057:	3f          	callpcrel
+
+00002058 <.LM808>:
+    2058:	80          	im 0
+    2059:	fb          	im -5
+    205a:	e4          	im -28
+    205b:	08          	load
+    205c:	52          	storesp 8
+    205d:	80          	im 0
+    205e:	72          	loadsp 8
+    205f:	34          	storeb
+
+00002060 <.LM809>:
+    2060:	cb          	im -53
+    2061:	8e          	im 14
+    2062:	3f          	callpcrel
+
+00002063 <.LM810>:
+    2063:	81          	im 1
+    2064:	51          	storesp 4
+    2065:	cc          	im -52
+    2066:	83          	im 3
+    2067:	3f          	callpcrel
+
+00002068 <.LM811>:
+    2068:	80          	im 0
+    2069:	51          	storesp 4
+    206a:	cc          	im -52
+    206b:	a2          	im 34
+    206c:	3f          	callpcrel
+
+0000206d <.LM812>:
+    206d:	80          	im 0
+    206e:	fa          	im -6
+    206f:	89          	im 9
+    2070:	80          	im 0
+    2071:	51          	storesp 4
+    2072:	c8          	im -56
+    2073:	bf          	im 63
+    2074:	3f          	callpcrel
+
+00002075 <.LM813>:
+    2075:	f2          	im -14
+    2076:	dc          	im -36
+    2077:	3f          	callpcrel
+
+00002078 <.LM814>:
+    2078:	81          	im 1
+    2079:	51          	storesp 4
+    207a:	cc          	im -52
+    207b:	92          	im 18
+    207c:	3f          	callpcrel
+
+0000207d <.LM815>:
+    207d:	80          	im 0
+    207e:	51          	storesp 4
+    207f:	cb          	im -53
+    2080:	e9          	im -23
+    2081:	3f          	callpcrel
+
+00002082 <.LM816>:
+    2082:	80          	im 0
+    2083:	fb          	im -5
+    2084:	e4          	im -28
+    2085:	08          	load
+    2086:	52          	storesp 8
+    2087:	80          	im 0
+    2088:	72          	loadsp 8
+    2089:	34          	storeb
+
+0000208a <.LM817>:
+    208a:	ca          	im -54
+    208b:	e4          	im -28
+    208c:	3f          	callpcrel
+
+0000208d <.LM818>:
+    208d:	81          	im 1
+    208e:	51          	storesp 4
+    208f:	cb          	im -53
+    2090:	d9          	im -39
+    2091:	3f          	callpcrel
+
+00002092 <.LM819>:
+    2092:	80          	im 0
+    2093:	51          	storesp 4
+    2094:	cb          	im -53
+    2095:	f8          	im -8
+    2096:	3f          	callpcrel
+    2097:	ff          	im -1
+    2098:	b2          	im 50
+    2099:	39          	poppcrel
+
+0000209a <get_fat>:
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+    209a:	f7          	im -9
+    209b:	3d          	pushspadd
+    209c:	0d          	popsp
+    209d:	7b          	loadsp 44
+
+0000209e <.LM2>:
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+    209e:	83          	im 3
+    209f:	e0          	im -32
+    20a0:	90          	im 16
+    20a1:	08          	load
+    20a2:	57          	storesp 28
+    20a3:	58          	storesp 32
+
+000020a4 <.LM3>:
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+    20a4:	81          	im 1
+    20a5:	78          	loadsp 32
+    20a6:	27          	ulessthanorequal
+    20a7:	9c          	im 28
+    20a8:	38          	neqbranch
+    20a9:	77          	loadsp 28
+    20aa:	88          	im 8
+    20ab:	17          	addsp 28
+    20ac:	08          	load
+    20ad:	27          	ulessthanorequal
+    20ae:	95          	im 21
+    20af:	38          	neqbranch
+
+000020b0 <.LM4>:
+		return 1;
+
+	switch (fs->fs_type) {
+    20b0:	75          	loadsp 20
+    20b1:	33          	loadb
+    20b2:	57          	storesp 28
+    20b3:	76          	loadsp 24
+    20b4:	82          	im 2
+    20b5:	2e          	eq
+    20b6:	81          	im 1
+    20b7:	d0          	im -48
+    20b8:	38          	neqbranch
+    20b9:	76          	loadsp 24
+    20ba:	82          	im 2
+    20bb:	24          	lessthan
+    20bc:	91          	im 17
+    20bd:	38          	neqbranch
+    20be:	76          	loadsp 24
+    20bf:	81          	im 1
+    20c0:	2e          	eq
+    20c1:	80          	im 0
+    20c2:	e6          	im -26
+    20c3:	38          	neqbranch
+
+000020c4 <.L4>:
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+    20c4:	81          	im 1
+
+000020c5 <.LM6>:
+}
+    20c5:	0b          	nop
+    20c6:	83          	im 3
+    20c7:	e0          	im -32
+    20c8:	80          	im 0
+    20c9:	0c          	store
+    20ca:	8b          	im 11
+    20cb:	3d          	pushspadd
+    20cc:	0d          	popsp
+    20cd:	04          	poppc
+
+000020ce <.L17>:
+    20ce:	76          	loadsp 24
+    20cf:	83          	im 3
+    20d0:	2e          	eq
+    20d1:	09          	not
+    20d2:	81          	im 1
+    20d3:	06          	and
+    20d4:	ef          	im -17
+    20d5:	38          	neqbranch
+
+000020d6 <.LM8>:
+    20d6:	84          	im 4
+    20d7:	54          	storesp 16
+    20d8:	77          	loadsp 28
+    20d9:	82          	im 2
+    20da:	2b          	ashiftleft
+    20db:	83          	im 3
+    20dc:	fc          	im -4
+    20dd:	06          	and
+    20de:	53          	storesp 12
+    20df:	77          	loadsp 28
+    20e0:	87          	im 7
+    20e1:	2a          	lshiftright
+    20e2:	8c          	im 12
+    20e3:	17          	addsp 28
+    20e4:	08          	load
+    20e5:	05          	add
+    20e6:	52          	storesp 8
+    20e7:	8b          	im 11
+    20e8:	3d          	pushspadd
+    20e9:	fc          	im -4
+    20ea:	05          	add
+    20eb:	51          	storesp 4
+    20ec:	f0          	im -16
+    20ed:	91          	im 17
+    20ee:	3f          	callpcrel
+    20ef:	83          	im 3
+    20f0:	e0          	im -32
+    20f1:	80          	im 0
+    20f2:	08          	load
+    20f3:	d0          	im -48
+    20f4:	38          	neqbranch
+
+000020f5 <.LM9>:
+    20f5:	02          	pushsp
+    20f6:	a7          	im 39
+    20f7:	05          	add
+    20f8:	33          	loadb
+    20f9:	02          	pushsp
+    20fa:	84          	im 4
+    20fb:	05          	add
+    20fc:	a6          	im 38
+    20fd:	05          	add
+    20fe:	33          	loadb
+    20ff:	71          	loadsp 4
+    2100:	98          	im 24
+    2101:	2b          	ashiftleft
+    2102:	71          	loadsp 4
+    2103:	90          	im 16
+    2104:	2b          	ashiftleft
+    2105:	07          	or
+    2106:	02          	pushsp
+    2107:	8c          	im 12
+    2108:	05          	add
+    2109:	a5          	im 37
+    210a:	05          	add
+    210b:	33          	loadb
+    210c:	70          	loadsp 0
+    210d:	88          	im 8
+    210e:	2b          	ashiftleft
+    210f:	72          	loadsp 8
+    2110:	07          	or
+    2111:	8f          	im 15
+    2112:	3d          	pushspadd
+    2113:	33          	loadb
+    2114:	71          	loadsp 4
+    2115:	80          	im 0
+    2116:	ff          	im -1
+    2117:	ff          	im -1
+    2118:	fe          	im -2
+    2119:	80          	im 0
+    211a:	06          	and
+    211b:	07          	or
+
+0000211c <.LM10>:
+    211c:	83          	im 3
+    211d:	e0          	im -32
+    211e:	80          	im 0
+    211f:	0c          	store
+    2120:	52          	storesp 8
+    2121:	5c          	storesp 48
+    2122:	57          	storesp 28
+    2123:	58          	storesp 32
+    2124:	56          	storesp 24
+    2125:	8b          	im 11
+    2126:	3d          	pushspadd
+    2127:	0d          	popsp
+    2128:	04          	poppc
+
+00002129 <.L5>:
+    2129:	77          	loadsp 28
+    212a:	83          	im 3
+    212b:	ff          	im -1
+    212c:	ff          	im -1
+    212d:	06          	and
+    212e:	70          	loadsp 0
+    212f:	81          	im 1
+    2130:	2a          	lshiftright
+    2131:	11          	addsp 4
+    2132:	70          	loadsp 0
+    2133:	83          	im 3
+    2134:	ff          	im -1
+    2135:	ff          	im -1
+    2136:	06          	and
+
+00002137 <.LM12>:
+    2137:	70          	loadsp 0
+    2138:	83          	im 3
+    2139:	ff          	im -1
+    213a:	06          	and
+    213b:	71          	loadsp 4
+    213c:	89          	im 9
+    213d:	2a          	lshiftright
+    213e:	52          	storesp 8
+    213f:	5c          	storesp 48
+    2140:	51          	storesp 4
+    2141:	51          	storesp 4
+    2142:	55          	storesp 20
+
+00002143 <.LM13>:
+    2143:	78          	loadsp 32
+    2144:	83          	im 3
+    2145:	ff          	im -1
+    2146:	2e          	eq
+    2147:	80          	im 0
+    2148:	f2          	im -14
+    2149:	38          	neqbranch
+
+0000214a <.LM14>:
+    214a:	82          	im 2
+    214b:	54          	storesp 16
+    214c:	78          	loadsp 32
+    214d:	53          	storesp 12
+    214e:	8c          	im 12
+    214f:	16          	addsp 24
+    2150:	08          	load
+    2151:	15          	addsp 20
+    2152:	52          	storesp 8
+    2153:	8b          	im 11
+    2154:	3d          	pushspadd
+    2155:	fc          	im -4
+    2156:	05          	add
+    2157:	51          	storesp 4
+
+00002158 <.L18>:
+    2158:	ef          	im -17
+    2159:	a5          	im 37
+    215a:	3f          	callpcrel
+    215b:	83          	im 3
+    215c:	e0          	im -32
+    215d:	80          	im 0
+    215e:	08          	load
+    215f:	fe          	im -2
+    2160:	e3          	im -29
+    2161:	38          	neqbranch
+
+00002162 <.LM16>:
+    2162:	02          	pushsp
+    2163:	a5          	im 37
+    2164:	05          	add
+    2165:	33          	loadb
+    2166:	8b          	im 11
+    2167:	3d          	pushspadd
+    2168:	33          	loadb
+    2169:	71          	loadsp 4
+    216a:	88          	im 8
+    216b:	2b          	ashiftleft
+    216c:	07          	or
+
+0000216d <.LM17>:
+    216d:	79          	loadsp 36
+    216e:	81          	im 1
+    216f:	06          	and
+    2170:	71          	loadsp 4
+    2171:	84          	im 4
+    2172:	2a          	lshiftright
+    2173:	53          	storesp 12
+    2174:	57          	storesp 28
+    2175:	58          	storesp 32
+    2176:	56          	storesp 24
+    2177:	74          	loadsp 16
+    2178:	86          	im 6
+    2179:	38          	neqbranch
+    217a:	76          	loadsp 24
+    217b:	9f          	im 31
+    217c:	ff          	im -1
+    217d:	06          	and
+    217e:	56          	storesp 24
+
+0000217f <.L12>:
+    217f:	75          	loadsp 20
+
+00002180 <.LM18>:
+    2180:	83          	im 3
+    2181:	e0          	im -32
+    2182:	80          	im 0
+    2183:	0c          	store
+    2184:	8b          	im 11
+    2185:	3d          	pushspadd
+    2186:	0d          	popsp
+    2187:	04          	poppc
+
+00002188 <.L13>:
+    2188:	76          	loadsp 24
+    2189:	54          	storesp 16
+    218a:	77          	loadsp 28
+    218b:	10          	addsp 0
+    218c:	83          	im 3
+    218d:	fe          	im -2
+    218e:	06          	and
+    218f:	53          	storesp 12
+    2190:	77          	loadsp 28
+    2191:	88          	im 8
+    2192:	2a          	lshiftright
+    2193:	8c          	im 12
+    2194:	17          	addsp 28
+    2195:	08          	load
+    2196:	05          	add
+    2197:	52          	storesp 8
+    2198:	8b          	im 11
+    2199:	3d          	pushspadd
+    219a:	fc          	im -4
+    219b:	05          	add
+    219c:	51          	storesp 4
+    219d:	ee          	im -18
+    219e:	e0          	im -32
+    219f:	3f          	callpcrel
+    21a0:	83          	im 3
+    21a1:	e0          	im -32
+    21a2:	80          	im 0
+    21a3:	08          	load
+    21a4:	fe          	im -2
+    21a5:	9e          	im 30
+    21a6:	38          	neqbranch
+
+000021a7 <.LM20>:
+    21a7:	02          	pushsp
+    21a8:	a5          	im 37
+    21a9:	05          	add
+    21aa:	33          	loadb
+    21ab:	8b          	im 11
+    21ac:	3d          	pushspadd
+    21ad:	33          	loadb
+    21ae:	71          	loadsp 4
+    21af:	88          	im 8
+    21b0:	2b          	ashiftleft
+    21b1:	07          	or
+
+000021b2 <.LM21>:
+    21b2:	83          	im 3
+    21b3:	e0          	im -32
+    21b4:	80          	im 0
+    21b5:	0c          	store
+    21b6:	56          	storesp 24
+    21b7:	8b          	im 11
+    21b8:	3d          	pushspadd
+    21b9:	0d          	popsp
+    21ba:	04          	poppc
+
+000021bb <.L6>:
+    21bb:	76          	loadsp 24
+    21bc:	54          	storesp 16
+    21bd:	78          	loadsp 32
+    21be:	53          	storesp 12
+    21bf:	8c          	im 12
+    21c0:	16          	addsp 24
+    21c1:	08          	load
+    21c2:	15          	addsp 20
+    21c3:	52          	storesp 8
+    21c4:	8b          	im 11
+    21c5:	3d          	pushspadd
+    21c6:	fc          	im -4
+    21c7:	05          	add
+    21c8:	51          	storesp 4
+    21c9:	ee          	im -18
+    21ca:	b4          	im 52
+    21cb:	3f          	callpcrel
+    21cc:	83          	im 3
+    21cd:	e0          	im -32
+    21ce:	80          	im 0
+    21cf:	08          	load
+    21d0:	fd          	im -3
+    21d1:	f2          	im -14
+    21d2:	38          	neqbranch
+
+000021d3 <.LM23>:
+    21d3:	76          	loadsp 24
+    21d4:	54          	storesp 16
+    21d5:	83          	im 3
+    21d6:	e0          	im -32
+    21d7:	80          	im 0
+    21d8:	08          	load
+    21d9:	53          	storesp 12
+    21da:	8c          	im 12
+    21db:	16          	addsp 24
+    21dc:	08          	load
+    21dd:	15          	addsp 20
+    21de:	81          	im 1
+    21df:	05          	add
+    21e0:	52          	storesp 8
+    21e1:	8b          	im 11
+    21e2:	3d          	pushspadd
+    21e3:	fd          	im -3
+    21e4:	05          	add
+    21e5:	51          	storesp 4
+    21e6:	fe          	im -2
+    21e7:	f0          	im -16
+    21e8:	39          	poppcrel
+
+000021e9 <clust2sect>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+    21e9:	fb          	im -5
+    21ea:	3d          	pushspadd
+    21eb:	0d          	popsp
+
+000021ec <.LM25>:
+	FATFS *fs = FatFs;
+    21ec:	83          	im 3
+    21ed:	e0          	im -32
+    21ee:	90          	im 16
+    21ef:	08          	load
+
+000021f0 <.LM26>:
+
+
+	clst -= 2;
+    21f0:	fe          	im -2
+    21f1:	19          	addsp 36
+
+000021f2 <.LM27>:
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+    21f2:	88          	im 8
+    21f3:	12          	addsp 8
+    21f4:	08          	load
+    21f5:	fe          	im -2
+    21f6:	05          	add
+    21f7:	55          	storesp 20
+    21f8:	56          	storesp 24
+    21f9:	54          	storesp 16
+    21fa:	80          	im 0
+    21fb:	56          	storesp 24
+    21fc:	74          	loadsp 16
+    21fd:	73          	loadsp 12
+    21fe:	27          	ulessthanorequal
+    21ff:	8d          	im 13
+    2200:	38          	neqbranch
+
+00002201 <.LM28>:
+	return (DWORD)clst * fs->csize + fs->database;
+    2201:	82          	im 2
+    2202:	14          	addsp 16
+    2203:	33          	loadb
+    2204:	75          	loadsp 20
+    2205:	71          	loadsp 4
+    2206:	29          	mult
+    2207:	94          	im 20
+    2208:	16          	addsp 24
+    2209:	08          	load
+    220a:	05          	add
+    220b:	57          	storesp 28
+    220c:	53          	storesp 12
+
+0000220d <.L20>:
+}
+    220d:	75          	loadsp 20
+    220e:	83          	im 3
+    220f:	e0          	im -32
+    2210:	80          	im 0
+    2211:	0c          	store
+    2212:	87          	im 7
+    2213:	3d          	pushspadd
+    2214:	0d          	popsp
+    2215:	04          	poppc
+
+00002216 <dir_rewind>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+    2216:	fc          	im -4
+    2217:	3d          	pushspadd
+    2218:	0d          	popsp
+    2219:	76          	loadsp 24
+
+0000221a <.LM31>:
+	CLUST clst;
+	FATFS *fs = FatFs;
+    221a:	83          	im 3
+    221b:	e0          	im -32
+    221c:	90          	im 16
+    221d:	08          	load
+    221e:	55          	storesp 20
+    221f:	55          	storesp 20
+
+00002220 <.LM32>:
+
+
+	dj->index = 0;
+    2220:	80          	im 0
+    2221:	75          	loadsp 20
+    2222:	23          	storeh
+
+00002223 <.LM33>:
+	clst = dj->sclust;
+    2223:	88          	im 8
+    2224:	15          	addsp 20
+    2225:	08          	load
+    2226:	53          	storesp 12
+
+00002227 <.LM34>:
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+    2227:	72          	loadsp 8
+    2228:	81          	im 1
+    2229:	2e          	eq
+    222a:	88          	im 8
+    222b:	38          	neqbranch
+    222c:	88          	im 8
+    222d:	14          	addsp 16
+    222e:	08          	load
+    222f:	73          	loadsp 12
+    2230:	26          	ulessthan
+    2231:	8b          	im 11
+    2232:	38          	neqbranch
+
+00002233 <.L25>:
+		return FR_DISK_ERR;
+    2233:	81          	im 1
+
+00002234 <.LM36>:
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+    2234:	0b          	nop
+    2235:	83          	im 3
+    2236:	e0          	im -32
+    2237:	80          	im 0
+    2238:	0c          	store
+    2239:	86          	im 6
+    223a:	3d          	pushspadd
+    223b:	0d          	popsp
+    223c:	04          	poppc
+
+0000223d <.L24>:
+    223d:	72          	loadsp 8
+    223e:	90          	im 16
+    223f:	38          	neqbranch
+    2240:	73          	loadsp 12
+    2241:	33          	loadb
+    2242:	52          	storesp 8
+    2243:	71          	loadsp 4
+    2244:	83          	im 3
+    2245:	2e          	eq
+    2246:	09          	not
+    2247:	81          	im 1
+    2248:	06          	and
+    2249:	85          	im 5
+    224a:	38          	neqbranch
+
+0000224b <.LM38>:
+    224b:	90          	im 16
+    224c:	14          	addsp 16
+    224d:	08          	load
+    224e:	53          	storesp 12
+
+0000224f <.L26>:
+    224f:	72          	loadsp 8
+    2250:	8c          	im 12
+    2251:	16          	addsp 24
+    2252:	0c          	store
+
+00002253 <.LM40>:
+    2253:	72          	loadsp 8
+    2254:	80          	im 0
+    2255:	2e          	eq
+    2256:	98          	im 24
+    2257:	38          	neqbranch
+    2258:	72          	loadsp 8
+    2259:	51          	storesp 4
+    225a:	ff          	im -1
+    225b:	8d          	im 13
+    225c:	3f          	callpcrel
+    225d:	83          	im 3
+    225e:	e0          	im -32
+    225f:	80          	im 0
+    2260:	08          	load
+    2261:	90          	im 16
+    2262:	16          	addsp 24
+    2263:	0c          	store
+
+00002264 <.LM41>:
+    2264:	80          	im 0
+    2265:	52          	storesp 8
+
+00002266 <.L30>:
+    2266:	71          	loadsp 4
+    2267:	83          	im 3
+    2268:	e0          	im -32
+    2269:	80          	im 0
+    226a:	0c          	store
+    226b:	86          	im 6
+    226c:	3d          	pushspadd
+    226d:	0d          	popsp
+    226e:	04          	poppc
+
+0000226f <.L27>:
+    226f:	90          	im 16
+    2270:	14          	addsp 16
+    2271:	08          	load
+    2272:	90          	im 16
+    2273:	16          	addsp 24
+    2274:	0c          	store
+
+00002275 <.LM44>:
+    2275:	80          	im 0
+    2276:	52          	storesp 8
+    2277:	ee          	im -18
+    2278:	39          	poppcrel
+
+00002279 <dir_next>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+    2279:	fa          	im -6
+    227a:	3d          	pushspadd
+    227b:	0d          	popsp
+    227c:	78          	loadsp 32
+
+0000227d <.LM46>:
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+    227d:	83          	im 3
+    227e:	e0          	im -32
+    227f:	90          	im 16
+    2280:	08          	load
+
+00002281 <.LM47>:
+
+
+	i = dj->index + 1;
+    2281:	71          	loadsp 4
+    2282:	22          	loadh
+    2283:	81          	im 1
+    2284:	05          	add
+    2285:	70          	loadsp 0
+    2286:	83          	im 3
+    2287:	ff          	im -1
+    2288:	ff          	im -1
+    2289:	06          	and
+    228a:	57          	storesp 28
+    228b:	54          	storesp 16
+    228c:	57          	storesp 28
+    228d:	55          	storesp 20
+
+0000228e <.LM48>:
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+    228e:	73          	loadsp 12
+    228f:	80          	im 0
+    2290:	2e          	eq
+    2291:	b7          	im 55
+    2292:	38          	neqbranch
+    2293:	90          	im 16
+    2294:	15          	addsp 20
+    2295:	08          	load
+    2296:	53          	storesp 12
+    2297:	72          	loadsp 8
+    2298:	80          	im 0
+    2299:	2e          	eq
+    229a:	ae          	im 46
+    229b:	38          	neqbranch
+
+0000229c <.LM49>:
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+    229c:	73          	loadsp 12
+    229d:	8f          	im 15
+    229e:	06          	and
+    229f:	52          	storesp 8
+    22a0:	71          	loadsp 4
+    22a1:	99          	im 25
+    22a2:	38          	neqbranch
+
+000022a3 <.LM50>:
+		dj->sect++;			/* Next sector */
+    22a3:	81          	im 1
+    22a4:	13          	addsp 12
+    22a5:	90          	im 16
+    22a6:	16          	addsp 24
+    22a7:	0c          	store
+
+000022a8 <.LM51>:
+
+		if (dj->clust == 0) {	/* Static table */
+    22a8:	8c          	im 12
+    22a9:	15          	addsp 20
+    22aa:	08          	load
+    22ab:	53          	storesp 12
+    22ac:	72          	loadsp 8
+    22ad:	a5          	im 37
+    22ae:	38          	neqbranch
+
+000022af <.LM52>:
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+    22af:	83          	im 3
+
+000022b0 <.LM53>:
+    22b0:	0b          	nop
+    22b1:	84          	im 4
+    22b2:	17          	addsp 28
+    22b3:	22          	loadh
+    22b4:	57          	storesp 28
+    22b5:	52          	storesp 8
+    22b6:	73          	loadsp 12
+    22b7:	76          	loadsp 24
+    22b8:	27          	ulessthanorequal
+    22b9:	86          	im 6
+    22ba:	38          	neqbranch
+
+000022bb <.L34>:
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+    22bb:	73          	loadsp 12
+    22bc:	75          	loadsp 20
+    22bd:	23          	storeh
+
+000022be <.LM55>:
+
+	return FR_OK;
+    22be:	80          	im 0
+    22bf:	52          	storesp 8
+
+000022c0 <.L31>:
+}
+    22c0:	71          	loadsp 4
+    22c1:	83          	im 3
+    22c2:	e0          	im -32
+    22c3:	80          	im 0
+    22c4:	0c          	store
+    22c5:	88          	im 8
+    22c6:	3d          	pushspadd
+    22c7:	0d          	popsp
+    22c8:	04          	poppc
+
+000022c9 <.L33>:
+    22c9:	83          	im 3
+
+000022ca <.LM58>:
+    22ca:	0b          	nop
+    22cb:	83          	im 3
+    22cc:	e0          	im -32
+    22cd:	80          	im 0
+    22ce:	0c          	store
+    22cf:	88          	im 8
+    22d0:	3d          	pushspadd
+    22d1:	0d          	popsp
+    22d2:	04          	poppc
+
+000022d3 <.L35>:
+    22d3:	82          	im 2
+    22d4:	16          	addsp 24
+    22d5:	33          	loadb
+    22d6:	ff          	im -1
+    22d7:	05          	add
+    22d8:	74          	loadsp 16
+    22d9:	84          	im 4
+    22da:	2a          	lshiftright
+    22db:	06          	and
+    22dc:	52          	storesp 8
+    22dd:	71          	loadsp 4
+    22de:	dc          	im -36
+    22df:	38          	neqbranch
+
+000022e0 <.LM60>:
+    22e0:	72          	loadsp 8
+    22e1:	51          	storesp 4
+    22e2:	fb          	im -5
+    22e3:	b6          	im 54
+    22e4:	3f          	callpcrel
+
+000022e5 <.LM61>:
+    22e5:	81          	im 1
+    22e6:	52          	storesp 8
+    22e7:	71          	loadsp 4
+    22e8:	83          	im 3
+    22e9:	e0          	im -32
+    22ea:	80          	im 0
+    22eb:	08          	load
+    22ec:	27          	ulessthanorequal
+    22ed:	d2          	im -46
+    22ee:	38          	neqbranch
+
+000022ef <.LM62>:
+    22ef:	83          	im 3
+    22f0:	52          	storesp 8
+
+000022f1 <.LM63>:
+    22f1:	83          	im 3
+    22f2:	e0          	im -32
+    22f3:	80          	im 0
+    22f4:	08          	load
+    22f5:	88          	im 8
+    22f6:	17          	addsp 28
+    22f7:	08          	load
+    22f8:	27          	ulessthanorequal
+    22f9:	c6          	im -58
+    22fa:	38          	neqbranch
+
+000022fb <.LM64>:
+    22fb:	83          	im 3
+    22fc:	e0          	im -32
+    22fd:	80          	im 0
+    22fe:	08          	load
+    22ff:	8c          	im 12
+    2300:	16          	addsp 24
+    2301:	0c          	store
+
+00002302 <.LM65>:
+    2302:	83          	im 3
+    2303:	e0          	im -32
+    2304:	80          	im 0
+    2305:	08          	load
+    2306:	51          	storesp 4
+    2307:	fd          	im -3
+    2308:	e0          	im -32
+    2309:	3f          	callpcrel
+    230a:	83          	im 3
+    230b:	e0          	im -32
+    230c:	80          	im 0
+    230d:	08          	load
+    230e:	90          	im 16
+    230f:	16          	addsp 24
+    2310:	0c          	store
+
+00002311 <.LM66>:
+    2311:	73          	loadsp 12
+    2312:	75          	loadsp 20
+    2313:	23          	storeh
+
+00002314 <.LM67>:
+    2314:	80          	im 0
+    2315:	52          	storesp 8
+    2316:	ff          	im -1
+    2317:	a8          	im 40
+    2318:	39          	poppcrel
+
+00002319 <follow_path>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+    2319:	f2          	im -14
+    231a:	3d          	pushspadd
+    231b:	0d          	popsp
+    231c:	60          	loadsp 64
+    231d:	62          	loadsp 72
+
+0000231e <.LM69>:
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+    231e:	64          	loadsp 80
+    231f:	70          	loadsp 0
+    2320:	33          	loadb
+    2321:	58          	storesp 32
+    2322:	58          	storesp 32
+    2323:	5e          	storesp 56
+    2324:	5e          	storesp 56
+    2325:	74          	loadsp 16
+    2326:	a0          	im 32
+    2327:	2e          	eq
+    2328:	09          	not
+    2329:	81          	im 1
+    232a:	06          	and
+    232b:	8e          	im 14
+    232c:	38          	neqbranch
+
+0000232d <.L105>:
+    232d:	81          	im 1
+    232e:	16          	addsp 24
+    232f:	70          	loadsp 0
+    2330:	44          	storesp 80
+    2331:	70          	loadsp 0
+    2332:	33          	loadb
+    2333:	56          	storesp 24
+    2334:	56          	storesp 24
+    2335:	74          	loadsp 16
+    2336:	a0          	im 32
+    2337:	2e          	eq
+    2338:	f4          	im -12
+    2339:	38          	neqbranch
+
+0000233a <.L89>:
+	if (*path == '/') path++;			/* Strip heading separator */
+    233a:	75          	loadsp 20
+    233b:	33          	loadb
+    233c:	55          	storesp 20
+    233d:	74          	loadsp 16
+    233e:	af          	im 47
+    233f:	2e          	eq
+    2340:	82          	im 2
+    2341:	9c          	im 28
+    2342:	38          	neqbranch
+
+00002343 <.LM71>:
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+    2343:	80          	im 0
+    2344:	0b          	nop
+    2345:	88          	im 8
+    2346:	1f          	addsp 60
+    2347:	0c          	store
+
+00002348 <.LM72>:
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+    2348:	75          	loadsp 20
+    2349:	33          	loadb
+    234a:	55          	storesp 20
+    234b:	a0          	im 32
+    234c:	75          	loadsp 20
+    234d:	27          	ulessthanorequal
+    234e:	82          	im 2
+    234f:	a1          	im 33
+    2350:	38          	neqbranch
+
+00002351 <.L47>:
+    2351:	93          	im 19
+    2352:	3d          	pushspadd
+    2353:	84          	im 4
+    2354:	1f          	addsp 60
+    2355:	08          	load
+
+00002356 <.LBB2>:
+    2356:	70          	loadsp 0
+    2357:	58          	storesp 32
+    2358:	5c          	storesp 48
+    2359:	5f          	storesp 60
+
+0000235a <.LM74>:
+    235a:	8a          	im 10
+    235b:	55          	storesp 20
+
+0000235c <.L53>:
+    235c:	a0          	im 32
+    235d:	76          	loadsp 24
+    235e:	70          	loadsp 0
+    235f:	81          	im 1
+    2360:	05          	add
+    2361:	58          	storesp 32
+    2362:	34          	storeb
+    2363:	ff          	im -1
+    2364:	15          	addsp 20
+    2365:	55          	storesp 20
+    2366:	74          	loadsp 16
+    2367:	ff          	im -1
+    2368:	2e          	eq
+    2369:	09          	not
+    236a:	81          	im 1
+    236b:	06          	and
+    236c:	ef          	im -17
+    236d:	38          	neqbranch
+
+0000236e <.LBE4>:
+    236e:	80          	im 0
+    236f:	70          	loadsp 0
+    2370:	59          	storesp 36
+    2371:	59          	storesp 36
+    2372:	88          	im 8
+
+00002373 <.LM76>:
+    2373:	7f          	loadsp 60
+    2374:	08          	load
+    2375:	5d          	storesp 52
+    2376:	5a          	storesp 40
+
+00002377 <.L103>:
+    2377:	78          	loadsp 32
+    2378:	81          	im 1
+    2379:	1a          	addsp 40
+    237a:	70          	loadsp 0
+    237b:	81          	im 1
+    237c:	ff          	im -1
+    237d:	06          	and
+    237e:	7e          	loadsp 56
+    237f:	13          	addsp 12
+    2380:	70          	loadsp 0
+    2381:	33          	loadb
+
+00002382 <.LM78>:
+    2382:	70          	loadsp 0
+    2383:	af          	im 47
+    2384:	32          	xor
+    2385:	70          	loadsp 0
+    2386:	30          	neg
+    2387:	a0          	im 32
+    2388:	73          	loadsp 12
+    2389:	27          	ulessthanorequal
+    238a:	71          	loadsp 4
+    238b:	80          	im 0
+    238c:	25          	lessthanorequal
+    238d:	07          	or
+    238e:	51          	storesp 4
+    238f:	51          	storesp 4
+    2390:	52          	storesp 8
+    2391:	5b          	storesp 44
+    2392:	53          	storesp 12
+    2393:	5b          	storesp 44
+    2394:	57          	storesp 28
+    2395:	55          	storesp 20
+    2396:	74          	loadsp 16
+    2397:	80          	im 0
+    2398:	d3          	im -45
+    2399:	38          	neqbranch
+
+0000239a <.L109>:
+    239a:	76          	loadsp 24
+    239b:	ae          	im 46
+    239c:	2e          	eq
+    239d:	81          	im 1
+    239e:	e8          	im -24
+    239f:	38          	neqbranch
+    23a0:	77          	loadsp 28
+    23a1:	7a          	loadsp 40
+    23a2:	27          	ulessthanorequal
+    23a3:	75          	loadsp 20
+    23a4:	07          	or
+    23a5:	55          	storesp 20
+    23a6:	74          	loadsp 16
+    23a7:	80          	im 0
+    23a8:	2e          	eq
+    23a9:	81          	im 1
+    23aa:	e8          	im -24
+    23ab:	38          	neqbranch
+
+000023ac <.L111>:
+    23ac:	79          	loadsp 36
+    23ad:	88          	im 8
+    23ae:	32          	xor
+    23af:	70          	loadsp 0
+    23b0:	30          	neg
+    23b1:	78          	loadsp 32
+    23b2:	ae          	im 46
+    23b3:	32          	xor
+    23b4:	70          	loadsp 0
+    23b5:	30          	neg
+    23b6:	70          	loadsp 0
+    23b7:	73          	loadsp 12
+    23b8:	07          	or
+    23b9:	9f          	im 31
+    23ba:	2a          	lshiftright
+    23bb:	53          	storesp 12
+    23bc:	51          	storesp 4
+    23bd:	57          	storesp 28
+    23be:	51          	storesp 4
+    23bf:	56          	storesp 24
+    23c0:	75          	loadsp 20
+    23c1:	aa          	im 42
+    23c2:	38          	neqbranch
+
+000023c3 <.LM81>:
+    23c3:	88          	im 8
+    23c4:	58          	storesp 32
+    23c5:	8b          	im 11
+
+000023c6 <.LM82>:
+    23c6:	79          	loadsp 36
+    23c7:	81          	im 1
+    23c8:	1b          	addsp 44
+    23c9:	70          	loadsp 0
+    23ca:	81          	im 1
+    23cb:	ff          	im -1
+    23cc:	06          	and
+    23cd:	7f          	loadsp 60
+    23ce:	13          	addsp 12
+    23cf:	70          	loadsp 0
+    23d0:	33          	loadb
+
+000023d1 <.LM83>:
+    23d1:	70          	loadsp 0
+    23d2:	af          	im 47
+    23d3:	32          	xor
+    23d4:	70          	loadsp 0
+    23d5:	30          	neg
+    23d6:	a0          	im 32
+    23d7:	73          	loadsp 12
+    23d8:	27          	ulessthanorequal
+    23d9:	71          	loadsp 4
+    23da:	80          	im 0
+    23db:	25          	lessthanorequal
+    23dc:	07          	or
+    23dd:	51          	storesp 4
+    23de:	51          	storesp 4
+    23df:	52          	storesp 8
+    23e0:	5c          	storesp 48
+    23e1:	53          	storesp 12
+    23e2:	5c          	storesp 48
+    23e3:	58          	storesp 32
+    23e4:	56          	storesp 24
+    23e5:	5a          	storesp 40
+    23e6:	74          	loadsp 16
+    23e7:	80          	im 0
+    23e8:	2e          	eq
+    23e9:	ff          	im -1
+    23ea:	af          	im 47
+    23eb:	38          	neqbranch
+
+000023ec <.L56>:
+    23ec:	7b          	loadsp 44
+    23ed:	19          	addsp 36
+    23ee:	7f          	loadsp 60
+    23ef:	0c          	store
+
+000023f0 <.LM85>:
+    23f0:	80          	im 0
+    23f1:	55          	storesp 20
+    23f2:	76          	loadsp 24
+    23f3:	a0          	im 32
+    23f4:	26          	ulessthan
+    23f5:	83          	im 3
+    23f6:	38          	neqbranch
+    23f7:	81          	im 1
+    23f8:	55          	storesp 20
+
+000023f9 <.L69>:
+    23f9:	74          	loadsp 16
+    23fa:	8b          	im 11
+    23fb:	1c          	addsp 48
+    23fc:	34          	storeb
+
+000023fd <.LBB6>:
+    23fd:	7d          	loadsp 52
+    23fe:	51          	storesp 4
+    23ff:	fc          	im -4
+    2400:	95          	im 21
+    2401:	3f          	callpcrel
+    2402:	83          	im 3
+    2403:	e0          	im -32
+    2404:	80          	im 0
+    2405:	08          	load
+    2406:	5a          	storesp 40
+
+00002407 <.LM87>:
+    2407:	83          	im 3
+    2408:	e0          	im -32
+    2409:	80          	im 0
+    240a:	08          	load
+    240b:	80          	im 0
+    240c:	2e          	eq
+    240d:	81          	im 1
+    240e:	d9          	im -39
+    240f:	38          	neqbranch
+
+00002410 <.L73>:
+    2410:	79          	loadsp 36
+    2411:	56          	storesp 24
+
+00002412 <.LM89>:
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+    2412:	79          	loadsp 36
+    2413:	82          	im 2
+    2414:	b0          	im 48
+    2415:	38          	neqbranch
+
+00002416 <.L84>:
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+    2416:	84          	im 4
+    2417:	1e          	addsp 56
+    2418:	08          	load
+    2419:	8b          	im 11
+    241a:	11          	addsp 4
+    241b:	33          	loadb
+    241c:	56          	storesp 24
+    241d:	5b          	storesp 44
+    241e:	74          	loadsp 16
+    241f:	80          	im 0
+    2420:	dd          	im -35
+    2421:	38          	neqbranch
+
+00002422 <.LM91>:
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+    2422:	8b          	im 11
+    2423:	1d          	addsp 52
+    2424:	33          	loadb
+    2425:	70          	loadsp 0
+    2426:	84          	im 4
+    2427:	2a          	lshiftright
+    2428:	70          	loadsp 0
+    2429:	81          	im 1
+    242a:	06          	and
+    242b:	51          	storesp 4
+    242c:	56          	storesp 24
+    242d:	57          	storesp 28
+    242e:	74          	loadsp 16
+    242f:	80          	im 0
+    2430:	2e          	eq
+    2431:	82          	im 2
+    2432:	a7          	im 39
+    2433:	38          	neqbranch
+
+00002434 <.LM92>:
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+    2434:	95          	im 21
+    2435:	1d          	addsp 52
+    2436:	33          	loadb
+    2437:	94          	im 20
+    2438:	1e          	addsp 56
+    2439:	33          	loadb
+    243a:	71          	loadsp 4
+    243b:	98          	im 24
+    243c:	2b          	ashiftleft
+    243d:	71          	loadsp 4
+    243e:	90          	im 16
+    243f:	2b          	ashiftleft
+    2440:	07          	or
+    2441:	7f          	loadsp 60
+    2442:	9b          	im 27
+    2443:	05          	add
+    2444:	33          	loadb
+    2445:	60          	loadsp 64
+    2446:	9a          	im 26
+    2447:	05          	add
+    2448:	33          	loadb
+    2449:	71          	loadsp 4
+    244a:	88          	im 8
+    244b:	2b          	ashiftleft
+    244c:	07          	or
+    244d:	72          	loadsp 8
+    244e:	07          	or
+    244f:	62          	loadsp 72
+    2450:	88          	im 8
+    2451:	05          	add
+    2452:	0c          	store
+
+00002453 <.LM93>:
+    2453:	7e          	loadsp 56
+    2454:	52          	storesp 8
+    2455:	5a          	storesp 40
+    2456:	58          	storesp 32
+    2457:	56          	storesp 24
+    2458:	58          	storesp 32
+
+00002459 <.LM94>:
+    2459:	8a          	im 10
+    245a:	55          	storesp 20
+    245b:	fd          	im -3
+    245c:	ff          	im -1
+    245d:	39          	poppcrel
+
+0000245e <.L106>:
+    245e:	81          	im 1
+    245f:	16          	addsp 24
+    2460:	70          	loadsp 0
+    2461:	44          	storesp 80
+    2462:	56          	storesp 24
+
+00002463 <.LM96>:
+    2463:	80          	im 0
+    2464:	0b          	nop
+    2465:	88          	im 8
+    2466:	1f          	addsp 60
+    2467:	0c          	store
+
+00002468 <.LM97>:
+    2468:	75          	loadsp 20
+    2469:	33          	loadb
+    246a:	55          	storesp 20
+    246b:	74          	loadsp 16
+    246c:	a0          	im 32
+    246d:	26          	ulessthan
+    246e:	fd          	im -3
+    246f:	e1          	im -31
+    2470:	38          	neqbranch
+
+00002471 <.L107>:
+    2471:	7d          	loadsp 52
+    2472:	51          	storesp 4
+    2473:	fb          	im -5
+    2474:	a1          	im 33
+    2475:	3f          	callpcrel
+    2476:	83          	im 3
+    2477:	e0          	im -32
+    2478:	80          	im 0
+    2479:	08          	load
+    247a:	56          	storesp 24
+
+0000247b <.LM99>:
+    247b:	80          	im 0
+    247c:	7d          	loadsp 52
+    247d:	34          	storeb
+
+0000247e <.L48>:
+		}
+	}
+
+	return res;
+}
+    247e:	75          	loadsp 20
+    247f:	83          	im 3
+    2480:	e0          	im -32
+    2481:	80          	im 0
+    2482:	0c          	store
+    2483:	90          	im 16
+    2484:	3d          	pushspadd
+    2485:	0d          	popsp
+    2486:	04          	poppc
+
+00002487 <.L108>:
+    2487:	81          	im 1
+    2488:	70          	loadsp 0
+    2489:	79          	loadsp 36
+    248a:	7c          	loadsp 48
+    248b:	27          	ulessthanorequal
+    248c:	07          	or
+    248d:	51          	storesp 4
+    248e:	55          	storesp 20
+    248f:	74          	loadsp 16
+    2490:	fe          	im -2
+    2491:	9a          	im 26
+    2492:	38          	neqbranch
+
+00002493 <.L66>:
+    2493:	ff          	im -1
+    2494:	9f          	im 31
+    2495:	17          	addsp 28
+    2496:	55          	storesp 20
+    2497:	74          	loadsp 16
+    2498:	99          	im 25
+    2499:	26          	ulessthan
+    249a:	89          	im 9
+    249b:	38          	neqbranch
+    249c:	e0          	im -32
+    249d:	17          	addsp 28
+    249e:	70          	loadsp 0
+    249f:	81          	im 1
+    24a0:	ff          	im -1
+    24a1:	06          	and
+    24a2:	58          	storesp 32
+    24a3:	55          	storesp 20
+
+000024a4 <.L68>:
+    24a4:	77          	loadsp 28
+    24a5:	81          	im 1
+    24a6:	19          	addsp 36
+    24a7:	70          	loadsp 0
+    24a8:	81          	im 1
+    24a9:	ff          	im -1
+    24aa:	06          	and
+    24ab:	7d          	loadsp 52
+    24ac:	13          	addsp 12
+    24ad:	53          	storesp 12
+    24ae:	5a          	storesp 40
+    24af:	57          	storesp 28
+    24b0:	55          	storesp 20
+    24b1:	76          	loadsp 24
+    24b2:	75          	loadsp 20
+    24b3:	34          	storeb
+    24b4:	fd          	im -3
+    24b5:	c1          	im -63
+    24b6:	39          	poppcrel
+
+000024b7 <.L81>:
+    24b7:	ff          	im -1
+    24b8:	17          	addsp 28
+    24b9:	57          	storesp 28
+    24ba:	76          	loadsp 24
+    24bb:	ff          	im -1
+    24bc:	2e          	eq
+    24bd:	80          	im 0
+    24be:	fd          	im -3
+    24bf:	38          	neqbranch
+
+000024c0 <.L112>:
+    24c0:	78          	loadsp 32
+    24c1:	70          	loadsp 0
+    24c2:	81          	im 1
+    24c3:	05          	add
+    24c4:	5a          	storesp 40
+    24c5:	33          	loadb
+    24c6:	78          	loadsp 32
+    24c7:	70          	loadsp 0
+    24c8:	81          	im 1
+    24c9:	05          	add
+    24ca:	5a          	storesp 40
+    24cb:	33          	loadb
+    24cc:	71          	loadsp 4
+    24cd:	71          	loadsp 4
+    24ce:	31          	sub
+    24cf:	52          	storesp 8
+    24d0:	56          	storesp 24
+    24d1:	56          	storesp 24
+    24d2:	75          	loadsp 20
+    24d3:	80          	im 0
+    24d4:	2e          	eq
+    24d5:	e1          	im -31
+    24d6:	38          	neqbranch
+
+000024d7 <.L80>:
+    24d7:	7d          	loadsp 52
+    24d8:	51          	storesp 4
+    24d9:	fb          	im -5
+    24da:	9e          	im 30
+    24db:	3f          	callpcrel
+    24dc:	83          	im 3
+    24dd:	e0          	im -32
+    24de:	80          	im 0
+    24df:	08          	load
+    24e0:	5a          	storesp 40
+
+000024e1 <.LM106>:
+    24e1:	83          	im 3
+    24e2:	e0          	im -32
+    24e3:	80          	im 0
+    24e4:	08          	load
+    24e5:	fe          	im -2
+    24e6:	a9          	im 41
+    24e7:	38          	neqbranch
+
+000024e8 <.L74>:
+    24e8:	a0          	im 32
+    24e9:	54          	storesp 16
+    24ea:	7d          	loadsp 52
+    24eb:	22          	loadh
+    24ec:	70          	loadsp 0
+    24ed:	85          	im 5
+    24ee:	2b          	ashiftleft
+    24ef:	83          	im 3
+    24f0:	e0          	im -32
+    24f1:	06          	and
+    24f2:	54          	storesp 16
+    24f3:	55          	storesp 20
+    24f4:	90          	im 16
+    24f5:	1e          	addsp 56
+    24f6:	08          	load
+    24f7:	52          	storesp 8
+    24f8:	7c          	loadsp 48
+    24f9:	51          	storesp 4
+    24fa:	e8          	im -24
+    24fb:	83          	im 3
+    24fc:	3f          	callpcrel
+    24fd:	83          	im 3
+    24fe:	e0          	im -32
+    24ff:	80          	im 0
+    2500:	08          	load
+    2501:	5a          	storesp 40
+    2502:	83          	im 3
+    2503:	e0          	im -32
+    2504:	80          	im 0
+    2505:	08          	load
+    2506:	80          	im 0
+    2507:	dc          	im -36
+    2508:	38          	neqbranch
+
+00002509 <.LM108>:
+    2509:	7c          	loadsp 48
+    250a:	33          	loadb
+    250b:	55          	storesp 20
+
+0000250c <.LM109>:
+    250c:	74          	loadsp 16
+    250d:	80          	im 0
+    250e:	2e          	eq
+    250f:	80          	im 0
+    2510:	dd          	im -35
+    2511:	38          	neqbranch
+
+00002512 <.LM110>:
+    2512:	8b          	im 11
+    2513:	1d          	addsp 52
+    2514:	33          	loadb
+    2515:	70          	loadsp 0
+    2516:	83          	im 3
+    2517:	2a          	lshiftright
+    2518:	70          	loadsp 0
+    2519:	81          	im 1
+    251a:	06          	and
+    251b:	51          	storesp 4
+    251c:	56          	storesp 24
+    251d:	56          	storesp 24
+    251e:	74          	loadsp 16
+    251f:	ff          	im -1
+    2520:	b6          	im 54
+    2521:	38          	neqbranch
+
+00002522 <.LM111>:
+    2522:	8b          	im 11
+
+00002523 <.LM112>:
+    2523:	7d          	loadsp 52
+    2524:	7f          	loadsp 60
+    2525:	84          	im 4
+    2526:	05          	add
+    2527:	08          	load
+
+00002528 <.LM113>:
+    2528:	83          	im 3
+    2529:	e0          	im -32
+    252a:	80          	im 0
+    252b:	08          	load
+
+0000252c <.LM114>:
+    252c:	ff          	im -1
+    252d:	14          	addsp 16
+    252e:	54          	storesp 16
+    252f:	59          	storesp 36
+    2530:	5a          	storesp 40
+    2531:	5a          	storesp 40
+    2532:	57          	storesp 28
+    2533:	76          	loadsp 24
+    2534:	ff          	im -1
+    2535:	2e          	eq
+    2536:	09          	not
+    2537:	81          	im 1
+    2538:	06          	and
+    2539:	ff          	im -1
+    253a:	85          	im 5
+    253b:	38          	neqbranch
+
+0000253c <.L82>:
+    253c:	75          	loadsp 20
+    253d:	ff          	im -1
+    253e:	98          	im 24
+    253f:	38          	neqbranch
+    2540:	79          	loadsp 36
+    2541:	56          	storesp 24
+    2542:	fd          	im -3
+    2543:	d2          	im -46
+    2544:	39          	poppcrel
+
+00002545 <.L110>:
+    2545:	79          	loadsp 36
+    2546:	83          	im 3
+    2547:	2e          	eq
+    2548:	09          	not
+    2549:	81          	im 1
+    254a:	06          	and
+    254b:	fe          	im -2
+    254c:	b1          	im 49
+    254d:	38          	neqbranch
+    254e:	84          	im 4
+    254f:	1e          	addsp 56
+    2550:	08          	load
+    2551:	8b          	im 11
+    2552:	11          	addsp 4
+    2553:	33          	loadb
+    2554:	51          	storesp 4
+    2555:	55          	storesp 20
+    2556:	74          	loadsp 16
+    2557:	fe          	im -2
+    2558:	a5          	im 37
+    2559:	38          	neqbranch
+
+0000255a <.L102>:
+    255a:	84          	im 4
+
+0000255b <.LM118>:
+    255b:	0b          	nop
+    255c:	83          	im 3
+    255d:	e0          	im -32
+    255e:	80          	im 0
+    255f:	0c          	store
+    2560:	90          	im 16
+    2561:	3d          	pushspadd
+    2562:	0d          	popsp
+    2563:	04          	poppc
+
+00002564 <.L92>:
+    2564:	81          	im 1
+
+00002565 <.LM120>:
+    2565:	0b          	nop
+    2566:	83          	im 3
+    2567:	e0          	im -32
+    2568:	80          	im 0
+    2569:	0c          	store
+    256a:	90          	im 16
+    256b:	3d          	pushspadd
+    256c:	0d          	popsp
+    256d:	04          	poppc
+
+0000256e <.L93>:
+    256e:	83          	im 3
+
+0000256f <.LM122>:
+    256f:	0b          	nop
+    2570:	84          	im 4
+    2571:	1f          	addsp 60
+    2572:	08          	load
+    2573:	8b          	im 11
+    2574:	11          	addsp 4
+    2575:	33          	loadb
+    2576:	51          	storesp 4
+    2577:	56          	storesp 24
+    2578:	56          	storesp 24
+    2579:	74          	loadsp 16
+    257a:	fe          	im -2
+    257b:	82          	im 2
+    257c:	38          	neqbranch
+    257d:	dc          	im -36
+    257e:	39          	poppcrel
+
+0000257f <check_fs>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+    257f:	f8          	im -8
+    2580:	3d          	pushspadd
+    2581:	0d          	popsp
+    2582:	7a          	loadsp 40
+    2583:	7c          	loadsp 48
+    2584:	59          	storesp 36
+    2585:	57          	storesp 28
+
+00002586 <.LM124>:
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+    2586:	82          	im 2
+    2587:	54          	storesp 16
+    2588:	83          	im 3
+    2589:	fe          	im -2
+    258a:	53          	storesp 12
+    258b:	77          	loadsp 28
+    258c:	52          	storesp 8
+    258d:	76          	loadsp 24
+    258e:	51          	storesp 4
+    258f:	e6          	im -26
+    2590:	ee          	im -18
+    2591:	3f          	callpcrel
+
+00002592 <.LM125>:
+		return 3;
+    2592:	83          	im 3
+    2593:	56          	storesp 24
+
+00002594 <.LM126>:
+    2594:	83          	im 3
+    2595:	e0          	im -32
+    2596:	80          	im 0
+    2597:	08          	load
+    2598:	80          	im 0
+    2599:	ec          	im -20
+    259a:	38          	neqbranch
+
+0000259b <.LM127>:
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+    259b:	81          	im 1
+    259c:	17          	addsp 28
+    259d:	33          	loadb
+    259e:	77          	loadsp 28
+    259f:	33          	loadb
+    25a0:	71          	loadsp 4
+    25a1:	88          	im 8
+    25a2:	2b          	ashiftleft
+    25a3:	07          	or
+    25a4:	56          	storesp 24
+    25a5:	56          	storesp 24
+
+000025a6 <.LM128>:
+		return 2;
+    25a6:	82          	im 2
+    25a7:	56          	storesp 24
+
+000025a8 <.LM129>:
+    25a8:	74          	loadsp 16
+    25a9:	82          	im 2
+    25aa:	d4          	im -44
+    25ab:	d5          	im -43
+    25ac:	2e          	eq
+    25ad:	09          	not
+    25ae:	81          	im 1
+    25af:	06          	and
+    25b0:	80          	im 0
+    25b1:	d4          	im -44
+    25b2:	38          	neqbranch
+
+000025b3 <.LM130>:
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+    25b3:	75          	loadsp 20
+    25b4:	54          	storesp 16
+    25b5:	b6          	im 54
+    25b6:	53          	storesp 12
+    25b7:	77          	loadsp 28
+    25b8:	52          	storesp 8
+    25b9:	76          	loadsp 24
+    25ba:	51          	storesp 4
+    25bb:	e6          	im -26
+    25bc:	c2          	im -62
+    25bd:	3f          	callpcrel
+    25be:	83          	im 3
+    25bf:	e0          	im -32
+    25c0:	80          	im 0
+    25c1:	08          	load
+    25c2:	98          	im 24
+    25c3:	38          	neqbranch
+    25c4:	81          	im 1
+    25c5:	17          	addsp 28
+    25c6:	33          	loadb
+    25c7:	77          	loadsp 28
+    25c8:	33          	loadb
+    25c9:	71          	loadsp 4
+    25ca:	88          	im 8
+    25cb:	2b          	ashiftleft
+    25cc:	07          	or
+
+000025cd <.LM131>:
+		return 0;
+    25cd:	83          	im 3
+    25ce:	e0          	im -32
+    25cf:	80          	im 0
+    25d0:	08          	load
+    25d1:	52          	storesp 8
+    25d2:	56          	storesp 24
+    25d3:	56          	storesp 24
+
+000025d4 <.LM132>:
+    25d4:	74          	loadsp 16
+    25d5:	81          	im 1
+    25d6:	82          	im 2
+    25d7:	c6          	im -58
+    25d8:	2e          	eq
+    25d9:	ac          	im 44
+    25da:	38          	neqbranch
+
+000025db <.L116>:
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+    25db:	82          	im 2
+    25dc:	54          	storesp 16
+    25dd:	80          	im 0
+    25de:	d2          	im -46
+    25df:	53          	storesp 12
+    25e0:	77          	loadsp 28
+    25e1:	52          	storesp 8
+    25e2:	76          	loadsp 24
+    25e3:	51          	storesp 4
+    25e4:	e6          	im -26
+    25e5:	99          	im 25
+    25e6:	3f          	callpcrel
+    25e7:	83          	im 3
+    25e8:	e0          	im -32
+    25e9:	80          	im 0
+    25ea:	08          	load
+    25eb:	98          	im 24
+    25ec:	38          	neqbranch
+    25ed:	81          	im 1
+    25ee:	17          	addsp 28
+    25ef:	33          	loadb
+    25f0:	77          	loadsp 28
+    25f1:	33          	loadb
+    25f2:	71          	loadsp 4
+    25f3:	88          	im 8
+    25f4:	2b          	ashiftleft
+    25f5:	07          	or
+
+000025f6 <.LM134>:
+		return 0;
+    25f6:	83          	im 3
+    25f7:	e0          	im -32
+    25f8:	80          	im 0
+    25f9:	08          	load
+    25fa:	52          	storesp 8
+    25fb:	56          	storesp 24
+    25fc:	56          	storesp 24
+
+000025fd <.LM135>:
+    25fd:	74          	loadsp 16
+    25fe:	81          	im 1
+    25ff:	82          	im 2
+    2600:	c6          	im -58
+    2601:	2e          	eq
+    2602:	83          	im 3
+    2603:	38          	neqbranch
+
+00002604 <.L117>:
+	return 1;
+    2604:	81          	im 1
+    2605:	56          	storesp 24
+
+00002606 <.L113>:
+}
+    2606:	75          	loadsp 20
+    2607:	83          	im 3
+    2608:	e0          	im -32
+    2609:	80          	im 0
+    260a:	0c          	store
+    260b:	8a          	im 10
+    260c:	3d          	pushspadd
+    260d:	0d          	popsp
+    260e:	04          	poppc
+
+0000260f <pf_mount>:
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+    260f:	ec          	im -20
+    2610:	3d          	pushspadd
+    2611:	0d          	popsp
+    2612:	66          	loadsp 88
+    2613:	58          	storesp 32
+
+00002614 <.LM139>:
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+    2614:	80          	im 0
+    2615:	0b          	nop
+    2616:	83          	im 3
+    2617:	e0          	im -32
+    2618:	90          	im 16
+    2619:	0c          	store
+
+0000261a <.LM140>:
+	if (!fs) return FR_OK;				/* Unregister fs object */
+    261a:	77          	loadsp 28
+    261b:	56          	storesp 24
+    261c:	77          	loadsp 28
+    261d:	80          	im 0
+    261e:	2e          	eq
+    261f:	82          	im 2
+    2620:	d3          	im -45
+    2621:	38          	neqbranch
+
+00002622 <.LM141>:
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+    2622:	c1          	im -63
+    2623:	8c          	im 12
+    2624:	3f          	callpcrel
+    2625:	83          	im 3
+    2626:	e0          	im -32
+    2627:	80          	im 0
+    2628:	08          	load
+    2629:	81          	im 1
+    262a:	06          	and
+    262b:	55          	storesp 20
+
+0000262c <.LM142>:
+		return FR_NOT_READY;
+    262c:	82          	im 2
+    262d:	56          	storesp 24
+
+0000262e <.LM143>:
+    262e:	74          	loadsp 16
+    262f:	82          	im 2
+    2630:	c3          	im -61
+    2631:	38          	neqbranch
+
+00002632 <.LM144>:
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+    2632:	74          	loadsp 16
+
+00002633 <.LM145>:
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+    2633:	75          	loadsp 20
+    2634:	53          	storesp 12
+    2635:	8e          	im 14
+    2636:	3d          	pushspadd
+    2637:	70          	loadsp 0
+    2638:	53          	storesp 12
+    2639:	58          	storesp 32
+    263a:	59          	storesp 36
+    263b:	fe          	im -2
+    263c:	c2          	im -62
+    263d:	3f          	callpcrel
+    263e:	83          	im 3
+    263f:	e0          	im -32
+    2640:	80          	im 0
+    2641:	08          	load
+    2642:	81          	im 1
+    2643:	ff          	im -1
+    2644:	06          	and
+    2645:	56          	storesp 24
+
+00002646 <.LM146>:
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+    2646:	75          	loadsp 20
+    2647:	81          	im 1
+    2648:	2e          	eq
+    2649:	82          	im 2
+    264a:	b2          	im 50
+    264b:	38          	neqbranch
+
+0000264c <.LM147>:
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+    264c:	75          	loadsp 20
+    264d:	83          	im 3
+    264e:	2e          	eq
+    264f:	83          	im 3
+    2650:	88          	im 8
+    2651:	38          	neqbranch
+
+00002652 <.L126>:
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+    2652:	75          	loadsp 20
+    2653:	83          	im 3
+    2654:	8e          	im 14
+    2655:	38          	neqbranch
+
+00002656 <.LM149>:
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+    2656:	a4          	im 36
+    2657:	54          	storesp 16
+    2658:	8d          	im 13
+    2659:	53          	storesp 12
+    265a:	78          	loadsp 32
+    265b:	52          	storesp 8
+    265c:	76          	loadsp 24
+    265d:	51          	storesp 4
+    265e:	e5          	im -27
+    265f:	9f          	im 31
+    2660:	3f          	callpcrel
+    2661:	81          	im 1
+    2662:	56          	storesp 24
+    2663:	83          	im 3
+    2664:	e0          	im -32
+    2665:	80          	im 0
+    2666:	08          	load
+    2667:	82          	im 2
+    2668:	8b          	im 11
+    2669:	38          	neqbranch
+
+0000266a <.LM150>:
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+    266a:	02          	pushsp
+    266b:	ba          	im 58
+    266c:	05          	add
+    266d:	33          	loadb
+    266e:	02          	pushsp
+    266f:	84          	im 4
+    2670:	05          	add
+    2671:	b9          	im 57
+    2672:	05          	add
+    2673:	33          	loadb
+    2674:	71          	loadsp 4
+    2675:	88          	im 8
+    2676:	2b          	ashiftleft
+    2677:	07          	or
+    2678:	58          	storesp 32
+    2679:	5c          	storesp 48
+
+0000267a <.LM151>:
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+    267a:	76          	loadsp 24
+    267b:	ab          	im 43
+    267c:	38          	neqbranch
+    267d:	02          	pushsp
+    267e:	80          	im 0
+    267f:	ca          	im -54
+    2680:	05          	add
+    2681:	33          	loadb
+    2682:	02          	pushsp
+    2683:	84          	im 4
+    2684:	05          	add
+    2685:	80          	im 0
+    2686:	c9          	im -55
+    2687:	05          	add
+    2688:	33          	loadb
+    2689:	71          	loadsp 4
+    268a:	98          	im 24
+    268b:	2b          	ashiftleft
+    268c:	71          	loadsp 4
+    268d:	90          	im 16
+    268e:	2b          	ashiftleft
+    268f:	07          	or
+    2690:	96          	im 22
+    2691:	3d          	pushspadd
+    2692:	33          	loadb
+    2693:	70          	loadsp 0
+    2694:	88          	im 8
+    2695:	2b          	ashiftleft
+    2696:	72          	loadsp 8
+    2697:	07          	or
+    2698:	02          	pushsp
+    2699:	94          	im 20
+    269a:	05          	add
+    269b:	80          	im 0
+    269c:	c7          	im -57
+    269d:	05          	add
+    269e:	33          	loadb
+    269f:	71          	loadsp 4
+    26a0:	07          	or
+    26a1:	54          	storesp 16
+    26a2:	52          	storesp 8
+    26a3:	5d          	storesp 52
+    26a4:	57          	storesp 28
+    26a5:	58          	storesp 32
+    26a6:	56          	storesp 24
+
+000026a7 <.L129>:
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+    26a7:	02          	pushsp
+    26a8:	b3          	im 51
+    26a9:	05          	add
+    26aa:	33          	loadb
+    26ab:	77          	loadsp 28
+    26ac:	71          	loadsp 4
+    26ad:	29          	mult
+
+000026ae <.LM153>:
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+    26ae:	02          	pushsp
+    26af:	88          	im 8
+    26b0:	05          	add
+    26b1:	b2          	im 50
+    26b2:	05          	add
+    26b3:	33          	loadb
+    26b4:	02          	pushsp
+    26b5:	8c          	im 12
+    26b6:	05          	add
+    26b7:	b1          	im 49
+    26b8:	05          	add
+    26b9:	33          	loadb
+    26ba:	71          	loadsp 4
+    26bb:	88          	im 8
+    26bc:	2b          	ashiftleft
+    26bd:	07          	or
+    26be:	7c          	loadsp 48
+    26bf:	11          	addsp 4
+    26c0:	70          	loadsp 0
+    26c1:	8c          	im 12
+    26c2:	1e          	addsp 56
+    26c3:	0c          	store
+    26c4:	5e          	storesp 56
+    26c5:	59          	storesp 36
+    26c6:	57          	storesp 28
+    26c7:	58          	storesp 32
+    26c8:	5c          	storesp 48
+
+000026c9 <.LM154>:
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+    26c9:	8d          	im 13
+    26ca:	3d          	pushspadd
+    26cb:	33          	loadb
+    26cc:	82          	im 2
+    26cd:	19          	addsp 36
+    26ce:	34          	storeb
+
+000026cf <.LM155>:
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+    26cf:	02          	pushsp
+    26d0:	b5          	im 53
+    26d1:	05          	add
+    26d2:	33          	loadb
+    26d3:	8f          	im 15
+    26d4:	3d          	pushspadd
+    26d5:	33          	loadb
+    26d6:	71          	loadsp 4
+    26d7:	88          	im 8
+    26d8:	2b          	ashiftleft
+    26d9:	07          	or
+    26da:	5a          	storesp 40
+    26db:	5b          	storesp 44
+    26dc:	78          	loadsp 32
+    26dd:	84          	im 4
+    26de:	19          	addsp 36
+    26df:	23          	storeh
+
+000026e0 <.LM156>:
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+    26e0:	02          	pushsp
+    26e1:	b7          	im 55
+    26e2:	05          	add
+    26e3:	33          	loadb
+    26e4:	02          	pushsp
+    26e5:	84          	im 4
+    26e6:	05          	add
+    26e7:	b6          	im 54
+    26e8:	05          	add
+    26e9:	33          	loadb
+    26ea:	71          	loadsp 4
+    26eb:	88          	im 8
+    26ec:	2b          	ashiftleft
+    26ed:	07          	or
+    26ee:	56          	storesp 24
+    26ef:	5b          	storesp 44
+
+000026f0 <.LM157>:
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+    26f0:	74          	loadsp 16
+    26f1:	ab          	im 43
+    26f2:	38          	neqbranch
+    26f3:	02          	pushsp
+    26f4:	80          	im 0
+    26f5:	c6          	im -58
+    26f6:	05          	add
+    26f7:	33          	loadb
+    26f8:	02          	pushsp
+    26f9:	84          	im 4
+    26fa:	05          	add
+    26fb:	80          	im 0
+    26fc:	c5          	im -59
+    26fd:	05          	add
+    26fe:	33          	loadb
+    26ff:	71          	loadsp 4
+    2700:	98          	im 24
+    2701:	2b          	ashiftleft
+    2702:	71          	loadsp 4
+    2703:	90          	im 16
+    2704:	2b          	ashiftleft
+    2705:	07          	or
+    2706:	95          	im 21
+    2707:	3d          	pushspadd
+    2708:	33          	loadb
+    2709:	70          	loadsp 0
+    270a:	88          	im 8
+    270b:	2b          	ashiftleft
+    270c:	72          	loadsp 8
+    270d:	07          	or
+    270e:	02          	pushsp
+    270f:	94          	im 20
+    2710:	05          	add
+    2711:	80          	im 0
+    2712:	c3          	im -61
+    2713:	05          	add
+    2714:	33          	loadb
+    2715:	71          	loadsp 4
+    2716:	07          	or
+    2717:	51          	storesp 4
+    2718:	52          	storesp 8
+    2719:	53          	storesp 12
+    271a:	57          	storesp 28
+    271b:	5d          	storesp 52
+    271c:	5b          	storesp 44
+
+0000271d <.L130>:
+	mclst = (tsect						/* Last cluster# + 1 */
+    271d:	74          	loadsp 16
+    271e:	76          	loadsp 24
+    271f:	31          	sub
+    2720:	77          	loadsp 28
+    2721:	31          	sub
+    2722:	79          	loadsp 36
+    2723:	84          	im 4
+    2724:	2a          	lshiftright
+    2725:	8f          	im 15
+    2726:	3d          	pushspadd
+    2727:	33          	loadb
+    2728:	54          	storesp 16
+    2729:	71          	loadsp 4
+    272a:	71          	loadsp 4
+    272b:	31          	sub
+    272c:	53          	storesp 12
+    272d:	56          	storesp 24
+    272e:	56          	storesp 24
+    272f:	9d          	im 29
+    2730:	d1          	im -47
+    2731:	3f          	callpcrel
+    2732:	83          	im 3
+    2733:	e0          	im -32
+    2734:	80          	im 0
+    2735:	08          	load
+    2736:	82          	im 2
+    2737:	05          	add
+
+00002738 <.LM159>:
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+    2738:	70          	loadsp 0
+    2739:	88          	im 8
+    273a:	1a          	addsp 40
+    273b:	0c          	store
+
+0000273c <.LM160>:
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+    273c:	70          	loadsp 0
+    273d:	9f          	im 31
+    273e:	f6          	im -10
+    273f:	26          	ulessthan
+    2740:	81          	im 1
+    2741:	05          	add
+    2742:	57          	storesp 28
+    2743:	55          	storesp 20
+
+00002744 <.LM161>:
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+    2744:	83          	im 3
+    2745:	ff          	im -1
+    2746:	f6          	im -10
+    2747:	75          	loadsp 20
+    2748:	27          	ulessthanorequal
+    2749:	83          	im 3
+    274a:	38          	neqbranch
+
+0000274b <.LM162>:
+#if _FS_FAT32
+		fmt = FS_FAT32;
+    274b:	83          	im 3
+    274c:	56          	storesp 24
+
+0000274d <.L132>:
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+    274d:	75          	loadsp 20
+    274e:	78          	loadsp 32
+    274f:	34          	storeb
+
+00002750 <.LM164>:
+	if (_FS_FAT32 && fmt == FS_FAT32)
+    2750:	75          	loadsp 20
+    2751:	83          	im 3
+    2752:	2e          	eq
+    2753:	81          	im 1
+    2754:	98          	im 24
+    2755:	38          	neqbranch
+
+00002756 <.LM165>:
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+    2756:	76          	loadsp 24
+    2757:	1a          	addsp 40
+    2758:	90          	im 16
+    2759:	19          	addsp 36
+    275a:	0c          	store
+
+0000275b <.LM166>:
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+    275b:	84          	im 4
+    275c:	18          	addsp 32
+    275d:	22          	loadh
+    275e:	77          	loadsp 28
+    275f:	1b          	addsp 44
+    2760:	71          	loadsp 4
+    2761:	84          	im 4
+    2762:	2a          	lshiftright
+    2763:	05          	add
+    2764:	94          	im 20
+    2765:	1a          	addsp 40
+    2766:	0c          	store
+    2767:	55          	storesp 20
+
+00002768 <.LM167>:
+
+	fs->flag = 0;
+    2768:	80          	im 0
+    2769:	0b          	nop
+    276a:	81          	im 1
+    276b:	19          	addsp 36
+    276c:	34          	storeb
+
+0000276d <.LM168>:
+	FatFs = fs;
+    276d:	77          	loadsp 28
+    276e:	83          	im 3
+    276f:	e0          	im -32
+    2770:	90          	im 16
+    2771:	0c          	store
+
+00002772 <.LM169>:
+
+	return FR_OK;
+    2772:	80          	im 0
+    2773:	56          	storesp 24
+
+00002774 <.L119>:
+}
+    2774:	75          	loadsp 20
+    2775:	83          	im 3
+    2776:	e0          	im -32
+    2777:	80          	im 0
+    2778:	0c          	store
+    2779:	96          	im 22
+    277a:	3d          	pushspadd
+    277b:	0d          	popsp
+    277c:	04          	poppc
+
+0000277d <.L138>:
+    277d:	90          	im 16
+    277e:	54          	storesp 16
+    277f:	83          	im 3
+    2780:	be          	im 62
+    2781:	53          	storesp 12
+    2782:	74          	loadsp 16
+    2783:	52          	storesp 8
+    2784:	76          	loadsp 24
+    2785:	51          	storesp 4
+    2786:	e2          	im -30
+    2787:	f7          	im -9
+    2788:	3f          	callpcrel
+    2789:	83          	im 3
+    278a:	e0          	im -32
+    278b:	80          	im 0
+    278c:	08          	load
+    278d:	80          	im 0
+    278e:	ca          	im -54
+    278f:	38          	neqbranch
+
+00002790 <.LM172>:
+    2790:	8e          	im 14
+    2791:	3d          	pushspadd
+    2792:	33          	loadb
+    2793:	55          	storesp 20
+    2794:	74          	loadsp 16
+    2795:	80          	im 0
+    2796:	2e          	eq
+    2797:	80          	im 0
+    2798:	ca          	im -54
+    2799:	38          	neqbranch
+
+0000279a <.LM173>:
+    279a:	02          	pushsp
+    279b:	bb          	im 59
+    279c:	05          	add
+    279d:	33          	loadb
+    279e:	02          	pushsp
+    279f:	84          	im 4
+    27a0:	05          	add
+    27a1:	ba          	im 58
+    27a2:	05          	add
+    27a3:	33          	loadb
+    27a4:	71          	loadsp 4
+    27a5:	98          	im 24
+    27a6:	2b          	ashiftleft
+    27a7:	71          	loadsp 4
+    27a8:	90          	im 16
+    27a9:	2b          	ashiftleft
+    27aa:	07          	or
+    27ab:	02          	pushsp
+    27ac:	8c          	im 12
+    27ad:	05          	add
+    27ae:	b9          	im 57
+    27af:	05          	add
+    27b0:	33          	loadb
+    27b1:	70          	loadsp 0
+    27b2:	88          	im 8
+    27b3:	2b          	ashiftleft
+    27b4:	72          	loadsp 8
+    27b5:	07          	or
+    27b6:	94          	im 20
+    27b7:	3d          	pushspadd
+    27b8:	33          	loadb
+    27b9:	71          	loadsp 4
+    27ba:	07          	or
+
+000027bb <.LM174>:
+    27bb:	70          	loadsp 0
+    27bc:	58          	storesp 32
+    27bd:	7c          	loadsp 48
+    27be:	57          	storesp 28
+    27bf:	54          	storesp 16
+    27c0:	52          	storesp 8
+    27c1:	5d          	storesp 52
+    27c2:	57          	storesp 28
+    27c3:	5a          	storesp 40
+    27c4:	56          	storesp 24
+    27c5:	fb          	im -5
+    27c6:	b8          	im 56
+    27c7:	3f          	callpcrel
+    27c8:	83          	im 3
+    27c9:	e0          	im -32
+    27ca:	80          	im 0
+    27cb:	08          	load
+    27cc:	81          	im 1
+    27cd:	ff          	im -1
+    27ce:	06          	and
+    27cf:	56          	storesp 24
+
+000027d0 <.LM175>:
+    27d0:	75          	loadsp 20
+    27d1:	83          	im 3
+    27d2:	2e          	eq
+    27d3:	09          	not
+    27d4:	81          	im 1
+    27d5:	06          	and
+    27d6:	fc          	im -4
+    27d7:	fa          	im -6
+    27d8:	38          	neqbranch
+
+000027d9 <.L135>:
+    27d9:	81          	im 1
+
+000027da <.LM176>:
+    27da:	0b          	nop
+    27db:	83          	im 3
+    27dc:	e0          	im -32
+    27dd:	80          	im 0
+    27de:	0c          	store
+    27df:	96          	im 22
+    27e0:	3d          	pushspadd
+    27e1:	0d          	popsp
+    27e2:	04          	poppc
+
+000027e3 <.L136>:
+    27e3:	87          	im 7
+
+000027e4 <.LM178>:
+    27e4:	0b          	nop
+    27e5:	83          	im 3
+    27e6:	e0          	im -32
+    27e7:	80          	im 0
+    27e8:	0c          	store
+    27e9:	96          	im 22
+    27ea:	3d          	pushspadd
+    27eb:	0d          	popsp
+    27ec:	04          	poppc
+
+000027ed <.L139>:
+    27ed:	02          	pushsp
+    27ee:	80          	im 0
+    27ef:	d2          	im -46
+    27f0:	05          	add
+    27f1:	33          	loadb
+    27f2:	02          	pushsp
+    27f3:	84          	im 4
+    27f4:	05          	add
+    27f5:	80          	im 0
+    27f6:	d1          	im -47
+    27f7:	05          	add
+    27f8:	33          	loadb
+    27f9:	71          	loadsp 4
+    27fa:	98          	im 24
+    27fb:	2b          	ashiftleft
+    27fc:	71          	loadsp 4
+    27fd:	90          	im 16
+    27fe:	2b          	ashiftleft
+    27ff:	07          	or
+    2800:	98          	im 24
+    2801:	3d          	pushspadd
+    2802:	33          	loadb
+    2803:	70          	loadsp 0
+    2804:	88          	im 8
+    2805:	2b          	ashiftleft
+    2806:	72          	loadsp 8
+    2807:	07          	or
+    2808:	02          	pushsp
+    2809:	94          	im 20
+    280a:	05          	add
+    280b:	80          	im 0
+    280c:	cf          	im -49
+    280d:	05          	add
+    280e:	33          	loadb
+    280f:	71          	loadsp 4
+    2810:	07          	or
+    2811:	90          	im 16
+    2812:	1e          	addsp 56
+    2813:	0c          	store
+    2814:	52          	storesp 8
+
+00002815 <.LM180>:
+    2815:	84          	im 4
+    2816:	1c          	addsp 48
+    2817:	22          	loadh
+    2818:	7b          	loadsp 44
+    2819:	1f          	addsp 60
+    281a:	71          	loadsp 4
+    281b:	84          	im 4
+    281c:	2a          	lshiftright
+    281d:	05          	add
+    281e:	94          	im 20
+    281f:	1e          	addsp 56
+    2820:	0c          	store
+    2821:	52          	storesp 8
+    2822:	5e          	storesp 56
+    2823:	57          	storesp 28
+    2824:	5a          	storesp 40
+    2825:	56          	storesp 24
+
+00002826 <.LM181>:
+    2826:	80          	im 0
+    2827:	0b          	nop
+    2828:	81          	im 1
+    2829:	19          	addsp 36
+    282a:	34          	storeb
+
+0000282b <.LM182>:
+    282b:	77          	loadsp 28
+    282c:	83          	im 3
+    282d:	e0          	im -32
+    282e:	90          	im 16
+    282f:	0c          	store
+
+00002830 <.LM183>:
+    2830:	80          	im 0
+    2831:	56          	storesp 24
+    2832:	fe          	im -2
+    2833:	c0          	im -64
+    2834:	39          	poppcrel
+
+00002835 <pf_open>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+    2835:	e9          	im -23
+    2836:	3d          	pushspadd
+    2837:	0d          	popsp
+
+00002838 <.LM185>:
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+    2838:	83          	im 3
+    2839:	e0          	im -32
+    283a:	90          	im 16
+    283b:	08          	load
+    283c:	56          	storesp 24
+
+0000283d <.LM186>:
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+    283d:	86          	im 6
+    283e:	54          	storesp 16
+
+0000283f <.LM187>:
+    283f:	75          	loadsp 20
+    2840:	80          	im 0
+    2841:	2e          	eq
+    2842:	be          	im 62
+    2843:	38          	neqbranch
+
+00002844 <.LM188>:
+
+	fs->flag = 0;
+    2844:	80          	im 0
+    2845:	0b          	nop
+    2846:	81          	im 1
+    2847:	17          	addsp 28
+    2848:	34          	storeb
+
+00002849 <.LM189>:
+	dj.fn = sp;
+    2849:	99          	im 25
+    284a:	3d          	pushspadd
+    284b:	e0          	im -32
+    284c:	11          	addsp 4
+    284d:	46          	storesp 88
+
+0000284e <.LM190>:
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+    284e:	6a          	loadsp 104
+    284f:	54          	storesp 16
+    2850:	c0          	im -64
+    2851:	11          	addsp 4
+    2852:	53          	storesp 12
+    2853:	ec          	im -20
+    2854:	05          	add
+    2855:	51          	storesp 4
+    2856:	f5          	im -11
+    2857:	c1          	im -63
+    2858:	3f          	callpcrel
+
+00002859 <.LM191>:
+	if (res != FR_OK) return res;		/* Follow failed */
+    2859:	83          	im 3
+    285a:	e0          	im -32
+    285b:	80          	im 0
+    285c:	08          	load
+    285d:	54          	storesp 16
+    285e:	83          	im 3
+    285f:	e0          	im -32
+    2860:	80          	im 0
+    2861:	08          	load
+    2862:	9e          	im 30
+    2863:	38          	neqbranch
+
+00002864 <.LM192>:
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+    2864:	89          	im 9
+    2865:	3d          	pushspadd
+    2866:	33          	loadb
+    2867:	54          	storesp 16
+    2868:	73          	loadsp 12
+    2869:	80          	im 0
+    286a:	2e          	eq
+    286b:	93          	im 19
+    286c:	38          	neqbranch
+    286d:	02          	pushsp
+    286e:	ab          	im 43
+    286f:	05          	add
+    2870:	33          	loadb
+    2871:	70          	loadsp 0
+    2872:	84          	im 4
+    2873:	2a          	lshiftright
+    2874:	70          	loadsp 0
+    2875:	81          	im 1
+    2876:	06          	and
+    2877:	51          	storesp 4
+    2878:	55          	storesp 20
+    2879:	55          	storesp 20
+    287a:	73          	loadsp 12
+    287b:	80          	im 0
+    287c:	2e          	eq
+    287d:	8c          	im 12
+    287e:	38          	neqbranch
+
+0000287f <.L144>:
+		return FR_NO_FILE;
+    287f:	83          	im 3
+    2880:	54          	storesp 16
+
+00002881 <.L140>:
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+    2881:	73          	loadsp 12
+    2882:	83          	im 3
+    2883:	e0          	im -32
+    2884:	80          	im 0
+    2885:	0c          	store
+    2886:	99          	im 25
+    2887:	3d          	pushspadd
+    2888:	0d          	popsp
+    2889:	04          	poppc
+
+0000288a <.L143>:
+    288a:	02          	pushsp
+    288b:	b5          	im 53
+    288c:	05          	add
+    288d:	33          	loadb
+    288e:	8f          	im 15
+    288f:	3d          	pushspadd
+    2890:	33          	loadb
+    2891:	71          	loadsp 4
+    2892:	98          	im 24
+    2893:	2b          	ashiftleft
+    2894:	71          	loadsp 4
+    2895:	90          	im 16
+    2896:	2b          	ashiftleft
+    2897:	07          	or
+    2898:	02          	pushsp
+    2899:	8c          	im 12
+    289a:	05          	add
+    289b:	bb          	im 59
+    289c:	05          	add
+    289d:	33          	loadb
+    289e:	02          	pushsp
+    289f:	90          	im 16
+    28a0:	05          	add
+    28a1:	ba          	im 58
+    28a2:	05          	add
+    28a3:	33          	loadb
+    28a4:	71          	loadsp 4
+    28a5:	88          	im 8
+    28a6:	2b          	ashiftleft
+    28a7:	07          	or
+    28a8:	72          	loadsp 8
+    28a9:	07          	or
+    28aa:	a0          	im 32
+    28ab:	1b          	addsp 44
+    28ac:	0c          	store
+
+000028ad <.LM196>:
+    28ad:	02          	pushsp
+    28ae:	90          	im 16
+    28af:	05          	add
+    28b0:	bf          	im 63
+    28b1:	05          	add
+    28b2:	33          	loadb
+    28b3:	02          	pushsp
+    28b4:	94          	im 20
+    28b5:	05          	add
+    28b6:	be          	im 62
+    28b7:	05          	add
+    28b8:	33          	loadb
+    28b9:	71          	loadsp 4
+    28ba:	98          	im 24
+    28bb:	2b          	ashiftleft
+    28bc:	71          	loadsp 4
+    28bd:	90          	im 16
+    28be:	2b          	ashiftleft
+    28bf:	07          	or
+    28c0:	02          	pushsp
+    28c1:	9c          	im 28
+    28c2:	05          	add
+    28c3:	bd          	im 61
+    28c4:	05          	add
+    28c5:	33          	loadb
+    28c6:	70          	loadsp 0
+    28c7:	88          	im 8
+    28c8:	2b          	ashiftleft
+    28c9:	72          	loadsp 8
+    28ca:	07          	or
+    28cb:	99          	im 25
+    28cc:	3d          	pushspadd
+    28cd:	33          	loadb
+    28ce:	71          	loadsp 4
+    28cf:	07          	or
+    28d0:	7f          	loadsp 60
+    28d1:	9c          	im 28
+    28d2:	05          	add
+    28d3:	0c          	store
+    28d4:	52          	storesp 8
+
+000028d5 <.LM197>:
+    28d5:	83          	im 3
+    28d6:	e0          	im -32
+    28d7:	80          	im 0
+    28d8:	08          	load
+    28d9:	98          	im 24
+    28da:	1f          	addsp 60
+    28db:	0c          	store
+    28dc:	56          	storesp 24
+    28dd:	5a          	storesp 40
+    28de:	52          	storesp 8
+    28df:	52          	storesp 8
+    28e0:	53          	storesp 12
+    28e1:	57          	storesp 28
+    28e2:	59          	storesp 36
+    28e3:	57          	storesp 28
+
+000028e4 <.LM198>:
+    28e4:	81          	im 1
+    28e5:	0b          	nop
+    28e6:	81          	im 1
+    28e7:	17          	addsp 28
+    28e8:	34          	storeb
+
+000028e9 <.LM199>:
+    28e9:	83          	im 3
+    28ea:	e0          	im -32
+    28eb:	80          	im 0
+    28ec:	08          	load
+
+000028ed <.LM200>:
+    28ed:	83          	im 3
+    28ee:	e0          	im -32
+    28ef:	80          	im 0
+    28f0:	0c          	store
+    28f1:	99          	im 25
+    28f2:	3d          	pushspadd
+    28f3:	0d          	popsp
+    28f4:	04          	poppc
+
+000028f5 <pf_read>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+    28f5:	f4          	im -12
+    28f6:	3d          	pushspadd
+    28f7:	0d          	popsp
+    28f8:	7e          	loadsp 56
+    28f9:	61          	loadsp 68
+    28fa:	02          	pushsp
+    28fb:	88          	im 8
+    28fc:	05          	add
+    28fd:	be          	im 62
+    28fe:	05          	add
+    28ff:	22          	loadh
+
+00002900 <.LM202>:
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+    2900:	72          	loadsp 8
+
+00002901 <.LM203>:
+	FATFS *fs = FatFs;
+    2901:	83          	im 3
+    2902:	e0          	im -32
+    2903:	90          	im 16
+    2904:	08          	load
+    2905:	5c          	storesp 48
+    2906:	5d          	storesp 52
+    2907:	5b          	storesp 44
+    2908:	5c          	storesp 48
+    2909:	5c          	storesp 48
+
+0000290a <.LM204>:
+
+
+	*br = 0;
+    290a:	80          	im 0
+    290b:	7b          	loadsp 44
+    290c:	23          	storeh
+
+0000290d <.LM205>:
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+    290d:	86          	im 6
+    290e:	56          	storesp 24
+    290f:	77          	loadsp 28
+    2910:	80          	im 0
+    2911:	2e          	eq
+    2912:	81          	im 1
+    2913:	ca          	im -54
+    2914:	38          	neqbranch
+
+00002915 <.LM206>:
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+    2915:	81          	im 1
+    2916:	18          	addsp 32
+    2917:	33          	loadb
+    2918:	81          	im 1
+    2919:	06          	and
+    291a:	55          	storesp 20
+
+0000291b <.LM207>:
+		return FR_NOT_OPENED;
+    291b:	85          	im 5
+    291c:	56          	storesp 24
+
+0000291d <.LM208>:
+    291d:	74          	loadsp 16
+    291e:	80          	im 0
+    291f:	2e          	eq
+    2920:	81          	im 1
+    2921:	bc          	im 60
+    2922:	38          	neqbranch
+
+00002923 <.LM209>:
+
+	remain = fs->fsize - fs->fptr;
+    2923:	98          	im 24
+    2924:	18          	addsp 32
+    2925:	08          	load
+    2926:	9c          	im 28
+    2927:	19          	addsp 36
+    2928:	08          	load
+    2929:	71          	loadsp 4
+    292a:	31          	sub
+    292b:	56          	storesp 24
+    292c:	57          	storesp 28
+
+0000292d <.LM210>:
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+    292d:	78          	loadsp 32
+    292e:	75          	loadsp 20
+    292f:	26          	ulessthan
+    2930:	81          	im 1
+    2931:	b5          	im 53
+    2932:	38          	neqbranch
+
+00002933 <.L149>:
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+    2933:	78          	loadsp 32
+    2934:	80          	im 0
+    2935:	2e          	eq
+    2936:	81          	im 1
+    2937:	a4          	im 36
+    2938:	38          	neqbranch
+
+00002939 <.L169>:
+    2939:	76          	loadsp 24
+    293a:	83          	im 3
+    293b:	ff          	im -1
+    293c:	06          	and
+    293d:	55          	storesp 20
+    293e:	74          	loadsp 16
+    293f:	80          	im 0
+    2940:	c1          	im -63
+    2941:	38          	neqbranch
+
+00002942 <.LM213>:
+    2942:	82          	im 2
+    2943:	18          	addsp 32
+    2944:	33          	loadb
+    2945:	ff          	im -1
+    2946:	05          	add
+    2947:	77          	loadsp 28
+    2948:	89          	im 9
+    2949:	2a          	lshiftright
+    294a:	06          	and
+    294b:	70          	loadsp 0
+    294c:	81          	im 1
+    294d:	ff          	im -1
+    294e:	06          	and
+    294f:	51          	storesp 4
+    2950:	55          	storesp 20
+
+00002951 <.LM214>:
+    2951:	74          	loadsp 16
+    2952:	93          	im 19
+    2953:	38          	neqbranch
+
+00002954 <.LM215>:
+    2954:	76          	loadsp 24
+    2955:	81          	im 1
+    2956:	99          	im 25
+    2957:	38          	neqbranch
+    2958:	a0          	im 32
+    2959:	18          	addsp 32
+    295a:	08          	load
+    295b:	56          	storesp 24
+
+0000295c <.L155>:
+    295c:	81          	im 1
+    295d:	76          	loadsp 24
+    295e:	27          	ulessthanorequal
+    295f:	81          	im 1
+    2960:	a3          	im 35
+    2961:	38          	neqbranch
+
+00002962 <.LM217>:
+    2962:	75          	loadsp 20
+    2963:	a4          	im 36
+    2964:	19          	addsp 36
+    2965:	0c          	store
+
+00002966 <.L153>:
+    2966:	a4          	im 36
+    2967:	18          	addsp 32
+    2968:	08          	load
+    2969:	51          	storesp 4
+    296a:	f0          	im -16
+    296b:	fd          	im -3
+    296c:	3f          	callpcrel
+
+0000296d <.LM219>:
+    296d:	83          	im 3
+    296e:	e0          	im -32
+    296f:	80          	im 0
+    2970:	08          	load
+    2971:	80          	im 0
+    2972:	2e          	eq
+    2973:	81          	im 1
+    2974:	8f          	im 15
+    2975:	38          	neqbranch
+
+00002976 <.LM220>:
+    2976:	83          	im 3
+    2977:	e0          	im -32
+    2978:	80          	im 0
+    2979:	08          	load
+    297a:	15          	addsp 20
+    297b:	a8          	im 40
+    297c:	19          	addsp 36
+    297d:	0c          	store
+    297e:	98          	im 24
+    297f:	18          	addsp 32
+    2980:	08          	load
+    2981:	57          	storesp 28
+
+00002982 <.L152>:
+    2982:	76          	loadsp 24
+    2983:	83          	im 3
+    2984:	ff          	im -1
+    2985:	06          	and
+    2986:	84          	im 4
+    2987:	80          	im 0
+    2988:	71          	loadsp 4
+    2989:	31          	sub
+    298a:	70          	loadsp 0
+    298b:	83          	im 3
+    298c:	ff          	im -1
+    298d:	ff          	im -1
+    298e:	06          	and
+    298f:	58          	storesp 32
+    2990:	51          	storesp 4
+    2991:	55          	storesp 20
+
+00002992 <.LM222>:
+    2992:	78          	loadsp 32
+    2993:	76          	loadsp 24
+    2994:	27          	ulessthanorequal
+    2995:	83          	im 3
+    2996:	38          	neqbranch
+    2997:	78          	loadsp 32
+    2998:	56          	storesp 24
+
+00002999 <.L159>:
+    2999:	75          	loadsp 20
+    299a:	54          	storesp 16
+    299b:	98          	im 24
+    299c:	18          	addsp 32
+    299d:	08          	load
+    299e:	83          	im 3
+    299f:	ff          	im -1
+    29a0:	06          	and
+    29a1:	53          	storesp 12
+    29a2:	a8          	im 40
+    29a3:	18          	addsp 32
+    29a4:	08          	load
+    29a5:	52          	storesp 8
+    29a6:	79          	loadsp 36
+    29a7:	55          	storesp 20
+    29a8:	7b          	loadsp 44
+    29a9:	80          	im 0
+    29aa:	2e          	eq
+    29ab:	80          	im 0
+    29ac:	d2          	im -46
+    29ad:	38          	neqbranch
+
+000029ae <.L161>:
+    29ae:	74          	loadsp 16
+    29af:	51          	storesp 4
+    29b0:	de          	im -34
+    29b1:	cd          	im -51
+    29b2:	3f          	callpcrel
+
+000029b3 <.LM224>:
+    29b3:	83          	im 3
+    29b4:	e0          	im -32
+    29b5:	80          	im 0
+    29b6:	08          	load
+    29b7:	80          	im 0
+    29b8:	cb          	im -53
+    29b9:	38          	neqbranch
+
+000029ba <.LM225>:
+    29ba:	98          	im 24
+    29bb:	18          	addsp 32
+    29bc:	08          	load
+    29bd:	16          	addsp 24
+    29be:	70          	loadsp 0
+    29bf:	58          	storesp 32
+    29c0:	98          	im 24
+    29c1:	19          	addsp 36
+    29c2:	0c          	store
+    29c3:	75          	loadsp 20
+    29c4:	1a          	addsp 40
+
+000029c5 <.LM226>:
+    29c5:	79          	loadsp 36
+    29c6:	77          	loadsp 28
+    29c7:	31          	sub
+    29c8:	70          	loadsp 0
+    29c9:	83          	im 3
+    29ca:	ff          	im -1
+    29cb:	ff          	im -1
+    29cc:	06          	and
+    29cd:	7d          	loadsp 52
+    29ce:	22          	loadh
+    29cf:	79          	loadsp 36
+    29d0:	05          	add
+    29d1:	52          	storesp 8
+    29d2:	5b          	storesp 44
+    29d3:	56          	storesp 24
+    29d4:	5a          	storesp 40
+    29d5:	74          	loadsp 16
+    29d6:	7b          	loadsp 44
+    29d7:	23          	storeh
+    29d8:	78          	loadsp 32
+    29d9:	fe          	im -2
+    29da:	de          	im -34
+    29db:	38          	neqbranch
+
+000029dc <.L165>:
+	}
+
+	return FR_OK;
+    29dc:	80          	im 0
+    29dd:	56          	storesp 24
+
+000029de <.L146>:
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+    29de:	75          	loadsp 20
+    29df:	83          	im 3
+    29e0:	e0          	im -32
+    29e1:	80          	im 0
+    29e2:	0c          	store
+    29e3:	8e          	im 14
+    29e4:	3d          	pushspadd
+    29e5:	0d          	popsp
+    29e6:	04          	poppc
+
+000029e7 <.L167>:
+    29e7:	74          	loadsp 16
+    29e8:	83          	im 3
+    29e9:	ff          	im -1
+    29ea:	ff          	im -1
+    29eb:	06          	and
+    29ec:	59          	storesp 36
+    29ed:	fe          	im -2
+    29ee:	c4          	im -60
+    29ef:	39          	poppcrel
+
+000029f0 <.L154>:
+    29f0:	a4          	im 36
+    29f1:	18          	addsp 32
+    29f2:	08          	load
+    29f3:	51          	storesp 4
+    29f4:	ed          	im -19
+    29f5:	a4          	im 36
+    29f6:	3f          	callpcrel
+    29f7:	83          	im 3
+    29f8:	e0          	im -32
+    29f9:	80          	im 0
+    29fa:	08          	load
+    29fb:	56          	storesp 24
+    29fc:	fe          	im -2
+    29fd:	de          	im -34
+    29fe:	39          	poppcrel
+
+000029ff <.L168>:
+    29ff:	7b          	loadsp 44
+    2a00:	55          	storesp 20
+    2a01:	ff          	im -1
+    2a02:	ab          	im 43
+    2a03:	39          	poppcrel
+
+00002a04 <.L157>:
+    2a04:	80          	im 0
+    2a05:	0b          	nop
+    2a06:	81          	im 1
+    2a07:	19          	addsp 36
+    2a08:	34          	storeb
+
+00002a09 <.LM233>:
+    2a09:	81          	im 1
+
+00002a0a <.LM234>:
+    2a0a:	0b          	nop
+    2a0b:	83          	im 3
+    2a0c:	e0          	im -32
+    2a0d:	80          	im 0
+    2a0e:	0c          	store
+    2a0f:	8e          	im 14
+    2a10:	3d          	pushspadd
+    2a11:	0d          	popsp
+    2a12:	04          	poppc
+
+00002a13 <pf_lseek>:
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+    2a13:	fa          	im -6
+    2a14:	3d          	pushspadd
+    2a15:	0d          	popsp
+    2a16:	78          	loadsp 32
+
+00002a17 <.LM236>:
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+    2a17:	83          	im 3
+    2a18:	e0          	im -32
+    2a19:	90          	im 16
+    2a1a:	08          	load
+    2a1b:	55          	storesp 20
+    2a1c:	55          	storesp 20
+
+00002a1d <.LM237>:
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+    2a1d:	86          	im 6
+    2a1e:	56          	storesp 24
+    2a1f:	73          	loadsp 12
+    2a20:	80          	im 0
+    2a21:	2e          	eq
+    2a22:	81          	im 1
+    2a23:	cd          	im -51
+    2a24:	38          	neqbranch
+
+00002a25 <.LM238>:
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+    2a25:	81          	im 1
+    2a26:	14          	addsp 16
+    2a27:	33          	loadb
+    2a28:	81          	im 1
+    2a29:	06          	and
+    2a2a:	53          	storesp 12
+
+00002a2b <.LM239>:
+			return FR_NOT_OPENED;
+    2a2b:	85          	im 5
+    2a2c:	56          	storesp 24
+
+00002a2d <.LM240>:
+    2a2d:	72          	loadsp 8
+    2a2e:	80          	im 0
+    2a2f:	2e          	eq
+    2a30:	81          	im 1
+    2a31:	bf          	im 63
+    2a32:	38          	neqbranch
+
+00002a33 <.LM241>:
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+    2a33:	9c          	im 28
+    2a34:	14          	addsp 16
+    2a35:	08          	load
+    2a36:	53          	storesp 12
+    2a37:	74          	loadsp 16
+    2a38:	73          	loadsp 12
+    2a39:	26          	ulessthan
+    2a3a:	81          	im 1
+    2a3b:	be          	im 62
+    2a3c:	38          	neqbranch
+
+00002a3d <.L173>:
+	ifptr = fs->fptr;
+    2a3d:	98          	im 24
+    2a3e:	14          	addsp 16
+    2a3f:	08          	load
+    2a40:	57          	storesp 28
+
+00002a41 <.LM243>:
+	fs->fptr = 0;
+    2a41:	80          	im 0
+    2a42:	0b          	nop
+    2a43:	98          	im 24
+    2a44:	15          	addsp 20
+    2a45:	0c          	store
+
+00002a46 <.LM244>:
+	if (ofs > 0) {
+    2a46:	74          	loadsp 16
+    2a47:	80          	im 0
+    2a48:	2e          	eq
+    2a49:	81          	im 1
+    2a4a:	a4          	im 36
+    2a4b:	38          	neqbranch
+
+00002a4c <.LM245>:
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+    2a4c:	82          	im 2
+    2a4d:	14          	addsp 16
+    2a4e:	33          	loadb
+    2a4f:	70          	loadsp 0
+    2a50:	89          	im 9
+    2a51:	2b          	ashiftleft
+    2a52:	57          	storesp 28
+    2a53:	53          	storesp 12
+
+00002a54 <.LM246>:
+		if (ifptr > 0 &&
+    2a54:	76          	loadsp 24
+    2a55:	80          	im 0
+    2a56:	2e          	eq
+    2a57:	81          	im 1
+    2a58:	a6          	im 38
+    2a59:	38          	neqbranch
+    2a5a:	75          	loadsp 20
+    2a5b:	52          	storesp 8
+    2a5c:	ff          	im -1
+    2a5d:	15          	addsp 20
+    2a5e:	51          	storesp 4
+    2a5f:	97          	im 23
+    2a60:	a1          	im 33
+    2a61:	3f          	callpcrel
+    2a62:	83          	im 3
+    2a63:	e0          	im -32
+    2a64:	80          	im 0
+    2a65:	08          	load
+    2a66:	ff          	im -1
+    2a67:	18          	addsp 32
+    2a68:	77          	loadsp 28
+    2a69:	54          	storesp 16
+    2a6a:	70          	loadsp 0
+    2a6b:	53          	storesp 12
+    2a6c:	58          	storesp 32
+    2a6d:	53          	storesp 12
+    2a6e:	97          	im 23
+    2a6f:	92          	im 18
+    2a70:	3f          	callpcrel
+    2a71:	83          	im 3
+    2a72:	e0          	im -32
+    2a73:	80          	im 0
+    2a74:	08          	load
+    2a75:	73          	loadsp 12
+    2a76:	26          	ulessthan
+    2a77:	81          	im 1
+    2a78:	86          	im 6
+    2a79:	38          	neqbranch
+
+00002a7a <.LM247>:
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+    2a7a:	75          	loadsp 20
+    2a7b:	30          	neg
+    2a7c:	70          	loadsp 0
+    2a7d:	78          	loadsp 32
+    2a7e:	06          	and
+    2a7f:	70          	loadsp 0
+    2a80:	98          	im 24
+    2a81:	17          	addsp 28
+    2a82:	0c          	store
+
+00002a83 <.LM248>:
+			ofs -= fs->fptr;
+    2a83:	76          	loadsp 24
+    2a84:	71          	loadsp 4
+    2a85:	31          	sub
+
+00002a86 <.LM249>:
+			clst = fs->curr_clust;
+    2a86:	a4          	im 36
+    2a87:	17          	addsp 28
+    2a88:	08          	load
+    2a89:	52          	storesp 8
+    2a8a:	57          	storesp 28
+    2a8b:	51          	storesp 4
+    2a8c:	53          	storesp 12
+
+00002a8d <.L176>:
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+    2a8d:	75          	loadsp 20
+    2a8e:	75          	loadsp 20
+    2a8f:	27          	ulessthanorequal
+    2a90:	b7          	im 55
+    2a91:	38          	neqbranch
+
+00002a92 <.L188>:
+    2a92:	72          	loadsp 8
+    2a93:	51          	storesp 4
+    2a94:	ec          	im -20
+    2a95:	84          	im 4
+    2a96:	3f          	callpcrel
+    2a97:	83          	im 3
+    2a98:	e0          	im -32
+    2a99:	80          	im 0
+    2a9a:	08          	load
+    2a9b:	53          	storesp 12
+
+00002a9c <.LM252>:
+    2a9c:	81          	im 1
+    2a9d:	0b          	nop
+    2a9e:	83          	im 3
+    2a9f:	e0          	im -32
+    2aa0:	80          	im 0
+    2aa1:	08          	load
+    2aa2:	27          	ulessthanorequal
+    2aa3:	80          	im 0
+    2aa4:	e5          	im -27
+    2aa5:	38          	neqbranch
+    2aa6:	83          	im 3
+    2aa7:	e0          	im -32
+    2aa8:	80          	im 0
+    2aa9:	08          	load
+    2aaa:	88          	im 8
+    2aab:	15          	addsp 20
+    2aac:	08          	load
+    2aad:	27          	ulessthanorequal
+    2aae:	80          	im 0
+    2aaf:	da          	im -38
+    2ab0:	38          	neqbranch
+
+00002ab1 <.LM253>:
+    2ab1:	83          	im 3
+    2ab2:	e0          	im -32
+    2ab3:	80          	im 0
+    2ab4:	08          	load
+    2ab5:	a4          	im 36
+    2ab6:	15          	addsp 20
+    2ab7:	0c          	store
+
+00002ab8 <.LM254>:
+    2ab8:	98          	im 24
+    2ab9:	14          	addsp 16
+    2aba:	08          	load
+    2abb:	16          	addsp 24
+    2abc:	98          	im 24
+    2abd:	15          	addsp 20
+    2abe:	0c          	store
+
+00002abf <.LM255>:
+    2abf:	74          	loadsp 16
+    2ac0:	76          	loadsp 24
+    2ac1:	31          	sub
+    2ac2:	55          	storesp 20
+    2ac3:	74          	loadsp 16
+    2ac4:	76          	loadsp 24
+    2ac5:	26          	ulessthan
+    2ac6:	cb          	im -53
+    2ac7:	38          	neqbranch
+
+00002ac8 <.L185>:
+		}
+		fs->fptr += ofs;
+    2ac8:	98          	im 24
+    2ac9:	14          	addsp 16
+    2aca:	08          	load
+    2acb:	15          	addsp 20
+    2acc:	70          	loadsp 0
+    2acd:	98          	im 24
+    2ace:	16          	addsp 24
+    2acf:	0c          	store
+
+00002ad0 <.LM257>:
+		sect = clust2sect(clst);		/* Current sector */
+    2ad0:	73          	loadsp 12
+    2ad1:	52          	storesp 8
+    2ad2:	56          	storesp 24
+    2ad3:	ee          	im -18
+    2ad4:	94          	im 20
+    2ad5:	3f          	callpcrel
+
+00002ad6 <.LM258>:
+		if (!sect) goto fe_abort;
+    2ad6:	83          	im 3
+    2ad7:	e0          	im -32
+    2ad8:	80          	im 0
+    2ad9:	08          	load
+    2ada:	80          	im 0
+    2adb:	2e          	eq
+    2adc:	ad          	im 45
+    2add:	38          	neqbranch
+
+00002ade <.LM259>:
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+    2ade:	82          	im 2
+    2adf:	14          	addsp 16
+    2ae0:	33          	loadb
+    2ae1:	ff          	im -1
+    2ae2:	05          	add
+    2ae3:	76          	loadsp 24
+    2ae4:	89          	im 9
+    2ae5:	2a          	lshiftright
+    2ae6:	06          	and
+    2ae7:	83          	im 3
+    2ae8:	e0          	im -32
+    2ae9:	80          	im 0
+    2aea:	08          	load
+    2aeb:	05          	add
+    2aec:	a8          	im 40
+    2aed:	15          	addsp 20
+    2aee:	0c          	store
+
+00002aef <.L174>:
+	}
+
+	return FR_OK;
+    2aef:	80          	im 0
+    2af0:	56          	storesp 24
+
+00002af1 <.L170>:
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+    2af1:	75          	loadsp 20
+    2af2:	83          	im 3
+    2af3:	e0          	im -32
+    2af4:	80          	im 0
+    2af5:	0c          	store
+    2af6:	88          	im 8
+    2af7:	3d          	pushspadd
+    2af8:	0d          	popsp
+    2af9:	04          	poppc
+
+00002afa <.L187>:
+    2afa:	72          	loadsp 8
+    2afb:	55          	storesp 20
+    2afc:	fe          	im -2
+    2afd:	bf          	im 63
+    2afe:	39          	poppcrel
+
+00002aff <.L175>:
+    2aff:	a0          	im 32
+    2b00:	14          	addsp 16
+    2b01:	08          	load
+
+00002b02 <.LM264>:
+    2b02:	70          	loadsp 0
+    2b03:	a4          	im 36
+    2b04:	16          	addsp 24
+    2b05:	0c          	store
+    2b06:	53          	storesp 12
+    2b07:	ff          	im -1
+    2b08:	84          	im 4
+    2b09:	39          	poppcrel
+
+00002b0a <.L181>:
+    2b0a:	80          	im 0
+    2b0b:	0b          	nop
+    2b0c:	81          	im 1
+    2b0d:	15          	addsp 20
+    2b0e:	34          	storeb
+
+00002b0f <.LM266>:
+    2b0f:	81          	im 1
+
+00002b10 <.LM267>:
+    2b10:	0b          	nop
+    2b11:	83          	im 3
+    2b12:	e0          	im -32
+    2b13:	80          	im 0
+    2b14:	0c          	store
+    2b15:	88          	im 8
+    2b16:	3d          	pushspadd
+    2b17:	0d          	popsp
+    2b18:	04          	poppc
+
+00002b19 <pf_opendir>:
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+    2b19:	ee          	im -18
+    2b1a:	3d          	pushspadd
+    2b1b:	0d          	popsp
+    2b1c:	64          	loadsp 80
+    2b1d:	56          	storesp 24
+
+00002b1e <.LM269>:
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+    2b1e:	86          	im 6
+    2b1f:	55          	storesp 20
+
+00002b20 <.LM270>:
+    2b20:	83          	im 3
+    2b21:	e0          	im -32
+    2b22:	90          	im 16
+    2b23:	08          	load
+    2b24:	80          	im 0
+    2b25:	2e          	eq
+    2b26:	80          	im 0
+    2b27:	f1          	im -15
+    2b28:	38          	neqbranch
+
+00002b29 <.LM271>:
+	} else {
+		dj->fn = sp;
+    2b29:	94          	im 20
+    2b2a:	3d          	pushspadd
+    2b2b:	f4          	im -12
+    2b2c:	11          	addsp 4
+    2b2d:	84          	im 4
+    2b2e:	18          	addsp 32
+    2b2f:	0c          	store
+
+00002b30 <.LM272>:
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+    2b30:	66          	loadsp 88
+    2b31:	54          	storesp 16
+    2b32:	d4          	im -44
+    2b33:	05          	add
+    2b34:	52          	storesp 8
+    2b35:	75          	loadsp 20
+    2b36:	51          	storesp 4
+    2b37:	ef          	im -17
+    2b38:	e0          	im -32
+    2b39:	3f          	callpcrel
+    2b3a:	83          	im 3
+    2b3b:	e0          	im -32
+    2b3c:	80          	im 0
+    2b3d:	08          	load
+    2b3e:	55          	storesp 20
+
+00002b3f <.LM273>:
+		if (res == FR_OK) {						/* Follow completed */
+    2b3f:	83          	im 3
+    2b40:	e0          	im -32
+    2b41:	80          	im 0
+    2b42:	08          	load
+    2b43:	80          	im 0
+    2b44:	cf          	im -49
+    2b45:	38          	neqbranch
+
+00002b46 <.LM274>:
+			if (dir[0]) {						/* It is not the root dir */
+    2b46:	89          	im 9
+    2b47:	3d          	pushspadd
+    2b48:	33          	loadb
+    2b49:	54          	storesp 16
+    2b4a:	73          	loadsp 12
+    2b4b:	80          	im 0
+    2b4c:	2e          	eq
+    2b4d:	bc          	im 60
+    2b4e:	38          	neqbranch
+
+00002b4f <.LM275>:
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+    2b4f:	02          	pushsp
+    2b50:	ab          	im 43
+    2b51:	05          	add
+    2b52:	33          	loadb
+    2b53:	70          	loadsp 0
+    2b54:	84          	im 4
+    2b55:	2a          	lshiftright
+    2b56:	70          	loadsp 0
+    2b57:	81          	im 1
+    2b58:	06          	and
+    2b59:	51          	storesp 4
+    2b5a:	55          	storesp 20
+    2b5b:	55          	storesp 20
+
+00002b5c <.LM276>:
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+    2b5c:	84          	im 4
+    2b5d:	55          	storesp 20
+
+00002b5e <.LM277>:
+    2b5e:	73          	loadsp 12
+    2b5f:	80          	im 0
+    2b60:	2e          	eq
+    2b61:	b7          	im 55
+    2b62:	38          	neqbranch
+
+00002b63 <.LM278>:
+    2b63:	02          	pushsp
+    2b64:	b5          	im 53
+    2b65:	05          	add
+    2b66:	33          	loadb
+    2b67:	8f          	im 15
+    2b68:	3d          	pushspadd
+    2b69:	33          	loadb
+    2b6a:	71          	loadsp 4
+    2b6b:	98          	im 24
+    2b6c:	2b          	ashiftleft
+    2b6d:	71          	loadsp 4
+    2b6e:	90          	im 16
+    2b6f:	2b          	ashiftleft
+    2b70:	07          	or
+    2b71:	02          	pushsp
+    2b72:	8c          	im 12
+    2b73:	05          	add
+    2b74:	bb          	im 59
+    2b75:	05          	add
+    2b76:	33          	loadb
+    2b77:	02          	pushsp
+    2b78:	90          	im 16
+    2b79:	05          	add
+    2b7a:	ba          	im 58
+    2b7b:	05          	add
+    2b7c:	33          	loadb
+    2b7d:	71          	loadsp 4
+    2b7e:	88          	im 8
+    2b7f:	2b          	ashiftleft
+    2b80:	07          	or
+    2b81:	72          	loadsp 8
+    2b82:	07          	or
+    2b83:	88          	im 8
+    2b84:	1b          	addsp 44
+    2b85:	0c          	store
+    2b86:	53          	storesp 12
+    2b87:	57          	storesp 28
+    2b88:	59          	storesp 36
+    2b89:	57          	storesp 28
+
+00002b8a <.L198>:
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+    2b8a:	75          	loadsp 20
+    2b8b:	51          	storesp 4
+    2b8c:	ed          	im -19
+    2b8d:	88          	im 8
+    2b8e:	3f          	callpcrel
+    2b8f:	83          	im 3
+    2b90:	e0          	im -32
+    2b91:	80          	im 0
+    2b92:	08          	load
+    2b93:	55          	storesp 20
+
+00002b94 <.L192>:
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+    2b94:	74          	loadsp 16
+    2b95:	83          	im 3
+    2b96:	2e          	eq
+    2b97:	8a          	im 10
+    2b98:	38          	neqbranch
+
+00002b99 <.L191>:
+	}
+
+	return res;
+}
+    2b99:	74          	loadsp 16
+    2b9a:	83          	im 3
+    2b9b:	e0          	im -32
+    2b9c:	80          	im 0
+    2b9d:	0c          	store
+    2b9e:	94          	im 20
+    2b9f:	3d          	pushspadd
+    2ba0:	0d          	popsp
+    2ba1:	04          	poppc
+
+00002ba2 <.L200>:
+    2ba2:	84          	im 4
+
+00002ba3 <.LM283>:
+    2ba3:	0b          	nop
+    2ba4:	83          	im 3
+    2ba5:	e0          	im -32
+    2ba6:	80          	im 0
+    2ba7:	0c          	store
+    2ba8:	94          	im 20
+    2ba9:	3d          	pushspadd
+    2baa:	0d          	popsp
+    2bab:	04          	poppc
+
+00002bac <pf_readdir>:
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+    2bac:	eb          	im -21
+    2bad:	3d          	pushspadd
+    2bae:	0d          	popsp
+    2baf:	67          	loadsp 92
+    2bb0:	69          	loadsp 100
+    2bb1:	5b          	storesp 44
+    2bb2:	59          	storesp 36
+
+00002bb3 <.LM285>:
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+    2bb3:	86          	im 6
+    2bb4:	55          	storesp 20
+
+00002bb5 <.LM286>:
+    2bb5:	83          	im 3
+    2bb6:	e0          	im -32
+    2bb7:	90          	im 16
+    2bb8:	08          	load
+    2bb9:	80          	im 0
+    2bba:	2e          	eq
+    2bbb:	81          	im 1
+    2bbc:	f1          	im -15
+    2bbd:	38          	neqbranch
+
+00002bbe <.LM287>:
+	} else {
+		dj->fn = sp;
+    2bbe:	97          	im 23
+    2bbf:	3d          	pushspadd
+    2bc0:	f4          	im -12
+    2bc1:	05          	add
+    2bc2:	84          	im 4
+    2bc3:	1a          	addsp 40
+    2bc4:	0c          	store
+
+00002bc5 <.LM288>:
+		if (!fno) {
+    2bc5:	79          	loadsp 36
+    2bc6:	80          	im 0
+    2bc7:	2e          	eq
+    2bc8:	83          	im 3
+    2bc9:	84          	im 4
+    2bca:	38          	neqbranch
+
+00002bcb <.LBB24>:
+    2bcb:	8c          	im 12
+    2bcc:	3d          	pushspadd
+    2bcd:	58          	storesp 32
+
+00002bce <.LM290>:
+    2bce:	83          	im 3
+    2bcf:	55          	storesp 20
+
+00002bd0 <.LM291>:
+    2bd0:	90          	im 16
+    2bd1:	19          	addsp 36
+    2bd2:	08          	load
+    2bd3:	81          	im 1
+    2bd4:	fb          	im -5
+    2bd5:	38          	neqbranch
+
+00002bd6 <.L240>:
+    2bd6:	80          	im 0
+    2bd7:	0b          	nop
+    2bd8:	90          	im 16
+    2bd9:	1a          	addsp 40
+    2bda:	0c          	store
+
+00002bdb <.L216>:
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+    2bdb:	74          	loadsp 16
+    2bdc:	83          	im 3
+    2bdd:	2e          	eq
+    2bde:	82          	im 2
+    2bdf:	e6          	im -26
+    2be0:	38          	neqbranch
+
+00002be1 <.LM294>:
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+    2be1:	74          	loadsp 16
+    2be2:	81          	im 1
+    2be3:	ca          	im -54
+    2be4:	38          	neqbranch
+
+00002be5 <.L241>:
+    2be5:	89          	im 9
+    2be6:	1a          	addsp 40
+    2be7:	57          	storesp 28
+
+00002be8 <.LM296>:
+    2be8:	90          	im 16
+    2be9:	19          	addsp 36
+    2bea:	08          	load
+    2beb:	80          	im 0
+    2bec:	2e          	eq
+    2bed:	81          	im 1
+    2bee:	a0          	im 32
+    2bef:	38          	neqbranch
+
+00002bf0 <.LM297>:
+    2bf0:	80          	im 0
+    2bf1:	56          	storesp 24
+
+00002bf2 <.L226>:
+    2bf2:	77          	loadsp 28
+    2bf3:	16          	addsp 24
+    2bf4:	70          	loadsp 0
+    2bf5:	33          	loadb
+    2bf6:	51          	storesp 4
+    2bf7:	55          	storesp 20
+
+00002bf8 <.LM299>:
+    2bf8:	74          	loadsp 16
+    2bf9:	a0          	im 32
+    2bfa:	2e          	eq
+    2bfb:	9b          	im 27
+    2bfc:	38          	neqbranch
+
+00002bfd <.LM300>:
+    2bfd:	74          	loadsp 16
+    2bfe:	85          	im 5
+    2bff:	2e          	eq
+    2c00:	82          	im 2
+    2c01:	a9          	im 41
+    2c02:	38          	neqbranch
+
+00002c03 <.LM301>:
+    2c03:	74          	loadsp 16
+    2c04:	77          	loadsp 28
+    2c05:	70          	loadsp 0
+    2c06:	81          	im 1
+    2c07:	05          	add
+    2c08:	59          	storesp 36
+    2c09:	34          	storeb
+
+00002c0a <.LM302>:
+    2c0a:	81          	im 1
+    2c0b:	16          	addsp 24
+    2c0c:	70          	loadsp 0
+    2c0d:	81          	im 1
+    2c0e:	ff          	im -1
+    2c0f:	06          	and
+    2c10:	57          	storesp 28
+    2c11:	55          	storesp 20
+    2c12:	87          	im 7
+    2c13:	76          	loadsp 24
+    2c14:	27          	ulessthanorequal
+    2c15:	dc          	im -36
+    2c16:	38          	neqbranch
+
+00002c17 <.L222>:
+    2c17:	88          	im 8
+    2c18:	18          	addsp 32
+    2c19:	33          	loadb
+    2c1a:	55          	storesp 20
+    2c1b:	74          	loadsp 16
+    2c1c:	a0          	im 32
+    2c1d:	2e          	eq
+    2c1e:	a9          	im 41
+    2c1f:	38          	neqbranch
+
+00002c20 <.LM304>:
+    2c20:	ae          	im 46
+    2c21:	77          	loadsp 28
+    2c22:	70          	loadsp 0
+    2c23:	81          	im 1
+    2c24:	05          	add
+    2c25:	59          	storesp 36
+    2c26:	34          	storeb
+
+00002c27 <.LM305>:
+    2c27:	88          	im 8
+    2c28:	56          	storesp 24
+
+00002c29 <.L232>:
+    2c29:	77          	loadsp 28
+    2c2a:	16          	addsp 24
+    2c2b:	70          	loadsp 0
+    2c2c:	33          	loadb
+    2c2d:	51          	storesp 4
+    2c2e:	55          	storesp 20
+
+00002c2f <.LM307>:
+    2c2f:	74          	loadsp 16
+    2c30:	a0          	im 32
+    2c31:	2e          	eq
+    2c32:	95          	im 21
+    2c33:	38          	neqbranch
+
+00002c34 <.LM308>:
+    2c34:	74          	loadsp 16
+    2c35:	77          	loadsp 28
+    2c36:	70          	loadsp 0
+    2c37:	81          	im 1
+    2c38:	05          	add
+    2c39:	59          	storesp 36
+    2c3a:	34          	storeb
+
+00002c3b <.LM309>:
+    2c3b:	81          	im 1
+    2c3c:	16          	addsp 24
+    2c3d:	70          	loadsp 0
+    2c3e:	81          	im 1
+    2c3f:	ff          	im -1
+    2c40:	06          	and
+    2c41:	57          	storesp 28
+    2c42:	55          	storesp 20
+    2c43:	8a          	im 10
+    2c44:	76          	loadsp 24
+    2c45:	27          	ulessthanorequal
+    2c46:	e2          	im -30
+    2c47:	38          	neqbranch
+
+00002c48 <.L227>:
+    2c48:	8b          	im 11
+    2c49:	18          	addsp 32
+    2c4a:	33          	loadb
+    2c4b:	88          	im 8
+    2c4c:	1b          	addsp 44
+    2c4d:	34          	storeb
+
+00002c4e <.LM311>:
+    2c4e:	9f          	im 31
+    2c4f:	18          	addsp 32
+    2c50:	33          	loadb
+    2c51:	9e          	im 30
+    2c52:	19          	addsp 36
+    2c53:	33          	loadb
+    2c54:	71          	loadsp 4
+    2c55:	98          	im 24
+    2c56:	2b          	ashiftleft
+    2c57:	71          	loadsp 4
+    2c58:	90          	im 16
+    2c59:	2b          	ashiftleft
+    2c5a:	07          	or
+    2c5b:	9d          	im 29
+    2c5c:	1b          	addsp 44
+    2c5d:	33          	loadb
+    2c5e:	70          	loadsp 0
+    2c5f:	88          	im 8
+    2c60:	2b          	ashiftleft
+    2c61:	72          	loadsp 8
+    2c62:	07          	or
+    2c63:	9c          	im 28
+    2c64:	1d          	addsp 52
+    2c65:	33          	loadb
+    2c66:	71          	loadsp 4
+    2c67:	07          	or
+    2c68:	7f          	loadsp 60
+    2c69:	0c          	store
+    2c6a:	52          	storesp 8
+
+00002c6b <.LM312>:
+    2c6b:	99          	im 25
+    2c6c:	1c          	addsp 48
+    2c6d:	33          	loadb
+    2c6e:	98          	im 24
+    2c6f:	1d          	addsp 52
+    2c70:	33          	loadb
+    2c71:	71          	loadsp 4
+    2c72:	88          	im 8
+    2c73:	2b          	ashiftleft
+    2c74:	07          	or
+    2c75:	53          	storesp 12
+    2c76:	51          	storesp 4
+    2c77:	53          	storesp 12
+    2c78:	57          	storesp 28
+    2c79:	5c          	storesp 48
+    2c7a:	56          	storesp 24
+    2c7b:	74          	loadsp 16
+    2c7c:	84          	im 4
+    2c7d:	1b          	addsp 44
+    2c7e:	23          	storeh
+
+00002c7f <.LM313>:
+    2c7f:	97          	im 23
+    2c80:	18          	addsp 32
+    2c81:	33          	loadb
+    2c82:	96          	im 22
+    2c83:	19          	addsp 36
+    2c84:	33          	loadb
+    2c85:	71          	loadsp 4
+    2c86:	88          	im 8
+    2c87:	2b          	ashiftleft
+    2c88:	07          	or
+    2c89:	56          	storesp 24
+    2c8a:	56          	storesp 24
+    2c8b:	74          	loadsp 16
+    2c8c:	86          	im 6
+    2c8d:	1b          	addsp 44
+    2c8e:	23          	storeh
+
+00002c8f <.L220>:
+    2c8f:	80          	im 0
+    2c90:	77          	loadsp 28
+    2c91:	34          	storeb
+
+00002c92 <.LBE26>:
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+    2c92:	78          	loadsp 32
+    2c93:	51          	storesp 4
+    2c94:	eb          	im -21
+    2c95:	e3          	im -29
+    2c96:	3f          	callpcrel
+    2c97:	83          	im 3
+    2c98:	e0          	im -32
+    2c99:	80          	im 0
+    2c9a:	08          	load
+    2c9b:	55          	storesp 20
+
+00002c9c <.LM316>:
+				if (res == FR_NO_FILE) {
+    2c9c:	83          	im 3
+    2c9d:	e0          	im -32
+    2c9e:	80          	im 0
+    2c9f:	08          	load
+    2ca0:	83          	im 3
+    2ca1:	2e          	eq
+    2ca2:	09          	not
+    2ca3:	81          	im 1
+    2ca4:	06          	and
+    2ca5:	88          	im 8
+    2ca6:	38          	neqbranch
+
+00002ca7 <.LM317>:
+					dj->sect = 0;
+    2ca7:	80          	im 0
+    2ca8:	0b          	nop
+    2ca9:	90          	im 16
+    2caa:	1a          	addsp 40
+    2cab:	0c          	store
+
+00002cac <.LM318>:
+					res = FR_OK;
+    2cac:	80          	im 0
+    2cad:	55          	storesp 20
+
+00002cae <.L203>:
+				}
+			}
+		}
+	}
+
+	return res;
+}
+    2cae:	74          	loadsp 16
+    2caf:	83          	im 3
+    2cb0:	e0          	im -32
+    2cb1:	80          	im 0
+    2cb2:	0c          	store
+    2cb3:	97          	im 23
+    2cb4:	3d          	pushspadd
+    2cb5:	0d          	popsp
+    2cb6:	04          	poppc
+
+00002cb7 <.L211>:
+    2cb7:	78          	loadsp 32
+    2cb8:	51          	storesp 4
+    2cb9:	eb          	im -21
+    2cba:	be          	im 62
+    2cbb:	3f          	callpcrel
+    2cbc:	83          	im 3
+    2cbd:	e0          	im -32
+    2cbe:	80          	im 0
+    2cbf:	08          	load
+    2cc0:	55          	storesp 20
+
+00002cc1 <.LM321>:
+    2cc1:	83          	im 3
+    2cc2:	e0          	im -32
+    2cc3:	80          	im 0
+    2cc4:	08          	load
+    2cc5:	fe          	im -2
+    2cc6:	8f          	im 15
+    2cc7:	38          	neqbranch
+    2cc8:	90          	im 16
+    2cc9:	19          	addsp 36
+    2cca:	08          	load
+    2ccb:	80          	im 0
+    2ccc:	2e          	eq
+    2ccd:	fe          	im -2
+    2cce:	8c          	im 12
+    2ccf:	38          	neqbranch
+
+00002cd0 <.L215>:
+    2cd0:	a0          	im 32
+    2cd1:	54          	storesp 16
+    2cd2:	78          	loadsp 32
+    2cd3:	22          	loadh
+    2cd4:	70          	loadsp 0
+    2cd5:	85          	im 5
+    2cd6:	2b          	ashiftleft
+    2cd7:	83          	im 3
+    2cd8:	e0          	im -32
+    2cd9:	06          	and
+    2cda:	54          	storesp 16
+    2cdb:	56          	storesp 24
+    2cdc:	90          	im 16
+    2cdd:	19          	addsp 36
+    2cde:	08          	load
+    2cdf:	52          	storesp 8
+    2ce0:	77          	loadsp 28
+    2ce1:	51          	storesp 4
+    2ce2:	d8          	im -40
+    2ce3:	9b          	im 27
+    2ce4:	3f          	callpcrel
+    2ce5:	83          	im 3
+    2ce6:	e0          	im -32
+    2ce7:	80          	im 0
+    2ce8:	08          	load
+    2ce9:	80          	im 0
+    2cea:	f4          	im -12
+    2ceb:	38          	neqbranch
+
+00002cec <.LM323>:
+    2cec:	77          	loadsp 28
+    2ced:	33          	loadb
+    2cee:	56          	storesp 24
+
+00002cef <.LM324>:
+    2cef:	75          	loadsp 20
+    2cf0:	80          	im 0
+    2cf1:	2e          	eq
+    2cf2:	80          	im 0
+    2cf3:	f5          	im -11
+    2cf4:	38          	neqbranch
+
+00002cf5 <.LM325>:
+    2cf5:	8b          	im 11
+    2cf6:	18          	addsp 32
+    2cf7:	33          	loadb
+    2cf8:	bf          	im 63
+    2cf9:	06          	and
+
+00002cfa <.LM326>:
+    2cfa:	76          	loadsp 24
+    2cfb:	81          	im 1
+    2cfc:	e5          	im -27
+    2cfd:	32          	xor
+    2cfe:	70          	loadsp 0
+    2cff:	30          	neg
+    2d00:	70          	loadsp 0
+    2d01:	9f          	im 31
+    2d02:	2a          	lshiftright
+    2d03:	51          	storesp 4
+    2d04:	51          	storesp 4
+    2d05:	56          	storesp 24
+    2d06:	57          	storesp 28
+    2d07:	75          	loadsp 20
+    2d08:	ae          	im 46
+    2d09:	2e          	eq
+    2d0a:	ff          	im -1
+    2d0b:	ab          	im 43
+    2d0c:	38          	neqbranch
+    2d0d:	74          	loadsp 16
+    2d0e:	80          	im 0
+    2d0f:	2e          	eq
+    2d10:	ff          	im -1
+    2d11:	a5          	im 37
+    2d12:	38          	neqbranch
+    2d13:	76          	loadsp 24
+    2d14:	83          	im 3
+    2d15:	2a          	lshiftright
+    2d16:	70          	loadsp 0
+    2d17:	81          	im 1
+    2d18:	06          	and
+    2d19:	51          	storesp 4
+    2d1a:	55          	storesp 20
+    2d1b:	74          	loadsp 16
+    2d1c:	ff          	im -1
+    2d1d:	99          	im 25
+    2d1e:	38          	neqbranch
+    2d1f:	83          	im 3
+    2d20:	e0          	im -32
+    2d21:	80          	im 0
+    2d22:	08          	load
+    2d23:	55          	storesp 20
+
+00002d24 <.LM327>:
+    2d24:	74          	loadsp 16
+    2d25:	ff          	im -1
+    2d26:	87          	im 7
+    2d27:	38          	neqbranch
+    2d28:	fd          	im -3
+    2d29:	bb          	im 59
+    2d2a:	39          	poppcrel
+
+00002d2b <.L247>:
+    2d2b:	81          	im 1
+    2d2c:	e5          	im -27
+    2d2d:	55          	storesp 20
+
+00002d2e <.LM329>:
+    2d2e:	74          	loadsp 16
+    2d2f:	77          	loadsp 28
+    2d30:	70          	loadsp 0
+    2d31:	81          	im 1
+    2d32:	05          	add
+    2d33:	59          	storesp 36
+    2d34:	34          	storeb
+
+00002d35 <.LM330>:
+    2d35:	81          	im 1
+    2d36:	16          	addsp 24
+    2d37:	70          	loadsp 0
+    2d38:	81          	im 1
+    2d39:	ff          	im -1
+    2d3a:	06          	and
+    2d3b:	57          	storesp 28
+    2d3c:	55          	storesp 20
+    2d3d:	87          	im 7
+    2d3e:	76          	loadsp 24
+    2d3f:	27          	ulessthanorequal
+    2d40:	fd          	im -3
+    2d41:	b0          	im 48
+    2d42:	38          	neqbranch
+    2d43:	fd          	im -3
+    2d44:	d2          	im -46
+    2d45:	39          	poppcrel
+
+00002d46 <.L246>:
+    2d46:	80          	im 0
+    2d47:	0b          	nop
+    2d48:	90          	im 16
+    2d49:	1a          	addsp 40
+    2d4a:	0c          	store
+    2d4b:	fd          	im -3
+    2d4c:	98          	im 24
+    2d4d:	39          	poppcrel
+
+00002d4e <.L245>:
+    2d4e:	78          	loadsp 32
+    2d4f:	51          	storesp 4
+    2d50:	e9          	im -23
+    2d51:	c4          	im -60
+    2d52:	3f          	callpcrel
+    2d53:	83          	im 3
+    2d54:	e0          	im -32
+    2d55:	80          	im 0
+    2d56:	08          	load
+
+00002d57 <.LM333>:
+    2d57:	83          	im 3
+    2d58:	e0          	im -32
+    2d59:	80          	im 0
+    2d5a:	0c          	store
+    2d5b:	97          	im 23
+    2d5c:	3d          	pushspadd
+    2d5d:	0d          	popsp
+    2d5e:	04          	poppc
+
+00002d5f <.L238>:
+    2d5f:	81          	im 1
+    2d60:	55          	storesp 20
+
+00002d61 <.LM335>:
+    2d61:	80          	im 0
+    2d62:	0b          	nop
+    2d63:	90          	im 16
+    2d64:	1a          	addsp 40
+    2d65:	0c          	store
+    2d66:	fc          	im -4
+    2d67:	f3          	im -13
+    2d68:	39          	poppcrel
+
+00002d69 <.L239>:
+    2d69:	83          	im 3
+    2d6a:	55          	storesp 20
+
+00002d6b <.LM337>:
+    2d6b:	80          	im 0
+    2d6c:	0b          	nop
+    2d6d:	90          	im 16
+    2d6e:	1a          	addsp 40
+    2d6f:	0c          	store
+    2d70:	fc          	im -4
+    2d71:	e9          	im -23
+    2d72:	39          	poppcrel
+
+00002d73 <mmcInit>:
+#include "mmcconf.h"
+#include "debug.h"
+
+void mmcInit(void)
+{
+    2d73:	80          	im 0
+    2d74:	3d          	pushspadd
+    2d75:	0d          	popsp
+
+00002d76 <.LM2>:
+	// initialize SPI interface
+	spiInit();
+    2d76:	85          	im 5
+    2d77:	db          	im -37
+    2d78:	3f          	callpcrel
+
+00002d79 <.LM3>:
+	// release chip select
+	mmcChipSelect(0);
+    2d79:	80          	im 0
+    2d7a:	51          	storesp 4
+    2d7b:	85          	im 5
+    2d7c:	f0          	im -16
+    2d7d:	3f          	callpcrel
+    2d7e:	82          	im 2
+    2d7f:	3d          	pushspadd
+    2d80:	0d          	popsp
+    2d81:	04          	poppc
+
+00002d82 <mmcReadLoop>:
+}
+
+u08 mmcReset(void)
+{
+	u16 retry;
+	u08 r1;
+	u08 i;
+	u08 sdcard;
+
+	//
+	i=0xff; //255x
+	do { spiTransferFF(); i--; } while(i);	//255x
+
+	//
+	r1 = mmcSendCommand(MMC_GO_IDLE_STATE, 0);
+	if (r1!=1) return -1;
+
+	retry=0xffff; //65535x
+	do
+	{
+		r1 = mmcSendCommand(55, 0);
+		if (r1!=1) break; //MMC
+		//if (r1==5) break; //MMC  <--- kontrolovat takhle rekl Bob 27.6.2008
+								//Strana 120 ve specifikaci.
+								//bit 0 - in idle state, bit 2 - illegal command
+
+		r1 = mmcSendCommand(41, 0);
+		if (r1==0) break; //SD
+
+		retry--;
+	}
+	while(retry);
+
+	// initializing card for operation
+	r1 = mmcSendCommand(MMC_SEND_OP_COND, 0);
+	// SDkarty vraceji 0
+	// MMCkarta vraci 1
+	//if (r1>=2) return -1; //problem (MMC taky nefunguje)
+	if (r1!=0) return -1;
+
+	//kdyz jsem to tady nechal jit s MMC kartou dal (s r1=1)
+	//tak to na nekterem z dalsich povelu zustalo zasekle
+	//a po vytazeni MMC a vlozeni jine SD se muset mackat Reset :-(
+
+	/*
+	if( r1!=0  &&  r1!=5)
+	{
+		u08 v;
+		v=inb(PINC)&0xf0;
+		v|=(0x0f ^ (r1 & 0x0f) );
+		PORTC=v;
+	 	while(1); //nekonecna smycka
+	 return -1;
+	}
+	*/
+
+	// turn off CRC checking to simplify communication
+	//r1 = 
+	mmcSendCommand(MMC_CRC_ON_OFF, 0);
+
+	// set block length to 512 bytes
+	//r1 = 
+	mmcSendCommand(MMC_SET_BLOCKLEN, 512);
+
+	// return success
+	return 0;
+}
+
+u08 mmcSendCommand(u08 cmd, u32 arg)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	//
+	//spiTransferFF();			//pribude 34 bajtu kodu (!)
+	// issue the command
+	r1 = mmcCommand(cmd, arg);
+	//
+	//spiTransferFF();
+	// release chip select
+	mmcChipSelect(0);
+
+	return r1;
+}
+
+unsigned char mmc_sector_buffer[512];
+
+void mmcReadLoop()
+{
+    2d82:	ff          	im -1
+    2d83:	3d          	pushspadd
+    2d84:	0d          	popsp
+
+00002d85 <.LM5>:
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+    2d85:	83          	im 3
+    2d86:	e3          	im -29
+    2d87:	e8          	im -24
+    2d88:	52          	storesp 8
+
+00002d89 <.LM6>:
+
+	i=0x80;	//512
+    2d89:	81          	im 1
+    2d8a:	80          	im 0
+    2d8b:	51          	storesp 4
+
+00002d8c <.L3>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2d8c:	86          	im 6
+    2d8d:	d0          	im -48
+    2d8e:	3f          	callpcrel
+    2d8f:	83          	im 3
+    2d90:	e0          	im -32
+    2d91:	80          	im 0
+    2d92:	08          	load
+    2d93:	72          	loadsp 8
+    2d94:	70          	loadsp 0
+    2d95:	81          	im 1
+    2d96:	05          	add
+    2d97:	54          	storesp 16
+    2d98:	34          	storeb
+    2d99:	ff          	im -1
+    2d9a:	11          	addsp 4
+    2d9b:	70          	loadsp 0
+    2d9c:	83          	im 3
+    2d9d:	ff          	im -1
+    2d9e:	ff          	im -1
+    2d9f:	06          	and
+    2da0:	51          	storesp 4
+    2da1:	51          	storesp 4
+    2da2:	70          	loadsp 0
+    2da3:	e8          	im -24
+    2da4:	38          	neqbranch
+
+00002da5 <.LM8>:
+
+	//spiDisplay(1);
+	i=0x80;	//512
+    2da5:	81          	im 1
+    2da6:	80          	im 0
+    2da7:	51          	storesp 4
+
+00002da8 <.L6>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2da8:	86          	im 6
+    2da9:	b4          	im 52
+    2daa:	3f          	callpcrel
+    2dab:	83          	im 3
+    2dac:	e0          	im -32
+    2dad:	80          	im 0
+    2dae:	08          	load
+    2daf:	72          	loadsp 8
+    2db0:	70          	loadsp 0
+    2db1:	81          	im 1
+    2db2:	05          	add
+    2db3:	54          	storesp 16
+    2db4:	34          	storeb
+    2db5:	ff          	im -1
+    2db6:	11          	addsp 4
+    2db7:	70          	loadsp 0
+    2db8:	83          	im 3
+    2db9:	ff          	im -1
+    2dba:	ff          	im -1
+    2dbb:	06          	and
+    2dbc:	51          	storesp 4
+    2dbd:	51          	storesp 4
+    2dbe:	70          	loadsp 0
+    2dbf:	e8          	im -24
+    2dc0:	38          	neqbranch
+
+00002dc1 <.LM10>:
+
+	i=0x80;	//512
+    2dc1:	81          	im 1
+    2dc2:	80          	im 0
+    2dc3:	51          	storesp 4
+
+00002dc4 <.L9>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2dc4:	86          	im 6
+    2dc5:	98          	im 24
+    2dc6:	3f          	callpcrel
+    2dc7:	83          	im 3
+    2dc8:	e0          	im -32
+    2dc9:	80          	im 0
+    2dca:	08          	load
+    2dcb:	72          	loadsp 8
+    2dcc:	70          	loadsp 0
+    2dcd:	81          	im 1
+    2dce:	05          	add
+    2dcf:	54          	storesp 16
+    2dd0:	34          	storeb
+    2dd1:	ff          	im -1
+    2dd2:	11          	addsp 4
+    2dd3:	70          	loadsp 0
+    2dd4:	83          	im 3
+    2dd5:	ff          	im -1
+    2dd6:	ff          	im -1
+    2dd7:	06          	and
+    2dd8:	51          	storesp 4
+    2dd9:	51          	storesp 4
+    2dda:	70          	loadsp 0
+    2ddb:	e8          	im -24
+    2ddc:	38          	neqbranch
+
+00002ddd <.LM12>:
+
+	i=0x80;	//512
+    2ddd:	81          	im 1
+    2dde:	80          	im 0
+    2ddf:	51          	storesp 4
+
+00002de0 <.L12>:
+	do { *buffer++ = spiTransferFF(); i--; } while(i);
+    2de0:	85          	im 5
+    2de1:	fc          	im -4
+    2de2:	3f          	callpcrel
+    2de3:	83          	im 3
+    2de4:	e0          	im -32
+    2de5:	80          	im 0
+    2de6:	08          	load
+    2de7:	72          	loadsp 8
+    2de8:	70          	loadsp 0
+    2de9:	81          	im 1
+    2dea:	05          	add
+    2deb:	54          	storesp 16
+    2dec:	34          	storeb
+    2ded:	ff          	im -1
+    2dee:	11          	addsp 4
+    2def:	70          	loadsp 0
+    2df0:	83          	im 3
+    2df1:	ff          	im -1
+    2df2:	ff          	im -1
+    2df3:	06          	and
+    2df4:	51          	storesp 4
+    2df5:	51          	storesp 4
+    2df6:	70          	loadsp 0
+    2df7:	e8          	im -24
+    2df8:	38          	neqbranch
+    2df9:	83          	im 3
+    2dfa:	3d          	pushspadd
+    2dfb:	0d          	popsp
+    2dfc:	04          	poppc
+
+00002dfd <mmcCommand>:
+
+	//spiDisplay(0);
+
+}
+
+u08 mmcRead(u32 sector)
+{
+	u08 r1;
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_READ_SINGLE_BLOCK, sector<<9);
+
+	// check for valid response
+	if(r1 != 0x00) return r1;
+
+	// wait for block start
+	while(spiTransferFF() != MMC_STARTBLOCK_READ);
+
+	//zacatek bloku
+
+	//nacti 512 bytu
+	mmcReadLoop();
+
+	// read 16-bit CRC
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	//// + 1x FF navic pred releasnutim chip selectu
+	//spiTransferFF();
+	//
+	// release chip select
+	mmcChipSelect(0);
+
+	//debug("Hexdump\n");
+	//hexdump(mmc_sector_buffer,80);
+
+	//
+	return 0;	//success
+}
+
+u08 mmcWrite(u32 sector)
+{
+	u08 r1;
+	u16 i;
+	u08 *buffer=mmc_sector_buffer;	//natvrdo!
+
+	// assert chip select
+	mmcChipSelect(1);
+	// issue command
+	r1 = mmcCommand(MMC_WRITE_BLOCK, sector<<9);
+	// check for valid response
+	if(r1 != 0x00)
+		return r1;
+	// send dummy
+	spiTransferFF();
+	// send data start token
+	spiTransferByte(MMC_STARTBLOCK_WRITE);
+
+	// write data (512 bytes)
+	i=0x200;
+	do { spiTransferByte(*buffer++); i--; }	while(i);
+
+	// write 16-bit CRC (dummy values)
+	//2x FF:
+	spiTransferFF();
+	spiTransferFF();
+	// read data response token
+	r1 = spiTransferFF();
+	if( (r1&MMC_DR_MASK) != MMC_DR_ACCEPT)
+		return r1;
+	// wait until card not busy
+	while(!spiTransferFF());
+	// release chip select
+	mmcChipSelect(0);
+	// return success
+	return 0;
+}
+
+u08 mmcCommand(u08 cmd, u32 arg)
+{
+    2dfd:	fd          	im -3
+    2dfe:	3d          	pushspadd
+    2dff:	0d          	popsp
+    2e00:	76          	loadsp 24
+    2e01:	02          	pushsp
+    2e02:	84          	im 4
+    2e03:	05          	add
+    2e04:	97          	im 23
+    2e05:	05          	add
+    2e06:	33          	loadb
+    2e07:	53          	storesp 12
+    2e08:	53          	storesp 12
+
+00002e09 <.LM15>:
+	u08 r1;
+	u08 retry=0xff;	//255x
+    2e09:	81          	im 1
+    2e0a:	ff          	im -1
+    2e0b:	54          	storesp 16
+
+00002e0c <.LM16>:
+	//
+
+	spiTransferFF();
+    2e0c:	85          	im 5
+    2e0d:	d0          	im -48
+    2e0e:	3f          	callpcrel
+
+00002e0f <.LM17>:
+
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+    2e0f:	85          	im 5
+    2e10:	cd          	im -51
+    2e11:	3f          	callpcrel
+
+00002e12 <.LM18>:
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+    2e12:	85          	im 5
+    2e13:	ca          	im -54
+    2e14:	3f          	callpcrel
+
+00002e15 <.LM19>:
+	spiTransferFF();	//pridano navic! 27.6.2008 doporucil Bob!k
+    2e15:	85          	im 5
+    2e16:	c7          	im -57
+    2e17:	3f          	callpcrel
+
+00002e18 <.LM20>:
+
+	// send command
+	spiTransferByte(cmd | 0x40);
+    2e18:	71          	loadsp 4
+    2e19:	80          	im 0
+    2e1a:	c0          	im -64
+    2e1b:	07          	or
+    2e1c:	51          	storesp 4
+    2e1d:	84          	im 4
+    2e1e:	e4          	im -28
+    2e1f:	3f          	callpcrel
+
+00002e20 <.LM21>:
+	//
+	spiTransferByte(arg>>24);
+    2e20:	72          	loadsp 8
+    2e21:	98          	im 24
+    2e22:	2a          	lshiftright
+    2e23:	51          	storesp 4
+    2e24:	84          	im 4
+    2e25:	dd          	im -35
+    2e26:	3f          	callpcrel
+
+00002e27 <.LM22>:
+	spiTransferByte(arg>>16);
+    2e27:	72          	loadsp 8
+    2e28:	90          	im 16
+    2e29:	2a          	lshiftright
+    2e2a:	70          	loadsp 0
+    2e2b:	81          	im 1
+    2e2c:	ff          	im -1
+    2e2d:	06          	and
+    2e2e:	52          	storesp 8
+    2e2f:	52          	storesp 8
+    2e30:	84          	im 4
+    2e31:	d1          	im -47
+    2e32:	3f          	callpcrel
+
+00002e33 <.LM23>:
+	spiTransferByte(arg>>8);
+    2e33:	72          	loadsp 8
+    2e34:	88          	im 8
+    2e35:	2a          	lshiftright
+    2e36:	70          	loadsp 0
+    2e37:	81          	im 1
+    2e38:	ff          	im -1
+    2e39:	06          	and
+    2e3a:	52          	storesp 8
+    2e3b:	52          	storesp 8
+    2e3c:	84          	im 4
+    2e3d:	c5          	im -59
+    2e3e:	3f          	callpcrel
+
+00002e3f <.LM24>:
+	spiTransferByte(arg);
+    2e3f:	72          	loadsp 8
+    2e40:	81          	im 1
+    2e41:	ff          	im -1
+    2e42:	06          	and
+    2e43:	51          	storesp 4
+    2e44:	84          	im 4
+    2e45:	bd          	im 61
+    2e46:	3f          	callpcrel
+
+00002e47 <.LM25>:
+	//Alternativni zpusob pres ((u08*)&arg)[] je delsi.
+
+	spiTransferByte(0x95);	// crc valid only for MMC_GO_IDLE_STATE
+    2e47:	81          	im 1
+    2e48:	95          	im 21
+    2e49:	51          	storesp 4
+    2e4a:	84          	im 4
+    2e4b:	b7          	im 55
+    2e4c:	3f          	callpcrel
+
+00002e4d <.L17>:
+	// end command
+	// wait for response
+	// if more than 255 retries, card has timed-out
+	// return the received 0xFF
+	do
+	{
+		r1 = spiTransferFF();
+    2e4d:	85          	im 5
+    2e4e:	8f          	im 15
+    2e4f:	3f          	callpcrel
+    2e50:	83          	im 3
+    2e51:	e0          	im -32
+    2e52:	80          	im 0
+    2e53:	08          	load
+    2e54:	81          	im 1
+    2e55:	ff          	im -1
+    2e56:	06          	and
+
+00002e57 <.LM27>:
+		retry--;
+    2e57:	ff          	im -1
+    2e58:	15          	addsp 20
+    2e59:	70          	loadsp 0
+    2e5a:	81          	im 1
+    2e5b:	ff          	im -1
+    2e5c:	06          	and
+
+00002e5d <.LM28>:
+	}
+    2e5d:	70          	loadsp 0
+    2e5e:	30          	neg
+    2e5f:	70          	loadsp 0
+    2e60:	9f          	im 31
+    2e61:	2a          	lshiftright
+    2e62:	51          	storesp 4
+    2e63:	52          	storesp 8
+    2e64:	56          	storesp 24
+    2e65:	53          	storesp 12
+    2e66:	53          	storesp 12
+    2e67:	72          	loadsp 8
+    2e68:	81          	im 1
+    2e69:	ff          	im -1
+    2e6a:	2e          	eq
+    2e6b:	09          	not
+    2e6c:	81          	im 1
+    2e6d:	06          	and
+    2e6e:	84          	im 4
+    2e6f:	38          	neqbranch
+    2e70:	71          	loadsp 4
+    2e71:	db          	im -37
+    2e72:	38          	neqbranch
+
+00002e73 <.L22>:
+	while(retry && (r1 == 0xFF) );
+
+	// return response
+	return r1;
+}
+    2e73:	72          	loadsp 8
+    2e74:	83          	im 3
+    2e75:	e0          	im -32
+    2e76:	80          	im 0
+    2e77:	0c          	store
+    2e78:	85          	im 5
+    2e79:	3d          	pushspadd
+    2e7a:	0d          	popsp
+    2e7b:	04          	poppc
+
+00002e7c <mmcRead>:
+    2e7c:	fd          	im -3
+    2e7d:	3d          	pushspadd
+    2e7e:	0d          	popsp
+
+00002e7f <.LM31>:
+    2e7f:	81          	im 1
+    2e80:	51          	storesp 4
+    2e81:	83          	im 3
+    2e82:	ea          	im -22
+    2e83:	3f          	callpcrel
+
+00002e84 <.LM32>:
+    2e84:	75          	loadsp 20
+    2e85:	89          	im 9
+    2e86:	2b          	ashiftleft
+    2e87:	52          	storesp 8
+    2e88:	91          	im 17
+    2e89:	51          	storesp 4
+    2e8a:	fe          	im -2
+    2e8b:	f1          	im -15
+    2e8c:	3f          	callpcrel
+    2e8d:	83          	im 3
+    2e8e:	e0          	im -32
+    2e8f:	80          	im 0
+    2e90:	08          	load
+    2e91:	81          	im 1
+    2e92:	ff          	im -1
+    2e93:	06          	and
+
+00002e94 <.LM33>:
+    2e94:	70          	loadsp 0
+    2e95:	55          	storesp 20
+    2e96:	53          	storesp 12
+    2e97:	72          	loadsp 8
+    2e98:	80          	im 0
+    2e99:	2e          	eq
+    2e9a:	8a          	im 10
+    2e9b:	38          	neqbranch
+
+00002e9c <.LM34>:
+    2e9c:	73          	loadsp 12
+    2e9d:	83          	im 3
+    2e9e:	e0          	im -32
+    2e9f:	80          	im 0
+    2ea0:	0c          	store
+    2ea1:	85          	im 5
+    2ea2:	3d          	pushspadd
+    2ea3:	0d          	popsp
+    2ea4:	04          	poppc
+
+00002ea5 <.L27>:
+    2ea5:	84          	im 4
+    2ea6:	b7          	im 55
+    2ea7:	3f          	callpcrel
+    2ea8:	83          	im 3
+    2ea9:	e0          	im -32
+    2eaa:	80          	im 0
+    2eab:	08          	load
+    2eac:	81          	im 1
+    2ead:	ff          	im -1
+    2eae:	06          	and
+    2eaf:	53          	storesp 12
+    2eb0:	72          	loadsp 8
+    2eb1:	81          	im 1
+    2eb2:	fe          	im -2
+    2eb3:	2e          	eq
+    2eb4:	09          	not
+    2eb5:	81          	im 1
+    2eb6:	06          	and
+    2eb7:	ed          	im -19
+    2eb8:	38          	neqbranch
+
+00002eb9 <.LM36>:
+    2eb9:	fd          	im -3
+    2eba:	c7          	im -57
+    2ebb:	3f          	callpcrel
+
+00002ebc <.LM37>:
+    2ebc:	84          	im 4
+    2ebd:	a0          	im 32
+    2ebe:	3f          	callpcrel
+
+00002ebf <.LM38>:
+    2ebf:	84          	im 4
+    2ec0:	9d          	im 29
+    2ec1:	3f          	callpcrel
+
+00002ec2 <.LM39>:
+    2ec2:	80          	im 0
+    2ec3:	51          	storesp 4
+    2ec4:	83          	im 3
+    2ec5:	a7          	im 39
+    2ec6:	3f          	callpcrel
+
+00002ec7 <.LM40>:
+    2ec7:	80          	im 0
+
+00002ec8 <.LM41>:
+    2ec8:	0b          	nop
+    2ec9:	83          	im 3
+    2eca:	e0          	im -32
+    2ecb:	80          	im 0
+    2ecc:	0c          	store
+    2ecd:	85          	im 5
+    2ece:	3d          	pushspadd
+    2ecf:	0d          	popsp
+    2ed0:	04          	poppc
+
+00002ed1 <mmcSendCommand>:
+    2ed1:	fe          	im -2
+    2ed2:	3d          	pushspadd
+    2ed3:	0d          	popsp
+    2ed4:	02          	pushsp
+    2ed5:	93          	im 19
+    2ed6:	05          	add
+    2ed7:	33          	loadb
+    2ed8:	53          	storesp 12
+
+00002ed9 <.LM43>:
+    2ed9:	81          	im 1
+    2eda:	51          	storesp 4
+    2edb:	83          	im 3
+    2edc:	90          	im 16
+    2edd:	3f          	callpcrel
+
+00002ede <.LM44>:
+    2ede:	75          	loadsp 20
+    2edf:	52          	storesp 8
+    2ee0:	72          	loadsp 8
+    2ee1:	51          	storesp 4
+    2ee2:	fe          	im -2
+    2ee3:	99          	im 25
+    2ee4:	3f          	callpcrel
+    2ee5:	83          	im 3
+    2ee6:	e0          	im -32
+    2ee7:	80          	im 0
+    2ee8:	08          	load
+    2ee9:	81          	im 1
+    2eea:	ff          	im -1
+    2eeb:	06          	and
+    2eec:	53          	storesp 12
+
+00002eed <.LM45>:
+    2eed:	80          	im 0
+    2eee:	51          	storesp 4
+    2eef:	82          	im 2
+    2ef0:	fc          	im -4
+    2ef1:	3f          	callpcrel
+
+00002ef2 <.LM46>:
+    2ef2:	72          	loadsp 8
+    2ef3:	83          	im 3
+    2ef4:	e0          	im -32
+    2ef5:	80          	im 0
+    2ef6:	0c          	store
+    2ef7:	84          	im 4
+    2ef8:	3d          	pushspadd
+    2ef9:	0d          	popsp
+    2efa:	04          	poppc
+
+00002efb <mmcReset>:
+    2efb:	fd          	im -3
+    2efc:	3d          	pushspadd
+    2efd:	0d          	popsp
+
+00002efe <.LM48>:
+    2efe:	81          	im 1
+    2eff:	ff          	im -1
+    2f00:	53          	storesp 12
+
+00002f01 <.L32>:
+    2f01:	83          	im 3
+    2f02:	db          	im -37
+    2f03:	3f          	callpcrel
+    2f04:	ff          	im -1
+    2f05:	13          	addsp 12
+    2f06:	70          	loadsp 0
+    2f07:	81          	im 1
+    2f08:	ff          	im -1
+    2f09:	06          	and
+    2f0a:	51          	storesp 4
+    2f0b:	53          	storesp 12
+    2f0c:	72          	loadsp 8
+    2f0d:	f3          	im -13
+    2f0e:	38          	neqbranch
+
+00002f0f <.LM50>:
+    2f0f:	72          	loadsp 8
+    2f10:	52          	storesp 8
+    2f11:	72          	loadsp 8
+    2f12:	51          	storesp 4
+    2f13:	ff          	im -1
+    2f14:	bc          	im 60
+    2f15:	3f          	callpcrel
+    2f16:	83          	im 3
+    2f17:	e0          	im -32
+    2f18:	80          	im 0
+    2f19:	08          	load
+    2f1a:	81          	im 1
+    2f1b:	ff          	im -1
+    2f1c:	06          	and
+    2f1d:	53          	storesp 12
+
+00002f1e <.LM51>:
+    2f1e:	81          	im 1
+    2f1f:	ff          	im -1
+    2f20:	54          	storesp 16
+    2f21:	72          	loadsp 8
+    2f22:	81          	im 1
+    2f23:	2e          	eq
+    2f24:	09          	not
+    2f25:	81          	im 1
+    2f26:	06          	and
+    2f27:	80          	im 0
+    2f28:	e2          	im -30
+    2f29:	38          	neqbranch
+
+00002f2a <.LM52>:
+    2f2a:	83          	im 3
+    2f2b:	ff          	im -1
+    2f2c:	ff          	im -1
+    2f2d:	54          	storesp 16
+
+00002f2e <.L36>:
+    2f2e:	80          	im 0
+    2f2f:	52          	storesp 8
+    2f30:	b7          	im 55
+    2f31:	51          	storesp 4
+    2f32:	ff          	im -1
+    2f33:	9d          	im 29
+    2f34:	3f          	callpcrel
+    2f35:	83          	im 3
+    2f36:	e0          	im -32
+    2f37:	80          	im 0
+    2f38:	08          	load
+    2f39:	81          	im 1
+    2f3a:	ff          	im -1
+    2f3b:	06          	and
+    2f3c:	53          	storesp 12
+
+00002f3d <.LM54>:
+    2f3d:	72          	loadsp 8
+    2f3e:	81          	im 1
+    2f3f:	2e          	eq
+    2f40:	09          	not
+    2f41:	81          	im 1
+    2f42:	06          	and
+    2f43:	a1          	im 33
+    2f44:	38          	neqbranch
+
+00002f45 <.LM55>:
+    2f45:	80          	im 0
+    2f46:	52          	storesp 8
+    2f47:	a9          	im 41
+    2f48:	51          	storesp 4
+    2f49:	ff          	im -1
+    2f4a:	86          	im 6
+    2f4b:	3f          	callpcrel
+    2f4c:	83          	im 3
+    2f4d:	e0          	im -32
+    2f4e:	80          	im 0
+    2f4f:	08          	load
+    2f50:	81          	im 1
+    2f51:	ff          	im -1
+    2f52:	06          	and
+    2f53:	53          	storesp 12
+
+00002f54 <.LM56>:
+    2f54:	72          	loadsp 8
+    2f55:	80          	im 0
+    2f56:	2e          	eq
+    2f57:	8d          	im 13
+    2f58:	38          	neqbranch
+
+00002f59 <.LM57>:
+    2f59:	ff          	im -1
+    2f5a:	14          	addsp 16
+    2f5b:	70          	loadsp 0
+    2f5c:	83          	im 3
+    2f5d:	ff          	im -1
+    2f5e:	ff          	im -1
+    2f5f:	06          	and
+    2f60:	55          	storesp 20
+    2f61:	53          	storesp 12
+
+00002f62 <.LM58>:
+    2f62:	73          	loadsp 12
+    2f63:	ca          	im -54
+    2f64:	38          	neqbranch
+
+00002f65 <.L37>:
+    2f65:	80          	im 0
+    2f66:	52          	storesp 8
+    2f67:	81          	im 1
+    2f68:	51          	storesp 4
+    2f69:	fe          	im -2
+    2f6a:	e6          	im -26
+    2f6b:	3f          	callpcrel
+    2f6c:	83          	im 3
+    2f6d:	e0          	im -32
+    2f6e:	80          	im 0
+    2f6f:	08          	load
+    2f70:	81          	im 1
+    2f71:	ff          	im -1
+    2f72:	06          	and
+    2f73:	53          	storesp 12
+
+00002f74 <.LM60>:
+    2f74:	81          	im 1
+    2f75:	ff          	im -1
+    2f76:	54          	storesp 16
+    2f77:	72          	loadsp 8
+    2f78:	92          	im 18
+    2f79:	38          	neqbranch
+
+00002f7a <.LM61>:
+    2f7a:	72          	loadsp 8
+    2f7b:	52          	storesp 8
+    2f7c:	bb          	im 59
+    2f7d:	51          	storesp 4
+    2f7e:	fe          	im -2
+    2f7f:	d1          	im -47
+    2f80:	3f          	callpcrel
+
+00002f81 <.LM62>:
+    2f81:	84          	im 4
+    2f82:	80          	im 0
+    2f83:	52          	storesp 8
+    2f84:	90          	im 16
+    2f85:	51          	storesp 4
+    2f86:	fe          	im -2
+    2f87:	c9          	im -55
+    2f88:	3f          	callpcrel
+
+00002f89 <.LM63>:
+    2f89:	72          	loadsp 8
+    2f8a:	54          	storesp 16
+
+00002f8b <.L31>:
+    2f8b:	73          	loadsp 12
+    2f8c:	83          	im 3
+    2f8d:	e0          	im -32
+    2f8e:	80          	im 0
+    2f8f:	0c          	store
+    2f90:	85          	im 5
+    2f91:	3d          	pushspadd
+    2f92:	0d          	popsp
+    2f93:	04          	poppc
+
+00002f94 <mmcWrite>:
+    2f94:	fb          	im -5
+    2f95:	3d          	pushspadd
+    2f96:	0d          	popsp
+
+00002f97 <.LM66>:
+    2f97:	83          	im 3
+    2f98:	e3          	im -29
+    2f99:	e8          	im -24
+    2f9a:	56          	storesp 24
+
+00002f9b <.LM67>:
+    2f9b:	81          	im 1
+    2f9c:	51          	storesp 4
+    2f9d:	81          	im 1
+    2f9e:	ce          	im -50
+    2f9f:	3f          	callpcrel
+
+00002fa0 <.LM68>:
+    2fa0:	77          	loadsp 28
+    2fa1:	89          	im 9
+    2fa2:	2b          	ashiftleft
+    2fa3:	52          	storesp 8
+    2fa4:	98          	im 24
+    2fa5:	51          	storesp 4
+    2fa6:	fc          	im -4
+    2fa7:	d5          	im -43
+    2fa8:	3f          	callpcrel
+    2fa9:	83          	im 3
+    2faa:	e0          	im -32
+    2fab:	80          	im 0
+    2fac:	08          	load
+    2fad:	81          	im 1
+    2fae:	ff          	im -1
+    2faf:	06          	and
+
+00002fb0 <.LM69>:
+    2fb0:	70          	loadsp 0
+    2fb1:	56          	storesp 24
+    2fb2:	54          	storesp 16
+
+00002fb3 <.LM70>:
+    2fb3:	73          	loadsp 12
+    2fb4:	80          	im 0
+    2fb5:	2e          	eq
+    2fb6:	8a          	im 10
+    2fb7:	38          	neqbranch
+
+00002fb8 <.L43>:
+    2fb8:	74          	loadsp 16
+    2fb9:	83          	im 3
+    2fba:	e0          	im -32
+    2fbb:	80          	im 0
+    2fbc:	0c          	store
+    2fbd:	87          	im 7
+    2fbe:	3d          	pushspadd
+    2fbf:	0d          	popsp
+    2fc0:	04          	poppc
+
+00002fc1 <.L52>:
+    2fc1:	82          	im 2
+    2fc2:	9b          	im 27
+    2fc3:	3f          	callpcrel
+
+00002fc4 <.LM73>:
+    2fc4:	81          	im 1
+    2fc5:	fe          	im -2
+    2fc6:	51          	storesp 4
+    2fc7:	81          	im 1
+    2fc8:	ba          	im 58
+    2fc9:	3f          	callpcrel
+
+00002fca <.LM74>:
+    2fca:	84          	im 4
+    2fcb:	80          	im 0
+    2fcc:	53          	storesp 12
+
+00002fcd <.L45>:
+    2fcd:	75          	loadsp 20
+    2fce:	70          	loadsp 0
+    2fcf:	81          	im 1
+    2fd0:	05          	add
+    2fd1:	57          	storesp 28
+    2fd2:	33          	loadb
+    2fd3:	51          	storesp 4
+    2fd4:	81          	im 1
+    2fd5:	ad          	im 45
+    2fd6:	3f          	callpcrel
+    2fd7:	ff          	im -1
+    2fd8:	13          	addsp 12
+    2fd9:	70          	loadsp 0
+    2fda:	83          	im 3
+    2fdb:	ff          	im -1
+    2fdc:	ff          	im -1
+    2fdd:	06          	and
+    2fde:	51          	storesp 4
+    2fdf:	53          	storesp 12
+    2fe0:	72          	loadsp 8
+    2fe1:	eb          	im -21
+    2fe2:	38          	neqbranch
+
+00002fe3 <.LM76>:
+    2fe3:	81          	im 1
+    2fe4:	f9          	im -7
+    2fe5:	3f          	callpcrel
+
+00002fe6 <.LM77>:
+    2fe6:	81          	im 1
+    2fe7:	f6          	im -10
+    2fe8:	3f          	callpcrel
+
+00002fe9 <.LM78>:
+    2fe9:	81          	im 1
+    2fea:	f3          	im -13
+    2feb:	3f          	callpcrel
+    2fec:	83          	im 3
+    2fed:	e0          	im -32
+    2fee:	80          	im 0
+    2fef:	08          	load
+    2ff0:	81          	im 1
+    2ff1:	ff          	im -1
+    2ff2:	06          	and
+
+00002ff3 <.LM79>:
+    2ff3:	70          	loadsp 0
+    2ff4:	9f          	im 31
+    2ff5:	06          	and
+
+00002ff6 <.LM80>:
+    2ff6:	54          	storesp 16
+    2ff7:	55          	storesp 20
+
+00002ff8 <.LM81>:
+    2ff8:	72          	loadsp 8
+    2ff9:	85          	im 5
+    2ffa:	2e          	eq
+    2ffb:	09          	not
+    2ffc:	81          	im 1
+    2ffd:	06          	and
+    2ffe:	ff          	im -1
+    2fff:	b8          	im 56
+    3000:	38          	neqbranch
+
+00003001 <.L49>:
+    3001:	81          	im 1
+    3002:	db          	im -37
+    3003:	3f          	callpcrel
+    3004:	83          	im 3
+    3005:	e0          	im -32
+    3006:	80          	im 0
+    3007:	08          	load
+    3008:	81          	im 1
+    3009:	ff          	im -1
+    300a:	06          	and
+    300b:	53          	storesp 12
+    300c:	72          	loadsp 8
+    300d:	80          	im 0
+    300e:	2e          	eq
+    300f:	f1          	im -15
+    3010:	38          	neqbranch
+
+00003011 <.LM83>:
+    3011:	80          	im 0
+    3012:	51          	storesp 4
+    3013:	80          	im 0
+    3014:	d8          	im -40
+    3015:	3f          	callpcrel
+
+00003016 <.LM84>:
+    3016:	80          	im 0
+
+00003017 <.LM85>:
+    3017:	0b          	nop
+    3018:	83          	im 3
+    3019:	e0          	im -32
+    301a:	80          	im 0
+    301b:	0c          	store
+    301c:	87          	im 7
+    301d:	3d          	pushspadd
+    301e:	0d          	popsp
+    301f:	04          	poppc
+
+00003020 <updateSpiState>:
+int spi_slow; // 1 is slow
+int spi_chip_select_n; // 0 is selected
+int display;
+void updateSpiState()
+{
+    3020:	ff          	im -1
+    3021:	3d          	pushspadd
+    3022:	0d          	popsp
+
+00003023 <.LM2>:
+	*zpu_spi_state = (spi_slow<<1)|(spi_chip_select_n);
+    3023:	83          	im 3
+    3024:	e7          	im -25
+    3025:	f0          	im -16
+    3026:	08          	load
+    3027:	10          	addsp 0
+    3028:	83          	im 3
+    3029:	e7          	im -25
+    302a:	e8          	im -24
+    302b:	08          	load
+    302c:	07          	or
+    302d:	80          	im 0
+    302e:	fc          	im -4
+    302f:	a8          	im 40
+    3030:	08          	load
+    3031:	52          	storesp 8
+    3032:	71          	loadsp 4
+    3033:	0c          	store
+    3034:	83          	im 3
+    3035:	3d          	pushspadd
+    3036:	0d          	popsp
+    3037:	04          	poppc
+
+00003038 <setSpiFast>:
+}
+
+// access routines
+void setSpiFast()
+{
+	spi_slow = 0;
+    3038:	80          	im 0
+    3039:	0b          	nop
+    303a:	83          	im 3
+    303b:	e7          	im -25
+    303c:	f0          	im -16
+    303d:	0c          	store
+
+0000303e <.LM5>:
+	updateSpiState();
+    303e:	e1          	im -31
+    303f:	3f          	callpcrel
+    3040:	04          	poppc
+
+00003041 <setSpiSlow>:
+}
+
+void setSpiSlow()
+{
+	spi_slow = 1;
+    3041:	81          	im 1
+    3042:	0b          	nop
+    3043:	83          	im 3
+    3044:	e7          	im -25
+    3045:	f0          	im -16
+    3046:	0c          	store
+
+00003047 <.LM8>:
+	updateSpiState();
+    3047:	d8          	im -40
+    3048:	3f          	callpcrel
+    3049:	04          	poppc
+
+0000304a <set_spi_clock_freq>:
+}
+
+void set_spi_clock_freq() // avr handles spi clock?
+{
+	setSpiFast();
+    304a:	ed          	im -19
+    304b:	3f          	callpcrel
+    304c:	04          	poppc
+
+0000304d <spiDisplay>:
+}
+
+void spiInit()
+{
+	spiDisplay(0);
+	spi_slow = 1;
+	spi_chip_select_n = 1;
+	updateSpiState();
+}
+
+void mmcChipSelect(int select)
+{
+	spi_chip_select_n = !select;
+	updateSpiState();
+}
+
+u08 spiTransferByte(u08 data)
+{
+	u08 res = 0;
+
+	//debug("spiTransferByte");
+
+	/*if (display!=0)
+	{
+		plotnext(hextoatarichar((data&0xf0) >> 4));
+		plotnext(hextoatarichar((data&0xf)));
+	}*/
+
+	// send the given data
+	*zpu_spi_data = data;
+
+	// wait for transfer to complete
+	while ((1&*zpu_spi_state) == 1);
+
+	// return the received data
+	res = *zpu_spi_data;
+
+	if (display!=0)
+	{
+		plotnext(hextoatarichar((res&0xf0) >> 4));
+		plotnext(hextoatarichar((res&0xf)));
+
+		//plotnext(toatarichar(' '));
+	}
+
+	return res;
+}
+
+u08 spiTransferFF()
+{
+	return spiTransferByte(0xFF);
+}
+
+void spiDisplay(int i)
+{
+	display = i;
+    304d:	71          	loadsp 4
+    304e:	83          	im 3
+    304f:	e7          	im -25
+    3050:	ec          	im -20
+    3051:	0c          	store
+    3052:	04          	poppc
+
+00003053 <spiInit>:
+    3053:	80          	im 0
+    3054:	3d          	pushspadd
+    3055:	0d          	popsp
+
+00003056 <.LM14>:
+    3056:	80          	im 0
+    3057:	51          	storesp 4
+    3058:	f4          	im -12
+    3059:	3f          	callpcrel
+
+0000305a <.LM15>:
+    305a:	81          	im 1
+    305b:	0b          	nop
+    305c:	83          	im 3
+    305d:	e7          	im -25
+    305e:	f0          	im -16
+    305f:	0c          	store
+
+00003060 <.LM16>:
+    3060:	81          	im 1
+    3061:	0b          	nop
+    3062:	83          	im 3
+    3063:	e7          	im -25
+    3064:	e8          	im -24
+    3065:	0c          	store
+
+00003066 <.LM17>:
+    3066:	ff          	im -1
+    3067:	b8          	im 56
+    3068:	3f          	callpcrel
+    3069:	82          	im 2
+    306a:	3d          	pushspadd
+    306b:	0d          	popsp
+    306c:	04          	poppc
+
+0000306d <mmcChipSelect>:
+    306d:	80          	im 0
+    306e:	3d          	pushspadd
+    306f:	0d          	popsp
+
+00003070 <.LM19>:
+    3070:	72          	loadsp 8
+    3071:	30          	neg
+    3072:	70          	loadsp 0
+    3073:	74          	loadsp 16
+    3074:	07          	or
+    3075:	80          	im 0
+    3076:	25          	lessthanorequal
+    3077:	83          	im 3
+    3078:	e7          	im -25
+    3079:	e8          	im -24
+    307a:	0c          	store
+    307b:	51          	storesp 4
+
+0000307c <.LM20>:
+    307c:	ff          	im -1
+    307d:	a2          	im 34
+    307e:	3f          	callpcrel
+    307f:	82          	im 2
+    3080:	3d          	pushspadd
+    3081:	0d          	popsp
+    3082:	04          	poppc
+
+00003083 <spiTransferByte>:
+    3083:	fd          	im -3
+    3084:	3d          	pushspadd
+    3085:	0d          	popsp
+    3086:	02          	pushsp
+    3087:	97          	im 23
+    3088:	05          	add
+    3089:	33          	loadb
+
+0000308a <.LM22>:
+    308a:	80          	im 0
+    308b:	fc          	im -4
+    308c:	ac          	im 44
+    308d:	08          	load
+    308e:	55          	storesp 20
+    308f:	74          	loadsp 16
+    3090:	0c          	store
+    3091:	80          	im 0
+    3092:	fc          	im -4
+    3093:	a8          	im 40
+    3094:	08          	load
+    3095:	53          	storesp 12
+
+00003096 <.L10>:
+    3096:	72          	loadsp 8
+    3097:	08          	load
+    3098:	70          	loadsp 0
+    3099:	81          	im 1
+    309a:	06          	and
+    309b:	51          	storesp 4
+    309c:	52          	storesp 8
+    309d:	71          	loadsp 4
+    309e:	f7          	im -9
+    309f:	38          	neqbranch
+
+000030a0 <.LM24>:
+    30a0:	73          	loadsp 12
+    30a1:	08          	load
+    30a2:	70          	loadsp 0
+    30a3:	81          	im 1
+    30a4:	ff          	im -1
+    30a5:	06          	and
+    30a6:	51          	storesp 4
+    30a7:	52          	storesp 8
+
+000030a8 <.LM25>:
+    30a8:	83          	im 3
+    30a9:	e7          	im -25
+    30aa:	ec          	im -20
+    30ab:	08          	load
+    30ac:	8a          	im 10
+    30ad:	38          	neqbranch
+
+000030ae <.LM26>:
+    30ae:	71          	loadsp 4
+    30af:	83          	im 3
+    30b0:	e0          	im -32
+    30b1:	80          	im 0
+    30b2:	0c          	store
+    30b3:	85          	im 5
+    30b4:	3d          	pushspadd
+    30b5:	0d          	popsp
+    30b6:	04          	poppc
+
+000030b7 <.L14>:
+    30b7:	71          	loadsp 4
+    30b8:	84          	im 4
+    30b9:	2a          	lshiftright
+    30ba:	51          	storesp 4
+    30bb:	85          	im 5
+    30bc:	fa          	im -6
+    30bd:	3f          	callpcrel
+    30be:	83          	im 3
+    30bf:	e0          	im -32
+    30c0:	80          	im 0
+    30c1:	08          	load
+    30c2:	51          	storesp 4
+    30c3:	87          	im 7
+    30c4:	85          	im 5
+    30c5:	3f          	callpcrel
+
+000030c6 <.LM28>:
+    30c6:	71          	loadsp 4
+    30c7:	8f          	im 15
+    30c8:	06          	and
+    30c9:	51          	storesp 4
+    30ca:	85          	im 5
+    30cb:	eb          	im -21
+    30cc:	3f          	callpcrel
+    30cd:	83          	im 3
+    30ce:	e0          	im -32
+    30cf:	80          	im 0
+    30d0:	08          	load
+    30d1:	51          	storesp 4
+    30d2:	86          	im 6
+    30d3:	f6          	im -10
+    30d4:	3f          	callpcrel
+
+000030d5 <.LBE2>:
+    30d5:	71          	loadsp 4
+    30d6:	83          	im 3
+    30d7:	e0          	im -32
+    30d8:	80          	im 0
+    30d9:	0c          	store
+    30da:	85          	im 5
+    30db:	3d          	pushspadd
+    30dc:	0d          	popsp
+    30dd:	04          	poppc
+
+000030de <spiTransferFF>:
+    30de:	80          	im 0
+    30df:	3d          	pushspadd
+    30e0:	0d          	popsp
+
+000030e1 <.LM31>:
+    30e1:	81          	im 1
+    30e2:	ff          	im -1
+    30e3:	51          	storesp 4
+    30e4:	ff          	im -1
+    30e5:	9d          	im 29
+    30e6:	3f          	callpcrel
+    30e7:	83          	im 3
+    30e8:	e0          	im -32
+    30e9:	80          	im 0
+    30ea:	08          	load
+    30eb:	81          	im 1
+    30ec:	ff          	im -1
+    30ed:	06          	and
+    30ee:	83          	im 3
+    30ef:	e0          	im -32
+    30f0:	80          	im 0
+    30f1:	0c          	store
+
+000030f2 <.LM32>:
+    30f2:	82          	im 2
+    30f3:	3d          	pushspadd
+    30f4:	0d          	popsp
+    30f5:	04          	poppc
+
+000030f6 <USART_Data_Needed>:
+
+void actions();
+
+int USART_Data_Needed()
+{
+    30f6:	fe          	im -2
+    30f7:	3d          	pushspadd
+    30f8:	0d          	popsp
+
+000030f9 <.LM2>:
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+    30f9:	80          	im 0
+    30fa:	fb          	im -5
+    30fb:	ec          	im -20
+    30fc:	08          	load
+    30fd:	70          	loadsp 0
+    30fe:	33          	loadb
+    30ff:	70          	loadsp 0
+    3100:	81          	im 1
+    3101:	ff          	im -1
+    3102:	06          	and
+    3103:	70          	loadsp 0
+    3104:	84          	im 4
+    3105:	2a          	lshiftright
+    3106:	81          	im 1
+    3107:	32          	xor
+    3108:	81          	im 1
+    3109:	06          	and
+    310a:	55          	storesp 20
+    310b:	51          	storesp 4
+    310c:	52          	storesp 8
+    310d:	53          	storesp 12
+
+0000310e <.LM3>:
+	if (needed)
+    310e:	71          	loadsp 4
+    310f:	80          	im 0
+    3110:	2e          	eq
+    3111:	8c          	im 12
+    3112:	38          	neqbranch
+
+00003113 <.LM4>:
+	{
+		*zpu_pokey_irqen = 0x28;
+    3113:	a8          	im 40
+    3114:	73          	loadsp 12
+    3115:	34          	storeb
+
+00003116 <.LM5>:
+		*zpu_pokey_irqen = 0x38;
+    3116:	80          	im 0
+    3117:	fb          	im -5
+    3118:	ec          	im -20
+    3119:	08          	load
+    311a:	51          	storesp 4
+    311b:	b8          	im 56
+    311c:	71          	loadsp 4
+    311d:	34          	storeb
+
+0000311e <.L2>:
+	}
+	return needed;
+}
+    311e:	71          	loadsp 4
+    311f:	83          	im 3
+    3120:	e0          	im -32
+    3121:	80          	im 0
+    3122:	0c          	store
+    3123:	84          	im 4
+    3124:	3d          	pushspadd
+    3125:	0d          	popsp
+    3126:	04          	poppc
+
+00003127 <USART_Data_Ready>:
+
+int USART_Data_Ready()
+{
+    3127:	fe          	im -2
+    3128:	3d          	pushspadd
+    3129:	0d          	popsp
+
+0000312a <.LM8>:
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+    312a:	80          	im 0
+    312b:	fb          	im -5
+    312c:	ec          	im -20
+    312d:	08          	load
+    312e:	70          	loadsp 0
+    312f:	33          	loadb
+    3130:	70          	loadsp 0
+    3131:	81          	im 1
+    3132:	ff          	im -1
+    3133:	06          	and
+    3134:	70          	loadsp 0
+    3135:	85          	im 5
+    3136:	2a          	lshiftright
+    3137:	81          	im 1
+    3138:	32          	xor
+    3139:	81          	im 1
+    313a:	06          	and
+    313b:	55          	storesp 20
+    313c:	51          	storesp 4
+    313d:	52          	storesp 8
+    313e:	53          	storesp 12
+
+0000313f <.LM9>:
+	if (ready)
+    313f:	71          	loadsp 4
+    3140:	80          	im 0
+    3141:	2e          	eq
+    3142:	8c          	im 12
+    3143:	38          	neqbranch
+
+00003144 <.LM10>:
+	{
+		*zpu_pokey_irqen = 0x18;
+    3144:	98          	im 24
+    3145:	73          	loadsp 12
+    3146:	34          	storeb
+
+00003147 <.LM11>:
+		*zpu_pokey_irqen = 0x38;
+    3147:	80          	im 0
+    3148:	fb          	im -5
+    3149:	ec          	im -20
+    314a:	08          	load
+    314b:	51          	storesp 4
+    314c:	b8          	im 56
+    314d:	71          	loadsp 4
+    314e:	34          	storeb
+
+0000314f <.L5>:
+	}
+	return ready;
+}
+    314f:	71          	loadsp 4
+    3150:	83          	im 3
+    3151:	e0          	im -32
+    3152:	80          	im 0
+    3153:	0c          	store
+    3154:	84          	im 4
+    3155:	3d          	pushspadd
+    3156:	0d          	popsp
+    3157:	04          	poppc
+
+00003158 <USART_Receive_Mode>:
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+    3158:	80          	im 0
+    3159:	3d          	pushspadd
+    315a:	0d          	popsp
+
+0000315b <.LM14>:
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+    315b:	80          	im 0
+    315c:	fb          	im -5
+    315d:	e8          	im -24
+    315e:	08          	load
+    315f:	51          	storesp 4
+    3160:	93          	im 19
+    3161:	71          	loadsp 4
+    3162:	34          	storeb
+
+00003163 <.LM15>:
+	*zpu_pokey_skrest = 0xff;
+    3163:	80          	im 0
+    3164:	fb          	im -5
+    3165:	f4          	im -12
+    3166:	08          	load
+    3167:	51          	storesp 4
+    3168:	ff          	im -1
+    3169:	71          	loadsp 4
+    316a:	34          	storeb
+    316b:	82          	im 2
+    316c:	3d          	pushspadd
+    316d:	0d          	popsp
+    316e:	04          	poppc
+
+0000316f <USART_Init>:
+    316f:	fe          	im -2
+    3170:	3d          	pushspadd
+    3171:	0d          	popsp
+    3172:	02          	pushsp
+    3173:	93          	im 19
+    3174:	05          	add
+    3175:	33          	loadb
+
+00003176 <.LM17>:
+    3176:	80          	im 0
+    3177:	fb          	im -5
+    3178:	e8          	im -24
+    3179:	08          	load
+    317a:	53          	storesp 12
+    317b:	53          	storesp 12
+    317c:	80          	im 0
+    317d:	72          	loadsp 8
+    317e:	34          	storeb
+
+0000317f <.LM18>:
+    317f:	8a          	im 10
+    3180:	51          	storesp 4
+    3181:	ff          	im -1
+    3182:	a6          	im 38
+    3183:	af          	im 47
+    3184:	3f          	callpcrel
+
+00003185 <.LM19>:
+    3185:	d2          	im -46
+    3186:	3f          	callpcrel
+
+00003187 <.LM20>:
+    3187:	80          	im 0
+    3188:	fb          	im -5
+    3189:	f8          	im -8
+    318a:	08          	load
+    318b:	52          	storesp 8
+    318c:	80          	im 0
+    318d:	f8          	im -8
+    318e:	72          	loadsp 8
+    318f:	34          	storeb
+
+00003190 <.LM21>:
+    3190:	80          	im 0
+    3191:	fc          	im -4
+    3192:	90          	im 16
+    3193:	08          	load
+    3194:	52          	storesp 8
+    3195:	80          	im 0
+    3196:	72          	loadsp 8
+    3197:	34          	storeb
+
+00003198 <.LM22>:
+    3198:	fa          	im -6
+    3199:	13          	addsp 12
+    319a:	80          	im 0
+    319b:	fc          	im -4
+    319c:	98          	im 24
+    319d:	08          	load
+    319e:	53          	storesp 12
+    319f:	53          	storesp 12
+    31a0:	72          	loadsp 8
+    31a1:	72          	loadsp 8
+    31a2:	34          	storeb
+
+000031a3 <.LM23>:
+    31a3:	80          	im 0
+    31a4:	fc          	im -4
+    31a5:	80          	im 0
+    31a6:	08          	load
+    31a7:	52          	storesp 8
+    31a8:	80          	im 0
+    31a9:	72          	loadsp 8
+    31aa:	34          	storeb
+
+000031ab <.LM24>:
+    31ab:	80          	im 0
+    31ac:	fc          	im -4
+    31ad:	88          	im 8
+    31ae:	08          	load
+    31af:	52          	storesp 8
+    31b0:	72          	loadsp 8
+    31b1:	72          	loadsp 8
+    31b2:	34          	storeb
+
+000031b3 <.LM25>:
+    31b3:	80          	im 0
+    31b4:	fb          	im -5
+    31b5:	ec          	im -20
+    31b6:	08          	load
+    31b7:	52          	storesp 8
+    31b8:	80          	im 0
+    31b9:	72          	loadsp 8
+    31ba:	34          	storeb
+
+000031bb <.LM26>:
+    31bb:	80          	im 0
+    31bc:	fb          	im -5
+    31bd:	ec          	im -20
+    31be:	08          	load
+    31bf:	52          	storesp 8
+    31c0:	b8          	im 56
+    31c1:	72          	loadsp 8
+    31c2:	34          	storeb
+    31c3:	84          	im 4
+    31c4:	3d          	pushspadd
+    31c5:	0d          	popsp
+    31c6:	04          	poppc
+
+000031c7 <USART_Transmit_Byte>:
+    31c7:	ff          	im -1
+    31c8:	3d          	pushspadd
+    31c9:	0d          	popsp
+    31ca:	02          	pushsp
+    31cb:	8f          	im 15
+    31cc:	05          	add
+    31cd:	33          	loadb
+
+000031ce <.LM28>:
+    31ce:	80          	im 0
+    31cf:	fb          	im -5
+    31d0:	f0          	im -16
+    31d1:	08          	load
+    31d2:	52          	storesp 8
+    31d3:	52          	storesp 8
+    31d4:	71          	loadsp 4
+    31d5:	71          	loadsp 4
+    31d6:	34          	storeb
+
+000031d7 <.L10>:
+    31d7:	fe          	im -2
+    31d8:	9d          	im 29
+    31d9:	3f          	callpcrel
+    31da:	83          	im 3
+    31db:	e0          	im -32
+    31dc:	80          	im 0
+    31dd:	08          	load
+    31de:	80          	im 0
+    31df:	2e          	eq
+    31e0:	f6          	im -10
+    31e1:	38          	neqbranch
+    31e2:	83          	im 3
+    31e3:	3d          	pushspadd
+    31e4:	0d          	popsp
+    31e5:	04          	poppc
+
+000031e6 <USART_Receive_Byte>:
+    31e6:	80          	im 0
+    31e7:	3d          	pushspadd
+    31e8:	0d          	popsp
+
+000031e9 <.LM31>:
+    31e9:	fe          	im -2
+    31ea:	bc          	im 60
+    31eb:	3f          	callpcrel
+    31ec:	83          	im 3
+    31ed:	e0          	im -32
+    31ee:	80          	im 0
+    31ef:	08          	load
+    31f0:	90          	im 16
+    31f1:	38          	neqbranch
+
+000031f2 <.L16>:
+    31f2:	ff          	im -1
+    31f3:	b6          	im 54
+    31f4:	e4          	im -28
+    31f5:	3f          	callpcrel
+    31f6:	fe          	im -2
+    31f7:	af          	im 47
+    31f8:	3f          	callpcrel
+    31f9:	83          	im 3
+    31fa:	e0          	im -32
+    31fb:	80          	im 0
+    31fc:	08          	load
+    31fd:	80          	im 0
+    31fe:	2e          	eq
+    31ff:	f2          	im -14
+    3200:	38          	neqbranch
+
+00003201 <.L18>:
+    3201:	80          	im 0
+    3202:	fb          	im -5
+    3203:	f0          	im -16
+    3204:	08          	load
+    3205:	70          	loadsp 0
+    3206:	33          	loadb
+    3207:	70          	loadsp 0
+    3208:	81          	im 1
+    3209:	ff          	im -1
+    320a:	06          	and
+    320b:	83          	im 3
+    320c:	e0          	im -32
+    320d:	80          	im 0
+    320e:	0c          	store
+    320f:	51          	storesp 4
+    3210:	51          	storesp 4
+
+00003211 <.LM33>:
+    3211:	82          	im 2
+    3212:	3d          	pushspadd
+    3213:	0d          	popsp
+    3214:	04          	poppc
+
+00003215 <USART_Transmit_Mode>:
+    3215:	80          	im 0
+    3216:	3d          	pushspadd
+    3217:	0d          	popsp
+
+00003218 <.LM35>:
+    3218:	80          	im 0
+    3219:	fb          	im -5
+    321a:	e8          	im -24
+    321b:	08          	load
+    321c:	51          	storesp 4
+    321d:	a3          	im 35
+    321e:	71          	loadsp 4
+    321f:	34          	storeb
+
+00003220 <.LM36>:
+    3220:	80          	im 0
+    3221:	fb          	im -5
+    3222:	f4          	im -12
+    3223:	08          	load
+    3224:	51          	storesp 4
+    3225:	ff          	im -1
+    3226:	71          	loadsp 4
+    3227:	34          	storeb
+
+00003228 <.LM37>:
+    3228:	80          	im 0
+    3229:	fb          	im -5
+    322a:	ec          	im -20
+    322b:	08          	load
+    322c:	51          	storesp 4
+    322d:	a8          	im 40
+    322e:	71          	loadsp 4
+    322f:	34          	storeb
+
+00003230 <.LM38>:
+    3230:	80          	im 0
+    3231:	fb          	im -5
+    3232:	ec          	im -20
+    3233:	08          	load
+    3234:	51          	storesp 4
+    3235:	b8          	im 56
+    3236:	71          	loadsp 4
+    3237:	34          	storeb
+    3238:	82          	im 2
+    3239:	3d          	pushspadd
+    323a:	0d          	popsp
+    323b:	04          	poppc
+
+0000323c <USART_Framing_Error>:
+}
+
+int USART_Framing_Error()
+{
+    323c:	80          	im 0
+    323d:	3d          	pushspadd
+    323e:	0d          	popsp
+
+0000323f <.LM40>:
+	if (0xc0&(*zpu_pokey_skctl))
+    323f:	80          	im 0
+    3240:	fb          	im -5
+    3241:	e8          	im -24
+    3242:	08          	load
+    3243:	70          	loadsp 0
+    3244:	33          	loadb
+    3245:	70          	loadsp 0
+    3246:	81          	im 1
+    3247:	c0          	im -64
+    3248:	06          	and
+
+00003249 <.LM41>:
+	{
+		return 0;
+    3249:	70          	loadsp 0
+    324a:	30          	neg
+
+0000324b <.LM42>:
+	}
+	else
+	{
+		return 1;
+	}
+}
+    324b:	70          	loadsp 0
+    324c:	80          	im 0
+    324d:	25          	lessthanorequal
+    324e:	83          	im 3
+    324f:	e0          	im -32
+    3250:	80          	im 0
+    3251:	0c          	store
+    3252:	51          	storesp 4
+    3253:	51          	storesp 4
+    3254:	51          	storesp 4
+    3255:	51          	storesp 4
+    3256:	82          	im 2
+    3257:	3d          	pushspadd
+    3258:	0d          	popsp
+    3259:	04          	poppc
+
+0000325a <USART_Wait_Transmit_Complete>:
+
+void USART_Wait_Transmit_Complete()
+{
+    325a:	ff          	im -1
+    325b:	3d          	pushspadd
+    325c:	0d          	popsp
+    325d:	80          	im 0
+    325e:	fb          	im -5
+    325f:	ec          	im -20
+    3260:	08          	load
+    3261:	52          	storesp 8
+
+00003262 <.L24>:
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+    3262:	71          	loadsp 4
+    3263:	33          	loadb
+    3264:	70          	loadsp 0
+    3265:	81          	im 1
+    3266:	ff          	im -1
+    3267:	06          	and
+    3268:	70          	loadsp 0
+    3269:	83          	im 3
+    326a:	2a          	lshiftright
+    326b:	81          	im 1
+    326c:	32          	xor
+    326d:	70          	loadsp 0
+    326e:	81          	im 1
+    326f:	06          	and
+    3270:	51          	storesp 4
+    3271:	51          	storesp 4
+    3272:	51          	storesp 4
+    3273:	51          	storesp 4
+
+00003274 <.LM45>:
+		if (ready)
+    3274:	70          	loadsp 0
+    3275:	80          	im 0
+    3276:	2e          	eq
+    3277:	ea          	im -22
+    3278:	38          	neqbranch
+
+00003279 <.LM46>:
+		{
+			*zpu_pokey_irqen = 0x30;
+    3279:	b0          	im 48
+    327a:	72          	loadsp 8
+    327b:	34          	storeb
+
+0000327c <.LM47>:
+			*zpu_pokey_irqen = 0x38;
+    327c:	80          	im 0
+    327d:	fb          	im -5
+    327e:	ec          	im -20
+    327f:	08          	load
+    3280:	51          	storesp 4
+    3281:	b8          	im 56
+    3282:	71          	loadsp 4
+    3283:	34          	storeb
+
+00003284 <.LBE2>:
+    3284:	83          	im 3
+    3285:	3d          	pushspadd
+    3286:	0d          	popsp
+    3287:	04          	poppc
+
+00003288 <set_green_led>:
+
+#include "regs.h"
+
+void set_green_led(int i)
+{
+    3288:	80          	im 0
+    3289:	3d          	pushspadd
+    328a:	0d          	popsp
+
+0000328b <.LM2>:
+	*zpu_ledg = i;
+    328b:	80          	im 0
+    328c:	fc          	im -4
+    328d:	b4          	im 52
+    328e:	08          	load
+    328f:	73          	loadsp 12
+    3290:	71          	loadsp 4
+    3291:	0c          	store
+    3292:	51          	storesp 4
+    3293:	82          	im 2
+    3294:	3d          	pushspadd
+    3295:	0d          	popsp
+    3296:	04          	poppc
+
+00003297 <set_red_led>:
+}
+void set_red_led(int i)
+{
+    3297:	80          	im 0
+    3298:	3d          	pushspadd
+    3299:	0d          	popsp
+
+0000329a <.LM4>:
+	*zpu_ledr = i;
+    329a:	80          	im 0
+    329b:	fc          	im -4
+    329c:	b0          	im 48
+    329d:	08          	load
+    329e:	73          	loadsp 12
+    329f:	71          	loadsp 4
+    32a0:	0c          	store
+    32a1:	51          	storesp 4
+    32a2:	82          	im 2
+    32a3:	3d          	pushspadd
+    32a4:	0d          	popsp
+    32a5:	04          	poppc
+
+000032a6 <set_drive_number>:
+}
+void set_drive_number(int i)
+{
+    32a6:	80          	im 0
+    32a7:	3d          	pushspadd
+    32a8:	0d          	popsp
+
+000032a9 <.LM6>:
+	*zpu_hex = i;
+    32a9:	80          	im 0
+    32aa:	fc          	im -4
+    32ab:	9c          	im 28
+    32ac:	08          	load
+    32ad:	73          	loadsp 12
+    32ae:	71          	loadsp 4
+    32af:	0c          	store
+    32b0:	51          	storesp 4
+    32b1:	82          	im 2
+    32b2:	3d          	pushspadd
+    32b3:	0d          	popsp
+    32b4:	04          	poppc
+
+000032b5 <init_display>:
+}
+void init_display()
+{
+    32b5:	80          	im 0
+    32b6:	3d          	pushspadd
+    32b7:	0d          	popsp
+
+000032b8 <.LM8>:
+	*zpu_hex = 0;
+    32b8:	80          	im 0
+    32b9:	fc          	im -4
+    32ba:	9c          	im 28
+    32bb:	08          	load
+    32bc:	51          	storesp 4
+    32bd:	80          	im 0
+    32be:	71          	loadsp 4
+    32bf:	0c          	store
+    32c0:	82          	im 2
+    32c1:	3d          	pushspadd
+    32c2:	0d          	popsp
+    32c3:	04          	poppc
+
+000032c4 <topofscreen>:
+int debugoffsetval;
+
+void topofscreen()
+{
+	xpos = 0;
+    32c4:	80          	im 0
+    32c5:	0b          	nop
+    32c6:	83          	im 3
+    32c7:	e7          	im -25
+    32c8:	f4          	im -12
+    32c9:	0c          	store
+
+000032ca <.LM3>:
+	ypos = 0;
+    32ca:	80          	im 0
+    32cb:	0b          	nop
+    32cc:	83          	im 3
+    32cd:	e8          	im -24
+    32ce:	80          	im 0
+    32cf:	0c          	store
+    32d0:	04          	poppc
+
+000032d1 <setxpos>:
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+    32d1:	71          	loadsp 4
+    32d2:	83          	im 3
+    32d3:	e7          	im -25
+    32d4:	f4          	im -12
+    32d5:	0c          	store
+    32d6:	04          	poppc
+
+000032d7 <setypos>:
+}
+
+void setypos(int val)
+{
+	ypos = val;
+    32d7:	71          	loadsp 4
+    32d8:	83          	im 3
+    32d9:	e8          	im -24
+    32da:	80          	im 0
+    32db:	0c          	store
+    32dc:	04          	poppc
+
+000032dd <initdebug>:
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+    32dd:	80          	im 0
+    32de:	0b          	nop
+    32df:	83          	im 3
+    32e0:	e7          	im -25
+    32e1:	f4          	im -12
+    32e2:	0c          	store
+
+000032e3 <.LM10>:
+	ypos = 0;
+    32e3:	80          	im 0
+    32e4:	0b          	nop
+    32e5:	83          	im 3
+    32e6:	e8          	im -24
+    32e7:	80          	im 0
+    32e8:	0c          	store
+
+000032e9 <.LM11>:
+	onoff = onoff_in;
+    32e9:	71          	loadsp 4
+    32ea:	83          	im 3
+    32eb:	e7          	im -25
+    32ec:	fc          	im -4
+    32ed:	0c          	store
+    32ee:	04          	poppc
+
+000032ef <plot>:
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+    32ef:	ff          	im -1
+    32f0:	3d          	pushspadd
+    32f1:	0d          	popsp
+    32f2:	75          	loadsp 20
+    32f3:	02          	pushsp
+    32f4:	84          	im 4
+    32f5:	05          	add
+    32f6:	8f          	im 15
+    32f7:	05          	add
+    32f8:	33          	loadb
+    32f9:	53          	storesp 12
+    32fa:	51          	storesp 4
+
+000032fb <.LM13>:
+	if (onoff == 0) return;
+    32fb:	83          	im 3
+    32fc:	e7          	im -25
+    32fd:	fc          	im -4
+    32fe:	08          	load
+    32ff:	80          	im 0
+    3300:	2e          	eq
+    3301:	9a          	im 26
+    3302:	38          	neqbranch
+
+00003303 <.LM14>:
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val+debugoffsetval;
+    3303:	70          	loadsp 0
+    3304:	10          	addsp 0
+    3305:	10          	addsp 0
+    3306:	11          	addsp 4
+    3307:	70          	loadsp 0
+    3308:	10          	addsp 0
+    3309:	10          	addsp 0
+    330a:	10          	addsp 0
+    330b:	16          	addsp 24
+    330c:	86          	im 6
+    330d:	b8          	im 56
+    330e:	c0          	im -64
+    330f:	11          	addsp 4
+    3310:	83          	im 3
+    3311:	e7          	im -25
+    3312:	f8          	im -8
+    3313:	08          	load
+    3314:	15          	addsp 20
+    3315:	55          	storesp 20
+    3316:	51          	storesp 4
+    3317:	51          	storesp 4
+    3318:	51          	storesp 4
+    3319:	71          	loadsp 4
+    331a:	71          	loadsp 4
+    331b:	34          	storeb
+
+0000331c <.L5>:
+}
+    331c:	83          	im 3
+    331d:	3d          	pushspadd
+    331e:	0d          	popsp
+    331f:	04          	poppc
+
+00003320 <nextline>:
+    3320:	fd          	im -3
+    3321:	3d          	pushspadd
+    3322:	0d          	popsp
+
+00003323 <.LM17>:
+    3323:	80          	im 0
+    3324:	0b          	nop
+    3325:	83          	im 3
+    3326:	e7          	im -25
+    3327:	f4          	im -12
+    3328:	0c          	store
+
+00003329 <.LM18>:
+    3329:	83          	im 3
+    332a:	e8          	im -24
+    332b:	80          	im 0
+    332c:	08          	load
+    332d:	81          	im 1
+    332e:	05          	add
+    332f:	54          	storesp 16
+
+00003330 <.LM19>:
+    3330:	73          	loadsp 12
+    3331:	98          	im 24
+    3332:	2e          	eq
+    3333:	a3          	im 35
+    3334:	38          	neqbranch
+    3335:	73          	loadsp 12
+    3336:	83          	im 3
+    3337:	e8          	im -24
+    3338:	80          	im 0
+    3339:	0c          	store
+
+0000333a <.LM20>:
+    333a:	80          	im 0
+    333b:	54          	storesp 16
+
+0000333c <.L13>:
+    333c:	83          	im 3
+    333d:	e8          	im -24
+    333e:	80          	im 0
+    333f:	08          	load
+    3340:	53          	storesp 12
+    3341:	73          	loadsp 12
+    3342:	52          	storesp 8
+    3343:	80          	im 0
+    3344:	51          	storesp 4
+    3345:	ff          	im -1
+    3346:	a8          	im 40
+    3347:	3f          	callpcrel
+
+00003348 <.LM22>:
+    3348:	81          	im 1
+    3349:	14          	addsp 16
+    334a:	54          	storesp 16
+    334b:	73          	loadsp 12
+    334c:	a8          	im 40
+    334d:	2e          	eq
+    334e:	09          	not
+    334f:	81          	im 1
+    3350:	06          	and
+    3351:	ea          	im -22
+    3352:	38          	neqbranch
+    3353:	85          	im 5
+    3354:	3d          	pushspadd
+    3355:	0d          	popsp
+    3356:	04          	poppc
+
+00003357 <.L18>:
+    3357:	80          	im 0
+    3358:	0b          	nop
+    3359:	83          	im 3
+    335a:	e8          	im -24
+    335b:	80          	im 0
+    335c:	0c          	store
+
+0000335d <.LM24>:
+    335d:	80          	im 0
+    335e:	54          	storesp 16
+    335f:	dc          	im -36
+    3360:	39          	poppcrel
+
+00003361 <toatarichar>:
+    3361:	fe          	im -2
+    3362:	3d          	pushspadd
+    3363:	0d          	popsp
+    3364:	74          	loadsp 16
+    3365:	52          	storesp 8
+
+00003366 <.LM26>:
+    3366:	80          	im 0
+    3367:	53          	storesp 12
+    3368:	80          	im 0
+    3369:	ff          	im -1
+    336a:	72          	loadsp 8
+    336b:	25          	lessthanorequal
+    336c:	88          	im 8
+    336d:	38          	neqbranch
+    336e:	81          	im 1
+
+0000336f <.LM27>:
+    336f:	0b          	nop
+    3370:	ff          	im -1
+    3371:	80          	im 0
+    3372:	13          	addsp 12
+    3373:	53          	storesp 12
+    3374:	53          	storesp 12
+
+00003375 <.L21>:
+    3375:	ff          	im -1
+    3376:	bf          	im 63
+    3377:	12          	addsp 8
+    3378:	51          	storesp 4
+    3379:	99          	im 25
+    337a:	71          	loadsp 4
+    337b:	27          	ulessthanorequal
+    337c:	a7          	im 39
+    337d:	38          	neqbranch
+
+0000337e <.LM29>:
+    337e:	ff          	im -1
+    337f:	9f          	im 31
+    3380:	12          	addsp 8
+    3381:	51          	storesp 4
+    3382:	70          	loadsp 0
+    3383:	99          	im 25
+    3384:	26          	ulessthan
+    3385:	96          	im 22
+    3386:	38          	neqbranch
+
+00003387 <.L23>:
+    3387:	72          	loadsp 8
+    3388:	80          	im 0
+    3389:	2e          	eq
+    338a:	85          	im 5
+    338b:	38          	neqbranch
+
+0000338c <.LM31>:
+    338c:	81          	im 1
+    338d:	80          	im 0
+    338e:	12          	addsp 8
+    338f:	52          	storesp 8
+
+00003390 <.L30>:
+    3390:	71          	loadsp 4
+    3391:	81          	im 1
+    3392:	ff          	im -1
+    3393:	06          	and
+    3394:	83          	im 3
+    3395:	e0          	im -32
+    3396:	80          	im 0
+    3397:	0c          	store
+
+00003398 <.LM33>:
+    3398:	84          	im 4
+    3399:	3d          	pushspadd
+    339a:	0d          	popsp
+    339b:	04          	poppc
+
+0000339c <.L34>:
+    339c:	d0          	im -48
+    339d:	12          	addsp 8
+    339e:	51          	storesp 4
+    339f:	70          	loadsp 0
+    33a0:	89          	im 9
+    33a1:	26          	ulessthan
+    33a2:	86          	im 6
+    33a3:	38          	neqbranch
+
+000033a4 <.L32>:
+    33a4:	e0          	im -32
+    33a5:	12          	addsp 8
+    33a6:	52          	storesp 8
+    33a7:	df          	im -33
+    33a8:	39          	poppcrel
+
+000033a9 <.L26>:
+    33a9:	e0          	im -32
+    33aa:	12          	addsp 8
+
+000033ab <.LM37>:
+    33ab:	70          	loadsp 0
+    33ac:	53          	storesp 12
+    33ad:	51          	storesp 4
+
+000033ae <.LM38>:
+    33ae:	8f          	im 15
+    33af:	71          	loadsp 4
+    33b0:	27          	ulessthanorequal
+    33b1:	d5          	im -43
+    33b2:	38          	neqbranch
+
+000033b3 <.LM39>:
+    33b3:	80          	im 0
+    33b4:	52          	storesp 8
+    33b5:	d1          	im -47
+    33b6:	39          	poppcrel
+
+000033b7 <hextoatarichar>:
+    33b7:	ff          	im -1
+    33b8:	3d          	pushspadd
+    33b9:	0d          	popsp
+    33ba:	73          	loadsp 12
+    33bb:	52          	storesp 8
+
+000033bc <.LM41>:
+    33bc:	71          	loadsp 4
+    33bd:	89          	im 9
+    33be:	26          	ulessthan
+    33bf:	90          	im 16
+    33c0:	38          	neqbranch
+
+000033c1 <.LM42>:
+    33c1:	90          	im 16
+    33c2:	12          	addsp 8
+    33c3:	52          	storesp 8
+
+000033c4 <.L37>:
+    33c4:	71          	loadsp 4
+    33c5:	81          	im 1
+    33c6:	ff          	im -1
+    33c7:	06          	and
+    33c8:	83          	im 3
+    33c9:	e0          	im -32
+    33ca:	80          	im 0
+    33cb:	0c          	store
+
+000033cc <.LM44>:
+    33cc:	83          	im 3
+    33cd:	3d          	pushspadd
+    33ce:	0d          	popsp
+    33cf:	04          	poppc
+
+000033d0 <.L36>:
+    33d0:	f6          	im -10
+    33d1:	12          	addsp 8
+    33d2:	51          	storesp 4
+    33d3:	70          	loadsp 0
+    33d4:	85          	im 5
+    33d5:	26          	ulessthan
+    33d6:	ed          	im -19
+    33d7:	38          	neqbranch
+
+000033d8 <.LM46>:
+    33d8:	97          	im 23
+    33d9:	12          	addsp 8
+
+000033da <.LM47>:
+    33da:	70          	loadsp 0
+    33db:	81          	im 1
+    33dc:	ff          	im -1
+    33dd:	06          	and
+    33de:	83          	im 3
+    33df:	e0          	im -32
+    33e0:	80          	im 0
+    33e1:	0c          	store
+    33e2:	52          	storesp 8
+
+000033e3 <.LM48>:
+    33e3:	83          	im 3
+    33e4:	3d          	pushspadd
+    33e5:	0d          	popsp
+    33e6:	04          	poppc
+
+000033e7 <debugoffset>:
+void debugoffset(int x)
+{
+	debugoffsetval = x;
+    33e7:	71          	loadsp 4
+    33e8:	83          	im 3
+    33e9:	e7          	im -25
+    33ea:	f8          	im -8
+    33eb:	0c          	store
+    33ec:	04          	poppc
+
+000033ed <debug>:
+}
+void debug(char const * str)
+{
+    33ed:	fc          	im -4
+    33ee:	3d          	pushspadd
+    33ef:	0d          	popsp
+    33f0:	76          	loadsp 24
+    33f1:	55          	storesp 20
+
+000033f2 <.L51>:
+	while (1)
+	{
+		int val = *str++;
+    33f2:	74          	loadsp 16
+    33f3:	70          	loadsp 0
+    33f4:	81          	im 1
+    33f5:	05          	add
+    33f6:	56          	storesp 24
+    33f7:	33          	loadb
+    33f8:	54          	storesp 16
+
+000033f9 <.LM53>:
+		if (val==0) break;
+    33f9:	73          	loadsp 12
+    33fa:	80          	im 0
+    33fb:	2e          	eq
+    33fc:	80          	im 0
+    33fd:	c2          	im -62
+    33fe:	38          	neqbranch
+
+000033ff <.L53>:
+		if (val=='\n') {nextline();continue;};
+    33ff:	73          	loadsp 12
+    3400:	8a          	im 10
+    3401:	2e          	eq
+    3402:	b0          	im 48
+    3403:	38          	neqbranch
+
+00003404 <.LM55>:
+
+		plot(toatarichar(val),xpos,ypos);
+    3404:	73          	loadsp 12
+    3405:	51          	storesp 4
+    3406:	fe          	im -2
+    3407:	d9          	im -39
+    3408:	3f          	callpcrel
+    3409:	83          	im 3
+    340a:	e8          	im -24
+    340b:	80          	im 0
+    340c:	08          	load
+    340d:	53          	storesp 12
+    340e:	83          	im 3
+    340f:	e7          	im -25
+    3410:	f4          	im -12
+    3411:	08          	load
+    3412:	52          	storesp 8
+    3413:	83          	im 3
+    3414:	e0          	im -32
+    3415:	80          	im 0
+    3416:	08          	load
+    3417:	81          	im 1
+    3418:	ff          	im -1
+    3419:	06          	and
+    341a:	51          	storesp 4
+    341b:	fd          	im -3
+    341c:	d2          	im -46
+    341d:	3f          	callpcrel
+
+0000341e <.LM56>:
+		++xpos;
+    341e:	83          	im 3
+    341f:	e7          	im -25
+    3420:	f4          	im -12
+    3421:	08          	load
+    3422:	81          	im 1
+    3423:	05          	add
+    3424:	83          	im 3
+    3425:	e7          	im -25
+    3426:	f4          	im -12
+    3427:	0c          	store
+
+00003428 <.LM57>:
+		if (xpos==40)
+    3428:	83          	im 3
+    3429:	e7          	im -25
+    342a:	f4          	im -12
+    342b:	08          	load
+    342c:	a8          	im 40
+    342d:	2e          	eq
+    342e:	09          	not
+    342f:	81          	im 1
+    3430:	06          	and
+    3431:	c0          	im -64
+    3432:	38          	neqbranch
+
+00003433 <.L50>:
+		{
+			nextline();
+    3433:	fd          	im -3
+    3434:	eb          	im -21
+    3435:	3f          	callpcrel
+
+00003436 <.LM59>:
+    3436:	74          	loadsp 16
+    3437:	70          	loadsp 0
+    3438:	81          	im 1
+    3439:	05          	add
+    343a:	56          	storesp 24
+    343b:	33          	loadb
+    343c:	54          	storesp 16
+
+0000343d <.LM60>:
+    343d:	73          	loadsp 12
+    343e:	c0          	im -64
+    343f:	38          	neqbranch
+
+00003440 <.L43>:
+		}
+	}
+	debugoffsetval = 0;
+    3440:	80          	im 0
+    3441:	0b          	nop
+    3442:	83          	im 3
+    3443:	e7          	im -25
+    3444:	f8          	im -8
+    3445:	0c          	store
+    3446:	86          	im 6
+    3447:	3d          	pushspadd
+    3448:	0d          	popsp
+    3449:	04          	poppc
+
+0000344a <plotnext>:
+}
+
+void plotnext(unsigned char val)
+{
+    344a:	fd          	im -3
+    344b:	3d          	pushspadd
+    344c:	0d          	popsp
+    344d:	02          	pushsp
+    344e:	97          	im 23
+    344f:	05          	add
+    3450:	33          	loadb
+
+00003451 <.LM63>:
+	plot(val,xpos,ypos);
+    3451:	83          	im 3
+    3452:	e8          	im -24
+    3453:	80          	im 0
+    3454:	08          	load
+    3455:	54          	storesp 16
+    3456:	83          	im 3
+    3457:	e7          	im -25
+    3458:	f4          	im -12
+    3459:	08          	load
+    345a:	53          	storesp 12
+    345b:	51          	storesp 4
+    345c:	fd          	im -3
+    345d:	91          	im 17
+    345e:	3f          	callpcrel
+
+0000345f <.LM64>:
+
+	++xpos;
+    345f:	83          	im 3
+    3460:	e7          	im -25
+    3461:	f4          	im -12
+    3462:	08          	load
+    3463:	81          	im 1
+    3464:	05          	add
+    3465:	83          	im 3
+    3466:	e7          	im -25
+    3467:	f4          	im -12
+    3468:	0c          	store
+
+00003469 <.LM65>:
+	if (xpos==40) nextline();
+    3469:	83          	im 3
+    346a:	e7          	im -25
+    346b:	f4          	im -12
+    346c:	08          	load
+    346d:	a8          	im 40
+    346e:	2e          	eq
+    346f:	85          	im 5
+    3470:	38          	neqbranch
+
+00003471 <.LM66>:
+}
+    3471:	85          	im 5
+    3472:	3d          	pushspadd
+    3473:	0d          	popsp
+    3474:	04          	poppc
+
+00003475 <.L57>:
+    3475:	fd          	im -3
+    3476:	a9          	im 41
+    3477:	3f          	callpcrel
+
+00003478 <.LM68>:
+    3478:	85          	im 5
+    3479:	3d          	pushspadd
+    347a:	0d          	popsp
+    347b:	04          	poppc
+
+0000347c <plotnextnumber>:
+
+void plotnextnumber(unsigned short val)
+{
+    347c:	fe          	im -2
+    347d:	3d          	pushspadd
+    347e:	0d          	popsp
+    347f:	02          	pushsp
+    3480:	92          	im 18
+    3481:	05          	add
+    3482:	22          	loadh
+
+00003483 <.LM70>:
+	plotnext(hextoatarichar((val&0xf000)>>12));
+    3483:	70          	loadsp 0
+    3484:	8c          	im 12
+    3485:	2a          	lshiftright
+    3486:	52          	storesp 8
+    3487:	52          	storesp 8
+    3488:	fe          	im -2
+    3489:	ad          	im 45
+    348a:	3f          	callpcrel
+    348b:	83          	im 3
+    348c:	e0          	im -32
+    348d:	80          	im 0
+    348e:	08          	load
+    348f:	81          	im 1
+    3490:	ff          	im -1
+    3491:	06          	and
+    3492:	51          	storesp 4
+    3493:	ff          	im -1
+    3494:	b5          	im 53
+    3495:	3f          	callpcrel
+
+00003496 <.LM71>:
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+    3496:	71          	loadsp 4
+    3497:	9e          	im 30
+    3498:	80          	im 0
+    3499:	06          	and
+    349a:	70          	loadsp 0
+    349b:	88          	im 8
+    349c:	2a          	lshiftright
+    349d:	52          	storesp 8
+    349e:	53          	storesp 12
+    349f:	fe          	im -2
+    34a0:	96          	im 22
+    34a1:	3f          	callpcrel
+    34a2:	83          	im 3
+    34a3:	e0          	im -32
+    34a4:	80          	im 0
+    34a5:	08          	load
+    34a6:	81          	im 1
+    34a7:	ff          	im -1
+    34a8:	06          	and
+    34a9:	51          	storesp 4
+    34aa:	ff          	im -1
+    34ab:	9e          	im 30
+    34ac:	3f          	callpcrel
+
+000034ad <.LM72>:
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+    34ad:	71          	loadsp 4
+    34ae:	81          	im 1
+    34af:	f0          	im -16
+    34b0:	06          	and
+    34b1:	70          	loadsp 0
+    34b2:	84          	im 4
+    34b3:	2a          	lshiftright
+    34b4:	52          	storesp 8
+    34b5:	53          	storesp 12
+    34b6:	fd          	im -3
+    34b7:	ff          	im -1
+    34b8:	3f          	callpcrel
+    34b9:	83          	im 3
+    34ba:	e0          	im -32
+    34bb:	80          	im 0
+    34bc:	08          	load
+    34bd:	81          	im 1
+    34be:	ff          	im -1
+    34bf:	06          	and
+    34c0:	51          	storesp 4
+    34c1:	ff          	im -1
+    34c2:	87          	im 7
+    34c3:	3f          	callpcrel
+
+000034c4 <.LM73>:
+	plotnext(hextoatarichar((val&0x000f)>>0));
+    34c4:	71          	loadsp 4
+    34c5:	8f          	im 15
+    34c6:	06          	and
+    34c7:	51          	storesp 4
+    34c8:	fd          	im -3
+    34c9:	ed          	im -19
+    34ca:	3f          	callpcrel
+    34cb:	83          	im 3
+    34cc:	e0          	im -32
+    34cd:	80          	im 0
+    34ce:	08          	load
+    34cf:	81          	im 1
+    34d0:	ff          	im -1
+    34d1:	06          	and
+    34d2:	51          	storesp 4
+    34d3:	fe          	im -2
+    34d4:	f5          	im -11
+    34d5:	3f          	callpcrel
+
+000034d6 <.LM74>:
+	debugoffsetval = 0;
+    34d6:	80          	im 0
+    34d7:	0b          	nop
+    34d8:	83          	im 3
+    34d9:	e7          	im -25
+    34da:	f8          	im -8
+    34db:	0c          	store
+    34dc:	84          	im 4
+    34dd:	3d          	pushspadd
+    34de:	0d          	popsp
+    34df:	04          	poppc
+
+000034e0 <hexdump>:
+}
+
+void hexdump(char const * str, int length)
+{
+    34e0:	fb          	im -5
+    34e1:	3d          	pushspadd
+    34e2:	0d          	popsp
+    34e3:	77          	loadsp 28
+    34e4:	79          	loadsp 36
+    34e5:	56          	storesp 24
+    34e6:	56          	storesp 24
+
+000034e7 <.LM76>:
+	nextline();
+    34e7:	fc          	im -4
+    34e8:	b7          	im 55
+    34e9:	3f          	callpcrel
+
+000034ea <.LM77>:
+
+	for (;length>0;--length)
+    34ea:	80          	im 0
+    34eb:	75          	loadsp 20
+    34ec:	25          	lessthanorequal
+    34ed:	80          	im 0
+    34ee:	fb          	im -5
+    34ef:	38          	neqbranch
+
+000034f0 <.L70>:
+	{
+		unsigned char val= *str++;
+    34f0:	75          	loadsp 20
+    34f1:	70          	loadsp 0
+    34f2:	81          	im 1
+    34f3:	05          	add
+    34f4:	57          	storesp 28
+    34f5:	33          	loadb
+
+000034f6 <.LM79>:
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+    34f6:	70          	loadsp 0
+    34f7:	52          	storesp 8
+    34f8:	54          	storesp 16
+    34f9:	fc          	im -4
+    34fa:	e6          	im -26
+    34fb:	3f          	callpcrel
+    34fc:	83          	im 3
+    34fd:	e8          	im -24
+    34fe:	80          	im 0
+    34ff:	08          	load
+    3500:	53          	storesp 12
+    3501:	83          	im 3
+    3502:	e7          	im -25
+    3503:	f4          	im -12
+    3504:	08          	load
+    3505:	52          	storesp 8
+    3506:	83          	im 3
+    3507:	e0          	im -32
+    3508:	80          	im 0
+    3509:	08          	load
+    350a:	81          	im 1
+    350b:	ff          	im -1
+    350c:	06          	and
+    350d:	51          	storesp 4
+    350e:	fb          	im -5
+    350f:	df          	im -33
+    3510:	3f          	callpcrel
+
+00003511 <.LM80>:
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+    3511:	73          	loadsp 12
+    3512:	84          	im 4
+    3513:	2a          	lshiftright
+    3514:	51          	storesp 4
+    3515:	fd          	im -3
+    3516:	a0          	im 32
+    3517:	3f          	callpcrel
+    3518:	83          	im 3
+    3519:	e8          	im -24
+    351a:	80          	im 0
+    351b:	08          	load
+    351c:	53          	storesp 12
+    351d:	83          	im 3
+    351e:	e7          	im -25
+    351f:	f4          	im -12
+    3520:	08          	load
+    3521:	10          	addsp 0
+    3522:	94          	im 20
+    3523:	05          	add
+    3524:	52          	storesp 8
+    3525:	83          	im 3
+    3526:	e0          	im -32
+    3527:	80          	im 0
+    3528:	08          	load
+    3529:	81          	im 1
+    352a:	ff          	im -1
+    352b:	06          	and
+    352c:	51          	storesp 4
+    352d:	fb          	im -5
+    352e:	c0          	im -64
+    352f:	3f          	callpcrel
+
+00003530 <.LM81>:
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+    3530:	73          	loadsp 12
+    3531:	8f          	im 15
+    3532:	06          	and
+    3533:	51          	storesp 4
+    3534:	fd          	im -3
+    3535:	81          	im 1
+    3536:	3f          	callpcrel
+    3537:	83          	im 3
+    3538:	e8          	im -24
+    3539:	80          	im 0
+    353a:	08          	load
+    353b:	53          	storesp 12
+    353c:	83          	im 3
+    353d:	e7          	im -25
+    353e:	f4          	im -12
+    353f:	08          	load
+    3540:	10          	addsp 0
+    3541:	95          	im 21
+    3542:	05          	add
+    3543:	52          	storesp 8
+    3544:	83          	im 3
+    3545:	e0          	im -32
+    3546:	80          	im 0
+    3547:	08          	load
+    3548:	81          	im 1
+    3549:	ff          	im -1
+    354a:	06          	and
+    354b:	51          	storesp 4
+    354c:	fb          	im -5
+    354d:	a1          	im 33
+    354e:	3f          	callpcrel
+
+0000354f <.LM82>:
+
+		++xpos;
+    354f:	83          	im 3
+    3550:	e7          	im -25
+    3551:	f4          	im -12
+    3552:	08          	load
+    3553:	81          	im 1
+    3554:	05          	add
+    3555:	83          	im 3
+    3556:	e7          	im -25
+    3557:	f4          	im -12
+    3558:	0c          	store
+
+00003559 <.LM83>:
+		if (xpos==10)
+    3559:	83          	im 3
+    355a:	e7          	im -25
+    355b:	f4          	im -12
+    355c:	08          	load
+    355d:	8a          	im 10
+    355e:	2e          	eq
+    355f:	91          	im 17
+    3560:	38          	neqbranch
+
+00003561 <.LM84>:
+    3561:	ff          	im -1
+    3562:	15          	addsp 20
+    3563:	55          	storesp 20
+
+00003564 <.L71>:
+    3564:	74          	loadsp 16
+    3565:	80          	im 0
+    3566:	24          	lessthan
+    3567:	ff          	im -1
+    3568:	87          	im 7
+    3569:	38          	neqbranch
+
+0000356a <.L66>:
+		{
+			nextline();
+		}
+	}
+	nextline();
+    356a:	fb          	im -5
+    356b:	b4          	im 52
+    356c:	3f          	callpcrel
+    356d:	87          	im 7
+    356e:	3d          	pushspadd
+    356f:	0d          	popsp
+    3570:	04          	poppc
+
+00003571 <.L69>:
+    3571:	fb          	im -5
+    3572:	ad          	im 45
+    3573:	3f          	callpcrel
+
+00003574 <.LM87>:
+    3574:	ff          	im -1
+    3575:	15          	addsp 20
+    3576:	55          	storesp 20
+    3577:	ec          	im -20
+    3578:	39          	poppcrel
+
+00003579 <hexdump_pure>:
+}
+
+void hexdump_pure(char const * str, int length)
+{
+    3579:	fb          	im -5
+    357a:	3d          	pushspadd
+    357b:	0d          	popsp
+    357c:	77          	loadsp 28
+    357d:	79          	loadsp 36
+
+0000357e <.LM89>:
+	xpos = xpos&0xfffe;
+    357e:	83          	im 3
+    357f:	e7          	im -25
+    3580:	f4          	im -12
+    3581:	08          	load
+    3582:	83          	im 3
+    3583:	ff          	im -1
+    3584:	fe          	im -2
+    3585:	06          	and
+    3586:	83          	im 3
+    3587:	e7          	im -25
+    3588:	f4          	im -12
+    3589:	0c          	store
+    358a:	56          	storesp 24
+    358b:	56          	storesp 24
+
+0000358c <.LM90>:
+	for (;length>0;--length)
+    358c:	80          	im 0
+    358d:	75          	loadsp 20
+    358e:	25          	lessthanorequal
+    358f:	80          	im 0
+    3590:	e5          	im -27
+    3591:	38          	neqbranch
+
+00003592 <.L83>:
+	{
+		unsigned char val= *str++;
+    3592:	75          	loadsp 20
+    3593:	70          	loadsp 0
+    3594:	81          	im 1
+    3595:	05          	add
+    3596:	57          	storesp 28
+    3597:	33          	loadb
+
+00003598 <.LM92>:
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+    3598:	70          	loadsp 0
+    3599:	84          	im 4
+    359a:	2a          	lshiftright
+    359b:	52          	storesp 8
+    359c:	54          	storesp 16
+    359d:	fc          	im -4
+    359e:	98          	im 24
+    359f:	3f          	callpcrel
+    35a0:	83          	im 3
+    35a1:	e8          	im -24
+    35a2:	80          	im 0
+    35a3:	08          	load
+    35a4:	53          	storesp 12
+    35a5:	83          	im 3
+    35a6:	e7          	im -25
+    35a7:	f4          	im -12
+    35a8:	08          	load
+    35a9:	52          	storesp 8
+    35aa:	83          	im 3
+    35ab:	e7          	im -25
+    35ac:	f4          	im -12
+    35ad:	08          	load
+    35ae:	81          	im 1
+    35af:	05          	add
+    35b0:	83          	im 3
+    35b1:	e7          	im -25
+    35b2:	f4          	im -12
+    35b3:	0c          	store
+    35b4:	83          	im 3
+    35b5:	e0          	im -32
+    35b6:	80          	im 0
+    35b7:	08          	load
+    35b8:	81          	im 1
+    35b9:	ff          	im -1
+    35ba:	06          	and
+    35bb:	51          	storesp 4
+    35bc:	fa          	im -6
+    35bd:	b1          	im 49
+    35be:	3f          	callpcrel
+
+000035bf <.LM93>:
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+    35bf:	73          	loadsp 12
+    35c0:	8f          	im 15
+    35c1:	06          	and
+    35c2:	51          	storesp 4
+    35c3:	fb          	im -5
+    35c4:	f2          	im -14
+    35c5:	3f          	callpcrel
+    35c6:	83          	im 3
+    35c7:	e8          	im -24
+    35c8:	80          	im 0
+    35c9:	08          	load
+    35ca:	53          	storesp 12
+    35cb:	83          	im 3
+    35cc:	e7          	im -25
+    35cd:	f4          	im -12
+    35ce:	08          	load
+    35cf:	52          	storesp 8
+    35d0:	83          	im 3
+    35d1:	e7          	im -25
+    35d2:	f4          	im -12
+    35d3:	08          	load
+    35d4:	81          	im 1
+    35d5:	05          	add
+    35d6:	83          	im 3
+    35d7:	e7          	im -25
+    35d8:	f4          	im -12
+    35d9:	0c          	store
+    35da:	83          	im 3
+    35db:	e0          	im -32
+    35dc:	80          	im 0
+    35dd:	08          	load
+    35de:	81          	im 1
+    35df:	ff          	im -1
+    35e0:	06          	and
+    35e1:	51          	storesp 4
+    35e2:	fa          	im -6
+    35e3:	8b          	im 11
+    35e4:	3f          	callpcrel
+
+000035e5 <.LM94>:
+
+		if (xpos==40)
+    35e5:	83          	im 3
+    35e6:	e7          	im -25
+    35e7:	f4          	im -12
+    35e8:	08          	load
+    35e9:	a8          	im 40
+    35ea:	2e          	eq
+    35eb:	8e          	im 14
+    35ec:	38          	neqbranch
+
+000035ed <.LM95>:
+    35ed:	ff          	im -1
+    35ee:	15          	addsp 20
+    35ef:	55          	storesp 20
+
+000035f0 <.L84>:
+    35f0:	74          	loadsp 16
+    35f1:	80          	im 0
+    35f2:	24          	lessthan
+    35f3:	ff          	im -1
+    35f4:	9d          	im 29
+    35f5:	38          	neqbranch
+
+000035f6 <.L79>:
+    35f6:	87          	im 7
+    35f7:	3d          	pushspadd
+    35f8:	0d          	popsp
+    35f9:	04          	poppc
+
+000035fa <.L82>:
+		{
+			nextline();
+    35fa:	fa          	im -6
+    35fb:	a4          	im 36
+    35fc:	3f          	callpcrel
+
+000035fd <.LM97>:
+    35fd:	ff          	im -1
+    35fe:	15          	addsp 20
+    35ff:	55          	storesp 20
+    3600:	ef          	im -17
+    3601:	39          	poppcrel
+
+00003602 <__udivsi3>:
+    3602:	83          	im 3
+    3603:	e0          	im -32
+    3604:	8c          	im 12
+    3605:	08          	load
+    3606:	02          	pushsp
+    3607:	83          	im 3
+    3608:	e0          	im -32
+    3609:	8c          	im 12
+    360a:	0c          	store
+    360b:	fd          	im -3
+    360c:	3d          	pushspadd
+    360d:	0d          	popsp
+    360e:	80          	im 0
+    360f:	53          	storesp 12
+    3610:	83          	im 3
+    3611:	e0          	im -32
+    3612:	8c          	im 12
+    3613:	08          	load
+    3614:	8c          	im 12
+    3615:	05          	add
+    3616:	08          	load
+    3617:	52          	storesp 8
+    3618:	83          	im 3
+    3619:	e0          	im -32
+    361a:	8c          	im 12
+    361b:	08          	load
+    361c:	88          	im 8
+    361d:	05          	add
+    361e:	08          	load
+    361f:	51          	storesp 4
+    3620:	83          	im 3
+    3621:	d4          	im -44
+    3622:	3f          	callpcrel
+    3623:	83          	im 3
+    3624:	e0          	im -32
+    3625:	80          	im 0
+    3626:	08          	load
+    3627:	70          	loadsp 0
+    3628:	83          	im 3
+    3629:	e0          	im -32
+    362a:	80          	im 0
+    362b:	0c          	store
+    362c:	54          	storesp 16
+    362d:	85          	im 5
+    362e:	3d          	pushspadd
+    362f:	0d          	popsp
+    3630:	83          	im 3
+    3631:	e0          	im -32
+    3632:	8c          	im 12
+    3633:	0c          	store
+    3634:	04          	poppc
+
+00003635 <__umodsi3>:
+    3635:	83          	im 3
+    3636:	e0          	im -32
+    3637:	8c          	im 12
+    3638:	08          	load
+    3639:	02          	pushsp
+    363a:	83          	im 3
+    363b:	e0          	im -32
+    363c:	8c          	im 12
+    363d:	0c          	store
+    363e:	fd          	im -3
+    363f:	3d          	pushspadd
+    3640:	0d          	popsp
+    3641:	81          	im 1
+    3642:	53          	storesp 12
+    3643:	83          	im 3
+    3644:	e0          	im -32
+    3645:	8c          	im 12
+    3646:	08          	load
+    3647:	8c          	im 12
+    3648:	05          	add
+    3649:	08          	load
+    364a:	52          	storesp 8
+    364b:	83          	im 3
+    364c:	e0          	im -32
+    364d:	8c          	im 12
+    364e:	08          	load
+    364f:	88          	im 8
+    3650:	05          	add
+    3651:	08          	load
+    3652:	51          	storesp 4
+    3653:	83          	im 3
+    3654:	a1          	im 33
+    3655:	3f          	callpcrel
+    3656:	83          	im 3
+    3657:	e0          	im -32
+    3658:	80          	im 0
+    3659:	08          	load
+    365a:	70          	loadsp 0
+    365b:	83          	im 3
+    365c:	e0          	im -32
+    365d:	80          	im 0
+    365e:	0c          	store
+    365f:	54          	storesp 16
+    3660:	85          	im 5
+    3661:	3d          	pushspadd
+    3662:	0d          	popsp
+    3663:	83          	im 3
+    3664:	e0          	im -32
+    3665:	8c          	im 12
+    3666:	0c          	store
+    3667:	04          	poppc
+
+00003668 <__divsi3>:
+    3668:	83          	im 3
+    3669:	e0          	im -32
+    366a:	8c          	im 12
+    366b:	08          	load
+    366c:	02          	pushsp
+    366d:	83          	im 3
+    366e:	e0          	im -32
+    366f:	8c          	im 12
+    3670:	0c          	store
+    3671:	f9          	im -7
+    3672:	3d          	pushspadd
+    3673:	0d          	popsp
+    3674:	80          	im 0
+    3675:	0b          	nop
+    3676:	83          	im 3
+    3677:	e0          	im -32
+    3678:	8c          	im 12
+    3679:	08          	load
+    367a:	fc          	im -4
+    367b:	05          	add
+    367c:	0c          	store
+    367d:	83          	im 3
+    367e:	e0          	im -32
+    367f:	8c          	im 12
+    3680:	08          	load
+    3681:	88          	im 8
+    3682:	05          	add
+    3683:	08          	load
+    3684:	80          	im 0
+    3685:	25          	lessthanorequal
+    3686:	b9          	im 57
+    3687:	38          	neqbranch
+    3688:	83          	im 3
+    3689:	e0          	im -32
+    368a:	8c          	im 12
+    368b:	08          	load
+    368c:	88          	im 8
+    368d:	05          	add
+    368e:	08          	load
+    368f:	30          	neg
+    3690:	83          	im 3
+    3691:	e0          	im -32
+    3692:	8c          	im 12
+    3693:	08          	load
+    3694:	88          	im 8
+    3695:	05          	add
+    3696:	0c          	store
+    3697:	80          	im 0
+    3698:	0b          	nop
+    3699:	83          	im 3
+    369a:	e0          	im -32
+    369b:	8c          	im 12
+    369c:	08          	load
+    369d:	f4          	im -12
+    369e:	05          	add
+    369f:	0c          	store
+    36a0:	83          	im 3
+    36a1:	e0          	im -32
+    36a2:	8c          	im 12
+    36a3:	08          	load
+    36a4:	fc          	im -4
+    36a5:	05          	add
+    36a6:	08          	load
+    36a7:	8a          	im 10
+    36a8:	38          	neqbranch
+    36a9:	81          	im 1
+    36aa:	0b          	nop
+    36ab:	83          	im 3
+    36ac:	e0          	im -32
+    36ad:	8c          	im 12
+    36ae:	08          	load
+    36af:	f4          	im -12
+    36b0:	05          	add
+    36b1:	0c          	store
+
+000036b2 <.L3>:
+    36b2:	83          	im 3
+    36b3:	e0          	im -32
+    36b4:	8c          	im 12
+    36b5:	08          	load
+    36b6:	f4          	im -12
+    36b7:	05          	add
+    36b8:	08          	load
+    36b9:	83          	im 3
+    36ba:	e0          	im -32
+    36bb:	8c          	im 12
+    36bc:	08          	load
+    36bd:	fc          	im -4
+    36be:	05          	add
+    36bf:	0c          	store
+
+000036c0 <.L2>:
+    36c0:	83          	im 3
+    36c1:	e0          	im -32
+    36c2:	8c          	im 12
+    36c3:	08          	load
+    36c4:	8c          	im 12
+    36c5:	05          	add
+    36c6:	08          	load
+    36c7:	80          	im 0
+    36c8:	25          	lessthanorequal
+    36c9:	b9          	im 57
+    36ca:	38          	neqbranch
+    36cb:	83          	im 3
+    36cc:	e0          	im -32
+    36cd:	8c          	im 12
+    36ce:	08          	load
+    36cf:	8c          	im 12
+    36d0:	05          	add
+    36d1:	08          	load
+    36d2:	30          	neg
+    36d3:	83          	im 3
+    36d4:	e0          	im -32
+    36d5:	8c          	im 12
+    36d6:	08          	load
+    36d7:	8c          	im 12
+    36d8:	05          	add
+    36d9:	0c          	store
+    36da:	80          	im 0
+    36db:	0b          	nop
+    36dc:	83          	im 3
+    36dd:	e0          	im -32
+    36de:	8c          	im 12
+    36df:	08          	load
+    36e0:	f0          	im -16
+    36e1:	05          	add
+    36e2:	0c          	store
+    36e3:	83          	im 3
+    36e4:	e0          	im -32
+    36e5:	8c          	im 12
+    36e6:	08          	load
+    36e7:	fc          	im -4
+    36e8:	05          	add
+    36e9:	08          	load
+    36ea:	8a          	im 10
+    36eb:	38          	neqbranch
+    36ec:	81          	im 1
+    36ed:	0b          	nop
+    36ee:	83          	im 3
+    36ef:	e0          	im -32
+    36f0:	8c          	im 12
+    36f1:	08          	load
+    36f2:	f0          	im -16
+    36f3:	05          	add
+    36f4:	0c          	store
+
+000036f5 <.L5>:
+    36f5:	83          	im 3
+    36f6:	e0          	im -32
+    36f7:	8c          	im 12
+    36f8:	08          	load
+    36f9:	f0          	im -16
+    36fa:	05          	add
+    36fb:	08          	load
+    36fc:	83          	im 3
+    36fd:	e0          	im -32
+    36fe:	8c          	im 12
+    36ff:	08          	load
+    3700:	fc          	im -4
+    3701:	05          	add
+    3702:	0c          	store
+
+00003703 <.L4>:
+    3703:	80          	im 0
+    3704:	53          	storesp 12
+    3705:	83          	im 3
+    3706:	e0          	im -32
+    3707:	8c          	im 12
+    3708:	08          	load
+    3709:	8c          	im 12
+    370a:	05          	add
+    370b:	08          	load
+    370c:	52          	storesp 8
+    370d:	83          	im 3
+    370e:	e0          	im -32
+    370f:	8c          	im 12
+    3710:	08          	load
+    3711:	88          	im 8
+    3712:	05          	add
+    3713:	08          	load
+    3714:	51          	storesp 4
+    3715:	81          	im 1
+    3716:	df          	im -33
+    3717:	3f          	callpcrel
+    3718:	83          	im 3
+    3719:	e0          	im -32
+    371a:	80          	im 0
+    371b:	08          	load
+    371c:	70          	loadsp 0
+    371d:	83          	im 3
+    371e:	e0          	im -32
+    371f:	8c          	im 12
+    3720:	08          	load
+    3721:	f8          	im -8
+    3722:	05          	add
+    3723:	0c          	store
+    3724:	54          	storesp 16
+    3725:	83          	im 3
+    3726:	e0          	im -32
+    3727:	8c          	im 12
+    3728:	08          	load
+    3729:	fc          	im -4
+    372a:	05          	add
+    372b:	08          	load
+    372c:	80          	im 0
+    372d:	2e          	eq
+    372e:	90          	im 16
+    372f:	38          	neqbranch
+    3730:	83          	im 3
+    3731:	e0          	im -32
+    3732:	8c          	im 12
+    3733:	08          	load
+    3734:	f8          	im -8
+    3735:	05          	add
+    3736:	08          	load
+    3737:	30          	neg
+    3738:	83          	im 3
+    3739:	e0          	im -32
+    373a:	8c          	im 12
+    373b:	08          	load
+    373c:	f8          	im -8
+    373d:	05          	add
+    373e:	0c          	store
+
+0000373f <.L6>:
+    373f:	83          	im 3
+    3740:	e0          	im -32
+    3741:	8c          	im 12
+    3742:	08          	load
+    3743:	f8          	im -8
+    3744:	05          	add
+    3745:	08          	load
+    3746:	70          	loadsp 0
+    3747:	83          	im 3
+    3748:	e0          	im -32
+    3749:	80          	im 0
+    374a:	0c          	store
+    374b:	54          	storesp 16
+    374c:	89          	im 9
+    374d:	3d          	pushspadd
+    374e:	0d          	popsp
+    374f:	83          	im 3
+    3750:	e0          	im -32
+    3751:	8c          	im 12
+    3752:	0c          	store
+    3753:	04          	poppc
+
+00003754 <__modsi3>:
+    3754:	83          	im 3
+    3755:	e0          	im -32
+    3756:	8c          	im 12
+    3757:	08          	load
+    3758:	02          	pushsp
+    3759:	83          	im 3
+    375a:	e0          	im -32
+    375b:	8c          	im 12
+    375c:	0c          	store
+    375d:	fb          	im -5
+    375e:	3d          	pushspadd
+    375f:	0d          	popsp
+    3760:	80          	im 0
+    3761:	0b          	nop
+    3762:	83          	im 3
+    3763:	e0          	im -32
+    3764:	8c          	im 12
+    3765:	08          	load
+    3766:	fc          	im -4
+    3767:	05          	add
+    3768:	0c          	store
+    3769:	83          	im 3
+    376a:	e0          	im -32
+    376b:	8c          	im 12
+    376c:	08          	load
+    376d:	88          	im 8
+    376e:	05          	add
+    376f:	08          	load
+    3770:	80          	im 0
+    3771:	25          	lessthanorequal
+    3772:	99          	im 25
+    3773:	38          	neqbranch
+    3774:	83          	im 3
+    3775:	e0          	im -32
+    3776:	8c          	im 12
+    3777:	08          	load
+    3778:	88          	im 8
+    3779:	05          	add
+    377a:	08          	load
+    377b:	30          	neg
+    377c:	83          	im 3
+    377d:	e0          	im -32
+    377e:	8c          	im 12
+    377f:	08          	load
+    3780:	88          	im 8
+    3781:	05          	add
+    3782:	0c          	store
+    3783:	81          	im 1
+    3784:	0b          	nop
+    3785:	83          	im 3
+    3786:	e0          	im -32
+    3787:	8c          	im 12
+    3788:	08          	load
+    3789:	fc          	im -4
+    378a:	05          	add
+    378b:	0c          	store
+
+0000378c <.L8>:
+    378c:	83          	im 3
+    378d:	e0          	im -32
+    378e:	8c          	im 12
+    378f:	08          	load
+    3790:	8c          	im 12
+    3791:	05          	add
+    3792:	08          	load
+    3793:	80          	im 0
+    3794:	25          	lessthanorequal
+    3795:	90          	im 16
+    3796:	38          	neqbranch
+    3797:	83          	im 3
+    3798:	e0          	im -32
+    3799:	8c          	im 12
+    379a:	08          	load
+    379b:	8c          	im 12
+    379c:	05          	add
+    379d:	08          	load
+    379e:	30          	neg
+    379f:	83          	im 3
+    37a0:	e0          	im -32
+    37a1:	8c          	im 12
+    37a2:	08          	load
+    37a3:	8c          	im 12
+    37a4:	05          	add
+    37a5:	0c          	store
+
+000037a6 <.L9>:
+    37a6:	81          	im 1
+    37a7:	53          	storesp 12
+    37a8:	83          	im 3
+    37a9:	e0          	im -32
+    37aa:	8c          	im 12
+    37ab:	08          	load
+    37ac:	8c          	im 12
+    37ad:	05          	add
+    37ae:	08          	load
+    37af:	52          	storesp 8
+    37b0:	83          	im 3
+    37b1:	e0          	im -32
+    37b2:	8c          	im 12
+    37b3:	08          	load
+    37b4:	88          	im 8
+    37b5:	05          	add
+    37b6:	08          	load
+    37b7:	51          	storesp 4
+    37b8:	bd          	im 61
+    37b9:	3f          	callpcrel
+    37ba:	83          	im 3
+    37bb:	e0          	im -32
+    37bc:	80          	im 0
+    37bd:	08          	load
+    37be:	70          	loadsp 0
+    37bf:	83          	im 3
+    37c0:	e0          	im -32
+    37c1:	8c          	im 12
+    37c2:	08          	load
+    37c3:	f8          	im -8
+    37c4:	05          	add
+    37c5:	0c          	store
+    37c6:	54          	storesp 16
+    37c7:	83          	im 3
+    37c8:	e0          	im -32
+    37c9:	8c          	im 12
+    37ca:	08          	load
+    37cb:	fc          	im -4
+    37cc:	05          	add
+    37cd:	08          	load
+    37ce:	80          	im 0
+    37cf:	2e          	eq
+    37d0:	90          	im 16
+    37d1:	38          	neqbranch
+    37d2:	83          	im 3
+    37d3:	e0          	im -32
+    37d4:	8c          	im 12
+    37d5:	08          	load
+    37d6:	f8          	im -8
+    37d7:	05          	add
+    37d8:	08          	load
+    37d9:	30          	neg
+    37da:	83          	im 3
+    37db:	e0          	im -32
+    37dc:	8c          	im 12
+    37dd:	08          	load
+    37de:	f8          	im -8
+    37df:	05          	add
+    37e0:	0c          	store
+
+000037e1 <.L10>:
+    37e1:	83          	im 3
+    37e2:	e0          	im -32
+    37e3:	8c          	im 12
+    37e4:	08          	load
+    37e5:	f8          	im -8
+    37e6:	05          	add
+    37e7:	08          	load
+    37e8:	70          	loadsp 0
+    37e9:	83          	im 3
+    37ea:	e0          	im -32
+    37eb:	80          	im 0
+    37ec:	0c          	store
+    37ed:	54          	storesp 16
+    37ee:	87          	im 7
+    37ef:	3d          	pushspadd
+    37f0:	0d          	popsp
+    37f1:	83          	im 3
+    37f2:	e0          	im -32
+    37f3:	8c          	im 12
+    37f4:	0c          	store
+    37f5:	04          	poppc
+
+000037f6 <udivmodsi4>:
+    37f6:	83          	im 3
+    37f7:	e0          	im -32
+    37f8:	8c          	im 12
+    37f9:	08          	load
+    37fa:	02          	pushsp
+    37fb:	83          	im 3
+    37fc:	e0          	im -32
+    37fd:	8c          	im 12
+    37fe:	0c          	store
+    37ff:	fd          	im -3
+    3800:	3d          	pushspadd
+    3801:	0d          	popsp
+    3802:	81          	im 1
+    3803:	0b          	nop
+    3804:	83          	im 3
+    3805:	e0          	im -32
+    3806:	8c          	im 12
+    3807:	08          	load
+    3808:	fc          	im -4
+    3809:	05          	add
+    380a:	0c          	store
+    380b:	80          	im 0
+    380c:	0b          	nop
+    380d:	83          	im 3
+    380e:	e0          	im -32
+    380f:	8c          	im 12
+    3810:	08          	load
+    3811:	f8          	im -8
+    3812:	05          	add
+    3813:	0c          	store
+
+00003814 <.L2>:
+    3814:	83          	im 3
+    3815:	e0          	im -32
+    3816:	8c          	im 12
+    3817:	08          	load
+    3818:	8c          	im 12
+    3819:	05          	add
+    381a:	08          	load
+    381b:	83          	im 3
+    381c:	e0          	im -32
+    381d:	8c          	im 12
+    381e:	08          	load
+    381f:	88          	im 8
+    3820:	05          	add
+    3821:	08          	load
+    3822:	27          	ulessthanorequal
+    3823:	b9          	im 57
+    3824:	38          	neqbranch
+    3825:	83          	im 3
+    3826:	e0          	im -32
+    3827:	8c          	im 12
+    3828:	08          	load
+    3829:	fc          	im -4
+    382a:	05          	add
+    382b:	08          	load
+    382c:	80          	im 0
+    382d:	2e          	eq
+    382e:	ae          	im 46
+    382f:	38          	neqbranch
+    3830:	80          	im 0
+    3831:	0b          	nop
+    3832:	83          	im 3
+    3833:	e0          	im -32
+    3834:	8c          	im 12
+    3835:	08          	load
+    3836:	8c          	im 12
+    3837:	05          	add
+    3838:	08          	load
+    3839:	24          	lessthan
+    383a:	a2          	im 34
+    383b:	38          	neqbranch
+    383c:	83          	im 3
+    383d:	e0          	im -32
+    383e:	8c          	im 12
+    383f:	08          	load
+    3840:	8c          	im 12
+    3841:	05          	add
+    3842:	08          	load
+    3843:	10          	addsp 0
+    3844:	83          	im 3
+    3845:	e0          	im -32
+    3846:	8c          	im 12
+    3847:	08          	load
+    3848:	8c          	im 12
+    3849:	05          	add
+    384a:	0c          	store
+    384b:	83          	im 3
+    384c:	e0          	im -32
+    384d:	8c          	im 12
+    384e:	08          	load
+    384f:	fc          	im -4
+    3850:	05          	add
+    3851:	08          	load
+    3852:	10          	addsp 0
+    3853:	83          	im 3
+    3854:	e0          	im -32
+    3855:	8c          	im 12
+    3856:	08          	load
+    3857:	fc          	im -4
+    3858:	05          	add
+    3859:	0c          	store
+    385a:	ff          	im -1
+    385b:	b8          	im 56
+    385c:	39          	poppcrel
+
+0000385d <.L4>:
+    385d:	83          	im 3
+    385e:	e0          	im -32
+    385f:	8c          	im 12
+    3860:	08          	load
+    3861:	fc          	im -4
+    3862:	05          	add
+    3863:	08          	load
+    3864:	80          	im 0
+    3865:	2e          	eq
+    3866:	80          	im 0
+    3867:	e1          	im -31
+    3868:	38          	neqbranch
+    3869:	83          	im 3
+    386a:	e0          	im -32
+    386b:	8c          	im 12
+    386c:	08          	load
+    386d:	8c          	im 12
+    386e:	05          	add
+    386f:	08          	load
+    3870:	83          	im 3
+    3871:	e0          	im -32
+    3872:	8c          	im 12
+    3873:	08          	load
+    3874:	88          	im 8
+    3875:	05          	add
+    3876:	08          	load
+    3877:	26          	ulessthan
+    3878:	ad          	im 45
+    3879:	38          	neqbranch
+    387a:	83          	im 3
+    387b:	e0          	im -32
+    387c:	8c          	im 12
+    387d:	08          	load
+    387e:	88          	im 8
+    387f:	05          	add
+    3880:	08          	load
+    3881:	83          	im 3
+    3882:	e0          	im -32
+    3883:	8c          	im 12
+    3884:	08          	load
+    3885:	8c          	im 12
+    3886:	05          	add
+    3887:	08          	load
+    3888:	31          	sub
+    3889:	83          	im 3
+    388a:	e0          	im -32
+    388b:	8c          	im 12
+    388c:	08          	load
+    388d:	88          	im 8
+    388e:	05          	add
+    388f:	0c          	store
+    3890:	83          	im 3
+    3891:	e0          	im -32
+    3892:	8c          	im 12
+    3893:	08          	load
+    3894:	f8          	im -8
+    3895:	05          	add
+    3896:	08          	load
+    3897:	83          	im 3
+    3898:	e0          	im -32
+    3899:	8c          	im 12
+    389a:	08          	load
+    389b:	fc          	im -4
+    389c:	05          	add
+    389d:	08          	load
+    389e:	07          	or
+    389f:	83          	im 3
+    38a0:	e0          	im -32
+    38a1:	8c          	im 12
+    38a2:	08          	load
+    38a3:	f8          	im -8
+    38a4:	05          	add
+    38a5:	0c          	store
+
+000038a6 <.L6>:
+    38a6:	83          	im 3
+    38a7:	e0          	im -32
+    38a8:	8c          	im 12
+    38a9:	08          	load
+    38aa:	fc          	im -4
+    38ab:	05          	add
+    38ac:	08          	load
+    38ad:	81          	im 1
+    38ae:	2a          	lshiftright
+    38af:	83          	im 3
+    38b0:	e0          	im -32
+    38b1:	8c          	im 12
+    38b2:	08          	load
+    38b3:	fc          	im -4
+    38b4:	05          	add
+    38b5:	0c          	store
+    38b6:	83          	im 3
+    38b7:	e0          	im -32
+    38b8:	8c          	im 12
+    38b9:	08          	load
+    38ba:	8c          	im 12
+    38bb:	05          	add
+    38bc:	08          	load
+    38bd:	81          	im 1
+    38be:	2a          	lshiftright
+    38bf:	83          	im 3
+    38c0:	e0          	im -32
+    38c1:	8c          	im 12
+    38c2:	08          	load
+    38c3:	8c          	im 12
+    38c4:	05          	add
+    38c5:	0c          	store
+    38c6:	ff          	im -1
+    38c7:	95          	im 21
+    38c8:	39          	poppcrel
+
+000038c9 <.L5>:
+    38c9:	83          	im 3
+    38ca:	e0          	im -32
+    38cb:	8c          	im 12
+    38cc:	08          	load
+    38cd:	90          	im 16
+    38ce:	05          	add
+    38cf:	08          	load
+    38d0:	80          	im 0
+    38d1:	2e          	eq
+    38d2:	93          	im 19
+    38d3:	38          	neqbranch
+    38d4:	83          	im 3
+    38d5:	e0          	im -32
+    38d6:	8c          	im 12
+    38d7:	08          	load
+    38d8:	88          	im 8
+    38d9:	05          	add
+    38da:	08          	load
+    38db:	70          	loadsp 0
+    38dc:	83          	im 3
+    38dd:	e0          	im -32
+    38de:	8c          	im 12
+    38df:	08          	load
+    38e0:	f4          	im -12
+    38e1:	05          	add
+    38e2:	0c          	store
+    38e3:	51          	storesp 4
+    38e4:	91          	im 17
+    38e5:	39          	poppcrel
+
+000038e6 <.L7>:
+    38e6:	83          	im 3
+    38e7:	e0          	im -32
+    38e8:	8c          	im 12
+    38e9:	08          	load
+    38ea:	f8          	im -8
+    38eb:	05          	add
+    38ec:	08          	load
+    38ed:	70          	loadsp 0
+    38ee:	83          	im 3
+    38ef:	e0          	im -32
+    38f0:	8c          	im 12
+    38f1:	08          	load
+    38f2:	f4          	im -12
+    38f3:	05          	add
+    38f4:	0c          	store
+    38f5:	51          	storesp 4
+
+000038f6 <.L1>:
+    38f6:	83          	im 3
+    38f7:	e0          	im -32
+    38f8:	8c          	im 12
+    38f9:	08          	load
+    38fa:	f4          	im -12
+    38fb:	05          	add
+    38fc:	08          	load
+    38fd:	83          	im 3
+    38fe:	e0          	im -32
+    38ff:	80          	im 0
+    3900:	0c          	store
+    3901:	85          	im 5
+    3902:	3d          	pushspadd
+    3903:	0d          	popsp
+    3904:	83          	im 3
+    3905:	e0          	im -32
+    3906:	8c          	im 12
+    3907:	0c          	store
+    3908:	04          	poppc
+
+00003909 <__mulsi3>:
+    3909:	83          	im 3
+    390a:	e0          	im -32
+    390b:	8c          	im 12
+    390c:	08          	load
+    390d:	02          	pushsp
+    390e:	83          	im 3
+    390f:	e0          	im -32
+    3910:	8c          	im 12
+    3911:	0c          	store
+    3912:	ff          	im -1
+    3913:	3d          	pushspadd
+    3914:	0d          	popsp
+    3915:	80          	im 0
+    3916:	0b          	nop
+    3917:	83          	im 3
+    3918:	e0          	im -32
+    3919:	8c          	im 12
+    391a:	08          	load
+    391b:	fc          	im -4
+    391c:	05          	add
+    391d:	0c          	store
+
+0000391e <.L2>:
+    391e:	83          	im 3
+    391f:	e0          	im -32
+    3920:	8c          	im 12
+    3921:	08          	load
+    3922:	88          	im 8
+    3923:	05          	add
+    3924:	08          	load
+    3925:	81          	im 1
+    3926:	06          	and
+    3927:	ff          	im -1
+    3928:	11          	addsp 4
+    3929:	70          	loadsp 0
+    392a:	09          	not
+    392b:	70          	loadsp 0
+    392c:	83          	im 3
+    392d:	e0          	im -32
+    392e:	8c          	im 12
+    392f:	08          	load
+    3930:	8c          	im 12
+    3931:	05          	add
+    3932:	08          	load
+    3933:	06          	and
+    3934:	83          	im 3
+    3935:	e0          	im -32
+    3936:	8c          	im 12
+    3937:	08          	load
+    3938:	fc          	im -4
+    3939:	05          	add
+    393a:	08          	load
+    393b:	11          	addsp 4
+    393c:	83          	im 3
+    393d:	e0          	im -32
+    393e:	8c          	im 12
+    393f:	08          	load
+    3940:	fc          	im -4
+    3941:	05          	add
+    3942:	0c          	store
+    3943:	83          	im 3
+    3944:	e0          	im -32
+    3945:	8c          	im 12
+    3946:	08          	load
+    3947:	88          	im 8
+    3948:	05          	add
+    3949:	08          	load
+    394a:	81          	im 1
+    394b:	2a          	lshiftright
+    394c:	83          	im 3
+    394d:	e0          	im -32
+    394e:	8c          	im 12
+    394f:	08          	load
+    3950:	88          	im 8
+    3951:	05          	add
+    3952:	0c          	store
+    3953:	83          	im 3
+    3954:	e0          	im -32
+    3955:	8c          	im 12
+    3956:	08          	load
+    3957:	8c          	im 12
+    3958:	05          	add
+    3959:	08          	load
+    395a:	10          	addsp 0
+    395b:	83          	im 3
+    395c:	e0          	im -32
+    395d:	8c          	im 12
+    395e:	08          	load
+    395f:	8c          	im 12
+    3960:	05          	add
+    3961:	0c          	store
+    3962:	51          	storesp 4
+    3963:	51          	storesp 4
+    3964:	51          	storesp 4
+    3965:	51          	storesp 4
+    3966:	83          	im 3
+    3967:	e0          	im -32
+    3968:	8c          	im 12
+    3969:	08          	load
+    396a:	88          	im 8
+    396b:	05          	add
+    396c:	08          	load
+    396d:	80          	im 0
+    396e:	2e          	eq
+    396f:	84          	im 4
+    3970:	38          	neqbranch
+    3971:	ff          	im -1
+    3972:	ab          	im 43
+    3973:	39          	poppcrel
+
+00003974 <.L3>:
+    3974:	83          	im 3
+    3975:	e0          	im -32
+    3976:	8c          	im 12
+    3977:	08          	load
+    3978:	fc          	im -4
+    3979:	05          	add
+    397a:	08          	load
+    397b:	70          	loadsp 0
+    397c:	83          	im 3
+    397d:	e0          	im -32
+    397e:	80          	im 0
+    397f:	0c          	store
+    3980:	51          	storesp 4
+    3981:	83          	im 3
+    3982:	3d          	pushspadd
+    3983:	0d          	popsp
+    3984:	83          	im 3
+    3985:	e0          	im -32
+    3986:	8c          	im 12
+    3987:	0c          	store
+    3988:	04          	poppc
+
+00003989 <memcpy>:
+    3989:	fc          	im -4
+    398a:	3d          	pushspadd
+    398b:	0d          	popsp
+    398c:	76          	loadsp 24
+
+0000398d <.LM2>:
+    398d:	70          	loadsp 0
+
+0000398e <.LM3>:
+    398e:	79          	loadsp 36
+
+0000398f <.LM4>:
+    398f:	7b          	loadsp 44
+    3990:	55          	storesp 20
+    3991:	55          	storesp 20
+    3992:	55          	storesp 20
+    3993:	55          	storesp 20
+
+00003994 <.LM5>:
+    3994:	8f          	im 15
+    3995:	72          	loadsp 8
+    3996:	27          	ulessthanorequal
+    3997:	8c          	im 12
+    3998:	38          	neqbranch
+    3999:	72          	loadsp 8
+    399a:	75          	loadsp 20
+    399b:	07          	or
+    399c:	83          	im 3
+    399d:	06          	and
+    399e:	51          	storesp 4
+    399f:	70          	loadsp 0
+    39a0:	80          	im 0
+    39a1:	2e          	eq
+    39a2:	a9          	im 41
+    39a3:	38          	neqbranch
+
+000039a4 <.L2>:
+    39a4:	ff          	im -1
+    39a5:	12          	addsp 8
+    39a6:	52          	storesp 8
+    39a7:	71          	loadsp 4
+    39a8:	ff          	im -1
+    39a9:	2e          	eq
+    39aa:	98          	im 24
+    39ab:	38          	neqbranch
+
+000039ac <.L21>:
+    39ac:	72          	loadsp 8
+    39ad:	70          	loadsp 0
+    39ae:	81          	im 1
+    39af:	05          	add
+    39b0:	54          	storesp 16
+    39b1:	33          	loadb
+    39b2:	74          	loadsp 16
+    39b3:	70          	loadsp 0
+    39b4:	81          	im 1
+    39b5:	05          	add
+    39b6:	56          	storesp 24
+    39b7:	34          	storeb
+    39b8:	ff          	im -1
+    39b9:	12          	addsp 8
+    39ba:	52          	storesp 8
+    39bb:	71          	loadsp 4
+    39bc:	ff          	im -1
+    39bd:	2e          	eq
+    39be:	09          	not
+    39bf:	81          	im 1
+    39c0:	06          	and
+    39c1:	ea          	im -22
+    39c2:	38          	neqbranch
+
+000039c3 <.L17>:
+    39c3:	74          	loadsp 16
+    39c4:	83          	im 3
+    39c5:	e0          	im -32
+    39c6:	80          	im 0
+    39c7:	0c          	store
+    39c8:	86          	im 6
+    39c9:	3d          	pushspadd
+    39ca:	0d          	popsp
+    39cb:	04          	poppc
+
+000039cc <.L20>:
+    39cc:	74          	loadsp 16
+    39cd:	51          	storesp 4
+
+000039ce <.L5>:
+    39ce:	72          	loadsp 8
+    39cf:	70          	loadsp 0
+    39d0:	84          	im 4
+    39d1:	05          	add
+    39d2:	54          	storesp 16
+    39d3:	08          	load
+    39d4:	71          	loadsp 4
+    39d5:	70          	loadsp 0
+    39d6:	84          	im 4
+    39d7:	05          	add
+    39d8:	53          	storesp 12
+    39d9:	0c          	store
+
+000039da <.LM10>:
+    39da:	72          	loadsp 8
+    39db:	70          	loadsp 0
+    39dc:	84          	im 4
+    39dd:	05          	add
+    39de:	54          	storesp 16
+    39df:	08          	load
+    39e0:	71          	loadsp 4
+    39e1:	70          	loadsp 0
+    39e2:	84          	im 4
+    39e3:	05          	add
+    39e4:	53          	storesp 12
+    39e5:	0c          	store
+
+000039e6 <.LM11>:
+    39e6:	72          	loadsp 8
+    39e7:	70          	loadsp 0
+    39e8:	84          	im 4
+    39e9:	05          	add
+    39ea:	54          	storesp 16
+    39eb:	08          	load
+    39ec:	71          	loadsp 4
+    39ed:	70          	loadsp 0
+    39ee:	84          	im 4
+    39ef:	05          	add
+    39f0:	53          	storesp 12
+    39f1:	0c          	store
+
+000039f2 <.LM12>:
+    39f2:	72          	loadsp 8
+    39f3:	70          	loadsp 0
+    39f4:	84          	im 4
+    39f5:	05          	add
+    39f6:	54          	storesp 16
+    39f7:	08          	load
+    39f8:	71          	loadsp 4
+    39f9:	70          	loadsp 0
+    39fa:	84          	im 4
+    39fb:	05          	add
+    39fc:	53          	storesp 12
+    39fd:	0c          	store
+
+000039fe <.LM13>:
+    39fe:	f0          	im -16
+    39ff:	12          	addsp 8
+    3a00:	52          	storesp 8
+    3a01:	71          	loadsp 4
+    3a02:	8f          	im 15
+    3a03:	26          	ulessthan
+    3a04:	c9          	im -55
+    3a05:	38          	neqbranch
+
+00003a06 <.LM14>:
+    3a06:	83          	im 3
+    3a07:	72          	loadsp 8
+    3a08:	27          	ulessthanorequal
+    3a09:	95          	im 21
+    3a0a:	38          	neqbranch
+
+00003a0b <.L22>:
+    3a0b:	72          	loadsp 8
+    3a0c:	70          	loadsp 0
+    3a0d:	84          	im 4
+    3a0e:	05          	add
+    3a0f:	54          	storesp 16
+    3a10:	08          	load
+    3a11:	71          	loadsp 4
+    3a12:	70          	loadsp 0
+    3a13:	84          	im 4
+    3a14:	05          	add
+    3a15:	53          	storesp 12
+    3a16:	0c          	store
+
+00003a17 <.LM16>:
+    3a17:	fc          	im -4
+    3a18:	12          	addsp 8
+    3a19:	52          	storesp 8
+    3a1a:	71          	loadsp 4
+    3a1b:	83          	im 3
+    3a1c:	26          	ulessthan
+    3a1d:	ed          	im -19
+    3a1e:	38          	neqbranch
+
+00003a1f <.L15>:
+    3a1f:	70          	loadsp 0
+    3a20:	54          	storesp 16
+    3a21:	ff          	im -1
+    3a22:	81          	im 1
+    3a23:	39          	poppcrel
Index: unmerged/zpu_firmware/replay/HelloTinyROM.dis
===================================================================
--- unmerged/zpu_firmware/replay/HelloTinyROM.dis	(nonexistent)
+++ unmerged/zpu_firmware/replay/HelloTinyROM.dis	(revision 1)
@@ -0,0 +1,5937 @@
+
+HelloTinyROM.elf:     file format elf32-zpu
+
+Disassembly of section .fixed_vectors:
+
+00000000 <_start>:
+   0:	0b          	nop
+   1:	0b          	nop
+   2:	0b          	nop
+   3:	89          	im 9
+   4:	ab          	im 43
+   5:	04          	poppc
+   6:	0b          	nop
+   7:	0b          	nop
+   8:	0b          	nop
+   9:	0b          	nop
+   a:	0b          	nop
+   b:	0b          	nop
+   c:	0b          	nop
+   d:	0b          	nop
+   e:	0b          	nop
+   f:	0b          	nop
+  10:	0b          	nop
+  11:	0b          	nop
+  12:	0b          	nop
+  13:	0b          	nop
+  14:	0b          	nop
+  15:	0b          	nop
+  16:	0b          	nop
+  17:	0b          	nop
+  18:	0b          	nop
+  19:	0b          	nop
+  1a:	0b          	nop
+  1b:	0b          	nop
+  1c:	0b          	nop
+  1d:	0b          	nop
+  1e:	0b          	nop
+  1f:	0b          	nop
+  20:	0b          	nop
+  21:	0b          	nop
+  22:	0b          	nop
+  23:	0b          	nop
+	...
+
+00000040 <_loadh>:
+  40:	71          	loadsp 4
+  41:	fd          	im -3
+  42:	06          	and
+  43:	08          	load
+  44:	72          	loadsp 8
+  45:	83          	im 3
+  46:	06          	and
+  47:	09          	not
+  48:	81          	im 1
+  49:	05          	add
+  4a:	82          	im 2
+  4b:	05          	add
+  4c:	83          	im 3
+  4d:	2b          	ashiftleft
+  4e:	2a          	lshiftright
+  4f:	83          	im 3
+  50:	ff          	im -1
+  51:	ff          	im -1
+  52:	06          	and
+  53:	52          	storesp 8
+  54:	04          	poppc
+	...
+
+00000060 <_storeh>:
+  60:	71          	loadsp 4
+  61:	fd          	im -3
+  62:	06          	and
+  63:	08          	load
+  64:	83          	im 3
+  65:	ff          	im -1
+  66:	ff          	im -1
+  67:	73          	loadsp 12
+  68:	83          	im 3
+  69:	06          	and
+  6a:	09          	not
+  6b:	81          	im 1
+  6c:	05          	add
+  6d:	82          	im 2
+  6e:	05          	add
+  6f:	83          	im 3
+  70:	2b          	ashiftleft
+  71:	2b          	ashiftleft
+  72:	09          	not
+  73:	06          	and
+  74:	73          	loadsp 12
+  75:	83          	im 3
+  76:	ff          	im -1
+  77:	ff          	im -1
+  78:	0b          	nop
+  79:	0b          	nop
+  7a:	0b          	nop
+  7b:	0b          	nop
+  7c:	83          	im 3
+  7d:	a7          	im 39
+  7e:	04          	poppc
+	...
+
+00000080 <_lessthan>:
+  80:	72          	loadsp 8
+  81:	09          	not
+  82:	81          	im 1
+  83:	05          	add
+  84:	72          	loadsp 8
+  85:	05          	add
+  86:	73          	loadsp 12
+  87:	73          	loadsp 12
+  88:	09          	not
+  89:	06          	and
+  8a:	09          	not
+  8b:	06          	and
+  8c:	73          	loadsp 12
+  8d:	09          	not
+  8e:	73          	loadsp 12
+  8f:	06          	and
+  90:	07          	or
+  91:	0a          	flip
+  92:	81          	im 1
+  93:	06          	and
+  94:	53          	storesp 12
+  95:	51          	storesp 4
+  96:	04          	poppc
+	...
+
+000000a0 <_lessthanorequal>:
+  a0:	72          	loadsp 8
+  a1:	72          	loadsp 8
+  a2:	24          	lessthan
+  a3:	73          	loadsp 12
+  a4:	73          	loadsp 12
+  a5:	2e          	eq
+  a6:	07          	or
+  a7:	53          	storesp 12
+  a8:	51          	storesp 4
+  a9:	04          	poppc
+	...
+
+000000c0 <_ulessthan>:
+  c0:	71          	loadsp 4
+  c1:	73          	loadsp 12
+  c2:	71          	loadsp 4
+  c3:	09          	not
+  c4:	71          	loadsp 4
+  c5:	06          	and
+  c6:	81          	im 1
+  c7:	06          	and
+  c8:	30          	neg
+  c9:	72          	loadsp 8
+  ca:	0a          	flip
+  cb:	10          	addsp 0
+  cc:	0a          	flip
+  cd:	72          	loadsp 8
+  ce:	0a          	flip
+  cf:	10          	addsp 0
+  d0:	0a          	flip
+  d1:	31          	sub
+  d2:	05          	add
+  d3:	0a          	flip
+  d4:	81          	im 1
+  d5:	06          	and
+  d6:	51          	storesp 4
+  d7:	51          	storesp 4
+  d8:	53          	storesp 12
+  d9:	51          	storesp 4
+  da:	04          	poppc
+  db:	00          	breakpoint
+  dc:	00          	breakpoint
+  dd:	00          	breakpoint
+	...
+
+000000e0 <_ulessthanorequal>:
+  e0:	72          	loadsp 8
+  e1:	72          	loadsp 8
+  e2:	26          	ulessthan
+  e3:	73          	loadsp 12
+  e4:	73          	loadsp 12
+  e5:	2e          	eq
+  e6:	07          	or
+  e7:	53          	storesp 12
+  e8:	51          	storesp 4
+  e9:	04          	poppc
+	...
+
+00000100 <_swap>:
+	...
+
+00000120 <_slowmult>:
+ 120:	0b          	nop
+ 121:	0b          	nop
+ 122:	0b          	nop
+ 123:	88          	im 8
+ 124:	bc          	im 60
+ 125:	04          	poppc
+	...
+
+00000140 <_lshiftright>:
+ 140:	72          	loadsp 8
+ 141:	0a          	flip
+ 142:	72          	loadsp 8
+ 143:	2b          	ashiftleft
+ 144:	0a          	flip
+ 145:	53          	storesp 12
+ 146:	51          	storesp 4
+ 147:	04          	poppc
+	...
+
+00000160 <_ashiftleft>:
+ 160:	72          	loadsp 8
+ 161:	72          	loadsp 8
+ 162:	9f          	im 31
+ 163:	06          	and
+ 164:	09          	not
+ 165:	81          	im 1
+ 166:	05          	add
+ 167:	0b          	nop
+ 168:	0b          	nop
+ 169:	0b          	nop
+ 16a:	88          	im 8
+ 16b:	9f          	im 31
+ 16c:	05          	add
+ 16d:	04          	poppc
+	...
+
+00000180 <_ashiftright>:
+ 180:	72          	loadsp 8
+ 181:	72          	loadsp 8
+ 182:	2a          	lshiftright
+ 183:	ff          	im -1
+ 184:	73          	loadsp 12
+ 185:	9f          	im 31
+ 186:	06          	and
+ 187:	2a          	lshiftright
+ 188:	09          	not
+ 189:	74          	loadsp 16
+ 18a:	09          	not
+ 18b:	0a          	flip
+ 18c:	81          	im 1
+ 18d:	06          	and
+ 18e:	ff          	im -1
+ 18f:	05          	add
+ 190:	06          	and
+ 191:	07          	or
+ 192:	53          	storesp 12
+ 193:	51          	storesp 4
+ 194:	04          	poppc
+	...
+
+000001a0 <_call>:
+ 1a0:	71          	loadsp 4
+ 1a1:	71          	loadsp 4
+ 1a2:	53          	storesp 12
+ 1a3:	51          	storesp 4
+ 1a4:	02          	pushsp
+ 1a5:	0d          	popsp
+ 1a6:	04          	poppc
+
+000001a7 <_storehtail>:
+ 1a7:	06          	and
+ 1a8:	73          	loadsp 12
+ 1a9:	83          	im 3
+ 1aa:	06          	and
+ 1ab:	09          	not
+ 1ac:	81          	im 1
+ 1ad:	05          	add
+ 1ae:	82          	im 2
+ 1af:	05          	add
+ 1b0:	83          	im 3
+ 1b1:	2b          	ashiftleft
+ 1b2:	0b          	nop
+ 1b3:	2b          	ashiftleft
+ 1b4:	07          	or
+ 1b5:	72          	loadsp 8
+ 1b6:	fc          	im -4
+ 1b7:	06          	and
+ 1b8:	0c          	store
+ 1b9:	51          	storesp 4
+ 1ba:	51          	storesp 4
+ 1bb:	04          	poppc
+ 1bc:	00          	breakpoint
+ 1bd:	00          	breakpoint
+	...
+
+000001c0 <_eq>:
+ 1c0:	72          	loadsp 8
+ 1c1:	09          	not
+ 1c2:	81          	im 1
+ 1c3:	05          	add
+ 1c4:	72          	loadsp 8
+ 1c5:	05          	add
+ 1c6:	09          	not
+ 1c7:	70          	loadsp 0
+ 1c8:	81          	im 1
+ 1c9:	05          	add
+ 1ca:	09          	not
+ 1cb:	06          	and
+ 1cc:	0a          	flip
+ 1cd:	81          	im 1
+ 1ce:	06          	and
+ 1cf:	53          	storesp 12
+ 1d0:	51          	storesp 4
+ 1d1:	04          	poppc
+	...
+
+000001e0 <_neq>:
+ 1e0:	72          	loadsp 8
+ 1e1:	09          	not
+ 1e2:	81          	im 1
+ 1e3:	05          	add
+ 1e4:	72          	loadsp 8
+ 1e5:	05          	add
+ 1e6:	09          	not
+ 1e7:	70          	loadsp 0
+ 1e8:	81          	im 1
+ 1e9:	05          	add
+ 1ea:	09          	not
+ 1eb:	06          	and
+ 1ec:	0a          	flip
+ 1ed:	09          	not
+ 1ee:	81          	im 1
+ 1ef:	06          	and
+ 1f0:	53          	storesp 12
+ 1f1:	51          	storesp 4
+ 1f2:	04          	poppc
+	...
+
+00000200 <_neg>:
+ 200:	71          	loadsp 4
+ 201:	09          	not
+ 202:	81          	im 1
+ 203:	05          	add
+ 204:	52          	storesp 8
+ 205:	04          	poppc
+	...
+
+00000220 <_sub>:
+ 220:	72          	loadsp 8
+ 221:	72          	loadsp 8
+ 222:	09          	not
+ 223:	81          	im 1
+ 224:	05          	add
+ 225:	05          	add
+ 226:	53          	storesp 12
+ 227:	51          	storesp 4
+ 228:	04          	poppc
+	...
+
+00000240 <_xor>:
+ 240:	72          	loadsp 8
+ 241:	09          	not
+ 242:	72          	loadsp 8
+ 243:	06          	and
+ 244:	73          	loadsp 12
+ 245:	73          	loadsp 12
+ 246:	09          	not
+ 247:	06          	and
+ 248:	07          	or
+ 249:	53          	storesp 12
+ 24a:	51          	storesp 4
+ 24b:	04          	poppc
+	...
+
+00000260 <_loadb>:
+ 260:	71          	loadsp 4
+ 261:	fc          	im -4
+ 262:	06          	and
+ 263:	08          	load
+ 264:	72          	loadsp 8
+ 265:	83          	im 3
+ 266:	06          	and
+ 267:	09          	not
+ 268:	81          	im 1
+ 269:	05          	add
+ 26a:	83          	im 3
+ 26b:	05          	add
+ 26c:	10          	addsp 0
+ 26d:	10          	addsp 0
+ 26e:	10          	addsp 0
+ 26f:	2a          	lshiftright
+ 270:	81          	im 1
+ 271:	ff          	im -1
+ 272:	06          	and
+ 273:	52          	storesp 8
+ 274:	04          	poppc
+	...
+
+00000280 <_storeb>:
+ 280:	71          	loadsp 4
+ 281:	fc          	im -4
+ 282:	06          	and
+ 283:	08          	load
+ 284:	0b          	nop
+ 285:	0b          	nop
+ 286:	0b          	nop
+ 287:	92          	im 18
+ 288:	b8          	im 56
+ 289:	73          	loadsp 12
+ 28a:	83          	im 3
+ 28b:	06          	and
+ 28c:	10          	addsp 0
+ 28d:	10          	addsp 0
+ 28e:	05          	add
+ 28f:	08          	load
+ 290:	06          	and
+ 291:	0b          	nop
+ 292:	0b          	nop
+ 293:	0b          	nop
+ 294:	88          	im 8
+ 295:	a2          	im 34
+ 296:	04          	poppc
+	...
+
+000002a0 <_div>:
+ 2a0:	0b          	nop
+ 2a1:	0b          	nop
+ 2a2:	0b          	nop
+ 2a3:	88          	im 8
+ 2a4:	fe          	im -2
+ 2a5:	04          	poppc
+	...
+
+000002c0 <_mod>:
+ 2c0:	0b          	nop
+ 2c1:	0b          	nop
+ 2c2:	0b          	nop
+ 2c3:	88          	im 8
+ 2c4:	d8          	im -40
+ 2c5:	04          	poppc
+	...
+
+000002e0 <_eqbranch>:
+ 2e0:	72          	loadsp 8
+ 2e1:	09          	not
+ 2e2:	70          	loadsp 0
+ 2e3:	81          	im 1
+ 2e4:	05          	add
+ 2e5:	09          	not
+ 2e6:	06          	and
+ 2e7:	0a          	flip
+ 2e8:	81          	im 1
+ 2e9:	06          	and
+ 2ea:	ff          	im -1
+ 2eb:	05          	add
+ 2ec:	70          	loadsp 0
+ 2ed:	54          	storesp 16
+ 2ee:	71          	loadsp 4
+ 2ef:	06          	and
+ 2f0:	73          	loadsp 12
+ 2f1:	09          	not
+ 2f2:	72          	loadsp 8
+ 2f3:	74          	loadsp 16
+ 2f4:	05          	add
+ 2f5:	ff          	im -1
+ 2f6:	05          	add
+ 2f7:	06          	and
+ 2f8:	07          	or
+ 2f9:	51          	storesp 4
+ 2fa:	51          	storesp 4
+ 2fb:	51          	storesp 4
+ 2fc:	04          	poppc
+ 2fd:	00          	breakpoint
+	...
+
+00000300 <_neqbranch>:
+ 300:	72          	loadsp 8
+ 301:	09          	not
+ 302:	70          	loadsp 0
+ 303:	81          	im 1
+ 304:	05          	add
+ 305:	09          	not
+ 306:	06          	and
+ 307:	0a          	flip
+ 308:	09          	not
+ 309:	81          	im 1
+ 30a:	06          	and
+ 30b:	ff          	im -1
+ 30c:	05          	add
+ 30d:	70          	loadsp 0
+ 30e:	54          	storesp 16
+ 30f:	71          	loadsp 4
+ 310:	06          	and
+ 311:	73          	loadsp 12
+ 312:	09          	not
+ 313:	72          	loadsp 8
+ 314:	74          	loadsp 16
+ 315:	05          	add
+ 316:	ff          	im -1
+ 317:	05          	add
+ 318:	06          	and
+ 319:	07          	or
+ 31a:	51          	storesp 4
+ 31b:	51          	storesp 4
+ 31c:	51          	storesp 4
+ 31d:	04          	poppc
+	...
+
+00000320 <_poppcrel>:
+ 320:	05          	add
+ 321:	ff          	im -1
+ 322:	05          	add
+ 323:	04          	poppc
+	...
+
+00000340 <_config>:
+ 340:	81          	im 1
+ 341:	0b          	nop
+ 342:	92          	im 18
+ 343:	c8          	im -56
+ 344:	0c          	store
+ 345:	51          	storesp 4
+ 346:	04          	poppc
+	...
+
+0000035d <_pushpc>:
+ 35d:	71          	loadsp 4
+ 35e:	81          	im 1
+ 35f:	05          	add
+ 360:	52          	storesp 8
+ 361:	04          	poppc
+	...
+
+0000037d <_syscall_emulate>:
+	...
+
+0000039d <_pushspadd>:
+ 39d:	02          	pushsp
+ 39e:	84          	im 4
+ 39f:	05          	add
+ 3a0:	72          	loadsp 8
+ 3a1:	10          	addsp 0
+ 3a2:	10          	addsp 0
+ 3a3:	05          	add
+ 3a4:	52          	storesp 8
+ 3a5:	04          	poppc
+	...
+
+000003bd <_halfmult>:
+	...
+
+000003dd <_callpcrel>:
+ 3dd:	71          	loadsp 4
+ 3de:	71          	loadsp 4
+ 3df:	05          	add
+ 3e0:	ff          	im -1
+ 3e1:	05          	add
+ 3e2:	71          	loadsp 4
+ 3e3:	53          	storesp 12
+ 3e4:	51          	storesp 4
+ 3e5:	02          	pushsp
+ 3e6:	0d          	popsp
+ 3e7:	04          	poppc
+	...
+Disassembly of section .text:
+
+00000400 <_ashiftleftBegin>:
+ 400:	10          	addsp 0
+ 401:	10          	addsp 0
+ 402:	10          	addsp 0
+ 403:	10          	addsp 0
+ 404:	10          	addsp 0
+ 405:	10          	addsp 0
+ 406:	10          	addsp 0
+ 407:	10          	addsp 0
+ 408:	10          	addsp 0
+ 409:	10          	addsp 0
+ 40a:	10          	addsp 0
+ 40b:	10          	addsp 0
+ 40c:	10          	addsp 0
+ 40d:	10          	addsp 0
+ 40e:	10          	addsp 0
+ 40f:	10          	addsp 0
+ 410:	10          	addsp 0
+ 411:	10          	addsp 0
+ 412:	10          	addsp 0
+ 413:	10          	addsp 0
+ 414:	10          	addsp 0
+ 415:	10          	addsp 0
+ 416:	10          	addsp 0
+ 417:	10          	addsp 0
+ 418:	10          	addsp 0
+ 419:	10          	addsp 0
+ 41a:	10          	addsp 0
+ 41b:	10          	addsp 0
+ 41c:	10          	addsp 0
+ 41d:	10          	addsp 0
+ 41e:	10          	addsp 0
+
+0000041f <_ashiftleftEnd>:
+ 41f:	53          	storesp 12
+ 420:	51          	storesp 4
+ 421:	04          	poppc
+
+00000422 <_storebtail>:
+ 422:	73          	loadsp 12
+ 423:	81          	im 1
+ 424:	ff          	im -1
+ 425:	06          	and
+ 426:	73          	loadsp 12
+ 427:	83          	im 3
+ 428:	06          	and
+ 429:	09          	not
+ 42a:	81          	im 1
+ 42b:	05          	add
+ 42c:	83          	im 3
+ 42d:	05          	add
+ 42e:	10          	addsp 0
+ 42f:	10          	addsp 0
+ 430:	10          	addsp 0
+ 431:	2b          	ashiftleft
+ 432:	07          	or
+ 433:	72          	loadsp 8
+ 434:	fc          	im -4
+ 435:	06          	and
+ 436:	0c          	store
+ 437:	51          	storesp 4
+ 438:	51          	storesp 4
+ 439:	04          	poppc
+
+0000043a <_syscall>:
+ 43a:	3c          	syscall
+ 43b:	04          	poppc
+
+0000043c <_slowmultImpl>:
+ 43c:	72          	loadsp 8
+ 43d:	72          	loadsp 8
+ 43e:	80          	im 0
+ 43f:	72          	loadsp 8
+ 440:	81          	im 1
+ 441:	06          	and
+ 442:	ff          	im -1
+ 443:	05          	add
+ 444:	09          	not
+ 445:	72          	loadsp 8
+ 446:	06          	and
+ 447:	05          	add
+ 448:	71          	loadsp 4
+ 449:	10          	addsp 0
+ 44a:	52          	storesp 8
+ 44b:	72          	loadsp 8
+ 44c:	0a          	flip
+ 44d:	10          	addsp 0
+ 44e:	0a          	flip
+ 44f:	53          	storesp 12
+ 450:	72          	loadsp 8
+ 451:	ed          	im -19
+ 452:	38          	neqbranch
+ 453:	51          	storesp 4
+ 454:	51          	storesp 4
+ 455:	53          	storesp 12
+ 456:	51          	storesp 4
+ 457:	04          	poppc
+
+00000458 <___mod>:
+ 458:	83          	im 3
+ 459:	e0          	im -32
+ 45a:	80          	im 0
+ 45b:	08          	load
+ 45c:	83          	im 3
+ 45d:	e0          	im -32
+ 45e:	84          	im 4
+ 45f:	08          	load
+ 460:	83          	im 3
+ 461:	e0          	im -32
+ 462:	88          	im 8
+ 463:	08          	load
+ 464:	75          	loadsp 20
+ 465:	75          	loadsp 20
+ 466:	8f          	im 15
+ 467:	82          	im 2
+ 468:	2d          	call
+ 469:	50          	storesp 0
+ 46a:	50          	storesp 0
+ 46b:	83          	im 3
+ 46c:	e0          	im -32
+ 46d:	80          	im 0
+ 46e:	08          	load
+ 46f:	56          	storesp 24
+ 470:	83          	im 3
+ 471:	e0          	im -32
+ 472:	88          	im 8
+ 473:	0c          	store
+ 474:	83          	im 3
+ 475:	e0          	im -32
+ 476:	84          	im 4
+ 477:	0c          	store
+ 478:	83          	im 3
+ 479:	e0          	im -32
+ 47a:	80          	im 0
+ 47b:	0c          	store
+ 47c:	51          	storesp 4
+ 47d:	04          	poppc
+
+0000047e <___div>:
+ 47e:	83          	im 3
+ 47f:	e0          	im -32
+ 480:	80          	im 0
+ 481:	08          	load
+ 482:	83          	im 3
+ 483:	e0          	im -32
+ 484:	84          	im 4
+ 485:	08          	load
+ 486:	83          	im 3
+ 487:	e0          	im -32
+ 488:	88          	im 8
+ 489:	08          	load
+ 48a:	75          	loadsp 20
+ 48b:	75          	loadsp 20
+ 48c:	8d          	im 13
+ 48d:	96          	im 22
+ 48e:	2d          	call
+ 48f:	50          	storesp 0
+ 490:	50          	storesp 0
+ 491:	83          	im 3
+ 492:	e0          	im -32
+ 493:	80          	im 0
+ 494:	08          	load
+ 495:	56          	storesp 24
+ 496:	83          	im 3
+ 497:	e0          	im -32
+ 498:	88          	im 8
+ 499:	0c          	store
+ 49a:	83          	im 3
+ 49b:	e0          	im -32
+ 49c:	84          	im 4
+ 49d:	0c          	store
+ 49e:	83          	im 3
+ 49f:	e0          	im -32
+ 4a0:	80          	im 0
+ 4a1:	0c          	store
+ 4a2:	51          	storesp 4
+ 4a3:	04          	poppc
+	...
+
+000004a6 <_boot>:
+ 4a6:	80          	im 0
+ 4a7:	04          	poppc
+
+000004a8 <_break>:
+ 4a8:	89          	im 9
+ 4a9:	a8          	im 40
+ 4aa:	04          	poppc
+
+000004ab <_premain>:
+ 4ab:	89          	im 9
+ 4ac:	a8          	im 40
+ 4ad:	0b          	nop
+ 4ae:	8c          	im 12
+ 4af:	d8          	im -40
+ 4b0:	04          	poppc
+
+000004b1 <wait_us>:
+#include "led.h"
+
+void
+wait_us(int unsigned num)
+{
+ 4b1:	83          	im 3
+ 4b2:	e0          	im -32
+ 4b3:	8c          	im 12
+ 4b4:	08          	load
+ 4b5:	02          	pushsp
+ 4b6:	83          	im 3
+ 4b7:	e0          	im -32
+ 4b8:	8c          	im 12
+ 4b9:	0c          	store
+ 4ba:	fe          	im -2
+ 4bb:	3d          	pushspadd
+ 4bc:	0d          	popsp
+
+000004bd <.LM2>:
+	// 28ish
+	int unsigned cycles = num*28;
+ 4bd:	83          	im 3
+ 4be:	e0          	im -32
+ 4bf:	8c          	im 12
+ 4c0:	08          	load
+ 4c1:	88          	im 8
+ 4c2:	05          	add
+ 4c3:	08          	load
+ 4c4:	70          	loadsp 0
+ 4c5:	70          	loadsp 0
+ 4c6:	83          	im 3
+ 4c7:	2b          	ashiftleft
+ 4c8:	70          	loadsp 0
+ 4c9:	73          	loadsp 12
+ 4ca:	31          	sub
+ 4cb:	70          	loadsp 0
+ 4cc:	82          	im 2
+ 4cd:	2b          	ashiftleft
+ 4ce:	70          	loadsp 0
+ 4cf:	83          	im 3
+ 4d0:	e0          	im -32
+ 4d1:	8c          	im 12
+ 4d2:	08          	load
+ 4d3:	fc          	im -4
+ 4d4:	05          	add
+ 4d5:	0c          	store
+
+000004d6 <.LM3>:
+	*zpu_pause = cycles;
+ 4d6:	92          	im 18
+ 4d7:	d4          	im -44
+ 4d8:	08          	load
+ 4d9:	83          	im 3
+ 4da:	e0          	im -32
+ 4db:	8c          	im 12
+ 4dc:	08          	load
+ 4dd:	fc          	im -4
+ 4de:	05          	add
+ 4df:	08          	load
+ 4e0:	71          	loadsp 4
+ 4e1:	0c          	store
+ 4e2:	51          	storesp 4
+ 4e3:	51          	storesp 4
+ 4e4:	51          	storesp 4
+ 4e5:	51          	storesp 4
+ 4e6:	52          	storesp 8
+ 4e7:	52          	storesp 8
+
+000004e8 <.LM4>:
+}
+ 4e8:	84          	im 4
+ 4e9:	3d          	pushspadd
+ 4ea:	0d          	popsp
+ 4eb:	83          	im 3
+ 4ec:	e0          	im -32
+ 4ed:	8c          	im 12
+ 4ee:	0c          	store
+ 4ef:	04          	poppc
+
+000004f0 <clear_64k_ram>:
+
+void clear_64k_ram()
+{
+ 4f0:	83          	im 3
+ 4f1:	e0          	im -32
+ 4f2:	8c          	im 12
+ 4f3:	08          	load
+ 4f4:	02          	pushsp
+ 4f5:	83          	im 3
+ 4f6:	e0          	im -32
+ 4f7:	8c          	im 12
+ 4f8:	0c          	store
+ 4f9:	ff          	im -1
+ 4fa:	3d          	pushspadd
+ 4fb:	0d          	popsp
+
+000004fc <.LM6>:
+	int i=0;
+ 4fc:	80          	im 0
+ 4fd:	0b          	nop
+ 4fe:	83          	im 3
+ 4ff:	e0          	im -32
+ 500:	8c          	im 12
+ 501:	08          	load
+ 502:	fc          	im -4
+ 503:	05          	add
+ 504:	0c          	store
+
+00000505 <.LM7>:
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+ 505:	92          	im 18
+ 506:	e4          	im -28
+ 507:	08          	load
+ 508:	51          	storesp 4
+ 509:	ff          	im -1
+ 50a:	87          	im 7
+ 50b:	c3          	im -61
+ 50c:	e1          	im -31
+ 50d:	f0          	im -16
+ 50e:	71          	loadsp 4
+ 50f:	0c          	store
+
+00000510 <.LM8>:
+	*zpu_ledg = 0x0;
+ 510:	92          	im 18
+ 511:	e0          	im -32
+ 512:	08          	load
+ 513:	51          	storesp 4
+ 514:	80          	im 0
+ 515:	71          	loadsp 4
+ 516:	0c          	store
+
+00000517 <.LM9>:
+	//wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+ 517:	88          	im 8
+ 518:	80          	im 0
+ 519:	0a          	flip
+ 51a:	0b          	nop
+ 51b:	83          	im 3
+ 51c:	e0          	im -32
+ 51d:	8c          	im 12
+ 51e:	08          	load
+ 51f:	fc          	im -4
+ 520:	05          	add
+ 521:	0c          	store
+
+00000522 <.L3>:
+ 522:	83          	im 3
+ 523:	e0          	im -32
+ 524:	8c          	im 12
+ 525:	08          	load
+ 526:	fc          	im -4
+ 527:	05          	add
+ 528:	08          	load
+ 529:	81          	im 1
+ 52a:	84          	im 4
+ 52b:	80          	im 0
+ 52c:	80          	im 0
+ 52d:	2e          	eq
+ 52e:	9e          	im 30
+ 52f:	38          	neqbranch
+
+00000530 <.LM10>:
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+ 530:	83          	im 3
+ 531:	e0          	im -32
+ 532:	8c          	im 12
+ 533:	08          	load
+ 534:	fc          	im -4
+ 535:	05          	add
+ 536:	08          	load
+ 537:	51          	storesp 4
+ 538:	80          	im 0
+ 539:	71          	loadsp 4
+ 53a:	34          	storeb
+
+0000053b <.LM11>:
+ 53b:	83          	im 3
+ 53c:	e0          	im -32
+ 53d:	8c          	im 12
+ 53e:	08          	load
+ 53f:	fc          	im -4
+ 540:	05          	add
+ 541:	08          	load
+ 542:	81          	im 1
+ 543:	05          	add
+ 544:	83          	im 3
+ 545:	e0          	im -32
+ 546:	8c          	im 12
+ 547:	08          	load
+ 548:	fc          	im -4
+ 549:	05          	add
+ 54a:	0c          	store
+ 54b:	d6          	im -42
+ 54c:	39          	poppcrel
+
+0000054d <.L4>:
+	}
+
+	*zpu_ledr = 0x55555555;
+ 54d:	92          	im 18
+ 54e:	e4          	im -28
+ 54f:	08          	load
+ 550:	51          	storesp 4
+ 551:	85          	im 5
+ 552:	aa          	im 42
+ 553:	d5          	im -43
+ 554:	aa          	im 42
+ 555:	d5          	im -43
+ 556:	71          	loadsp 4
+ 557:	0c          	store
+
+00000558 <.LM13>:
+	*zpu_ledg = 0x55555555;
+ 558:	92          	im 18
+ 559:	e0          	im -32
+ 55a:	08          	load
+ 55b:	51          	storesp 4
+ 55c:	85          	im 5
+ 55d:	aa          	im 42
+ 55e:	d5          	im -43
+ 55f:	aa          	im 42
+ 560:	d5          	im -43
+ 561:	71          	loadsp 4
+ 562:	0c          	store
+
+00000563 <.LM14>:
+
+	for (i=0x800000; i!=0x810000; i+=4)
+ 563:	82          	im 2
+ 564:	80          	im 0
+ 565:	0a          	flip
+ 566:	0b          	nop
+ 567:	83          	im 3
+ 568:	e0          	im -32
+ 569:	8c          	im 12
+ 56a:	08          	load
+ 56b:	fc          	im -4
+ 56c:	05          	add
+ 56d:	0c          	store
+
+0000056e <.L6>:
+ 56e:	83          	im 3
+ 56f:	e0          	im -32
+ 570:	8c          	im 12
+ 571:	08          	load
+ 572:	fc          	im -4
+ 573:	05          	add
+ 574:	08          	load
+ 575:	84          	im 4
+ 576:	84          	im 4
+ 577:	80          	im 0
+ 578:	80          	im 0
+ 579:	2e          	eq
+ 57a:	9e          	im 30
+ 57b:	38          	neqbranch
+
+0000057c <.LM15>:
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+ 57c:	83          	im 3
+ 57d:	e0          	im -32
+ 57e:	8c          	im 12
+ 57f:	08          	load
+ 580:	fc          	im -4
+ 581:	05          	add
+ 582:	08          	load
+ 583:	51          	storesp 4
+ 584:	80          	im 0
+ 585:	71          	loadsp 4
+ 586:	0c          	store
+
+00000587 <.LM16>:
+ 587:	83          	im 3
+ 588:	e0          	im -32
+ 589:	8c          	im 12
+ 58a:	08          	load
+ 58b:	fc          	im -4
+ 58c:	05          	add
+ 58d:	08          	load
+ 58e:	84          	im 4
+ 58f:	05          	add
+ 590:	83          	im 3
+ 591:	e0          	im -32
+ 592:	8c          	im 12
+ 593:	08          	load
+ 594:	fc          	im -4
+ 595:	05          	add
+ 596:	0c          	store
+ 597:	d6          	im -42
+ 598:	39          	poppcrel
+
+00000599 <.L7>:
+	}
+
+	*zpu_ledr = 0;
+ 599:	92          	im 18
+ 59a:	e4          	im -28
+ 59b:	08          	load
+ 59c:	51          	storesp 4
+ 59d:	80          	im 0
+ 59e:	71          	loadsp 4
+ 59f:	0c          	store
+
+000005a0 <.LM18>:
+	*zpu_ledg = 0xf0f0f0f0;
+ 5a0:	92          	im 18
+ 5a1:	e0          	im -32
+ 5a2:	08          	load
+ 5a3:	51          	storesp 4
+ 5a4:	ff          	im -1
+ 5a5:	87          	im 7
+ 5a6:	c3          	im -61
+ 5a7:	e1          	im -31
+ 5a8:	f0          	im -16
+ 5a9:	71          	loadsp 4
+ 5aa:	0c          	store
+
+000005ab <.LM19>:
+	//wait_us(200000);
+	return;
+}
+ 5ab:	83          	im 3
+ 5ac:	3d          	pushspadd
+ 5ad:	0d          	popsp
+ 5ae:	83          	im 3
+ 5af:	e0          	im -32
+ 5b0:	8c          	im 12
+ 5b1:	0c          	store
+ 5b2:	04          	poppc
+
+000005b3 <reset_6502>:
+
+void reset_6502(unsigned int reset_n)
+{
+ 5b3:	83          	im 3
+ 5b4:	e0          	im -32
+ 5b5:	8c          	im 12
+ 5b6:	08          	load
+ 5b7:	02          	pushsp
+ 5b8:	83          	im 3
+ 5b9:	e0          	im -32
+ 5ba:	8c          	im 12
+ 5bb:	0c          	store
+ 5bc:	fe          	im -2
+ 5bd:	3d          	pushspadd
+ 5be:	0d          	popsp
+
+000005bf <.LM21>:
+	int prev = *zpu_config;
+ 5bf:	92          	im 18
+ 5c0:	d0          	im -48
+ 5c1:	08          	load
+ 5c2:	70          	loadsp 0
+ 5c3:	08          	load
+ 5c4:	83          	im 3
+ 5c5:	e0          	im -32
+ 5c6:	8c          	im 12
+ 5c7:	08          	load
+ 5c8:	fc          	im -4
+ 5c9:	05          	add
+ 5ca:	0c          	store
+ 5cb:	51          	storesp 4
+
+000005cc <.LM22>:
+	if (reset_n == 1)
+ 5cc:	83          	im 3
+ 5cd:	e0          	im -32
+ 5ce:	8c          	im 12
+ 5cf:	08          	load
+ 5d0:	88          	im 8
+ 5d1:	05          	add
+ 5d2:	08          	load
+ 5d3:	81          	im 1
+ 5d4:	2e          	eq
+ 5d5:	09          	not
+ 5d6:	81          	im 1
+ 5d7:	06          	and
+ 5d8:	95          	im 21
+ 5d9:	38          	neqbranch
+
+000005da <.LM23>:
+		*zpu_config = prev&~(1<<7);
+ 5da:	92          	im 18
+ 5db:	d0          	im -48
+ 5dc:	08          	load
+ 5dd:	83          	im 3
+ 5de:	e0          	im -32
+ 5df:	8c          	im 12
+ 5e0:	08          	load
+ 5e1:	fc          	im -4
+ 5e2:	05          	add
+ 5e3:	08          	load
+ 5e4:	fe          	im -2
+ 5e5:	ff          	im -1
+ 5e6:	06          	and
+ 5e7:	70          	loadsp 0
+ 5e8:	72          	loadsp 8
+ 5e9:	0c          	store
+ 5ea:	52          	storesp 8
+ 5eb:	52          	storesp 8
+ 5ec:	93          	im 19
+ 5ed:	39          	poppcrel
+
+000005ee <.L10>:
+	else
+		*zpu_config = prev|(1<<7);
+ 5ee:	92          	im 18
+ 5ef:	d0          	im -48
+ 5f0:	08          	load
+ 5f1:	83          	im 3
+ 5f2:	e0          	im -32
+ 5f3:	8c          	im 12
+ 5f4:	08          	load
+ 5f5:	fc          	im -4
+ 5f6:	05          	add
+ 5f7:	08          	load
+ 5f8:	81          	im 1
+ 5f9:	80          	im 0
+ 5fa:	07          	or
+ 5fb:	70          	loadsp 0
+ 5fc:	72          	loadsp 8
+ 5fd:	0c          	store
+ 5fe:	52          	storesp 8
+ 5ff:	52          	storesp 8
+
+00000600 <.L9>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+ 600:	84          	im 4
+ 601:	3d          	pushspadd
+ 602:	0d          	popsp
+ 603:	83          	im 3
+ 604:	e0          	im -32
+ 605:	8c          	im 12
+ 606:	0c          	store
+ 607:	04          	poppc
+
+00000608 <pause_6502>:
+
+void pause_6502(unsigned int pause)
+{
+ 608:	83          	im 3
+ 609:	e0          	im -32
+ 60a:	8c          	im 12
+ 60b:	08          	load
+ 60c:	02          	pushsp
+ 60d:	83          	im 3
+ 60e:	e0          	im -32
+ 60f:	8c          	im 12
+ 610:	0c          	store
+ 611:	fe          	im -2
+ 612:	3d          	pushspadd
+ 613:	0d          	popsp
+
+00000614 <.LM27>:
+	int prev = *zpu_config;
+ 614:	92          	im 18
+ 615:	d0          	im -48
+ 616:	08          	load
+ 617:	70          	loadsp 0
+ 618:	08          	load
+ 619:	83          	im 3
+ 61a:	e0          	im -32
+ 61b:	8c          	im 12
+ 61c:	08          	load
+ 61d:	fc          	im -4
+ 61e:	05          	add
+ 61f:	0c          	store
+ 620:	51          	storesp 4
+
+00000621 <.LM28>:
+	if (pause == 0)
+ 621:	83          	im 3
+ 622:	e0          	im -32
+ 623:	8c          	im 12
+ 624:	08          	load
+ 625:	88          	im 8
+ 626:	05          	add
+ 627:	08          	load
+ 628:	95          	im 21
+ 629:	38          	neqbranch
+
+0000062a <.LM29>:
+		*zpu_config = prev&~(1<<6);
+ 62a:	92          	im 18
+ 62b:	d0          	im -48
+ 62c:	08          	load
+ 62d:	83          	im 3
+ 62e:	e0          	im -32
+ 62f:	8c          	im 12
+ 630:	08          	load
+ 631:	fc          	im -4
+ 632:	05          	add
+ 633:	08          	load
+ 634:	ff          	im -1
+ 635:	bf          	im 63
+ 636:	06          	and
+ 637:	70          	loadsp 0
+ 638:	72          	loadsp 8
+ 639:	0c          	store
+ 63a:	52          	storesp 8
+ 63b:	52          	storesp 8
+ 63c:	93          	im 19
+ 63d:	39          	poppcrel
+
+0000063e <.L13>:
+	else
+		*zpu_config = prev|(1<<6);
+ 63e:	92          	im 18
+ 63f:	d0          	im -48
+ 640:	08          	load
+ 641:	83          	im 3
+ 642:	e0          	im -32
+ 643:	8c          	im 12
+ 644:	08          	load
+ 645:	fc          	im -4
+ 646:	05          	add
+ 647:	08          	load
+ 648:	80          	im 0
+ 649:	c0          	im -64
+ 64a:	07          	or
+ 64b:	70          	loadsp 0
+ 64c:	72          	loadsp 8
+ 64d:	0c          	store
+ 64e:	52          	storesp 8
+ 64f:	52          	storesp 8
+
+00000650 <.L12>:
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+ 650:	84          	im 4
+ 651:	3d          	pushspadd
+ 652:	0d          	popsp
+ 653:	83          	im 3
+ 654:	e0          	im -32
+ 655:	8c          	im 12
+ 656:	0c          	store
+ 657:	04          	poppc
+
+00000658 <main>:
+
+int main(void)
+{
+ 658:	83          	im 3
+ 659:	e0          	im -32
+ 65a:	8c          	im 12
+ 65b:	08          	load
+ 65c:	02          	pushsp
+ 65d:	83          	im 3
+ 65e:	e0          	im -32
+ 65f:	8c          	im 12
+ 660:	0c          	store
+ 661:	fd          	im -3
+ 662:	3d          	pushspadd
+ 663:	0d          	popsp
+
+00000664 <.LM33>:
+	unsigned int i=0;
+ 664:	80          	im 0
+ 665:	0b          	nop
+ 666:	83          	im 3
+ 667:	e0          	im -32
+ 668:	8c          	im 12
+ 669:	08          	load
+ 66a:	fc          	im -4
+ 66b:	05          	add
+ 66c:	0c          	store
+
+0000066d <.LM34>:
+	unsigned char temp = 0;
+ 66d:	80          	im 0
+ 66e:	0b          	nop
+ 66f:	83          	im 3
+ 670:	e0          	im -32
+ 671:	8c          	im 12
+ 672:	08          	load
+ 673:	f8          	im -8
+ 674:	05          	add
+ 675:	34          	storeb
+
+00000676 <.LM35>:
+	pause_6502(1);
+ 676:	81          	im 1
+ 677:	51          	storesp 4
+ 678:	ff          	im -1
+ 679:	8e          	im 14
+ 67a:	3f          	callpcrel
+
+0000067b <.LM36>:
+
+		//wait_us(200000);
+		reset_6502(0);
+ 67b:	80          	im 0
+ 67c:	51          	storesp 4
+ 67d:	fe          	im -2
+ 67e:	b4          	im 52
+ 67f:	3f          	callpcrel
+
+00000680 <.LM37>:
+		*atari_nmien = 0x00;
+ 680:	93          	im 19
+ 681:	b4          	im 52
+ 682:	08          	load
+ 683:	52          	storesp 8
+ 684:	80          	im 0
+ 685:	72          	loadsp 8
+ 686:	34          	storeb
+
+00000687 <.LM38>:
+		clear_64k_ram();
+ 687:	fc          	im -4
+ 688:	e7          	im -25
+ 689:	3f          	callpcrel
+
+0000068a <.LM39>:
+		reset_6502(1);
+ 68a:	81          	im 1
+ 68b:	51          	storesp 4
+ 68c:	fe          	im -2
+ 68d:	a5          	im 37
+ 68e:	3f          	callpcrel
+
+0000068f <.LM40>:
+		pause_6502(0);
+ 68f:	80          	im 0
+ 690:	51          	storesp 4
+ 691:	fe          	im -2
+ 692:	f5          	im -11
+ 693:	3f          	callpcrel
+
+00000694 <.L16>:
+	for(;;);
+ 694:	ff          	im -1
+ 695:	39          	poppcrel
+
+00000696 <__divsi3>:
+ 696:	83          	im 3
+ 697:	e0          	im -32
+ 698:	8c          	im 12
+ 699:	08          	load
+ 69a:	02          	pushsp
+ 69b:	83          	im 3
+ 69c:	e0          	im -32
+ 69d:	8c          	im 12
+ 69e:	0c          	store
+ 69f:	f9          	im -7
+ 6a0:	3d          	pushspadd
+ 6a1:	0d          	popsp
+ 6a2:	80          	im 0
+ 6a3:	0b          	nop
+ 6a4:	83          	im 3
+ 6a5:	e0          	im -32
+ 6a6:	8c          	im 12
+ 6a7:	08          	load
+ 6a8:	fc          	im -4
+ 6a9:	05          	add
+ 6aa:	0c          	store
+ 6ab:	83          	im 3
+ 6ac:	e0          	im -32
+ 6ad:	8c          	im 12
+ 6ae:	08          	load
+ 6af:	88          	im 8
+ 6b0:	05          	add
+ 6b1:	08          	load
+ 6b2:	80          	im 0
+ 6b3:	25          	lessthanorequal
+ 6b4:	b9          	im 57
+ 6b5:	38          	neqbranch
+ 6b6:	83          	im 3
+ 6b7:	e0          	im -32
+ 6b8:	8c          	im 12
+ 6b9:	08          	load
+ 6ba:	88          	im 8
+ 6bb:	05          	add
+ 6bc:	08          	load
+ 6bd:	30          	neg
+ 6be:	83          	im 3
+ 6bf:	e0          	im -32
+ 6c0:	8c          	im 12
+ 6c1:	08          	load
+ 6c2:	88          	im 8
+ 6c3:	05          	add
+ 6c4:	0c          	store
+ 6c5:	80          	im 0
+ 6c6:	0b          	nop
+ 6c7:	83          	im 3
+ 6c8:	e0          	im -32
+ 6c9:	8c          	im 12
+ 6ca:	08          	load
+ 6cb:	f4          	im -12
+ 6cc:	05          	add
+ 6cd:	0c          	store
+ 6ce:	83          	im 3
+ 6cf:	e0          	im -32
+ 6d0:	8c          	im 12
+ 6d1:	08          	load
+ 6d2:	fc          	im -4
+ 6d3:	05          	add
+ 6d4:	08          	load
+ 6d5:	8a          	im 10
+ 6d6:	38          	neqbranch
+ 6d7:	81          	im 1
+ 6d8:	0b          	nop
+ 6d9:	83          	im 3
+ 6da:	e0          	im -32
+ 6db:	8c          	im 12
+ 6dc:	08          	load
+ 6dd:	f4          	im -12
+ 6de:	05          	add
+ 6df:	0c          	store
+
+000006e0 <.L3>:
+ 6e0:	83          	im 3
+ 6e1:	e0          	im -32
+ 6e2:	8c          	im 12
+ 6e3:	08          	load
+ 6e4:	f4          	im -12
+ 6e5:	05          	add
+ 6e6:	08          	load
+ 6e7:	83          	im 3
+ 6e8:	e0          	im -32
+ 6e9:	8c          	im 12
+ 6ea:	08          	load
+ 6eb:	fc          	im -4
+ 6ec:	05          	add
+ 6ed:	0c          	store
+
+000006ee <.L2>:
+ 6ee:	83          	im 3
+ 6ef:	e0          	im -32
+ 6f0:	8c          	im 12
+ 6f1:	08          	load
+ 6f2:	8c          	im 12
+ 6f3:	05          	add
+ 6f4:	08          	load
+ 6f5:	80          	im 0
+ 6f6:	25          	lessthanorequal
+ 6f7:	b9          	im 57
+ 6f8:	38          	neqbranch
+ 6f9:	83          	im 3
+ 6fa:	e0          	im -32
+ 6fb:	8c          	im 12
+ 6fc:	08          	load
+ 6fd:	8c          	im 12
+ 6fe:	05          	add
+ 6ff:	08          	load
+ 700:	30          	neg
+ 701:	83          	im 3
+ 702:	e0          	im -32
+ 703:	8c          	im 12
+ 704:	08          	load
+ 705:	8c          	im 12
+ 706:	05          	add
+ 707:	0c          	store
+ 708:	80          	im 0
+ 709:	0b          	nop
+ 70a:	83          	im 3
+ 70b:	e0          	im -32
+ 70c:	8c          	im 12
+ 70d:	08          	load
+ 70e:	f0          	im -16
+ 70f:	05          	add
+ 710:	0c          	store
+ 711:	83          	im 3
+ 712:	e0          	im -32
+ 713:	8c          	im 12
+ 714:	08          	load
+ 715:	fc          	im -4
+ 716:	05          	add
+ 717:	08          	load
+ 718:	8a          	im 10
+ 719:	38          	neqbranch
+ 71a:	81          	im 1
+ 71b:	0b          	nop
+ 71c:	83          	im 3
+ 71d:	e0          	im -32
+ 71e:	8c          	im 12
+ 71f:	08          	load
+ 720:	f0          	im -16
+ 721:	05          	add
+ 722:	0c          	store
+
+00000723 <.L5>:
+ 723:	83          	im 3
+ 724:	e0          	im -32
+ 725:	8c          	im 12
+ 726:	08          	load
+ 727:	f0          	im -16
+ 728:	05          	add
+ 729:	08          	load
+ 72a:	83          	im 3
+ 72b:	e0          	im -32
+ 72c:	8c          	im 12
+ 72d:	08          	load
+ 72e:	fc          	im -4
+ 72f:	05          	add
+ 730:	0c          	store
+
+00000731 <.L4>:
+ 731:	80          	im 0
+ 732:	53          	storesp 12
+ 733:	83          	im 3
+ 734:	e0          	im -32
+ 735:	8c          	im 12
+ 736:	08          	load
+ 737:	8c          	im 12
+ 738:	05          	add
+ 739:	08          	load
+ 73a:	52          	storesp 8
+ 73b:	83          	im 3
+ 73c:	e0          	im -32
+ 73d:	8c          	im 12
+ 73e:	08          	load
+ 73f:	88          	im 8
+ 740:	05          	add
+ 741:	08          	load
+ 742:	51          	storesp 4
+ 743:	81          	im 1
+ 744:	df          	im -33
+ 745:	3f          	callpcrel
+ 746:	83          	im 3
+ 747:	e0          	im -32
+ 748:	80          	im 0
+ 749:	08          	load
+ 74a:	70          	loadsp 0
+ 74b:	83          	im 3
+ 74c:	e0          	im -32
+ 74d:	8c          	im 12
+ 74e:	08          	load
+ 74f:	f8          	im -8
+ 750:	05          	add
+ 751:	0c          	store
+ 752:	54          	storesp 16
+ 753:	83          	im 3
+ 754:	e0          	im -32
+ 755:	8c          	im 12
+ 756:	08          	load
+ 757:	fc          	im -4
+ 758:	05          	add
+ 759:	08          	load
+ 75a:	80          	im 0
+ 75b:	2e          	eq
+ 75c:	90          	im 16
+ 75d:	38          	neqbranch
+ 75e:	83          	im 3
+ 75f:	e0          	im -32
+ 760:	8c          	im 12
+ 761:	08          	load
+ 762:	f8          	im -8
+ 763:	05          	add
+ 764:	08          	load
+ 765:	30          	neg
+ 766:	83          	im 3
+ 767:	e0          	im -32
+ 768:	8c          	im 12
+ 769:	08          	load
+ 76a:	f8          	im -8
+ 76b:	05          	add
+ 76c:	0c          	store
+
+0000076d <.L6>:
+ 76d:	83          	im 3
+ 76e:	e0          	im -32
+ 76f:	8c          	im 12
+ 770:	08          	load
+ 771:	f8          	im -8
+ 772:	05          	add
+ 773:	08          	load
+ 774:	70          	loadsp 0
+ 775:	83          	im 3
+ 776:	e0          	im -32
+ 777:	80          	im 0
+ 778:	0c          	store
+ 779:	54          	storesp 16
+ 77a:	89          	im 9
+ 77b:	3d          	pushspadd
+ 77c:	0d          	popsp
+ 77d:	83          	im 3
+ 77e:	e0          	im -32
+ 77f:	8c          	im 12
+ 780:	0c          	store
+ 781:	04          	poppc
+
+00000782 <__modsi3>:
+ 782:	83          	im 3
+ 783:	e0          	im -32
+ 784:	8c          	im 12
+ 785:	08          	load
+ 786:	02          	pushsp
+ 787:	83          	im 3
+ 788:	e0          	im -32
+ 789:	8c          	im 12
+ 78a:	0c          	store
+ 78b:	fb          	im -5
+ 78c:	3d          	pushspadd
+ 78d:	0d          	popsp
+ 78e:	80          	im 0
+ 78f:	0b          	nop
+ 790:	83          	im 3
+ 791:	e0          	im -32
+ 792:	8c          	im 12
+ 793:	08          	load
+ 794:	fc          	im -4
+ 795:	05          	add
+ 796:	0c          	store
+ 797:	83          	im 3
+ 798:	e0          	im -32
+ 799:	8c          	im 12
+ 79a:	08          	load
+ 79b:	88          	im 8
+ 79c:	05          	add
+ 79d:	08          	load
+ 79e:	80          	im 0
+ 79f:	25          	lessthanorequal
+ 7a0:	99          	im 25
+ 7a1:	38          	neqbranch
+ 7a2:	83          	im 3
+ 7a3:	e0          	im -32
+ 7a4:	8c          	im 12
+ 7a5:	08          	load
+ 7a6:	88          	im 8
+ 7a7:	05          	add
+ 7a8:	08          	load
+ 7a9:	30          	neg
+ 7aa:	83          	im 3
+ 7ab:	e0          	im -32
+ 7ac:	8c          	im 12
+ 7ad:	08          	load
+ 7ae:	88          	im 8
+ 7af:	05          	add
+ 7b0:	0c          	store
+ 7b1:	81          	im 1
+ 7b2:	0b          	nop
+ 7b3:	83          	im 3
+ 7b4:	e0          	im -32
+ 7b5:	8c          	im 12
+ 7b6:	08          	load
+ 7b7:	fc          	im -4
+ 7b8:	05          	add
+ 7b9:	0c          	store
+
+000007ba <.L8>:
+ 7ba:	83          	im 3
+ 7bb:	e0          	im -32
+ 7bc:	8c          	im 12
+ 7bd:	08          	load
+ 7be:	8c          	im 12
+ 7bf:	05          	add
+ 7c0:	08          	load
+ 7c1:	80          	im 0
+ 7c2:	25          	lessthanorequal
+ 7c3:	90          	im 16
+ 7c4:	38          	neqbranch
+ 7c5:	83          	im 3
+ 7c6:	e0          	im -32
+ 7c7:	8c          	im 12
+ 7c8:	08          	load
+ 7c9:	8c          	im 12
+ 7ca:	05          	add
+ 7cb:	08          	load
+ 7cc:	30          	neg
+ 7cd:	83          	im 3
+ 7ce:	e0          	im -32
+ 7cf:	8c          	im 12
+ 7d0:	08          	load
+ 7d1:	8c          	im 12
+ 7d2:	05          	add
+ 7d3:	0c          	store
+
+000007d4 <.L9>:
+ 7d4:	81          	im 1
+ 7d5:	53          	storesp 12
+ 7d6:	83          	im 3
+ 7d7:	e0          	im -32
+ 7d8:	8c          	im 12
+ 7d9:	08          	load
+ 7da:	8c          	im 12
+ 7db:	05          	add
+ 7dc:	08          	load
+ 7dd:	52          	storesp 8
+ 7de:	83          	im 3
+ 7df:	e0          	im -32
+ 7e0:	8c          	im 12
+ 7e1:	08          	load
+ 7e2:	88          	im 8
+ 7e3:	05          	add
+ 7e4:	08          	load
+ 7e5:	51          	storesp 4
+ 7e6:	bd          	im 61
+ 7e7:	3f          	callpcrel
+ 7e8:	83          	im 3
+ 7e9:	e0          	im -32
+ 7ea:	80          	im 0
+ 7eb:	08          	load
+ 7ec:	70          	loadsp 0
+ 7ed:	83          	im 3
+ 7ee:	e0          	im -32
+ 7ef:	8c          	im 12
+ 7f0:	08          	load
+ 7f1:	f8          	im -8
+ 7f2:	05          	add
+ 7f3:	0c          	store
+ 7f4:	54          	storesp 16
+ 7f5:	83          	im 3
+ 7f6:	e0          	im -32
+ 7f7:	8c          	im 12
+ 7f8:	08          	load
+ 7f9:	fc          	im -4
+ 7fa:	05          	add
+ 7fb:	08          	load
+ 7fc:	80          	im 0
+ 7fd:	2e          	eq
+ 7fe:	90          	im 16
+ 7ff:	38          	neqbranch
+ 800:	83          	im 3
+ 801:	e0          	im -32
+ 802:	8c          	im 12
+ 803:	08          	load
+ 804:	f8          	im -8
+ 805:	05          	add
+ 806:	08          	load
+ 807:	30          	neg
+ 808:	83          	im 3
+ 809:	e0          	im -32
+ 80a:	8c          	im 12
+ 80b:	08          	load
+ 80c:	f8          	im -8
+ 80d:	05          	add
+ 80e:	0c          	store
+
+0000080f <.L10>:
+ 80f:	83          	im 3
+ 810:	e0          	im -32
+ 811:	8c          	im 12
+ 812:	08          	load
+ 813:	f8          	im -8
+ 814:	05          	add
+ 815:	08          	load
+ 816:	70          	loadsp 0
+ 817:	83          	im 3
+ 818:	e0          	im -32
+ 819:	80          	im 0
+ 81a:	0c          	store
+ 81b:	54          	storesp 16
+ 81c:	87          	im 7
+ 81d:	3d          	pushspadd
+ 81e:	0d          	popsp
+ 81f:	83          	im 3
+ 820:	e0          	im -32
+ 821:	8c          	im 12
+ 822:	0c          	store
+ 823:	04          	poppc
+
+00000824 <udivmodsi4>:
+ 824:	83          	im 3
+ 825:	e0          	im -32
+ 826:	8c          	im 12
+ 827:	08          	load
+ 828:	02          	pushsp
+ 829:	83          	im 3
+ 82a:	e0          	im -32
+ 82b:	8c          	im 12
+ 82c:	0c          	store
+ 82d:	fd          	im -3
+ 82e:	3d          	pushspadd
+ 82f:	0d          	popsp
+ 830:	81          	im 1
+ 831:	0b          	nop
+ 832:	83          	im 3
+ 833:	e0          	im -32
+ 834:	8c          	im 12
+ 835:	08          	load
+ 836:	fc          	im -4
+ 837:	05          	add
+ 838:	0c          	store
+ 839:	80          	im 0
+ 83a:	0b          	nop
+ 83b:	83          	im 3
+ 83c:	e0          	im -32
+ 83d:	8c          	im 12
+ 83e:	08          	load
+ 83f:	f8          	im -8
+ 840:	05          	add
+ 841:	0c          	store
+
+00000842 <.L2>:
+ 842:	83          	im 3
+ 843:	e0          	im -32
+ 844:	8c          	im 12
+ 845:	08          	load
+ 846:	8c          	im 12
+ 847:	05          	add
+ 848:	08          	load
+ 849:	83          	im 3
+ 84a:	e0          	im -32
+ 84b:	8c          	im 12
+ 84c:	08          	load
+ 84d:	88          	im 8
+ 84e:	05          	add
+ 84f:	08          	load
+ 850:	27          	ulessthanorequal
+ 851:	b9          	im 57
+ 852:	38          	neqbranch
+ 853:	83          	im 3
+ 854:	e0          	im -32
+ 855:	8c          	im 12
+ 856:	08          	load
+ 857:	fc          	im -4
+ 858:	05          	add
+ 859:	08          	load
+ 85a:	80          	im 0
+ 85b:	2e          	eq
+ 85c:	ae          	im 46
+ 85d:	38          	neqbranch
+ 85e:	80          	im 0
+ 85f:	0b          	nop
+ 860:	83          	im 3
+ 861:	e0          	im -32
+ 862:	8c          	im 12
+ 863:	08          	load
+ 864:	8c          	im 12
+ 865:	05          	add
+ 866:	08          	load
+ 867:	24          	lessthan
+ 868:	a2          	im 34
+ 869:	38          	neqbranch
+ 86a:	83          	im 3
+ 86b:	e0          	im -32
+ 86c:	8c          	im 12
+ 86d:	08          	load
+ 86e:	8c          	im 12
+ 86f:	05          	add
+ 870:	08          	load
+ 871:	10          	addsp 0
+ 872:	83          	im 3
+ 873:	e0          	im -32
+ 874:	8c          	im 12
+ 875:	08          	load
+ 876:	8c          	im 12
+ 877:	05          	add
+ 878:	0c          	store
+ 879:	83          	im 3
+ 87a:	e0          	im -32
+ 87b:	8c          	im 12
+ 87c:	08          	load
+ 87d:	fc          	im -4
+ 87e:	05          	add
+ 87f:	08          	load
+ 880:	10          	addsp 0
+ 881:	83          	im 3
+ 882:	e0          	im -32
+ 883:	8c          	im 12
+ 884:	08          	load
+ 885:	fc          	im -4
+ 886:	05          	add
+ 887:	0c          	store
+ 888:	ff          	im -1
+ 889:	b8          	im 56
+ 88a:	39          	poppcrel
+
+0000088b <.L4>:
+ 88b:	83          	im 3
+ 88c:	e0          	im -32
+ 88d:	8c          	im 12
+ 88e:	08          	load
+ 88f:	fc          	im -4
+ 890:	05          	add
+ 891:	08          	load
+ 892:	80          	im 0
+ 893:	2e          	eq
+ 894:	80          	im 0
+ 895:	e1          	im -31
+ 896:	38          	neqbranch
+ 897:	83          	im 3
+ 898:	e0          	im -32
+ 899:	8c          	im 12
+ 89a:	08          	load
+ 89b:	8c          	im 12
+ 89c:	05          	add
+ 89d:	08          	load
+ 89e:	83          	im 3
+ 89f:	e0          	im -32
+ 8a0:	8c          	im 12
+ 8a1:	08          	load
+ 8a2:	88          	im 8
+ 8a3:	05          	add
+ 8a4:	08          	load
+ 8a5:	26          	ulessthan
+ 8a6:	ad          	im 45
+ 8a7:	38          	neqbranch
+ 8a8:	83          	im 3
+ 8a9:	e0          	im -32
+ 8aa:	8c          	im 12
+ 8ab:	08          	load
+ 8ac:	88          	im 8
+ 8ad:	05          	add
+ 8ae:	08          	load
+ 8af:	83          	im 3
+ 8b0:	e0          	im -32
+ 8b1:	8c          	im 12
+ 8b2:	08          	load
+ 8b3:	8c          	im 12
+ 8b4:	05          	add
+ 8b5:	08          	load
+ 8b6:	31          	sub
+ 8b7:	83          	im 3
+ 8b8:	e0          	im -32
+ 8b9:	8c          	im 12
+ 8ba:	08          	load
+ 8bb:	88          	im 8
+ 8bc:	05          	add
+ 8bd:	0c          	store
+ 8be:	83          	im 3
+ 8bf:	e0          	im -32
+ 8c0:	8c          	im 12
+ 8c1:	08          	load
+ 8c2:	f8          	im -8
+ 8c3:	05          	add
+ 8c4:	08          	load
+ 8c5:	83          	im 3
+ 8c6:	e0          	im -32
+ 8c7:	8c          	im 12
+ 8c8:	08          	load
+ 8c9:	fc          	im -4
+ 8ca:	05          	add
+ 8cb:	08          	load
+ 8cc:	07          	or
+ 8cd:	83          	im 3
+ 8ce:	e0          	im -32
+ 8cf:	8c          	im 12
+ 8d0:	08          	load
+ 8d1:	f8          	im -8
+ 8d2:	05          	add
+ 8d3:	0c          	store
+
+000008d4 <.L6>:
+ 8d4:	83          	im 3
+ 8d5:	e0          	im -32
+ 8d6:	8c          	im 12
+ 8d7:	08          	load
+ 8d8:	fc          	im -4
+ 8d9:	05          	add
+ 8da:	08          	load
+ 8db:	81          	im 1
+ 8dc:	2a          	lshiftright
+ 8dd:	83          	im 3
+ 8de:	e0          	im -32
+ 8df:	8c          	im 12
+ 8e0:	08          	load
+ 8e1:	fc          	im -4
+ 8e2:	05          	add
+ 8e3:	0c          	store
+ 8e4:	83          	im 3
+ 8e5:	e0          	im -32
+ 8e6:	8c          	im 12
+ 8e7:	08          	load
+ 8e8:	8c          	im 12
+ 8e9:	05          	add
+ 8ea:	08          	load
+ 8eb:	81          	im 1
+ 8ec:	2a          	lshiftright
+ 8ed:	83          	im 3
+ 8ee:	e0          	im -32
+ 8ef:	8c          	im 12
+ 8f0:	08          	load
+ 8f1:	8c          	im 12
+ 8f2:	05          	add
+ 8f3:	0c          	store
+ 8f4:	ff          	im -1
+ 8f5:	95          	im 21
+ 8f6:	39          	poppcrel
+
+000008f7 <.L5>:
+ 8f7:	83          	im 3
+ 8f8:	e0          	im -32
+ 8f9:	8c          	im 12
+ 8fa:	08          	load
+ 8fb:	90          	im 16
+ 8fc:	05          	add
+ 8fd:	08          	load
+ 8fe:	80          	im 0
+ 8ff:	2e          	eq
+ 900:	93          	im 19
+ 901:	38          	neqbranch
+ 902:	83          	im 3
+ 903:	e0          	im -32
+ 904:	8c          	im 12
+ 905:	08          	load
+ 906:	88          	im 8
+ 907:	05          	add
+ 908:	08          	load
+ 909:	70          	loadsp 0
+ 90a:	83          	im 3
+ 90b:	e0          	im -32
+ 90c:	8c          	im 12
+ 90d:	08          	load
+ 90e:	f4          	im -12
+ 90f:	05          	add
+ 910:	0c          	store
+ 911:	51          	storesp 4
+ 912:	91          	im 17
+ 913:	39          	poppcrel
+
+00000914 <.L7>:
+ 914:	83          	im 3
+ 915:	e0          	im -32
+ 916:	8c          	im 12
+ 917:	08          	load
+ 918:	f8          	im -8
+ 919:	05          	add
+ 91a:	08          	load
+ 91b:	70          	loadsp 0
+ 91c:	83          	im 3
+ 91d:	e0          	im -32
+ 91e:	8c          	im 12
+ 91f:	08          	load
+ 920:	f4          	im -12
+ 921:	05          	add
+ 922:	0c          	store
+ 923:	51          	storesp 4
+
+00000924 <.L1>:
+ 924:	83          	im 3
+ 925:	e0          	im -32
+ 926:	8c          	im 12
+ 927:	08          	load
+ 928:	f4          	im -12
+ 929:	05          	add
+ 92a:	08          	load
+ 92b:	83          	im 3
+ 92c:	e0          	im -32
+ 92d:	80          	im 0
+ 92e:	0c          	store
+ 92f:	85          	im 5
+ 930:	3d          	pushspadd
+ 931:	0d          	popsp
+ 932:	83          	im 3
+ 933:	e0          	im -32
+ 934:	8c          	im 12
+ 935:	0c          	store
+ 936:	04          	poppc
+Disassembly of section .rodata:
+
+00000938 <_mask>:
+ 938:	00          	breakpoint
+ 939:	ff          	im -1
+ 93a:	ff          	im -1
+ 93b:	ff          	im -1
+ 93c:	ff          	im -1
+ 93d:	00          	breakpoint
+ 93e:	ff          	im -1
+ 93f:	ff          	im -1
+ 940:	ff          	im -1
+ 941:	ff          	im -1
+ 942:	00          	breakpoint
+ 943:	ff          	im -1
+ 944:	ff          	im -1
+ 945:	ff          	im -1
+ 946:	ff          	im -1
+	...
+Disassembly of section .data:
+
+00000948 <_data>:
+ 948:	00          	breakpoint
+ 949:	00          	breakpoint
+	...
+
+0000094c <_cpu_config>:
+ 94c:	00          	breakpoint
+ 94d:	00          	breakpoint
+	...
+
+00000950 <zpu_config>:
+ 950:	00          	breakpoint
+ 951:	04          	poppc
+	...
+
+00000954 <zpu_pause>:
+ 954:	00          	breakpoint
+ 955:	04          	poppc
+ 956:	00          	breakpoint
+ 957:	04          	poppc
+
+00000958 <zpu_switches>:
+ 958:	00          	breakpoint
+ 959:	04          	poppc
+ 95a:	00          	breakpoint
+ 95b:	08          	load
+
+0000095c <zpu_key>:
+ 95c:	00          	breakpoint
+ 95d:	04          	poppc
+ 95e:	00          	breakpoint
+ 95f:	0c          	store
+
+00000960 <zpu_ledg>:
+ 960:	00          	breakpoint
+ 961:	04          	poppc
+ 962:	00          	breakpoint
+ 963:	10          	addsp 0
+
+00000964 <zpu_ledr>:
+ 964:	00          	breakpoint
+ 965:	04          	poppc
+ 966:	00          	breakpoint
+ 967:	14          	addsp 16
+
+00000968 <zpu_spi_data>:
+ 968:	00          	breakpoint
+ 969:	04          	poppc
+ 96a:	00          	breakpoint
+ 96b:	18          	addsp 32
+
+0000096c <zpu_spi_state>:
+ 96c:	00          	breakpoint
+ 96d:	04          	poppc
+ 96e:	00          	breakpoint
+ 96f:	1c          	addsp 48
+
+00000970 <zpu_sio>:
+ 970:	00          	breakpoint
+ 971:	04          	poppc
+ 972:	00          	breakpoint
+ 973:	20          	.byte 32
+
+00000974 <zpu_board>:
+ 974:	00          	breakpoint
+ 975:	04          	poppc
+ 976:	00          	breakpoint
+ 977:	24          	lessthan
+
+00000978 <zpu_hex>:
+ 978:	00          	breakpoint
+ 979:	04          	poppc
+ 97a:	00          	breakpoint
+ 97b:	28          	swap
+
+0000097c <zpu_sector>:
+ 97c:	00          	breakpoint
+ 97d:	04          	poppc
+ 97e:	00          	breakpoint
+ 97f:	2c          	ashiftright
+
+00000980 <zpu_pokey_audf0>:
+ 980:	00          	breakpoint
+ 981:	04          	poppc
+ 982:	00          	breakpoint
+ 983:	40          	storesp 64
+
+00000984 <zpu_pokey_audc0>:
+ 984:	00          	breakpoint
+ 985:	04          	poppc
+ 986:	00          	breakpoint
+ 987:	44          	storesp 80
+
+00000988 <zpu_pokey_audf1>:
+ 988:	00          	breakpoint
+ 989:	04          	poppc
+ 98a:	00          	breakpoint
+ 98b:	48          	storesp 96
+
+0000098c <zpu_pokey_audc1>:
+ 98c:	00          	breakpoint
+ 98d:	04          	poppc
+ 98e:	00          	breakpoint
+ 98f:	4c          	storesp 112
+
+00000990 <zpu_pokey_audf2>:
+ 990:	00          	breakpoint
+ 991:	04          	poppc
+ 992:	00          	breakpoint
+ 993:	50          	storesp 0
+
+00000994 <zpu_pokey_audc2>:
+ 994:	00          	breakpoint
+ 995:	04          	poppc
+ 996:	00          	breakpoint
+ 997:	54          	storesp 16
+
+00000998 <zpu_pokey_audf3>:
+ 998:	00          	breakpoint
+ 999:	04          	poppc
+ 99a:	00          	breakpoint
+ 99b:	58          	storesp 32
+
+0000099c <zpu_pokey_audc3>:
+ 99c:	00          	breakpoint
+ 99d:	04          	poppc
+ 99e:	00          	breakpoint
+ 99f:	5c          	storesp 48
+
+000009a0 <zpu_pokey_audctl>:
+ 9a0:	00          	breakpoint
+ 9a1:	04          	poppc
+ 9a2:	00          	breakpoint
+ 9a3:	60          	loadsp 64
+
+000009a4 <zpu_pokey_skrest>:
+ 9a4:	00          	breakpoint
+ 9a5:	04          	poppc
+ 9a6:	00          	breakpoint
+ 9a7:	68          	loadsp 96
+
+000009a8 <zpu_pokey_serout>:
+ 9a8:	00          	breakpoint
+ 9a9:	04          	poppc
+ 9aa:	00          	breakpoint
+ 9ab:	74          	loadsp 16
+
+000009ac <zpu_pokey_irqen>:
+ 9ac:	00          	breakpoint
+ 9ad:	04          	poppc
+ 9ae:	00          	breakpoint
+ 9af:	78          	loadsp 32
+
+000009b0 <zpu_pokey_skctl>:
+ 9b0:	00          	breakpoint
+ 9b1:	04          	poppc
+ 9b2:	00          	breakpoint
+ 9b3:	7c          	loadsp 48
+
+000009b4 <atari_nmien>:
+ 9b4:	00          	breakpoint
+ 9b5:	01          	.byte 1
+ 9b6:	d4          	im -44
+ 9b7:	0e          	.byte 14
+
+000009b8 <atari_dlistl>:
+ 9b8:	00          	breakpoint
+ 9b9:	01          	.byte 1
+ 9ba:	d4          	im -44
+ 9bb:	02          	pushsp
+
+000009bc <atari_dlisth>:
+ 9bc:	00          	breakpoint
+ 9bd:	01          	.byte 1
+ 9be:	d4          	im -44
+ 9bf:	03          	.byte 3
+
+000009c0 <atari_colbk>:
+ 9c0:	00          	breakpoint
+ 9c1:	01          	.byte 1
+ 9c2:	d0          	im -48
+ 9c3:	1a          	addsp 40
+
+000009c4 <atari_colpf1>:
+ 9c4:	00          	breakpoint
+ 9c5:	01          	.byte 1
+ 9c6:	d0          	im -48
+ 9c7:	17          	addsp 28
+
+000009c8 <atari_colpf2>:
+ 9c8:	00          	breakpoint
+ 9c9:	01          	.byte 1
+ 9ca:	d0          	im -48
+ 9cb:	18          	addsp 32
+
+000009cc <atari_prior>:
+ 9cc:	00          	breakpoint
+ 9cd:	01          	.byte 1
+ 9ce:	d0          	im -48
+ 9cf:	1b          	addsp 44
+
+000009d0 <atari_random>:
+ 9d0:	00          	breakpoint
+ 9d1:	01          	.byte 1
+ 9d2:	d2          	im -46
+ 9d3:	0a          	flip
+
+000009d4 <atari_porta>:
+ 9d4:	00          	breakpoint
+ 9d5:	01          	.byte 1
+ 9d6:	d3          	im -45
+	...
+
+000009d8 <atari_portb>:
+ 9d8:	00          	breakpoint
+ 9d9:	01          	.byte 1
+ 9da:	d3          	im -45
+ 9db:	01          	.byte 1
+
+000009dc <atari_trig0>:
+ 9dc:	00          	breakpoint
+ 9dd:	01          	.byte 1
+ 9de:	d0          	im -48
+ 9df:	10          	addsp 0
+
+000009e0 <atari_chbase>:
+ 9e0:	00          	breakpoint
+ 9e1:	01          	.byte 1
+ 9e2:	d4          	im -44
+ 9e3:	09          	not
+
+000009e4 <atari_chactl>:
+ 9e4:	00          	breakpoint
+ 9e5:	01          	.byte 1
+ 9e6:	d4          	im -44
+ 9e7:	01          	.byte 1
+
+000009e8 <atari_dmactl>:
+ 9e8:	00          	breakpoint
+ 9e9:	01          	.byte 1
+ 9ea:	d4          	im -44
+	...
+
+000009ec <atari_skctl>:
+ 9ec:	00          	breakpoint
+ 9ed:	01          	.byte 1
+ 9ee:	d2          	im -46
+ 9ef:	0f          	.byte 15
+Disassembly of section .bss:
+
+0000f000 <__bss_start>:
+	...
+Disassembly of section .debug_abbrev:
+
+00000000 <.Ldebug_abbrev0>:
+   0:	01          	.byte 1
+   1:	11          	addsp 4
+   2:	01          	.byte 1
+   3:	10          	addsp 0
+   4:	06          	and
+   5:	12          	addsp 8
+   6:	01          	.byte 1
+   7:	11          	addsp 4
+   8:	01          	.byte 1
+   9:	25          	lessthanorequal
+   a:	08          	load
+   b:	13          	addsp 12
+   c:	0b          	nop
+   d:	03          	.byte 3
+   e:	08          	load
+   f:	1b          	addsp 44
+  10:	08          	load
+  11:	00          	breakpoint
+  12:	00          	breakpoint
+  13:	02          	pushsp
+  14:	2e          	eq
+  15:	01          	.byte 1
+  16:	01          	.byte 1
+  17:	13          	addsp 12
+  18:	3f          	callpcrel
+  19:	0c          	store
+  1a:	03          	.byte 3
+  1b:	08          	load
+  1c:	3a          	config
+  1d:	0b          	nop
+  1e:	3b          	pushpc
+  1f:	0b          	nop
+  20:	27          	ulessthanorequal
+  21:	0c          	store
+  22:	11          	addsp 4
+  23:	01          	.byte 1
+  24:	12          	addsp 8
+  25:	01          	.byte 1
+  26:	40          	storesp 64
+  27:	0a          	flip
+  28:	00          	breakpoint
+  29:	00          	breakpoint
+  2a:	03          	.byte 3
+  2b:	05          	add
+  2c:	00          	breakpoint
+  2d:	03          	.byte 3
+  2e:	08          	load
+  2f:	3a          	config
+  30:	0b          	nop
+  31:	3b          	pushpc
+  32:	0b          	nop
+  33:	49          	storesp 100
+  34:	13          	addsp 12
+  35:	02          	pushsp
+  36:	0a          	flip
+  37:	00          	breakpoint
+  38:	00          	breakpoint
+  39:	04          	poppc
+  3a:	34          	storeb
+  3b:	00          	breakpoint
+  3c:	03          	.byte 3
+  3d:	08          	load
+  3e:	3a          	config
+  3f:	0b          	nop
+  40:	3b          	pushpc
+  41:	0b          	nop
+  42:	49          	storesp 100
+  43:	13          	addsp 12
+  44:	02          	pushsp
+  45:	0a          	flip
+  46:	00          	breakpoint
+  47:	00          	breakpoint
+  48:	05          	add
+  49:	24          	lessthan
+  4a:	00          	breakpoint
+  4b:	03          	.byte 3
+  4c:	08          	load
+  4d:	0b          	nop
+  4e:	0b          	nop
+  4f:	3e          	halfmult
+  50:	0b          	nop
+  51:	00          	breakpoint
+  52:	00          	breakpoint
+  53:	06          	and
+  54:	2e          	eq
+  55:	01          	.byte 1
+  56:	01          	.byte 1
+  57:	13          	addsp 12
+  58:	3f          	callpcrel
+  59:	0c          	store
+  5a:	03          	.byte 3
+  5b:	08          	load
+  5c:	3a          	config
+  5d:	0b          	nop
+  5e:	3b          	pushpc
+  5f:	0b          	nop
+  60:	11          	addsp 4
+  61:	01          	.byte 1
+  62:	12          	addsp 8
+  63:	01          	.byte 1
+  64:	40          	storesp 64
+  65:	0a          	flip
+  66:	00          	breakpoint
+  67:	00          	breakpoint
+  68:	07          	or
+  69:	2e          	eq
+  6a:	01          	.byte 1
+  6b:	01          	.byte 1
+  6c:	13          	addsp 12
+  6d:	3f          	callpcrel
+  6e:	0c          	store
+  6f:	03          	.byte 3
+  70:	08          	load
+  71:	3a          	config
+  72:	0b          	nop
+  73:	3b          	pushpc
+  74:	0b          	nop
+  75:	27          	ulessthanorequal
+  76:	0c          	store
+  77:	49          	storesp 100
+  78:	13          	addsp 12
+  79:	11          	addsp 4
+  7a:	01          	.byte 1
+  7b:	12          	addsp 8
+  7c:	01          	.byte 1
+  7d:	40          	storesp 64
+  7e:	0a          	flip
+  7f:	00          	breakpoint
+  80:	00          	breakpoint
+  81:	08          	load
+  82:	34          	storeb
+  83:	00          	breakpoint
+  84:	03          	.byte 3
+  85:	08          	load
+  86:	3a          	config
+  87:	0b          	nop
+  88:	3b          	pushpc
+  89:	0b          	nop
+  8a:	49          	storesp 100
+  8b:	13          	addsp 12
+  8c:	3f          	callpcrel
+  8d:	0c          	store
+  8e:	3c          	syscall
+  8f:	0c          	store
+  90:	00          	breakpoint
+  91:	00          	breakpoint
+  92:	09          	not
+  93:	0f          	.byte 15
+  94:	00          	breakpoint
+  95:	0b          	nop
+  96:	0b          	nop
+  97:	49          	storesp 100
+  98:	13          	addsp 12
+  99:	00          	breakpoint
+  9a:	00          	breakpoint
+  9b:	0a          	flip
+  9c:	35          	div
+  9d:	00          	breakpoint
+  9e:	49          	storesp 100
+  9f:	13          	addsp 12
+  a0:	00          	breakpoint
+	...
+
+000000a3 <.Ldebug_abbrev0>:
+  a3:	01          	.byte 1
+  a4:	11          	addsp 4
+  a5:	01          	.byte 1
+  a6:	10          	addsp 0
+  a7:	06          	and
+  a8:	12          	addsp 8
+  a9:	01          	.byte 1
+  aa:	11          	addsp 4
+  ab:	01          	.byte 1
+  ac:	25          	lessthanorequal
+  ad:	08          	load
+  ae:	13          	addsp 12
+  af:	0b          	nop
+  b0:	03          	.byte 3
+  b1:	08          	load
+  b2:	1b          	addsp 44
+  b3:	08          	load
+  b4:	00          	breakpoint
+  b5:	00          	breakpoint
+  b6:	02          	pushsp
+  b7:	34          	storeb
+  b8:	00          	breakpoint
+  b9:	03          	.byte 3
+  ba:	08          	load
+  bb:	3a          	config
+  bc:	0b          	nop
+  bd:	3b          	pushpc
+  be:	0b          	nop
+  bf:	49          	storesp 100
+  c0:	13          	addsp 12
+  c1:	3f          	callpcrel
+  c2:	0c          	store
+  c3:	02          	pushsp
+  c4:	0a          	flip
+  c5:	00          	breakpoint
+  c6:	00          	breakpoint
+  c7:	03          	.byte 3
+  c8:	0f          	.byte 15
+  c9:	00          	breakpoint
+  ca:	0b          	nop
+  cb:	0b          	nop
+  cc:	49          	storesp 100
+  cd:	13          	addsp 12
+  ce:	00          	breakpoint
+  cf:	00          	breakpoint
+  d0:	04          	poppc
+  d1:	35          	div
+  d2:	00          	breakpoint
+  d3:	49          	storesp 100
+  d4:	13          	addsp 12
+  d5:	00          	breakpoint
+  d6:	00          	breakpoint
+  d7:	05          	add
+  d8:	24          	lessthan
+  d9:	00          	breakpoint
+  da:	03          	.byte 3
+  db:	08          	load
+  dc:	0b          	nop
+  dd:	0b          	nop
+  de:	3e          	halfmult
+  df:	0b          	nop
+  e0:	00          	breakpoint
+	...
+Disassembly of section .debug_info:
+
+00000000 <.Ldebug_info0>:
+   0:	00          	breakpoint
+   1:	00          	breakpoint
+   2:	02          	pushsp
+   3:	18          	addsp 32
+   4:	00          	breakpoint
+   5:	02          	pushsp
+   6:	00          	breakpoint
+   7:	00          	breakpoint
+   8:	00          	breakpoint
+   9:	00          	breakpoint
+   a:	04          	poppc
+   b:	01          	.byte 1
+   c:	00          	breakpoint
+   d:	00          	breakpoint
+   e:	00          	breakpoint
+   f:	00          	breakpoint
+  10:	00          	breakpoint
+  11:	00          	breakpoint
+  12:	06          	and
+  13:	96          	im 22
+  14:	00          	breakpoint
+  15:	00          	breakpoint
+  16:	04          	poppc
+  17:	b1          	im 49
+  18:	47          	storesp 92
+  19:	4e          	storesp 120
+  1a:	55          	storesp 20
+  1b:	20          	.byte 32
+  1c:	43          	storesp 76
+  1d:	20          	.byte 32
+  1e:	33          	loadb
+  1f:	2e          	eq
+  20:	34          	storeb
+  21:	2e          	eq
+  22:	32          	xor
+  23:	00          	breakpoint
+  24:	01          	.byte 1
+  25:	6d          	loadsp 116
+  26:	61          	loadsp 68
+  27:	69          	loadsp 100
+  28:	6e          	loadsp 120
+  29:	2e          	eq
+  2a:	63          	loadsp 76
+  2b:	00          	breakpoint
+  2c:	2f          	neq
+  2d:	68          	loadsp 96
+  2e:	6f          	loadsp 124
+  2f:	6d          	loadsp 116
+  30:	65          	loadsp 84
+  31:	2f          	neq
+  32:	6d          	loadsp 116
+  33:	61          	loadsp 68
+  34:	72          	loadsp 8
+  35:	6b          	loadsp 108
+  36:	77          	loadsp 28
+  37:	2f          	neq
+  38:	61          	loadsp 68
+  39:	6c          	loadsp 112
+  3a:	74          	loadsp 16
+  3b:	65          	loadsp 84
+  3c:	72          	loadsp 8
+  3d:	61          	loadsp 68
+  3e:	2f          	neq
+  3f:	61          	loadsp 68
+  40:	74          	loadsp 16
+  41:	61          	loadsp 68
+  42:	72          	loadsp 8
+  43:	69          	loadsp 100
+  44:	5f          	storesp 60
+  45:	78          	loadsp 32
+  46:	65          	loadsp 84
+  47:	5f          	storesp 60
+  48:	66          	loadsp 88
+  49:	70          	loadsp 0
+  4a:	67          	loadsp 92
+  4b:	61          	loadsp 68
+  4c:	2f          	neq
+  4d:	7a          	loadsp 40
+  4e:	70          	loadsp 0
+  4f:	75          	loadsp 20
+  50:	2f          	neq
+  51:	6c          	loadsp 112
+  52:	65          	loadsp 84
+  53:	64          	loadsp 80
+  54:	73          	loadsp 12
+  55:	5f          	storesp 60
+  56:	6e          	loadsp 120
+  57:	6f          	loadsp 124
+  58:	73          	loadsp 12
+  59:	64          	loadsp 80
+  5a:	72          	loadsp 8
+  5b:	69          	loadsp 100
+  5c:	76          	loadsp 24
+  5d:	65          	loadsp 84
+  5e:	00          	breakpoint
+  5f:	02          	pushsp
+  60:	00          	breakpoint
+  61:	00          	breakpoint
+  62:	00          	breakpoint
+  63:	9a          	im 26
+  64:	01          	.byte 1
+  65:	77          	loadsp 28
+  66:	61          	loadsp 68
+  67:	69          	loadsp 100
+  68:	74          	loadsp 16
+  69:	5f          	storesp 60
+  6a:	75          	loadsp 20
+  6b:	73          	loadsp 12
+  6c:	00          	breakpoint
+  6d:	01          	.byte 1
+  6e:	06          	and
+  6f:	01          	.byte 1
+  70:	00          	breakpoint
+  71:	00          	breakpoint
+  72:	04          	poppc
+  73:	b1          	im 49
+  74:	00          	breakpoint
+  75:	00          	breakpoint
+  76:	04          	poppc
+  77:	f0          	im -16
+  78:	01          	.byte 1
+  79:	53          	storesp 12
+  7a:	03          	.byte 3
+  7b:	6e          	loadsp 120
+  7c:	75          	loadsp 20
+  7d:	6d          	loadsp 116
+  7e:	00          	breakpoint
+  7f:	01          	.byte 1
+  80:	05          	add
+  81:	00          	breakpoint
+  82:	00          	breakpoint
+  83:	00          	breakpoint
+  84:	9a          	im 26
+  85:	02          	pushsp
+  86:	91          	im 17
+  87:	08          	load
+  88:	04          	poppc
+  89:	63          	loadsp 76
+  8a:	79          	loadsp 36
+  8b:	63          	loadsp 76
+  8c:	6c          	loadsp 112
+  8d:	65          	loadsp 84
+  8e:	73          	loadsp 12
+  8f:	00          	breakpoint
+  90:	01          	.byte 1
+  91:	08          	load
+  92:	00          	breakpoint
+  93:	00          	breakpoint
+  94:	00          	breakpoint
+  95:	9a          	im 26
+  96:	02          	pushsp
+  97:	91          	im 17
+  98:	7c          	loadsp 48
+  99:	00          	breakpoint
+  9a:	05          	add
+  9b:	75          	loadsp 20
+  9c:	6e          	loadsp 120
+  9d:	73          	loadsp 12
+  9e:	69          	loadsp 100
+  9f:	67          	loadsp 92
+  a0:	6e          	loadsp 120
+  a1:	65          	loadsp 84
+  a2:	64          	loadsp 80
+  a3:	20          	.byte 32
+  a4:	69          	loadsp 100
+  a5:	6e          	loadsp 120
+  a6:	74          	loadsp 16
+  a7:	00          	breakpoint
+  a8:	04          	poppc
+  a9:	07          	or
+  aa:	06          	and
+  ab:	00          	breakpoint
+  ac:	00          	breakpoint
+  ad:	00          	breakpoint
+  ae:	d7          	im -41
+  af:	01          	.byte 1
+  b0:	63          	loadsp 76
+  b1:	6c          	loadsp 112
+  b2:	65          	loadsp 84
+  b3:	61          	loadsp 68
+  b4:	72          	loadsp 8
+  b5:	5f          	storesp 60
+  b6:	36          	mod
+  b7:	34          	storeb
+  b8:	6b          	loadsp 108
+  b9:	5f          	storesp 60
+  ba:	72          	loadsp 8
+  bb:	61          	loadsp 68
+  bc:	6d          	loadsp 116
+  bd:	00          	breakpoint
+  be:	01          	.byte 1
+  bf:	0d          	popsp
+  c0:	00          	breakpoint
+  c1:	00          	breakpoint
+  c2:	04          	poppc
+  c3:	f0          	im -16
+  c4:	00          	breakpoint
+  c5:	00          	breakpoint
+  c6:	05          	add
+  c7:	b3          	im 51
+  c8:	01          	.byte 1
+  c9:	53          	storesp 12
+  ca:	04          	poppc
+  cb:	69          	loadsp 100
+  cc:	00          	breakpoint
+  cd:	01          	.byte 1
+  ce:	0e          	.byte 14
+  cf:	00          	breakpoint
+  d0:	00          	breakpoint
+  d1:	00          	breakpoint
+  d2:	d7          	im -41
+  d3:	02          	pushsp
+  d4:	91          	im 17
+  d5:	7c          	loadsp 48
+  d6:	00          	breakpoint
+  d7:	05          	add
+  d8:	69          	loadsp 100
+  d9:	6e          	loadsp 120
+  da:	74          	loadsp 16
+  db:	00          	breakpoint
+  dc:	04          	poppc
+  dd:	05          	add
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+  e0:	00          	breakpoint
+  e1:	01          	.byte 1
+  e2:	1e          	addsp 56
+  e3:	01          	.byte 1
+  e4:	72          	loadsp 8
+  e5:	65          	loadsp 84
+  e6:	73          	loadsp 12
+  e7:	65          	loadsp 84
+  e8:	74          	loadsp 16
+  e9:	5f          	storesp 60
+  ea:	36          	mod
+  eb:	35          	div
+  ec:	30          	neg
+  ed:	32          	xor
+  ee:	00          	breakpoint
+  ef:	01          	.byte 1
+  f0:	2b          	ashiftleft
+  f1:	01          	.byte 1
+  f2:	00          	breakpoint
+  f3:	00          	breakpoint
+  f4:	05          	add
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+  f7:	00          	breakpoint
+  f8:	06          	and
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+  fa:	01          	.byte 1
+  fb:	53          	storesp 12
+  fc:	03          	.byte 3
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+  fe:	65          	loadsp 84
+  ff:	73          	loadsp 12
+ 100:	65          	loadsp 84
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+ 102:	5f          	storesp 60
+ 103:	6e          	loadsp 120
+ 104:	00          	breakpoint
+ 105:	01          	.byte 1
+ 106:	2a          	lshiftright
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+ 108:	00          	breakpoint
+ 109:	00          	breakpoint
+ 10a:	9a          	im 26
+ 10b:	02          	pushsp
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+ 112:	76          	loadsp 24
+ 113:	00          	breakpoint
+ 114:	01          	.byte 1
+ 115:	2c          	ashiftright
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+ 117:	00          	breakpoint
+ 118:	00          	breakpoint
+ 119:	d7          	im -41
+ 11a:	02          	pushsp
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+ 11d:	00          	breakpoint
+ 11e:	02          	pushsp
+ 11f:	00          	breakpoint
+ 120:	00          	breakpoint
+ 121:	01          	.byte 1
+ 122:	5c          	storesp 48
+ 123:	01          	.byte 1
+ 124:	70          	loadsp 0
+ 125:	61          	loadsp 68
+ 126:	75          	loadsp 20
+ 127:	73          	loadsp 12
+ 128:	65          	loadsp 84
+ 129:	5f          	storesp 60
+ 12a:	36          	mod
+ 12b:	35          	div
+ 12c:	30          	neg
+ 12d:	32          	xor
+ 12e:	00          	breakpoint
+ 12f:	01          	.byte 1
+ 130:	35          	div
+ 131:	01          	.byte 1
+ 132:	00          	breakpoint
+ 133:	00          	breakpoint
+ 134:	06          	and
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+ 137:	00          	breakpoint
+ 138:	06          	and
+ 139:	58          	storesp 32
+ 13a:	01          	.byte 1
+ 13b:	53          	storesp 12
+ 13c:	03          	.byte 3
+ 13d:	70          	loadsp 0
+ 13e:	61          	loadsp 68
+ 13f:	75          	loadsp 20
+ 140:	73          	loadsp 12
+ 141:	65          	loadsp 84
+ 142:	00          	breakpoint
+ 143:	01          	.byte 1
+ 144:	34          	storeb
+ 145:	00          	breakpoint
+ 146:	00          	breakpoint
+ 147:	00          	breakpoint
+ 148:	9a          	im 26
+ 149:	02          	pushsp
+ 14a:	91          	im 17
+ 14b:	08          	load
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+ 14d:	70          	loadsp 0
+ 14e:	72          	loadsp 8
+ 14f:	65          	loadsp 84
+ 150:	76          	loadsp 24
+ 151:	00          	breakpoint
+ 152:	01          	.byte 1
+ 153:	36          	mod
+ 154:	00          	breakpoint
+ 155:	00          	breakpoint
+ 156:	00          	breakpoint
+ 157:	d7          	im -41
+ 158:	02          	pushsp
+ 159:	91          	im 17
+ 15a:	7c          	loadsp 48
+ 15b:	00          	breakpoint
+ 15c:	07          	or
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+ 15e:	00          	breakpoint
+ 15f:	01          	.byte 1
+ 160:	94          	im 20
+ 161:	01          	.byte 1
+ 162:	6d          	loadsp 116
+ 163:	61          	loadsp 68
+ 164:	69          	loadsp 100
+ 165:	6e          	loadsp 120
+ 166:	00          	breakpoint
+ 167:	01          	.byte 1
+ 168:	3f          	callpcrel
+ 169:	01          	.byte 1
+ 16a:	00          	breakpoint
+ 16b:	00          	breakpoint
+ 16c:	00          	breakpoint
+ 16d:	d7          	im -41
+ 16e:	00          	breakpoint
+ 16f:	00          	breakpoint
+ 170:	06          	and
+ 171:	58          	storesp 32
+ 172:	00          	breakpoint
+ 173:	00          	breakpoint
+ 174:	06          	and
+ 175:	96          	im 22
+ 176:	01          	.byte 1
+ 177:	53          	storesp 12
+ 178:	04          	poppc
+ 179:	69          	loadsp 100
+ 17a:	00          	breakpoint
+ 17b:	01          	.byte 1
+ 17c:	40          	storesp 64
+ 17d:	00          	breakpoint
+ 17e:	00          	breakpoint
+ 17f:	00          	breakpoint
+ 180:	9a          	im 26
+ 181:	02          	pushsp
+ 182:	91          	im 17
+ 183:	7c          	loadsp 48
+ 184:	04          	poppc
+ 185:	74          	loadsp 16
+ 186:	65          	loadsp 84
+ 187:	6d          	loadsp 116
+ 188:	70          	loadsp 0
+ 189:	00          	breakpoint
+ 18a:	01          	.byte 1
+ 18b:	41          	storesp 68
+ 18c:	00          	breakpoint
+ 18d:	00          	breakpoint
+ 18e:	01          	.byte 1
+ 18f:	94          	im 20
+ 190:	02          	pushsp
+ 191:	91          	im 17
+ 192:	78          	loadsp 32
+ 193:	00          	breakpoint
+ 194:	05          	add
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+ 196:	6e          	loadsp 120
+ 197:	73          	loadsp 12
+ 198:	69          	loadsp 100
+ 199:	67          	loadsp 92
+ 19a:	6e          	loadsp 120
+ 19b:	65          	loadsp 84
+ 19c:	64          	loadsp 80
+ 19d:	20          	.byte 32
+ 19e:	63          	loadsp 76
+ 19f:	68          	loadsp 96
+ 1a0:	61          	loadsp 68
+ 1a1:	72          	loadsp 8
+ 1a2:	00          	breakpoint
+ 1a3:	01          	.byte 1
+ 1a4:	08          	load
+ 1a5:	08          	load
+ 1a6:	7a          	loadsp 40
+ 1a7:	70          	loadsp 0
+ 1a8:	75          	loadsp 20
+ 1a9:	5f          	storesp 60
+ 1aa:	63          	loadsp 76
+ 1ab:	6f          	loadsp 124
+ 1ac:	6e          	loadsp 120
+ 1ad:	66          	loadsp 88
+ 1ae:	69          	loadsp 100
+ 1af:	67          	loadsp 92
+ 1b0:	00          	breakpoint
+ 1b1:	02          	pushsp
+ 1b2:	05          	add
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+ 1b4:	00          	breakpoint
+ 1b5:	01          	.byte 1
+ 1b6:	b9          	im 57
+ 1b7:	01          	.byte 1
+ 1b8:	01          	.byte 1
+ 1b9:	09          	not
+ 1ba:	04          	poppc
+ 1bb:	00          	breakpoint
+ 1bc:	00          	breakpoint
+ 1bd:	01          	.byte 1
+ 1be:	bf          	im 63
+ 1bf:	0a          	flip
+ 1c0:	00          	breakpoint
+ 1c1:	00          	breakpoint
+ 1c2:	00          	breakpoint
+ 1c3:	d7          	im -41
+ 1c4:	08          	load
+ 1c5:	7a          	loadsp 40
+ 1c6:	70          	loadsp 0
+ 1c7:	75          	loadsp 20
+ 1c8:	5f          	storesp 60
+ 1c9:	70          	loadsp 0
+ 1ca:	61          	loadsp 68
+ 1cb:	75          	loadsp 20
+ 1cc:	73          	loadsp 12
+ 1cd:	65          	loadsp 84
+ 1ce:	00          	breakpoint
+ 1cf:	02          	pushsp
+ 1d0:	06          	and
+ 1d1:	00          	breakpoint
+ 1d2:	00          	breakpoint
+ 1d3:	01          	.byte 1
+ 1d4:	b9          	im 57
+ 1d5:	01          	.byte 1
+ 1d6:	01          	.byte 1
+ 1d7:	08          	load
+ 1d8:	7a          	loadsp 40
+ 1d9:	70          	loadsp 0
+ 1da:	75          	loadsp 20
+ 1db:	5f          	storesp 60
+ 1dc:	6c          	loadsp 112
+ 1dd:	65          	loadsp 84
+ 1de:	64          	loadsp 80
+ 1df:	67          	loadsp 92
+ 1e0:	00          	breakpoint
+ 1e1:	02          	pushsp
+ 1e2:	09          	not
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+ 1e4:	00          	breakpoint
+ 1e5:	01          	.byte 1
+ 1e6:	b9          	im 57
+ 1e7:	01          	.byte 1
+ 1e8:	01          	.byte 1
+ 1e9:	08          	load
+ 1ea:	7a          	loadsp 40
+ 1eb:	70          	loadsp 0
+ 1ec:	75          	loadsp 20
+ 1ed:	5f          	storesp 60
+ 1ee:	6c          	loadsp 112
+ 1ef:	65          	loadsp 84
+ 1f0:	64          	loadsp 80
+ 1f1:	72          	loadsp 8
+ 1f2:	00          	breakpoint
+ 1f3:	02          	pushsp
+ 1f4:	0a          	flip
+ 1f5:	00          	breakpoint
+ 1f6:	00          	breakpoint
+ 1f7:	01          	.byte 1
+ 1f8:	b9          	im 57
+ 1f9:	01          	.byte 1
+ 1fa:	01          	.byte 1
+ 1fb:	08          	load
+ 1fc:	61          	loadsp 68
+ 1fd:	74          	loadsp 16
+ 1fe:	61          	loadsp 68
+ 1ff:	72          	loadsp 8
+ 200:	69          	loadsp 100
+ 201:	5f          	storesp 60
+ 202:	6e          	loadsp 120
+ 203:	6d          	loadsp 116
+ 204:	69          	loadsp 100
+ 205:	65          	loadsp 84
+ 206:	6e          	loadsp 120
+ 207:	00          	breakpoint
+ 208:	02          	pushsp
+ 209:	22          	loadh
+ 20a:	00          	breakpoint
+ 20b:	00          	breakpoint
+ 20c:	02          	pushsp
+ 20d:	10          	addsp 0
+ 20e:	01          	.byte 1
+ 20f:	01          	.byte 1
+ 210:	09          	not
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+ 212:	00          	breakpoint
+ 213:	00          	breakpoint
+ 214:	02          	pushsp
+ 215:	16          	addsp 24
+ 216:	0a          	flip
+ 217:	00          	breakpoint
+ 218:	00          	breakpoint
+ 219:	01          	.byte 1
+ 21a:	94          	im 20
+	...
+
+0000021c <.Ldebug_info0>:
+ 21c:	00          	breakpoint
+ 21d:	00          	breakpoint
+ 21e:	04          	poppc
+ 21f:	c5          	im -59
+ 220:	00          	breakpoint
+ 221:	02          	pushsp
+ 222:	00          	breakpoint
+ 223:	00          	breakpoint
+ 224:	00          	breakpoint
+ 225:	a3          	im 35
+ 226:	04          	poppc
+ 227:	01          	.byte 1
+ 228:	00          	breakpoint
+ 229:	00          	breakpoint
+ 22a:	01          	.byte 1
+ 22b:	9a          	im 26
+ 22c:	00          	breakpoint
+ 22d:	00          	breakpoint
+ 22e:	06          	and
+ 22f:	96          	im 22
+ 230:	00          	breakpoint
+ 231:	00          	breakpoint
+ 232:	06          	and
+ 233:	96          	im 22
+ 234:	47          	storesp 92
+ 235:	4e          	storesp 120
+ 236:	55          	storesp 20
+ 237:	20          	.byte 32
+ 238:	43          	storesp 76
+ 239:	20          	.byte 32
+ 23a:	33          	loadb
+ 23b:	2e          	eq
+ 23c:	34          	storeb
+ 23d:	2e          	eq
+ 23e:	32          	xor
+ 23f:	00          	breakpoint
+ 240:	01          	.byte 1
+ 241:	72          	loadsp 8
+ 242:	65          	loadsp 84
+ 243:	67          	loadsp 92
+ 244:	73          	loadsp 12
+ 245:	2e          	eq
+ 246:	63          	loadsp 76
+ 247:	00          	breakpoint
+ 248:	2f          	neq
+ 249:	68          	loadsp 96
+ 24a:	6f          	loadsp 124
+ 24b:	6d          	loadsp 116
+ 24c:	65          	loadsp 84
+ 24d:	2f          	neq
+ 24e:	6d          	loadsp 116
+ 24f:	61          	loadsp 68
+ 250:	72          	loadsp 8
+ 251:	6b          	loadsp 108
+ 252:	77          	loadsp 28
+ 253:	2f          	neq
+ 254:	61          	loadsp 68
+ 255:	6c          	loadsp 112
+ 256:	74          	loadsp 16
+ 257:	65          	loadsp 84
+ 258:	72          	loadsp 8
+ 259:	61          	loadsp 68
+ 25a:	2f          	neq
+ 25b:	61          	loadsp 68
+ 25c:	74          	loadsp 16
+ 25d:	61          	loadsp 68
+ 25e:	72          	loadsp 8
+ 25f:	69          	loadsp 100
+ 260:	5f          	storesp 60
+ 261:	78          	loadsp 32
+ 262:	65          	loadsp 84
+ 263:	5f          	storesp 60
+ 264:	66          	loadsp 88
+ 265:	70          	loadsp 0
+ 266:	67          	loadsp 92
+ 267:	61          	loadsp 68
+ 268:	2f          	neq
+ 269:	7a          	loadsp 40
+ 26a:	70          	loadsp 0
+ 26b:	75          	loadsp 20
+ 26c:	2f          	neq
+ 26d:	6c          	loadsp 112
+ 26e:	65          	loadsp 84
+ 26f:	64          	loadsp 80
+ 270:	73          	loadsp 12
+ 271:	5f          	storesp 60
+ 272:	6e          	loadsp 120
+ 273:	6f          	loadsp 124
+ 274:	73          	loadsp 12
+ 275:	64          	loadsp 80
+ 276:	72          	loadsp 8
+ 277:	69          	loadsp 100
+ 278:	76          	loadsp 24
+ 279:	65          	loadsp 84
+ 27a:	00          	breakpoint
+ 27b:	02          	pushsp
+ 27c:	7a          	loadsp 40
+ 27d:	70          	loadsp 0
+ 27e:	75          	loadsp 20
+ 27f:	5f          	storesp 60
+ 280:	63          	loadsp 76
+ 281:	6f          	loadsp 124
+ 282:	6e          	loadsp 120
+ 283:	66          	loadsp 88
+ 284:	69          	loadsp 100
+ 285:	67          	loadsp 92
+ 286:	00          	breakpoint
+ 287:	01          	.byte 1
+ 288:	05          	add
+ 289:	00          	breakpoint
+ 28a:	00          	breakpoint
+ 28b:	00          	breakpoint
+ 28c:	78          	loadsp 32
+ 28d:	01          	.byte 1
+ 28e:	05          	add
+ 28f:	03          	.byte 3
+ 290:	00          	breakpoint
+ 291:	00          	breakpoint
+ 292:	09          	not
+ 293:	50          	storesp 0
+ 294:	03          	.byte 3
+ 295:	04          	poppc
+ 296:	00          	breakpoint
+ 297:	00          	breakpoint
+ 298:	00          	breakpoint
+ 299:	7e          	loadsp 56
+ 29a:	04          	poppc
+ 29b:	00          	breakpoint
+ 29c:	00          	breakpoint
+ 29d:	00          	breakpoint
+ 29e:	83          	im 3
+ 29f:	05          	add
+ 2a0:	69          	loadsp 100
+ 2a1:	6e          	loadsp 120
+ 2a2:	74          	loadsp 16
+ 2a3:	00          	breakpoint
+ 2a4:	04          	poppc
+ 2a5:	05          	add
+ 2a6:	02          	pushsp
+ 2a7:	7a          	loadsp 40
+ 2a8:	70          	loadsp 0
+ 2a9:	75          	loadsp 20
+ 2aa:	5f          	storesp 60
+ 2ab:	70          	loadsp 0
+ 2ac:	61          	loadsp 68
+ 2ad:	75          	loadsp 20
+ 2ae:	73          	loadsp 12
+ 2af:	65          	loadsp 84
+ 2b0:	00          	breakpoint
+ 2b1:	01          	.byte 1
+ 2b2:	06          	and
+ 2b3:	00          	breakpoint
+ 2b4:	00          	breakpoint
+ 2b5:	00          	breakpoint
+ 2b6:	78          	loadsp 32
+ 2b7:	01          	.byte 1
+ 2b8:	05          	add
+ 2b9:	03          	.byte 3
+ 2ba:	00          	breakpoint
+ 2bb:	00          	breakpoint
+ 2bc:	09          	not
+ 2bd:	54          	storesp 16
+ 2be:	02          	pushsp
+ 2bf:	7a          	loadsp 40
+ 2c0:	70          	loadsp 0
+ 2c1:	75          	loadsp 20
+ 2c2:	5f          	storesp 60
+ 2c3:	73          	loadsp 12
+ 2c4:	77          	loadsp 28
+ 2c5:	69          	loadsp 100
+ 2c6:	74          	loadsp 16
+ 2c7:	63          	loadsp 76
+ 2c8:	68          	loadsp 96
+ 2c9:	65          	loadsp 84
+ 2ca:	73          	loadsp 12
+ 2cb:	00          	breakpoint
+ 2cc:	01          	.byte 1
+ 2cd:	07          	or
+ 2ce:	00          	breakpoint
+ 2cf:	00          	breakpoint
+ 2d0:	00          	breakpoint
+ 2d1:	78          	loadsp 32
+ 2d2:	01          	.byte 1
+ 2d3:	05          	add
+ 2d4:	03          	.byte 3
+ 2d5:	00          	breakpoint
+ 2d6:	00          	breakpoint
+ 2d7:	09          	not
+ 2d8:	58          	storesp 32
+ 2d9:	02          	pushsp
+ 2da:	7a          	loadsp 40
+ 2db:	70          	loadsp 0
+ 2dc:	75          	loadsp 20
+ 2dd:	5f          	storesp 60
+ 2de:	6b          	loadsp 108
+ 2df:	65          	loadsp 84
+ 2e0:	79          	loadsp 36
+ 2e1:	00          	breakpoint
+ 2e2:	01          	.byte 1
+ 2e3:	08          	load
+ 2e4:	00          	breakpoint
+ 2e5:	00          	breakpoint
+ 2e6:	00          	breakpoint
+ 2e7:	78          	loadsp 32
+ 2e8:	01          	.byte 1
+ 2e9:	05          	add
+ 2ea:	03          	.byte 3
+ 2eb:	00          	breakpoint
+ 2ec:	00          	breakpoint
+ 2ed:	09          	not
+ 2ee:	5c          	storesp 48
+ 2ef:	02          	pushsp
+ 2f0:	7a          	loadsp 40
+ 2f1:	70          	loadsp 0
+ 2f2:	75          	loadsp 20
+ 2f3:	5f          	storesp 60
+ 2f4:	6c          	loadsp 112
+ 2f5:	65          	loadsp 84
+ 2f6:	64          	loadsp 80
+ 2f7:	67          	loadsp 92
+ 2f8:	00          	breakpoint
+ 2f9:	01          	.byte 1
+ 2fa:	09          	not
+ 2fb:	00          	breakpoint
+ 2fc:	00          	breakpoint
+ 2fd:	00          	breakpoint
+ 2fe:	78          	loadsp 32
+ 2ff:	01          	.byte 1
+ 300:	05          	add
+ 301:	03          	.byte 3
+ 302:	00          	breakpoint
+ 303:	00          	breakpoint
+ 304:	09          	not
+ 305:	60          	loadsp 64
+ 306:	02          	pushsp
+ 307:	7a          	loadsp 40
+ 308:	70          	loadsp 0
+ 309:	75          	loadsp 20
+ 30a:	5f          	storesp 60
+ 30b:	6c          	loadsp 112
+ 30c:	65          	loadsp 84
+ 30d:	64          	loadsp 80
+ 30e:	72          	loadsp 8
+ 30f:	00          	breakpoint
+ 310:	01          	.byte 1
+ 311:	0a          	flip
+ 312:	00          	breakpoint
+ 313:	00          	breakpoint
+ 314:	00          	breakpoint
+ 315:	78          	loadsp 32
+ 316:	01          	.byte 1
+ 317:	05          	add
+ 318:	03          	.byte 3
+ 319:	00          	breakpoint
+ 31a:	00          	breakpoint
+ 31b:	09          	not
+ 31c:	64          	loadsp 80
+ 31d:	02          	pushsp
+ 31e:	7a          	loadsp 40
+ 31f:	70          	loadsp 0
+ 320:	75          	loadsp 20
+ 321:	5f          	storesp 60
+ 322:	73          	loadsp 12
+ 323:	70          	loadsp 0
+ 324:	69          	loadsp 100
+ 325:	5f          	storesp 60
+ 326:	64          	loadsp 80
+ 327:	61          	loadsp 68
+ 328:	74          	loadsp 16
+ 329:	61          	loadsp 68
+ 32a:	00          	breakpoint
+ 32b:	01          	.byte 1
+ 32c:	0b          	nop
+ 32d:	00          	breakpoint
+ 32e:	00          	breakpoint
+ 32f:	00          	breakpoint
+ 330:	78          	loadsp 32
+ 331:	01          	.byte 1
+ 332:	05          	add
+ 333:	03          	.byte 3
+ 334:	00          	breakpoint
+ 335:	00          	breakpoint
+ 336:	09          	not
+ 337:	68          	loadsp 96
+ 338:	02          	pushsp
+ 339:	7a          	loadsp 40
+ 33a:	70          	loadsp 0
+ 33b:	75          	loadsp 20
+ 33c:	5f          	storesp 60
+ 33d:	73          	loadsp 12
+ 33e:	70          	loadsp 0
+ 33f:	69          	loadsp 100
+ 340:	5f          	storesp 60
+ 341:	73          	loadsp 12
+ 342:	74          	loadsp 16
+ 343:	61          	loadsp 68
+ 344:	74          	loadsp 16
+ 345:	65          	loadsp 84
+ 346:	00          	breakpoint
+ 347:	01          	.byte 1
+ 348:	0c          	store
+ 349:	00          	breakpoint
+ 34a:	00          	breakpoint
+ 34b:	00          	breakpoint
+ 34c:	78          	loadsp 32
+ 34d:	01          	.byte 1
+ 34e:	05          	add
+ 34f:	03          	.byte 3
+ 350:	00          	breakpoint
+ 351:	00          	breakpoint
+ 352:	09          	not
+ 353:	6c          	loadsp 112
+ 354:	02          	pushsp
+ 355:	7a          	loadsp 40
+ 356:	70          	loadsp 0
+ 357:	75          	loadsp 20
+ 358:	5f          	storesp 60
+ 359:	73          	loadsp 12
+ 35a:	69          	loadsp 100
+ 35b:	6f          	loadsp 124
+ 35c:	00          	breakpoint
+ 35d:	01          	.byte 1
+ 35e:	0d          	popsp
+ 35f:	00          	breakpoint
+ 360:	00          	breakpoint
+ 361:	00          	breakpoint
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+ 390:	78          	loadsp 32
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+ 5e7:	32          	xor
+ 5e8:	00          	breakpoint
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+	...
+Disassembly of section .debug_line:
+
+00000000 <.Ldebug_line0>:
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+	...
+
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+	...
+Disassembly of section .debug_frame:
+
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+Disassembly of section .debug_pubnames:
+
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+ 172:	66          	loadsp 88
+ 173:	32          	xor
+ 174:	00          	breakpoint
+ 175:	00          	breakpoint
+ 176:	00          	breakpoint
+ 177:	02          	pushsp
+ 178:	47          	storesp 92
+ 179:	7a          	loadsp 40
+ 17a:	70          	loadsp 0
+ 17b:	75          	loadsp 20
+ 17c:	5f          	storesp 60
+ 17d:	70          	loadsp 0
+ 17e:	6f          	loadsp 124
+ 17f:	6b          	loadsp 108
+ 180:	65          	loadsp 84
+ 181:	79          	loadsp 36
+ 182:	5f          	storesp 60
+ 183:	61          	loadsp 68
+ 184:	75          	loadsp 20
+ 185:	64          	loadsp 80
+ 186:	63          	loadsp 76
+ 187:	32          	xor
+ 188:	00          	breakpoint
+ 189:	00          	breakpoint
+ 18a:	00          	breakpoint
+ 18b:	02          	pushsp
+ 18c:	65          	loadsp 84
+ 18d:	7a          	loadsp 40
+ 18e:	70          	loadsp 0
+ 18f:	75          	loadsp 20
+ 190:	5f          	storesp 60
+ 191:	70          	loadsp 0
+ 192:	6f          	loadsp 124
+ 193:	6b          	loadsp 108
+ 194:	65          	loadsp 84
+ 195:	79          	loadsp 36
+ 196:	5f          	storesp 60
+ 197:	61          	loadsp 68
+ 198:	75          	loadsp 20
+ 199:	64          	loadsp 80
+ 19a:	66          	loadsp 88
+ 19b:	33          	loadb
+ 19c:	00          	breakpoint
+ 19d:	00          	breakpoint
+ 19e:	00          	breakpoint
+ 19f:	02          	pushsp
+ 1a0:	83          	im 3
+ 1a1:	7a          	loadsp 40
+ 1a2:	70          	loadsp 0
+ 1a3:	75          	loadsp 20
+ 1a4:	5f          	storesp 60
+ 1a5:	70          	loadsp 0
+ 1a6:	6f          	loadsp 124
+ 1a7:	6b          	loadsp 108
+ 1a8:	65          	loadsp 84
+ 1a9:	79          	loadsp 36
+ 1aa:	5f          	storesp 60
+ 1ab:	61          	loadsp 68
+ 1ac:	75          	loadsp 20
+ 1ad:	64          	loadsp 80
+ 1ae:	63          	loadsp 76
+ 1af:	33          	loadb
+ 1b0:	00          	breakpoint
+ 1b1:	00          	breakpoint
+ 1b2:	00          	breakpoint
+ 1b3:	02          	pushsp
+ 1b4:	a1          	im 33
+ 1b5:	7a          	loadsp 40
+ 1b6:	70          	loadsp 0
+ 1b7:	75          	loadsp 20
+ 1b8:	5f          	storesp 60
+ 1b9:	70          	loadsp 0
+ 1ba:	6f          	loadsp 124
+ 1bb:	6b          	loadsp 108
+ 1bc:	65          	loadsp 84
+ 1bd:	79          	loadsp 36
+ 1be:	5f          	storesp 60
+ 1bf:	61          	loadsp 68
+ 1c0:	75          	loadsp 20
+ 1c1:	64          	loadsp 80
+ 1c2:	63          	loadsp 76
+ 1c3:	74          	loadsp 16
+ 1c4:	6c          	loadsp 112
+ 1c5:	00          	breakpoint
+ 1c6:	00          	breakpoint
+ 1c7:	00          	breakpoint
+ 1c8:	02          	pushsp
+ 1c9:	c0          	im -64
+ 1ca:	7a          	loadsp 40
+ 1cb:	70          	loadsp 0
+ 1cc:	75          	loadsp 20
+ 1cd:	5f          	storesp 60
+ 1ce:	70          	loadsp 0
+ 1cf:	6f          	loadsp 124
+ 1d0:	6b          	loadsp 108
+ 1d1:	65          	loadsp 84
+ 1d2:	79          	loadsp 36
+ 1d3:	5f          	storesp 60
+ 1d4:	73          	loadsp 12
+ 1d5:	6b          	loadsp 108
+ 1d6:	72          	loadsp 8
+ 1d7:	65          	loadsp 84
+ 1d8:	73          	loadsp 12
+ 1d9:	74          	loadsp 16
+ 1da:	00          	breakpoint
+ 1db:	00          	breakpoint
+ 1dc:	00          	breakpoint
+ 1dd:	02          	pushsp
+ 1de:	df          	im -33
+ 1df:	7a          	loadsp 40
+ 1e0:	70          	loadsp 0
+ 1e1:	75          	loadsp 20
+ 1e2:	5f          	storesp 60
+ 1e3:	70          	loadsp 0
+ 1e4:	6f          	loadsp 124
+ 1e5:	6b          	loadsp 108
+ 1e6:	65          	loadsp 84
+ 1e7:	79          	loadsp 36
+ 1e8:	5f          	storesp 60
+ 1e9:	73          	loadsp 12
+ 1ea:	65          	loadsp 84
+ 1eb:	72          	loadsp 8
+ 1ec:	6f          	loadsp 124
+ 1ed:	75          	loadsp 20
+ 1ee:	74          	loadsp 16
+ 1ef:	00          	breakpoint
+ 1f0:	00          	breakpoint
+ 1f1:	00          	breakpoint
+ 1f2:	02          	pushsp
+ 1f3:	fe          	im -2
+ 1f4:	7a          	loadsp 40
+ 1f5:	70          	loadsp 0
+ 1f6:	75          	loadsp 20
+ 1f7:	5f          	storesp 60
+ 1f8:	70          	loadsp 0
+ 1f9:	6f          	loadsp 124
+ 1fa:	6b          	loadsp 108
+ 1fb:	65          	loadsp 84
+ 1fc:	79          	loadsp 36
+ 1fd:	5f          	storesp 60
+ 1fe:	69          	loadsp 100
+ 1ff:	72          	loadsp 8
+ 200:	71          	loadsp 4
+ 201:	65          	loadsp 84
+ 202:	6e          	loadsp 120
+ 203:	00          	breakpoint
+ 204:	00          	breakpoint
+ 205:	00          	breakpoint
+ 206:	03          	.byte 3
+ 207:	1c          	addsp 48
+ 208:	7a          	loadsp 40
+ 209:	70          	loadsp 0
+ 20a:	75          	loadsp 20
+ 20b:	5f          	storesp 60
+ 20c:	70          	loadsp 0
+ 20d:	6f          	loadsp 124
+ 20e:	6b          	loadsp 108
+ 20f:	65          	loadsp 84
+ 210:	79          	loadsp 36
+ 211:	5f          	storesp 60
+ 212:	73          	loadsp 12
+ 213:	6b          	loadsp 108
+ 214:	63          	loadsp 76
+ 215:	74          	loadsp 16
+ 216:	6c          	loadsp 112
+ 217:	00          	breakpoint
+ 218:	00          	breakpoint
+ 219:	00          	breakpoint
+ 21a:	03          	.byte 3
+ 21b:	3a          	config
+ 21c:	61          	loadsp 68
+ 21d:	74          	loadsp 16
+ 21e:	61          	loadsp 68
+ 21f:	72          	loadsp 8
+ 220:	69          	loadsp 100
+ 221:	5f          	storesp 60
+ 222:	6e          	loadsp 120
+ 223:	6d          	loadsp 116
+ 224:	69          	loadsp 100
+ 225:	65          	loadsp 84
+ 226:	6e          	loadsp 120
+ 227:	00          	breakpoint
+ 228:	00          	breakpoint
+ 229:	00          	breakpoint
+ 22a:	03          	.byte 3
+ 22b:	54          	storesp 16
+ 22c:	61          	loadsp 68
+ 22d:	74          	loadsp 16
+ 22e:	61          	loadsp 68
+ 22f:	72          	loadsp 8
+ 230:	69          	loadsp 100
+ 231:	5f          	storesp 60
+ 232:	64          	loadsp 80
+ 233:	6c          	loadsp 112
+ 234:	69          	loadsp 100
+ 235:	73          	loadsp 12
+ 236:	74          	loadsp 16
+ 237:	6c          	loadsp 112
+ 238:	00          	breakpoint
+ 239:	00          	breakpoint
+ 23a:	00          	breakpoint
+ 23b:	03          	.byte 3
+ 23c:	6f          	loadsp 124
+ 23d:	61          	loadsp 68
+ 23e:	74          	loadsp 16
+ 23f:	61          	loadsp 68
+ 240:	72          	loadsp 8
+ 241:	69          	loadsp 100
+ 242:	5f          	storesp 60
+ 243:	64          	loadsp 80
+ 244:	6c          	loadsp 112
+ 245:	69          	loadsp 100
+ 246:	73          	loadsp 12
+ 247:	74          	loadsp 16
+ 248:	68          	loadsp 96
+ 249:	00          	breakpoint
+ 24a:	00          	breakpoint
+ 24b:	00          	breakpoint
+ 24c:	03          	.byte 3
+ 24d:	8a          	im 10
+ 24e:	61          	loadsp 68
+ 24f:	74          	loadsp 16
+ 250:	61          	loadsp 68
+ 251:	72          	loadsp 8
+ 252:	69          	loadsp 100
+ 253:	5f          	storesp 60
+ 254:	63          	loadsp 76
+ 255:	6f          	loadsp 124
+ 256:	6c          	loadsp 112
+ 257:	62          	loadsp 72
+ 258:	6b          	loadsp 108
+ 259:	00          	breakpoint
+ 25a:	00          	breakpoint
+ 25b:	00          	breakpoint
+ 25c:	03          	.byte 3
+ 25d:	a4          	im 36
+ 25e:	61          	loadsp 68
+ 25f:	74          	loadsp 16
+ 260:	61          	loadsp 68
+ 261:	72          	loadsp 8
+ 262:	69          	loadsp 100
+ 263:	5f          	storesp 60
+ 264:	63          	loadsp 76
+ 265:	6f          	loadsp 124
+ 266:	6c          	loadsp 112
+ 267:	70          	loadsp 0
+ 268:	66          	loadsp 88
+ 269:	31          	sub
+ 26a:	00          	breakpoint
+ 26b:	00          	breakpoint
+ 26c:	00          	breakpoint
+ 26d:	03          	.byte 3
+ 26e:	bf          	im 63
+ 26f:	61          	loadsp 68
+ 270:	74          	loadsp 16
+ 271:	61          	loadsp 68
+ 272:	72          	loadsp 8
+ 273:	69          	loadsp 100
+ 274:	5f          	storesp 60
+ 275:	63          	loadsp 76
+ 276:	6f          	loadsp 124
+ 277:	6c          	loadsp 112
+ 278:	70          	loadsp 0
+ 279:	66          	loadsp 88
+ 27a:	32          	xor
+ 27b:	00          	breakpoint
+ 27c:	00          	breakpoint
+ 27d:	00          	breakpoint
+ 27e:	03          	.byte 3
+ 27f:	da          	im -38
+ 280:	61          	loadsp 68
+ 281:	74          	loadsp 16
+ 282:	61          	loadsp 68
+ 283:	72          	loadsp 8
+ 284:	69          	loadsp 100
+ 285:	5f          	storesp 60
+ 286:	70          	loadsp 0
+ 287:	72          	loadsp 8
+ 288:	69          	loadsp 100
+ 289:	6f          	loadsp 124
+ 28a:	72          	loadsp 8
+ 28b:	00          	breakpoint
+ 28c:	00          	breakpoint
+ 28d:	00          	breakpoint
+ 28e:	03          	.byte 3
+ 28f:	f4          	im -12
+ 290:	61          	loadsp 68
+ 291:	74          	loadsp 16
+ 292:	61          	loadsp 68
+ 293:	72          	loadsp 8
+ 294:	69          	loadsp 100
+ 295:	5f          	storesp 60
+ 296:	72          	loadsp 8
+ 297:	61          	loadsp 68
+ 298:	6e          	loadsp 120
+ 299:	64          	loadsp 80
+ 29a:	6f          	loadsp 124
+ 29b:	6d          	loadsp 116
+ 29c:	00          	breakpoint
+ 29d:	00          	breakpoint
+ 29e:	00          	breakpoint
+ 29f:	04          	poppc
+ 2a0:	0f          	.byte 15
+ 2a1:	61          	loadsp 68
+ 2a2:	74          	loadsp 16
+ 2a3:	61          	loadsp 68
+ 2a4:	72          	loadsp 8
+ 2a5:	69          	loadsp 100
+ 2a6:	5f          	storesp 60
+ 2a7:	70          	loadsp 0
+ 2a8:	6f          	loadsp 124
+ 2a9:	72          	loadsp 8
+ 2aa:	74          	loadsp 16
+ 2ab:	61          	loadsp 68
+ 2ac:	00          	breakpoint
+ 2ad:	00          	breakpoint
+ 2ae:	00          	breakpoint
+ 2af:	04          	poppc
+ 2b0:	29          	mult
+ 2b1:	61          	loadsp 68
+ 2b2:	74          	loadsp 16
+ 2b3:	61          	loadsp 68
+ 2b4:	72          	loadsp 8
+ 2b5:	69          	loadsp 100
+ 2b6:	5f          	storesp 60
+ 2b7:	70          	loadsp 0
+ 2b8:	6f          	loadsp 124
+ 2b9:	72          	loadsp 8
+ 2ba:	74          	loadsp 16
+ 2bb:	62          	loadsp 72
+ 2bc:	00          	breakpoint
+ 2bd:	00          	breakpoint
+ 2be:	00          	breakpoint
+ 2bf:	04          	poppc
+ 2c0:	43          	storesp 76
+ 2c1:	61          	loadsp 68
+ 2c2:	74          	loadsp 16
+ 2c3:	61          	loadsp 68
+ 2c4:	72          	loadsp 8
+ 2c5:	69          	loadsp 100
+ 2c6:	5f          	storesp 60
+ 2c7:	74          	loadsp 16
+ 2c8:	72          	loadsp 8
+ 2c9:	69          	loadsp 100
+ 2ca:	67          	loadsp 92
+ 2cb:	30          	neg
+ 2cc:	00          	breakpoint
+ 2cd:	00          	breakpoint
+ 2ce:	00          	breakpoint
+ 2cf:	04          	poppc
+ 2d0:	5d          	storesp 52
+ 2d1:	61          	loadsp 68
+ 2d2:	74          	loadsp 16
+ 2d3:	61          	loadsp 68
+ 2d4:	72          	loadsp 8
+ 2d5:	69          	loadsp 100
+ 2d6:	5f          	storesp 60
+ 2d7:	63          	loadsp 76
+ 2d8:	68          	loadsp 96
+ 2d9:	62          	loadsp 72
+ 2da:	61          	loadsp 68
+ 2db:	73          	loadsp 12
+ 2dc:	65          	loadsp 84
+ 2dd:	00          	breakpoint
+ 2de:	00          	breakpoint
+ 2df:	00          	breakpoint
+ 2e0:	04          	poppc
+ 2e1:	78          	loadsp 32
+ 2e2:	61          	loadsp 68
+ 2e3:	74          	loadsp 16
+ 2e4:	61          	loadsp 68
+ 2e5:	72          	loadsp 8
+ 2e6:	69          	loadsp 100
+ 2e7:	5f          	storesp 60
+ 2e8:	63          	loadsp 76
+ 2e9:	68          	loadsp 96
+ 2ea:	61          	loadsp 68
+ 2eb:	63          	loadsp 76
+ 2ec:	74          	loadsp 16
+ 2ed:	6c          	loadsp 112
+ 2ee:	00          	breakpoint
+ 2ef:	00          	breakpoint
+ 2f0:	00          	breakpoint
+ 2f1:	04          	poppc
+ 2f2:	93          	im 19
+ 2f3:	61          	loadsp 68
+ 2f4:	74          	loadsp 16
+ 2f5:	61          	loadsp 68
+ 2f6:	72          	loadsp 8
+ 2f7:	69          	loadsp 100
+ 2f8:	5f          	storesp 60
+ 2f9:	64          	loadsp 80
+ 2fa:	6d          	loadsp 116
+ 2fb:	61          	loadsp 68
+ 2fc:	63          	loadsp 76
+ 2fd:	74          	loadsp 16
+ 2fe:	6c          	loadsp 112
+ 2ff:	00          	breakpoint
+ 300:	00          	breakpoint
+ 301:	00          	breakpoint
+ 302:	04          	poppc
+ 303:	ae          	im 46
+ 304:	61          	loadsp 68
+ 305:	74          	loadsp 16
+ 306:	61          	loadsp 68
+ 307:	72          	loadsp 8
+ 308:	69          	loadsp 100
+ 309:	5f          	storesp 60
+ 30a:	73          	loadsp 12
+ 30b:	6b          	loadsp 108
+ 30c:	63          	loadsp 76
+ 30d:	74          	loadsp 16
+ 30e:	6c          	loadsp 112
+ 30f:	00          	breakpoint
+ 310:	00          	breakpoint
+ 311:	00          	breakpoint
+	...
+Disassembly of section .debug_aranges:
+
+00000000 <.debug_aranges>:
+   0:	00          	breakpoint
+   1:	00          	breakpoint
+   2:	00          	breakpoint
+   3:	1c          	addsp 48
+   4:	00          	breakpoint
+   5:	02          	pushsp
+   6:	00          	breakpoint
+   7:	00          	breakpoint
+   8:	00          	breakpoint
+   9:	00          	breakpoint
+   a:	04          	poppc
+   b:	00          	breakpoint
+   c:	00          	breakpoint
+   d:	00          	breakpoint
+   e:	00          	breakpoint
+   f:	00          	breakpoint
+  10:	00          	breakpoint
+  11:	00          	breakpoint
+  12:	04          	poppc
+  13:	b1          	im 49
+  14:	00          	breakpoint
+  15:	00          	breakpoint
+  16:	02          	pushsp
+  17:	8e          	im 14
+	...
+Disassembly of section .comment:
+
+00000000 <.comment>:
+   0:	00          	breakpoint
+   1:	47          	storesp 92
+   2:	43          	storesp 76
+   3:	43          	storesp 76
+   4:	3a          	config
+   5:	20          	.byte 32
+   6:	28          	swap
+   7:	47          	storesp 92
+   8:	4e          	storesp 120
+   9:	55          	storesp 20
+   a:	29          	mult
+   b:	20          	.byte 32
+   c:	33          	loadb
+   d:	2e          	eq
+   e:	34          	storeb
+   f:	2e          	eq
+  10:	32          	xor
+  11:	00          	breakpoint
+  12:	00          	breakpoint
+  13:	47          	storesp 92
+  14:	43          	storesp 76
+  15:	43          	storesp 76
+  16:	3a          	config
+  17:	20          	.byte 32
+  18:	28          	swap
+  19:	47          	storesp 92
+  1a:	4e          	storesp 120
+  1b:	55          	storesp 20
+  1c:	29          	mult
+  1d:	20          	.byte 32
+  1e:	33          	loadb
+  1f:	2e          	eq
+  20:	34          	storeb
+  21:	2e          	eq
+  22:	32          	xor
+  23:	00          	breakpoint
+  24:	00          	breakpoint
+  25:	47          	storesp 92
+  26:	43          	storesp 76
+  27:	43          	storesp 76
+  28:	3a          	config
+  29:	20          	.byte 32
+  2a:	28          	swap
+  2b:	47          	storesp 92
+  2c:	4e          	storesp 120
+  2d:	55          	storesp 20
+  2e:	29          	mult
+  2f:	20          	.byte 32
+  30:	33          	loadb
+  31:	2e          	eq
+  32:	34          	storeb
+  33:	2e          	eq
+  34:	32          	xor
+  35:	00          	breakpoint
+  36:	00          	breakpoint
+  37:	47          	storesp 92
+  38:	43          	storesp 76
+  39:	43          	storesp 76
+  3a:	3a          	config
+  3b:	20          	.byte 32
+  3c:	28          	swap
+  3d:	47          	storesp 92
+  3e:	4e          	storesp 120
+  3f:	55          	storesp 20
+  40:	29          	mult
+  41:	20          	.byte 32
+  42:	33          	loadb
+  43:	2e          	eq
+  44:	34          	storeb
+  45:	2e          	eq
+  46:	32          	xor
+	...
Index: unmerged/zpu_firmware/replay/Makefile
===================================================================
--- unmerged/zpu_firmware/replay/Makefile	(nonexistent)
+++ unmerged/zpu_firmware/replay/Makefile	(revision 1)
@@ -0,0 +1,89 @@
+BASE	= zpu-elf
+CC      = $(BASE)-gcc
+LD      = $(BASE)-gcc
+AS      = $(BASE)-as
+CP      = $(BASE)-objcopy
+DUMP    = $(BASE)-objdump
+
+ROMGEN = ./zpuromgen
+
+# we use mincrt0.s from here
+STARTUP_DIR = .
+
+# we fetch ROM prologue / epilogue from here
+RTL_DIR = $(ZPUFLEXDIR)/RTL/
+
+
+BUILD_DIR=zpu_obj
+
+#MINSTARTUP_SRC = mincrt0.s
+MINSTARTUP_SRC = mycrt0.s
+MINSTARTUP_OBJ = $(patsubst $(STARTUP_DIR)/%.s,$(BUILD_DIR)/%.o,$(MINSTARTUP_SRC))
+
+MAIN_PRJ = HelloTinyROM
+MAIN_SRC = main.c regs.c
+#MAIN_SRC = stuff.c
+MAIN_OBJ = $(COMMON_OBJ) $(patsubst %.c,$(BUILD_DIR)/%.o,$(MAIN_SRC))
+
+LINKMAP  = ./standalone_simple.ld
+
+
+# Commandline options for each tool.
+
+#ZPUOPTS= -mno-poppcrel -mno-pushspadd -mno-callpcrel -mno-shortop -mno-neg # No-neg requires bugfixed toolchain
+#Include everything -> need to include emulation rom...
+ZPUOPTS =
+CFLAGS  = -I. -c -g -O0 $(ZPUOPTS) -DDISABLE_UART_RX
+
+LFLAGS  = -nostartfiles -Wl,--relax -g -O0
+#LFLAGS  = -nostartfiles -Os
+
+
+# Our target.
+all: $(BUILD_DIR) $(MAIN_PRJ).bin $(MAIN_PRJ)_ROM.mif $(MAIN_PRJ).rpt $(MAIN_PRJ).dis
+
+clean:
+	rm -f $(BUILD_DIR)/*.o *.hex *.elf *.map *.lst *.srec $(MAIN_PRJ).rom *~ */*.o *.bin
+
+# Convert ELF binary to disassembly
+%.dis: %.elf
+	zpu-elf-objdump -DS $< > $@
+
+# Convert ELF binary to bin file.
+%.bin: %.elf
+	$(CP) -O binary $< $@
+
+%.rpt: %.elf
+	echo >$@ -n "End of code:\t"
+	$(DUMP) -x $< | grep >>$@ _romend
+	echo >>$@ -n "Start of BSS:\t"
+	$(DUMP) -x $< | grep  >>$@ __bss_start__
+	echo >>$@ -n "End of BSS:\t"
+	$(DUMP) -x $< | grep >>$@ __bss_end__
+	cat $@
+
+$(ROMGEN): ./zpuromgen.c
+	gcc -o ./zpuromgen ./zpuromgen.c
+
+%_ROM.mif: %.bin $(ROMGEN)
+	sed 's/dualportram/$*_ROM/' >$*_ROM.mif <./rom_prologue.vhd
+	$(ROMGEN) $*.bin >>$*_ROM.mif
+	cat >>$*_ROM.mif ./rom_epilogue.vhd
+
+# Link - this produces an ELF binary.
+
+$(MAIN_PRJ).elf: $(MINSTARTUP_OBJ) $(MAIN_OBJ)
+	$(LD) $(LFLAGS) -T $(LINKMAP) -o $@ $+ $(LIBS)
+
+$(BUILD_DIR)/%.o: %.c Makefile
+	$(CC) $(CFLAGS)  -o $@ -c $<
+
+$(BUILD_DIR)/%.o: %.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR)/%.o: $(STARTUP_DIR)/%.s
+	$(AS) -o $@ $<
+
+$(BUILD_DIR):
+	mkdir $(BUILD_DIR)
+
Index: unmerged/zpu_firmware/replay/bootloader
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/bootloader
___________________________________________________________________
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/debug.c
===================================================================
--- unmerged/zpu_firmware/replay/debug.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/debug.c	(revision 1)
@@ -0,0 +1,178 @@
+#include "debug.h"
+#include "pause.h"
+
+#define ATARIBASE = 0x10000;
+int xpos;
+int ypos;
+int onoff; // perhaps we can plot to another address buffer, which we can scroll through in the monitor?
+
+int debugoffsetval;
+
+void topofscreen()
+{
+	xpos = 0;
+	ypos = 0;
+}
+
+void setxpos(int val)
+{
+	xpos = val;
+}
+
+void setypos(int val)
+{
+	ypos = val;
+}
+
+void initdebug(int onoff_in)
+{
+	xpos = 0;
+	ypos = 0;
+	onoff = onoff_in;
+}
+
+void nextline()
+{
+	int i;
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+	for (i=0;i!=40;++i)
+		plot(0,i,ypos);
+
+	//Delay100usX(5000);
+}
+
+unsigned char toatarichar(int val)
+{
+	int inv = val>=128;
+	if (inv)
+	{
+		val-=128;
+	}
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else if (val>=32 && val<=47)
+	{
+		val+=-32;
+	}
+	else
+	{
+		val = 0;
+	}
+	if (inv)
+	{
+		val+=128;
+	}
+	return val;
+}
+unsigned char hextoatarichar(int val)
+{
+	if (val>=0 && val<=9)
+	{
+		val+=+16;	
+	}
+	else if (val>=10 && val<=15)
+	{
+		val+=-10+33;
+	}
+	return val;
+}
+void plot(unsigned char val, int x, int y)
+{
+	if (onoff == 0) return;
+
+	unsigned char volatile * baseaddr = (unsigned char volatile *)(40000 + 0x10000);
+	*(baseaddr + y*40+x) = val+debugoffsetval;
+}
+void debugoffset(int x)
+{
+	debugoffsetval = x;
+}
+void debug(char const * str)
+{
+	while (1)
+	{
+		int val = *str++;
+		if (val==0) break;
+		if (val=='\n') {nextline();continue;};
+
+		plot(toatarichar(val),xpos,ypos);
+		++xpos;
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+	debugoffsetval = 0;
+}
+
+void plotnext(unsigned char val)
+{
+	plot(val,xpos,ypos);
+
+	++xpos;
+	if (xpos==40) nextline();
+}
+
+void plotnextnumber(unsigned short val)
+{
+	plotnext(hextoatarichar((val&0xf000)>>12));
+	plotnext(hextoatarichar((val&0x0f00)>>8));
+	plotnext(hextoatarichar((val&0x00f0)>>4));
+	plotnext(hextoatarichar((val&0x000f)>>0));
+	debugoffsetval = 0;
+}
+
+void hexdump(char const * str, int length)
+{
+	nextline();
+
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		// LH 10 cols = char
+		// RH 20 cols = hex
+
+		plot(toatarichar(val),xpos,ypos);
+		plot(hextoatarichar((val&0xf0) >> 4),xpos*2+20,ypos);
+		plot(hextoatarichar(val&0xf),xpos*2+21,ypos);
+
+		++xpos;
+		if (xpos==10)
+		{
+			nextline();
+		}
+	}
+	nextline();
+}
+
+void hexdump_pure(char const * str, int length)
+{
+	xpos = xpos&0xfffe;
+	for (;length>0;--length)
+	{
+		unsigned char val= *str++;
+		
+		plot(hextoatarichar((val&0xf0) >> 4),xpos++,ypos);
+		plot(hextoatarichar(val&0xf),xpos++,ypos);
+
+		if (xpos==40)
+		{
+			nextline();
+		}
+	}
+}
+
Index: unmerged/zpu_firmware/replay/fat.h
===================================================================
--- unmerged/zpu_firmware/replay/fat.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/fat.h	(revision 1)
@@ -0,0 +1,435 @@
+/*! \file fat.h \brief FAT16/32 file system driver. */
+//*****************************************************************************
+//
+// File Name	: 'fat.h'
+// Title		: FAT16/32 file system driver
+// Author		: Pascal Stang
+// Date			: 11/07/2000
+// Revised		: 12/12/2000
+// Version		: 0.3
+// Target MCU	: ATmega103 (should work for Atmel AVR Series)
+// Editor Tabs	: 4
+//
+// NOTE: This code is currently below version 1.0, and therefore is considered
+// to be lacking in some functionality or documentation, or may not be fully
+// tested.  Nonetheless, you can expect most functions to work.
+//
+///	\ingroup general
+/// \defgroup fat FAT16/32 File System Interface (fat.c)
+/// \code #include "fat.h" \endcode
+/// \par Overview
+///		This FAT16/32 interface allows you to detect and mount FAT16/32
+///		partitions, browse directories and files, and read file data.
+///		The interface is designed to operate with the avrlib IDE/ATA driver.
+///		Reading FAT efficiently requires at least 512+ bytes of RAM so this
+///		interface may not be suitable for processors with less than 1K of RAM.
+///		This interface will properly follow a file's cluster chain so files
+///		need not be defragmented.
+///
+/// \note This code is based in part on work done by Jesper Hansen for his
+///		excellent YAMPP MP3 player project.
+//
+// ----------------------------------------------------------------------------
+// 17.8.2008
+// Bob!k & Raster, C.P.U.
+// Original code was modified especially for the SDrive device. 
+// Some parts of code have been added, removed, rewrited or optimized due to
+// lack of MCU AVR Atmega8 memory.
+// ----------------------------------------------------------------------------
+//
+// This code is distributed under the GNU Public License
+//		which can be found at http://www.gnu.org/licenses/gpl.txt
+//
+//*****************************************************************************
+
+#ifndef FAT_H
+#define FAT_H
+
+#define FALSE 0
+#define TRUE -1
+
+#define DRIVE0 1
+
+// Some useful cluster numbers
+#define MSDOSFSROOT     0		// cluster 0 means the root dir
+#define CLUST_FREE      0               // cluster 0 also means a free cluster
+#define MSDOSFSFREE     CLUST_FREE
+#define CLUST_FIRST     2               // first legal cluster number
+#define CLUST_RSRVD     0xfffffff6      // reserved cluster range
+#define CLUST_BAD       0xfffffff7      // a cluster with a defect
+#define CLUST_EOFS      0xfffffff8      // start of eof cluster range
+#define CLUST_EOFE      0xffffffff      // end of eof cluster range
+
+#define FAT12_MASK      0x00000fff      // mask for 12 bit cluster numbers
+#define FAT16_MASK      0x0000ffff      // mask for 16 bit cluster numbers
+#define FAT32_MASK      0x0fffffff      // mask for FAT32 cluster numbers
+
+
+// Partition Type used in the partition record
+#define PART_TYPE_UNKNOWN		0x00
+#define PART_TYPE_FAT12			0x01
+#define PART_TYPE_XENIX			0x02
+#define PART_TYPE_DOSFAT16		0x04
+#define PART_TYPE_EXTDOS		0x05
+#define PART_TYPE_FAT16			0x06
+#define PART_TYPE_NTFS			0x07
+#define PART_TYPE_FAT32			0x0B
+#define PART_TYPE_FAT32LBA		0x0C
+#define PART_TYPE_FAT16LBA		0x0E
+#define PART_TYPE_EXTDOSLBA		0x0F
+#define PART_TYPE_ONTRACK		0x33
+#define PART_TYPE_NOVELL		0x40
+#define PART_TYPE_PCIX			0x4B
+#define PART_TYPE_PHOENIXSAVE	0xA0
+#define PART_TYPE_CPM			0xDB
+#define PART_TYPE_DBFS			0xE0
+#define PART_TYPE_BBT			0xFF
+
+struct partrecord // length 16 bytes
+{			
+	unsigned char	prIsActive;					// 0x80 indicates active partition
+	unsigned char	prStartHead;				// starting head for partition
+	unsigned short	prStartCylSect;				// starting cylinder and sector
+	unsigned char	prPartType;					// partition type (see above)
+	unsigned char	prEndHead;					// ending head for this partition
+	unsigned short	prEndCylSect;				// ending cylinder and sector
+	unsigned long	prStartLBA;					// first LBA sector for this partition
+	unsigned long	prSize;						// size of this partition (bytes or sectors ?)
+};
+
+        
+struct partsector
+{
+	unsigned char	psPartCode[512-64-2];		// pad so struct is 512b
+	unsigned char	psPart[64];					// four partition records (64 bytes)
+	unsigned char	psBootSectSig0;				// two signature bytes (2 bytes)
+	unsigned char	psBootSectSig1;
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+
+// Format of a boot sector.  This is the first sector on a DOS floppy disk
+// or the first sector of a partition on a hard disk.  But, it is not the
+// first sector of a partitioned hard disk.
+struct bootsector33 {
+	unsigned char 	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[19];					// BIOS parameter block
+	unsigned char	bsDriveNumber;				// drive number (0x80)
+	unsigned char	bsBootCode[479];			// pad so struct is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct extboot {
+	unsigned char	exDriveNumber;				// drive number (0x80)
+	unsigned char	exReserved1;				// reserved
+	unsigned char	exBootSignature;			// ext. boot signature (0x29)
+#define EXBOOTSIG       0x29
+	unsigned char	exVolumeID[4];				// volume ID number
+	unsigned char	exVolumeLabel[11];			// volume label
+	unsigned char	exFileSysType[8];			// fs type (FAT12 or FAT16)
+};
+
+struct bootsector50 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOemName[8];				// OEM name and version
+	unsigned char	bsBPB[25];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[448];			// pad so structure is 512b
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55 
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+};
+
+struct bootsector710 {
+	unsigned char	bsJump[3];					// jump inst E9xxxx or EBxx90
+	unsigned char	bsOEMName[8];				// OEM name and version
+	unsigned char	bsBPB[53];					// BIOS parameter block
+	unsigned char	bsExt[26];					// Bootsector Extension
+	unsigned char	bsBootCode[418];			// pad so structure is 512b
+	unsigned char	bsBootSectSig2;				// 2 & 3 are only defined for FAT32?
+	unsigned char	bsBootSectSig3;
+	unsigned char	bsBootSectSig0;				// boot sector signature byte 0x55
+	unsigned char	bsBootSectSig1;				// boot sector signature byte 0xAA
+#define BOOTSIG0        0x55
+#define BOOTSIG1        0xaa
+#define BOOTSIG2        0
+#define BOOTSIG3        0
+};
+
+
+/***************************************************************/
+/***************************************************************/
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct bpb33 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char    bpbSecPerClust;	// sectors per cluster
+        unsigned short	bpbResSectors;	// number of reserved sectors
+        unsigned char	bpbFATs;		// number of FATs
+        unsigned short	bpbRootDirEnts;	// number of root directory entries
+        unsigned short	bpbSectors;		// total number of sectors
+        unsigned char	bpbMedia;		// media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned short	bpbHiddenSecs;  // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not present in the DOS 3.3 bpb.
+struct bpb50 {
+        unsigned short	bpbBytesPerSec; // bytes per sector
+        unsigned char	bpbSecPerClust; // sectors per cluster
+        unsigned short	bpbResSectors;  // number of reserved sectors
+        unsigned char	bpbFATs;        // number of FATs
+        unsigned short	bpbRootDirEnts; // number of root directory entries
+        unsigned short	bpbSectors;     // total number of sectors
+        unsigned char	bpbMedia;       // media descriptor
+        unsigned short	bpbFATsecs;     // number of sectors per FAT
+        unsigned short	bpbSecPerTrack; // sectors per track
+        unsigned short	bpbHeads;       // number of heads
+        unsigned long	bpbHiddenSecs;  // # of hidden sectors
+// 3.3 compat ends here
+        unsigned long	bpbHugeSectors; // # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32)
+// This one has a few extensions to bpb50.
+struct bpb710 {
+		unsigned short	bpbBytesPerSec;	// bytes per sector
+		unsigned char	bpbSecPerClust;	// sectors per cluster
+		unsigned short	bpbResSectors;	// number of reserved sectors
+		unsigned char	bpbFATs;		// number of FATs
+		unsigned short	bpbRootDirEnts;	// number of root directory entries
+		unsigned short	bpbSectors;		// total number of sectors
+		unsigned char	bpbMedia;		// media descriptor
+		unsigned short	bpbFATsecs;		// number of sectors per FAT
+		unsigned short	bpbSecPerTrack;	// sectors per track
+		unsigned short	bpbHeads;		// number of heads
+		unsigned long	bpbHiddenSecs;	// # of hidden sectors
+// 3.3 compat ends here
+		unsigned long	bpbHugeSectors;	// # of sectors if bpbSectors == 0
+// 5.0 compat ends here
+		unsigned long     bpbBigFATsecs;// like bpbFATsecs for FAT32
+		unsigned short      bpbExtFlags;	// extended flags:
+#define FATNUM    0xf			// mask for numbering active FAT
+#define FATMIRROR 0x80			// FAT is mirrored (like it always was)
+		unsigned short      bpbFSVers;	// filesystem version
+#define FSVERS    0				// currently only 0 is understood
+		unsigned long     bpbRootClust;	// start cluster for root directory
+		unsigned short      bpbFSInfo;	// filesystem info structure sector
+		unsigned short      bpbBackup;	// backup boot sector
+		// There is a 12 byte filler here, but we ignore it
+};
+
+
+// ***************************************************************
+// * byte versions of the above structs                          *
+// ***************************************************************
+
+// BIOS Parameter Block (BPB) for DOS 3.3
+struct byte_bpb33 {
+        unsigned char bpbBytesPerSec[2];		// bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[2];      // number of hidden sectors
+};
+
+// BPB for DOS 5.0
+// The difference is bpbHiddenSecs is a short for DOS 3.3,
+// and bpbHugeSectors is not in the 3.3 bpb.
+struct byte_bpb50 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // number of hidden sectors
+        unsigned char bpbHugeSectors[4];		// # of sectors if bpbSectors == 0
+};
+
+// BPB for DOS 7.10 (FAT32).
+// This one has a few extensions to bpb50.
+struct byte_bpb710 {
+        unsigned char bpbBytesPerSec[2];     // bytes per sector
+        unsigned char bpbSecPerClust;        // sectors per cluster
+        unsigned char bpbResSectors[2];      // number of reserved sectors
+        unsigned char bpbFATs;               // number of FATs
+        unsigned char bpbRootDirEnts[2];     // number of root directory entries
+        unsigned char bpbSectors[2];         // total number of sectors
+        unsigned char bpbMedia;              // media descriptor
+        unsigned char bpbFATsecs[2];         // number of sectors per FAT
+        unsigned char bpbSecPerTrack[2];     // sectors per track
+        unsigned char bpbHeads[2];           // number of heads
+        unsigned char bpbHiddenSecs[4];      // # of hidden sectors
+        unsigned char bpbHugeSectors[4];     // # of sectors if bpbSectors == 0
+        unsigned char bpbBigFATsecs[4];      // like bpbFATsecs for FAT32
+        unsigned char bpbExtFlags[2];        // extended flags:
+        unsigned char bpbFSVers[2];          // filesystem version
+        unsigned char bpbRootClust[4];       // start cluster for root directory
+        unsigned char bpbFSInfo[2];          // filesystem info structure sector
+        unsigned char bpbBackup[2];          // backup boot sector
+        // There is a 12 byte filler here, but we ignore it
+};
+
+// FAT32 FSInfo block.
+struct fsinfo {
+        unsigned char fsisig1[4];
+        unsigned char fsifill1[480];
+        unsigned char fsisig2[4];
+        unsigned char fsinfree[4];
+        unsigned char fsinxtfree[4];
+        unsigned char fsifill2[12];
+        unsigned char fsisig3[4];
+        unsigned char fsifill3[508];
+        unsigned char fsisig4[4];
+};
+
+
+// Structure of a dos directory entry.
+struct direntry {
+		unsigned char		deName[8];      // filename, blank filled
+#define SLOT_EMPTY      0x00            // slot has never been used
+#define SLOT_E5         0x05            // the real value is 0xE5
+#define SLOT_DELETED    0xE5            // file in this slot deleted
+		unsigned char		deExtension[3]; // extension, blank filled
+		unsigned char		deAttributes;   // file attributes
+#define ATTR_NORMAL     0x00            // normal file
+#define ATTR_READONLY   0x01            // file is readonly
+#define ATTR_HIDDEN     0x02            // file is hidden
+#define ATTR_SYSTEM     0x04            // file is a system file
+#define ATTR_VOLUME     0x08            // entry is a volume label
+#define ATTR_LONG_FILENAME	0x0F		// this is a long filename entry			    
+#define ATTR_DIRECTORY  0x10            // entry is a directory name
+#define ATTR_ARCHIVE    0x20            // file is new or modified
+		unsigned char        deLowerCase;    // NT VFAT lower case flags  (set to zero)
+#define LCASE_BASE      0x08            // filename base in lower case
+#define LCASE_EXT       0x10            // filename extension in lower case
+		unsigned char        deCHundredth;   // hundredth of seconds in CTime
+		unsigned char        deCTime[2];     // create time
+		unsigned char        deCDate[2];     // create date
+		unsigned char        deADate[2];     // access date
+		unsigned short        deHighClust; 	// high bytes of cluster number
+		unsigned char        deMTime[2];     // last update time
+		unsigned char        deMDate[2];     // last update date
+		unsigned short        deStartCluster; // starting cluster of file
+		unsigned long       deFileSize;  	// size of file in bytes
+};
+
+// number of directory entries in one sector
+#define DIRENTRIES_PER_SECTOR	0x10
+
+// Structure of a Win95 long name directory entry
+struct winentry {
+		unsigned char		weCnt;			// 
+#define WIN_LAST        0x40
+#define WIN_CNT         0x3f
+		unsigned char		wePart1[10];
+		unsigned char		weAttributes;
+#define ATTR_WIN95      0x0f
+		unsigned char		weReserved1;
+		unsigned char		weChksum;
+		unsigned char		wePart2[12];
+		unsigned short       	weReserved2;
+		unsigned char		wePart3[4];
+};
+
+#define WIN_ENTRY_CHARS	13      // Number of chars per winentry
+
+// Maximum filename length in Win95
+// Note: Must be < sizeof(dirent.d_name)
+#define WIN_MAXLEN      255
+
+// This is the format of the contents of the deTime field in the direntry
+// structure.
+// We don't use bitfields because we don't know how compilers for
+// arbitrary machines will lay them out.
+#define DT_2SECONDS_MASK        0x1F    // seconds divided by 2
+#define DT_2SECONDS_SHIFT       0
+#define DT_MINUTES_MASK         0x7E0   // minutes
+#define DT_MINUTES_SHIFT        5
+#define DT_HOURS_MASK           0xF800  // hours
+#define DT_HOURS_SHIFT          11
+
+// This is the format of the contents of the deDate field in the direntry
+// structure.
+#define DD_DAY_MASK				0x1F	// day of month
+#define DD_DAY_SHIFT			0
+#define DD_MONTH_MASK			0x1E0	// month
+#define DD_MONTH_SHIFT			5
+#define DD_YEAR_MASK			0xFE00	// year - 1980
+#define DD_YEAR_SHIFT			9
+
+
+#define FLAGS_ATRMEDIUMSIZE		0x80
+#define FLAGS_XEXLOADER			0x40
+#define FLAGS_ATRDOUBLESECTORS	0x20
+#define FLAGS_XFDTYPE			0x10
+#define FLAGS_READONLY			0x08
+#define FLAGS_WRITEERROR		0x04
+#define FLAGS_DRIVEON			0x01
+
+// Stuctures
+typedef struct						//2+2+2+2+2+4+1=15
+{
+	unsigned short start_cluster;		//< file starting cluster
+	unsigned short dir_cluster;
+	unsigned short current_cluster;
+	unsigned short ncluster;
+	unsigned short file_index;			//< file index
+	unsigned long size;					//< file size
+	unsigned char flags;				//< file flags
+}virtual_disk_t;
+
+struct FileInfoStruct
+{
+	unsigned char Attr;				//< file attr for last file accessed
+	unsigned short Date;			//< last update date
+	unsigned short Time;			//< last update time
+	unsigned char percomstate;		//=0 default, 1=percomwrite ok (single sectors), 2=percomwrite ok (double sectors), 3=percomwrite bad
+	//
+	virtual_disk_t vDisk;
+};
+
+struct GlobalSystemValues			//4+4+2+2+1=13 bytes
+{
+	unsigned long FirstFATSector;
+	unsigned long FirstDataSector;
+	unsigned short RootDirSectors;
+	unsigned short BytesPerSector;
+	unsigned char SectorsPerCluster;
+};
+
+#define FirstFATSector		GS.FirstFATSector
+#define FirstDataSector		GS.FirstDataSector
+#define RootDirSectors		GS.RootDirSectors
+#define BytesPerSector		GS.BytesPerSector
+#define SectorsPerCluster	GS.SectorsPerCluster
+
+
+unsigned char fatInit();
+unsigned long fatClustToSect(unsigned short clust);
+unsigned char fatChangeDirectory(unsigned short entry);
+unsigned char fatGetDirEntry(unsigned short entry, unsigned char use_long_names);
+unsigned short nextCluster(unsigned short cluster);
+
+#endif
Index: unmerged/zpu_firmware/replay/main.c
===================================================================
--- unmerged/zpu_firmware/replay/main.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/main.c	(revision 1)
@@ -0,0 +1,75 @@
+#include "regs.h"
+#include "led.h"
+
+void
+wait_us(int unsigned num)
+{
+	// 28ish
+	int unsigned cycles = num*28;
+	*zpu_pause = cycles;
+}
+
+void clear_64k_ram()
+{
+	int i=0;
+	// sdram from 8MB to 16MB
+	// sram from 0x200000 
+
+	*zpu_ledr = 0xf0f0f0f0;
+	*zpu_ledg = 0x0;
+	//wait_us(200000);
+	
+	for (i=0x200000; i!=0x210000; i+=1)
+	{
+		// TODO - use short!
+		*(unsigned char volatile *)(i) = 0x0000;
+	}
+
+	*zpu_ledr = 0x55555555;
+	*zpu_ledg = 0x55555555;
+
+	for (i=0x800000; i!=0x810000; i+=4)
+	{
+		*(unsigned int volatile *)(i) = 0x00000000;
+	}
+
+	*zpu_ledr = 0;
+	*zpu_ledg = 0xf0f0f0f0;
+	//wait_us(200000);
+	return;
+}
+
+void reset_6502(unsigned int reset_n)
+{
+	int prev = *zpu_config;
+	if (reset_n == 1)
+		*zpu_config = prev&~(1<<7);
+	else
+		*zpu_config = prev|(1<<7);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+void pause_6502(unsigned int pause)
+{
+	int prev = *zpu_config;
+	if (pause == 0)
+		*zpu_config = prev&~(1<<6);
+	else
+		*zpu_config = prev|(1<<6);
+	// USES ASHIFTLEFT even with it disabled!! *reset_6502 = reset_n<<7;
+}
+
+int main(void)
+{
+	unsigned int i=0;
+	unsigned char temp = 0;
+	pause_6502(1);
+
+		//wait_us(200000);
+		reset_6502(0);
+		*atari_nmien = 0x00;
+		clear_64k_ram();
+		reset_6502(1);
+		pause_6502(0);
+	for(;;);
+}
Index: unmerged/zpu_firmware/replay/pff.c
===================================================================
--- unmerged/zpu_firmware/replay/pff.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/pff.c	(revision 1)
@@ -0,0 +1,1114 @@
+/*----------------------------------------------------------------------------/
+/  Petit FatFs - FAT file system module  R0.02a                (C)ChaN, 2010
+/-----------------------------------------------------------------------------/
+/ Petit FatFs module is an open source software to implement FAT file system to
+/ small embedded systems. This is a free software and is opened for education,
+/ research and commercial developments under license policy of following trems.
+/
+/  Copyright (C) 2010, ChaN, all right reserved.
+/
+/ * The Petit FatFs module is a free software and there is NO WARRANTY.
+/ * No restriction on use. You can use, modify and redistribute it for
+/   personal, non-profit or commercial use UNDER YOUR RESPONSIBILITY.
+/ * Redistributions of source code must retain the above copyright notice.
+/
+/-----------------------------------------------------------------------------/
+/ Jun 15,'09  R0.01a  First release. (Branched from FatFs R0.07b.)
+/
+/ Dec 14,'09  R0.02   Added multiple code page support.
+/                     Added write funciton.
+/                     Changed stream read mode interface.
+/ Dec 07,'10  R0.02a  Added some configuration options.
+/                     Fixed fails to open objects with DBCS character.
+/----------------------------------------------------------------------------*/
+
+#include "pff.h"		/* Petit FatFs configurations and declarations */
+#include "diskio.h"		/* Declarations of low level disk I/O functions */
+
+
+
+/*--------------------------------------------------------------------------
+
+   Module Private Definitions
+
+---------------------------------------------------------------------------*/
+
+
+#if _FS_FAT32
+#define LD_CLUST(dir)	(((DWORD)LD_WORD(dir+DIR_FstClusHI)<<16) | LD_WORD(dir+DIR_FstClusLO))
+#else
+#define LD_CLUST(dir)	LD_WORD(dir+DIR_FstClusLO)
+#endif
+
+
+/*--------------------------------------------------------*/
+/* DBCS code ranges and SBCS extend char conversion table */
+
+#if _CODE_PAGE == 932	/* Japanese Shift-JIS */
+#define _DF1S	0x81	/* DBC 1st byte range 1 start */
+#define _DF1E	0x9F	/* DBC 1st byte range 1 end */
+#define _DF2S	0xE0	/* DBC 1st byte range 2 start */
+#define _DF2E	0xFC	/* DBC 1st byte range 2 end */
+#define _DS1S	0x40	/* DBC 2nd byte range 1 start */
+#define _DS1E	0x7E	/* DBC 2nd byte range 1 end */
+#define _DS2S	0x80	/* DBC 2nd byte range 2 start */
+#define _DS2E	0xFC	/* DBC 2nd byte range 2 end */
+
+#elif _CODE_PAGE == 936	/* Simplified Chinese GBK */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0x80
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 949	/* Korean */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x41
+#define _DS1E	0x5A
+#define _DS2S	0x61
+#define _DS2E	0x7A
+#define _DS3S	0x81
+#define _DS3E	0xFE
+
+#elif _CODE_PAGE == 950	/* Traditional Chinese Big5 */
+#define _DF1S	0x81
+#define _DF1E	0xFE
+#define _DS1S	0x40
+#define _DS1E	0x7E
+#define _DS2S	0xA1
+#define _DS2E	0xFE
+
+#elif _CODE_PAGE == 437	/* U.S. (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 720	/* Arabic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 737	/* Greek (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \
+				0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 775	/* Baltic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 850	/* Multilingual Latin 1 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 852	/* Latin 2 (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF}
+
+#elif _CODE_PAGE == 855	/* Cyrillic (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \
+				0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \
+				0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 857	/* Turkish (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 858	/* Multilingual Latin 1 + Euro (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \
+				0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 862	/* Hebrew (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 866	/* Russian (OEM) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 874	/* Thai (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \
+				0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF}
+
+#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1253 /* Greek (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \
+				0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF}
+
+#elif _CODE_PAGE == 1254 /* Turkish (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F}
+
+#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1256 /* Arabic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF}
+
+#elif _CODE_PAGE == 1257 /* Baltic (Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \
+				0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF}
+
+#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */
+#define _DF1S	0
+#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \
+				0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \
+				0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F}
+
+#elif _CODE_PAGE == 1	/* ASCII (for only non-LFN cfg) */
+#define _DF1S	0
+
+#else
+#error Unknown code page
+
+#endif
+
+
+
+/* Character code support macros */
+
+#define IsUpper(c)	(((c)>='A')&&((c)<='Z'))
+#define IsLower(c)	(((c)>='a')&&((c)<='z'))
+
+#if _DF1S		/* DBCS configuration */
+
+#ifdef _DF2S	/* Two 1st byte areas */
+#define IsDBCS1(c)	(((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E))
+#else			/* One 1st byte area */
+#define IsDBCS1(c)	((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E)
+#endif
+
+#ifdef _DS3S	/* Three 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E))
+#else			/* Two 2nd byte areas */
+#define IsDBCS2(c)	(((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E))
+#endif
+
+#else			/* SBCS configuration */
+
+#define IsDBCS1(c)	0
+#define IsDBCS2(c)	0
+
+#endif /* _DF1S */
+
+
+/* FatFs refers the members in the FAT structures with byte offset instead
+/ of structure member because there are incompatibility of the packing option
+/ between various compilers. */
+
+#define BS_jmpBoot			0
+#define BS_OEMName			3
+#define BPB_BytsPerSec		11
+#define BPB_SecPerClus		13
+#define BPB_RsvdSecCnt		14
+#define BPB_NumFATs			16
+#define BPB_RootEntCnt		17
+#define BPB_TotSec16		19
+#define BPB_Media			21
+#define BPB_FATSz16			22
+#define BPB_SecPerTrk		24
+#define BPB_NumHeads		26
+#define BPB_HiddSec			28
+#define BPB_TotSec32		32
+#define BS_55AA				510
+
+#define BS_DrvNum			36
+#define BS_BootSig			38
+#define BS_VolID			39
+#define BS_VolLab			43
+#define BS_FilSysType		54
+
+#define BPB_FATSz32			36
+#define BPB_ExtFlags		40
+#define BPB_FSVer			42
+#define BPB_RootClus		44
+#define BPB_FSInfo			48
+#define BPB_BkBootSec		50
+#define BS_DrvNum32			64
+#define BS_BootSig32		66
+#define BS_VolID32			67
+#define BS_VolLab32			71
+#define BS_FilSysType32		82
+
+#define MBR_Table			446
+
+#define	DIR_Name			0
+#define	DIR_Attr			11
+#define	DIR_NTres			12
+#define	DIR_CrtTime			14
+#define	DIR_CrtDate			16
+#define	DIR_FstClusHI		20
+#define	DIR_WrtTime			22
+#define	DIR_WrtDate			24
+#define	DIR_FstClusLO		26
+#define	DIR_FileSize		28
+
+
+
+/*--------------------------------------------------------------------------
+
+   Private Functions
+
+---------------------------------------------------------------------------*/
+
+
+static
+FATFS *FatFs;	/* Pointer to the file system object (logical drive) */
+
+
+/* Fill memory */
+static
+void mem_set (void* dst, int val, int cnt) {
+	char *d = (char*)dst;
+	while (cnt--) *d++ = (char)val;
+}
+
+/* Compare memory to memory */
+static
+int mem_cmp (const void* dst, const void* src, int cnt) {
+	const char *d = (const char *)dst, *s = (const char *)src;
+	int r = 0;
+	while (cnt-- && (r = *d++ - *s++) == 0) ;
+	return r;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* FAT access - Read value of a FAT entry                                */
+/*-----------------------------------------------------------------------*/
+
+static
+CLUST get_fat (	/* 1:IO error, Else:Cluster status */
+	CLUST clst	/* Cluster# to get the link information */
+)
+{
+	WORD wc, bc, ofs;
+	BYTE buf[4];
+	FATFS *fs = FatFs;
+
+
+	if (clst < 2 || clst >= fs->n_fatent)	/* Range check */
+		return 1;
+
+	switch (fs->fs_type) {
+#if _FS_FAT12
+	case FS_FAT12 :
+		bc = (WORD)clst; bc += bc / 2;
+		ofs = bc % 512; bc /= 512;
+		if (ofs != 511) {
+			if (disk_readp(buf, fs->fatbase + bc, ofs, 2)) break;
+		} else {
+			if (disk_readp(buf, fs->fatbase + bc, 511, 1)) break;
+			if (disk_readp(buf+1, fs->fatbase + bc + 1, 0, 1)) break;
+		}
+		wc = LD_WORD(buf);
+		return (clst & 1) ? (wc >> 4) : (wc & 0xFFF);
+#endif
+	case FS_FAT16 :
+		if (disk_readp(buf, fs->fatbase + clst / 256, (WORD)(((WORD)clst % 256) * 2), 2)) break;
+		return LD_WORD(buf);
+#if _FS_FAT32
+	case FS_FAT32 :
+		if (disk_readp(buf, fs->fatbase + clst / 128, (WORD)(((WORD)clst % 128) * 4), 4)) break;
+		return LD_DWORD(buf) & 0x0FFFFFFF;
+#endif
+	}
+
+	return 1;	/* An error occured at the disk I/O layer */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get sector# from cluster#                                             */
+/*-----------------------------------------------------------------------*/
+
+static
+DWORD clust2sect (	/* !=0: Sector number, 0: Failed - invalid cluster# */
+	CLUST clst		/* Cluster# to be converted */
+)
+{
+	FATFS *fs = FatFs;
+
+
+	clst -= 2;
+	if (clst >= (fs->n_fatent - 2)) return 0;		/* Invalid cluster# */
+	return (DWORD)clst * fs->csize + fs->database;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Rewind directory index                           */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_rewind (
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	FATFS *fs = FatFs;
+
+
+	dj->index = 0;
+	clst = dj->sclust;
+	if (clst == 1 || clst >= fs->n_fatent)	/* Check start cluster range */
+		return FR_DISK_ERR;
+	if (_FS_FAT32 && !clst && fs->fs_type == FS_FAT32)	/* Replace cluster# 0 with root cluster# if in FAT32 */
+		clst = (CLUST)fs->dirbase;
+	dj->clust = clst;						/* Current cluster */
+	dj->sect = clst ? clust2sect(clst) : fs->dirbase;	/* Current sector */
+
+	return FR_OK;	/* Seek succeeded */
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Move directory index next                        */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_next (	/* FR_OK:Succeeded, FR_NO_FILE:End of table */
+	DIR *dj			/* Pointer to directory object */
+)
+{
+	CLUST clst;
+	WORD i;
+	FATFS *fs = FatFs;
+
+
+	i = dj->index + 1;
+	if (!i || !dj->sect)	/* Report EOT when index has reached 65535 */
+		return FR_NO_FILE;
+
+	if (!(i % 16)) {		/* Sector changed? */
+		dj->sect++;			/* Next sector */
+
+		if (dj->clust == 0) {	/* Static table */
+			if (i >= fs->n_rootdir)	/* Report EOT when end of table */
+				return FR_NO_FILE;
+		}
+		else {					/* Dynamic table */
+			if (((i / 16) & (fs->csize-1)) == 0) {	/* Cluster changed? */
+				clst = get_fat(dj->clust);		/* Get next cluster */
+				if (clst <= 1) return FR_DISK_ERR;
+				if (clst >= fs->n_fatent)		/* When it reached end of dynamic table */
+					return FR_NO_FILE;			/* Report EOT */
+				dj->clust = clst;				/* Initialize data for new cluster */
+				dj->sect = clust2sect(clst);
+			}
+		}
+	}
+
+	dj->index = i;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Directory handling - Find an object in the directory                  */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT dir_find (
+	DIR *dj,		/* Pointer to the directory object linked to the file name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE c;
+
+
+	res = dir_rewind(dj);			/* Rewind directory object */
+	if (res != FR_OK) return res;
+
+	do {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];	/* First character */
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dj->fn, 11)) /* Is it a valid entry? */
+			break;
+		res = dir_next(dj);					/* Next entry */
+	} while (res == FR_OK);
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read an object from the directory                                     */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+FRESULT dir_read (
+	DIR *dj,		/* Pointer to the directory object to store read object name */
+	BYTE *dir		/* 32-byte working buffer */
+)
+{
+	FRESULT res;
+	BYTE a, c;
+
+
+	res = FR_NO_FILE;
+	while (dj->sect) {
+		res = disk_readp(dir, dj->sect, (WORD)((dj->index % 16) * 32), 32)	/* Read an entry */
+			? FR_DISK_ERR : FR_OK;
+		if (res != FR_OK) break;
+		c = dir[DIR_Name];
+		if (c == 0) { res = FR_NO_FILE; break; }	/* Reached to end of table */
+		a = dir[DIR_Attr] & AM_MASK;
+		if (c != 0xE5 && c != '.' && !(a & AM_VOL))	/* Is it a valid entry? */
+			break;
+		res = dir_next(dj);			/* Next entry */
+		if (res != FR_OK) break;
+	}
+
+	if (res != FR_OK) dj->sect = 0;
+
+	return res;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Pick a segment and create the object name in directory form           */
+/*-----------------------------------------------------------------------*/
+
+#ifdef _EXCVT
+	static const BYTE cvt[] = _EXCVT;
+#endif
+
+static
+FRESULT create_name (
+	DIR *dj,			/* Pointer to the directory object */
+	const char **path	/* Pointer to pointer to the segment in the path string */
+)
+{
+	BYTE c, d, ni, si, i, *sfn;
+	const char *p;
+
+	/* Create file name in directory form */
+	sfn = dj->fn;
+	mem_set(sfn, ' ', 11);
+	si = i = 0; ni = 8;
+	p = *path;
+	for (;;) {
+		c = p[si++];
+		if (c <= ' ' || c == '/') break;	/* Break on end of segment */
+		if (c == '.' || i >= ni) {
+			if (ni != 8 || c != '.') break;
+			i = 8; ni = 11;
+			continue;
+		}
+#ifdef _EXCVT
+		if (c >= 0x80)					/* To upper extended char (SBCS) */
+			c = cvt[c - 0x80];
+#endif
+		if (IsDBCS1(c) && i < ni - 1) {	/* DBC 1st byte? */
+			d = p[si++];				/* Get 2nd byte */
+			sfn[i++] = c;
+			sfn[i++] = d;
+		} else {						/* Single byte code */
+			if (IsLower(c)) c -= 0x20;	/* toupper */
+			sfn[i++] = c;
+		}
+	}
+	*path = &p[si];						/* Rerurn pointer to the next segment */
+
+	sfn[11] = (c <= ' ') ? 1 : 0;		/* Set last segment flag if end of path */
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Get file information from directory entry                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+static
+void get_fileinfo (		/* No return code */
+	DIR *dj,			/* Pointer to the directory object */
+	BYTE *dir,			/* 32-byte working buffer */
+	FILINFO *fno	 	/* Pointer to store the file information */
+)
+{
+	BYTE i, c;
+	char *p;
+
+
+	p = fno->fname;
+	if (dj->sect) {
+		for (i = 0; i < 8; i++) {	/* Copy file name body */
+			c = dir[i];
+			if (c == ' ') break;
+			if (c == 0x05) c = 0xE5;
+			*p++ = c;
+		}
+		if (dir[8] != ' ') {		/* Copy file name extension */
+			*p++ = '.';
+			for (i = 8; i < 11; i++) {
+				c = dir[i];
+				if (c == ' ') break;
+				*p++ = c;
+			}
+		}
+		fno->fattrib = dir[DIR_Attr];				/* Attribute */
+		fno->fsize = LD_DWORD(dir+DIR_FileSize);	/* Size */
+		fno->fdate = LD_WORD(dir+DIR_WrtDate);		/* Date */
+		fno->ftime = LD_WORD(dir+DIR_WrtTime);		/* Time */
+	}
+	*p = 0;
+}
+#endif /* _USE_DIR */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Follow a file path                                                    */
+/*-----------------------------------------------------------------------*/
+
+static
+FRESULT follow_path (	/* FR_OK(0): successful, !=0: error code */
+	DIR *dj,			/* Directory object to return last directory and found object */
+	BYTE *dir,			/* 32-byte working buffer */
+	const char *path	/* Full-path string to find a file or directory */
+)
+{
+	FRESULT res;
+
+
+	while (*path == ' ') path++;		/* Skip leading spaces */
+	if (*path == '/') path++;			/* Strip heading separator */
+	dj->sclust = 0;						/* Set start directory (always root dir) */
+
+	if ((BYTE)*path <= ' ') {			/* Null path means the root directory */
+		res = dir_rewind(dj);
+		dir[0] = 0;
+
+	} else {							/* Follow path */
+		for (;;) {
+			res = create_name(dj, &path);	/* Get a segment */
+			if (res != FR_OK) break;
+			res = dir_find(dj, dir);		/* Find it */
+			if (res != FR_OK) {				/* Could not find the object */
+				if (res == FR_NO_FILE && !*(dj->fn+11))
+					res = FR_NO_PATH;
+				break;
+			}
+			if (*(dj->fn+11)) break;		/* Last segment match. Function completed. */
+			if (!(dir[DIR_Attr] & AM_DIR)) { /* Cannot follow because it is a file */
+				res = FR_NO_PATH; break;
+			}
+			dj->sclust = LD_CLUST(dir);
+		}
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Check a sector if it is an FAT boot record                            */
+/*-----------------------------------------------------------------------*/
+
+static
+BYTE check_fs (	/* 0:The FAT boot record, 1:Valid boot record but not an FAT, 2:Not a boot record, 3:Error */
+	BYTE *buf,	/* Working buffer */
+	DWORD sect	/* Sector# (lba) to check if it is an FAT boot record or not */
+)
+{
+	if (disk_readp(buf, sect, 510, 2))		/* Read the boot sector */
+		return 3;
+	if (LD_WORD(buf) != 0xAA55)				/* Check record signature */
+		return 2;
+
+	if (!disk_readp(buf, sect, BS_FilSysType, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT12/16 */
+		return 0;
+	if (_FS_FAT32 && !disk_readp(buf, sect, BS_FilSysType32, 2) && LD_WORD(buf) == 0x4146)	/* Check FAT32 */
+		return 0;
+	return 1;
+}
+
+
+
+
+/*--------------------------------------------------------------------------
+
+   Public Functions
+
+--------------------------------------------------------------------------*/
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Mount/Unmount a Locical Drive                                         */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_mount (
+	FATFS *fs		/* Pointer to new file system object (NULL: Unmount) */
+)
+{
+	BYTE fmt, buf[36];
+	DWORD bsect, fsize, tsect, mclst;
+
+
+	FatFs = 0;
+	if (!fs) return FR_OK;				/* Unregister fs object */
+
+	if (disk_initialize() & STA_NOINIT)	/* Check if the drive is ready or not */
+		return FR_NOT_READY;
+
+	/* Search FAT partition on the drive */
+	bsect = 0;
+	fmt = check_fs(buf, bsect);			/* Check sector 0 as an SFD format */
+	if (fmt == 1) {						/* Not an FAT boot record, it may be FDISK format */
+		/* Check a partition listed in top of the partition table */
+		if (disk_readp(buf, bsect, MBR_Table, 16)) {	/* 1st partition entry */
+			fmt = 3;
+		} else {
+			if (buf[4]) {					/* Is the partition existing? */
+				bsect = LD_DWORD(&buf[8]);	/* Partition offset in LBA */
+				fmt = check_fs(buf, bsect);	/* Check the partition */
+			}
+		}
+	}
+	if (fmt == 3) return FR_DISK_ERR;
+	if (fmt) return FR_NO_FILESYSTEM;	/* No valid FAT patition is found */
+
+	/* Initialize the file system object */
+	if (disk_readp(buf, bsect, 13, sizeof(buf))) return FR_DISK_ERR;
+
+	fsize = LD_WORD(buf+BPB_FATSz16-13);				/* Number of sectors per FAT */
+	if (!fsize) fsize = LD_DWORD(buf+BPB_FATSz32-13);
+
+	fsize *= buf[BPB_NumFATs-13];						/* Number of sectors in FAT area */
+	fs->fatbase = bsect + LD_WORD(buf+BPB_RsvdSecCnt-13); /* FAT start sector (lba) */
+	fs->csize = buf[BPB_SecPerClus-13];					/* Number of sectors per cluster */
+	fs->n_rootdir = LD_WORD(buf+BPB_RootEntCnt-13);		/* Nmuber of root directory entries */
+	tsect = LD_WORD(buf+BPB_TotSec16-13);				/* Number of sectors on the file system */
+	if (!tsect) tsect = LD_DWORD(buf+BPB_TotSec32-13);
+	mclst = (tsect						/* Last cluster# + 1 */
+		- LD_WORD(buf+BPB_RsvdSecCnt-13) - fsize - fs->n_rootdir / 16
+		) / fs->csize + 2;
+	fs->n_fatent = (CLUST)mclst;
+
+	fmt = FS_FAT16;							/* Determine the FAT sub type */
+	if (mclst < 0xFF7) 						/* Number of clusters < 0xFF5 */
+#if _FS_FAT12
+		fmt = FS_FAT12;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+	if (mclst >= 0xFFF7)					/* Number of clusters >= 0xFFF5 */
+#if _FS_FAT32
+		fmt = FS_FAT32;
+#else
+		return FR_NO_FILESYSTEM;
+#endif
+
+	fs->fs_type = fmt;		/* FAT sub-type */
+	if (_FS_FAT32 && fmt == FS_FAT32)
+		fs->dirbase = LD_DWORD(buf+(BPB_RootClus-13));	/* Root directory start cluster */
+	else
+		fs->dirbase = fs->fatbase + fsize;				/* Root directory start sector (lba) */
+	fs->database = fs->fatbase + fsize + fs->n_rootdir / 16;	/* Data start sector (lba) */
+
+	fs->flag = 0;
+	FatFs = fs;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Open or Create a File                                                 */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_open (
+	const char *path	/* Pointer to the file name */
+)
+{
+	FRESULT res;
+	DIR dj;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs)						/* Check file system */
+		return FR_NOT_ENABLED;
+
+	fs->flag = 0;
+	dj.fn = sp;
+	res = follow_path(&dj, dir, path);	/* Follow the file path */
+	if (res != FR_OK) return res;		/* Follow failed */
+	if (!dir[0] || (dir[DIR_Attr] & AM_DIR))	/* It is a directory */
+		return FR_NO_FILE;
+
+	fs->org_clust = LD_CLUST(dir);			/* File start cluster */
+	fs->fsize = LD_DWORD(dir+DIR_FileSize);	/* File size */
+	fs->fptr = 0;						/* File pointer */
+	fs->flag = FA_OPENED;
+
+	return FR_OK;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read File                                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_READ
+
+FRESULT pf_read (
+	void* buff,		/* Pointer to the read buffer (NULL:Forward data to the stream)*/
+	WORD btr,		/* Number of bytes to read */
+	WORD* br		/* Pointer to number of bytes read */
+)
+{
+	DRESULT dr;
+	CLUST clst;
+	DWORD sect, remain;
+	WORD rcnt;
+	BYTE cs, *rbuff = buff;
+	FATFS *fs = FatFs;
+
+
+	*br = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	remain = fs->fsize - fs->fptr;
+	if (btr > remain) btr = (WORD)remain;			/* Truncate btr by remaining bytes */
+
+	while (btr)	{									/* Repeat until all data transferred */
+		if ((fs->fptr % 512) == 0) {				/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fr_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fr_abort;
+			fs->dsect = sect + cs;
+		}
+		rcnt = (WORD)(512 - (fs->fptr % 512));		/* Get partial sector data from sector buffer */
+		if (rcnt > btr) rcnt = btr;
+		dr = disk_readp(!buff ? 0 : rbuff, fs->dsect, (WORD)(fs->fptr % 512), rcnt);
+		if (dr) goto fr_abort;
+		fs->fptr += rcnt; rbuff += rcnt;			/* Update pointers and counters */
+		btr -= rcnt; *br += rcnt;
+	}
+
+	return FR_OK;
+
+fr_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write File                                                            */
+/*-----------------------------------------------------------------------*/
+#if _USE_WRITE
+
+FRESULT pf_write (
+	const void* buff,	/* Pointer to the data to be written */
+	WORD btw,			/* Number of bytes to write (0:Finalize the current write operation) */
+	WORD* bw			/* Pointer to number of bytes written */
+)
+{
+	CLUST clst;
+	DWORD sect, remain;
+	const BYTE *p = buff;
+	BYTE cs;
+	WORD wcnt;
+	FATFS *fs = FatFs;
+
+
+	*bw = 0;
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+		return FR_NOT_OPENED;
+
+	if (!btw) {		/* Finalize request */
+		if ((fs->flag & FA__WIP) && disk_writep(0, 0)) goto fw_abort;
+		fs->flag &= ~FA__WIP;
+		return FR_OK;
+	} else {		/* Write data request */
+		if (!(fs->flag & FA__WIP))		/* Round-down fptr to the sector boundary */
+			fs->fptr &= 0xFFFFFE00;
+	}
+	remain = fs->fsize - fs->fptr;
+	if (btw > remain) btw = (WORD)remain;			/* Truncate btw by remaining bytes */
+
+	while (btw)	{									/* Repeat until all data transferred */
+		if (((WORD)fs->fptr % 512) == 0) {			/* On the sector boundary? */
+			cs = (BYTE)(fs->fptr / 512 & (fs->csize - 1));	/* Sector offset in the cluster */
+			if (!cs) {								/* On the cluster boundary? */
+				clst = (fs->fptr == 0) ?			/* On the top of the file? */
+					fs->org_clust : get_fat(fs->curr_clust);
+				if (clst <= 1) goto fw_abort;
+				fs->curr_clust = clst;				/* Update current cluster */
+			}
+			sect = clust2sect(fs->curr_clust);		/* Get current sector */
+			if (!sect) goto fw_abort;
+			fs->dsect = sect + cs;
+			if (disk_writep(0, fs->dsect)) goto fw_abort;	/* Initiate a sector write operation */
+			fs->flag |= FA__WIP;
+		}
+		wcnt = 512 - ((WORD)fs->fptr % 512);		/* Number of bytes to write to the sector */
+		if (wcnt > btw) wcnt = btw;
+		if (disk_writep(p, wcnt)) goto fw_abort;	/* Send data to the sector */
+		fs->fptr += wcnt; p += wcnt;				/* Update pointers and counters */
+		btw -= wcnt; *bw += wcnt;
+		if (((WORD)fs->fptr % 512) == 0) {
+			if (disk_writep(0, 0)) goto fw_abort;	/* Finalize the currtent secter write operation */
+			fs->flag &= ~FA__WIP;
+		}
+	}
+
+	return FR_OK;
+
+fw_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Seek File R/W Pointer                                                 */
+/*-----------------------------------------------------------------------*/
+#if _USE_LSEEK
+
+FRESULT pf_lseek (
+	DWORD ofs		/* File pointer from top of file */
+)
+{
+	CLUST clst;
+	DWORD bcs, sect, ifptr;
+	FATFS *fs = FatFs;
+
+
+	if (!fs) return FR_NOT_ENABLED;		/* Check file system */
+	if (!(fs->flag & FA_OPENED))		/* Check if opened */
+			return FR_NOT_OPENED;
+
+	if (ofs > fs->fsize) ofs = fs->fsize;	/* Clip offset with the file size */
+	ifptr = fs->fptr;
+	fs->fptr = 0;
+	if (ofs > 0) {
+		bcs = (DWORD)fs->csize * 512;	/* Cluster size (byte) */
+		if (ifptr > 0 &&
+			(ofs - 1) / bcs >= (ifptr - 1) / bcs) {	/* When seek to same or following cluster, */
+			fs->fptr = (ifptr - 1) & ~(bcs - 1);	/* start from the current cluster */
+			ofs -= fs->fptr;
+			clst = fs->curr_clust;
+		} else {							/* When seek to back cluster, */
+			clst = fs->org_clust;			/* start from the first cluster */
+			fs->curr_clust = clst;
+		}
+		while (ofs > bcs) {				/* Cluster following loop */
+			clst = get_fat(clst);		/* Follow cluster chain */
+			if (clst <= 1 || clst >= fs->n_fatent) goto fe_abort;
+			fs->curr_clust = clst;
+			fs->fptr += bcs;
+			ofs -= bcs;
+		}
+		fs->fptr += ofs;
+		sect = clust2sect(clst);		/* Current sector */
+		if (!sect) goto fe_abort;
+		fs->dsect = sect + (fs->fptr / 512 & (fs->csize - 1));
+	}
+
+	return FR_OK;
+
+fe_abort:
+	fs->flag = 0;
+	return FR_DISK_ERR;
+}
+#endif
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Create a Directroy Object                                             */
+/*-----------------------------------------------------------------------*/
+#if _USE_DIR
+
+FRESULT pf_opendir (
+	DIR *dj,			/* Pointer to directory object to create */
+	const char *path	/* Pointer to the directory path */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		res = follow_path(dj, dir, path);		/* Follow the path to the directory */
+		if (res == FR_OK) {						/* Follow completed */
+			if (dir[0]) {						/* It is not the root dir */
+				if (dir[DIR_Attr] & AM_DIR)		/* The object is a directory */
+					dj->sclust = LD_CLUST(dir);
+				else							/* The object is not a directory */
+					res = FR_NO_PATH;
+			}
+			if (res == FR_OK)
+				res = dir_rewind(dj);			/* Rewind dir */
+		}
+		if (res == FR_NO_FILE) res = FR_NO_PATH;
+	}
+
+	return res;
+}
+
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Directory Entry in Sequense                                      */
+/*-----------------------------------------------------------------------*/
+
+FRESULT pf_readdir (
+	DIR *dj,			/* Pointer to the open directory object */
+	FILINFO *fno		/* Pointer to file information to return */
+)
+{
+	FRESULT res;
+	BYTE sp[12], dir[32];
+	FATFS *fs = FatFs;
+
+
+	if (!fs) {				/* Check file system */
+		res = FR_NOT_ENABLED;
+	} else {
+		dj->fn = sp;
+		if (!fno) {
+			res = dir_rewind(dj);
+		} else {
+			res = dir_read(dj, dir);
+			if (res == FR_NO_FILE) {
+				dj->sect = 0;
+				res = FR_OK;
+			}
+			if (res == FR_OK) {				/* A valid entry is found */
+				get_fileinfo(dj, dir, fno);	/* Get the object information */
+				res = dir_next(dj);			/* Increment index for next */
+				if (res == FR_NO_FILE) {
+					dj->sect = 0;
+					res = FR_OK;
+				}
+			}
+		}
+	}
+
+	return res;
+}
+
+#endif /* _USE_DIR */
+
Index: unmerged/zpu_firmware/replay/rom_epilogue.vhd
===================================================================
--- unmerged/zpu_firmware/replay/rom_epilogue.vhd	(nonexistent)
+++ unmerged/zpu_firmware/replay/rom_epilogue.vhd	(revision 1)
@@ -0,0 +1 @@
+END; 
Index: unmerged/zpu_firmware/replay/stuff.c
===================================================================
--- unmerged/zpu_firmware/replay/stuff.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/stuff.c	(revision 1)
@@ -0,0 +1,13 @@
+#include "regs.h"
+#include "regs.c"
+#include "main.c"
+#include "fat.c" 
+#include "SDrive.c"
+#include "mmc.c"
+#include "spi.c"
+#include "uart.c"
+#include "led.c"
+#include "pind.c" 
+#include "eeprom.c"
+#include "pause.c"
+
Index: unmerged/zpu_firmware/replay/uart.h
===================================================================
--- unmerged/zpu_firmware/replay/uart.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/uart.h	(revision 1)
@@ -0,0 +1,23 @@
+#ifndef UART_H
+#define UART_H
+
+#include "types.h"
+
+// Might be simplest to use another Pokey as the UART...
+
+void USART_Init( u08 value ); // value is baud rate
+// must flush too
+
+void USART_Transmit_Byte( unsigned char data );
+unsigned char USART_Receive_Byte( void );
+
+int USART_Data_Ready();
+
+void USART_Transmit_Mode();
+void USART_Receive_Mode();
+
+int USART_Framing_Error();
+
+void USART_Wait_Transmit_Complete();
+
+#endif
Index: unmerged/zpu_firmware/replay/types.h
===================================================================
--- unmerged/zpu_firmware/replay/types.h	(nonexistent)
+++ unmerged/zpu_firmware/replay/types.h	(revision 1)
@@ -0,0 +1,13 @@
+#ifndef types_h
+#define types_h
+
+typedef unsigned char u08;
+typedef unsigned char uint8_t;
+typedef unsigned short u16;
+typedef unsigned int u32;
+
+#define EEMEM
+
+#endif
+
+
Index: unmerged/zpu_firmware/replay/zpuromgen.c
===================================================================
--- unmerged/zpu_firmware/replay/zpuromgen.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/zpuromgen.c	(revision 1)
@@ -0,0 +1,59 @@
+// zpuromgen.c
+//
+// Program to turn a binary file into a VHDL lookup table.
+//   by Adam Pierce
+//   29-Feb-2008
+//
+// This software is free to use by anyone for any purpose.
+//
+
+#include <unistd.h>
+#include <stdio.h>
+
+typedef unsigned char BYTE;
+
+main(int argc, char **argv)
+{
+       BYTE    opcode[4];
+       int     fd;
+       int     addr = 0;
+       ssize_t s;
+
+// Check the user has given us an input file.
+       if(argc < 2)
+       {
+               printf("Usage: %s <binary_file>\n\n", argv[0]);
+               return 1;
+       }
+
+// Open the input file.
+       fd = open(argv[1], 0);
+       if(fd == -1)
+       {
+               perror("File Open");
+               return 2;
+       }
+
+       while(1)
+       {
+       // Read 32 bits.
+               s = read(fd, opcode, 4);
+               if(s == -1)
+               {
+                       perror("File read");
+                       return 3;
+               }
+
+               if(s == 0)
+                       break; // End of file.
+
+       // Output to STDOUT.
+               printf("%04x : %02x%02x%02x%02x;\n",
+                      addr++, opcode[0], opcode[1],
+                      opcode[2], opcode[3]);
+       }
+
+       close(fd);
+       return 0;
+}
+
Index: unmerged/zpu_firmware/replay/test.c
===================================================================
--- unmerged/zpu_firmware/replay/test.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/test.c	(revision 1)
@@ -0,0 +1,71 @@
+
+
+unsigned char toatarichar(int val)
+{
+	if (val>='A' && val<='Z')
+	{
+		val+=-'A'+33;
+	}
+	else if (val>='a' && val<='z')
+	{
+		val+=-'a'+33+64;
+	}
+	else if (val>='0' && val<='9')
+	{
+		val+=-'0'+16;	
+	}
+	else
+	{
+		val = 0;
+	}
+	return val;
+}
+
+int xpos = 0;
+int ypos = 0;
+
+void nextline()
+{
+	xpos=0;
+	ypos+=1;
+	if (ypos==24)
+		ypos = 0;
+}
+void plot(unsigned char a, int x, int y)
+{
+	printf("%d %d %d\n",a,x,y);
+}
+
+void debug(char const * str)
+{
+//        char buffer[256];
+//        buffer[0] = 'W';
+//        buffer[1] = 'T';
+//        buffer[2] = 'F';
+//        buffer[3] = 0;
+//        str = buffer;
+
+        while (1)
+        {
+                int val = *str++;
+                if (val==0) break;
+
+                plot(toatarichar(val),xpos,ypos);
+                ++xpos;
+                if (xpos==40)
+                {
+                        nextline();
+                }
+        }
+        nextline();
+        //Delay100usX(10000);
+}
+
+
+int main(void)
+{
+	printf("%d %d\n", 'H', toatarichar('H'));
+	debug("Goodbye sweet world!");
+	return 0;
+}
+
Index: unmerged/zpu_firmware/replay/zpuromgen
===================================================================
Cannot display: file marked as a binary type.
svn:mime-type = application/octet-stream

Property changes on: unmerged/zpu_firmware/replay/zpuromgen
___________________________________________________________________
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Added: svn:mime-type
## -0,0 +1 ##
+application/octet-stream
\ No newline at end of property
Index: unmerged/zpu_firmware/replay/uart.c
===================================================================
--- unmerged/zpu_firmware/replay/uart.c	(nonexistent)
+++ unmerged/zpu_firmware/replay/uart.c	(revision 1)
@@ -0,0 +1,103 @@
+#include "uart.h"
+
+#include "regs.h"
+
+void actions();
+
+int USART_Data_Needed()
+{
+	int needed = 0==(0x10&(*zpu_pokey_irqen));
+	if (needed)
+	{
+		*zpu_pokey_irqen = 0x28;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return needed;
+}
+
+int USART_Data_Ready()
+{
+	int ready = 0==(0x20&(*zpu_pokey_irqen));
+	if (ready)
+	{
+		*zpu_pokey_irqen = 0x18;
+		*zpu_pokey_irqen = 0x38;
+	}
+	return ready;
+}
+
+void USART_Init( u08 value )
+{
+	// value is pokey div + 6
+	*zpu_pokey_skctl = 0;
+	wait_us(10);
+	USART_Receive_Mode(); // turn of reset and listen to commands
+	*zpu_pokey_audctl = 0x78; // linked channels, fast clocked
+	*zpu_pokey_audf1 = 0x00;
+	*zpu_pokey_audf0 = value-6;
+	*zpu_pokey_audf3 = 0x00;
+	*zpu_pokey_audf2 = value-6;
+
+	*zpu_pokey_irqen = 0x00;
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Transmit_Byte( unsigned char data )
+{
+	*zpu_pokey_serout = data;
+
+	// wait until next byte is needed 
+	while (!USART_Data_Needed());
+}
+unsigned char USART_Receive_Byte( void )
+{
+	// wait for data
+	while (!USART_Data_Ready())
+	{
+		actions();
+	}
+
+	u08 res = *zpu_pokey_serout; //serin at same address
+	return res;
+}
+
+void USART_Transmit_Mode()
+{
+	*zpu_pokey_skctl = 0x23; // 010 for transmission
+	*zpu_pokey_skrest = 0xff;
+	*zpu_pokey_irqen = 0x28; // clear data needed
+	*zpu_pokey_irqen = 0x38;
+}
+
+void USART_Receive_Mode()
+{
+	*zpu_pokey_skctl = 0x13; // 001 for receiving
+	*zpu_pokey_skrest = 0xff;
+}
+
+int USART_Framing_Error()
+{
+	if (0xc0&(*zpu_pokey_skctl))
+	{
+		return 0;
+	}
+	else
+	{
+		return 1;
+	}
+}
+
+void USART_Wait_Transmit_Complete()
+{
+	while (1)
+	{
+		int ready = 0==(0x08&(*zpu_pokey_irqen));
+		if (ready)
+		{
+			*zpu_pokey_irqen = 0x30;
+			*zpu_pokey_irqen = 0x38;
+			return;
+		}
+	}
+}
+
