Activity
From 03/25/2016 to 04/23/2016
04/23/2016
- 03:28 PM EclaireXL Revision 451 (repo2): Added testbenches. Do not respond to bus cycles that do not target the cart
04/22/2016
- 11:11 PM EclaireXL Revision 450 (repo2): sram model for tb
- 10:28 PM EclaireXL Revision 449 (repo2): Moved memory timing bridge inside slave_timing, its an internal detail really
04/21/2016
- 11:02 PM EclaireXL Revision 448 (repo2): Adjusted delays and verified in sim
- 10:02 PM EclaireXL Revision 447 (repo2): Trivial but important fixes, thanks to quartus warnings
- 09:55 PM EclaireXL Revision 446 (repo2): 70ns accuracy is not enough for reliable Atari bus sampling, use faster clock we are already using for sram
04/19/2016
- 11:13 PM EclaireXL Revision 445 (repo2): Register bus_data before we write it
- 11:13 PM EclaireXL Revision 444 (repo2): Fixed c0 decode and made more explicit
04/18/2016
- 10:33 PM EclaireXL Revision 443 (repo2): Simulated and repaired 6502 bus and sram bus
04/16/2016
- 04:31 PM EclaireXL Revision 442 (repo2): constraint all cart input/outputs - 1.79MHz so not a problem. Improve sram constraints - including adding a bit of hold time.
- 04:29 PM EclaireXL Revision 441 (repo2): register output data
- 04:28 PM EclaireXL Revision 440 (repo2): Missed commit
- 03:27 PM EclaireXL Revision 439 (repo2): Simulated/corrected sram back-back write timings
- 12:33 PM EclaireXL Revision 438 (repo2): First cut implementation of veronica clone for ultimate cart - does not work yet, but getting close. Project to try out Rob Finchs 65816 core.
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