Analysis & Synthesis report for pokeymax Fri Jun 19 21:55:42 2026 Quartus Prime Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Analysis & Synthesis Default Parameter Settings 5. Parallel Compilation 6. Analysis & Synthesis Source Files Read 7. Analysis & Synthesis Resource Usage Summary 8. Analysis & Synthesis Resource Utilization by Entity 9. Analysis & Synthesis IP Cores Summary 10. Registers Removed During Synthesis 11. Removed Registers Triggering Further Register Optimizations 12. General Register Statistics 13. Inverted Register Statistics 14. Multiplexer Restructuring Statistics (Restructuring Performed) 15. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i 16. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i 17. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i 18. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i 19. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i 20. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i 21. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i 22. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i 23. Parameter Settings for User Entity Instance: Top-level Entity: |pokeymax 24. Parameter Settings for User Entity Instance: int_osc:oscillator|altera_int_osc:int_osc_0 25. Parameter Settings for User Entity Instance: pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component 26. Parameter Settings for User Entity Instance: pll_reset_sync:pll_sync 27. Parameter Settings for User Entity Instance: slave_timing_6502:bus_adapt 28. Parameter Settings for User Entity Instance: pokey:pokey1 29. Parameter Settings for User Entity Instance: pokey:pokey1|complete_address_decoder:decode_addr1 30. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf0_delay 31. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf1_delay 32. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf2_delay 33. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf3_delay 34. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audctl_delay 35. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0 36. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay 37. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1 38. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay 39. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2 40. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay 41. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3 42. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay 43. Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:twotone_del 44. Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:stimer_delay 45. Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_64_div 46. Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_15_div 47. Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serout_clock_delay 48. Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serin_clock_delay 49. Parameter Settings for User Entity Instance: dc_blocker:pokey1_dc_blocker 50. Parameter Settings for User Entity Instance: complete_address_decoder:\gen_config:decode_addr1 51. Parameter Settings for User Entity Instance: sigmadelta_dither:dac_dithergen 52. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0 53. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2 54. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3 55. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst 56. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i 57. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i 58. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i 59. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i 60. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i 61. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i 62. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i 63. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i 64. altpll Parameter Settings by Entity Instance 65. Port Connectivity Checks: "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0" 66. Port Connectivity Checks: "synchronizer:synchronizer_SIO" 67. Port Connectivity Checks: "spdif_transmitter:\spdif_on:spdif" 68. Port Connectivity Checks: "filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd" 69. Port Connectivity Checks: "sigmadelta_dither:dac_dithergen" 70. Port Connectivity Checks: "mixer:mixer1" 71. Port Connectivity Checks: "complete_address_decoder:\gen_config:decode_addr1" 72. Port Connectivity Checks: "pokey:pokey1|latch_delay_line:stimer_delay" 73. Port Connectivity Checks: "pokey:pokey1|latch_delay_line:twotone_del" 74. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audctl_delay" 75. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf3_delay" 76. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf2_delay" 77. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf1_delay" 78. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf0_delay" 79. Port Connectivity Checks: "pokey:pokey1|complete_address_decoder:decode_addr1" 80. Port Connectivity Checks: "pokey:pokey1" 81. Port Connectivity Checks: "pokey_mixer_mux:pokey_mixer_both" 82. Port Connectivity Checks: "slave_timing_6502:bus_adapt" 83. Port Connectivity Checks: "synchronizer:synchronizer_fancy_enable" 84. Port Connectivity Checks: "synchronizer:synchronizer_gtia_audio" 85. Port Connectivity Checks: "int_osc:oscillator" 86. Post-Synthesis Netlist Statistics for Top Partition 87. Elapsed Time Per Partition 88. Analysis & Synthesis Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2025 Altera Corporation. All rights reserved. Your use of Altera Corporation's design tools, logic functions and other software and tools, and any partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, the Altera Quartus Prime License Agreement, the Altera IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the Altera Software License Subscription Agreements on the Quartus Prime software download page. +--------------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+-------------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Fri Jun 19 21:55:42 2026 ; ; Quartus Prime Version ; 25.1std.0 Build 1129 10/21/2025 SC Lite Edition ; ; Revision Name ; pokeymax ; ; Top-level Entity Name ; pokeymax ; ; Family ; MAX 10 ; ; Total logic elements ; 1,377 ; ; Total combinational functions ; 1,067 ; ; Dedicated logic registers ; 874 ; ; Total registers ; 874 ; ; Total pins ; 70 ; ; Total virtual pins ; 0 ; ; Total memory bits ; 0 ; ; Embedded Multiplier 9-bit elements ; 0 ; ; Total PLLs ; 1 ; ; UFM blocks ; 0 ; ; ADC blocks ; 0 ; +------------------------------------+-------------------------------------------------+ +------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +------------------------------------------------------------------+--------------------+--------------------+ ; Device ; 10M02SCU169C8G ; ; ; Top-level entity name ; pokeymax ; pokeymax ; ; Family name ; MAX 10 ; Cyclone V ; ; Auto Resource Sharing ; On ; Off ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Intel FPGA IP Evaluation Mode ; Enable ; Enable ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto Open-Drain Pins ; On ; On ; ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; +------------------------------------------------------------------+--------------------+--------------------+ +-------------------------------------------------+ ; Analysis & Synthesis Default Parameter Settings ; +--------------------+----------------------------+ ; Name ; Setting ; +--------------------+----------------------------+ ; a4_bit ; 0 ; ; enable_adc ; 0 ; ; enable_audout2 ; 0 ; ; enable_auto_stereo ; 0 ; ; enable_covox ; 0 ; ; enable_flash ; 0 ; ; enable_iox ; 0 ; ; enable_ps2 ; 0 ; ; enable_psg ; 0 ; ; enable_sample ; 0 ; ; enable_sid ; 0 ; ; enable_spdif ; 1 ; ; ext_bits ; 10 ; ; fancy_switch_bit ; 0 ; ; fpga ; 10M02SCU169C8G ; ; gtia_audio_bit ; 0 ; ; optimisearea ; 1 ; ; paddle_comp ; 0 ; ; paddle_lvds ; 1 ; ; pll_v2 ; 0 ; ; pokeys ; 1 ; ; ps2clk_bit ; 0 ; ; ps2dat_bit ; 0 ; ; spdif_bit ; 10 ; ; version ; 314002MA ; +--------------------+----------------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 32 ; ; Maximum allowed ; 16 ; ; ; ; ; Average used ; 1.00 ; ; Maximum used ; 5 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 0.0% ; ; Processor 3 ; 0.0% ; ; Processor 4 ; 0.0% ; ; Processor 5 ; 0.0% ; +----------------------------+-------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +-----------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-------------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +-----------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-------------+ ; audio_signal_detector.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/audio_signal_detector.vhd ; ; ; flash_controller.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/flash_controller.vhd ; ; ; stereo_detect.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/stereo_detect.vhd ; ; ; iox_glue.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/iox_glue.vhdl ; ; ; i2c_master.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/i2c_master.vhd ; ; ; slave_timing_6502.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/slave_timing_6502.vhd ; ; ; pll_reset_sync.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pll_reset_sync.vhdl ; ; ; complete_address_decoder.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/complete_address_decoder.vhdl ; ; ; syncreset_enable_divider.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/syncreset_enable_divider.vhd ; ; ; enable_divider.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/enable_divider.vhdl ; ; ; delay_line.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/delay_line.vhdl ; ; ; wide_delay_line.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/wide_delay_line.vhdl ; ; ; latch_delay_line.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/latch_delay_line.vhdl ; ; ; sigmadelta_1storder.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_1storder.vhd ; ; ; sigmadelta_2ndorder.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_2ndorder.vhd ; ; ; sigmadelta_dither.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_dither.vhd ; ; ; sigmadelta_2ndorder_dither.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_2ndorder_dither.vhd ; ; ; filtered_sigmadelta.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/filtered_sigmadelta.vhd ; ; ; fir_filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_filter.vhdl ; ; ; generic_ram_infer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/generic_ram_infer.vhdl ; ; ; m9k_grouped.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/m9k_grouped.vhdl ; ; ; simple_low_pass_filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/simple_low_pass_filter.vhdl ; ; ; pokey/pokey_poly_17_9.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_17_9.vhdl ; ; ; pokey/pokey_poly_5.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_5.vhdl ; ; ; pokey/pokey_poly_4.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_4.vhdl ; ; ; pokey/pokey_noise_filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_noise_filter.vhdl ; ; ; pokey/pokey_mixer_mux.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_mixer_mux.vhdl ; ; ; pokey/pokey_mixer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_mixer.vhdl ; ; ; pokey/pokey_keyboard_scanner.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_keyboard_scanner.vhdl ; ; ; pokey/pokey_countdown_timer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_countdown_timer.vhdl ; ; ; pokey/pokey.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl ; ; ; synchronizer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/synchronizer.vhdl ; ; ; audiotypes.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/audiotypes.vhdl ; ; ; dc_blocker.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/dc_blocker.vhdl ; ; ; mixer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/mixer.vhdl ; ; ; clockgen.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/clockgen.vhd ; ; ; spdif_transmitter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/spdif_transmitter.vhdl ; ; ; ps2_keyboard.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/ps2_keyboard.vhdl ; ; ; ps2_to_atari800.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/ps2_to_atari800.vhdl ; ; ; pokeymax.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd ; ; ; PSG/envelope.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/envelope.vhdl ; ; ; PSG/noise.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/noise.vhdl ; ; ; PSG/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/top.vhdl ; ; ; PSG/freqdiv.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/freqdiv.vhdl ; ; ; PSG/mixer.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/mixer.vhdl ; ; ; PSG/volume.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/volume.vhdl ; ; ; PSG/volume_profile.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/volume_profile.vhdl ; ; ; SID/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/top.vhdl ; ; ; SID/oscillator.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/oscillator.vhdl ; ; ; SID/wavegen.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/wavegen.vhdl ; ; ; SID/envelope.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/envelope.vhdl ; ; ; SID/envelope_tapmatch.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/envelope_tapmatch.vhdl ; ; ; SID/amplitudeModulator.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/amplitudeModulator.vhdl ; ; ; SID/preFilterSum.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/preFilterSum.vhdl ; ; ; SID/filter.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/filter.vhdl ; ; ; SID/f_distortion.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/f_distortion.vhdl ; ; ; SID/f_distortion_mux.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/f_distortion_mux.vhdl ; ; ; SID/postFilterSum.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/postFilterSum.vhdl ; ; ; sample/channel.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/channel.vhdl ; ; ; sample/adpcm.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/adpcm.vhdl ; ; ; sample/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/top.vhdl ; ; ; covox/top.vhdl ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/covox/top.vhdl ; ; ; sigma_delta/fir_compensator.sv ; yes ; User SystemVerilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigma_delta/fir_compensator.sv ; ; ; int_osc/synthesis/int_osc.vhd ; yes ; User VHDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/int_osc/synthesis/int_osc.vhd ; int_osc ; ; int_osc/synthesis/submodules/altera_int_osc.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/int_osc/synthesis/submodules/altera_int_osc.v ; int_osc ; ; pllv3.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pllv3.vhd ; ; ; lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v ; lvds_tx ; ; lvds_rx/altera_soft_lvds_rx_uCmNW05P.v ; yes ; User Verilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_rx/altera_soft_lvds_rx_uCmNW05P.v ; lvds_rx ; ; paddle_gpio.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio.vhd ; paddle_gpio ; ; paddle_gpio/altera_gpio_lite.sv ; yes ; User SystemVerilog HDL File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv ; paddle_gpio ; ; fir_sample_buffer.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_sample_buffer.vhd ; ; ; fir_buffer.vhd ; yes ; User Wizard-Generated File ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_buffer.vhd ; ; ; altpll.tdf ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altpll.tdf ; ; ; aglobal251.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/aglobal251.inc ; ; ; stratix_pll.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/stratix_pll.inc ; ; ; stratixii_pll.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/stratixii_pll.inc ; ; ; cycloneii_pll.inc ; yes ; Megafunction ; /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; ; db/pllv3_altpll.v ; yes ; Auto-Generated Megafunction ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/db/pllv3_altpll.v ; ; +-----------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+-------------+ +------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Usage Summary ; +---------------------------------------------+--------------------------------------------------------------------------------------------------+ ; Resource ; Usage ; +---------------------------------------------+--------------------------------------------------------------------------------------------------+ ; Estimated Total logic elements ; 1,377 ; ; ; ; ; Total combinational functions ; 1067 ; ; Logic element usage by number of LUT inputs ; ; ; -- 4 input functions ; 418 ; ; -- 3 input functions ; 461 ; ; -- <=2 input functions ; 188 ; ; ; ; ; Logic elements by mode ; ; ; -- normal mode ; 688 ; ; -- arithmetic mode ; 379 ; ; ; ; ; Total registers ; 874 ; ; -- Dedicated logic registers ; 874 ; ; -- I/O registers ; 0 ; ; ; ; ; I/O pins ; 70 ; ; ; ; ; Embedded Multiplier 9-bit elements ; 0 ; ; ; ; ; Total PLLs ; 1 ; ; -- PLLs ; 1 ; ; ; ; ; Maximum fan-out node ; pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated|wire_pll1_clk[0] ; ; Maximum fan-out ; 861 ; ; Total fan-out ; 6754 ; ; Average fan-out ; 3.18 ; +---------------------------------------------+--------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Resource Utilization by Entity ; +-------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------+--------------+ ; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name ; Entity Name ; Library Name ; +-------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------+--------------+ ; |pokeymax ; 1067 (31) ; 874 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 70 ; 0 ; 0 ; |pokeymax ; pokeymax ; work ; ; |dc_blocker:pokey1_dc_blocker| ; 57 (57) ; 36 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|dc_blocker:pokey1_dc_blocker ; dc_blocker ; work ; ; |filtered_sigmadelta:dac_0| ; 76 (0) ; 43 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|filtered_sigmadelta:dac_0 ; filtered_sigmadelta ; work ; ; |sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd| ; 76 (76) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd ; sigmadelta_2ndorder ; work ; ; |filtered_sigmadelta:dac_2| ; 76 (0) ; 43 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|filtered_sigmadelta:dac_2 ; filtered_sigmadelta ; work ; ; |sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd| ; 76 (76) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|filtered_sigmadelta:dac_2|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd ; sigmadelta_2ndorder ; work ; ; |filtered_sigmadelta:dac_3| ; 57 (0) ; 43 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|filtered_sigmadelta:dac_3 ; filtered_sigmadelta ; work ; ; |sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd| ; 57 (57) ; 43 (43) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|filtered_sigmadelta:dac_3|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd ; sigmadelta_2ndorder ; work ; ; |int_osc:oscillator| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|int_osc:oscillator ; int_osc ; int_osc ; ; |altera_int_osc:int_osc_0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|int_osc:oscillator|altera_int_osc:int_osc_0 ; altera_int_osc ; int_osc ; ; |mixer:mixer1| ; 87 (87) ; 78 (78) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|mixer:mixer1 ; mixer ; work ; ; |paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0 ; paddle_gpio ; paddle_gpio ; ; |altera_gpio_lite:paddle_gpio_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst ; altera_gpio_lite ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i ; altgpio_one_bit ; paddle_gpio ; ; |pll_reset_sync:pll_sync| ; 9 (9) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pll_reset_sync:pll_sync ; pll_reset_sync ; work ; ; |pllv3:\pll_v3_inst:pll_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pllv3:\pll_v3_inst:pll_inst ; pllv3 ; work ; ; |altpll:altpll_component| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component ; altpll ; work ; ; |pllv3_altpll:auto_generated| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated ; pllv3_altpll ; work ; ; |pokey:pokey1| ; 341 (168) ; 448 (269) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1 ; pokey ; work ; ; |delay_line:serin_clock_delay| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|delay_line:serin_clock_delay ; delay_line ; work ; ; |delay_line:serout_clock_delay| ; 5 (5) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|delay_line:serout_clock_delay ; delay_line ; work ; ; |latch_delay_line:stimer_delay| ; 3 (3) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|latch_delay_line:stimer_delay ; latch_delay_line ; work ; ; |latch_delay_line:twotone_del| ; 0 (0) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|latch_delay_line:twotone_del ; latch_delay_line ; work ; ; |pokey_countdown_timer:timer0| ; 15 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 6 (6) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_countdown_timer:timer1| ; 14 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_countdown_timer:timer2| ; 14 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 5 (5) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_countdown_timer:timer3| ; 16 (9) ; 11 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3 ; pokey_countdown_timer ; work ; ; |delay_line:underflow0_delay| ; 7 (7) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay ; delay_line ; work ; ; |pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1| ; 38 (38) ; 28 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1 ; pokey_keyboard_scanner ; work ; ; |pokey_noise_filter:pokey_noise_filter0| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter0 ; pokey_noise_filter ; work ; ; |pokey_noise_filter:pokey_noise_filter1| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1 ; pokey_noise_filter ; work ; ; |pokey_noise_filter:pokey_noise_filter2| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2 ; pokey_noise_filter ; work ; ; |pokey_noise_filter:pokey_noise_filter3| ; 4 (4) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3 ; pokey_noise_filter ; work ; ; |pokey_poly_17_9:poly_17_19_lfsr| ; 18 (18) ; 18 (18) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr ; pokey_poly_17_9 ; work ; ; |pokey_poly_4:poly_4_lfsr| ; 4 (4) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_poly_4:poly_4_lfsr ; pokey_poly_4 ; work ; ; |pokey_poly_5:poly_5_lfsr| ; 5 (5) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|pokey_poly_5:poly_5_lfsr ; pokey_poly_5 ; work ; ; |synchronizer:sio_clk1_synchronizer| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|synchronizer:sio_clk1_synchronizer ; synchronizer ; work ; ; |synchronizer:sio_in1_synchronizer| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|synchronizer:sio_in1_synchronizer ; synchronizer ; work ; ; |synchronizer:sio_in2_synchronizer| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|synchronizer:sio_in2_synchronizer ; synchronizer ; work ; ; |syncreset_enable_divider:enable_15_div| ; 10 (10) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_15_div ; syncreset_enable_divider ; work ; ; |syncreset_enable_divider:enable_64_div| ; 8 (8) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_64_div ; syncreset_enable_divider ; work ; ; |wide_delay_line:audctl_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|wide_delay_line:audctl_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf0_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|wide_delay_line:audf0_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf1_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|wide_delay_line:audf1_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf2_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|wide_delay_line:audf2_delay ; wide_delay_line ; work ; ; |wide_delay_line:audf3_delay| ; 0 (0) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey:pokey1|wide_delay_line:audf3_delay ; wide_delay_line ; work ; ; |pokey_mixer:\flash_off:shared_pokey_mixer| ; 79 (79) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey_mixer:\flash_off:shared_pokey_mixer ; pokey_mixer ; work ; ; |pokey_mixer_mux:pokey_mixer_both| ; 21 (21) ; 29 (29) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|pokey_mixer_mux:pokey_mixer_both ; pokey_mixer_mux ; work ; ; |simple_low_pass_filter:\spdif_on:filter_left| ; 83 (83) ; 42 (42) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|simple_low_pass_filter:\spdif_on:filter_left ; simple_low_pass_filter ; work ; ; |slave_timing_6502:bus_adapt| ; 76 (76) ; 39 (36) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|slave_timing_6502:bus_adapt ; slave_timing_6502 ; work ; ; |synchronizer:synchronizer_phi| ; 0 (0) ; 3 (3) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|slave_timing_6502:bus_adapt|synchronizer:synchronizer_phi ; synchronizer ; work ; ; |spdif_transmitter:\spdif_on:spdif| ; 74 (74) ; 59 (59) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |pokeymax|spdif_transmitter:\spdif_on:spdif ; spdif_transmitter ; work ; +-------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +---------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis IP Cores Summary ; +--------+------------------+---------+--------------+--------------+-------------------------------------------------------+-----------------+ ; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ; +--------+------------------+---------+--------------+--------------+-------------------------------------------------------+-----------------+ ; Altera ; altera_gpio_lite ; 23.1 ; N/A ; N/A ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0 ; paddle_gpio.vhd ; ; Altera ; ALTPLL ; 23.1 ; N/A ; N/A ; |pokeymax|pllv3:\pll_v3_inst:pll_inst ; pllv3.vhd ; ; N/A ; altera_int_osc ; 23.1 ; N/A ; N/A ; |pokeymax|int_osc:oscillator ; int_osc.qsys ; +--------+------------------+---------+--------------+--------------+-------------------------------------------------------+-----------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+ ; spdif_transmitter:\spdif_on:spdif|data_in_buffer[0..7] ; Stuck at GND due to stuck port data_in ; ; slave_timing_6502:bus_adapt|phi_addr_reg[4..7] ; Stuck at GND due to stuck port data_in ; ; synchronizer:synchronizer_fancy_enable|ff_reg[2] ; Stuck at GND due to stuck port data_in ; ; synchronizer:synchronizer_gtia_audio|ff_reg[2] ; Stuck at GND due to stuck port data_in ; ; synchronizer:synchronizer_fancy_enable|ff_reg[1] ; Stuck at GND due to stuck port data_in ; ; synchronizer:synchronizer_gtia_audio|ff_reg[1] ; Stuck at GND due to stuck port data_in ; ; synchronizer:synchronizer_fancy_enable|ff_reg[0] ; Stuck at GND due to stuck port data_in ; ; synchronizer:synchronizer_gtia_audio|ff_reg[0] ; Stuck at GND due to stuck port data_in ; ; CONFIG_ENABLE_REG ; Lost fanout ; ; mixer:mixer1|RIGHT_REG ; Lost fanout ; ; mixer:mixer1|RIGHT_SNAP_REG[8..19] ; Lost fanout ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[0..23] ; Lost fanout ; ; CHANNEL1SUM_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; CHANNEL2SUM_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; CHANNEL3SUM_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_1_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[4,5] ; Stuck at GND due to stuck port data_in ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|cycle_delay_reg ; Merged with pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8] ; ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[0..5] ; Stuck at GND due to stuck port data_in ; ; mixer:mixer1|audio3_reg[15] ; Merged with mixer:mixer1|audio2_reg[15] ; ; mixer:mixer1|audio3_reg[14] ; Merged with mixer:mixer1|audio2_reg[14] ; ; mixer:mixer1|audio3_reg[13] ; Merged with mixer:mixer1|audio2_reg[13] ; ; mixer:mixer1|audio3_reg[12] ; Merged with mixer:mixer1|audio2_reg[12] ; ; mixer:mixer1|audio3_reg[11] ; Merged with mixer:mixer1|audio2_reg[11] ; ; mixer:mixer1|audio3_reg[10] ; Merged with mixer:mixer1|audio2_reg[10] ; ; mixer:mixer1|audio3_reg[9] ; Merged with mixer:mixer1|audio2_reg[9] ; ; mixer:mixer1|audio3_reg[8] ; Merged with mixer:mixer1|audio2_reg[8] ; ; mixer:mixer1|audio3_reg[7] ; Merged with mixer:mixer1|audio2_reg[7] ; ; mixer:mixer1|audio3_reg[6] ; Merged with mixer:mixer1|audio2_reg[6] ; ; mixer:mixer1|audio3_reg[5] ; Merged with mixer:mixer1|audio2_reg[5] ; ; mixer:mixer1|audio3_reg[4] ; Merged with mixer:mixer1|audio2_reg[4] ; ; mixer:mixer1|audio3_reg[3] ; Merged with mixer:mixer1|audio2_reg[3] ; ; mixer:mixer1|audio3_reg[2] ; Merged with mixer:mixer1|audio2_reg[2] ; ; mixer:mixer1|audio3_reg[1] ; Merged with mixer:mixer1|audio2_reg[1] ; ; mixer:mixer1|audio3_reg[0] ; Merged with mixer:mixer1|audio2_reg[0] ; ; CHANNEL_EN_REG[0,2..4] ; Stuck at VCC due to stuck port clock_enable ; ; POST_DIVIDE_REG[1,3] ; Stuck at GND due to stuck port clock_enable ; ; POST_DIVIDE_REG[5,7] ; Stuck at VCC due to stuck port clock_enable ; ; POST_DIVIDE_REG[0,2,4,6] ; Stuck at GND due to stuck port clock_enable ; ; GTIA_ENABLE_REG[0] ; Stuck at GND due to stuck port clock_enable ; ; RESTRICT_CAPABILITY_REG[0] ; Stuck at VCC due to stuck port clock_enable ; ; GTIA_ENABLE_REG[1] ; Stuck at GND due to stuck port clock_enable ; ; RESTRICT_CAPABILITY_REG[1] ; Stuck at VCC due to stuck port clock_enable ; ; CHANNEL_EN_REG[1] ; Stuck at VCC due to stuck port clock_enable ; ; GTIA_ENABLE_REG[2] ; Stuck at VCC due to stuck port clock_enable ; ; RESTRICT_CAPABILITY_REG[2] ; Stuck at VCC due to stuck port clock_enable ; ; GTIA_ENABLE_REG[3] ; Stuck at VCC due to stuck port clock_enable ; ; RESTRICT_CAPABILITY_REG[3,4] ; Stuck at VCC due to stuck port clock_enable ; ; SIO_DATA_VOLUME_REG[0] ; Stuck at GND due to stuck port clock_enable ; ; SIO_DATA_VOLUME_REG[1] ; Stuck at VCC due to stuck port clock_enable ; ; VERSION_LOC_REG[1,2] ; Lost fanout ; ; SATURATE_REG ; Stuck at VCC due to stuck port clock_enable ; ; VERSION_LOC_REG[0] ; Lost fanout ; ; CHANNEL_MODE_REG ; Stuck at GND due to stuck port clock_enable ; ; IRQ_EN_REG ; Lost fanout ; ; DETECT_RIGHT_REG ; Lost fanout ; ; PAL_REG ; Lost fanout ; ; CHANNEL1SUM_REG[1] ; Stuck at GND due to stuck port data_in ; ; CHANNEL2SUM_REG[1] ; Stuck at GND due to stuck port data_in ; ; CHANNEL3SUM_REG[1] ; Stuck at GND due to stuck port data_in ; ; CHANNEL1SUM_REG[0] ; Stuck at GND due to stuck port data_in ; ; CHANNEL2SUM_REG[0] ; Stuck at GND due to stuck port data_in ; ; CHANNEL3SUM_REG[0] ; Stuck at GND due to stuck port data_in ; ; CHANNEL1SUM_REG[3] ; Stuck at GND due to stuck port data_in ; ; CHANNEL2SUM_REG[3] ; Stuck at GND due to stuck port data_in ; ; CHANNEL3SUM_REG[3] ; Stuck at GND due to stuck port data_in ; ; CHANNEL1SUM_REG[2] ; Stuck at GND due to stuck port data_in ; ; CHANNEL2SUM_REG[2] ; Stuck at GND due to stuck port data_in ; ; CHANNEL3SUM_REG[2] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[0..3] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_1_REG[0..3] ; Stuck at GND due to stuck port data_in ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[0..3] ; Stuck at GND due to stuck port data_in ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[4] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[4] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[8] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[8] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[12] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[12] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[16] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[16] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[20] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[20] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[19] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[19] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[18] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[18] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[17] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[17] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[15] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[15] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[14] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[14] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[13] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[13] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[11] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[11] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[10] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[10] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[9] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[9] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[7] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[7] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[6] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[6] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[5] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[5] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[3] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[3] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[2] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[2] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[1] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[1] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum2_reg[0] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum2_reg[0] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[20] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[20] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[19] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[19] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[18] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[18] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[17] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[17] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[16] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[16] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[15] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[15] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[14] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[14] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[13] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[13] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[12] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[12] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[11] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[11] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[10] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[10] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[9] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[9] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[8] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[8] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[7] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[7] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[6] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[6] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[5] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[5] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[4] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[4] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[3] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[3] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[2] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[2] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[1] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[1] ; ; simple_low_pass_filter:\spdif_on:filter_right|accum_reg[0] ; Merged with simple_low_pass_filter:\spdif_on:filter_left|accum_reg[0] ; ; filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|ttl1_reg[21] ; Lost fanout ; ; filtered_sigmadelta:dac_2|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|ttl1_reg[21] ; Lost fanout ; ; filtered_sigmadelta:dac_3|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|ttl1_reg[21] ; Lost fanout ; ; pokey:pokey1|latch_delay_line:twotone_del|data_in_reg ; Stuck at GND due to stuck port data_in ; ; Total Number of Removed Registers = 193 ; ; +-------------------------------------------------------------------------------------+-------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +-----------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +-----------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------+ ; slave_timing_6502:bus_adapt|phi_addr_reg[7] ; Stuck at GND ; CONFIG_ENABLE_REG, CHANNEL_EN_REG[0], CHANNEL_EN_REG[2], CHANNEL_EN_REG[3], ; ; ; due to stuck port data_in ; CHANNEL_EN_REG[4], POST_DIVIDE_REG[1], POST_DIVIDE_REG[3], POST_DIVIDE_REG[5], ; ; ; ; POST_DIVIDE_REG[7], POST_DIVIDE_REG[0], POST_DIVIDE_REG[2], POST_DIVIDE_REG[4], ; ; ; ; POST_DIVIDE_REG[6], GTIA_ENABLE_REG[0], GTIA_ENABLE_REG[1], CHANNEL_EN_REG[1], ; ; ; ; GTIA_ENABLE_REG[2], GTIA_ENABLE_REG[3], SIO_DATA_VOLUME_REG[0], SIO_DATA_VOLUME_REG[1], ; ; ; ; VERSION_LOC_REG[2], VERSION_LOC_REG[1], SATURATE_REG, VERSION_LOC_REG[0], ; ; ; ; CHANNEL_MODE_REG, IRQ_EN_REG, PAL_REG, CHANNEL1SUM_REG[1], CHANNEL2SUM_REG[1], ; ; ; ; CHANNEL3SUM_REG[1], CHANNEL1SUM_REG[0], CHANNEL2SUM_REG[0], CHANNEL3SUM_REG[0], ; ; ; ; CHANNEL1SUM_REG[3], CHANNEL2SUM_REG[3], CHANNEL3SUM_REG[3], CHANNEL1SUM_REG[2], ; ; ; ; CHANNEL2SUM_REG[2], CHANNEL3SUM_REG[2], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[2], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[1], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[0], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_1_REG[2], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_1_REG[1], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_1_REG[0], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[2], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[1], ; ; ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[0] ; ; synchronizer:synchronizer_fancy_enable|ff_reg[2] ; Stuck at GND ; synchronizer:synchronizer_fancy_enable|ff_reg[1], ; ; ; due to stuck port data_in ; synchronizer:synchronizer_fancy_enable|ff_reg[0], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[23], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[22], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[21], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[20], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[19], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[18], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[17], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[16], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[15], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[14], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[13], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[12], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[11], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[10], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[9], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[8], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[7], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[6], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[5], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[4], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[3], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[2], ; ; ; ; mixer:mixer1|RIGHT_PLAYING_COUNT_REG[1], mixer:mixer1|RIGHT_PLAYING_COUNT_REG[0], ; ; ; ; DETECT_RIGHT_REG ; ; mixer:mixer1|RIGHT_REG ; Lost Fanouts ; mixer:mixer1|RIGHT_SNAP_REG[12], mixer:mixer1|RIGHT_SNAP_REG[11], ; ; ; ; mixer:mixer1|RIGHT_SNAP_REG[10], mixer:mixer1|RIGHT_SNAP_REG[9], ; ; ; ; mixer:mixer1|RIGHT_SNAP_REG[8] ; ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[0] ; Stuck at GND ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[1], ; ; ; due to stuck port data_in ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[2], ; ; ; ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[3], ; ; ; ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[4], ; ; ; ; spdif_transmitter:\spdif_on:spdif|channel_status_shift[5] ; ; synchronizer:synchronizer_gtia_audio|ff_reg[2] ; Stuck at GND ; synchronizer:synchronizer_gtia_audio|ff_reg[1], ; ; ; due to stuck port data_in ; synchronizer:synchronizer_gtia_audio|ff_reg[0] ; +-----------------------------------------------------------+---------------------------+-----------------------------------------------------------------------------------------+ +------------------------------------------------------+ ; General Register Statistics ; +----------------------------------------------+-------+ ; Statistic ; Value ; +----------------------------------------------+-------+ ; Total registers ; 874 ; ; Number of registers using Synchronous Clear ; 26 ; ; Number of registers using Synchronous Load ; 52 ; ; Number of registers using Asynchronous Clear ; 743 ; ; Number of registers using Asynchronous Load ; 0 ; ; Number of registers using Clock Enable ; 587 ; ; Number of registers using Preset ; 0 ; +----------------------------------------------+-------+ +-------------------------------------------------------------------------------------------------------------+ ; Inverted Register Statistics ; +---------------------------------------------------------------------------------------------------+---------+ ; Inverted Register ; Fan out ; +---------------------------------------------------------------------------------------------------+---------+ ; pokey:pokey1|sio_out_reg ; 1 ; ; slave_timing_6502:bus_adapt|state_reg[0] ; 5 ; ; slave_timing_6502:bus_adapt|phi_rw_n_reg ; 2 ; ; slave_timing_6502:bus_adapt|phi_edge_prev_reg ; 4 ; ; pokey:pokey1|serial_out_reg ; 3 ; ; slave_timing_6502:bus_adapt|phi_cs_reg ; 1 ; ; pokey:pokey1|irq_n_reg ; 1 ; ; pokey:pokey1|pot_reset_reg ; 11 ; ; pokey:pokey1|irqst_reg[3] ; 2 ; ; pokey:pokey1|irqst_reg[7] ; 3 ; ; pokey:pokey1|irqst_reg[6] ; 4 ; ; pokey:pokey1|irqst_reg[5] ; 4 ; ; pokey:pokey1|irqst_reg[4] ; 3 ; ; pokey:pokey1|irqst_reg[2] ; 3 ; ; pokey:pokey1|irqst_reg[1] ; 3 ; ; pokey:pokey1|irqst_reg[0] ; 3 ; ; pokey:pokey1|allpot_reg[0] ; 2 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0] ; 1 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[1] ; 1 ; ; pokey:pokey1|allpot_reg[1] ; 2 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9] ; 2 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[2] ; 1 ; ; pokey:pokey1|allpot_reg[2] ; 2 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[3] ; 1 ; ; pokey:pokey1|allpot_reg[3] ; 2 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11] ; 2 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4] ; 1 ; ; pokey:pokey1|allpot_reg[4] ; 2 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[5] ; 1 ; ; pokey:pokey1|allpot_reg[5] ; 2 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13] ; 4 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[6] ; 1 ; ; pokey:pokey1|allpot_reg[6] ; 2 ; ; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[7] ; 1 ; ; pokey:pokey1|allpot_reg[7] ; 2 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15] ; 2 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1] ; 1 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[1] ; 3 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[3] ; 3 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[0] ; 2 ; ; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[2] ; 2 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3] ; 1 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5] ; 1 ; ; pokey:pokey1|pokey_poly_4:poly_4_lfsr|shift_reg[1] ; 2 ; ; pokey:pokey1|pokey_poly_5:poly_5_lfsr|shift_reg[1] ; 1 ; ; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[7] ; 1 ; ; pokey:pokey1|pokey_poly_4:poly_4_lfsr|shift_reg[3] ; 1 ; ; pokey:pokey1|pokey_poly_5:poly_5_lfsr|shift_reg[3] ; 1 ; ; Total number of inverted registers = 48 ; ; +---------------------------------------------------------------------------------------------------+---------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------+ ; 3:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |pokeymax|pokey:pokey1|delay_line:serin_clock_delay|shift_reg[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|pot_counter_reg[5] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|serin_shift_reg[9] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0] ; ; 3:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |pokeymax|mixer:mixer1|divided_reg[15] ; ; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |pokeymax|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_0_REG[2] ; ; 3:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |pokeymax|pokey_mixer_mux:pokey_mixer_both|VOLUME_OUT_0_REG[10] ; ; 3:1 ; 6 bits ; 12 LEs ; 0 LEs ; 12 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[0] ; ; 3:1 ; 17 bits ; 34 LEs ; 17 LEs ; 17 LEs ; Yes ; |pokeymax|spdif_transmitter:\spdif_on:spdif|channel_status_shift[15] ; ; 4:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7] ; ; 3:1 ; 20 bits ; 40 LEs ; 20 LEs ; 20 LEs ; Yes ; |pokeymax|mixer:mixer1|acc_reg[18] ; ; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |pokeymax|pll_reset_sync:pll_sync|cnt[3] ; ; 4:1 ; 7 bits ; 14 LEs ; 14 LEs ; 0 LEs ; Yes ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[1] ; ; 4:1 ; 8 bits ; 16 LEs ; 16 LEs ; 0 LEs ; Yes ; |pokeymax|pokey:pokey1|serout_shift_reg[7] ; ; 4:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |pokeymax|pokey:pokey1|serin_bitcount_reg[3] ; ; 4:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |pokeymax|pokey_mixer_mux:pokey_mixer_both|CHANNEL_STATE_REG[2] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |pokeymax|spdif_transmitter:\spdif_on:spdif|data_out_buffer[7] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; Yes ; |pokeymax|spdif_transmitter:\spdif_on:spdif|data_out_buffer[3] ; ; 5:1 ; 4 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |pokeymax|pokey:pokey1|serout_bitcount_reg[2] ; ; 17:1 ; 7 bits ; 77 LEs ; 70 LEs ; 7 LEs ; Yes ; |pokeymax|slave_timing_6502:bus_adapt|registered_read_data_reg[1] ; ; 10:1 ; 2 bits ; 12 LEs ; 8 LEs ; 4 LEs ; Yes ; |pokeymax|spdif_transmitter:\spdif_on:spdif|data_out_buffer[4] ; ; 6:1 ; 2 bits ; 8 LEs ; 0 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[6] ; ; 6:1 ; 6 bits ; 24 LEs ; 6 LEs ; 18 LEs ; Yes ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0] ; ; 5:1 ; 8 bits ; 24 LEs ; 16 LEs ; 8 LEs ; Yes ; |pokeymax|pokey:pokey1|allpot_reg[2] ; ; 4:1 ; 2 bits ; 4 LEs ; 4 LEs ; 0 LEs ; No ; |pokeymax|mixer:mixer1|Mux1 ; ; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |pokeymax|pokey_mixer_mux:pokey_mixer_both|Mux14 ; ; 16:1 ; 3 bits ; 30 LEs ; 24 LEs ; 6 LEs ; No ; |pokeymax|CONFIG_DO[2] ; ; 14:1 ; 16 bits ; 144 LEs ; 80 LEs ; 64 LEs ; No ; |pokeymax|mixer:mixer1|Mux74 ; +--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; Assignment ; Value ; From ; To ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ ; GLOBAL_SIGNAL ; OFF ; - ; fr_clock ; +---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: Top-level Entity: |pokeymax ; +----------------------------+----------+----------------------------------+ ; Parameter Name ; Value ; Type ; +----------------------------+----------+----------------------------------+ ; pokeys ; 1 ; Untyped ; ; lowpass ; 0 ; Signed Integer ; ; enable_auto_stereo ; 0 ; Untyped ; ; fancy_switch_bit ; 0 ; Untyped ; ; gtia_audio_bit ; 0 ; Untyped ; ; detect_right_on_by_default ; 1 ; Signed Integer ; ; saturate_on_by_default ; 1 ; Signed Integer ; ; a4_bit ; 0 ; Untyped ; ; a5_bit ; 0 ; Signed Integer ; ; a6_bit ; 0 ; Signed Integer ; ; a7_bit ; 0 ; Signed Integer ; ; cs0_bit ; 18 ; Signed Integer ; ; cs1_bit ; 19 ; Signed Integer ; ; spdif_bit ; 10 ; Untyped ; ; ps2clk_bit ; 0 ; Untyped ; ; ps2dat_bit ; 0 ; Untyped ; ; adc_audio_detect ; 0 ; Signed Integer ; ; adc_fir_filter_v4 ; 0 ; Signed Integer ; ; sigmadelta_implementation ; 2 ; Signed Integer ; ; ext_bits ; 10 ; Untyped ; ; pll_v2 ; 0 ; Untyped ; ; enable_config ; 1 ; Signed Integer ; ; enable_sid ; 0 ; Untyped ; ; enable_psg ; 0 ; Untyped ; ; enable_covox ; 0 ; Untyped ; ; enable_sample ; 0 ; Untyped ; ; enable_flash ; 0 ; Untyped ; ; enable_audout2 ; 0 ; Untyped ; ; enable_spdif ; 1 ; Untyped ; ; enable_ps2 ; 0 ; Untyped ; ; enable_adc ; 0 ; Untyped ; ; enable_routing ; 0 ; Signed Integer ; ; paddle_lvds ; 1 ; Untyped ; ; paddle_comp ; 0 ; Untyped ; ; enable_iox ; 0 ; Untyped ; ; sid_wave_base ; 42496 ; Signed Integer ; ; sample_ram_size ; 43008 ; Signed Integer ; ; flash_addr_bits ; 16 ; Signed Integer ; ; ext_clk_enable ; 0 ; Signed Integer ; ; version ; 314002MA ; Untyped ; +----------------------------+----------+----------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: int_osc:oscillator|altera_int_osc:int_osc_0 ; +-----------------+--------+---------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+--------+---------------------------------------------------------------+ ; DEVICE_FAMILY ; MAX 10 ; String ; ; DEVICE_ID ; 08 ; String ; ; CLOCK_FREQUENCY ; 116 ; String ; +-----------------+--------+---------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component ; +-------------------------------+-------------------------+----------------------------------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------------+----------------------------------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; LPM_HINT ; CBX_MODULE_PREFIX=pllv3 ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 20345 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; ON ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 1 ; Untyped ; ; CLK3_MULTIPLY_BY ; 1 ; Signed Integer ; ; CLK2_MULTIPLY_BY ; 2 ; Signed Integer ; ; CLK1_MULTIPLY_BY ; 7 ; Signed Integer ; ; CLK0_MULTIPLY_BY ; 7 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 1 ; Untyped ; ; CLK3_DIVIDE_BY ; 8 ; Signed Integer ; ; CLK2_DIVIDE_BY ; 1 ; Signed Integer ; ; CLK1_DIVIDE_BY ; 3 ; Signed Integer ; ; CLK0_DIVIDE_BY ; 6 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK2_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK1_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; ; DPA_MULTIPLY_BY ; 0 ; Untyped ; ; DPA_DIVIDE_BY ; 1 ; Untyped ; ; DPA_DIVIDER ; 0 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; CLK6_COUNTER ; E0 ; Untyped ; ; CLK7_COUNTER ; E1 ; Untyped ; ; CLK8_COUNTER ; E2 ; Untyped ; ; CLK9_COUNTER ; E3 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; MAX 10 ; Untyped ; ; PORT_CLKENA0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA1 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA2 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA4 ; PORT_UNUSED ; Untyped ; ; PORT_CLKENA5 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK2 ; PORT_UNUSED ; Untyped ; ; PORT_EXTCLK3 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD0 ; PORT_UNUSED ; Untyped ; ; PORT_CLKBAD1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK0 ; PORT_USED ; Untyped ; ; PORT_CLK1 ; PORT_USED ; Untyped ; ; PORT_CLK2 ; PORT_USED ; Untyped ; ; PORT_CLK3 ; PORT_USED ; Untyped ; ; PORT_CLK4 ; PORT_UNUSED ; Untyped ; ; PORT_CLK5 ; PORT_UNUSED ; Untyped ; ; PORT_CLK6 ; PORT_UNUSED ; Untyped ; ; PORT_CLK7 ; PORT_UNUSED ; Untyped ; ; PORT_CLK8 ; PORT_UNUSED ; Untyped ; ; PORT_CLK9 ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATA ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATAOUT ; PORT_UNUSED ; Untyped ; ; PORT_SCANDONE ; PORT_UNUSED ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_UNUSED ; Untyped ; ; PORT_CLKLOSS ; PORT_UNUSED ; Untyped ; ; PORT_INCLK1 ; PORT_UNUSED ; Untyped ; ; PORT_INCLK0 ; PORT_USED ; Untyped ; ; PORT_FBIN ; PORT_UNUSED ; Untyped ; ; PORT_PLLENA ; PORT_UNUSED ; Untyped ; ; PORT_CLKSWITCH ; PORT_UNUSED ; Untyped ; ; PORT_ARESET ; PORT_UNUSED ; Untyped ; ; PORT_PFDENA ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLK ; PORT_UNUSED ; Untyped ; ; PORT_SCANACLR ; PORT_UNUSED ; Untyped ; ; PORT_SCANREAD ; PORT_UNUSED ; Untyped ; ; PORT_SCANWRITE ; PORT_UNUSED ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_USED ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_UNUSED ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_UNUSED ; Untyped ; ; PORT_PHASESTEP ; PORT_UNUSED ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_UNUSED ; Untyped ; ; PORT_SCANCLKENA ; PORT_UNUSED ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_UNUSED ; Untyped ; ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; pllv3_altpll ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 5 ; Signed Integer ; ; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; MAX 10 ; Untyped ; ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------------+----------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pll_reset_sync:pll_sync ; +----------------+-------+---------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------+ ; reset_cycles ; 64 ; Signed Integer ; +----------------+-------+---------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: slave_timing_6502:bus_adapt ; +----------------+-------+-------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------+ ; address_bits ; 8 ; Signed Integer ; +----------------+-------+-------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1 ; +----------------------+-------+----------------------------+ ; Parameter Name ; Value ; Type ; +----------------------+-------+----------------------------+ ; custom_keyboard_scan ; 0 ; Signed Integer ; +----------------------+-------+----------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|complete_address_decoder:decode_addr1 ; +----------------+-------+------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf0_delay ; +----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf1_delay ; +----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf2_delay ; +----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf3_delay ; +----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audctl_delay ; +----------------+-------+---------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------+ ; count ; 1 ; Signed Integer ; ; width ; 8 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0 ; +-----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1 ; +-----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2 ; +-----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3 ; +-----------------+-------+--------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +-----------------+-------+--------------------------------------------------------------+ ; underflow_delay ; 3 ; Signed Integer ; +-----------------+-------+--------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:twotone_del ; +----------------+-------+---------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------+ ; count ; 2 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:stimer_delay ; +----------------+-------+----------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------+ ; count ; 3 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_64_div ; +----------------+-------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------+ ; count ; 28 ; Signed Integer ; ; resetcount ; 7 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_15_div ; +----------------+-------+-------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------------+ ; count ; 114 ; Signed Integer ; ; resetcount ; 34 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serout_clock_delay ; +----------------+-------+----------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------+ ; count ; 2 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serin_clock_delay ; +----------------+-------+---------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------------------------+ ; count ; 5 ; Signed Integer ; +----------------+-------+---------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: dc_blocker:pokey1_dc_blocker ; +----------------+-------+--------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+--------------------------------------------------+ ; bits ; 16 ; Signed Integer ; ; extra_bits ; 4 ; Signed Integer ; ; k ; 10 ; Signed Integer ; +----------------+-------+--------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: complete_address_decoder:\gen_config:decode_addr1 ; +----------------+-------+-----------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------+ ; width ; 4 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: sigmadelta_dither:dac_dithergen ; +----------------+------------------+------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+------------------+------------------------------------------+ ; lfsr_seed ; 1010110011100001 ; Unsigned Binary ; +----------------+------------------+------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0 ; +----------------+-------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------+ ; implementation ; 2 ; Signed Integer ; ; lowpass ; 0 ; Signed Integer ; +----------------+-------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2 ; +----------------+-------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------+ ; implementation ; 2 ; Signed Integer ; ; lowpass ; 0 ; Signed Integer ; +----------------+-------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3 ; +----------------+-------+-----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------+ ; implementation ; 2 ; Signed Integer ; ; lowpass ; 0 ; Signed Integer ; +----------------+-------+-----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst ; +------------------------------------------+---------------------+-----------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+-----------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; SIZE ; 8 ; Signed Integer ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; USE_ADVANCED_DDR_FEATURES ; false ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; INVERT_CLKDIV_INPUT_CLOCK ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; ENABLE_OE_PORT ; true ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_PHASE_INVERT_CTRL_PORT ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+-----------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ ; PIN_TYPE ; bidir ; String ; ; BUFFER_TYPE ; pseudo_differential ; String ; ; REGISTER_MODE ; bypass ; String ; ; ASYNC_MODE ; none ; String ; ; SYNC_MODE ; none ; String ; ; BUS_HOLD ; false ; String ; ; SET_REGISTER_OUTPUTS_HIGH ; false ; String ; ; USE_ENHANCED_DDR_HIO_REGISTER ; false ; String ; ; BYPASS_THREE_QUARTER_REGISTER ; true ; String ; ; INVERT_OUTPUT ; false ; String ; ; INVERT_INPUT_CLOCK ; false ; String ; ; INVERT_OUTPUT_CLOCK ; false ; String ; ; INVERT_OE_INCLOCK ; false ; String ; ; USE_ONE_REG_TO_DRIVE_OE ; false ; String ; ; USE_DDIO_REG_TO_DRIVE_OE ; false ; String ; ; OPEN_DRAIN_OUTPUT ; false ; String ; ; ENABLE_OE_HALF_CYCLE_DELAY ; true ; String ; ; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false ; String ; ; ENABLE_CLOCK_ENA_PORT ; false ; String ; ; ENABLE_HR_CLOCK ; false ; String ; ; ENABLE_PHASE_DETECTOR_FOR_CK ; false ; String ; ; ENABLE_NSLEEP_PORT ; false ; String ; +------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------+ ; altpll Parameter Settings by Entity Instance ; +-------------------------------+-----------------------------------------------------+ ; Name ; Value ; +-------------------------------+-----------------------------------------------------+ ; Number of entity instances ; 1 ; ; Entity Instance ; pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component ; ; -- OPERATION_MODE ; NORMAL ; ; -- PLL_TYPE ; AUTO ; ; -- PRIMARY_CLOCK ; INCLK0 ; ; -- INCLK0_INPUT_FREQUENCY ; 20345 ; ; -- INCLK1_INPUT_FREQUENCY ; 0 ; ; -- VCO_MULTIPLY_BY ; 0 ; ; -- VCO_DIVIDE_BY ; 0 ; +-------------------------------+-----------------------------------------------------+ +-------------------------------------------------------------------------+ ; Port Connectivity Checks: "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0" ; +------+-------+----------+-----------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+-------+----------+-----------------------------------------------+ ; din ; Input ; Info ; Stuck at GND ; +------+-------+----------+-----------------------------------------------+ +----------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "synchronizer:synchronizer_SIO" ; +------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+--------+----------+-------------------------------------------------------------------------------------+ ; sync ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------+--------+----------+-------------------------------------------------------------------------------------+ +---------------------------------------------------------------+ ; Port Connectivity Checks: "spdif_transmitter:\spdif_on:spdif" ; +----------------+-------+----------+---------------------------+ ; Port ; Type ; Severity ; Details ; +----------------+-------+----------+---------------------------+ ; left_in[7..0] ; Input ; Info ; Stuck at GND ; ; right_in[7..0] ; Input ; Info ; Stuck at GND ; +----------------+-------+----------+---------------------------+ +----------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd" ; +--------+-------+----------+------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +--------+-------+----------+------------------------------------------------------------------------+ ; enable ; Input ; Info ; Stuck at VCC ; +--------+-------+----------+------------------------------------------------------------------------+ +-----------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "sigmadelta_dither:dac_dithergen" ; +-------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-------------+--------+----------+-------------------------------------------------------------------------------------+ ; dither_out2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "mixer:mixer1" ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ ; b_ch1_en[3..2] ; Input ; Info ; Stuck at VCC ; ; b_ch1_en[1..0] ; Input ; Info ; Stuck at GND ; ; l_ch1 ; Input ; Info ; Stuck at GND ; ; l_ch2 ; Input ; Info ; Stuck at GND ; ; l_ch3 ; Input ; Info ; Stuck at GND ; ; l_ch4 ; Input ; Info ; Stuck at GND ; ; r_ch0 ; Input ; Info ; Stuck at GND ; ; r_ch1 ; Input ; Info ; Stuck at GND ; ; r_ch2 ; Input ; Info ; Stuck at GND ; ; r_ch3 ; Input ; Info ; Stuck at GND ; ; r_ch4 ; Input ; Info ; Stuck at GND ; ; b_ch0[9..0] ; Input ; Info ; Stuck at GND ; ; b_ch0[10] ; Input ; Info ; Stuck at VCC ; ; mute_channel ; Input ; Info ; Stuck at GND ; ; s_audio ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; s_left ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; s_right ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; s_channel ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; audio_1_signed ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "complete_address_decoder:\gen_config:decode_addr1" ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; addr_decoded[15..13] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; addr_decoded[11..10] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; addr_decoded[6..5] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; addr_decoded[8] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|latch_delay_line:stimer_delay" ; +------------+-------+----------+----------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+----------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+----------------------------------------+ +-----------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|latch_delay_line:twotone_del" ; +------------+-------+----------+---------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+---------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+---------------------------------------+ +-----------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audctl_delay" ; +------------+-------+----------+---------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+---------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+---------------------------------------+ +----------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf3_delay" ; +------------+-------+----------+--------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------+ +----------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf2_delay" ; +------------+-------+----------+--------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------+ +----------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf1_delay" ; +------------+-------+----------+--------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------+ +----------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf0_delay" ; +------------+-------+----------+--------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+-------+----------+--------------------------------------+ ; sync_reset ; Input ; Info ; Stuck at GND ; +------------+-------+----------+--------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1|complete_address_decoder:decode_addr1" ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; addr_decoded[12] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey:pokey1" ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ ; keyboard_scan_update ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; sio_out3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +----------------------+--------+----------+-------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "pokey_mixer_mux:pokey_mixer_both" ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; volume_out_1 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; volume_out_2 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; volume_out_3 ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; profile_request ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; profile_ready ; Input ; Info ; Stuck at VCC ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "slave_timing_6502:bus_adapt" ; +---------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------------------+--------+----------+-------------------------------------------------------------------------------------+ ; bus_addr[7..4] ; Input ; Info ; Stuck at GND ; ; cs ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; enable_double_cycle ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +---------------------+--------+----------+-------------------------------------------------------------------------------------+ +--------------------------------------------------------------------+ ; Port Connectivity Checks: "synchronizer:synchronizer_fancy_enable" ; +------+-------+----------+------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+-------+----------+------------------------------------------+ ; raw ; Input ; Info ; Stuck at GND ; +------+-------+----------+------------------------------------------+ +------------------------------------------------------------------+ ; Port Connectivity Checks: "synchronizer:synchronizer_gtia_audio" ; +------+-------+----------+----------------------------------------+ ; Port ; Type ; Severity ; Details ; +------+-------+----------+----------------------------------------+ ; raw ; Input ; Info ; Stuck at GND ; +------+-------+----------+----------------------------------------+ +------------------------------------------------+ ; Port Connectivity Checks: "int_osc:oscillator" ; +--------+-------+----------+--------------------+ ; Port ; Type ; Severity ; Details ; +--------+-------+----------+--------------------+ ; oscena ; Input ; Info ; Stuck at VCC ; +--------+-------+----------+--------------------+ +-----------------------------------------------------+ ; Post-Synthesis Netlist Statistics for Top Partition ; +----------------------------+------------------------+ ; Type ; Count ; +----------------------------+------------------------+ ; boundary_port ; 70 ; ; cycloneiii_ff ; 874 ; ; CLR ; 251 ; ; ENA ; 89 ; ; ENA CLR ; 421 ; ; ENA CLR SCLR ; 20 ; ; ENA CLR SLD ; 51 ; ; ENA SCLR ; 6 ; ; SLD ; 1 ; ; plain ; 35 ; ; cycloneiii_io_obuf ; 39 ; ; cycloneiii_lcell_comb ; 1067 ; ; arith ; 379 ; ; 2 data inputs ; 72 ; ; 3 data inputs ; 307 ; ; normal ; 688 ; ; 0 data inputs ; 4 ; ; 1 data inputs ; 49 ; ; 2 data inputs ; 63 ; ; 3 data inputs ; 154 ; ; 4 data inputs ; 418 ; ; cycloneiii_pll ; 1 ; ; cycloneiii_pseudo_diff_out ; 8 ; ; fiftyfivenm_io_ibuf ; 8 ; ; fiftyfivenm_oscillator ; 1 ; ; ; ; ; Max LUT depth ; 7.10 ; ; Average LUT depth ; 3.34 ; +----------------------------+------------------------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:01 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus Prime Analysis & Synthesis Info: Version 25.1std.0 Build 1129 10/21/2025 SC Lite Edition Info: Processing started: Fri Jun 19 21:55:38 2026 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pokeymax -c pokeymax Warning (125092): Tcl Script File flash/synthesis/flash.qip not found Info (125063): set_global_assignment -name QIP_FILE flash/synthesis/flash.qip Info (16303): Aggressive Area optimization mode selected -- logic area will be prioritized at the potential cost of reduced timing performance Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (20030): Parallel compilation is enabled and will use 16 of the 24 processors detected Info (12021): Found 2 design units, including 1 entities, in source file audio_signal_detector.vhd Info (12022): Found design unit 1: audio_signal_detector-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/audio_signal_detector.vhd Line: 31 Info (12023): Found entity 1: audio_signal_detector File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/audio_signal_detector.vhd Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file flash_controller.vhd Info (12022): Found design unit 1: flash_controller-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/flash_controller.vhd Line: 54 Info (12023): Found entity 1: flash_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/flash_controller.vhd Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file stereo_detect.vhd Info (12022): Found design unit 1: stereo_detect-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/stereo_detect.vhd Line: 24 Info (12023): Found entity 1: stereo_detect File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/stereo_detect.vhd Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file iox_glue.vhdl Info (12022): Found design unit 1: iox_glue-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/iox_glue.vhdl Line: 46 Info (12023): Found entity 1: iox_glue File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/iox_glue.vhdl Line: 22 Info (12021): Found 2 design units, including 1 entities, in source file i2c_master.vhd Info (12022): Found design unit 1: i2c_master-logic File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/i2c_master.vhd Line: 54 Info (12023): Found entity 1: i2c_master File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/i2c_master.vhd Line: 36 Info (12021): Found 2 design units, including 1 entities, in source file slave_timing_6502.vhd Info (12022): Found design unit 1: slave_timing_6502-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/slave_timing_6502.vhd Line: 40 Info (12023): Found entity 1: slave_timing_6502 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/slave_timing_6502.vhd Line: 6 Info (12021): Found 2 design units, including 1 entities, in source file pll_reset_sync.vhdl Info (12022): Found design unit 1: pll_reset_sync-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pll_reset_sync.vhdl Line: 16 Info (12023): Found entity 1: pll_reset_sync File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pll_reset_sync.vhdl Line: 5 Info (12021): Found 2 design units, including 1 entities, in source file complete_address_decoder.vhdl Info (12022): Found design unit 1: complete_address_decoder-tree File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/complete_address_decoder.vhdl Line: 30 Info (12023): Found entity 1: complete_address_decoder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/complete_address_decoder.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file syncreset_enable_divider.vhd Info (12022): Found design unit 1: syncreset_enable_divider-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/syncreset_enable_divider.vhd Line: 25 Info (12023): Found entity 1: syncreset_enable_divider File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/syncreset_enable_divider.vhd Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file enable_divider.vhdl Info (12022): Found design unit 1: enable_divider-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/enable_divider.vhdl Line: 24 Info (12023): Found entity 1: enable_divider File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/enable_divider.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file delay_line.vhdl Info (12022): Found design unit 1: delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/delay_line.vhdl Line: 26 Info (12023): Found entity 1: delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/delay_line.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file wide_delay_line.vhdl Info (12022): Found design unit 1: wide_delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/wide_delay_line.vhdl Line: 26 Info (12023): Found entity 1: wide_delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/wide_delay_line.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file latch_delay_line.vhdl Info (12022): Found design unit 1: latch_delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/latch_delay_line.vhdl Line: 26 Info (12023): Found entity 1: latch_delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/latch_delay_line.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_1storder.vhd Info (12022): Found design unit 1: sigmadelta_1storder-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_1storder.vhd Line: 27 Info (12023): Found entity 1: sigmadelta_1storder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_1storder.vhd Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_2ndorder.vhd Info (12022): Found design unit 1: sigmadelta_2ndorder-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_2ndorder.vhd Line: 27 Info (12023): Found entity 1: sigmadelta_2ndorder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_2ndorder.vhd Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_dither.vhd Info (12022): Found design unit 1: sigmadelta_dither-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_dither.vhd Line: 32 Info (12023): Found entity 1: sigmadelta_dither File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_dither.vhd Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_2ndorder_dither.vhd Info (12022): Found design unit 1: sigmadelta_2ndorder_dither-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_2ndorder_dither.vhd Line: 32 Info (12023): Found entity 1: sigmadelta_2ndorder_dither File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigmadelta_2ndorder_dither.vhd Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file filtered_sigmadelta.vhd Info (12022): Found design unit 1: filtered_sigmadelta-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/filtered_sigmadelta.vhd Line: 34 Info (12023): Found entity 1: filtered_sigmadelta File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/filtered_sigmadelta.vhd Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file fir_filter.vhdl Info (12022): Found design unit 1: fir_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_filter.vhdl Line: 40 Info (12023): Found entity 1: fir_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_filter.vhdl Line: 15 Warning (12019): Can't analyze file -- file fir_rom.vhdl is missing Info (12021): Found 2 design units, including 1 entities, in source file generic_ram_infer.vhdl Info (12022): Found design unit 1: generic_ram_infer-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/generic_ram_infer.vhdl Line: 30 Info (12023): Found entity 1: generic_ram_infer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/generic_ram_infer.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file m9k_grouped.vhdl Info (12022): Found design unit 1: m9k_grouped-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/m9k_grouped.vhdl Line: 38 Info (12023): Found entity 1: m9k_grouped File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/m9k_grouped.vhdl Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file simple_low_pass_filter.vhdl Info (12022): Found design unit 1: simple_low_pass_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/simple_low_pass_filter.vhdl Line: 29 Info (12023): Found entity 1: simple_low_pass_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/simple_low_pass_filter.vhdl Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_17_9.vhdl Info (12022): Found design unit 1: pokey_poly_17_9-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_17_9.vhdl Line: 27 Info (12023): Found entity 1: pokey_poly_17_9 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_17_9.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_5.vhdl Info (12022): Found design unit 1: pokey_poly_5-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_5.vhdl Line: 24 Info (12023): Found entity 1: pokey_poly_5 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_5.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_4.vhdl Info (12022): Found design unit 1: pokey_poly_4-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_4.vhdl Line: 24 Info (12023): Found entity 1: pokey_poly_4 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_poly_4.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_noise_filter.vhdl Info (12022): Found design unit 1: pokey_noise_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_noise_filter.vhdl Line: 32 Info (12023): Found entity 1: pokey_noise_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_noise_filter.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_mixer_mux.vhdl Info (12022): Found design unit 1: pokey_mixer_mux-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_mixer_mux.vhdl Line: 36 Info (12023): Found entity 1: pokey_mixer_mux File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_mixer_mux.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_mixer.vhdl Info (12022): Found design unit 1: pokey_mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_mixer.vhdl Line: 24 Info (12023): Found entity 1: pokey_mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_mixer.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_keyboard_scanner.vhdl Info (12022): Found design unit 1: pokey_keyboard_scanner-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_keyboard_scanner.vhdl Line: 33 Info (12023): Found entity 1: pokey_keyboard_scanner File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_keyboard_scanner.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_countdown_timer.vhdl Info (12022): Found design unit 1: pokey_countdown_timer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_countdown_timer.vhdl Line: 28 Info (12023): Found entity 1: pokey_countdown_timer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_countdown_timer.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey.vhdl Info (12022): Found design unit 1: pokey-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 63 Info (12023): Found entity 1: pokey File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 14 Info (12021): Found 2 design units, including 1 entities, in source file phi_mult.vhdl Info (12022): Found design unit 1: phi_mult-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/phi_mult.vhdl Line: 21 Info (12023): Found entity 1: phi_mult File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/phi_mult.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file synchronizer.vhdl Info (12022): Found design unit 1: synchronizer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/synchronizer.vhdl Line: 21 Info (12023): Found entity 1: synchronizer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/synchronizer.vhdl Line: 12 Info (12021): Found 1 design units, including 0 entities, in source file audiotypes.vhdl Info (12022): Found design unit 1: AudioTypes File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/audiotypes.vhdl Line: 5 Info (12021): Found 2 design units, including 1 entities, in source file dc_blocker.vhdl Info (12022): Found design unit 1: dc_blocker-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/dc_blocker.vhdl Line: 42 Info (12023): Found entity 1: dc_blocker File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/dc_blocker.vhdl Line: 24 Info (12021): Found 2 design units, including 1 entities, in source file mixer.vhdl Info (12022): Found design unit 1: mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/mixer.vhdl Line: 58 Info (12023): Found entity 1: mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/mixer.vhdl Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file clockgen.vhd Info (12022): Found design unit 1: clockgen-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/clockgen.vhd Line: 35 Info (12023): Found entity 1: clockgen File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/clockgen.vhd Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file spdif_transmitter.vhdl Info (12022): Found design unit 1: spdif_transmitter-behavioral File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/spdif_transmitter.vhdl Line: 16 Info (12023): Found entity 1: spdif_transmitter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/spdif_transmitter.vhdl Line: 7 Info (12021): Found 2 design units, including 1 entities, in source file ps2_keyboard.vhdl Info (12022): Found design unit 1: ps2_keyboard-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/ps2_keyboard.vhdl Line: 35 Info (12023): Found entity 1: ps2_keyboard File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/ps2_keyboard.vhdl Line: 20 Info (12021): Found 2 design units, including 1 entities, in source file ps2_to_atari800.vhdl Info (12022): Found design unit 1: ps2_to_atari800-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/ps2_to_atari800.vhdl Line: 51 Info (12023): Found entity 1: ps2_to_atari800 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/ps2_to_atari800.vhdl Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file pokeymax.vhd Info (12022): Found design unit 1: pokeymax-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 119 Info (12023): Found entity 1: pokeymax File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file PSG/envelope.vhdl Info (12022): Found design unit 1: PSG_envelope-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/envelope.vhdl Line: 28 Info (12023): Found entity 1: PSG_envelope File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/envelope.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/noise.vhdl Info (12022): Found design unit 1: PSG_noise-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/noise.vhdl Line: 24 Info (12023): Found entity 1: PSG_noise File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/noise.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/top.vhdl Info (12022): Found design unit 1: PSG_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/top.vhdl Line: 49 Info (12023): Found entity 1: PSG_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/top.vhdl Line: 18 Info (12021): Found 2 design units, including 1 entities, in source file PSG/freqdiv.vhdl Info (12022): Found design unit 1: PSG_freqdiv-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/freqdiv.vhdl Line: 31 Info (12023): Found entity 1: PSG_freqdiv File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/freqdiv.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/mixer.vhdl Info (12022): Found design unit 1: PSG_mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/mixer.vhdl Line: 29 Info (12023): Found entity 1: PSG_mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/mixer.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/volume.vhdl Info (12022): Found design unit 1: PSG_volume-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/volume.vhdl Line: 28 Info (12023): Found entity 1: PSG_volume File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/volume.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file PSG/volume_profile.vhdl Info (12022): Found design unit 1: PSG_volume_profile-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/volume_profile.vhdl Line: 41 Info (12023): Found entity 1: PSG_volume_profile File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/PSG/volume_profile.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file SID/top.vhdl Info (12022): Found design unit 1: SID_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/top.vhdl Line: 64 Info (12023): Found entity 1: SID_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/top.vhdl Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file SID/oscillator.vhdl Info (12022): Found design unit 1: SID_oscillator-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/oscillator.vhdl Line: 31 Info (12023): Found entity 1: SID_oscillator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/oscillator.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/wavegen.vhdl Info (12022): Found design unit 1: SID_wavegen-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/wavegen.vhdl Line: 43 Info (12023): Found entity 1: SID_wavegen File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/wavegen.vhdl Line: 16 Info (12021): Found 2 design units, including 1 entities, in source file SID/envelope.vhdl Info (12022): Found design unit 1: SID_envelope-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/envelope.vhdl Line: 36 Info (12023): Found entity 1: SID_envelope File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/envelope.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file SID/envelope_tapmatch.vhdl Info (12022): Found design unit 1: SID_envelope_tapmatch-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/envelope_tapmatch.vhdl Line: 31 Info (12023): Found entity 1: SID_envelope_tapmatch File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/envelope_tapmatch.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file SID/amplitudeModulator.vhdl Info (12022): Found design unit 1: SID_amplitudeModulator-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/amplitudeModulator.vhdl Line: 29 Info (12023): Found entity 1: SID_amplitudeModulator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/amplitudeModulator.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/preFilterSum.vhdl Info (12022): Found design unit 1: SID_preFilterSum-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/preFilterSum.vhdl Line: 31 Info (12023): Found entity 1: SID_preFilterSum File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/preFilterSum.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/filter.vhdl Info (12022): Found design unit 1: SID_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/filter.vhdl Line: 147 Info (12023): Found entity 1: SID_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/filter.vhdl Line: 48 Info (12021): Found 2 design units, including 1 entities, in source file SID/f_distortion.vhdl Info (12022): Found design unit 1: SID_f_distortion-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/f_distortion.vhdl Line: 24 Info (12023): Found entity 1: SID_f_distortion File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/f_distortion.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/f_distortion_mux.vhdl Info (12022): Found design unit 1: SID_f_distortion_mux-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/f_distortion_mux.vhdl Line: 33 Info (12023): Found entity 1: SID_f_distortion_mux File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/f_distortion_mux.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file SID/postFilterSum.vhdl Info (12022): Found design unit 1: SID_postFilterSum-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/postFilterSum.vhdl Line: 30 Info (12023): Found entity 1: SID_postFilterSum File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/SID/postFilterSum.vhdl Line: 12 Info (12021): Found 2 design units, including 1 entities, in source file sample/channel.vhdl Info (12022): Found design unit 1: sample_channel-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/channel.vhdl Line: 33 Info (12023): Found entity 1: sample_channel File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/channel.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file sample/adpcm.vhdl Info (12022): Found design unit 1: sample_adpcm-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/adpcm.vhdl Line: 39 Info (12023): Found entity 1: sample_adpcm File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/adpcm.vhdl Line: 13 Info (12021): Found 2 design units, including 1 entities, in source file sample/top.vhdl Info (12022): Found design unit 1: sample_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/top.vhdl Line: 56 Info (12023): Found entity 1: sample_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sample/top.vhdl Line: 17 Info (12021): Found 2 design units, including 1 entities, in source file covox/top.vhdl Info (12022): Found design unit 1: covox_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/covox/top.vhdl Line: 33 Info (12023): Found entity 1: covox_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/covox/top.vhdl Line: 17 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/sigma_delta_adc.sv Info (12023): Found entity 1: sigma_delta_adc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigma_delta/sigma_delta_adc.sv Line: 5 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/cic_comb.sv Info (12023): Found entity 1: cic_comb File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigma_delta/cic_comb.sv Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/cic_integrator.sv Info (12023): Found entity 1: cic_integrator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigma_delta/cic_integrator.sv Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file sigma_delta/fir_compensator.sv Info (12023): Found entity 1: fir_compensator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/sigma_delta/fir_compensator.sv Line: 19 Info (12021): Found 2 design units, including 1 entities, in source file int_osc/synthesis/int_osc.vhd Info (12022): Found design unit 1: int_osc-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/int_osc/synthesis/int_osc.vhd Line: 16 Info (12023): Found entity 1: int_osc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/int_osc/synthesis/int_osc.vhd Line: 9 Info (12021): Found 1 design units, including 1 entities, in source file int_osc/synthesis/submodules/altera_int_osc.v Info (12023): Found entity 1: altera_int_osc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/int_osc/synthesis/submodules/altera_int_osc.v Line: 38 Info (12021): Found 2 design units, including 1 entities, in source file pll.vhd Info (12022): Found design unit 1: pll-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pll.vhd Line: 55 Info (12023): Found entity 1: pll File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pll.vhd Line: 43 Info (12021): Found 2 design units, including 1 entities, in source file pllv3.vhd Info (12022): Found design unit 1: pllv3-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pllv3.vhd Line: 56 Info (12023): Found entity 1: pllv3 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pllv3.vhd Line: 43 Info (12021): Found 2 design units, including 1 entities, in source file lvds_tx.vhd Info (12022): Found design unit 1: lvds_tx-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_tx.vhd Line: 18 Info (12023): Found entity 1: lvds_tx File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_tx.vhd Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v Info (12023): Found entity 1: altera_soft_lvds_tx_uCmMXfGB File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_tx/altera_soft_lvds_tx_uCmMXfGB.v Line: 29 Info (12021): Found 2 design units, including 1 entities, in source file lvds_rx.vhd Info (12022): Found design unit 1: lvds_rx-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_rx.vhd Line: 19 Info (12023): Found entity 1: lvds_rx File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_rx.vhd Line: 11 Info (12021): Found 1 design units, including 1 entities, in source file lvds_rx/altera_soft_lvds_rx_uCmNW05P.v Info (12023): Found entity 1: altera_soft_lvds_rx_uCmNW05P File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/lvds_rx/altera_soft_lvds_rx_uCmNW05P.v Line: 29 Info (12021): Found 2 design units, including 1 entities, in source file paddle_gpio.vhd Info (12022): Found design unit 1: paddle_gpio-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio.vhd Line: 21 Info (12023): Found entity 1: paddle_gpio File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio.vhd Line: 11 Info (12021): Found 2 design units, including 2 entities, in source file paddle_gpio/altera_gpio_lite.sv Info (12023): Found entity 1: altgpio_one_bit File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 16 Info (12023): Found entity 2: altera_gpio_lite File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 940 Info (12021): Found 2 design units, including 1 entities, in source file fir_sample_buffer.vhd Info (12022): Found design unit 1: fir_sample_buffer-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_sample_buffer.vhd Line: 59 Info (12023): Found entity 1: fir_sample_buffer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_sample_buffer.vhd Line: 43 Info (12021): Found 2 design units, including 1 entities, in source file fir_buffer.vhd Info (12022): Found design unit 1: fir_buffer-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_buffer.vhd Line: 57 Info (12023): Found entity 1: fir_buffer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/fir_buffer.vhd Line: 43 Info (12127): Elaborating entity "pokeymax" for the top level hierarchy Warning (10445): VHDL Subtype or Type Declaration warning at pokeymax.vhd(109): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 109 Warning (10445): VHDL Subtype or Type Declaration warning at pokeymax.vhd(931): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 931 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(193): object "ENABLE_DOUBLE_CYCLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 193 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(198): object "SID_WRITE_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 198 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(199): object "SID_READ_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 199 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(201): object "PSG_WRITE_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 201 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(203): object "SAMPLE_WRITE_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 203 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(259): object "SIGMADELTA_DITHER2" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 259 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(267): object "KEYBOARD_SCAN_UPDATE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 267 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(268): used implicit default value for signal "KEYBOARD_SCAN_ENABLE" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 268 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(271): object "POKEY_PROFILE_REQUEST" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 271 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(277): object "SID_AUDIO_IN_SIGNED" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 277 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(392): object "SAMPLE_AUDIO_IN_SIGNED" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 392 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(400): object "ADPCM_STEP_REQUEST" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 400 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(404): object "mixer_audio_out" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 404 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(405): object "mixer_l_enable" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 405 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(406): object "mixer_r_enable" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 406 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(407): object "mixer_audio_out_channel" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 407 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(409): object "MIXER_SIGNED_REG" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 409 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(410): used implicit default value for signal "MIXER_SIGNED_NEXT" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 410 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(419): object "CPU_FLASH_REQUEST_NEXT" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 419 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(420): used implicit default value for signal "CPU_FLASH_REQUEST_REG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 420 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(421): object "CPU_FLASH_WRITE_N_NEXT" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 421 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(422): used implicit default value for signal "CPU_FLASH_WRITE_N_REG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 422 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(423): object "CPU_FLASH_CFG_NEXT" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 423 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(424): used implicit default value for signal "CPU_FLASH_CFG_REG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 424 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(425): object "CPU_FLASH_ADDR_NEXT" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 425 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(426): used implicit default value for signal "CPU_FLASH_ADDR_REG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 426 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(427): object "CPU_FLASH_DATA_NEXT" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 427 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(428): used implicit default value for signal "CPU_FLASH_DATA_REG" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 428 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(429): used implicit default value for signal "CPU_FLASH_COMPLETE" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 429 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(437): used implicit default value for signal "CONFIG_FLASH_COMPLETE" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 437 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(438): used implicit default value for signal "CONFIG_FLASH_ADDR" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 438 Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(509): object "SIO_AUDIO_UNSIGNED" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 509 Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(510): used implicit default value for signal "SIO_AUDIO_SIGNED" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 510 Warning (10492): VHDL Process Statement warning at pokeymax.vhd(2448): signal "SIO_RXD_ADC" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2448 Warning (10492): VHDL Process Statement warning at pokeymax.vhd(2450): signal "SIO_RXD_ADC" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2450 Warning (10492): VHDL Process Statement warning at pokeymax.vhd(2452): signal "SIO_RXD_ADC" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2452 Warning (10873): Using initial value X (don't care) for net "ADC_TX_P" at pokeymax.vhd(103) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 103 Warning (10873): Using initial value X (don't care) for net "POTRESET_N" at pokeymax.vhd(110) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 110 Warning (10873): Using initial value X (don't care) for net "IOX_RST" at pokeymax.vhd(112) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 112 Info (12128): Elaborating entity "int_osc" for hierarchy "int_osc:oscillator" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 550 Info (12128): Elaborating entity "altera_int_osc" for hierarchy "int_osc:oscillator|altera_int_osc:int_osc_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/int_osc/synthesis/int_osc.vhd Line: 31 Info (12128): Elaborating entity "synchronizer" for hierarchy "synchronizer:synchronizer_gtia_audio" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 682 Info (12128): Elaborating entity "pllv3" for hierarchy "pllv3:\pll_v3_inst:pll_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 703 Info (12128): Elaborating entity "altpll" for hierarchy "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pllv3.vhd Line: 163 Info (12130): Elaborated megafunction instantiation "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pllv3.vhd Line: 163 Info (12133): Instantiated megafunction "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pllv3.vhd Line: 163 Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "6" Info (12134): Parameter "clk0_duty_cycle" = "50" Info (12134): Parameter "clk0_multiply_by" = "7" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "3" Info (12134): Parameter "clk1_duty_cycle" = "50" Info (12134): Parameter "clk1_multiply_by" = "7" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "clk2_divide_by" = "1" Info (12134): Parameter "clk2_duty_cycle" = "50" Info (12134): Parameter "clk2_multiply_by" = "2" Info (12134): Parameter "clk2_phase_shift" = "0" Info (12134): Parameter "clk3_divide_by" = "8" Info (12134): Parameter "clk3_duty_cycle" = "50" Info (12134): Parameter "clk3_multiply_by" = "1" Info (12134): Parameter "clk3_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "20345" Info (12134): Parameter "intended_device_family" = "MAX 10" Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pllv3" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "port_activeclock" = "PORT_UNUSED" Info (12134): Parameter "port_areset" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED" Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED" Info (12134): Parameter "port_clkloss" = "PORT_UNUSED" Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED" Info (12134): Parameter "port_configupdate" = "PORT_UNUSED" Info (12134): Parameter "port_fbin" = "PORT_UNUSED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_inclk1" = "PORT_UNUSED" Info (12134): Parameter "port_locked" = "PORT_USED" Info (12134): Parameter "port_pfdena" = "PORT_UNUSED" Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED" Info (12134): Parameter "port_phasedone" = "PORT_UNUSED" Info (12134): Parameter "port_phasestep" = "PORT_UNUSED" Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED" Info (12134): Parameter "port_pllena" = "PORT_UNUSED" Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED" Info (12134): Parameter "port_scanclk" = "PORT_UNUSED" Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED" Info (12134): Parameter "port_scandata" = "PORT_UNUSED" Info (12134): Parameter "port_scandataout" = "PORT_UNUSED" Info (12134): Parameter "port_scandone" = "PORT_UNUSED" Info (12134): Parameter "port_scanread" = "PORT_UNUSED" Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_USED" Info (12134): Parameter "port_clk2" = "PORT_USED" Info (12134): Parameter "port_clk3" = "PORT_USED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "port_clk5" = "PORT_UNUSED" Info (12134): Parameter "port_clkena0" = "PORT_UNUSED" Info (12134): Parameter "port_clkena1" = "PORT_UNUSED" Info (12134): Parameter "port_clkena2" = "PORT_UNUSED" Info (12134): Parameter "port_clkena3" = "PORT_UNUSED" Info (12134): Parameter "port_clkena4" = "PORT_UNUSED" Info (12134): Parameter "port_clkena5" = "PORT_UNUSED" Info (12134): Parameter "port_extclk0" = "PORT_UNUSED" Info (12134): Parameter "port_extclk1" = "PORT_UNUSED" Info (12134): Parameter "port_extclk2" = "PORT_UNUSED" Info (12134): Parameter "port_extclk3" = "PORT_UNUSED" Info (12134): Parameter "self_reset_on_loss_lock" = "ON" Info (12134): Parameter "width_clock" = "5" Info (12021): Found 1 design units, including 1 entities, in source file db/pllv3_altpll.v Info (12023): Found entity 1: pllv3_altpll File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/db/pllv3_altpll.v Line: 30 Info (12128): Elaborating entity "pllv3_altpll" for hierarchy "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated" File: /home/markw/intelFPGA_lite/25.1std/quartus/libraries/megafunctions/altpll.tdf Line: 898 Info (12128): Elaborating entity "pll_reset_sync" for hierarchy "pll_reset_sync:pll_sync" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 713 Info (12128): Elaborating entity "slave_timing_6502" for hierarchy "slave_timing_6502:bus_adapt" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 726 Info (12128): Elaborating entity "pokey_mixer_mux" for hierarchy "pokey_mixer_mux:pokey_mixer_both" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 839 Info (12128): Elaborating entity "pokey_mixer" for hierarchy "pokey_mixer:\flash_off:shared_pokey_mixer" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 857 Info (12128): Elaborating entity "pokey" for hierarchy "pokey:pokey1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 872 Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "pokey:pokey1|complete_address_decoder:decode_addr1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 621 Info (12128): Elaborating entity "wide_delay_line" for hierarchy "pokey:pokey1|wide_delay_line:audf0_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 657 Warning (10445): VHDL Subtype or Type Declaration warning at wide_delay_line.vhdl(47): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/wide_delay_line.vhdl Line: 47 Info (12128): Elaborating entity "pokey_countdown_timer" for hierarchy "pokey:pokey1|pokey_countdown_timer:timer0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 674 Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey_countdown_timer.vhdl Line: 62 Info (12128): Elaborating entity "latch_delay_line" for hierarchy "pokey:pokey1|latch_delay_line:twotone_del" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 701 Info (12128): Elaborating entity "latch_delay_line" for hierarchy "pokey:pokey1|latch_delay_line:stimer_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 914 Info (12128): Elaborating entity "pokey_noise_filter" for hierarchy "pokey:pokey1|pokey_noise_filter:pokey_noise_filter0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 921 Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "pokey:pokey1|syncreset_enable_divider:enable_64_div" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 981 Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "pokey:pokey1|syncreset_enable_divider:enable_15_div" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 985 Info (12128): Elaborating entity "pokey_poly_17_9" for hierarchy "pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 992 Info (12128): Elaborating entity "pokey_poly_5" for hierarchy "pokey:pokey1|pokey_poly_5:poly_5_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 995 Info (12128): Elaborating entity "pokey_poly_4" for hierarchy "pokey:pokey1|pokey_poly_4:poly_4_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 998 Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:pokey1|delay_line:serout_clock_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 1044 Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:pokey1|delay_line:serin_clock_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 1048 Info (12128): Elaborating entity "pokey_keyboard_scanner" for hierarchy "pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 1284 Info (12128): Elaborating entity "dc_blocker" for hierarchy "dc_blocker:pokey1_dc_blocker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 904 Info (12128): Elaborating entity "mixer" for hierarchy "mixer:mixer1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 1974 Info (12128): Elaborating entity "sigmadelta_dither" for hierarchy "sigmadelta_dither:dac_dithergen" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2067 Info (12128): Elaborating entity "filtered_sigmadelta" for hierarchy "filtered_sigmadelta:dac_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2080 Info (12128): Elaborating entity "sigmadelta_2ndorder" for hierarchy "filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/filtered_sigmadelta.vhd Line: 96 Info (12128): Elaborating entity "simple_low_pass_filter" for hierarchy "simple_low_pass_filter:\spdif_on:filter_left" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2159 Info (12128): Elaborating entity "spdif_transmitter" for hierarchy "spdif_transmitter:\spdif_on:spdif" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2178 Warning (10540): VHDL Signal Declaration warning at spdif_transmitter.vhdl(25): used explicit default value for signal "channel_status" because signal was never assigned a value File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/spdif_transmitter.vhdl Line: 25 Info (12128): Elaborating entity "paddle_gpio" for hierarchy "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 2459 Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio.vhd Line: 78 Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 1115 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 82 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(110): object "outclocken_wire" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 110 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 334 Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(540): object "inclocken_wire" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/paddle_gpio/altera_gpio_lite.sv Line: 540 Warning (13039): The following bidirectional pins have no drivers Warning (13040): bidirectional pin "IOX_SDA" has no driver File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 114 Warning (13040): bidirectional pin "IOX_SCL" has no driver File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 115 Warning (13027): Removed fan-outs from the following always-disabled I/O buffers Warning (13028): Removed fan-out from the always-disabled I/O buffer "EXT[10]" to the node "EXT[10]" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 95 Info (13000): Registers with preset signals will power-up high File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokey/pokey.vhdl Line: 452 Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Warning (13009): TRI or OPNDRN buffers permanently enabled Warning (13010): Node "EXT[10]~synth" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 95 Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "AUD[2]" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 93 Warning (13410): Pin "ADC_TX_P" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 103 Warning (13410): Pin "POTRESET_N" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 110 Warning (13410): Pin "IOX_RST" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 112 Info (286030): Timing-Driven Synthesis is running Info (17049): 47 registers lost all their fanouts during netlist optimizations. Warning (20013): Ignored 66 assignments for entity "altera_soft_lvds_rx_uCmNW05P" -- entity does not exist in design Warning (20013): Ignored 66 assignments for entity "altera_soft_lvds_tx_uCmMXfGB" -- entity does not exist in design Warning (20013): Ignored 13 assignments for entity "lvds_rx" -- entity does not exist in design Warning (20013): Ignored 13 assignments for entity "lvds_tx" -- entity does not exist in design Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL Warning (21074): Design contains 4 input pin(s) that do not drive logic Warning (15610): No output dependent on input pin "CLK_SLOW" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 77 Warning (15610): No output dependent on input pin "CLK1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 80 Warning (15610): No output dependent on input pin "ADC_RX_P" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 105 Warning (15610): No output dependent on input pin "IOX_INT" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_pokeymax_v4_M02_314002MA_mono/pokeymax.vhd Line: 113 Info (21057): Implemented 1530 device resources after synthesis - the final resource count might be different Info (21058): Implemented 16 input pins Info (21059): Implemented 16 output pins Info (21060): Implemented 38 bidirectional pins Info (21061): Implemented 1450 logic cells Info (21065): Implemented 1 PLLs Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 71 warnings Info: Peak virtual memory: 459 megabytes Info: Processing ended: Fri Jun 19 21:55:42 2026 Info: Elapsed time: 00:00:04 Info: Total CPU time (on all processors): 00:00:11