Analysis & Synthesis report for pokeymax
Sat May 11 10:22:53 2024
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Default Parameter Settings
  5. Parallel Compilation
  6. Analysis & Synthesis Source Files Read
  7. Analysis & Synthesis Resource Usage Summary
  8. Analysis & Synthesis Resource Utilization by Entity
  9. Analysis & Synthesis RAM Summary
 10. Analysis & Synthesis IP Cores Summary
 11. State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state
 12. State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state
 13. State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state
 14. State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state
 15. Registers Protected by Synthesis
 16. Logic Cells Representing Combinational Loops
 17. Registers Removed During Synthesis
 18. Removed Registers Triggering Further Register Optimizations
 19. General Register Statistics
 20. Inverted Register Statistics
 21. Registers Packed Into Inferred Megafunctions
 22. Multiplexer Restructuring Statistics (Restructuring Performed)
 23. Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy
 24. Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear
 25. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i
 26. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i
 27. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i
 28. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i
 29. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i
 30. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i
 31. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i
 32. Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i
 33. Source assignments for altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|altsyncram_4ga1:altsyncram2
 34. Parameter Settings for User Entity Instance: Top-level Entity: |pokeymax
 35. Parameter Settings for User Entity Instance: int_osc:oscillator|altera_int_osc:int_osc_0
 36. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst
 37. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0
 38. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller
 39. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller
 40. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy
 41. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear
 42. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg
 43. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker
 44. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor
 45. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker
 46. Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor
 47. Parameter Settings for User Entity Instance: pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component
 48. Parameter Settings for User Entity Instance: slave_timing_6502:bus_adapt
 49. Parameter Settings for User Entity Instance: pokey:pokey1
 50. Parameter Settings for User Entity Instance: pokey:pokey1|complete_address_decoder:decode_addr1
 51. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf0_delay
 52. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf1_delay
 53. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf2_delay
 54. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf3_delay
 55. Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audctl_delay
 56. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0
 57. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay
 58. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1
 59. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay
 60. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2
 61. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay
 62. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3
 63. Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay
 64. Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:twotone_del
 65. Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:stimer_delay
 66. Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_64_div
 67. Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_15_div
 68. Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serout_clock_delay
 69. Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serin_clock_delay
 70. Parameter Settings for User Entity Instance: complete_address_decoder:\gen_config:decode_addr1
 71. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0
 72. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2
 73. Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3
 74. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst
 75. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i
 76. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i
 77. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i
 78. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i
 79. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i
 80. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i
 81. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i
 82. Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i
 83. Parameter Settings for Inferred Entity Instance: altshift_taps:toggle_reg_rtl_0
 84. lpm_shiftreg Parameter Settings by Entity Instance
 85. altshift_taps Parameter Settings by Entity Instance
 86. altpll Parameter Settings by Entity Instance
 87. Port Connectivity Checks: "synchronizer:synchronizer_SIO"
 88. Port Connectivity Checks: "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0"
 89. Port Connectivity Checks: "simple_low_pass_filter:\adc_on:adcfilter"
 90. Port Connectivity Checks: "filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd"
 91. Port Connectivity Checks: "mixer:mixer1"
 92. Port Connectivity Checks: "complete_address_decoder:\gen_config:decode_addr1"
 93. Port Connectivity Checks: "pokey:pokey1|latch_delay_line:stimer_delay"
 94. Port Connectivity Checks: "pokey:pokey1|latch_delay_line:twotone_del"
 95. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audctl_delay"
 96. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf3_delay"
 97. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf2_delay"
 98. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf1_delay"
 99. Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf0_delay"
100. Port Connectivity Checks: "pokey:pokey1|complete_address_decoder:decode_addr1"
101. Port Connectivity Checks: "pokey:pokey1"
102. Port Connectivity Checks: "slave_timing_6502:bus_adapt"
103. Port Connectivity Checks: "pllv3:\pll_v3_inst:pll_inst"
104. Port Connectivity Checks: "synchronizer:synchronizer_fancy_enable"
105. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block"
106. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker"
107. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1"
108. Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst"
109. Port Connectivity Checks: "int_osc:oscillator"
110. Post-Synthesis Netlist Statistics for Top Partition
111. Elapsed Time Per Partition
112. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2020  Intel Corporation. All rights reserved.
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and other software and tools, and any partner logic 
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(including device programming or simulation files), and any 
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to the terms and conditions of the Intel Program License 
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the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+----------------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                                     ;
+------------------------------------+---------------------------------------------+
; Analysis & Synthesis Status        ; Successful - Sat May 11 10:22:53 2024       ;
; Quartus Prime Version              ; 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Revision Name                      ; pokeymax                                    ;
; Top-level Entity Name              ; pokeymax                                    ;
; Family                             ; MAX 10                                      ;
; Total logic elements               ; 2,448                                       ;
;     Total combinational functions  ; 1,924                                       ;
;     Dedicated logic registers      ; 1,451                                       ;
; Total registers                    ; 1451                                        ;
; Total pins                         ; 70                                          ;
; Total virtual pins                 ; 0                                           ;
; Total memory bits                  ; 253                                         ;
; Embedded Multiplier 9-bit elements ; 0                                           ;
; Total PLLs                         ; 1                                           ;
; UFM blocks                         ; 1                                           ;
; ADC blocks                         ; 0                                           ;
+------------------------------------+---------------------------------------------+


+------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                              ;
+------------------------------------------------------------------+--------------------+--------------------+
; Option                                                           ; Setting            ; Default Value      ;
+------------------------------------------------------------------+--------------------+--------------------+
; Device                                                           ; 10M16SCU169C8G     ;                    ;
; Top-level entity name                                            ; pokeymax           ; pokeymax           ;
; Family name                                                      ; MAX 10             ; Cyclone V          ;
; Optimization Technique                                           ; Area               ; Balanced           ;
; Use smart compilation                                            ; Off                ; Off                ;
; Enable parallel Assembler and Timing Analyzer during compilation ; On                 ; On                 ;
; Enable compact report table                                      ; Off                ; Off                ;
; Restructure Multiplexers                                         ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                              ; Off                ; Off                ;
; Preserve fewer node names                                        ; On                 ; On                 ;
; Intel FPGA IP Evaluation Mode                                    ; Enable             ; Enable             ;
; Verilog Version                                                  ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                     ; VHDL_1993          ; VHDL_1993          ;
; State Machine Processing                                         ; Auto               ; Auto               ;
; Safe State Machine                                               ; Off                ; Off                ;
; Extract Verilog State Machines                                   ; On                 ; On                 ;
; Extract VHDL State Machines                                      ; On                 ; On                 ;
; Ignore Verilog initial constructs                                ; Off                ; Off                ;
; Iteration limit for constant Verilog loops                       ; 5000               ; 5000               ;
; Iteration limit for non-constant Verilog loops                   ; 250                ; 250                ;
; Add Pass-Through Logic to Inferred RAMs                          ; On                 ; On                 ;
; Infer RAMs from Raw Logic                                        ; On                 ; On                 ;
; Parallel Synthesis                                               ; On                 ; On                 ;
; DSP Block Balancing                                              ; Auto               ; Auto               ;
; NOT Gate Push-Back                                               ; On                 ; On                 ;
; Power-Up Don't Care                                              ; On                 ; On                 ;
; Remove Redundant Logic Cells                                     ; Off                ; Off                ;
; Remove Duplicate Registers                                       ; On                 ; On                 ;
; Ignore CARRY Buffers                                             ; Off                ; Off                ;
; Ignore CASCADE Buffers                                           ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                            ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                        ; Off                ; Off                ;
; Ignore LCELL Buffers                                             ; Off                ; Off                ;
; Ignore SOFT Buffers                                              ; On                 ; On                 ;
; Limit AHDL Integers to 32 Bits                                   ; Off                ; Off                ;
; Carry Chain Length                                               ; 70                 ; 70                 ;
; Auto Carry Chains                                                ; On                 ; On                 ;
; Auto Open-Drain Pins                                             ; On                 ; On                 ;
; Perform WYSIWYG Primitive Resynthesis                            ; Off                ; Off                ;
; Auto ROM Replacement                                             ; On                 ; On                 ;
; Auto RAM Replacement                                             ; On                 ; On                 ;
; Auto DSP Block Replacement                                       ; On                 ; On                 ;
; Auto Shift Register Replacement                                  ; Auto               ; Auto               ;
; Allow Shift Register Merging across Hierarchies                  ; Auto               ; Auto               ;
; Auto Clock Enable Replacement                                    ; On                 ; On                 ;
; Strict RAM Replacement                                           ; Off                ; Off                ;
; Allow Synchronous Control Signals                                ; On                 ; On                 ;
; Force Use of Synchronous Clear Signals                           ; Off                ; Off                ;
; Auto RAM Block Balancing                                         ; On                 ; On                 ;
; Auto RAM to Logic Cell Conversion                                ; Off                ; Off                ;
; Auto Resource Sharing                                            ; Off                ; Off                ;
; Allow Any RAM Size For Recognition                               ; Off                ; Off                ;
; Allow Any ROM Size For Recognition                               ; Off                ; Off                ;
; Allow Any Shift Register Size For Recognition                    ; Off                ; Off                ;
; Use LogicLock Constraints during Resource Balancing              ; On                 ; On                 ;
; Ignore translate_off and synthesis_off directives                ; Off                ; Off                ;
; Timing-Driven Synthesis                                          ; On                 ; On                 ;
; Report Parameter Settings                                        ; On                 ; On                 ;
; Report Source Assignments                                        ; On                 ; On                 ;
; Report Connectivity Checks                                       ; On                 ; On                 ;
; Ignore Maximum Fan-Out Assignments                               ; Off                ; Off                ;
; Synchronization Register Chain Length                            ; 2                  ; 2                  ;
; Power Optimization During Synthesis                              ; Normal compilation ; Normal compilation ;
; HDL message level                                                ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                  ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report         ; 5000               ; 5000               ;
; Number of Swept Nodes Reported in Synthesis Report               ; 5000               ; 5000               ;
; Number of Inverted Registers Reported in Synthesis Report        ; 100                ; 100                ;
; Clock MUX Protection                                             ; On                 ; On                 ;
; Auto Gated Clock Conversion                                      ; Off                ; Off                ;
; Block Design Naming                                              ; Auto               ; Auto               ;
; SDC constraint protection                                        ; Off                ; Off                ;
; Synthesis Effort                                                 ; Auto               ; Auto               ;
; Shift Register Replacement - Allow Asynchronous Clear Signal     ; On                 ; On                 ;
; Pre-Mapping Resynthesis Optimization                             ; Off                ; Off                ;
; Analysis & Synthesis Message Level                               ; Medium             ; Medium             ;
; Disable Register Merging Across Hierarchies                      ; Auto               ; Auto               ;
; Resource Aware Inference For Block RAM                           ; On                 ; On                 ;
+------------------------------------------------------------------+--------------------+--------------------+


+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+------+------------------------------------------+
; Name ; Setting                                  ;
+------+------------------------------------------+
;      ; 1                                        ;
;      ; 2                                        ;
;      ; 3                                        ;
;      ; 4                                        ;
;      ; v4                                       ;
;      ; 0                                        ;
;      ; 10                                       ;
;      ; 17                                       ;
;      ; 10M16SCU169C8G                           ;
;      ; 7                                        ;
;      ; 5                                        ;
;      ; 6                                        ;
;      ; 79872                                    ;
;      ; pokeymax                                 ;
;      ; 127M16HK                                 ;
+------+------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 8           ;
; Maximum allowed            ; 4           ;
;                            ;             ;
; Average used               ; 1.00        ;
; Maximum used               ; 4           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   0.1%      ;
;     Processor 3            ;   0.0%      ;
;     Processor 4            ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                                                                                                                                               ;
+-----------------------------------------------------------------------+-----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+
; File Name with User-Entered Path                                      ; Used in Netlist ; File Type                         ; File Name with Absolute Path                                                                                                                             ; Library     ;
+-----------------------------------------------------------------------+-----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+
; flash_controller.vhd                                                  ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash_controller.vhd                                                  ;             ;
; stereo_detect.vhd                                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/stereo_detect.vhd                                                     ;             ;
; iox_glue.vhdl                                                         ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/iox_glue.vhdl                                                         ;             ;
; i2c_master.vhd                                                        ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/i2c_master.vhd                                                        ;             ;
; slave_timing_6502.vhd                                                 ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/slave_timing_6502.vhd                                                 ;             ;
; complete_address_decoder.vhdl                                         ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/complete_address_decoder.vhdl                                         ;             ;
; syncreset_enable_divider.vhd                                          ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/syncreset_enable_divider.vhd                                          ;             ;
; delay_line.vhdl                                                       ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/delay_line.vhdl                                                       ;             ;
; wide_delay_line.vhdl                                                  ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/wide_delay_line.vhdl                                                  ;             ;
; latch_delay_line.vhdl                                                 ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/latch_delay_line.vhdl                                                 ;             ;
; sigmadelta_1storder.vhd                                               ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sigmadelta_1storder.vhd                                               ;             ;
; sigmadelta_2ndorder.vhd                                               ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sigmadelta_2ndorder.vhd                                               ;             ;
; filtered_sigmadelta.vhd                                               ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/filtered_sigmadelta.vhd                                               ;             ;
; generic_ram_infer.vhdl                                                ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/generic_ram_infer.vhdl                                                ;             ;
; simple_low_pass_filter.vhdl                                           ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/simple_low_pass_filter.vhdl                                           ;             ;
; pokey/pokey_poly_17_9.vhdl                                            ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_17_9.vhdl                                            ;             ;
; pokey/pokey_poly_5.vhdl                                               ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_5.vhdl                                               ;             ;
; pokey/pokey_poly_4.vhdl                                               ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_4.vhdl                                               ;             ;
; pokey/pokey_noise_filter.vhdl                                         ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_noise_filter.vhdl                                         ;             ;
; pokey/pokey_mixer_mux.vhdl                                            ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_mixer_mux.vhdl                                            ;             ;
; pokey/pokey_mixer.vhdl                                                ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_mixer.vhdl                                                ;             ;
; pokey/pokey_keyboard_scanner.vhdl                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_keyboard_scanner.vhdl                                     ;             ;
; pokey/pokey_countdown_timer.vhdl                                      ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_countdown_timer.vhdl                                      ;             ;
; pokey/pokey.vhdl                                                      ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl                                                      ;             ;
; synchronizer.vhdl                                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/synchronizer.vhdl                                                     ;             ;
; audiotypes.vhdl                                                       ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/audiotypes.vhdl                                                       ;             ;
; mixer.vhdl                                                            ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl                                                            ;             ;
; clockgen.vhd                                                          ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/clockgen.vhd                                                          ;             ;
; spdif_transmitter.vhdl                                                ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/spdif_transmitter.vhdl                                                ;             ;
; ps2_keyboard.vhdl                                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/ps2_keyboard.vhdl                                                     ;             ;
; ps2_to_atari800.vhdl                                                  ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/ps2_to_atari800.vhdl                                                  ;             ;
; pokeymax.vhd                                                          ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd                                                          ;             ;
; PSG/envelope.vhdl                                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/envelope.vhdl                                                     ;             ;
; PSG/noise.vhdl                                                        ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/noise.vhdl                                                        ;             ;
; PSG/top.vhdl                                                          ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/top.vhdl                                                          ;             ;
; PSG/freqdiv.vhdl                                                      ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/freqdiv.vhdl                                                      ;             ;
; PSG/mixer.vhdl                                                        ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/mixer.vhdl                                                        ;             ;
; PSG/volume.vhdl                                                       ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/volume.vhdl                                                       ;             ;
; PSG/volume_profile.vhdl                                               ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/volume_profile.vhdl                                               ;             ;
; SID/top.vhdl                                                          ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/top.vhdl                                                          ;             ;
; SID/oscillator.vhdl                                                   ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/oscillator.vhdl                                                   ;             ;
; SID/wavegen.vhdl                                                      ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/wavegen.vhdl                                                      ;             ;
; SID/envelope.vhdl                                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/envelope.vhdl                                                     ;             ;
; SID/envelope_tapmatch.vhdl                                            ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/envelope_tapmatch.vhdl                                            ;             ;
; SID/amplitudeModulator.vhdl                                           ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/amplitudeModulator.vhdl                                           ;             ;
; SID/preFilterSum.vhdl                                                 ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/preFilterSum.vhdl                                                 ;             ;
; SID/filter.vhdl                                                       ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/filter.vhdl                                                       ;             ;
; SID/f_distortion.vhdl                                                 ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/f_distortion.vhdl                                                 ;             ;
; SID/f_distortion_mux.vhdl                                             ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/f_distortion_mux.vhdl                                             ;             ;
; SID/postFilterSum.vhdl                                                ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/postFilterSum.vhdl                                                ;             ;
; sample/channel.vhdl                                                   ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/channel.vhdl                                                   ;             ;
; sample/adpcm.vhdl                                                     ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/adpcm.vhdl                                                     ;             ;
; sample/top.vhdl                                                       ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/top.vhdl                                                       ;             ;
; covox/top.vhdl                                                        ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/covox/top.vhdl                                                        ;             ;
; int_osc/synthesis/int_osc.vhd                                         ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/int_osc/synthesis/int_osc.vhd                                         ; int_osc     ;
; int_osc/synthesis/submodules/altera_int_osc.v                         ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/int_osc/synthesis/submodules/altera_int_osc.v                         ; int_osc     ;
; flash/synthesis/flash.vhd                                             ; yes             ; User VHDL File                    ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/flash.vhd                                             ; flash       ;
; flash/synthesis/submodules/altera_onchip_flash_util.v                 ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v                 ; flash       ;
; flash/synthesis/submodules/altera_onchip_flash.v                      ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash.v                      ; flash       ;
; flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v ; flash       ;
; flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v  ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v  ; flash       ;
; flash/synthesis/submodules/rtl/altera_onchip_flash_block.v            ; yes             ; Encrypted User Verilog HDL File   ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v            ; flash       ;
; lvds_tx.vhd                                                           ; yes             ; User Wizard-Generated File        ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_tx.vhd                                                           ; lvds_tx     ;
; lvds_tx/altera_soft_lvds_tx_twD5CSXW.v                                ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_tx/altera_soft_lvds_tx_twD5CSXW.v                                ; lvds_tx     ;
; lvds_rx.vhd                                                           ; yes             ; User Wizard-Generated File        ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_rx.vhd                                                           ; lvds_rx     ;
; lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v                                ; yes             ; User Verilog HDL File             ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v                                ; lvds_rx     ;
; paddle_gpio.vhd                                                       ; yes             ; User Wizard-Generated File        ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio.vhd                                                       ; paddle_gpio ;
; paddle_gpio/altera_gpio_lite.sv                                       ; yes             ; User SystemVerilog HDL File       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv                                       ; paddle_gpio ;
; altera_std_synchronizer.v                                             ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altera_std_synchronizer.v                                                                ;             ;
; lpm_shiftreg.tdf                                                      ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf                                                                         ;             ;
; lpm_constant.inc                                                      ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_constant.inc                                                                         ;             ;
; dffeea.inc                                                            ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/dffeea.inc                                                                               ;             ;
; aglobal201.inc                                                        ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/aglobal201.inc                                                                           ;             ;
; pllv3.vhd                                                             ; yes             ; Auto-Found Wizard-Generated File  ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pllv3.vhd                                                             ;             ;
; altpll.tdf                                                            ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altpll.tdf                                                                               ;             ;
; stratix_pll.inc                                                       ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/stratix_pll.inc                                                                          ;             ;
; stratixii_pll.inc                                                     ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/stratixii_pll.inc                                                                        ;             ;
; cycloneii_pll.inc                                                     ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/cycloneii_pll.inc                                                                        ;             ;
; db/pllv3_altpll.v                                                     ; yes             ; Auto-Generated Megafunction       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/pllv3_altpll.v                                                     ;             ;
; altshift_taps.tdf                                                     ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altshift_taps.tdf                                                                        ;             ;
; altdpram.inc                                                          ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altdpram.inc                                                                             ;             ;
; lpm_counter.inc                                                       ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_counter.inc                                                                          ;             ;
; lpm_compare.inc                                                       ; yes             ; Megafunction                      ; /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/lpm_compare.inc                                                                          ;             ;
; db/shift_taps_n0m.tdf                                                 ; yes             ; Auto-Generated Megafunction       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/shift_taps_n0m.tdf                                                 ;             ;
; db/altsyncram_4ga1.tdf                                                ; yes             ; Auto-Generated Megafunction       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/altsyncram_4ga1.tdf                                                ;             ;
; db/cntr_97f.tdf                                                       ; yes             ; Auto-Generated Megafunction       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/cntr_97f.tdf                                                       ;             ;
; db/cmpr_krb.tdf                                                       ; yes             ; Auto-Generated Megafunction       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/cmpr_krb.tdf                                                       ;             ;
; db/cntr_vmg.tdf                                                       ; yes             ; Auto-Generated Megafunction       ; /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/cntr_vmg.tdf                                                       ;             ;
+-----------------------------------------------------------------------+-----------------+-----------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary                                                                                                    ;
+---------------------------------------------+--------------------------------------------------------------------------------------------------+
; Resource                                    ; Usage                                                                                            ;
+---------------------------------------------+--------------------------------------------------------------------------------------------------+
; Estimated Total logic elements              ; 2,448                                                                                            ;
;                                             ;                                                                                                  ;
; Total combinational functions               ; 1924                                                                                             ;
; Logic element usage by number of LUT inputs ;                                                                                                  ;
;     -- 4 input functions                    ; 745                                                                                              ;
;     -- 3 input functions                    ; 736                                                                                              ;
;     -- <=2 input functions                  ; 443                                                                                              ;
;                                             ;                                                                                                  ;
; Logic elements by mode                      ;                                                                                                  ;
;     -- normal mode                          ; 1395                                                                                             ;
;     -- arithmetic mode                      ; 529                                                                                              ;
;                                             ;                                                                                                  ;
; Total registers                             ; 1451                                                                                             ;
;     -- Dedicated logic registers            ; 1451                                                                                             ;
;     -- I/O registers                        ; 0                                                                                                ;
;                                             ;                                                                                                  ;
; I/O pins                                    ; 70                                                                                               ;
; Total memory bits                           ; 253                                                                                              ;
; UFM blocks                                  ; 1                                                                                                ;
;                                             ;                                                                                                  ;
; Embedded Multiplier 9-bit elements          ; 0                                                                                                ;
;                                             ;                                                                                                  ;
; Total PLLs                                  ; 1                                                                                                ;
;     -- PLLs                                 ; 1                                                                                                ;
;                                             ;                                                                                                  ;
; Maximum fan-out node                        ; pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated|wire_pll1_clk[0] ;
; Maximum fan-out                             ; 1456                                                                                             ;
; Total fan-out                               ; 10416                                                                                            ;
; Average fan-out                             ; 2.93                                                                                             ;
+---------------------------------------------+--------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                              ;
+---------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+--------------+
; Compilation Hierarchy Node                                                                                    ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; UFM Blocks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; ADC blocks ; Full Hierarchy Name                                                                                                                                                                                                                                                   ; Entity Name                                          ; Library Name ;
+---------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+--------------+
; |pokeymax                                                                                                     ; 1924 (240)          ; 1451 (133)                ; 253         ; 1          ; 0            ; 0       ; 0         ; 70   ; 0            ; 0          ; |pokeymax                                                                                                                                                                                                                                                             ; pokeymax                                             ; work         ;
;    |altshift_taps:toggle_reg_rtl_0|                                                                           ; 28 (0)              ; 17 (0)                    ; 253         ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|altshift_taps:toggle_reg_rtl_0                                                                                                                                                                                                                              ; altshift_taps                                        ; work         ;
;       |shift_taps_n0m:auto_generated|                                                                         ; 28 (0)              ; 17 (1)                    ; 253         ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated                                                                                                                                                                                                ; shift_taps_n0m                                       ; work         ;
;          |altsyncram_4ga1:altsyncram2|                                                                        ; 0 (0)               ; 0 (0)                     ; 253         ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|altsyncram_4ga1:altsyncram2                                                                                                                                                                    ; altsyncram_4ga1                                      ; work         ;
;          |cntr_97f:cntr1|                                                                                     ; 19 (17)             ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|cntr_97f:cntr1                                                                                                                                                                                 ; cntr_97f                                             ; work         ;
;             |cmpr_krb:cmpr6|                                                                                  ; 2 (2)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|cntr_97f:cntr1|cmpr_krb:cmpr6                                                                                                                                                                  ; cmpr_krb                                             ; work         ;
;          |cntr_vmg:cntr3|                                                                                     ; 9 (9)               ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|cntr_vmg:cntr3                                                                                                                                                                                 ; cntr_vmg                                             ; work         ;
;    |complete_address_decoder:\gen_config:decode_addr1|                                                        ; 2 (2)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|complete_address_decoder:\gen_config:decode_addr1                                                                                                                                                                                                           ; complete_address_decoder                             ; work         ;
;    |filtered_sigmadelta:dac_0|                                                                                ; 76 (0)              ; 43 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|filtered_sigmadelta:dac_0                                                                                                                                                                                                                                   ; filtered_sigmadelta                                  ; work         ;
;       |sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|                                                          ; 76 (76)             ; 43 (43)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd                                                                                                                                                                                      ; sigmadelta_2ndorder                                  ; work         ;
;    |filtered_sigmadelta:dac_2|                                                                                ; 76 (0)              ; 43 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|filtered_sigmadelta:dac_2                                                                                                                                                                                                                                   ; filtered_sigmadelta                                  ; work         ;
;       |sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|                                                          ; 76 (76)             ; 43 (43)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|filtered_sigmadelta:dac_2|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd                                                                                                                                                                                      ; sigmadelta_2ndorder                                  ; work         ;
;    |filtered_sigmadelta:dac_3|                                                                                ; 76 (0)              ; 43 (0)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|filtered_sigmadelta:dac_3                                                                                                                                                                                                                                   ; filtered_sigmadelta                                  ; work         ;
;       |sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|                                                          ; 76 (76)             ; 43 (43)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|filtered_sigmadelta:dac_3|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd                                                                                                                                                                                      ; sigmadelta_2ndorder                                  ; work         ;
;    |flash_controller:\flash_on:flash_controller_inst|                                                         ; 631 (144)           ; 400 (136)                 ; 0           ; 1          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst                                                                                                                                                                                                            ; flash_controller                                     ; work         ;
;       |flash:flash1|                                                                                          ; 487 (0)             ; 264 (0)                   ; 0           ; 1          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1                                                                                                                                                                                               ; flash                                                ; flash        ;
;          |altera_onchip_flash:onchip_flash_0|                                                                 ; 487 (0)             ; 264 (0)                   ; 0           ; 1          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0                                                                                                                                                            ; altera_onchip_flash                                  ; flash        ;
;             |altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|                                     ; 44 (44)             ; 33 (33)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller                                                                                                ; altera_onchip_flash_avmm_csr_controller              ; flash        ;
;             |altera_onchip_flash_avmm_data_controller:avmm_data_controller|                                   ; 443 (370)           ; 231 (195)                 ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller                                                                                              ; altera_onchip_flash_avmm_data_controller             ; flash        ;
;                |altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker| ; 18 (18)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker ; altera_onchip_flash_a_address_write_protection_check ; flash        ;
;                |altera_onchip_flash_convert_address:address_convertor|                                        ; 23 (23)             ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor                                        ; altera_onchip_flash_convert_address                  ; flash        ;
;                |altera_std_synchronizer:stdsync_busy_clear|                                                   ; 0 (0)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear                                                   ; altera_std_synchronizer                              ; work         ;
;                |altera_std_synchronizer:stdsync_busy|                                                         ; 0 (0)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy                                                         ; altera_std_synchronizer                              ; work         ;
;                |lpm_shiftreg:ufm_data_shiftreg|                                                               ; 32 (32)             ; 32 (32)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg                                                               ; lpm_shiftreg                                         ; work         ;
;             |altera_onchip_flash_block:altera_onchip_flash_block|                                             ; 0 (0)               ; 0 (0)                     ; 0           ; 1          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block                                                                                                        ; altera_onchip_flash_block                            ; flash        ;
;    |int_osc:oscillator|                                                                                       ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|int_osc:oscillator                                                                                                                                                                                                                                          ; int_osc                                              ; int_osc      ;
;       |altera_int_osc:int_osc_0|                                                                              ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|int_osc:oscillator|altera_int_osc:int_osc_0                                                                                                                                                                                                                 ; altera_int_osc                                       ; int_osc      ;
;    |lvds_rx:\adc_on:lvds_rx0|                                                                                 ; 0 (0)               ; 1 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|lvds_rx:\adc_on:lvds_rx0                                                                                                                                                                                                                                    ; lvds_rx                                              ; lvds_rx      ;
;       |altera_soft_lvds_rx_twD2Tqf3:lvds_rx_inst|                                                             ; 0 (0)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|lvds_rx:\adc_on:lvds_rx0|altera_soft_lvds_rx_twD2Tqf3:lvds_rx_inst                                                                                                                                                                                          ; altera_soft_lvds_rx_twD2Tqf3                         ; lvds_rx      ;
;    |mixer:mixer1|                                                                                             ; 181 (181)           ; 98 (98)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|mixer:mixer1                                                                                                                                                                                                                                                ; mixer                                                ; work         ;
;    |paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|                                                              ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0                                                                                                                                                                                                                 ; paddle_gpio                                          ; paddle_gpio  ;
;       |altera_gpio_lite:paddle_gpio_inst|                                                                     ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst                                                                                                                                                                               ; altera_gpio_lite                                     ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;          |altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i|                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i                                                                                                                          ; altgpio_one_bit                                      ; paddle_gpio  ;
;    |pllv3:\pll_v3_inst:pll_inst|                                                                              ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pllv3:\pll_v3_inst:pll_inst                                                                                                                                                                                                                                 ; pllv3                                                ; work         ;
;       |altpll:altpll_component|                                                                               ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component                                                                                                                                                                                                         ; altpll                                               ; work         ;
;          |pllv3_altpll:auto_generated|                                                                        ; 0 (0)               ; 0 (0)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated                                                                                                                                                                             ; pllv3_altpll                                         ; work         ;
;    |pokey:pokey1|                                                                                             ; 400 (227)           ; 448 (269)                 ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1                                                                                                                                                                                                                                                ; pokey                                                ; work         ;
;       |delay_line:serin_clock_delay|                                                                          ; 7 (7)               ; 5 (5)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|delay_line:serin_clock_delay                                                                                                                                                                                                                   ; delay_line                                           ; work         ;
;       |delay_line:serout_clock_delay|                                                                         ; 6 (6)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|delay_line:serout_clock_delay                                                                                                                                                                                                                  ; delay_line                                           ; work         ;
;       |latch_delay_line:stimer_delay|                                                                         ; 2 (2)               ; 4 (4)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|latch_delay_line:stimer_delay                                                                                                                                                                                                                  ; latch_delay_line                                     ; work         ;
;       |latch_delay_line:twotone_del|                                                                          ; 0 (0)               ; 2 (2)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|latch_delay_line:twotone_del                                                                                                                                                                                                                   ; latch_delay_line                                     ; work         ;
;       |pokey_countdown_timer:timer0|                                                                          ; 14 (9)              ; 11 (8)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0                                                                                                                                                                                                                   ; pokey_countdown_timer                                ; work         ;
;          |delay_line:underflow0_delay|                                                                        ; 5 (5)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay                                                                                                                                                                                       ; delay_line                                           ; work         ;
;       |pokey_countdown_timer:timer1|                                                                          ; 14 (9)              ; 11 (8)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1                                                                                                                                                                                                                   ; pokey_countdown_timer                                ; work         ;
;          |delay_line:underflow0_delay|                                                                        ; 5 (5)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay                                                                                                                                                                                       ; delay_line                                           ; work         ;
;       |pokey_countdown_timer:timer2|                                                                          ; 14 (9)              ; 11 (8)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2                                                                                                                                                                                                                   ; pokey_countdown_timer                                ; work         ;
;          |delay_line:underflow0_delay|                                                                        ; 5 (5)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay                                                                                                                                                                                       ; delay_line                                           ; work         ;
;       |pokey_countdown_timer:timer3|                                                                          ; 16 (9)              ; 11 (8)                    ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3                                                                                                                                                                                                                   ; pokey_countdown_timer                                ; work         ;
;          |delay_line:underflow0_delay|                                                                        ; 7 (7)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay                                                                                                                                                                                       ; delay_line                                           ; work         ;
;       |pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|                                       ; 38 (38)             ; 28 (28)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1                                                                                                                                                                                ; pokey_keyboard_scanner                               ; work         ;
;       |pokey_noise_filter:pokey_noise_filter0|                                                                ; 4 (4)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter0                                                                                                                                                                                                         ; pokey_noise_filter                                   ; work         ;
;       |pokey_noise_filter:pokey_noise_filter1|                                                                ; 4 (4)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter1                                                                                                                                                                                                         ; pokey_noise_filter                                   ; work         ;
;       |pokey_noise_filter:pokey_noise_filter2|                                                                ; 4 (4)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter2                                                                                                                                                                                                         ; pokey_noise_filter                                   ; work         ;
;       |pokey_noise_filter:pokey_noise_filter3|                                                                ; 4 (4)               ; 1 (1)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_noise_filter:pokey_noise_filter3                                                                                                                                                                                                         ; pokey_noise_filter                                   ; work         ;
;       |pokey_poly_17_9:poly_17_19_lfsr|                                                                       ; 18 (18)             ; 18 (18)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr                                                                                                                                                                                                                ; pokey_poly_17_9                                      ; work         ;
;       |pokey_poly_4:poly_4_lfsr|                                                                              ; 4 (4)               ; 4 (4)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_poly_4:poly_4_lfsr                                                                                                                                                                                                                       ; pokey_poly_4                                         ; work         ;
;       |pokey_poly_5:poly_5_lfsr|                                                                              ; 5 (5)               ; 5 (5)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|pokey_poly_5:poly_5_lfsr                                                                                                                                                                                                                       ; pokey_poly_5                                         ; work         ;
;       |synchronizer:sio_clk1_synchronizer|                                                                    ; 0 (0)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|synchronizer:sio_clk1_synchronizer                                                                                                                                                                                                             ; synchronizer                                         ; work         ;
;       |synchronizer:sio_in1_synchronizer|                                                                     ; 0 (0)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|synchronizer:sio_in1_synchronizer                                                                                                                                                                                                              ; synchronizer                                         ; work         ;
;       |synchronizer:sio_in2_synchronizer|                                                                     ; 0 (0)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|synchronizer:sio_in2_synchronizer                                                                                                                                                                                                              ; synchronizer                                         ; work         ;
;       |syncreset_enable_divider:enable_15_div|                                                                ; 11 (11)             ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_15_div                                                                                                                                                                                                         ; syncreset_enable_divider                             ; work         ;
;       |syncreset_enable_divider:enable_64_div|                                                                ; 8 (8)               ; 6 (6)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_64_div                                                                                                                                                                                                         ; syncreset_enable_divider                             ; work         ;
;       |wide_delay_line:audctl_delay|                                                                          ; 0 (0)               ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|wide_delay_line:audctl_delay                                                                                                                                                                                                                   ; wide_delay_line                                      ; work         ;
;       |wide_delay_line:audf0_delay|                                                                           ; 0 (0)               ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|wide_delay_line:audf0_delay                                                                                                                                                                                                                    ; wide_delay_line                                      ; work         ;
;       |wide_delay_line:audf1_delay|                                                                           ; 0 (0)               ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|wide_delay_line:audf1_delay                                                                                                                                                                                                                    ; wide_delay_line                                      ; work         ;
;       |wide_delay_line:audf2_delay|                                                                           ; 0 (0)               ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|wide_delay_line:audf2_delay                                                                                                                                                                                                                    ; wide_delay_line                                      ; work         ;
;       |wide_delay_line:audf3_delay|                                                                           ; 0 (0)               ; 8 (8)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey:pokey1|wide_delay_line:audf3_delay                                                                                                                                                                                                                    ; wide_delay_line                                      ; work         ;
;    |pokey_mixer_mux:pokey_mixer_both|                                                                         ; 34 (34)             ; 89 (89)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|pokey_mixer_mux:pokey_mixer_both                                                                                                                                                                                                                            ; pokey_mixer_mux                                      ; work         ;
;    |simple_low_pass_filter:\adc_on:adcfilter2|                                                                ; 83 (83)             ; 42 (42)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|simple_low_pass_filter:\adc_on:adcfilter2                                                                                                                                                                                                                   ; simple_low_pass_filter                               ; work         ;
;    |simple_low_pass_filter:\adc_on:adcfilter|                                                                 ; 83 (83)             ; 42 (42)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|simple_low_pass_filter:\adc_on:adcfilter                                                                                                                                                                                                                    ; simple_low_pass_filter                               ; work         ;
;    |slave_timing_6502:bus_adapt|                                                                              ; 10 (10)             ; 43 (40)                   ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|slave_timing_6502:bus_adapt                                                                                                                                                                                                                                 ; slave_timing_6502                                    ; work         ;
;       |synchronizer:synchronizer_phi|                                                                         ; 0 (0)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|slave_timing_6502:bus_adapt|synchronizer:synchronizer_phi                                                                                                                                                                                                   ; synchronizer                                         ; work         ;
;    |stereo_detect:\auto_stereo:a4|                                                                            ; 4 (4)               ; 6 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|stereo_detect:\auto_stereo:a4                                                                                                                                                                                                                               ; stereo_detect                                        ; work         ;
;       |synchronizer:synchronizer_4|                                                                           ; 0 (0)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|stereo_detect:\auto_stereo:a4|synchronizer:synchronizer_4                                                                                                                                                                                                   ; synchronizer                                         ; work         ;
;    |synchronizer:synchronizer_gtia_audio|                                                                     ; 0 (0)               ; 3 (3)                     ; 0           ; 0          ; 0            ; 0       ; 0         ; 0    ; 0            ; 0          ; |pokeymax|synchronizer:synchronizer_gtia_audio                                                                                                                                                                                                                        ; synchronizer                                         ; work         ;
+---------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+------------+--------------+---------+-----------+------+--------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                        ;
+-----------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; Name                                                                                                ; Type ; Mode             ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF  ;
+-----------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+
; altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|altsyncram_4ga1:altsyncram2|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 253          ; 1            ; 253          ; 1            ; 253  ; None ;
+-----------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis IP Cores Summary                                                                                                                                                                                                                   ;
+--------+---------------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; Vendor ; IP Core Name        ; Version ; Release Date ; License Type ; Entity Instance                                                                                                                                                ; IP Include File ;
+--------+---------------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
; Altera ; altera_soft_lvds    ; 20.1    ; N/A          ; N/A          ; |pokeymax|lvds_rx:\adc_on:lvds_rx0                                                                                                                             ; lvds_rx.vhd     ;
; Altera ; altera_soft_lvds    ; 20.1    ; N/A          ; N/A          ; |pokeymax|lvds_tx:\adc_on:lvds_tx0                                                                                                                             ; lvds_tx.vhd     ;
; N/A    ; altera_onchip_flash ; 19.1    ; N/A          ; N/A          ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1                                                                                        ; flash.qsys      ;
; Altera ; 6AF7_FFFF           ; N/A     ; N/A          ; Licensed     ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block ;                 ;
; Altera ; altera_gpio_lite    ; 20.1    ; N/A          ; N/A          ; |pokeymax|paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0                                                                                                          ; paddle_gpio.vhd ;
; N/A    ; altera_int_osc      ; 20.1    ; N/A          ; N/A          ; |pokeymax|int_osc:oscillator                                                                                                                                   ; int_osc.qsys    ;
+--------+---------------------+---------+--------------+--------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+


Encoding Type:  One-Hot
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state ;
+----------------------------------------------+---------------------------------------+----------------------------------------------+--------------------------------------------------------------------------+
; Name                                         ; avmm_read_valid_state.READ_VALID_IDLE ; avmm_read_valid_state.READ_VALID_PRE_READING ; avmm_read_valid_state.READ_VALID_READING                                 ;
+----------------------------------------------+---------------------------------------+----------------------------------------------+--------------------------------------------------------------------------+
; avmm_read_valid_state.READ_VALID_IDLE        ; 0                                     ; 0                                            ; 0                                                                        ;
; avmm_read_valid_state.READ_VALID_READING     ; 1                                     ; 0                                            ; 1                                                                        ;
; avmm_read_valid_state.READ_VALID_PRE_READING ; 1                                     ; 1                                            ; 0                                                                        ;
+----------------------------------------------+---------------------------------------+----------------------------------------------+--------------------------------------------------------------------------+


Encoding Type:  One-Hot
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state                                                                             ;
+--------------------------------+--------------------------------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+
; Name                           ; read_state.READ_STATE_PULSE_SE ; read_state.READ_STATE_CLEAR ; read_state.READ_STATE_FINAL ; read_state.READ_STATE_READY ; read_state.READ_STATE_DUMMY ; read_state.READ_STATE_SETUP ; read_state.READ_STATE_ADDR ; read_state.READ_STATE_IDLE ;
+--------------------------------+--------------------------------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+
; read_state.READ_STATE_IDLE     ; 0                              ; 0                           ; 0                           ; 0                           ; 0                           ; 0                           ; 0                          ; 0                          ;
; read_state.READ_STATE_ADDR     ; 0                              ; 0                           ; 0                           ; 0                           ; 0                           ; 0                           ; 1                          ; 1                          ;
; read_state.READ_STATE_SETUP    ; 0                              ; 0                           ; 0                           ; 0                           ; 0                           ; 1                           ; 0                          ; 1                          ;
; read_state.READ_STATE_DUMMY    ; 0                              ; 0                           ; 0                           ; 0                           ; 1                           ; 0                           ; 0                          ; 1                          ;
; read_state.READ_STATE_READY    ; 0                              ; 0                           ; 0                           ; 1                           ; 0                           ; 0                           ; 0                          ; 1                          ;
; read_state.READ_STATE_FINAL    ; 0                              ; 0                           ; 1                           ; 0                           ; 0                           ; 0                           ; 0                          ; 1                          ;
; read_state.READ_STATE_CLEAR    ; 0                              ; 1                           ; 0                           ; 0                           ; 0                           ; 0                           ; 0                          ; 1                          ;
; read_state.READ_STATE_PULSE_SE ; 1                              ; 0                           ; 0                           ; 0                           ; 0                           ; 0                           ; 0                          ; 1                          ;
+--------------------------------+--------------------------------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+


Encoding Type:  One-Hot
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state                                    ;
+-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+------------------------------+------------------------------+
; Name                              ; erase_state.ERASE_STATE_ERROR ; erase_state.ERASE_STATE_RESET ; erase_state.ERASE_STATE_WAIT_DONE ; erase_state.ERASE_STATE_WAIT_BUSY ; erase_state.ERASE_STATE_ADDR ; erase_state.ERASE_STATE_IDLE ;
+-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+------------------------------+------------------------------+
; erase_state.ERASE_STATE_IDLE      ; 0                             ; 0                             ; 0                                 ; 0                                 ; 0                            ; 0                            ;
; erase_state.ERASE_STATE_ADDR      ; 0                             ; 0                             ; 0                                 ; 0                                 ; 1                            ; 1                            ;
; erase_state.ERASE_STATE_WAIT_BUSY ; 0                             ; 0                             ; 0                                 ; 1                                 ; 0                            ; 1                            ;
; erase_state.ERASE_STATE_WAIT_DONE ; 0                             ; 0                             ; 1                                 ; 0                                 ; 0                            ; 1                            ;
; erase_state.ERASE_STATE_RESET     ; 0                             ; 1                             ; 0                                 ; 0                                 ; 0                            ; 1                            ;
; erase_state.ERASE_STATE_ERROR     ; 1                             ; 0                             ; 0                                 ; 0                                 ; 0                            ; 1                            ;
+-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+------------------------------+------------------------------+


Encoding Type:  One-Hot
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; State Machine - |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state                                                                    ;
+-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+-------------------------------+------------------------------+------------------------------+
; Name                              ; write_state.WRITE_STATE_ERROR ; write_state.WRITE_STATE_RESET ; write_state.WRITE_STATE_WAIT_DONE ; write_state.WRITE_STATE_WAIT_BUSY ; write_state.WRITE_STATE_WRITE ; write_state.WRITE_STATE_ADDR ; write_state.WRITE_STATE_IDLE ;
+-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+-------------------------------+------------------------------+------------------------------+
; write_state.WRITE_STATE_IDLE      ; 0                             ; 0                             ; 0                                 ; 0                                 ; 0                             ; 0                            ; 0                            ;
; write_state.WRITE_STATE_ADDR      ; 0                             ; 0                             ; 0                                 ; 0                                 ; 0                             ; 1                            ; 1                            ;
; write_state.WRITE_STATE_WRITE     ; 0                             ; 0                             ; 0                                 ; 0                                 ; 1                             ; 0                            ; 1                            ;
; write_state.WRITE_STATE_WAIT_BUSY ; 0                             ; 0                             ; 0                                 ; 1                                 ; 0                             ; 0                            ; 1                            ;
; write_state.WRITE_STATE_WAIT_DONE ; 0                             ; 0                             ; 1                                 ; 0                                 ; 0                             ; 0                            ; 1                            ;
; write_state.WRITE_STATE_RESET     ; 0                             ; 1                             ; 0                                 ; 0                                 ; 0                             ; 0                            ; 1                            ;
; write_state.WRITE_STATE_ERROR     ; 1                             ; 0                             ; 0                                 ; 0                                 ; 0                             ; 0                            ; 1                            ;
+-----------------------------------+-------------------------------+-------------------------------+-----------------------------------+-----------------------------------+-------------------------------+------------------------------+------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Protected by Synthesis                                                                                                                                                                                                                                                                                                  ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; Register Name                                                                                                                                                                                                     ; Protected by Synthesis Attribute or Preserve Register Assignment ; Not to be Touched by Netlist Optimizations ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear|dreg[0] ; yes                                                              ; yes                                        ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy|dreg[0]       ; yes                                                              ; yes                                        ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear|din_s1  ; yes                                                              ; yes                                        ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy|din_s1        ; yes                                                              ; yes                                        ;
; Total number of protected registers is 4                                                                                                                                                                          ;                                                                  ;                                            ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------+--------------------------------------------+


+------------------------------------------------------------------------+
; Logic Cells Representing Combinational Loops                           ;
+--------------------------------------------------------------------+---+
; Logic Cell Name                                                    ;   ;
+--------------------------------------------------------------------+---+
; flash_controller:\flash_on:flash_controller_inst|flash_data_read~0 ;   ;
; Number of logic cells representing combinational loops             ; 1 ;
+--------------------------------------------------------------------+---+
Note: All cells listed above may not be present at the end of synthesis due to various synthesis optimizations.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Registers Removed During Synthesis                                                                                                                                                                                                                                                                                                                                                  ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Register name                                                                                                                                                                               ; Reason for Removal                                                                                                                                                                    ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; synchronizer:synchronizer_fancy_enable|ff_reg[2]                                                                                                                                            ; Stuck at VCC due to stuck port data_in                                                                                                                                                ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|is_sector5_writable_reg      ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; synchronizer:synchronizer_fancy_enable|ff_reg[0,1]                                                                                                                                          ; Stuck at VCC due to stuck port data_in                                                                                                                                                ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_burstcount_input_reg[1] ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; CHANNEL3SUM_REG[4,5]                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_3_REG[4,5]                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; CHANNEL1SUM_REG[4,5]                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; CHANNEL2SUM_REG[4,5]                                                                                                                                                                        ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_1_REG[4,5]                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_IN_2_REG[4,5]                                                                                                                                      ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_page_addr[21,22]       ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|cycle_delay_reg                                                                                                                                ; Merged with pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[8]                                                                                                                 ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|reset_n_reg2                 ; Merged with flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|reset_n_reg2 ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|reset_n_reg1                 ; Merged with flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|reset_n_reg1 ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state~7                 ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state~8                 ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_state~9                 ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state~6                ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state~7                ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state~8                ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state~5                ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state~6                ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state~7                ; Lost fanout                                                                                                                                                                           ;
; filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|ttl1_reg[21]                                                                                                         ; Lost fanout                                                                                                                                                                           ;
; filtered_sigmadelta:dac_2|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|ttl1_reg[21]                                                                                                         ; Lost fanout                                                                                                                                                                           ;
; filtered_sigmadelta:dac_3|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd|ttl1_reg[21]                                                                                                         ; Lost fanout                                                                                                                                                                           ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|read_ctrl_count[2]           ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; pokey:pokey1|latch_delay_line:twotone_del|data_in_reg                                                                                                                                       ; Stuck at GND due to stuck port data_in                                                                                                                                                ;
; Total Number of Removed Registers = 36                                                                                                                                                      ;                                                                                                                                                                                       ;
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------+
; Removed Registers Triggering Further Register Optimizations                                                                      ;
+--------------------------------------------------+---------------------------+---------------------------------------------------+
; Register name                                    ; Reason for Removal        ; Registers Removed due to This Register            ;
+--------------------------------------------------+---------------------------+---------------------------------------------------+
; synchronizer:synchronizer_fancy_enable|ff_reg[2] ; Stuck at VCC              ; synchronizer:synchronizer_fancy_enable|ff_reg[1], ;
;                                                  ; due to stuck port data_in ; synchronizer:synchronizer_fancy_enable|ff_reg[0]  ;
+--------------------------------------------------+---------------------------+---------------------------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 1451  ;
; Number of registers using Synchronous Clear  ; 117   ;
; Number of registers using Synchronous Load   ; 112   ;
; Number of registers using Asynchronous Clear ; 1094  ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 937   ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Inverted Register Statistics                                                                                                                                                                              ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Inverted Register                                                                                                                                                                               ; Fan out ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; CHANNEL_EN_REG[0]                                                                                                                                                                               ; 2       ;
; CHANNEL_EN_REG[2]                                                                                                                                                                               ; 2       ;
; CHANNEL_EN_REG[3]                                                                                                                                                                               ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_drshft_neg_reg             ; 1       ;
; pokey:pokey1|sio_out_reg                                                                                                                                                                        ; 1       ;
; slave_timing_6502:bus_adapt|state_reg[0]                                                                                                                                                        ; 6       ;
; slave_timing_6502:bus_adapt|phi_rw_n_reg                                                                                                                                                        ; 3       ;
; slave_timing_6502:bus_adapt|phi_edge_prev_reg                                                                                                                                                   ; 4       ;
; RESTRICT_CAPABILITY_REG[2]                                                                                                                                                                      ; 2       ;
; RESTRICT_CAPABILITY_REG[1]                                                                                                                                                                      ; 3       ;
; RESTRICT_CAPABILITY_REG[0]                                                                                                                                                                      ; 2       ;
; RESTRICT_CAPABILITY_REG[4]                                                                                                                                                                      ; 2       ;
; RESTRICT_CAPABILITY_REG[3]                                                                                                                                                                      ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_drshft_reg                 ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[20] ; 6       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[21] ; 7       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[22] ; 7       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[12] ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[13] ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[14] ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[15] ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[17] ; 5       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[18] ; 8       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[19] ; 8       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[16] ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[11] ; 2       ;
; pokey:pokey1|serial_out_reg                                                                                                                                                                     ; 3       ;
; slave_timing_6502:bus_adapt|phi_cs_reg                                                                                                                                                          ; 1       ;
; stereo_detect:\auto_stereo:a4|addr_bit_sync_reg                                                                                                                                                 ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[1]                     ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[3]                     ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[4]                     ; 1       ;
; pokey:pokey1|irq_n_reg                                                                                                                                                                          ; 1       ;
; pokey:pokey1|pot_reset_reg                                                                                                                                                                      ; 34      ;
; flash_controller:\flash_on:flash_controller_inst|robin_reg[7]                                                                                                                                   ; 4       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[2]                     ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[0]                     ; 2       ;
; CPU_FLASH_WRITE_N_REG                                                                                                                                                                           ; 3       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[0]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[1]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[2]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[3]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[4]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[5]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[6]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[7]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[8]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[9]  ; 2       ;
; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[10] ; 2       ;
; POST_DIVIDE_REG[5]                                                                                                                                                                              ; 2       ;
; POST_DIVIDE_REG[7]                                                                                                                                                                              ; 2       ;
; GTIA_ENABLE_REG[2]                                                                                                                                                                              ; 3       ;
; DETECT_RIGHT_REG                                                                                                                                                                                ; 2       ;
; GTIA_ENABLE_REG[3]                                                                                                                                                                              ; 2       ;
; pokey:pokey1|irqst_reg[3]                                                                                                                                                                       ; 2       ;
; pokey:pokey1|irqst_reg[7]                                                                                                                                                                       ; 3       ;
; pokey:pokey1|irqst_reg[6]                                                                                                                                                                       ; 4       ;
; pokey:pokey1|irqst_reg[5]                                                                                                                                                                       ; 4       ;
; pokey:pokey1|irqst_reg[4]                                                                                                                                                                       ; 3       ;
; pokey:pokey1|irqst_reg[2]                                                                                                                                                                       ; 3       ;
; pokey:pokey1|irqst_reg[1]                                                                                                                                                                       ; 3       ;
; pokey:pokey1|irqst_reg[0]                                                                                                                                                                       ; 3       ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[2]                                                                                                                                           ; 3       ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[1]                                                                                                                                           ; 4       ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[0]                                                                                                                                           ; 3       ;
; pokey_mixer_mux:pokey_mixer_both|CHANNEL_DIRTY_REG[3]                                                                                                                                           ; 4       ;
; SATURATE_REG                                                                                                                                                                                    ; 2       ;
; pokey:pokey1|allpot_reg[0]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0]                                                                                               ; 1       ;
; CHANNEL_EN_REG[1]                                                                                                                                                                               ; 1       ;
; SID_FILTER1_REG[1]                                                                                                                                                                              ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]                                                                                                                                       ; 2       ;
; pokey:pokey1|allpot_reg[1]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[1]                                                                                               ; 1       ;
; PSG_STEREOMODE_REG[0]                                                                                                                                                                           ; 1       ;
; pokey:pokey1|allpot_reg[2]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[2]                                                                                               ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                                                                                                                                      ; 2       ;
; pokey:pokey1|allpot_reg[3]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[3]                                                                                               ; 1       ;
; CHANNEL_EN_REG[4]                                                                                                                                                                               ; 1       ;
; pokey:pokey1|allpot_reg[4]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[4]                                                                                               ; 1       ;
; SID_FILTER2_REG[1]                                                                                                                                                                              ; 1       ;
; PAL_REG                                                                                                                                                                                         ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[13]                                                                                                                                      ; 3       ;
; pokey:pokey1|allpot_reg[5]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[5]                                                                                               ; 1       ;
; pokey:pokey1|allpot_reg[6]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[6]                                                                                               ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[15]                                                                                                                                      ; 2       ;
; pokey:pokey1|allpot_reg[7]                                                                                                                                                                      ; 2       ;
; pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[7]                                                                                               ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[1]                                                                                                                                       ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[3]                                                                                                                                       ; 1       ;
; pokey:pokey1|pokey_poly_4:poly_4_lfsr|shift_reg[1]                                                                                                                                              ; 2       ;
; pokey:pokey1|pokey_poly_5:poly_5_lfsr|shift_reg[1]                                                                                                                                              ; 1       ;
; altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|dffe4                                                                                                                              ; 1       ;
; pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[5]                                                                                                                                       ; 1       ;
; pokey:pokey1|pokey_poly_4:poly_4_lfsr|shift_reg[3]                                                                                                                                              ; 1       ;
; Total number of inverted registers = 102*                                                                                                                                                       ;         ;
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
* Table truncated at 100 items. To change the number of inverted registers reported, set the "Number of Inverted Registers Reported" option under Assignments->Settings->Analysis and Synthesis Settings->More Settings


+----------------------------------------------------+
; Registers Packed Into Inferred Megafunctions       ;
+--------------------+------------------+------------+
; Register Name      ; Megafunction     ; Type       ;
+--------------------+------------------+------------+
; toggle_reg[1..255] ; toggle_reg_rtl_0 ; SHIFT_TAPS ;
+--------------------+------------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                                                ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_page_addr[9]               ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_addr_wire_neg_reg[21]      ;
; 3:1                ; 20 bits   ; 40 LEs        ; 20 LEs               ; 20 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_addr_wire_neg_reg[14]      ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                                                                                                                                         ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2]                                                                                                              ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[2]                                                                                                              ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                                                                                                              ;
; 3:1                ; 3 bits    ; 6 LEs         ; 3 LEs                ; 3 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1]                                                                                                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |pokeymax|PSG_PROFILESEL_REG[0]                                                                                                                                                                           ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |pokeymax|GTIA_ENABLE_REG[0]                                                                                                                                                                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |pokeymax|CHANNEL_MODE_REG                                                                                                                                                                                ;
; 3:1                ; 35 bits   ; 70 LEs        ; 0 LEs                ; 70 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|request_di_reg[27]                                                                                                                             ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pot_counter_reg[1]                                                                                                                                                                 ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                                                                                                                                          ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                                                                                                                                          ;
; 3:1                ; 8 bits    ; 16 LEs        ; 0 LEs                ; 16 LEs                 ; Yes        ; |pokeymax|pokey:pokey1|serin_shift_reg[9]                                                                                                                                                                 ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                                                                                                                                          ;
; 3:1                ; 24 bits   ; 48 LEs        ; 24 LEs               ; 24 LEs                 ; Yes        ; |pokeymax|mixer:mixer1|RIGHT_PLAYING_COUNT_REG[17]                                                                                                                                                        ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                                                                                                                                          ;
; 3:1                ; 6 bits    ; 12 LEs        ; 0 LEs                ; 12 LEs                 ; Yes        ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|compare_latch_reg[3]                                                                                               ;
; 4:1                ; 7 bits    ; 14 LEs        ; 14 LEs               ; 0 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[6]                                                                                                                                ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|CPU_FLASH_DATA_REG[23]                                                                                                                                                                          ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|CPU_FLASH_DATA_REG[15]                                                                                                                                                                          ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|CPU_FLASH_DATA_REG[27]                                                                                                                                                                          ;
; 3:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|CPU_FLASH_DATA_REG[5]                                                                                                                                                                           ;
; 4:1                ; 8 bits    ; 16 LEs        ; 8 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|serout_shift_reg[5]                                                                                                                                                                ;
; 4:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|serin_bitcount_reg[2]                                                                                                                                                              ;
; 4:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]                                                                                                                                ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|csr_status_busy[0]               ;
; 4:1                ; 10 bits   ; 20 LEs        ; 20 LEs               ; 0 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_page_addr[13]              ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |pokeymax|CONFIG_FLASH_STATE_REG[0]                                                                                                                                                                       ;
; 5:1                ; 4 bits    ; 12 LEs        ; 8 LEs                ; 4 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|serout_bitcount_reg[0]                                                                                                                                                             ;
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_sector_addr[2]             ;
; 6:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_burstcount_reg[1]           ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_erase_state[1]                 ;
; 6:1                ; 2 bits    ; 8 LEs         ; 2 LEs                ; 6 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|flash_ardin_align_backup_reg[0]  ;
; 18:1               ; 2 bits    ; 24 LEs        ; 10 LEs               ; 14 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|state_reg[0]                                                                                                                                   ;
; 7:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|data_count[2]                    ;
; 7:1                ; 22 bits   ; 88 LEs        ; 66 LEs               ; 22 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_count[17]                  ;
; 256:1              ; 10 bits   ; 1700 LEs      ; 110 LEs              ; 1590 LEs               ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|request_addr_reg[16]                                                                                                                           ;
; 8:1                ; 3 bits    ; 15 LEs        ; 12 LEs               ; 3 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_count[3]                   ;
; 7:1                ; 11 bits   ; 44 LEs        ; 33 LEs               ; 11 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_count[12]                  ;
; 9:1                ; 3 bits    ; 18 LEs        ; 6 LEs                ; 12 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_count[4]                   ;
; 257:1              ; 3 bits    ; 513 LEs       ; 15 LEs               ; 498 LEs                ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|request_addr_reg[1]                                                                                                                            ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |pokeymax|POST_DIVIDE_REG[5]                                                                                                                                                                              ;
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |pokeymax|GTIA_ENABLE_REG[3]                                                                                                                                                                              ;
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_wp_mode[0]                     ;
; 3:1                ; 23 bits   ; 46 LEs        ; 23 LEs               ; 23 LEs                 ; Yes        ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller|csr_sector_page_erase_addr_reg[22] ;
; 5:1                ; 8 bits    ; 24 LEs        ; 16 LEs               ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|allpot_reg[7]                                                                                                                                                                      ;
; 6:1                ; 2 bits    ; 8 LEs         ; 0 LEs                ; 8 LEs                  ; Yes        ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[7]                                                                                               ;
; 6:1                ; 6 bits    ; 24 LEs        ; 6 LEs                ; 18 LEs                 ; Yes        ; |pokeymax|pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1|keycode_latch_reg[0]                                                                                               ;
; 3:1                ; 25 bits   ; 50 LEs        ; 50 LEs               ; 0 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash_do[19]                                                                                                                                   ;
; 3:1                ; 5 bits    ; 10 LEs        ; 10 LEs               ; 0 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash_do[4]                                                                                                                                    ;
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |pokeymax|mixer:mixer1|Mux15                                                                                                                                                                              ;
; 3:1                ; 15 bits   ; 30 LEs        ; 30 LEs               ; 0 LEs                  ; No         ; |pokeymax|mixer:mixer1|saturated                                                                                                                                                                          ;
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|avmm_read_valid_state            ;
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |pokeymax|addr_bits                                                                                                                                                                                       ;
; 16:1               ; 2 bits    ; 20 LEs        ; 8 LEs                ; 12 LEs                 ; No         ; |pokeymax|mixer:mixer1|Mux7                                                                                                                                                                               ;
; 16:1               ; 15 bits   ; 150 LEs       ; 60 LEs               ; 90 LEs                 ; No         ; |pokeymax|mixer:mixer1|Mux43                                                                                                                                                                              ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state                      ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state                      ;
; 10:1               ; 2 bits    ; 12 LEs        ; 10 LEs               ; 2 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|erase_state                      ;
; 8:1                ; 2 bits    ; 10 LEs        ; 8 LEs                ; 2 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state                      ;
; 8:1                ; 2 bits    ; 10 LEs        ; 4 LEs                ; 6 LEs                  ; No         ; |pokeymax|flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|write_state                      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                           ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                      ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                      ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                      ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                      ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                       ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                       ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                       ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                       ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment                  ; Value                  ; From ; To                                                                                                                                                                 ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; dreg[0]                                                                                                                                                            ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; dreg[0]                                                                                                                                                            ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; dreg[0]                                                                                                                                                            ;
; PRESERVE_REGISTER           ; ON                     ; -    ; dreg[0]                                                                                                                                                            ;
; ADV_NETLIST_OPT_ALLOWED     ; NEVER_ALLOW            ; -    ; din_s1                                                                                                                                                             ;
; SYNCHRONIZER_IDENTIFICATION ; FORCED_IF_ASYNCHRONOUS ; -    ; din_s1                                                                                                                                                             ;
; DONT_MERGE_REGISTER         ; ON                     ; -    ; din_s1                                                                                                                                                             ;
; PRESERVE_REGISTER           ; ON                     ; -    ; din_s1                                                                                                                                                             ;
+-----------------------------+------------------------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; Assignment    ; Value ; From ; To                                                                                                                         ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+
; GLOBAL_SIGNAL ; OFF   ; -    ; fr_clock                                                                                                                   ;
+---------------+-------+------+----------------------------------------------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------+
; Source assignments for altshift_taps:toggle_reg_rtl_0|shift_taps_n0m:auto_generated|altsyncram_4ga1:altsyncram2 ;
+---------------------------------+--------------------+------+---------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                ;
+---------------------------------+--------------------+------+---------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                 ;
+---------------------------------+--------------------+------+---------------------------------------------------+


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: Top-level Entity: |pokeymax ;
+----------------------------+----------+----------------------------------+
; Parameter Name             ; Value    ; Type                             ;
+----------------------------+----------+----------------------------------+
; pokeys                     ; 1        ; Untyped                          ;
; lowpass                    ; 0        ; Signed Integer                   ;
; enable_auto_stereo         ; 1        ; Untyped                          ;
; fancy_switch_bit           ; 20       ; Signed Integer                   ;
; gtia_audio_bit             ; 7        ; Untyped                          ;
; detect_right_on_by_default ; 1        ; Signed Integer                   ;
; saturate_on_by_default     ; 1        ; Signed Integer                   ;
; a4_bit                     ; 1        ; Untyped                          ;
; a5_bit                     ; 2        ; Untyped                          ;
; a6_bit                     ; 3        ; Untyped                          ;
; a7_bit                     ; 4        ; Untyped                          ;
; cs0_bit                    ; 18       ; Signed Integer                   ;
; cs1_bit                    ; 19       ; Signed Integer                   ;
; spdif_bit                  ; 10       ; Untyped                          ;
; ps2clk_bit                 ; 5        ; Untyped                          ;
; ps2dat_bit                 ; 6        ; Untyped                          ;
; ext_bits                   ; 10       ; Untyped                          ;
; pll_v2                     ; 0        ; Untyped                          ;
; enable_config              ; 1        ; Signed Integer                   ;
; enable_sid                 ; 0        ; Untyped                          ;
; enable_psg                 ; 0        ; Untyped                          ;
; enable_covox               ; 0        ; Untyped                          ;
; enable_sample              ; 0        ; Untyped                          ;
; enable_flash               ; 1        ; Untyped                          ;
; enable_audout2             ; 0        ; Untyped                          ;
; enable_spdif               ; 0        ; Signed Integer                   ;
; enable_ps2                 ; 0        ; Signed Integer                   ;
; enable_adc                 ; 1        ; Untyped                          ;
; paddle_lvds                ; 1        ; Untyped                          ;
; paddle_comp                ; 0        ; Untyped                          ;
; enable_iox                 ; 0        ; Untyped                          ;
; sid_wave_base              ; 79872    ; Untyped                          ;
; flash_addr_bits            ; 17       ; Untyped                          ;
; ext_clk_enable             ; 0        ; Signed Integer                   ;
; version                    ; 127M16HK ; Untyped                          ;
+----------------------------+----------+----------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: int_osc:oscillator|altera_int_osc:int_osc_0 ;
+-----------------+--------+---------------------------------------------------------------+
; Parameter Name  ; Value  ; Type                                                          ;
+-----------------+--------+---------------------------------------------------------------+
; DEVICE_FAMILY   ; MAX 10 ; String                                                        ;
; DEVICE_ID       ; 08     ; String                                                        ;
; CLOCK_FREQUENCY ; 116    ; String                                                        ;
+-----------------+--------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst ;
+----------------+-------+----------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                 ;
+----------------+-------+----------------------------------------------------------------------+
; addr_bits      ; 17    ; Signed Integer                                                       ;
+----------------+-------+----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0 ;
+-------------------------------------+----------------+----------------------------------------------------------------------------------------+
; Parameter Name                      ; Value          ; Type                                                                                   ;
+-------------------------------------+----------------+----------------------------------------------------------------------------------------+
; DEVICE_FAMILY                       ; MAX 10         ; String                                                                                 ;
; PART_NAME                           ; 10M16SCU169C8G ; String                                                                                 ;
; IS_DUAL_BOOT                        ; False          ; String                                                                                 ;
; IS_ERAM_SKIP                        ; True           ; String                                                                                 ;
; IS_COMPRESSED_IMAGE                 ; False          ; String                                                                                 ;
; INIT_FILENAME                       ;                ; String                                                                                 ;
; DEVICE_ID                           ; 16             ; String                                                                                 ;
; INIT_FILENAME_SIM                   ;                ; String                                                                                 ;
; PARALLEL_MODE                       ; true           ; Enumerated                                                                             ;
; READ_AND_WRITE_MODE                 ; true           ; Enumerated                                                                             ;
; WRAPPING_BURST_MODE                 ; false          ; Enumerated                                                                             ;
; AVMM_CSR_DATA_WIDTH                 ; 32             ; Signed Integer                                                                         ;
; AVMM_DATA_DATA_WIDTH                ; 32             ; Signed Integer                                                                         ;
; AVMM_DATA_ADDR_WIDTH                ; 17             ; Signed Integer                                                                         ;
; AVMM_DATA_BURSTCOUNT_WIDTH          ; 2              ; Signed Integer                                                                         ;
; FLASH_DATA_WIDTH                    ; 32             ; Signed Integer                                                                         ;
; FLASH_ADDR_WIDTH                    ; 23             ; Signed Integer                                                                         ;
; FLASH_SEQ_READ_DATA_COUNT           ; 4              ; Signed Integer                                                                         ;
; FLASH_READ_CYCLE_MAX_INDEX          ; 4              ; Signed Integer                                                                         ;
; FLASH_ADDR_ALIGNMENT_BITS           ; 2              ; Signed Integer                                                                         ;
; FLASH_RESET_CYCLE_MAX_INDEX         ; 29             ; Signed Integer                                                                         ;
; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  ; 139            ; Signed Integer                                                                         ;
; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX ; 40600000       ; Signed Integer                                                                         ;
; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX ; 35380          ; Signed Integer                                                                         ;
; MIN_VALID_ADDR                      ; 0              ; Signed Integer                                                                         ;
; MAX_VALID_ADDR                      ; 104447         ; Signed Integer                                                                         ;
; MIN_UFM_VALID_ADDR                  ; 0              ; Signed Integer                                                                         ;
; MAX_UFM_VALID_ADDR                  ; 8191           ; Signed Integer                                                                         ;
; SECTOR1_START_ADDR                  ; 0              ; Signed Integer                                                                         ;
; SECTOR1_END_ADDR                    ; 4095           ; Signed Integer                                                                         ;
; SECTOR2_START_ADDR                  ; 4096           ; Signed Integer                                                                         ;
; SECTOR2_END_ADDR                    ; 8191           ; Signed Integer                                                                         ;
; SECTOR3_START_ADDR                  ; 8192           ; Signed Integer                                                                         ;
; SECTOR3_END_ADDR                    ; 36863          ; Signed Integer                                                                         ;
; SECTOR4_START_ADDR                  ; 36864          ; Signed Integer                                                                         ;
; SECTOR4_END_ADDR                    ; 104447         ; Signed Integer                                                                         ;
; SECTOR5_START_ADDR                  ; 0              ; Signed Integer                                                                         ;
; SECTOR5_END_ADDR                    ; 0              ; Signed Integer                                                                         ;
; SECTOR_READ_PROTECTION_MODE         ; 16             ; Signed Integer                                                                         ;
; SECTOR1_MAP                         ; 1              ; Signed Integer                                                                         ;
; SECTOR2_MAP                         ; 2              ; Signed Integer                                                                         ;
; SECTOR3_MAP                         ; 4              ; Signed Integer                                                                         ;
; SECTOR4_MAP                         ; 5              ; Signed Integer                                                                         ;
; SECTOR5_MAP                         ; 0              ; Signed Integer                                                                         ;
; ADDR_RANGE1_END_ADDR                ; 8191           ; Signed Integer                                                                         ;
; ADDR_RANGE2_END_ADDR                ; 104447         ; Signed Integer                                                                         ;
; ADDR_RANGE1_OFFSET                  ; 1024           ; Signed Integer                                                                         ;
; ADDR_RANGE2_OFFSET                  ; 39936          ; Signed Integer                                                                         ;
; ADDR_RANGE3_OFFSET                  ; 0              ; Signed Integer                                                                         ;
+-------------------------------------+----------------+----------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name      ; Value ; Type                                                                                                                                                                        ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; AVMM_CSR_DATA_WIDTH ; 32    ; Signed Integer                                                                                                                                                              ;
+---------------------+-------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller ;
+-------------------------------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name                      ; Value    ; Type                                                                                                                                                       ;
+-------------------------------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
; READ_AND_WRITE_MODE                 ; 1        ; Signed Integer                                                                                                                                             ;
; WRAPPING_BURST_MODE                 ; 0        ; Signed Integer                                                                                                                                             ;
; DATA_WIDTH                          ; 32       ; Signed Integer                                                                                                                                             ;
; AVMM_DATA_ADDR_WIDTH                ; 17       ; Signed Integer                                                                                                                                             ;
; AVMM_DATA_BURSTCOUNT_WIDTH          ; 2        ; Signed Integer                                                                                                                                             ;
; FLASH_ADDR_WIDTH                    ; 23       ; Signed Integer                                                                                                                                             ;
; FLASH_SEQ_READ_DATA_COUNT           ; 4        ; Signed Integer                                                                                                                                             ;
; FLASH_READ_CYCLE_MAX_INDEX          ; 4        ; Signed Integer                                                                                                                                             ;
; FLASH_ADDR_ALIGNMENT_BITS           ; 2        ; Signed Integer                                                                                                                                             ;
; FLASH_RESET_CYCLE_MAX_INDEX         ; 29       ; Signed Integer                                                                                                                                             ;
; FLASH_BUSY_TIMEOUT_CYCLE_MAX_INDEX  ; 139      ; Signed Integer                                                                                                                                             ;
; FLASH_ERASE_TIMEOUT_CYCLE_MAX_INDEX ; 40600000 ; Signed Integer                                                                                                                                             ;
; FLASH_WRITE_TIMEOUT_CYCLE_MAX_INDEX ; 35380    ; Signed Integer                                                                                                                                             ;
; MIN_VALID_ADDR                      ; 0        ; Signed Integer                                                                                                                                             ;
; MAX_VALID_ADDR                      ; 104447   ; Signed Integer                                                                                                                                             ;
; SECTOR1_START_ADDR                  ; 0        ; Signed Integer                                                                                                                                             ;
; SECTOR1_END_ADDR                    ; 4095     ; Signed Integer                                                                                                                                             ;
; SECTOR2_START_ADDR                  ; 4096     ; Signed Integer                                                                                                                                             ;
; SECTOR2_END_ADDR                    ; 8191     ; Signed Integer                                                                                                                                             ;
; SECTOR3_START_ADDR                  ; 8192     ; Signed Integer                                                                                                                                             ;
; SECTOR3_END_ADDR                    ; 36863    ; Signed Integer                                                                                                                                             ;
; SECTOR4_START_ADDR                  ; 36864    ; Signed Integer                                                                                                                                             ;
; SECTOR4_END_ADDR                    ; 104447   ; Signed Integer                                                                                                                                             ;
; SECTOR5_START_ADDR                  ; 0        ; Signed Integer                                                                                                                                             ;
; SECTOR5_END_ADDR                    ; 0        ; Signed Integer                                                                                                                                             ;
; SECTOR_READ_PROTECTION_MODE         ; 16       ; Signed Integer                                                                                                                                             ;
; SECTOR1_MAP                         ; 1        ; Signed Integer                                                                                                                                             ;
; SECTOR2_MAP                         ; 2        ; Signed Integer                                                                                                                                             ;
; SECTOR3_MAP                         ; 4        ; Signed Integer                                                                                                                                             ;
; SECTOR4_MAP                         ; 5        ; Signed Integer                                                                                                                                             ;
; SECTOR5_MAP                         ; 0        ; Signed Integer                                                                                                                                             ;
; ADDR_RANGE1_END_ADDR                ; 8191     ; Signed Integer                                                                                                                                             ;
; ADDR_RANGE2_END_ADDR                ; 104447   ; Signed Integer                                                                                                                                             ;
; ADDR_RANGE1_OFFSET                  ; 1024     ; Signed Integer                                                                                                                                             ;
; ADDR_RANGE2_OFFSET                  ; 39936    ; Signed Integer                                                                                                                                             ;
; ADDR_RANGE3_OFFSET                  ; 0        ; Signed Integer                                                                                                                                             ;
+-------------------------------------+----------+------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                    ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy_clear ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                          ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; depth          ; 2     ; Signed Integer                                                                                                                                                                                                                ;
+----------------+-------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg ;
+------------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name         ; Value  ; Type                                                                                                                                                                                                     ;
+------------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; LPM_WIDTH              ; 32     ; Signed Integer                                                                                                                                                                                           ;
; LPM_DIRECTION          ; LEFT   ; Untyped                                                                                                                                                                                                  ;
; LPM_AVALUE             ; UNUSED ; Untyped                                                                                                                                                                                                  ;
; LPM_SVALUE             ; UNUSED ; Untyped                                                                                                                                                                                                  ;
; DEVICE_FAMILY          ; MAX 10 ; Untyped                                                                                                                                                                                                  ;
; AUTO_CARRY_CHAINS      ; ON     ; AUTO_CARRY                                                                                                                                                                                               ;
; IGNORE_CARRY_BUFFERS   ; OFF    ; IGNORE_CARRY                                                                                                                                                                                             ;
; AUTO_CASCADE_CHAINS    ; ON     ; AUTO_CASCADE                                                                                                                                                                                             ;
; IGNORE_CASCADE_BUFFERS ; OFF    ; IGNORE_CASCADE                                                                                                                                                                                           ;
+------------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker ;
+------------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name   ; Value  ; Type                                                                                                                                                                                                                                          ;
+------------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; FLASH_ADDR_WIDTH ; 23     ; Signed Integer                                                                                                                                                                                                                                ;
; MIN_VALID_ADDR   ; 0      ; Signed Integer                                                                                                                                                                                                                                ;
; MAX_VALID_ADDR   ; 104447 ; Signed Integer                                                                                                                                                                                                                                ;
+------------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor ;
+----------------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name       ; Value  ; Type                                                                                                                                                                                                                              ;
+----------------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; FLASH_ADDR_WIDTH     ; 23     ; Signed Integer                                                                                                                                                                                                                    ;
; ADDR_RANGE1_END_ADDR ; 8191   ; Signed Integer                                                                                                                                                                                                                    ;
; ADDR_RANGE2_END_ADDR ; 104447 ; Signed Integer                                                                                                                                                                                                                    ;
; ADDR_RANGE1_OFFSET   ; 1024   ; Signed Integer                                                                                                                                                                                                                    ;
; ADDR_RANGE2_OFFSET   ; 39936  ; Signed Integer                                                                                                                                                                                                                    ;
; ADDR_RANGE3_OFFSET   ; 0      ; Signed Integer                                                                                                                                                                                                                    ;
+----------------------+--------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker ;
+--------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name     ; Value  ; Type                                                                                                                                                                                                                                                                       ;
+--------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; FLASH_ADDR_WIDTH   ; 23     ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR1_START_ADDR ; 0      ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR1_END_ADDR   ; 4095   ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR2_START_ADDR ; 4096   ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR2_END_ADDR   ; 8191   ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR3_START_ADDR ; 8192   ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR3_END_ADDR   ; 36863  ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR4_START_ADDR ; 36864  ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR4_END_ADDR   ; 104447 ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR5_START_ADDR ; 0      ; Signed Integer                                                                                                                                                                                                                                                             ;
; SECTOR5_END_ADDR   ; 0      ; Signed Integer                                                                                                                                                                                                                                                             ;
+--------------------+--------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                                                                                                                                                                   ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; SECTOR1_MAP    ; 1     ; Signed Integer                                                                                                                                                                                                                         ;
; SECTOR2_MAP    ; 2     ; Signed Integer                                                                                                                                                                                                                         ;
; SECTOR3_MAP    ; 4     ; Signed Integer                                                                                                                                                                                                                         ;
; SECTOR4_MAP    ; 5     ; Signed Integer                                                                                                                                                                                                                         ;
; SECTOR5_MAP    ; 0     ; Signed Integer                                                                                                                                                                                                                         ;
+----------------+-------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component ;
+-------------------------------+-------------------------+----------------------------------------+
; Parameter Name                ; Value                   ; Type                                   ;
+-------------------------------+-------------------------+----------------------------------------+
; OPERATION_MODE                ; NORMAL                  ; Untyped                                ;
; PLL_TYPE                      ; AUTO                    ; Untyped                                ;
; LPM_HINT                      ; CBX_MODULE_PREFIX=pllv3 ; Untyped                                ;
; QUALIFY_CONF_DONE             ; OFF                     ; Untyped                                ;
; COMPENSATE_CLOCK              ; CLK0                    ; Untyped                                ;
; SCAN_CHAIN                    ; LONG                    ; Untyped                                ;
; PRIMARY_CLOCK                 ; INCLK0                  ; Untyped                                ;
; INCLK0_INPUT_FREQUENCY        ; 20345                   ; Signed Integer                         ;
; INCLK1_INPUT_FREQUENCY        ; 0                       ; Untyped                                ;
; GATE_LOCK_SIGNAL              ; NO                      ; Untyped                                ;
; GATE_LOCK_COUNTER             ; 0                       ; Untyped                                ;
; LOCK_HIGH                     ; 1                       ; Untyped                                ;
; LOCK_LOW                      ; 1                       ; Untyped                                ;
; VALID_LOCK_MULTIPLIER         ; 1                       ; Untyped                                ;
; INVALID_LOCK_MULTIPLIER       ; 5                       ; Untyped                                ;
; SWITCH_OVER_ON_LOSSCLK        ; OFF                     ; Untyped                                ;
; SWITCH_OVER_ON_GATED_LOCK     ; OFF                     ; Untyped                                ;
; ENABLE_SWITCH_OVER_COUNTER    ; OFF                     ; Untyped                                ;
; SKIP_VCO                      ; OFF                     ; Untyped                                ;
; SWITCH_OVER_COUNTER           ; 0                       ; Untyped                                ;
; SWITCH_OVER_TYPE              ; AUTO                    ; Untyped                                ;
; FEEDBACK_SOURCE               ; EXTCLK0                 ; Untyped                                ;
; BANDWIDTH                     ; 0                       ; Untyped                                ;
; BANDWIDTH_TYPE                ; AUTO                    ; Untyped                                ;
; SPREAD_FREQUENCY              ; 0                       ; Untyped                                ;
; DOWN_SPREAD                   ; 0                       ; Untyped                                ;
; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF                     ; Untyped                                ;
; SELF_RESET_ON_LOSS_LOCK       ; ON                      ; Untyped                                ;
; CLK9_MULTIPLY_BY              ; 0                       ; Untyped                                ;
; CLK8_MULTIPLY_BY              ; 0                       ; Untyped                                ;
; CLK7_MULTIPLY_BY              ; 0                       ; Untyped                                ;
; CLK6_MULTIPLY_BY              ; 0                       ; Untyped                                ;
; CLK5_MULTIPLY_BY              ; 1                       ; Untyped                                ;
; CLK4_MULTIPLY_BY              ; 1                       ; Untyped                                ;
; CLK3_MULTIPLY_BY              ; 1                       ; Signed Integer                         ;
; CLK2_MULTIPLY_BY              ; 2                       ; Signed Integer                         ;
; CLK1_MULTIPLY_BY              ; 7                       ; Signed Integer                         ;
; CLK0_MULTIPLY_BY              ; 7                       ; Signed Integer                         ;
; CLK9_DIVIDE_BY                ; 0                       ; Untyped                                ;
; CLK8_DIVIDE_BY                ; 0                       ; Untyped                                ;
; CLK7_DIVIDE_BY                ; 0                       ; Untyped                                ;
; CLK6_DIVIDE_BY                ; 0                       ; Untyped                                ;
; CLK5_DIVIDE_BY                ; 1                       ; Untyped                                ;
; CLK4_DIVIDE_BY                ; 1                       ; Untyped                                ;
; CLK3_DIVIDE_BY                ; 8                       ; Signed Integer                         ;
; CLK2_DIVIDE_BY                ; 1                       ; Signed Integer                         ;
; CLK1_DIVIDE_BY                ; 3                       ; Signed Integer                         ;
; CLK0_DIVIDE_BY                ; 6                       ; Signed Integer                         ;
; CLK9_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK8_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK7_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK6_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK5_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK4_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK3_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK2_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK1_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK0_PHASE_SHIFT              ; 0                       ; Untyped                                ;
; CLK5_TIME_DELAY               ; 0                       ; Untyped                                ;
; CLK4_TIME_DELAY               ; 0                       ; Untyped                                ;
; CLK3_TIME_DELAY               ; 0                       ; Untyped                                ;
; CLK2_TIME_DELAY               ; 0                       ; Untyped                                ;
; CLK1_TIME_DELAY               ; 0                       ; Untyped                                ;
; CLK0_TIME_DELAY               ; 0                       ; Untyped                                ;
; CLK9_DUTY_CYCLE               ; 50                      ; Untyped                                ;
; CLK8_DUTY_CYCLE               ; 50                      ; Untyped                                ;
; CLK7_DUTY_CYCLE               ; 50                      ; Untyped                                ;
; CLK6_DUTY_CYCLE               ; 50                      ; Untyped                                ;
; CLK5_DUTY_CYCLE               ; 50                      ; Untyped                                ;
; CLK4_DUTY_CYCLE               ; 50                      ; Untyped                                ;
; CLK3_DUTY_CYCLE               ; 50                      ; Signed Integer                         ;
; CLK2_DUTY_CYCLE               ; 50                      ; Signed Integer                         ;
; CLK1_DUTY_CYCLE               ; 50                      ; Signed Integer                         ;
; CLK0_DUTY_CYCLE               ; 50                      ; Signed Integer                         ;
; CLK9_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK8_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK7_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK6_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK5_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK4_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK3_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK2_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK1_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK0_USE_EVEN_COUNTER_MODE    ; OFF                     ; Untyped                                ;
; CLK9_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK8_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK7_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK6_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK5_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK4_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK3_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK2_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK1_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; CLK0_USE_EVEN_COUNTER_VALUE   ; OFF                     ; Untyped                                ;
; LOCK_WINDOW_UI                ;  0.05                   ; Untyped                                ;
; LOCK_WINDOW_UI_BITS           ; UNUSED                  ; Untyped                                ;
; VCO_RANGE_DETECTOR_LOW_BITS   ; UNUSED                  ; Untyped                                ;
; VCO_RANGE_DETECTOR_HIGH_BITS  ; UNUSED                  ; Untyped                                ;
; DPA_MULTIPLY_BY               ; 0                       ; Untyped                                ;
; DPA_DIVIDE_BY                 ; 1                       ; Untyped                                ;
; DPA_DIVIDER                   ; 0                       ; Untyped                                ;
; EXTCLK3_MULTIPLY_BY           ; 1                       ; Untyped                                ;
; EXTCLK2_MULTIPLY_BY           ; 1                       ; Untyped                                ;
; EXTCLK1_MULTIPLY_BY           ; 1                       ; Untyped                                ;
; EXTCLK0_MULTIPLY_BY           ; 1                       ; Untyped                                ;
; EXTCLK3_DIVIDE_BY             ; 1                       ; Untyped                                ;
; EXTCLK2_DIVIDE_BY             ; 1                       ; Untyped                                ;
; EXTCLK1_DIVIDE_BY             ; 1                       ; Untyped                                ;
; EXTCLK0_DIVIDE_BY             ; 1                       ; Untyped                                ;
; EXTCLK3_PHASE_SHIFT           ; 0                       ; Untyped                                ;
; EXTCLK2_PHASE_SHIFT           ; 0                       ; Untyped                                ;
; EXTCLK1_PHASE_SHIFT           ; 0                       ; Untyped                                ;
; EXTCLK0_PHASE_SHIFT           ; 0                       ; Untyped                                ;
; EXTCLK3_TIME_DELAY            ; 0                       ; Untyped                                ;
; EXTCLK2_TIME_DELAY            ; 0                       ; Untyped                                ;
; EXTCLK1_TIME_DELAY            ; 0                       ; Untyped                                ;
; EXTCLK0_TIME_DELAY            ; 0                       ; Untyped                                ;
; EXTCLK3_DUTY_CYCLE            ; 50                      ; Untyped                                ;
; EXTCLK2_DUTY_CYCLE            ; 50                      ; Untyped                                ;
; EXTCLK1_DUTY_CYCLE            ; 50                      ; Untyped                                ;
; EXTCLK0_DUTY_CYCLE            ; 50                      ; Untyped                                ;
; VCO_MULTIPLY_BY               ; 0                       ; Untyped                                ;
; VCO_DIVIDE_BY                 ; 0                       ; Untyped                                ;
; SCLKOUT0_PHASE_SHIFT          ; 0                       ; Untyped                                ;
; SCLKOUT1_PHASE_SHIFT          ; 0                       ; Untyped                                ;
; VCO_MIN                       ; 0                       ; Untyped                                ;
; VCO_MAX                       ; 0                       ; Untyped                                ;
; VCO_CENTER                    ; 0                       ; Untyped                                ;
; PFD_MIN                       ; 0                       ; Untyped                                ;
; PFD_MAX                       ; 0                       ; Untyped                                ;
; M_INITIAL                     ; 0                       ; Untyped                                ;
; M                             ; 0                       ; Untyped                                ;
; N                             ; 1                       ; Untyped                                ;
; M2                            ; 1                       ; Untyped                                ;
; N2                            ; 1                       ; Untyped                                ;
; SS                            ; 1                       ; Untyped                                ;
; C0_HIGH                       ; 0                       ; Untyped                                ;
; C1_HIGH                       ; 0                       ; Untyped                                ;
; C2_HIGH                       ; 0                       ; Untyped                                ;
; C3_HIGH                       ; 0                       ; Untyped                                ;
; C4_HIGH                       ; 0                       ; Untyped                                ;
; C5_HIGH                       ; 0                       ; Untyped                                ;
; C6_HIGH                       ; 0                       ; Untyped                                ;
; C7_HIGH                       ; 0                       ; Untyped                                ;
; C8_HIGH                       ; 0                       ; Untyped                                ;
; C9_HIGH                       ; 0                       ; Untyped                                ;
; C0_LOW                        ; 0                       ; Untyped                                ;
; C1_LOW                        ; 0                       ; Untyped                                ;
; C2_LOW                        ; 0                       ; Untyped                                ;
; C3_LOW                        ; 0                       ; Untyped                                ;
; C4_LOW                        ; 0                       ; Untyped                                ;
; C5_LOW                        ; 0                       ; Untyped                                ;
; C6_LOW                        ; 0                       ; Untyped                                ;
; C7_LOW                        ; 0                       ; Untyped                                ;
; C8_LOW                        ; 0                       ; Untyped                                ;
; C9_LOW                        ; 0                       ; Untyped                                ;
; C0_INITIAL                    ; 0                       ; Untyped                                ;
; C1_INITIAL                    ; 0                       ; Untyped                                ;
; C2_INITIAL                    ; 0                       ; Untyped                                ;
; C3_INITIAL                    ; 0                       ; Untyped                                ;
; C4_INITIAL                    ; 0                       ; Untyped                                ;
; C5_INITIAL                    ; 0                       ; Untyped                                ;
; C6_INITIAL                    ; 0                       ; Untyped                                ;
; C7_INITIAL                    ; 0                       ; Untyped                                ;
; C8_INITIAL                    ; 0                       ; Untyped                                ;
; C9_INITIAL                    ; 0                       ; Untyped                                ;
; C0_MODE                       ; BYPASS                  ; Untyped                                ;
; C1_MODE                       ; BYPASS                  ; Untyped                                ;
; C2_MODE                       ; BYPASS                  ; Untyped                                ;
; C3_MODE                       ; BYPASS                  ; Untyped                                ;
; C4_MODE                       ; BYPASS                  ; Untyped                                ;
; C5_MODE                       ; BYPASS                  ; Untyped                                ;
; C6_MODE                       ; BYPASS                  ; Untyped                                ;
; C7_MODE                       ; BYPASS                  ; Untyped                                ;
; C8_MODE                       ; BYPASS                  ; Untyped                                ;
; C9_MODE                       ; BYPASS                  ; Untyped                                ;
; C0_PH                         ; 0                       ; Untyped                                ;
; C1_PH                         ; 0                       ; Untyped                                ;
; C2_PH                         ; 0                       ; Untyped                                ;
; C3_PH                         ; 0                       ; Untyped                                ;
; C4_PH                         ; 0                       ; Untyped                                ;
; C5_PH                         ; 0                       ; Untyped                                ;
; C6_PH                         ; 0                       ; Untyped                                ;
; C7_PH                         ; 0                       ; Untyped                                ;
; C8_PH                         ; 0                       ; Untyped                                ;
; C9_PH                         ; 0                       ; Untyped                                ;
; L0_HIGH                       ; 1                       ; Untyped                                ;
; L1_HIGH                       ; 1                       ; Untyped                                ;
; G0_HIGH                       ; 1                       ; Untyped                                ;
; G1_HIGH                       ; 1                       ; Untyped                                ;
; G2_HIGH                       ; 1                       ; Untyped                                ;
; G3_HIGH                       ; 1                       ; Untyped                                ;
; E0_HIGH                       ; 1                       ; Untyped                                ;
; E1_HIGH                       ; 1                       ; Untyped                                ;
; E2_HIGH                       ; 1                       ; Untyped                                ;
; E3_HIGH                       ; 1                       ; Untyped                                ;
; L0_LOW                        ; 1                       ; Untyped                                ;
; L1_LOW                        ; 1                       ; Untyped                                ;
; G0_LOW                        ; 1                       ; Untyped                                ;
; G1_LOW                        ; 1                       ; Untyped                                ;
; G2_LOW                        ; 1                       ; Untyped                                ;
; G3_LOW                        ; 1                       ; Untyped                                ;
; E0_LOW                        ; 1                       ; Untyped                                ;
; E1_LOW                        ; 1                       ; Untyped                                ;
; E2_LOW                        ; 1                       ; Untyped                                ;
; E3_LOW                        ; 1                       ; Untyped                                ;
; L0_INITIAL                    ; 1                       ; Untyped                                ;
; L1_INITIAL                    ; 1                       ; Untyped                                ;
; G0_INITIAL                    ; 1                       ; Untyped                                ;
; G1_INITIAL                    ; 1                       ; Untyped                                ;
; G2_INITIAL                    ; 1                       ; Untyped                                ;
; G3_INITIAL                    ; 1                       ; Untyped                                ;
; E0_INITIAL                    ; 1                       ; Untyped                                ;
; E1_INITIAL                    ; 1                       ; Untyped                                ;
; E2_INITIAL                    ; 1                       ; Untyped                                ;
; E3_INITIAL                    ; 1                       ; Untyped                                ;
; L0_MODE                       ; BYPASS                  ; Untyped                                ;
; L1_MODE                       ; BYPASS                  ; Untyped                                ;
; G0_MODE                       ; BYPASS                  ; Untyped                                ;
; G1_MODE                       ; BYPASS                  ; Untyped                                ;
; G2_MODE                       ; BYPASS                  ; Untyped                                ;
; G3_MODE                       ; BYPASS                  ; Untyped                                ;
; E0_MODE                       ; BYPASS                  ; Untyped                                ;
; E1_MODE                       ; BYPASS                  ; Untyped                                ;
; E2_MODE                       ; BYPASS                  ; Untyped                                ;
; E3_MODE                       ; BYPASS                  ; Untyped                                ;
; L0_PH                         ; 0                       ; Untyped                                ;
; L1_PH                         ; 0                       ; Untyped                                ;
; G0_PH                         ; 0                       ; Untyped                                ;
; G1_PH                         ; 0                       ; Untyped                                ;
; G2_PH                         ; 0                       ; Untyped                                ;
; G3_PH                         ; 0                       ; Untyped                                ;
; E0_PH                         ; 0                       ; Untyped                                ;
; E1_PH                         ; 0                       ; Untyped                                ;
; E2_PH                         ; 0                       ; Untyped                                ;
; E3_PH                         ; 0                       ; Untyped                                ;
; M_PH                          ; 0                       ; Untyped                                ;
; C1_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C2_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C3_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C4_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C5_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C6_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C7_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C8_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; C9_USE_CASC_IN                ; OFF                     ; Untyped                                ;
; CLK0_COUNTER                  ; G0                      ; Untyped                                ;
; CLK1_COUNTER                  ; G0                      ; Untyped                                ;
; CLK2_COUNTER                  ; G0                      ; Untyped                                ;
; CLK3_COUNTER                  ; G0                      ; Untyped                                ;
; CLK4_COUNTER                  ; G0                      ; Untyped                                ;
; CLK5_COUNTER                  ; G0                      ; Untyped                                ;
; CLK6_COUNTER                  ; E0                      ; Untyped                                ;
; CLK7_COUNTER                  ; E1                      ; Untyped                                ;
; CLK8_COUNTER                  ; E2                      ; Untyped                                ;
; CLK9_COUNTER                  ; E3                      ; Untyped                                ;
; L0_TIME_DELAY                 ; 0                       ; Untyped                                ;
; L1_TIME_DELAY                 ; 0                       ; Untyped                                ;
; G0_TIME_DELAY                 ; 0                       ; Untyped                                ;
; G1_TIME_DELAY                 ; 0                       ; Untyped                                ;
; G2_TIME_DELAY                 ; 0                       ; Untyped                                ;
; G3_TIME_DELAY                 ; 0                       ; Untyped                                ;
; E0_TIME_DELAY                 ; 0                       ; Untyped                                ;
; E1_TIME_DELAY                 ; 0                       ; Untyped                                ;
; E2_TIME_DELAY                 ; 0                       ; Untyped                                ;
; E3_TIME_DELAY                 ; 0                       ; Untyped                                ;
; M_TIME_DELAY                  ; 0                       ; Untyped                                ;
; N_TIME_DELAY                  ; 0                       ; Untyped                                ;
; EXTCLK3_COUNTER               ; E3                      ; Untyped                                ;
; EXTCLK2_COUNTER               ; E2                      ; Untyped                                ;
; EXTCLK1_COUNTER               ; E1                      ; Untyped                                ;
; EXTCLK0_COUNTER               ; E0                      ; Untyped                                ;
; ENABLE0_COUNTER               ; L0                      ; Untyped                                ;
; ENABLE1_COUNTER               ; L0                      ; Untyped                                ;
; CHARGE_PUMP_CURRENT           ; 2                       ; Untyped                                ;
; LOOP_FILTER_R                 ;  1.000000               ; Untyped                                ;
; LOOP_FILTER_C                 ; 5                       ; Untyped                                ;
; CHARGE_PUMP_CURRENT_BITS      ; 9999                    ; Untyped                                ;
; LOOP_FILTER_R_BITS            ; 9999                    ; Untyped                                ;
; LOOP_FILTER_C_BITS            ; 9999                    ; Untyped                                ;
; VCO_POST_SCALE                ; 0                       ; Untyped                                ;
; CLK2_OUTPUT_FREQUENCY         ; 0                       ; Untyped                                ;
; CLK1_OUTPUT_FREQUENCY         ; 0                       ; Untyped                                ;
; CLK0_OUTPUT_FREQUENCY         ; 0                       ; Untyped                                ;
; INTENDED_DEVICE_FAMILY        ; MAX 10                  ; Untyped                                ;
; PORT_CLKENA0                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKENA1                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKENA2                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKENA3                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKENA4                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKENA5                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_EXTCLKENA0               ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_EXTCLKENA1               ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_EXTCLKENA2               ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_EXTCLKENA3               ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_EXTCLK0                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_EXTCLK1                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_EXTCLK2                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_EXTCLK3                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKBAD0                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKBAD1                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLK0                     ; PORT_USED               ; Untyped                                ;
; PORT_CLK1                     ; PORT_USED               ; Untyped                                ;
; PORT_CLK2                     ; PORT_USED               ; Untyped                                ;
; PORT_CLK3                     ; PORT_USED               ; Untyped                                ;
; PORT_CLK4                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLK5                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLK6                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLK7                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLK8                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLK9                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANDATA                 ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANDATAOUT              ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANDONE                 ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCLKOUT1                 ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_SCLKOUT0                 ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_ACTIVECLOCK              ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKLOSS                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_INCLK1                   ; PORT_UNUSED             ; Untyped                                ;
; PORT_INCLK0                   ; PORT_USED               ; Untyped                                ;
; PORT_FBIN                     ; PORT_UNUSED             ; Untyped                                ;
; PORT_PLLENA                   ; PORT_UNUSED             ; Untyped                                ;
; PORT_CLKSWITCH                ; PORT_UNUSED             ; Untyped                                ;
; PORT_ARESET                   ; PORT_UNUSED             ; Untyped                                ;
; PORT_PFDENA                   ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANCLK                  ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANACLR                 ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANREAD                 ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANWRITE                ; PORT_UNUSED             ; Untyped                                ;
; PORT_ENABLE0                  ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_ENABLE1                  ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_LOCKED                   ; PORT_USED               ; Untyped                                ;
; PORT_CONFIGUPDATE             ; PORT_UNUSED             ; Untyped                                ;
; PORT_FBOUT                    ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_PHASEDONE                ; PORT_UNUSED             ; Untyped                                ;
; PORT_PHASESTEP                ; PORT_UNUSED             ; Untyped                                ;
; PORT_PHASEUPDOWN              ; PORT_UNUSED             ; Untyped                                ;
; PORT_SCANCLKENA               ; PORT_UNUSED             ; Untyped                                ;
; PORT_PHASECOUNTERSELECT       ; PORT_UNUSED             ; Untyped                                ;
; PORT_VCOOVERRANGE             ; PORT_CONNECTIVITY       ; Untyped                                ;
; PORT_VCOUNDERRANGE            ; PORT_CONNECTIVITY       ; Untyped                                ;
; M_TEST_SOURCE                 ; 5                       ; Untyped                                ;
; C0_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C1_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C2_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C3_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C4_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C5_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C6_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C7_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C8_TEST_SOURCE                ; 5                       ; Untyped                                ;
; C9_TEST_SOURCE                ; 5                       ; Untyped                                ;
; CBXI_PARAMETER                ; pllv3_altpll            ; Untyped                                ;
; VCO_FREQUENCY_CONTROL         ; AUTO                    ; Untyped                                ;
; VCO_PHASE_SHIFT_STEP          ; 0                       ; Untyped                                ;
; WIDTH_CLOCK                   ; 5                       ; Signed Integer                         ;
; WIDTH_PHASECOUNTERSELECT      ; 4                       ; Untyped                                ;
; USING_FBMIMICBIDIR_PORT       ; OFF                     ; Untyped                                ;
; DEVICE_FAMILY                 ; MAX 10                  ; Untyped                                ;
; SCAN_CHAIN_MIF_FILE           ; UNUSED                  ; Untyped                                ;
; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF                     ; Untyped                                ;
; AUTO_CARRY_CHAINS             ; ON                      ; AUTO_CARRY                             ;
; IGNORE_CARRY_BUFFERS          ; OFF                     ; IGNORE_CARRY                           ;
; AUTO_CASCADE_CHAINS           ; ON                      ; AUTO_CASCADE                           ;
; IGNORE_CASCADE_BUFFERS        ; OFF                     ; IGNORE_CASCADE                         ;
+-------------------------------+-------------------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: slave_timing_6502:bus_adapt ;
+----------------+-------+-------------------------------------------------+
; Parameter Name ; Value ; Type                                            ;
+----------------+-------+-------------------------------------------------+
; address_bits   ; 8     ; Signed Integer                                  ;
+----------------+-------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1 ;
+----------------------+-------+----------------------------+
; Parameter Name       ; Value ; Type                       ;
+----------------------+-------+----------------------------+
; custom_keyboard_scan ; 0     ; Signed Integer             ;
+----------------------+-------+----------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|complete_address_decoder:decode_addr1 ;
+----------------+-------+------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                   ;
+----------------+-------+------------------------------------------------------------------------+
; width          ; 4     ; Signed Integer                                                         ;
+----------------+-------+------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf0_delay ;
+----------------+-------+--------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                         ;
+----------------+-------+--------------------------------------------------------------+
; count          ; 1     ; Signed Integer                                               ;
; width          ; 8     ; Signed Integer                                               ;
+----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf1_delay ;
+----------------+-------+--------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                         ;
+----------------+-------+--------------------------------------------------------------+
; count          ; 1     ; Signed Integer                                               ;
; width          ; 8     ; Signed Integer                                               ;
+----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf2_delay ;
+----------------+-------+--------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                         ;
+----------------+-------+--------------------------------------------------------------+
; count          ; 1     ; Signed Integer                                               ;
; width          ; 8     ; Signed Integer                                               ;
+----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audf3_delay ;
+----------------+-------+--------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                         ;
+----------------+-------+--------------------------------------------------------------+
; count          ; 1     ; Signed Integer                                               ;
; width          ; 8     ; Signed Integer                                               ;
+----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|wide_delay_line:audctl_delay ;
+----------------+-------+---------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                          ;
+----------------+-------+---------------------------------------------------------------+
; count          ; 1     ; Signed Integer                                                ;
; width          ; 8     ; Signed Integer                                                ;
+----------------+-------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0 ;
+-----------------+-------+--------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                         ;
+-----------------+-------+--------------------------------------------------------------+
; underflow_delay ; 3     ; Signed Integer                                               ;
+-----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; count          ; 3     ; Signed Integer                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1 ;
+-----------------+-------+--------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                         ;
+-----------------+-------+--------------------------------------------------------------+
; underflow_delay ; 3     ; Signed Integer                                               ;
+-----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; count          ; 3     ; Signed Integer                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2 ;
+-----------------+-------+--------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                         ;
+-----------------+-------+--------------------------------------------------------------+
; underflow_delay ; 3     ; Signed Integer                                               ;
+-----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; count          ; 3     ; Signed Integer                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3 ;
+-----------------+-------+--------------------------------------------------------------+
; Parameter Name  ; Value ; Type                                                         ;
+-----------------+-------+--------------------------------------------------------------+
; underflow_delay ; 3     ; Signed Integer                                               ;
+-----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                                      ;
+----------------+-------+-------------------------------------------------------------------------------------------+
; count          ; 3     ; Signed Integer                                                                            ;
+----------------+-------+-------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:twotone_del ;
+----------------+-------+---------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                          ;
+----------------+-------+---------------------------------------------------------------+
; count          ; 2     ; Signed Integer                                                ;
+----------------+-------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|latch_delay_line:stimer_delay ;
+----------------+-------+----------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                           ;
+----------------+-------+----------------------------------------------------------------+
; count          ; 3     ; Signed Integer                                                 ;
+----------------+-------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_64_div ;
+----------------+-------+-------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                    ;
+----------------+-------+-------------------------------------------------------------------------+
; count          ; 28    ; Signed Integer                                                          ;
; resetcount     ; 7     ; Signed Integer                                                          ;
+----------------+-------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|syncreset_enable_divider:enable_15_div ;
+----------------+-------+-------------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                    ;
+----------------+-------+-------------------------------------------------------------------------+
; count          ; 114   ; Signed Integer                                                          ;
; resetcount     ; 34    ; Signed Integer                                                          ;
+----------------+-------+-------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serout_clock_delay ;
+----------------+-------+----------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                           ;
+----------------+-------+----------------------------------------------------------------+
; count          ; 2     ; Signed Integer                                                 ;
+----------------+-------+----------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: pokey:pokey1|delay_line:serin_clock_delay ;
+----------------+-------+---------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                          ;
+----------------+-------+---------------------------------------------------------------+
; count          ; 5     ; Signed Integer                                                ;
+----------------+-------+---------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: complete_address_decoder:\gen_config:decode_addr1 ;
+----------------+-------+-----------------------------------------------------------------------+
; Parameter Name ; Value ; Type                                                                  ;
+----------------+-------+-----------------------------------------------------------------------+
; width          ; 4     ; Signed Integer                                                        ;
+----------------+-------+-----------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_0 ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; implementation ; 2     ; Signed Integer                                ;
; lowpass        ; 0     ; Signed Integer                                ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_2 ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; implementation ; 2     ; Signed Integer                                ;
; lowpass        ; 0     ; Signed Integer                                ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: filtered_sigmadelta:dac_3 ;
+----------------+-------+-----------------------------------------------+
; Parameter Name ; Value ; Type                                          ;
+----------------+-------+-----------------------------------------------+
; implementation ; 2     ; Signed Integer                                ;
; lowpass        ; 0     ; Signed Integer                                ;
+----------------+-------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst ;
+------------------------------------------+---------------------+-----------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                      ;
+------------------------------------------+---------------------+-----------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                    ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                    ;
; REGISTER_MODE                            ; bypass              ; String                                                    ;
; SIZE                                     ; 8                   ; Signed Integer                                            ;
; ASYNC_MODE                               ; none                ; String                                                    ;
; SYNC_MODE                                ; none                ; String                                                    ;
; BUS_HOLD                                 ; false               ; String                                                    ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                    ;
; INVERT_OUTPUT                            ; false               ; String                                                    ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                    ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                    ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                    ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                    ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                    ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                    ;
; USE_ADVANCED_DDR_FEATURES                ; false               ; String                                                    ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                    ;
; INVERT_CLKDIV_INPUT_CLOCK                ; false               ; String                                                    ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                    ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                    ;
; ENABLE_OE_PORT                           ; true                ; String                                                    ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                    ;
; ENABLE_PHASE_INVERT_CTRL_PORT            ; false               ; String                                                    ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                    ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                    ;
+------------------------------------------+---------------------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[1].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[2].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[3].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[4].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[5].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[6].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[7].altgpio_bit_i ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; Parameter Name                           ; Value               ; Type                                                                                                           ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
; PIN_TYPE                                 ; bidir               ; String                                                                                                         ;
; BUFFER_TYPE                              ; pseudo_differential ; String                                                                                                         ;
; REGISTER_MODE                            ; bypass              ; String                                                                                                         ;
; ASYNC_MODE                               ; none                ; String                                                                                                         ;
; SYNC_MODE                                ; none                ; String                                                                                                         ;
; BUS_HOLD                                 ; false               ; String                                                                                                         ;
; SET_REGISTER_OUTPUTS_HIGH                ; false               ; String                                                                                                         ;
; USE_ENHANCED_DDR_HIO_REGISTER            ; false               ; String                                                                                                         ;
; BYPASS_THREE_QUARTER_REGISTER            ; true                ; String                                                                                                         ;
; INVERT_OUTPUT                            ; false               ; String                                                                                                         ;
; INVERT_INPUT_CLOCK                       ; false               ; String                                                                                                         ;
; INVERT_OUTPUT_CLOCK                      ; false               ; String                                                                                                         ;
; INVERT_OE_INCLOCK                        ; false               ; String                                                                                                         ;
; USE_ONE_REG_TO_DRIVE_OE                  ; false               ; String                                                                                                         ;
; USE_DDIO_REG_TO_DRIVE_OE                 ; false               ; String                                                                                                         ;
; OPEN_DRAIN_OUTPUT                        ; false               ; String                                                                                                         ;
; ENABLE_OE_HALF_CYCLE_DELAY               ; true                ; String                                                                                                         ;
; USE_ADVANCED_DDR_FEATURES_FOR_INPUT_ONLY ; false               ; String                                                                                                         ;
; ENABLE_CLOCK_ENA_PORT                    ; false               ; String                                                                                                         ;
; ENABLE_HR_CLOCK                          ; false               ; String                                                                                                         ;
; ENABLE_PHASE_DETECTOR_FOR_CK             ; false               ; String                                                                                                         ;
; ENABLE_NSLEEP_PORT                       ; false               ; String                                                                                                         ;
+------------------------------------------+---------------------+----------------------------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: altshift_taps:toggle_reg_rtl_0 ;
+----------------+----------------+-----------------------------------------------+
; Parameter Name ; Value          ; Type                                          ;
+----------------+----------------+-----------------------------------------------+
; WIDTH_BYTEENA  ; 1              ; Untyped                                       ;
; NUMBER_OF_TAPS ; 1              ; Untyped                                       ;
; TAP_DISTANCE   ; 255            ; Untyped                                       ;
; WIDTH          ; 1              ; Untyped                                       ;
; POWER_UP_STATE ; CLEARED        ; Untyped                                       ;
; CBXI_PARAMETER ; shift_taps_n0m ; Untyped                                       ;
+----------------+----------------+-----------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; lpm_shiftreg Parameter Settings by Entity Instance                                                                                                                                                                         ;
+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Name                       ; Value                                                                                                                                                                                         ;
+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Number of entity instances ; 1                                                                                                                                                                                             ;
; Entity Instance            ; flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg ;
;     -- LPM_WIDTH           ; 32                                                                                                                                                                                            ;
;     -- LPM_DIRECTION       ; LEFT                                                                                                                                                                                          ;
+----------------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------+
; altshift_taps Parameter Settings by Entity Instance         ;
+----------------------------+--------------------------------+
; Name                       ; Value                          ;
+----------------------------+--------------------------------+
; Number of entity instances ; 1                              ;
; Entity Instance            ; altshift_taps:toggle_reg_rtl_0 ;
;     -- NUMBER_OF_TAPS      ; 1                              ;
;     -- TAP_DISTANCE        ; 255                            ;
;     -- WIDTH               ; 1                              ;
+----------------------------+--------------------------------+


+-------------------------------------------------------------------------------------+
; altpll Parameter Settings by Entity Instance                                        ;
+-------------------------------+-----------------------------------------------------+
; Name                          ; Value                                               ;
+-------------------------------+-----------------------------------------------------+
; Number of entity instances    ; 1                                                   ;
; Entity Instance               ; pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component ;
;     -- OPERATION_MODE         ; NORMAL                                              ;
;     -- PLL_TYPE               ; AUTO                                                ;
;     -- PRIMARY_CLOCK          ; INCLK0                                              ;
;     -- INCLK0_INPUT_FREQUENCY ; 20345                                               ;
;     -- INCLK1_INPUT_FREQUENCY ; 0                                                   ;
;     -- VCO_MULTIPLY_BY        ; 0                                                   ;
;     -- VCO_DIVIDE_BY          ; 0                                                   ;
+-------------------------------+-----------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "synchronizer:synchronizer_SIO"                                                      ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; sync ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------+
; Port Connectivity Checks: "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0" ;
+------+-------+----------+-----------------------------------------------+
; Port ; Type  ; Severity ; Details                                       ;
+------+-------+----------+-----------------------------------------------+
; din  ; Input ; Info     ; Stuck at GND                                  ;
+------+-------+----------+-----------------------------------------------+


+----------------------------------------------------------------------+
; Port Connectivity Checks: "simple_low_pass_filter:\adc_on:adcfilter" ;
+----------------+-------+----------+----------------------------------+
; Port           ; Type  ; Severity ; Details                          ;
+----------------+-------+----------+----------------------------------+
; audio_in[7..0] ; Input ; Info     ; Stuck at GND                     ;
+----------------+-------+----------+----------------------------------+


+----------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd" ;
+--------+-------+----------+------------------------------------------------------------------------+
; Port   ; Type  ; Severity ; Details                                                                ;
+--------+-------+----------+------------------------------------------------------------------------+
; enable ; Input ; Info     ; Stuck at VCC                                                           ;
+--------+-------+----------+------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "mixer:mixer1"                                                                                   ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; adc_en[3..2]     ; Input  ; Info     ; Stuck at VCC                                                                        ;
; adc_en[1..0]     ; Input  ; Info     ; Stuck at GND                                                                        ;
; ch4              ; Input  ; Info     ; Stuck at GND                                                                        ;
; ch5              ; Input  ; Info     ; Stuck at GND                                                                        ;
; ch6              ; Input  ; Info     ; Stuck at GND                                                                        ;
; ch7              ; Input  ; Info     ; Stuck at GND                                                                        ;
; ch8              ; Input  ; Info     ; Stuck at GND                                                                        ;
; ch9              ; Input  ; Info     ; Stuck at GND                                                                        ;
; cha[14..0]       ; Input  ; Info     ; Stuck at GND                                                                        ;
; audio_1_unsigned ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "complete_address_decoder:\gen_config:decode_addr1"                                              ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; addr_decoded[10] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; addr_decoded[8]  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|latch_delay_line:stimer_delay" ;
+------------+-------+----------+----------------------------------------+
; Port       ; Type  ; Severity ; Details                                ;
+------------+-------+----------+----------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                           ;
+------------+-------+----------+----------------------------------------+


+-----------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|latch_delay_line:twotone_del" ;
+------------+-------+----------+---------------------------------------+
; Port       ; Type  ; Severity ; Details                               ;
+------------+-------+----------+---------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                          ;
+------------+-------+----------+---------------------------------------+


+-----------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audctl_delay" ;
+------------+-------+----------+---------------------------------------+
; Port       ; Type  ; Severity ; Details                               ;
+------------+-------+----------+---------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                          ;
+------------+-------+----------+---------------------------------------+


+----------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf3_delay" ;
+------------+-------+----------+--------------------------------------+
; Port       ; Type  ; Severity ; Details                              ;
+------------+-------+----------+--------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                         ;
+------------+-------+----------+--------------------------------------+


+----------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf2_delay" ;
+------------+-------+----------+--------------------------------------+
; Port       ; Type  ; Severity ; Details                              ;
+------------+-------+----------+--------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                         ;
+------------+-------+----------+--------------------------------------+


+----------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf1_delay" ;
+------------+-------+----------+--------------------------------------+
; Port       ; Type  ; Severity ; Details                              ;
+------------+-------+----------+--------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                         ;
+------------+-------+----------+--------------------------------------+


+----------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|wide_delay_line:audf0_delay" ;
+------------+-------+----------+--------------------------------------+
; Port       ; Type  ; Severity ; Details                              ;
+------------+-------+----------+--------------------------------------+
; sync_reset ; Input ; Info     ; Stuck at GND                         ;
+------------+-------+----------+--------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1|complete_address_decoder:decode_addr1"                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port             ; Type   ; Severity ; Details                                                                             ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+
; addr_decoded[12] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------------------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "pokey:pokey1"                                                                                       ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                 ; Type   ; Severity ; Details                                                                             ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+
; keyboard_scan_update ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; sio_out2             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; sio_out3             ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+----------------------+--------+----------+-------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "slave_timing_6502:bus_adapt"                                                                       ;
+---------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                ; Type   ; Severity ; Details                                                                             ;
+---------------------+--------+----------+-------------------------------------------------------------------------------------+
; cs                  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; enable_double_cycle ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+---------------------+--------+----------+-------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "pllv3:\pll_v3_inst:pll_inst"                                                        ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; Port ; Type   ; Severity ; Details                                                                             ;
+------+--------+----------+-------------------------------------------------------------------------------------+
; c3   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+------+--------+----------+-------------------------------------------------------------------------------------+


+--------------------------------------------------------------------+
; Port Connectivity Checks: "synchronizer:synchronizer_fancy_enable" ;
+------+-------+----------+------------------------------------------+
; Port ; Type  ; Severity ; Details                                  ;
+------+-------+----------+------------------------------------------+
; raw  ; Input ; Info     ; Stuck at VCC                             ;
+------+-------+----------+------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block" ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; Port     ; Type  ; Severity ; Details                                                                                                                                            ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+
; nosc_ena ; Input ; Info     ; Stuck at GND                                                                                                                                       ;
; par_en   ; Input ; Info     ; Stuck at VCC                                                                                                                                       ;
+----------+-------+----------+----------------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" ;
+-----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Port            ; Type  ; Severity ; Details                                                                                                                                                                                                             ;
+-----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; address[22..17] ; Input ; Info     ; Stuck at GND                                                                                                                                                                                                        ;
+-----------------+-------+----------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst|flash:flash1" ;
+-------------------------+-------+----------+----------------------------------------------+
; Port                    ; Type  ; Severity ; Details                                      ;
+-------------------------+-------+----------+----------------------------------------------+
; avmm_data_burstcount[1] ; Input ; Info     ; Stuck at GND                                 ;
; avmm_data_burstcount[0] ; Input ; Info     ; Stuck at VCC                                 ;
+-------------------------+-------+----------+----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Port Connectivity Checks: "flash_controller:\flash_on:flash_controller_inst"                                                            ;
+-------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; Port                          ; Type   ; Severity ; Details                                                                             ;
+-------------------------------+--------+----------+-------------------------------------------------------------------------------------+
; flash_req_request[7]          ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req_request[2]          ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req_complete            ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; flash_req_complete_slow[5..2] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; flash_req_complete_slow[7]    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
; flash_req2_addr[12..1]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req3_addr[12..8]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req3_addr[7]            ; Input  ; Info     ; Stuck at VCC                                                                        ;
; flash_req6_addr[12..9]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req6_addr[8]            ; Input  ; Info     ; Stuck at VCC                                                                        ;
; flash_req6_addr[7]            ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req7_addr[8..7]         ; Input  ; Info     ; Stuck at VCC                                                                        ;
; flash_req7_addr[12..9]        ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_req8_addr               ; Input  ; Info     ; Stuck at GND                                                                        ;
; flash_data_out                ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
+-------------------------------+--------+----------+-------------------------------------------------------------------------------------+


+------------------------------------------------+
; Port Connectivity Checks: "int_osc:oscillator" ;
+--------+-------+----------+--------------------+
; Port   ; Type  ; Severity ; Details            ;
+--------+-------+----------+--------------------+
; oscena ; Input ; Info     ; Stuck at VCC       ;
+--------+-------+----------+--------------------+


+-----------------------------------------------------+
; Post-Synthesis Netlist Statistics for Top Partition ;
+----------------------------+------------------------+
; Type                       ; Count                  ;
+----------------------------+------------------------+
; boundary_port              ; 70                     ;
; cycloneiii_ff              ; 1451                   ;
;     CLR                    ; 289                    ;
;     CLR SCLR               ; 20                     ;
;     CLR SLD                ; 30                     ;
;     ENA                    ; 177                    ;
;     ENA CLR                ; 653                    ;
;     ENA CLR SCLR           ; 26                     ;
;     ENA CLR SLD            ; 76                     ;
;     ENA SCLR               ; 5                      ;
;     SCLR                   ; 66                     ;
;     SLD                    ; 6                      ;
;     plain                  ; 103                    ;
; cycloneiii_io_obuf         ; 39                     ;
; cycloneiii_lcell_comb      ; 1924                   ;
;     arith                  ; 529                    ;
;         2 data inputs      ; 163                    ;
;         3 data inputs      ; 366                    ;
;     normal                 ; 1395                   ;
;         0 data inputs      ; 8                      ;
;         1 data inputs      ; 65                     ;
;         2 data inputs      ; 207                    ;
;         3 data inputs      ; 370                    ;
;         4 data inputs      ; 745                    ;
; cycloneiii_pll             ; 1                      ;
; cycloneiii_pseudo_diff_out ; 8                      ;
; cycloneiii_ram_block       ; 1                      ;
; fiftyfivenm_io_ibuf        ; 8                      ;
; fiftyfivenm_oscillator     ; 1                      ;
; fiftyfivenm_unvm           ; 1                      ;
;                            ;                        ;
; Max LUT depth              ; 9.00                   ;
; Average LUT depth          ; 3.73                   ;
+----------------------------+------------------------+


+-------------------------------+
; Elapsed Time Per Partition    ;
+----------------+--------------+
; Partition Name ; Elapsed Time ;
+----------------+--------------+
; Top            ; 00:00:02     ;
+----------------+--------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Analysis & Synthesis
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Sat May 11 10:22:45 2024
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pokeymax -c pokeymax
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
Info (12021): Found 2 design units, including 1 entities, in source file flash_controller.vhd
    Info (12022): Found design unit 1: flash_controller-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash_controller.vhd Line: 54
    Info (12023): Found entity 1: flash_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash_controller.vhd Line: 19
Info (12021): Found 2 design units, including 1 entities, in source file stereo_detect.vhd
    Info (12022): Found design unit 1: stereo_detect-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/stereo_detect.vhd Line: 24
    Info (12023): Found entity 1: stereo_detect File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/stereo_detect.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file iox_glue.vhdl
    Info (12022): Found design unit 1: iox_glue-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/iox_glue.vhdl Line: 46
    Info (12023): Found entity 1: iox_glue File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/iox_glue.vhdl Line: 22
Info (12021): Found 2 design units, including 1 entities, in source file i2c_master.vhd
    Info (12022): Found design unit 1: i2c_master-logic File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/i2c_master.vhd Line: 54
    Info (12023): Found entity 1: i2c_master File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/i2c_master.vhd Line: 36
Info (12021): Found 2 design units, including 1 entities, in source file slave_timing_6502.vhd
    Info (12022): Found design unit 1: slave_timing_6502-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/slave_timing_6502.vhd Line: 40
    Info (12023): Found entity 1: slave_timing_6502 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/slave_timing_6502.vhd Line: 6
Info (12021): Found 2 design units, including 1 entities, in source file complete_address_decoder.vhdl
    Info (12022): Found design unit 1: complete_address_decoder-tree File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/complete_address_decoder.vhdl Line: 30
    Info (12023): Found entity 1: complete_address_decoder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/complete_address_decoder.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file syncreset_enable_divider.vhd
    Info (12022): Found design unit 1: syncreset_enable_divider-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/syncreset_enable_divider.vhd Line: 25
    Info (12023): Found entity 1: syncreset_enable_divider File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/syncreset_enable_divider.vhd Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file enable_divider.vhdl
    Info (12022): Found design unit 1: enable_divider-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/enable_divider.vhdl Line: 24
    Info (12023): Found entity 1: enable_divider File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/enable_divider.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file delay_line.vhdl
    Info (12022): Found design unit 1: delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/delay_line.vhdl Line: 26
    Info (12023): Found entity 1: delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/delay_line.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file wide_delay_line.vhdl
    Info (12022): Found design unit 1: wide_delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/wide_delay_line.vhdl Line: 26
    Info (12023): Found entity 1: wide_delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/wide_delay_line.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file latch_delay_line.vhdl
    Info (12022): Found design unit 1: latch_delay_line-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/latch_delay_line.vhdl Line: 26
    Info (12023): Found entity 1: latch_delay_line File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/latch_delay_line.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_1storder.vhd
    Info (12022): Found design unit 1: sigmadelta_1storder-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sigmadelta_1storder.vhd Line: 27
    Info (12023): Found entity 1: sigmadelta_1storder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sigmadelta_1storder.vhd Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file sigmadelta_2ndorder.vhd
    Info (12022): Found design unit 1: sigmadelta_2ndorder-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sigmadelta_2ndorder.vhd Line: 27
    Info (12023): Found entity 1: sigmadelta_2ndorder File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sigmadelta_2ndorder.vhd Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file filtered_sigmadelta.vhd
    Info (12022): Found design unit 1: filtered_sigmadelta-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/filtered_sigmadelta.vhd Line: 32
    Info (12023): Found entity 1: filtered_sigmadelta File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/filtered_sigmadelta.vhd Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file generic_ram_infer.vhdl
    Info (12022): Found design unit 1: generic_ram_infer-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/generic_ram_infer.vhdl Line: 30
    Info (12023): Found entity 1: generic_ram_infer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/generic_ram_infer.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file simple_low_pass_filter.vhdl
    Info (12022): Found design unit 1: simple_low_pass_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/simple_low_pass_filter.vhdl Line: 29
    Info (12023): Found entity 1: simple_low_pass_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/simple_low_pass_filter.vhdl Line: 19
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_17_9.vhdl
    Info (12022): Found design unit 1: pokey_poly_17_9-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_17_9.vhdl Line: 27
    Info (12023): Found entity 1: pokey_poly_17_9 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_17_9.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_5.vhdl
    Info (12022): Found design unit 1: pokey_poly_5-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_5.vhdl Line: 24
    Info (12023): Found entity 1: pokey_poly_5 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_5.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_poly_4.vhdl
    Info (12022): Found design unit 1: pokey_poly_4-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_4.vhdl Line: 24
    Info (12023): Found entity 1: pokey_poly_4 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_poly_4.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_noise_filter.vhdl
    Info (12022): Found design unit 1: pokey_noise_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_noise_filter.vhdl Line: 32
    Info (12023): Found entity 1: pokey_noise_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_noise_filter.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_mixer_mux.vhdl
    Info (12022): Found design unit 1: pokey_mixer_mux-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_mixer_mux.vhdl Line: 36
    Info (12023): Found entity 1: pokey_mixer_mux File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_mixer_mux.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_mixer.vhdl
    Info (12022): Found design unit 1: pokey_mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_mixer.vhdl Line: 24
    Info (12023): Found entity 1: pokey_mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_mixer.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_keyboard_scanner.vhdl
    Info (12022): Found design unit 1: pokey_keyboard_scanner-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_keyboard_scanner.vhdl Line: 33
    Info (12023): Found entity 1: pokey_keyboard_scanner File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_keyboard_scanner.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey_countdown_timer.vhdl
    Info (12022): Found design unit 1: pokey_countdown_timer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_countdown_timer.vhdl Line: 28
    Info (12023): Found entity 1: pokey_countdown_timer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_countdown_timer.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file pokey/pokey.vhdl
    Info (12022): Found design unit 1: pokey-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 63
    Info (12023): Found entity 1: pokey File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 14
Info (12021): Found 2 design units, including 1 entities, in source file phi_mult.vhdl
    Info (12022): Found design unit 1: phi_mult-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/phi_mult.vhdl Line: 21
    Info (12023): Found entity 1: phi_mult File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/phi_mult.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file synchronizer.vhdl
    Info (12022): Found design unit 1: synchronizer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/synchronizer.vhdl Line: 21
    Info (12023): Found entity 1: synchronizer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/synchronizer.vhdl Line: 12
Info (12021): Found 1 design units, including 0 entities, in source file audiotypes.vhdl
    Info (12022): Found design unit 1: AudioTypes File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/audiotypes.vhdl Line: 4
Info (12021): Found 2 design units, including 1 entities, in source file mixer.vhdl
    Info (12022): Found design unit 1: mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 52
    Info (12023): Found entity 1: mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file clockgen.vhd
    Info (12022): Found design unit 1: clockgen-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/clockgen.vhd Line: 35
    Info (12023): Found entity 1: clockgen File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/clockgen.vhd Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file spdif_transmitter.vhdl
    Info (12022): Found design unit 1: spdif_transmitter-behavioral File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/spdif_transmitter.vhdl Line: 16
    Info (12023): Found entity 1: spdif_transmitter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/spdif_transmitter.vhdl Line: 7
Info (12021): Found 2 design units, including 1 entities, in source file ps2_keyboard.vhdl
    Info (12022): Found design unit 1: ps2_keyboard-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/ps2_keyboard.vhdl Line: 35
    Info (12023): Found entity 1: ps2_keyboard File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/ps2_keyboard.vhdl Line: 20
Info (12021): Found 2 design units, including 1 entities, in source file ps2_to_atari800.vhdl
    Info (12022): Found design unit 1: ps2_to_atari800-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/ps2_to_atari800.vhdl Line: 51
    Info (12023): Found entity 1: ps2_to_atari800 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/ps2_to_atari800.vhdl Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file pokeymax.vhd
    Info (12022): Found design unit 1: pokeymax-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 111
    Info (12023): Found entity 1: pokeymax File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file PSG/envelope.vhdl
    Info (12022): Found design unit 1: PSG_envelope-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/envelope.vhdl Line: 28
    Info (12023): Found entity 1: PSG_envelope File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/envelope.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file PSG/noise.vhdl
    Info (12022): Found design unit 1: PSG_noise-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/noise.vhdl Line: 24
    Info (12023): Found entity 1: PSG_noise File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/noise.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file PSG/top.vhdl
    Info (12022): Found design unit 1: PSG_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/top.vhdl Line: 49
    Info (12023): Found entity 1: PSG_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/top.vhdl Line: 18
Info (12021): Found 2 design units, including 1 entities, in source file PSG/freqdiv.vhdl
    Info (12022): Found design unit 1: PSG_freqdiv-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/freqdiv.vhdl Line: 31
    Info (12023): Found entity 1: PSG_freqdiv File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/freqdiv.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file PSG/mixer.vhdl
    Info (12022): Found design unit 1: PSG_mixer-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/mixer.vhdl Line: 29
    Info (12023): Found entity 1: PSG_mixer File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/mixer.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file PSG/volume.vhdl
    Info (12022): Found design unit 1: PSG_volume-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/volume.vhdl Line: 28
    Info (12023): Found entity 1: PSG_volume File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/volume.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file PSG/volume_profile.vhdl
    Info (12022): Found design unit 1: PSG_volume_profile-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/volume_profile.vhdl Line: 41
    Info (12023): Found entity 1: PSG_volume_profile File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/PSG/volume_profile.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file SID/top.vhdl
    Info (12022): Found design unit 1: SID_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/top.vhdl Line: 64
    Info (12023): Found entity 1: SID_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/top.vhdl Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file SID/oscillator.vhdl
    Info (12022): Found design unit 1: SID_oscillator-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/oscillator.vhdl Line: 31
    Info (12023): Found entity 1: SID_oscillator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/oscillator.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file SID/wavegen.vhdl
    Info (12022): Found design unit 1: SID_wavegen-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/wavegen.vhdl Line: 43
    Info (12023): Found entity 1: SID_wavegen File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/wavegen.vhdl Line: 16
Info (12021): Found 2 design units, including 1 entities, in source file SID/envelope.vhdl
    Info (12022): Found design unit 1: SID_envelope-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/envelope.vhdl Line: 36
    Info (12023): Found entity 1: SID_envelope File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/envelope.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file SID/envelope_tapmatch.vhdl
    Info (12022): Found design unit 1: SID_envelope_tapmatch-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/envelope_tapmatch.vhdl Line: 31
    Info (12023): Found entity 1: SID_envelope_tapmatch File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/envelope_tapmatch.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file SID/amplitudeModulator.vhdl
    Info (12022): Found design unit 1: SID_amplitudeModulator-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/amplitudeModulator.vhdl Line: 26
    Info (12023): Found entity 1: SID_amplitudeModulator File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/amplitudeModulator.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file SID/preFilterSum.vhdl
    Info (12022): Found design unit 1: SID_preFilterSum-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/preFilterSum.vhdl Line: 33
    Info (12023): Found entity 1: SID_preFilterSum File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/preFilterSum.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file SID/filter.vhdl
    Info (12022): Found design unit 1: SID_filter-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/filter.vhdl Line: 147
    Info (12023): Found entity 1: SID_filter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/filter.vhdl Line: 48
Info (12021): Found 2 design units, including 1 entities, in source file SID/f_distortion.vhdl
    Info (12022): Found design unit 1: SID_f_distortion-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/f_distortion.vhdl Line: 24
    Info (12023): Found entity 1: SID_f_distortion File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/f_distortion.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file SID/f_distortion_mux.vhdl
    Info (12022): Found design unit 1: SID_f_distortion_mux-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/f_distortion_mux.vhdl Line: 33
    Info (12023): Found entity 1: SID_f_distortion_mux File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/f_distortion_mux.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file SID/postFilterSum.vhdl
    Info (12022): Found design unit 1: SID_postFilterSum-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/postFilterSum.vhdl Line: 30
    Info (12023): Found entity 1: SID_postFilterSum File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/SID/postFilterSum.vhdl Line: 12
Info (12021): Found 2 design units, including 1 entities, in source file sample/channel.vhdl
    Info (12022): Found design unit 1: sample_channel-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/channel.vhdl Line: 33
    Info (12023): Found entity 1: sample_channel File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/channel.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file sample/adpcm.vhdl
    Info (12022): Found design unit 1: sample_adpcm-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/adpcm.vhdl Line: 39
    Info (12023): Found entity 1: sample_adpcm File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/adpcm.vhdl Line: 13
Info (12021): Found 2 design units, including 1 entities, in source file sample/top.vhdl
    Info (12022): Found design unit 1: sample_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/top.vhdl Line: 46
    Info (12023): Found entity 1: sample_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/sample/top.vhdl Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file covox/top.vhdl
    Info (12022): Found design unit 1: covox_top-vhdl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/covox/top.vhdl Line: 33
    Info (12023): Found entity 1: covox_top File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/covox/top.vhdl Line: 17
Info (12021): Found 2 design units, including 1 entities, in source file int_osc/synthesis/int_osc.vhd
    Info (12022): Found design unit 1: int_osc-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/int_osc/synthesis/int_osc.vhd Line: 16
    Info (12023): Found entity 1: int_osc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/int_osc/synthesis/int_osc.vhd Line: 9
Info (12021): Found 1 design units, including 1 entities, in source file int_osc/synthesis/submodules/altera_int_osc.v
    Info (12023): Found entity 1: altera_int_osc File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/int_osc/synthesis/submodules/altera_int_osc.v Line: 38
Info (12021): Found 2 design units, including 1 entities, in source file pll.vhd
    Info (12022): Found design unit 1: pll-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pll.vhd Line: 55
    Info (12023): Found entity 1: pll File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pll.vhd Line: 43
Info (12021): Found 2 design units, including 1 entities, in source file flash/synthesis/flash.vhd
    Info (12022): Found design unit 1: flash-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/flash.vhd Line: 29
    Info (12023): Found entity 1: flash File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/flash.vhd Line: 9
Info (12021): Found 7 design units, including 7 entities, in source file flash/synthesis/submodules/altera_onchip_flash_util.v
    Info (12023): Found entity 1: altera_onchip_flash_address_range_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 38
    Info (12023): Found entity 2: altera_onchip_flash_address_write_protection_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 55
    Info (12023): Found entity 3: altera_onchip_flash_s_address_write_protection_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 109
    Info (12023): Found entity 4: altera_onchip_flash_a_address_write_protection_check File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 147
    Info (12023): Found entity 5: altera_onchip_flash_convert_address File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 197
    Info (12023): Found entity 6: altera_onchip_flash_convert_sector File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 219
    Info (12023): Found entity 7: altera_onchip_flash_counter File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_util.v Line: 244
Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/altera_onchip_flash.v
    Info (12023): Found entity 1: altera_onchip_flash File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash.v Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v
    Info (12023): Found entity 1: altera_onchip_flash_avmm_data_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v
    Info (12023): Found entity 1: altera_onchip_flash_avmm_csr_controller File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_csr_controller.v Line: 38
Info (12021): Found 1 design units, including 1 entities, in source file flash/synthesis/submodules/rtl/altera_onchip_flash_block.v
    Info (12023): Found entity 1: altera_onchip_flash_block File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/rtl/altera_onchip_flash_block.v Line: 38
Info (12021): Found 2 design units, including 1 entities, in source file lvds_tx.vhd
    Info (12022): Found design unit 1: lvds_tx-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_tx.vhd Line: 18
    Info (12023): Found entity 1: lvds_tx File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_tx.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file lvds_tx/altera_soft_lvds_tx_twD5CSXW.v
    Info (12023): Found entity 1: altera_soft_lvds_tx_twD5CSXW File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_tx/altera_soft_lvds_tx_twD5CSXW.v Line: 29
Info (12021): Found 2 design units, including 1 entities, in source file lvds_rx.vhd
    Info (12022): Found design unit 1: lvds_rx-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_rx.vhd Line: 19
    Info (12023): Found entity 1: lvds_rx File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_rx.vhd Line: 11
Info (12021): Found 1 design units, including 1 entities, in source file lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v
    Info (12023): Found entity 1: altera_soft_lvds_rx_twD2Tqf3 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_rx/altera_soft_lvds_rx_twD2Tqf3.v Line: 29
Info (12021): Found 2 design units, including 1 entities, in source file paddle_gpio.vhd
    Info (12022): Found design unit 1: paddle_gpio-rtl File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio.vhd Line: 21
    Info (12023): Found entity 1: paddle_gpio File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio.vhd Line: 11
Info (12021): Found 2 design units, including 2 entities, in source file paddle_gpio/altera_gpio_lite.sv
    Info (12023): Found entity 1: altgpio_one_bit File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 16
    Info (12023): Found entity 2: altera_gpio_lite File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 940
Info (12127): Elaborating entity "pokeymax" for the top level hierarchy
Warning (10445): VHDL Subtype or Type Declaration warning at pokeymax.vhd(101): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 101
Warning (10445): VHDL Subtype or Type Declaration warning at pokeymax.vhd(836): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 836
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(173): object "ENABLE_DOUBLE_CYCLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 173
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(178): object "SID_WRITE_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 178
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(179): object "SID_READ_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 179
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(181): object "PSG_WRITE_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 181
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(183): object "SAMPLE_WRITE_ENABLE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 183
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(221): object "SIO_RXD_SYNC" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 221
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(235): object "AUDIO_1_UNSIGNED" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 235
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(248): object "KEYBOARD_SCAN_UPDATE" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 248
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(249): used implicit default value for signal "KEYBOARD_SCAN_ENABLE" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 249
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(258): used implicit default value for signal "SID_FLASH1_ADDR" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 258
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(259): used implicit default value for signal "SID_FLASH1_ROMREQUEST" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 259
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(260): object "SID_FLASH1_ROMREADY" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 260
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(261): used implicit default value for signal "SID_FLASH2_ADDR" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 261
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(262): used implicit default value for signal "SID_FLASH2_ROMREQUEST" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 262
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(263): object "SID_FLASH2_ROMREADY" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 263
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(296): used implicit default value for signal "PSG_PROFILE_ADDR" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 296
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(297): used implicit default value for signal "PSG_PROFILE_REQUEST" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 297
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(298): object "PSG_PROFILE_READY" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 298
Warning (10541): VHDL Signal Declaration warning at pokeymax.vhd(371): used implicit default value for signal "ADPCM_STEP_ADDR" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations. File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 371
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(373): object "ADPCM_STEP_READY" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 373
Warning (10036): Verilog HDL or VHDL warning at pokeymax.vhd(433): object "CLK6144" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 433
Warning (10445): VHDL Subtype or Type Declaration warning at pokeymax.vhd(530): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 530
Warning (10296): VHDL warning at pokeymax.vhd(530): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 530
Warning (10445): VHDL Subtype or Type Declaration warning at pokeymax.vhd(533): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 533
Warning (10296): VHDL warning at pokeymax.vhd(533): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 533
Critical Warning (10920): VHDL Incomplete Partial Association warning at pokeymax.vhd(507): port or argument "flash_req_complete_slow" has 1/8 unassociated elements File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 507
Warning (10873): Using initial value X (don't care) for net "POTRESET_N" at pokeymax.vhd(102) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 102
Warning (10873): Using initial value X (don't care) for net "IOX_RST" at pokeymax.vhd(104) File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 104
Info (12128): Elaborating entity "int_osc" for hierarchy "int_osc:oscillator" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 476
Info (12128): Elaborating entity "altera_int_osc" for hierarchy "int_osc:oscillator|altera_int_osc:int_osc_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/int_osc/synthesis/int_osc.vhd Line: 31
Info (12128): Elaborating entity "flash_controller" for hierarchy "flash_controller:\flash_on:flash_controller_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 507
Info (12128): Elaborating entity "flash" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash_controller.vhd Line: 140
Warning (10296): VHDL warning at flash.vhd(102): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/flash.vhd Line: 102
Warning (10296): VHDL warning at flash.vhd(103): ignored assignment of value to null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/flash.vhd Line: 103
Info (12128): Elaborating entity "altera_onchip_flash" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/flash.vhd Line: 100
Info (12128): Elaborating entity "altera_onchip_flash_avmm_csr_controller" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_csr_controller:avmm_csr_controller" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash.v Line: 203
Info (12128): Elaborating entity "altera_onchip_flash_avmm_data_controller" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash.v Line: 282
Warning (10036): Verilog HDL or VHDL warning at altera_onchip_flash_avmm_data_controller.v(220): object "read_count" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 220
Info (12128): Elaborating entity "altera_std_synchronizer" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 572
Info (12130): Elaborated megafunction instantiation "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 572
Info (12133): Instantiated megafunction "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_std_synchronizer:stdsync_busy" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 572
    Info (12134): Parameter "depth" = "2"
Info (12128): Elaborating entity "lpm_shiftreg" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1175
Info (12130): Elaborated megafunction instantiation "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1175
Info (12133): Instantiated megafunction "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|lpm_shiftreg:ufm_data_shiftreg" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1175
    Info (12134): Parameter "lpm_type" = "LPM_SHIFTREG"
    Info (12134): Parameter "lpm_width" = "32"
    Info (12134): Parameter "lpm_direction" = "LEFT"
Info (12128): Elaborating entity "altera_onchip_flash_address_range_check" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_address_range_check:address_range_checker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1185
Info (12128): Elaborating entity "altera_onchip_flash_convert_address" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_address:address_convertor" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1196
Info (12128): Elaborating entity "altera_onchip_flash_a_address_write_protection_check" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_a_address_write_protection_check:access_address_write_protection_checker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1238
Info (12128): Elaborating entity "altera_onchip_flash_s_address_write_protection_check" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_s_address_write_protection_check:sector_address_write_protection_checker" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1248
Info (12128): Elaborating entity "altera_onchip_flash_convert_sector" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_avmm_data_controller:avmm_data_controller|altera_onchip_flash_convert_sector:sector_convertor" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash_avmm_data_controller.v Line: 1259
Info (12128): Elaborating entity "altera_onchip_flash_block" for hierarchy "flash_controller:\flash_on:flash_controller_inst|flash:flash1|altera_onchip_flash:onchip_flash_0|altera_onchip_flash_block:altera_onchip_flash_block" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/flash/synthesis/submodules/altera_onchip_flash.v Line: 327
Info (12128): Elaborating entity "synchronizer" for hierarchy "synchronizer:synchronizer_gtia_audio" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 605
Warning (12125): Using design file pllv3.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info (12022): Found design unit 1: pllv3-SYN File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pllv3.vhd Line: 56
    Info (12023): Found entity 1: pllv3 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pllv3.vhd Line: 43
Info (12128): Elaborating entity "pllv3" for hierarchy "pllv3:\pll_v3_inst:pll_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 625
Info (12128): Elaborating entity "altpll" for hierarchy "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pllv3.vhd Line: 163
Info (12130): Elaborated megafunction instantiation "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pllv3.vhd Line: 163
Info (12133): Instantiated megafunction "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component" with the following parameter: File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pllv3.vhd Line: 163
    Info (12134): Parameter "bandwidth_type" = "AUTO"
    Info (12134): Parameter "clk0_divide_by" = "6"
    Info (12134): Parameter "clk0_duty_cycle" = "50"
    Info (12134): Parameter "clk0_multiply_by" = "7"
    Info (12134): Parameter "clk0_phase_shift" = "0"
    Info (12134): Parameter "clk1_divide_by" = "3"
    Info (12134): Parameter "clk1_duty_cycle" = "50"
    Info (12134): Parameter "clk1_multiply_by" = "7"
    Info (12134): Parameter "clk1_phase_shift" = "0"
    Info (12134): Parameter "clk2_divide_by" = "1"
    Info (12134): Parameter "clk2_duty_cycle" = "50"
    Info (12134): Parameter "clk2_multiply_by" = "2"
    Info (12134): Parameter "clk2_phase_shift" = "0"
    Info (12134): Parameter "clk3_divide_by" = "8"
    Info (12134): Parameter "clk3_duty_cycle" = "50"
    Info (12134): Parameter "clk3_multiply_by" = "1"
    Info (12134): Parameter "clk3_phase_shift" = "0"
    Info (12134): Parameter "compensate_clock" = "CLK0"
    Info (12134): Parameter "inclk0_input_frequency" = "20345"
    Info (12134): Parameter "intended_device_family" = "MAX 10"
    Info (12134): Parameter "lpm_hint" = "CBX_MODULE_PREFIX=pllv3"
    Info (12134): Parameter "lpm_type" = "altpll"
    Info (12134): Parameter "operation_mode" = "NORMAL"
    Info (12134): Parameter "pll_type" = "AUTO"
    Info (12134): Parameter "port_activeclock" = "PORT_UNUSED"
    Info (12134): Parameter "port_areset" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkbad1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkloss" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkswitch" = "PORT_UNUSED"
    Info (12134): Parameter "port_configupdate" = "PORT_UNUSED"
    Info (12134): Parameter "port_fbin" = "PORT_UNUSED"
    Info (12134): Parameter "port_inclk0" = "PORT_USED"
    Info (12134): Parameter "port_inclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_locked" = "PORT_USED"
    Info (12134): Parameter "port_pfdena" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasecounterselect" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasedone" = "PORT_UNUSED"
    Info (12134): Parameter "port_phasestep" = "PORT_UNUSED"
    Info (12134): Parameter "port_phaseupdown" = "PORT_UNUSED"
    Info (12134): Parameter "port_pllena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanaclr" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclk" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanclkena" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandata" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandataout" = "PORT_UNUSED"
    Info (12134): Parameter "port_scandone" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanread" = "PORT_UNUSED"
    Info (12134): Parameter "port_scanwrite" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk0" = "PORT_USED"
    Info (12134): Parameter "port_clk1" = "PORT_USED"
    Info (12134): Parameter "port_clk2" = "PORT_USED"
    Info (12134): Parameter "port_clk3" = "PORT_USED"
    Info (12134): Parameter "port_clk4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clk5" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena0" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena1" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena2" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena3" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena4" = "PORT_UNUSED"
    Info (12134): Parameter "port_clkena5" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk0" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk1" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk2" = "PORT_UNUSED"
    Info (12134): Parameter "port_extclk3" = "PORT_UNUSED"
    Info (12134): Parameter "self_reset_on_loss_lock" = "ON"
    Info (12134): Parameter "width_clock" = "5"
Info (12021): Found 1 design units, including 1 entities, in source file db/pllv3_altpll.v
    Info (12023): Found entity 1: pllv3_altpll File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/pllv3_altpll.v Line: 30
Info (12128): Elaborating entity "pllv3_altpll" for hierarchy "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated" File: /home/markw/intelFPGA_lite/20.1/quartus/libraries/megafunctions/altpll.tdf Line: 898
Info (12128): Elaborating entity "slave_timing_6502" for hierarchy "slave_timing_6502:bus_adapt" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 643
Info (12128): Elaborating entity "stereo_detect" for hierarchy "stereo_detect:\auto_stereo:a4" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 679
Info (12128): Elaborating entity "pokey_mixer_mux" for hierarchy "pokey_mixer_mux:pokey_mixer_both" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 756
Info (12128): Elaborating entity "pokey" for hierarchy "pokey:pokey1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 789
Info (12128): Elaborating entity "complete_address_decoder" for hierarchy "pokey:pokey1|complete_address_decoder:decode_addr1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 621
Info (12128): Elaborating entity "wide_delay_line" for hierarchy "pokey:pokey1|wide_delay_line:audf0_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 657
Warning (10445): VHDL Subtype or Type Declaration warning at wide_delay_line.vhdl(47): subtype or type has null range File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/wide_delay_line.vhdl Line: 47
Info (12128): Elaborating entity "pokey_countdown_timer" for hierarchy "pokey:pokey1|pokey_countdown_timer:timer0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 674
Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey_countdown_timer.vhdl Line: 62
Info (12128): Elaborating entity "latch_delay_line" for hierarchy "pokey:pokey1|latch_delay_line:twotone_del" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 701
Info (12128): Elaborating entity "latch_delay_line" for hierarchy "pokey:pokey1|latch_delay_line:stimer_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 919
Info (12128): Elaborating entity "pokey_noise_filter" for hierarchy "pokey:pokey1|pokey_noise_filter:pokey_noise_filter0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 926
Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "pokey:pokey1|syncreset_enable_divider:enable_64_div" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 986
Info (12128): Elaborating entity "syncreset_enable_divider" for hierarchy "pokey:pokey1|syncreset_enable_divider:enable_15_div" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 990
Info (12128): Elaborating entity "pokey_poly_17_9" for hierarchy "pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 996
Info (12128): Elaborating entity "pokey_poly_5" for hierarchy "pokey:pokey1|pokey_poly_5:poly_5_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 999
Info (12128): Elaborating entity "pokey_poly_4" for hierarchy "pokey:pokey1|pokey_poly_4:poly_4_lfsr" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 1002
Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:pokey1|delay_line:serout_clock_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 1048
Info (12128): Elaborating entity "delay_line" for hierarchy "pokey:pokey1|delay_line:serin_clock_delay" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 1052
Info (12128): Elaborating entity "pokey_keyboard_scanner" for hierarchy "pokey:pokey1|pokey_keyboard_scanner:\gen_normal_scan:pokey_keyboard_scanner1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokey/pokey.vhdl Line: 1288
Info (12128): Elaborating entity "mixer" for hierarchy "mixer:mixer1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 1725
Warning (10492): VHDL Process Statement warning at mixer.vhdl(193): signal "ADC_EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 193
Warning (10492): VHDL Process Statement warning at mixer.vhdl(194): signal "ADC_EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 194
Warning (10492): VHDL Process Statement warning at mixer.vhdl(195): signal "ADC_EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 195
Warning (10492): VHDL Process Statement warning at mixer.vhdl(196): signal "ADC_EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 196
Warning (10492): VHDL Process Statement warning at mixer.vhdl(235): signal "ADC_EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 235
Warning (10492): VHDL Process Statement warning at mixer.vhdl(236): signal "ADC_EN" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 236
Warning (10492): VHDL Process Statement warning at mixer.vhdl(327): signal "CHB" is read inside the Process Statement but isn't in the Process Statement's sensitivity list File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/mixer.vhdl Line: 327
Info (12128): Elaborating entity "filtered_sigmadelta" for hierarchy "filtered_sigmadelta:dac_0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 1760
Info (12128): Elaborating entity "sigmadelta_2ndorder" for hierarchy "filtered_sigmadelta:dac_0|sigmadelta_2ndorder:\gen_2ndorder_on:dac_2nd" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/filtered_sigmadelta.vhd Line: 79
Info (12128): Elaborating entity "lvds_tx" for hierarchy "lvds_tx:\adc_on:lvds_tx0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 1976
Info (12128): Elaborating entity "altera_soft_lvds_tx_twD5CSXW" for hierarchy "lvds_tx:\adc_on:lvds_tx0|altera_soft_lvds_tx_twD5CSXW:lvds_tx_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_tx.vhd Line: 28
Info (12128): Elaborating entity "lvds_rx" for hierarchy "lvds_rx:\adc_on:lvds_rx0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 1982
Info (12128): Elaborating entity "altera_soft_lvds_rx_twD2Tqf3" for hierarchy "lvds_rx:\adc_on:lvds_rx0|altera_soft_lvds_rx_twD2Tqf3:lvds_rx_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/lvds_rx.vhd Line: 30
Info (12128): Elaborating entity "simple_low_pass_filter" for hierarchy "simple_low_pass_filter:\adc_on:adcfilter" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 1990
Info (12128): Elaborating entity "paddle_gpio" for hierarchy "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 2030
Info (12128): Elaborating entity "altera_gpio_lite" for hierarchy "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio.vhd Line: 78
Info (12128): Elaborating entity "altgpio_one_bit" for hierarchy "paddle_gpio:\paddle_lvds_on:paddle_lvds_rx0|altera_gpio_lite:paddle_gpio_inst|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 1115
Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object "nsleep_in" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 82
Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(110): object "outclocken_wire" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 110
Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object "oe_outclocken_wire" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 334
Warning (10036): Verilog HDL or VHDL warning at altera_gpio_lite.sv(540): object "inclocken_wire" assigned a value but never read File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/paddle_gpio/altera_gpio_lite.sv Line: 540
Info (19000): Inferred 1 megafunctions from design logic
    Info (276034): Inferred altshift_taps megafunction from the following design logic: "toggle_reg_rtl_0"
        Info (286033): Parameter NUMBER_OF_TAPS set to 1
        Info (286033): Parameter TAP_DISTANCE set to 255
        Info (286033): Parameter WIDTH set to 1
Info (12130): Elaborated megafunction instantiation "altshift_taps:toggle_reg_rtl_0"
Info (12133): Instantiated megafunction "altshift_taps:toggle_reg_rtl_0" with the following parameter:
    Info (12134): Parameter "NUMBER_OF_TAPS" = "1"
    Info (12134): Parameter "TAP_DISTANCE" = "255"
    Info (12134): Parameter "WIDTH" = "1"
Info (12021): Found 1 design units, including 1 entities, in source file db/shift_taps_n0m.tdf
    Info (12023): Found entity 1: shift_taps_n0m File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/shift_taps_n0m.tdf Line: 29
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_4ga1.tdf
    Info (12023): Found entity 1: altsyncram_4ga1 File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/altsyncram_4ga1.tdf Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_97f.tdf
    Info (12023): Found entity 1: cntr_97f File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/cntr_97f.tdf Line: 28
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_krb.tdf
    Info (12023): Found entity 1: cmpr_krb File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/cmpr_krb.tdf Line: 23
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_vmg.tdf
    Info (12023): Found entity 1: cntr_vmg File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/cntr_vmg.tdf Line: 26
Warning (13039): The following bidirectional pins have no drivers
    Warning (13040): bidirectional pin "IOX_SDA" has no driver File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 106
    Warning (13040): bidirectional pin "IOX_SCL" has no driver File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 107
Info (13000): Registers with preset signals will power-up high File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 1342
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Warning (13024): Output pins are stuck at VCC or GND
    Warning (13410): Pin "AUD[2]" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 85
    Warning (13410): Pin "POTRESET_N" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 102
    Warning (13410): Pin "IOX_RST" is stuck at GND File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 104
Info (286030): Timing-Driven Synthesis is running
Info (17049): 12 registers lost all their fanouts during netlist optimizations.
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
    Info (16011): Adding 1 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 0 LCELL
Warning (15899): PLL "pllv3:\pll_v3_inst:pll_inst|altpll:altpll_component|pllv3_altpll:auto_generated|pll1" has parameters clk3_multiply_by and clk3_divide_by specified but port CLK[3] is not connected File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/db/pllv3_altpll.v Line: 46
Warning (21074): Design contains 3 input pin(s) that do not drive logic
    Warning (15610): No output dependent on input pin "CLK_SLOW" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 69
    Warning (15610): No output dependent on input pin "CLK1" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 72
    Warning (15610): No output dependent on input pin "IOX_INT" File: /home/markw/fpga/svn/repo/trunk/atari_800xl/atari_chips/pokeyv2/build_10M16_monov4/pokeymax.vhd Line: 105
Info (21057): Implemented 2652 device resources after synthesis - the final resource count might be different
    Info (21058): Implemented 16 input pins
    Info (21059): Implemented 16 output pins
    Info (21060): Implemented 38 bidirectional pins
    Info (21061): Implemented 2570 logic cells
    Info (21064): Implemented 1 RAM segments
    Info (21065): Implemented 1 PLLs
    Info (21070): Implemented 1 User Flash Memory blocks
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 59 warnings
    Info: Peak virtual memory: 474 megabytes
    Info: Processing ended: Sat May 11 10:22:53 2024
    Info: Elapsed time: 00:00:08
    Info: Total CPU time (on all processors): 00:00:15


