Timing Analyzer report for pokeymax
Mon Mar 27 20:49:04 2023
Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Slow 1200mV 85C Model Setup Summary
  8. Slow 1200mV 85C Model Hold Summary
  9. Slow 1200mV 85C Model Recovery Summary
 10. Slow 1200mV 85C Model Removal Summary
 11. Slow 1200mV 85C Model Minimum Pulse Width Summary
 12. Slow 1200mV 85C Model Metastability Summary
 13. Slow 1200mV 0C Model Fmax Summary
 14. Slow 1200mV 0C Model Setup Summary
 15. Slow 1200mV 0C Model Hold Summary
 16. Slow 1200mV 0C Model Recovery Summary
 17. Slow 1200mV 0C Model Removal Summary
 18. Slow 1200mV 0C Model Minimum Pulse Width Summary
 19. Slow 1200mV 0C Model Metastability Summary
 20. Fast 1200mV 0C Model Setup Summary
 21. Fast 1200mV 0C Model Hold Summary
 22. Fast 1200mV 0C Model Recovery Summary
 23. Fast 1200mV 0C Model Removal Summary
 24. Fast 1200mV 0C Model Minimum Pulse Width Summary
 25. Fast 1200mV 0C Model Metastability Summary
 26. Multicorner Timing Analysis Summary
 27. Board Trace Model Assignments
 28. Input Transition Times
 29. Signal Integrity Metrics (Slow 1200mv 0c Model)
 30. Signal Integrity Metrics (Slow 1200mv 85c Model)
 31. Signal Integrity Metrics (Fast 1200mv 0c Model)
 32. Setup Transfers
 33. Hold Transfers
 34. Report TCCS
 35. Report RSKM
 36. Unconstrained Paths Summary
 37. Clock Status Summary
 38. Unconstrained Input Ports
 39. Unconstrained Output Ports
 40. Unconstrained Input Ports
 41. Unconstrained Output Ports
 42. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 2020  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.



+-----------------------------------------------------------------------------+
; Timing Analyzer Summary                                                     ;
+-----------------------+-----------------------------------------------------+
; Quartus Prime Version ; Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition ;
; Timing Analyzer       ; Legacy Timing Analyzer                              ;
; Revision Name         ; pokeymax                                            ;
; Device Family         ; MAX 10                                              ;
; Device Name           ; 10M02SCU169C8G                                      ;
; Timing Models         ; Final                                               ;
; Delay Model           ; Combined                                            ;
; Rise/Fall Delays      ; Enabled                                             ;
+-----------------------+-----------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 12          ;
; Maximum allowed            ; 6           ;
;                            ;             ;
; Average used               ; 1.36        ;
; Maximum used               ; 6           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;   7.8%      ;
;     Processors 3-6         ;   7.1%      ;
+----------------------------+-------------+


+-------------------------------------------------------------------------------------+
; SDC File List                                                                       ;
+-------------------------------------------------+--------+--------------------------+
; SDC File Path                                   ; Status ; Read at                  ;
+-------------------------------------------------+--------+--------------------------+
; pokeymax.sdc                                    ; OK     ; Mon Mar 27 20:49:00 2023 ;
; int_osc/synthesis/submodules/altera_int_osc.sdc ; OK     ; Mon Mar 27 20:49:00 2023 ;
+-------------------------------------------------+--------+--------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                      ;
+-------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+---------------------------------------------------------------------+-----------------------------------------------------------------------+
; Clock Name                                                        ; Type      ; Period  ; Frequency  ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master   ; Source                                                              ; Targets                                                               ;
+-------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+---------------------------------------------------------------------+-----------------------------------------------------------------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 17.170  ; 58.24 MHz  ; 0.000 ; 8.585   ; 50.00      ; 3         ; 2           ;       ;        ;           ;            ; false    ; CLK_SLOW ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|inclk[0] ; { \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] } ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 8.585   ; 116.48 MHz ; 0.000 ; 4.292   ; 50.00      ; 3         ; 4           ;       ;        ;           ;            ; false    ; CLK_SLOW ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|inclk[0] ; { \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] } ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 9.365   ; 106.77 MHz ; 0.000 ; 4.682   ; 50.00      ; 9         ; 11          ;       ;        ;           ;            ; false    ; CLK_SLOW ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|inclk[0] ; { \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] } ;
; CLK_SLOW                                                          ; Base      ; 11.446  ; 87.36 MHz  ; 0.000 ; 5.723   ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                                     ; { CLK_SLOW }                                                          ;
; int_osc_clk                                                       ; Base      ; 8.620   ; 116.01 MHz ; 0.000 ; 4.310   ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                                     ; { oscillator|int_osc_0|oscillator_dut|clkout }                        ;
; PHI2                                                              ; Base      ; 526.315 ; 1.9 MHz    ; 0.000 ; 263.157 ;            ;           ;             ;       ;        ;           ;            ;          ;          ;                                                                     ; { PHI2 }                                                              ;
+-------------------------------------------------------------------+-----------+---------+------------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+----------+---------------------------------------------------------------------+-----------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                      ;
+------------+-----------------+-------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                        ; Note ;
+------------+-----------------+-------------------------------------------------------------------+------+
; 74.48 MHz  ; 74.48 MHz       ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 131.86 MHz ; 131.86 MHz      ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ;      ;
; 133.71 MHz ; 133.71 MHz      ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ;      ;
+------------+-----------------+-------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                        ;
+-------------------------------------------------------------------+--------+---------------+
; Clock                                                             ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------+--------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.997 ; -4.613        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 1.781  ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 3.743  ; 0.000         ;
+-------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                        ;
+-------------------------------------------------------------------+-------+---------------+
; Clock                                                             ; Slack ; End Point TNS ;
+-------------------------------------------------------------------+-------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.363 ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.475 ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.713 ; 0.000         ;
+-------------------------------------------------------------------+-------+---------------+


------------------------------------------
; Slow 1200mV 85C Model Recovery Summary ;
------------------------------------------
No paths to report.


-----------------------------------------
; Slow 1200mV 85C Model Removal Summary ;
-----------------------------------------
No paths to report.


+---------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                           ;
+-------------------------------------------------------------------+---------+---------------+
; Clock                                                             ; Slack   ; End Point TNS ;
+-------------------------------------------------------------------+---------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 4.040   ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 4.423   ; 0.000         ;
; CLK_SLOW                                                          ; 5.617   ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 8.315   ; 0.000         ;
; PHI2                                                              ; 262.848 ; 0.000         ;
+-------------------------------------------------------------------+---------+---------------+


-----------------------------------------------
; Slow 1200mV 85C Model Metastability Summary ;
-----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 103
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 15.826 ns




+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                       ;
+------------+-----------------+-------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                        ; Note ;
+------------+-----------------+-------------------------------------------------------------------+------+
; 78.15 MHz  ; 78.15 MHz       ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ;      ;
; 139.74 MHz ; 139.74 MHz      ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ;      ;
; 140.55 MHz ; 140.55 MHz      ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ;      ;
+------------+-----------------+-------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                         ;
+-------------------------------------------------------------------+--------+---------------+
; Clock                                                             ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------+--------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.228 ; -0.425        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 2.209  ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 4.374  ; 0.000         ;
+-------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                         ;
+-------------------------------------------------------------------+-------+---------------+
; Clock                                                             ; Slack ; End Point TNS ;
+-------------------------------------------------------------------+-------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.324 ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.449 ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.670 ; 0.000         ;
+-------------------------------------------------------------------+-------+---------------+


-----------------------------------------
; Slow 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Slow 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+---------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                            ;
+-------------------------------------------------------------------+---------+---------------+
; Clock                                                             ; Slack   ; End Point TNS ;
+-------------------------------------------------------------------+---------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 4.040   ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 4.426   ; 0.000         ;
; CLK_SLOW                                                          ; 5.636   ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 8.300   ; 0.000         ;
; PHI2                                                              ; 262.780 ; 0.000         ;
+-------------------------------------------------------------------+---------+---------------+


----------------------------------------------
; Slow 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 103
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 15.905 ns




+--------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                         ;
+-------------------------------------------------------------------+--------+---------------+
; Clock                                                             ; Slack  ; End Point TNS ;
+-------------------------------------------------------------------+--------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 5.092  ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 6.492  ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 11.921 ; 0.000         ;
+-------------------------------------------------------------------+--------+---------------+


+-------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                         ;
+-------------------------------------------------------------------+-------+---------------+
; Clock                                                             ; Slack ; End Point TNS ;
+-------------------------------------------------------------------+-------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.152 ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.170 ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 0.243 ; 0.000         ;
+-------------------------------------------------------------------+-------+---------------+


-----------------------------------------
; Fast 1200mV 0C Model Recovery Summary ;
-----------------------------------------
No paths to report.


----------------------------------------
; Fast 1200mV 0C Model Removal Summary ;
----------------------------------------
No paths to report.


+---------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                            ;
+-------------------------------------------------------------------+---------+---------------+
; Clock                                                             ; Slack   ; End Point TNS ;
+-------------------------------------------------------------------+---------+---------------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 4.068   ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 4.459   ; 0.000         ;
; CLK_SLOW                                                          ; 5.255   ; 0.000         ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 8.346   ; 0.000         ;
; PHI2                                                              ; 262.369 ; 0.000         ;
+-------------------------------------------------------------------+---------+---------------+


----------------------------------------------
; Fast 1200mV 0C Model Metastability Summary ;
----------------------------------------------
The design MTBF is not calculated because there are no specified synchronizers in the design.
Number of Synchronizer Chains Found: 103
Shortest Synchronizer Chain: 2 Registers
Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
Worst Case Available Settling Time: 16.603 ns




+--------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                            ;
+--------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Clock                                                              ; Setup  ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+--------------------------------------------------------------------+--------+-------+----------+---------+---------------------+
; Worst-case Slack                                                   ; -0.997 ; 0.152 ; N/A      ; N/A     ; 4.040               ;
;  CLK_SLOW                                                          ; N/A    ; N/A   ; N/A      ; N/A     ; 5.255               ;
;  PHI2                                                              ; N/A    ; N/A   ; N/A      ; N/A     ; 262.369             ;
;  \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 3.743  ; 0.152 ; N/A      ; N/A     ; 8.300               ;
;  \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -0.997 ; 0.243 ; N/A      ; N/A     ; 4.040               ;
;  \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 1.781  ; 0.170 ; N/A      ; N/A     ; 4.423               ;
; Design-wide TNS                                                    ; -4.613 ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  CLK_SLOW                                                          ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  PHI2                                                              ; N/A    ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; -4.613 ; 0.000 ; N/A      ; N/A     ; 0.000               ;
;  \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 0.000  ; 0.000 ; N/A      ; N/A     ; 0.000               ;
+--------------------------------------------------------------------+--------+-------+----------+---------+---------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                            ;
+--------------+-----------------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin          ; I/O Standard          ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+--------------+-----------------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; CLK_OUT      ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SOD          ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ACLK         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUD[1]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUD[2]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUD[3]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUD[4]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; POTRESET_N   ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; IOX_RST      ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[0]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[1]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[2]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[3]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[4]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[5]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[6]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; D[7]         ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; IRQ          ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; BCLK         ; 3.3 V Schmitt Trigger ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; EXT[1]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; EXT[2]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; EXT[3]       ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; IOX_SDA      ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; IOX_SCL      ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; ~ALTERA_TDO~ ; 3.3-V LVTTL           ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+--------------+-----------------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+--------------------------------------------------------------------------------+
; Input Transition Times                                                         ;
+--------------------+-----------------------+-----------------+-----------------+
; Pin                ; I/O Standard          ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------------+-----------------------+-----------------+-----------------+
; CLK0               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; CLK1               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[0]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[1]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[2]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[3]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[4]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[5]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[6]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; D[7]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; IRQ                ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; BCLK               ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; EXT[1]             ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; EXT[2]             ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; EXT[3]             ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; IOX_SDA            ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; IOX_SCL            ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; W_N                ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PHI2               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; A[3]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; A[2]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; A[1]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; A[0]               ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; CLK_SLOW           ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; CS1                ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; CS0_N              ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; IOX_INT            ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[0]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[6]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[5]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[4]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[7]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[2]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[1]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; PADDLE[3]          ; 3.3-V LVTTL           ; 2640 ps         ; 2640 ps         ;
; SID                ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_TMS~       ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_TCK~       ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_TDI~       ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_nCONFIG~   ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_nSTATUS~   ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
; ~ALTERA_CONF_DONE~ ; 3.3 V Schmitt Trigger ; 2640 ps         ; 2640 ps         ;
+--------------------+-----------------------+-----------------+-----------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard          ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; CLK_OUT      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 4.02e-08 V                   ; 3.12 V              ; -0.042 V            ; 0.21 V                               ; 0.194 V                              ; 8.53e-10 s                  ; 1.01e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 4.02e-08 V                  ; 3.12 V             ; -0.042 V           ; 0.21 V                              ; 0.194 V                             ; 8.53e-10 s                 ; 1.01e-09 s                 ; No                        ; No                        ;
; SOD          ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; ACLK         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; AUD[1]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; AUD[2]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; AUD[3]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; AUD[4]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; POTRESET_N   ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; IOX_RST      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.09 V              ; -0.0047 V           ; 0.291 V                              ; 0.288 V                              ; 4.58e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.09 V             ; -0.0047 V          ; 0.291 V                             ; 0.288 V                             ; 4.58e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; D[0]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[1]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[2]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[3]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[4]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[5]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[6]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; D[7]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; IRQ          ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; BCLK         ; 3.3 V Schmitt Trigger ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.09 V              ; -0.0047 V           ; 0.291 V                              ; 0.288 V                              ; 4.58e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.09 V             ; -0.0047 V          ; 0.291 V                             ; 0.288 V                             ; 4.58e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; EXT[1]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.128 V            ; 0.216 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.128 V           ; 0.216 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; EXT[2]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; EXT[3]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.09 V              ; -0.00467 V          ; 0.291 V                              ; 0.287 V                              ; 4.58e-09 s                  ; 4.89e-09 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.09 V             ; -0.00467 V         ; 0.291 V                             ; 0.287 V                             ; 4.58e-09 s                 ; 4.89e-09 s                 ; No                        ; No                        ;
; IOX_SDA      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
; IOX_SCL      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.07e-08 V                   ; 3.18 V              ; -0.115 V            ; 0.266 V                              ; 0.229 V                              ; 4.69e-10 s                  ; 6.38e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.07e-08 V                  ; 3.18 V             ; -0.115 V           ; 0.266 V                             ; 0.229 V                             ; 4.69e-10 s                 ; 6.38e-10 s                 ; No                        ; No                        ;
; ~ALTERA_TDO~ ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.08e-08 V                   ; 3.19 V              ; -0.126 V            ; 0.218 V                              ; 0.383 V                              ; 4.51e-10 s                  ; 4.73e-10 s                  ; No                         ; No                         ; 3.08 V                      ; 2.08e-08 V                  ; 3.19 V             ; -0.126 V           ; 0.218 V                             ; 0.383 V                             ; 4.51e-10 s                 ; 4.73e-10 s                 ; No                        ; No                        ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Slow 1200mv 85c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                   ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard          ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; CLK_OUT      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 2.5e-06 V                    ; 3.1 V               ; -0.0179 V           ; 0.19 V                               ; 0.192 V                              ; 1.04e-09 s                  ; 1.19e-09 s                  ; Yes                        ; No                         ; 3.08 V                      ; 2.5e-06 V                   ; 3.1 V              ; -0.0179 V          ; 0.19 V                              ; 0.192 V                             ; 1.04e-09 s                 ; 1.19e-09 s                 ; Yes                       ; No                        ;
; SOD          ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; ACLK         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; AUD[1]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; AUD[2]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; AUD[3]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; AUD[4]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; POTRESET_N   ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; IOX_RST      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.09 V              ; -0.00259 V          ; 0.276 V                              ; 0.25 V                               ; 5.46e-09 s                  ; 6.08e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.3e-06 V                   ; 3.09 V             ; -0.00259 V         ; 0.276 V                             ; 0.25 V                              ; 5.46e-09 s                 ; 6.08e-09 s                 ; No                        ; Yes                       ;
; D[0]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[1]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[2]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[3]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[4]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[5]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[6]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; D[7]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; IRQ          ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; BCLK         ; 3.3 V Schmitt Trigger ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.09 V              ; -0.00259 V          ; 0.276 V                              ; 0.25 V                               ; 5.46e-09 s                  ; 6.08e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.3e-06 V                   ; 3.09 V             ; -0.00259 V         ; 0.276 V                             ; 0.25 V                              ; 5.46e-09 s                 ; 6.08e-09 s                 ; No                        ; Yes                       ;
; EXT[1]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0684 V           ; 0.28 V                               ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0684 V          ; 0.28 V                              ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; EXT[2]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; EXT[3]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.09 V              ; -0.00259 V          ; 0.276 V                              ; 0.25 V                               ; 5.45e-09 s                  ; 6.08e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 1.3e-06 V                   ; 3.09 V             ; -0.00259 V         ; 0.276 V                             ; 0.25 V                              ; 5.45e-09 s                 ; 6.08e-09 s                 ; No                        ; Yes                       ;
; IOX_SDA      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
; IOX_SCL      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0624 V           ; 0.177 V                              ; 0.312 V                              ; 6.42e-10 s                  ; 6.7e-10 s                   ; No                         ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0624 V          ; 0.177 V                             ; 0.312 V                             ; 6.42e-10 s                 ; 6.7e-10 s                  ; No                        ; No                        ;
; ~ALTERA_TDO~ ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.3e-06 V                    ; 3.15 V              ; -0.0682 V           ; 0.279 V                              ; 0.237 V                              ; 4.81e-10 s                  ; 6.4e-10 s                   ; Yes                        ; No                         ; 3.08 V                      ; 1.3e-06 V                   ; 3.15 V             ; -0.0682 V          ; 0.279 V                             ; 0.237 V                             ; 4.81e-10 s                 ; 6.4e-10 s                  ; Yes                       ; No                        ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Signal Integrity Metrics (Fast 1200mv 0c Model)                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                    ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin          ; I/O Standard          ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; CLK_OUT      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 9.71e-07 V                   ; 3.53 V              ; -0.0288 V           ; 0.252 V                              ; 0.333 V                              ; 6.56e-10 s                  ; 7.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 9.71e-07 V                  ; 3.53 V             ; -0.0288 V          ; 0.252 V                             ; 0.333 V                             ; 6.56e-10 s                 ; 7.2e-10 s                  ; No                        ; Yes                       ;
; SOD          ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; ACLK         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; AUD[1]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; AUD[2]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; AUD[3]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; AUD[4]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; POTRESET_N   ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; IOX_RST      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.48 V              ; -0.00709 V          ; 0.333 V                              ; 0.272 V                              ; 3.62e-09 s                  ; 4.03e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.48 V             ; -0.00709 V         ; 0.333 V                             ; 0.272 V                             ; 3.62e-09 s                 ; 4.03e-09 s                 ; No                        ; Yes                       ;
; D[0]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[1]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[2]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[3]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[4]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[5]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[6]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; D[7]         ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; IRQ          ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; BCLK         ; 3.3 V Schmitt Trigger ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.48 V              ; -0.00709 V          ; 0.333 V                              ; 0.272 V                              ; 3.62e-09 s                  ; 4.03e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.48 V             ; -0.00709 V         ; 0.333 V                             ; 0.272 V                             ; 3.62e-09 s                 ; 4.03e-09 s                 ; No                        ; Yes                       ;
; EXT[1]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.65 V              ; -0.0209 V           ; 0.391 V                              ; 0.09 V                               ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.65 V             ; -0.0209 V          ; 0.391 V                             ; 0.09 V                              ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; EXT[2]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; EXT[3]       ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.48 V              ; -0.00727 V          ; 0.334 V                              ; 0.33 V                               ; 3.62e-09 s                  ; 4.03e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.48 V             ; -0.00727 V         ; 0.334 V                             ; 0.33 V                              ; 3.62e-09 s                 ; 4.03e-09 s                 ; No                        ; Yes                       ;
; IOX_SDA      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
; IOX_SCL      ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.63 V              ; -0.0257 V           ; 0.468 V                              ; 0.138 V                              ; 3.02e-10 s                  ; 4.44e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.63 V             ; -0.0257 V          ; 0.468 V                             ; 0.138 V                             ; 3.02e-10 s                 ; 4.44e-10 s                 ; No                        ; Yes                       ;
; ~ALTERA_TDO~ ; 3.3-V LVTTL           ; 0 s                 ; 0 s                 ; 3.46 V                       ; 5.04e-07 V                   ; 3.64 V              ; -0.0201 V           ; 0.391 V                              ; 0.088 V                              ; 2.79e-10 s                  ; 3.95e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 5.04e-07 V                  ; 3.64 V             ; -0.0201 V          ; 0.391 V                             ; 0.088 V                             ; 2.79e-10 s                 ; 3.95e-10 s                 ; No                        ; Yes                       ;
+--------------+-----------------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                       ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+------------+----------+----------+
; From Clock                                                        ; To Clock                                                          ; RR Paths   ; FR Paths   ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+------------+----------+----------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 112723     ; 0          ; 0        ; 0        ;
; PHI2                                                              ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 122476     ; 0          ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 10406      ; 0          ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; false path ; 0          ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 10406      ; 0          ; 0        ; 0        ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                        ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+------------+----------+----------+
; From Clock                                                        ; To Clock                                                          ; RR Paths   ; FR Paths   ; RF Paths ; FF Paths ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+------------+----------+----------+
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; 112723     ; 0          ; 0        ; 0        ;
; PHI2                                                              ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; false path ; false path ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 122476     ; 0          ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; 10406      ; 0          ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; false path ; 0          ; 0        ; 0        ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; 10406      ; 0          ; 0        ; 0        ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+------------+------------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No non-DPA dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths Summary                    ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 31    ; 31   ;
; Unconstrained Input Port Paths  ; 99    ; 99   ;
; Unconstrained Output Ports      ; 20    ; 20   ;
; Unconstrained Output Port Paths ; 40    ; 40   ;
+---------------------------------+-------+------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Status Summary                                                                                                                                            ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+-----------+-------------+
; Target                                                            ; Clock                                                             ; Type      ; Status      ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+-----------+-------------+
; CLK_SLOW                                                          ; CLK_SLOW                                                          ; Base      ; Constrained ;
; PHI2                                                              ; PHI2                                                              ; Base      ; Constrained ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] ; Generated ; Constrained ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] ; Generated ; Constrained ;
; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] ; Generated ; Constrained ;
; oscillator|int_osc_0|oscillator_dut|clkout                        ; int_osc_clk                                                       ; Base      ; Constrained ;
+-------------------------------------------------------------------+-------------------------------------------------------------------+-----------+-------------+


+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                         ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment                                                                              ;
+------------+--------------------------------------------------------------------------------------+
; A[0]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[1]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[2]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[3]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; BCLK       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CS0_N      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CS1        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[0]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[1]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[2]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[3]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[4]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[5]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[6]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[7]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; EXT[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; EXT[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; EXT[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_INT    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SCL    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SDA    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[0]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[1]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[2]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[3]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[4]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[5]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[6]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[7]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SID        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; W_N        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                          ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment                                                                               ;
+-------------+---------------------------------------------------------------------------------------+
; ACLK        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; BCLK        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CLK_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[0]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[1]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[2]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[3]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[4]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[5]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[6]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[7]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SCL     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SDA     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IRQ         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; POTRESET_N  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SOD         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------+
; Unconstrained Input Ports                                                                         ;
+------------+--------------------------------------------------------------------------------------+
; Input Port ; Comment                                                                              ;
+------------+--------------------------------------------------------------------------------------+
; A[0]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[1]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[2]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; A[3]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; BCLK       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CS0_N      ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CS1        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[0]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[1]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[2]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[3]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[4]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[5]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[6]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[7]       ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; EXT[1]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; EXT[2]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; EXT[3]     ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_INT    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SCL    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SDA    ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[0]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[1]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[2]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[3]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[4]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[5]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[6]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; PADDLE[7]  ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SID        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
; W_N        ; No input delay, min/max delays, false-path exceptions, or max skew assignments found ;
+------------+--------------------------------------------------------------------------------------+


+-----------------------------------------------------------------------------------------------------+
; Unconstrained Output Ports                                                                          ;
+-------------+---------------------------------------------------------------------------------------+
; Output Port ; Comment                                                                               ;
+-------------+---------------------------------------------------------------------------------------+
; ACLK        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[1]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[2]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[3]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; AUD[4]      ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; BCLK        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; CLK_OUT     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[0]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[1]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[2]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[3]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[4]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[5]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[6]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; D[7]        ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SCL     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IOX_SDA     ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; IRQ         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; POTRESET_N  ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
; SOD         ; No output delay, min/max delays, false-path exceptions, or max skew assignments found ;
+-------------+---------------------------------------------------------------------------------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus Prime Timing Analyzer
    Info: Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
    Info: Processing started: Mon Mar 27 20:49:00 2023
Info: Command: quartus_sta pokeymax -c pokeymax
Info: qsta_default_script.tcl version: #1
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (20030): Parallel compilation is enabled and will use 6 of the 6 processors detected
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'pokeymax.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 3 -multiply_by 2 -duty_cycle 50.00 -name {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0]} {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 3 -multiply_by 4 -duty_cycle 50.00 -name {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1]} {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 9 -multiply_by 11 -duty_cycle 50.00 -name {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2]} {\pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332104): Reading SDC File: 'int_osc/synthesis/submodules/altera_int_osc.sdc'
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info: Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info: Can't run Report Timing Closure Recommendations. The current device family is not supported.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -0.997
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.997              -4.613 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     1.781               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     3.743               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.363
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.363               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.475               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.713               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 4.040
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     4.040               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.423               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     5.617               0.000 CLK_SLOW 
    Info (332119):     8.315               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):   262.848               0.000 PHI2 
Info (332114): Report Metastability: Found 103 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 103
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 15.826 ns
    Info (332114): 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Critical Warning (332148): Timing requirements not met
Info (332146): Worst-case setup slack is -0.228
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):    -0.228              -0.425 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     2.209               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     4.374               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.324
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.324               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.449               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.670               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 4.040
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     4.040               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.426               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     5.636               0.000 CLK_SLOW 
    Info (332119):     8.300               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):   262.780               0.000 PHI2 
Info (332114): Report Metastability: Found 103 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 103
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 15.905 ns
    Info (332114): 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in the Timing Analyzer to see clock uncertainties.
Info (332146): Worst-case setup slack is 5.092
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     5.092               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     6.492               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):    11.921               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case hold slack is 0.152
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     0.152               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.170               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     0.243               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
Info (332140): No Recovery paths to report
Info (332140): No Removal paths to report
Info (332146): Worst-case minimum pulse width slack is 4.068
    Info (332119):     Slack       End Point TNS Clock 
    Info (332119): ========= =================== =====================
    Info (332119):     4.068               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     4.459               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[2] 
    Info (332119):     5.255               0.000 CLK_SLOW 
    Info (332119):     8.346               0.000 \pll_v2_inst:pll_inst|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):   262.369               0.000 PHI2 
Info (332114): Report Metastability: Found 103 synchronizer chains.
    Info (332114): The design MTBF is not calculated because there are no specified synchronizers in the design.
    Info (332114): Number of Synchronizer Chains Found: 103
    Info (332114): Shortest Synchronizer Chain: 2 Registers
    Info (332114): Fraction of Chains for which MTBFs Could Not be Calculated: 1.000
    Info (332114): Worst Case Available Settling Time: 16.603 ns
    Info (332114): 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus Prime Timing Analyzer was successful. 0 errors, 4 warnings
    Info: Peak virtual memory: 514 megabytes
    Info: Processing ended: Mon Mar 27 20:49:04 2023
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:06


