diff -urN qemu_clean/qemu-6.0.0/default-configs/devices/m68k-softmmu.mak qemu-6.0.0/default-configs/devices/m68k-softmmu.mak --- qemu_clean/qemu-6.0.0/default-configs/devices/m68k-softmmu.mak 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/default-configs/devices/m68k-softmmu.mak 2021-05-21 18:22:04.875771857 +0200 @@ -9,3 +9,4 @@ CONFIG_NEXTCUBE=y CONFIG_Q800=y CONFIG_M68K_VIRT=y +CONFIG_MISTER=y diff -urN qemu_clean/qemu-6.0.0/hw/m68k/Kconfig qemu-6.0.0/hw/m68k/Kconfig --- qemu_clean/qemu-6.0.0/hw/m68k/Kconfig 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/hw/m68k/Kconfig 2021-05-21 18:22:04.876771861 +0200 @@ -32,3 +32,6 @@ select GOLDFISH_TTY select GOLDFISH_RTC select VIRTIO_MMIO + +config MISTER + bool diff -urN qemu_clean/qemu-6.0.0/hw/m68k/meson.build qemu-6.0.0/hw/m68k/meson.build --- qemu_clean/qemu-6.0.0/hw/m68k/meson.build 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/hw/m68k/meson.build 2021-05-21 18:22:04.877771864 +0200 @@ -4,5 +4,6 @@ m68k_ss.add(when: 'CONFIG_NEXTCUBE', if_true: files('next-kbd.c', 'next-cube.c')) m68k_ss.add(when: 'CONFIG_Q800', if_true: files('q800.c')) m68k_ss.add(when: 'CONFIG_M68K_VIRT', if_true: files('virt.c')) +m68k_ss.add(when: 'CONFIG_MISTER', if_true: files('mister_minimig.c')) hw_arch += {'m68k': m68k_ss} diff -urN qemu_clean/qemu-6.0.0/hw/m68k/mister_minimig.c qemu-6.0.0/hw/m68k/mister_minimig.c --- qemu_clean/qemu-6.0.0/hw/m68k/mister_minimig.c 1970-01-01 01:00:00.000000000 +0100 +++ qemu-6.0.0/hw/m68k/mister_minimig.c 2021-05-21 18:28:58.639954453 +0200 @@ -0,0 +1,175 @@ +/* + * MiSTer Minimig system emulation. + * + * Copyright (c) 2021 Mark Watson + * + * This code is licensed under the GPL + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/m68k/mcf.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "sysemu/reset.h" +#include "hw/loader.h" +#include "elf.h" +#include "exec/address-spaces.h" +#include "qemu/error-report.h" +#include "sysemu/qtest.h" + +#include + +unsigned char volatile * chip_addr; +void * z3fastram_addr_shared; + + // qemu_mutex_lock_iothread(); + // mpc8xxx_gpio_set_irq(arg,mg->pin,mg->state); + // qemu_mutex_unlock_iothread(); + // see: + // ../svn/Linux-Kernel_MiSTer/drivers/video/fbdev/MiSTer_fb.c + // also: + //../svn/Minimig-AGA_MiSTer/sys/sys_top.v + // wire [63:0] f2h_irq = {video_sync,HDMI_TX_VS}; + // cyclonev_hps_interface_interrupts interrupts + // ( + // .irq(f2h_irq) + // ); + // if (ioctl(fb, FBIO_WAITFORVSYNC, &zero) == -1) + + +static void mister_irq_func(void *opaque, int n, int level) +{ + M68kCPU *cpu = opaque; + + // fprintf(stderr,"IRQ:%d\n",level); + + int irqlevel = 7&(level); + static int last = -1; + if (last!=irqlevel) + { + last = irqlevel; + m68k_set_irq_level(cpu, irqlevel, 24+irqlevel); + } +} + +static void mister_irq_init(M68kCPU *cpu) +{ + qemu_irq *mister_irq = qemu_allocate_irqs(mister_irq_func, cpu, 1); + SysBusDevice *s; + + DeviceState *dev; + dev = qdev_new("mister.interruptpoll"); + + s = SYS_BUS_DEVICE(dev); + sysbus_realize_and_unref(s, &error_fatal); + sysbus_connect_irq(s, 0, mister_irq[0]); + sysbus_mmio_map(s, 0, 0xdff01c); + sysbus_mmio_map(s, 1, 0xdff09a); + sysbus_mmio_map(s, 2, 0xbfd000); + + // 1c, 1e, 9a, 9c +} + +static void main_cpu_reset(void *opaque) +{ + M68kCPU *cpu = opaque; + CPUState *cs = CPU(cpu); + + cpu_reset(cs); + cpu->env.aregs[7] = ldl_phys(cs->as, 0); + cpu->env.pc = ldl_phys(cs->as, 4); +} + +static void mister_minimig_init(MachineState *machine) +{ + M68kCPU *cpu; + CPUM68KState *env; + + ram_addr_t ram_size = machine->ram_size; + fprintf(stderr,"qemu ram size:%d KB\n",ram_size); + + //hwaddr entry; + MemoryRegion *address_space_mem = get_system_memory(); + MemoryRegion *chipram = g_new(MemoryRegion, 1); + MemoryRegion *z2fastram = g_new(MemoryRegion, 1); + MemoryRegion *z3fastram = g_new(MemoryRegion, 1); + MemoryRegion *rtgcard = g_new(MemoryRegion, 1); + MemoryRegion *hardware = g_new(MemoryRegion, 1); + MemoryRegion *rom = g_new(MemoryRegion, 1); + + cpu = M68K_CPU(cpu_create(machine->cpu_type)); + qemu_register_reset(main_cpu_reset, cpu); + env = &cpu->env; + + unsigned int hpsbridgeaddr = 0xc0000000; + int fduncached = open("/dev/mem",(O_RDWR|O_SYNC)); + int fdcached = open("/sys/kernel/debug/minimig_irq/mmap_cached",(O_RDWR)); + + int chipram_bytes = 2*1024*1024; + void * chipram_addr = mmap(NULL,chipram_bytes,(PROT_READ|PROT_WRITE),MAP_SHARED,fduncached,hpsbridgeaddr+0); //cached? + chip_addr = chipram_addr; + + // int z2fastram_bytes = 8*1024*1024; +// unsigned int z2fast_physical = 0x38000000; // physical ddr address, shared with f2h bridge + // void * z2fastram_addr = mmap(NULL,z2fastram_bytes,(PROT_READ|PROT_WRITE),MAP_SHARED,fdcached,z2fast_physical); + + int z3fastram_bytes = 384*1024*1024; + //int z3fastram_bytes = 8*1024*1024; + unsigned int z3fast_physical = 0x28000000; // physical ddr address, shared with f2h bridge + void * z3fastram_addr = mmap(NULL,z3fastram_bytes,(PROT_READ|PROT_WRITE),MAP_SHARED,fdcached,z3fast_physical); +// void * z3fastram_addr = malloc(z3fastram_bytes); +// int locked = mlock(z3fastram_addr,z3fastram_bytes); +// fprintf(stderr,"Locked:%d\n",locked); +// z3fastram_addr_shared = z3fastram_addr; + + + int rtgcard_bytes = 16*1024*1024; + //int z3fastram_bytes = 8*1024*1024; + unsigned int rtg_physical = 0x27000000; // physical ddr address, shared with f2h bridge + void * rtgcard_addr = mmap(NULL,rtgcard_bytes,(PROT_READ|PROT_WRITE),MAP_SHARED,fdcached,rtg_physical); + + int hardware_bytes = 13*1024*1024; + void * hardware_addr = mmap(NULL,hardware_bytes,(PROT_READ|PROT_WRITE),MAP_SHARED,fduncached,hpsbridgeaddr + 0x200000); + + int rom_bytes = 1*1024*1024; + void * rom_addr_orig = mmap(NULL,rom_bytes,(PROT_READ|PROT_WRITE),MAP_SHARED,fdcached,hpsbridgeaddr+0xf00000); +/* void * rom_addr_fast = malloc(rom_bytes); + for (int i=0;i!=rom_bytes;i+=4) + { + *((unsigned int *)(rom_addr_fast+i)) = *((unsigned int *)(rom_addr_orig+i)); + }*/ + + memory_region_init_ram_ptr(chipram, NULL, "mister_minimig.chipram", chipram_bytes, chipram_addr); + // memory_region_init_ram_ptr(z2fastram, NULL, "mister_minimig.z2fastram", z2fastram_bytes, z2fastram_addr ); + memory_region_init_ram_ptr(z3fastram, NULL, "mister_minimig.z3fastram", z3fastram_bytes, z3fastram_addr ); + memory_region_init_ram_ptr(rtgcard, NULL, "mister_minimig.rtg", rtgcard_bytes, rtgcard_addr ); + + memory_region_init_ram_ptr(hardware, NULL, "mister_minimig.hardware", hardware_bytes, hardware_addr); + memory_region_init_ram_ptr(rom, NULL, "mister_minimig.rom", rom_bytes, rom_addr_orig); + rom->readonly = true; + + memory_region_add_subregion(address_space_mem, 0, chipram); + // memory_region_add_subregion(address_space_mem, 0x200000, z2fastram); + memory_region_add_subregion(address_space_mem, 0x2000000, rtgcard); + memory_region_add_subregion(address_space_mem, 0x40000000, z3fastram); + //memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); + memory_region_add_subregion(address_space_mem, 0x200000, hardware); + memory_region_add_subregion(address_space_mem, 0xf00000, rom); + + mister_irq_init(cpu); +} + +static void mister_minimig_machine_init(MachineClass *mc) +{ + mc->desc = "MiSTer minimig"; + mc->init = mister_minimig_init; + mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); + //mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68020"); + mc->default_ram_id = "mister_minimig.ram"; + mc->ignore_memory_transaction_failures = true; +} + +DEFINE_MACHINE("mister_minimig", mister_minimig_machine_init) + diff -urN qemu_clean/qemu-6.0.0/hw/timer/meson.build qemu-6.0.0/hw/timer/meson.build --- qemu_clean/qemu-6.0.0/hw/timer/meson.build 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/hw/timer/meson.build 2021-05-21 18:22:04.878771867 +0200 @@ -36,5 +36,6 @@ softmmu_ss.add(when: 'CONFIG_SSE_TIMER', if_true: files('sse-timer.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_TIMER', if_true: files('stm32f2xx_timer.c')) softmmu_ss.add(when: 'CONFIG_XILINX', if_true: files('xilinx_timer.c')) +softmmu_ss.add(when: 'CONFIG_MISTER', if_true: files('mister_interruptpoll.c')) specific_ss.add(when: 'CONFIG_AVR_TIMER16', if_true: files('avr_timer16.c')) diff -urN qemu_clean/qemu-6.0.0/hw/timer/mister_interruptpoll.c qemu-6.0.0/hw/timer/mister_interruptpoll.c --- qemu_clean/qemu-6.0.0/hw/timer/mister_interruptpoll.c 1970-01-01 01:00:00.000000000 +0100 +++ qemu-6.0.0/hw/timer/mister_interruptpoll.c 2021-05-21 18:23:51.296115633 +0200 @@ -0,0 +1,407 @@ +/* + * QEMU model of the Mister IRQ polling + * + * Copyright (c) 2021 Mark Watson + * + * GPL + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/ptimer.h" +#include "hw/qdev-properties.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qom/object.h" +#include "qemu/main-loop.h" +#include "qemu/qemu-print.h" +#include +#include "myioctl.h" +//#include "exec/exec-all.h" +void tb_invalidate_phys_range(unsigned long start, unsigned long end); + +#define D(x) + +extern void volatile * chip_addr; + +struct mister_timer +{ + ptimer_state *ptimer; + void *parent; + int nr; /* for debug. */ + + unsigned long timer_div; +}; + +struct timerblock +{ + SysBusDevice parent_obj; + + qemu_irq irq; + struct mister_timer *timers; + MemoryRegion hardware1; + MemoryRegion hardware2; + MemoryRegion hardware3; + unsigned char volatile * irqs; + + volatile void * hardware_addr1; + volatile void * hardware_addr2; + volatile void * hardware_addr3; +}; + +static int timer_update_irq(struct timerblock *t) +{ + int current = *t->irqs; + // fprintf(stderr,"I"); +// +// /* All timers within the same slave share a single IRQ line. */ +// static int last = -1; +// if (last!=current) +// { +// last = current; +if (current==15) +{ + // FILE *logfile = qemu_log_lock(); + // qemu_fprintf(logfile,"IRQ on write:%d:%ld\n",current,clock()); + // qemu_log_unlock(logfile); + qemu_set_irq(t->irq, 7&(~current)); +} +// return 1; +// } + return 0; +} + +static void * mythreadfunc(void * opaque) +{ + struct timerblock *t = opaque; + static int last = -1; + + static int first = 1; + if (first) + { + first =0; + fprintf(stderr,"ioctl thread:%d\n",gettid()); + } + + int fd = open ("/sys/kernel/debug/minimig_irq/ioctl_dev",O_RDONLY); + while (true) + { + int res = ioctl(fd, MINIMIG_IOC_WAIT_IRQ, 1); + if (res<0) + perror("arg:"); + + qemu_mutex_lock_iothread(); + int current = *t->irqs; + //fprintf(stderr,"i"); + // FILE *logfile = qemu_log_lock(); + // qemu_fprintf(logfile,"IRQ on ioctl:%d:%ld\n",current,clock()); + // qemu_log_unlock(logfile); + qemu_set_irq(t->irq, 7&(~current)); + qemu_mutex_unlock_iothread(); + + //fprintf(stderr,"IRQ:%d:%d:%d\n", current,fd,res); + } + return 0; +} + + +static uint64_t +hardware_read1(void *opaque, hwaddr addr, unsigned int size) +{ + struct timerblock *t = opaque; + + uint64_t res; + void volatile * hardware_addr = t->hardware_addr1+addr; + switch (size) + { + case 1: + res = *((unsigned char volatile *)(hardware_addr)); + break; + case 2: + res = *((unsigned short volatile *)(hardware_addr)); + break; + case 4: + res = *((unsigned int volatile *)(hardware_addr)); + break; + default: + exit(-1); + } + return res; +} + +static uint64_t +hardware_read2(void *opaque, hwaddr addr, unsigned int size) +{ + struct timerblock *t = opaque; + + uint64_t res; + void volatile * hardware_addr = t->hardware_addr2+addr; + switch (size) + { + case 1: + res = *((unsigned char volatile *)(hardware_addr)); + break; + case 2: + res = *((unsigned short volatile *)(hardware_addr)); + break; + case 4: + res = *((unsigned int volatile *)(hardware_addr)); + break; + default: + exit(-1); + } + return res; +} + +static uint64_t +hardware_read3(void *opaque, hwaddr addr, unsigned int size) +{ + struct timerblock *t = opaque; + + uint64_t res; + void volatile * hardware_addr = t->hardware_addr3+addr; + switch (size) + { + case 1: + res = *((unsigned char volatile *)(hardware_addr)); + break; + case 2: + res = *((unsigned short volatile *)(hardware_addr)); + break; + case 4: + res = *((unsigned int volatile *)(hardware_addr)); + break; + default: + exit(-1); + } + // fprintf(stderr,"CIAR:%04x=%04x(%d)\n",(unsigned int)addr,(unsigned int)res,size); + return res; +} + +static void +hardware_write1(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + struct timerblock *t = opaque; + + void volatile * hardware_addr = t->hardware_addr1+addr; + switch (size) + { + case 1: + *((unsigned char volatile *)(hardware_addr)) = val64; + break; + case 2: + *((unsigned short volatile *)(hardware_addr)) = val64; + break; + case 4: + *((unsigned int volatile *)(hardware_addr)) = val64; + break; + default: + exit(-1); + } + + timer_update_irq(t); +} + +static void +hardware_write2(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + struct timerblock *t = opaque; + + void volatile * hardware_addr = t->hardware_addr2+addr; + switch (size) + { + case 1: + *((unsigned char volatile *)(hardware_addr)) = val64; + break; + case 2: + *((unsigned short volatile *)(hardware_addr)) = val64; + break; + case 4: + *((unsigned int volatile *)(hardware_addr)) = val64; + break; + default: + exit(-1); + } + + timer_update_irq(t); + + static int first = 1; + if (first) + { + first =0; + fprintf(stderr,"io thread:%d\n",gettid()); + } +} + +static void +hardware_write3(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + struct timerblock *t = opaque; + + static int first = 1; + + void volatile * hardware_addr = t->hardware_addr3+addr; + switch (size) + { + case 1: + *((unsigned char volatile *)(hardware_addr)) = val64; + break; + case 2: + *((unsigned short volatile *)(hardware_addr)) = val64; + break; + case 4: + *((unsigned int volatile *)(hardware_addr)) = val64; + break; + default: + exit(-1); + } + + // fprintf(stderr,"CIAW:%04x=%04x(%d)\n",(unsigned int)addr,(unsigned int)val64,size); + + if (first) + { + first = false; + // fprintf(stderr,"Invalidating!"); + unsigned int hpsbridgeaddr = 0xc0000000; + tb_invalidate_phys_range(hpsbridgeaddr, (hpsbridgeaddr+0x200000)); + } +} + +static const MemoryRegionOps hardware_ops1 = { + .read = hardware_read1, + .write = hardware_write1, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4 + } +}; + +static const MemoryRegionOps hardware_ops2 = { + .read = hardware_read2, + .write = hardware_write2, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4 + } +}; + +static const MemoryRegionOps hardware_ops3 = { + .read = hardware_read3, + .write = hardware_write3, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4 + } +}; + + +#define TYPE_MISTER_IRQPOLL "mister.interruptpoll" +DECLARE_INSTANCE_CHECKER(struct timerblock, MISTER_IRQPOLL, + TYPE_MISTER_IRQPOLL) + +static void timer_hit(void *opaque) +{ + struct mister_timer *xt = opaque; + struct timerblock *t = xt->parent; + D(fprintf(stderr, "%s %d\n", __func__, xt->nr)); + + //ptimer_transaction_begin(xt->ptimer); + // ptimer_set_count(xt->ptimer,1); + //ptimer_transaction_commit(xt->ptimer); + + timer_update_irq(t); +} + +static void mister_interruptpoll_realize(DeviceState *dev, Error **errp) +{ + struct timerblock *t = MISTER_IRQPOLL(dev); + unsigned int i; + + unsigned int irqoffset = 0x1000000; + int fduncached = open("/dev/mem",(O_RDWR|O_SYNC)); + + unsigned int hpsbridgeaddr = 0xc0000000; + void * irqs = mmap(NULL,1,(PROT_READ|PROT_WRITE),MAP_SHARED,fduncached,hpsbridgeaddr+irqoffset); //cached? + + fprintf(stderr,"Init interrupt polling thread (requires kernel module):%p\n",irqs); + + int hardware_bytes = 4; //13*1024*1024; + void volatile * hardware_addr = mmap(NULL,8192,(PROT_READ|PROT_WRITE),MAP_SHARED,fduncached,hpsbridgeaddr + 0xdff000); + t->hardware_addr1 = hardware_addr+0x1c; + t->hardware_addr2 = hardware_addr+0x9a; + + void volatile * cia_addr = mmap(NULL,8192,(PROT_READ|PROT_WRITE),MAP_SHARED,fduncached,hpsbridgeaddr + 0xbfd000); + t->hardware_addr3 = cia_addr; + + //sysbus_mmio_map(s, 0, 0xdff01c); + //sysbus_mmio_map(s, 1, 0xdff09a); + //sysbus_mmio_map(s, 2, 0xbfe000); + + memory_region_init_io(&t->hardware1, OBJECT(t), &hardware_ops1, t, "mister.minimig.hardware1", hardware_bytes); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->hardware1); + memory_region_init_io(&t->hardware2, OBJECT(t), &hardware_ops2, t, "mister.minimig.hardware2", hardware_bytes); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->hardware2); + memory_region_init_io(&t->hardware3, OBJECT(t), &hardware_ops3, t, "mister.minimig.hardware3", hardware_bytes); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &t->hardware3); + + /* Init all the ptimers. */ + t->timers = g_malloc0(sizeof t->timers[0]); + struct mister_timer *xt = &t->timers[0]; + + t->irqs = irqs; + xt->parent = t; + xt->nr = i; + // xt->ptimer = ptimer_init(timer_hit, xt, PTIMER_POLICY_CONTINUOUS_TRIGGER); + + // ptimer_transaction_begin(xt->ptimer); + // ptimer_set_freq(xt->ptimer, t->freq_hz); + // ptimer_set_count(xt->ptimer,1); + // ptimer_run(xt->ptimer, 0); + // ptimer_transaction_commit(xt->ptimer); + + pthread_t * mythread = malloc(sizeof(pthread_t)); + memset(mythread,0,sizeof(pthread_t)); + pthread_create(mythread,NULL,&mythreadfunc,t); +} + +static void mister_interruptpoll_init(Object *obj) +{ + struct timerblock *t = MISTER_IRQPOLL(obj); + + /* All timers share a single irq line. */ + sysbus_init_irq(SYS_BUS_DEVICE(obj), &t->irq); +} + +static Property mister_interruptpoll_properties[] = { + DEFINE_PROP_END_OF_LIST(), +}; + +static void mister_interruptpoll_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = mister_interruptpoll_realize; + device_class_set_props(dc, mister_interruptpoll_properties); +} + +static const TypeInfo mister_interruptpoll_info = { + .name = TYPE_MISTER_IRQPOLL, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(struct timerblock), + .instance_init = mister_interruptpoll_init, + .class_init = mister_interruptpoll_class_init, +}; + +static void mister_interruptpoll_register_types(void) +{ + type_register_static(&mister_interruptpoll_info); +} + +type_init(mister_interruptpoll_register_types) diff -urN qemu_clean/qemu-6.0.0/myioctl.h qemu-6.0.0/myioctl.h --- qemu_clean/qemu-6.0.0/myioctl.h 1970-01-01 01:00:00.000000000 +0100 +++ qemu-6.0.0/myioctl.h 2021-05-21 18:22:04.879771871 +0200 @@ -0,0 +1,6 @@ +#include +#include + +#define MINIMIG_IOCTL_BASE 'M' + +#define MINIMIG_IOC_WAIT_IRQ _IOR(MINIMIG_IOCTL_BASE, 0, int) diff -urN qemu_clean/qemu-6.0.0/target/m68k/helper.c qemu-6.0.0/target/m68k/helper.c --- qemu_clean/qemu-6.0.0/target/m68k/helper.c 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/target/m68k/helper.c 2021-05-21 18:22:04.880771874 +0200 @@ -304,11 +304,13 @@ break; /* Unimplemented Registers */ case M68K_CR_CAAR: - case M68K_CR_PCR: case M68K_CR_BUSCR: cpu_abort(env_cpu(env), "Unimplemented control register write 0x%x = 0x%x\n", reg, val); + + case M68K_CR_PCR: + break; } /* Invalid control registers will generate an exception. */ @@ -409,10 +411,12 @@ break; /* Unimplemented Registers */ case M68K_CR_CAAR: - case M68K_CR_PCR: case M68K_CR_BUSCR: cpu_abort(env_cpu(env), "Unimplemented control register read 0x%x\n", reg); + + case M68K_CR_PCR: + break; } /* Invalid control registers will generate an exception. */ diff -urN qemu_clean/qemu-6.0.0/target/m68k/op_helper.c qemu-6.0.0/target/m68k/op_helper.c --- qemu_clean/qemu-6.0.0/target/m68k/op_helper.c 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/target/m68k/op_helper.c 2021-05-21 18:22:04.882771881 +0200 @@ -21,6 +21,7 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "exec/log.h" #include "semihosting/semihost.h" #if defined(CONFIG_USER_ONLY) @@ -242,6 +243,7 @@ qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n", ++count, m68k_exception_name(cs->exception_index), vector, env->pc, env->aregs[7], sr); + //log_target_disas(cs, env->pc, 64); } fmt |= 0x40000000; @@ -470,6 +472,7 @@ cpu_restore_state(cs, retaddr, true); if (m68k_feature(env, M68K_FEATURE_M68040)) { + fprintf(stderr,"bus error: phys:%p virt:%p\n",(void *)physaddr,(void *)addr); env->mmu.mmusr = 0; /* diff -urN qemu_clean/qemu-6.0.0/target/m68k/translate.c qemu-6.0.0/target/m68k/translate.c --- qemu_clean/qemu-6.0.0/target/m68k/translate.c 2021-04-29 19:18:58.000000000 +0200 +++ qemu-6.0.0/target/m68k/translate.c 2021-05-21 18:22:04.885771891 +0200 @@ -5528,12 +5528,8 @@ gen_exception(s, s->base.pc_next, EXCP_PRIVILEGE); return; } - if (m68k_feature(s->env, M68K_FEATURE_M68040)) { SRC_EA(env, addr, OS_LONG, 0, NULL); /* FIXME: check the state frame */ - } else { - disas_undef(env, s, insn); - } } DISAS_INSN(fsave) @@ -5543,14 +5539,10 @@ return; } - if (m68k_feature(s->env, M68K_FEATURE_M68040)) { /* always write IDLE */ TCGv idle = tcg_const_i32(0x41000000); DEST_EA(env, insn, OS_LONG, idle, NULL); tcg_temp_free(idle); - } else { - disas_undef(env, s, insn); - } } #endif diff -urN qemu_clean/qemu-6.0.0/tmp/qemu_system_test/go qemu-6.0.0/tmp/qemu_system_test/go --- qemu_clean/qemu-6.0.0/tmp/qemu_system_test/go 1970-01-01 01:00:00.000000000 +0100 +++ qemu-6.0.0/tmp/qemu_system_test/go 2021-05-21 18:22:04.886771895 +0200 @@ -0,0 +1 @@ +LD_LIBRARY_PATH=./qemu_system_test/libs/lib/arm-linux-gnueabihf/ ./qemu_system_test/libs/lib/ld-linux-armhf.so.3 ./qemu_system_test/qemu-system-m68k --machine mister_minimig --nographic